1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
814 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
815 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
817 // First set operation action for all vector types to either promote
818 // (for widening) or expand (for scalarization). Then we will selectively
819 // turn on ones that can be effectively codegen'd.
820 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
821 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
822 MVT VT = (MVT::SimpleValueType)i;
823 setOperationAction(ISD::ADD , VT, Expand);
824 setOperationAction(ISD::SUB , VT, Expand);
825 setOperationAction(ISD::FADD, VT, Expand);
826 setOperationAction(ISD::FNEG, VT, Expand);
827 setOperationAction(ISD::FSUB, VT, Expand);
828 setOperationAction(ISD::MUL , VT, Expand);
829 setOperationAction(ISD::FMUL, VT, Expand);
830 setOperationAction(ISD::SDIV, VT, Expand);
831 setOperationAction(ISD::UDIV, VT, Expand);
832 setOperationAction(ISD::FDIV, VT, Expand);
833 setOperationAction(ISD::SREM, VT, Expand);
834 setOperationAction(ISD::UREM, VT, Expand);
835 setOperationAction(ISD::LOAD, VT, Expand);
836 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
837 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
838 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
839 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
840 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
841 setOperationAction(ISD::FABS, VT, Expand);
842 setOperationAction(ISD::FSIN, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FCOS, VT, Expand);
845 setOperationAction(ISD::FSINCOS, VT, Expand);
846 setOperationAction(ISD::FREM, VT, Expand);
847 setOperationAction(ISD::FMA, VT, Expand);
848 setOperationAction(ISD::FPOWI, VT, Expand);
849 setOperationAction(ISD::FSQRT, VT, Expand);
850 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
851 setOperationAction(ISD::FFLOOR, VT, Expand);
852 setOperationAction(ISD::FCEIL, VT, Expand);
853 setOperationAction(ISD::FTRUNC, VT, Expand);
854 setOperationAction(ISD::FRINT, VT, Expand);
855 setOperationAction(ISD::FNEARBYINT, VT, Expand);
856 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHS, VT, Expand);
858 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
859 setOperationAction(ISD::MULHU, VT, Expand);
860 setOperationAction(ISD::SDIVREM, VT, Expand);
861 setOperationAction(ISD::UDIVREM, VT, Expand);
862 setOperationAction(ISD::FPOW, VT, Expand);
863 setOperationAction(ISD::CTPOP, VT, Expand);
864 setOperationAction(ISD::CTTZ, VT, Expand);
865 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::CTLZ, VT, Expand);
867 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
868 setOperationAction(ISD::SHL, VT, Expand);
869 setOperationAction(ISD::SRA, VT, Expand);
870 setOperationAction(ISD::SRL, VT, Expand);
871 setOperationAction(ISD::ROTL, VT, Expand);
872 setOperationAction(ISD::ROTR, VT, Expand);
873 setOperationAction(ISD::BSWAP, VT, Expand);
874 setOperationAction(ISD::SETCC, VT, Expand);
875 setOperationAction(ISD::FLOG, VT, Expand);
876 setOperationAction(ISD::FLOG2, VT, Expand);
877 setOperationAction(ISD::FLOG10, VT, Expand);
878 setOperationAction(ISD::FEXP, VT, Expand);
879 setOperationAction(ISD::FEXP2, VT, Expand);
880 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
881 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
882 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
883 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
885 setOperationAction(ISD::TRUNCATE, VT, Expand);
886 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
887 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
888 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
889 setOperationAction(ISD::VSELECT, VT, Expand);
890 setOperationAction(ISD::SELECT_CC, VT, Expand);
891 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
892 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
893 setTruncStoreAction(VT,
894 (MVT::SimpleValueType)InnerVT, Expand);
895 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
896 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
898 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
899 // we have to deal with them whether we ask for Expansion or not. Setting
900 // Expand causes its own optimisation problems though, so leave them legal.
901 if (VT.getVectorElementType() == MVT::i1)
902 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
905 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
906 // with -msoft-float, disable use of MMX as well.
907 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
908 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
909 // No operations on x86mmx supported, everything uses intrinsics.
912 // MMX-sized vectors (other than x86mmx) are expected to be expanded
913 // into smaller operations.
914 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
915 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
916 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
917 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
918 setOperationAction(ISD::AND, MVT::v8i8, Expand);
919 setOperationAction(ISD::AND, MVT::v4i16, Expand);
920 setOperationAction(ISD::AND, MVT::v2i32, Expand);
921 setOperationAction(ISD::AND, MVT::v1i64, Expand);
922 setOperationAction(ISD::OR, MVT::v8i8, Expand);
923 setOperationAction(ISD::OR, MVT::v4i16, Expand);
924 setOperationAction(ISD::OR, MVT::v2i32, Expand);
925 setOperationAction(ISD::OR, MVT::v1i64, Expand);
926 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
927 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
928 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
929 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
932 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
933 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
935 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
936 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
937 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
938 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
941 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
942 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
944 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
945 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
947 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
948 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
949 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
950 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
951 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
952 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
953 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
954 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
955 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
956 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
957 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
958 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
961 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
962 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
964 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
965 // registers cannot be used even for integer operations.
966 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
967 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
968 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
969 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
971 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
972 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
973 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
974 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
975 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
976 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
977 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
978 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
979 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
980 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
982 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
983 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
984 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
985 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
986 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
987 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
988 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
989 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
990 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
991 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
992 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
994 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
995 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
996 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
997 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
999 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
1000 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1002 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1003 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1005 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1006 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1007 MVT VT = (MVT::SimpleValueType)i;
1008 // Do not attempt to custom lower non-power-of-2 vectors
1009 if (!isPowerOf2_32(VT.getVectorNumElements()))
1011 // Do not attempt to custom lower non-128-bit vectors
1012 if (!VT.is128BitVector())
1014 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1015 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1019 // We support custom legalizing of sext and anyext loads for specific
1020 // memory vector types which we can load as a scalar (or sequence of
1021 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1022 // loads these must work with a single scalar load.
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1024 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1025 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1030 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1031 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1033 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1034 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1035 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1036 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1037 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1038 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1040 if (Subtarget->is64Bit()) {
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1042 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1045 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1046 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1047 MVT VT = (MVT::SimpleValueType)i;
1049 // Do not attempt to promote non-128-bit vectors
1050 if (!VT.is128BitVector())
1053 setOperationAction(ISD::AND, VT, Promote);
1054 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1055 setOperationAction(ISD::OR, VT, Promote);
1056 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1057 setOperationAction(ISD::XOR, VT, Promote);
1058 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1059 setOperationAction(ISD::LOAD, VT, Promote);
1060 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1061 setOperationAction(ISD::SELECT, VT, Promote);
1062 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1065 // Custom lower v2i64 and v2f64 selects.
1066 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1067 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1068 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1069 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1071 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1072 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1074 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1075 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1076 // As there is no 64-bit GPR available, we need build a special custom
1077 // sequence to convert from v2i32 to v2f32.
1078 if (!Subtarget->is64Bit())
1079 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1081 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1082 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1084 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1086 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1087 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1088 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1091 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1092 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1093 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1094 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1095 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1096 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1100 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1103 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1108 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1111 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1112 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1114 // FIXME: Do we need to handle scalar-to-vector here?
1115 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1117 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1120 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1121 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1122 // There is no BLENDI for byte vectors. We don't need to custom lower
1123 // some vselects for now.
1124 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1126 // SSE41 brings specific instructions for doing vector sign extend even in
1127 // cases where we don't have SRA.
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1129 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1130 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1132 // i8 and i16 vectors are custom because the source register and source
1133 // source memory operand types are not the same width. f32 vectors are
1134 // custom since the immediate controlling the insert encodes additional
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1144 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1146 // FIXME: these should be Legal, but that's only for the case where
1147 // the index is constant. For now custom expand to deal with that.
1148 if (Subtarget->is64Bit()) {
1149 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1150 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1154 if (Subtarget->hasSSE2()) {
1155 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1156 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1158 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1159 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1161 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1162 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1164 // In the customized shift lowering, the legal cases in AVX2 will be
1166 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1167 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1169 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1170 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1172 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1175 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1176 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1180 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1181 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1183 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1184 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1185 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1187 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1197 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1200 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1210 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1211 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1213 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1214 // even though v8i16 is a legal type.
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1216 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1217 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1219 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1220 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1221 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1223 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1224 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1226 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1228 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1232 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1234 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1235 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1239 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1240 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1243 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1244 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1248 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1249 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1253 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1255 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1256 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1258 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1259 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1261 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1262 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1264 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1265 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1269 setOperationAction(ISD::FMA, MVT::f32, Legal);
1270 setOperationAction(ISD::FMA, MVT::f64, Legal);
1273 if (Subtarget->hasInt256()) {
1274 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1275 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1276 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1277 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1279 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1280 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1281 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1282 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1284 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1285 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1286 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1287 // Don't lower v32i8 because there is no 128-bit byte mul
1289 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1290 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1291 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1292 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1294 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1295 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1297 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1298 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1299 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1300 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1302 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1303 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1304 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1305 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1307 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1309 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1310 // Don't lower v32i8 because there is no 128-bit byte mul
1313 // In the customized shift lowering, the legal cases in AVX2 will be
1315 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1316 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1318 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1319 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1321 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1323 // Custom lower several nodes for 256-bit types.
1324 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1325 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1326 MVT VT = (MVT::SimpleValueType)i;
1328 // Extract subvector is special because the value type
1329 // (result) is 128-bit but the source is 256-bit wide.
1330 if (VT.is128BitVector())
1331 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1333 // Do not attempt to custom lower other non-256-bit vectors
1334 if (!VT.is256BitVector())
1337 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1338 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1339 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1340 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1341 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1342 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1343 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1346 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1347 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1348 MVT VT = (MVT::SimpleValueType)i;
1350 // Do not attempt to promote non-256-bit vectors
1351 if (!VT.is256BitVector())
1354 setOperationAction(ISD::AND, VT, Promote);
1355 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1356 setOperationAction(ISD::OR, VT, Promote);
1357 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1358 setOperationAction(ISD::XOR, VT, Promote);
1359 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1360 setOperationAction(ISD::LOAD, VT, Promote);
1361 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1362 setOperationAction(ISD::SELECT, VT, Promote);
1363 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1367 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1368 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1370 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1373 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1374 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1375 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1377 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1378 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1379 setOperationAction(ISD::XOR, MVT::i1, Legal);
1380 setOperationAction(ISD::OR, MVT::i1, Legal);
1381 setOperationAction(ISD::AND, MVT::i1, Legal);
1382 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1387 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1389 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1396 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1402 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1403 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1407 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1408 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1409 if (Subtarget->is64Bit()) {
1410 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1418 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1422 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1423 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1426 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1447 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1448 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1450 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1460 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1462 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1463 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1465 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1466 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1468 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1470 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1476 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1477 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1479 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1480 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1481 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1482 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1483 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1484 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1486 if (Subtarget->hasCDI()) {
1487 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1488 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1491 // Custom lower several nodes.
1492 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1493 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1494 MVT VT = (MVT::SimpleValueType)i;
1496 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1497 // Extract subvector is special because the value type
1498 // (result) is 256/128-bit but the source is 512-bit wide.
1499 if (VT.is128BitVector() || VT.is256BitVector())
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1502 if (VT.getVectorElementType() == MVT::i1)
1503 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1505 // Do not attempt to custom lower other non-512-bit vectors
1506 if (!VT.is512BitVector())
1509 if ( EltSize >= 32) {
1510 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1511 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1513 setOperationAction(ISD::VSELECT, VT, Legal);
1514 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1515 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1516 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1519 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1520 MVT VT = (MVT::SimpleValueType)i;
1522 // Do not attempt to promote non-256-bit vectors
1523 if (!VT.is512BitVector())
1526 setOperationAction(ISD::SELECT, VT, Promote);
1527 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1531 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1532 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1535 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1536 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1538 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1539 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1540 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1541 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1543 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1544 const MVT VT = (MVT::SimpleValueType)i;
1546 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1548 // Do not attempt to promote non-256-bit vectors
1549 if (!VT.is512BitVector())
1552 if ( EltSize < 32) {
1553 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1554 setOperationAction(ISD::VSELECT, VT, Legal);
1559 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1560 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1561 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1563 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1564 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1565 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1568 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1569 // of this type with custom code.
1570 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1571 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1572 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1576 // We want to custom lower some of our intrinsics.
1577 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1579 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1580 if (!Subtarget->is64Bit())
1581 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1583 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1584 // handle type legalization for these operations here.
1586 // FIXME: We really should do custom legalization for addition and
1587 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1588 // than generic legalization for 64-bit multiplication-with-overflow, though.
1589 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1590 // Add/Sub/Mul with overflow operations are custom lowered.
1592 setOperationAction(ISD::SADDO, VT, Custom);
1593 setOperationAction(ISD::UADDO, VT, Custom);
1594 setOperationAction(ISD::SSUBO, VT, Custom);
1595 setOperationAction(ISD::USUBO, VT, Custom);
1596 setOperationAction(ISD::SMULO, VT, Custom);
1597 setOperationAction(ISD::UMULO, VT, Custom);
1601 if (!Subtarget->is64Bit()) {
1602 // These libcalls are not available in 32-bit.
1603 setLibcallName(RTLIB::SHL_I128, nullptr);
1604 setLibcallName(RTLIB::SRL_I128, nullptr);
1605 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 // Combine sin / cos into one node or libcall if possible.
1609 if (Subtarget->hasSinCos()) {
1610 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1611 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1612 if (Subtarget->isTargetDarwin()) {
1613 // For MacOSX, we don't want to the normal expansion of a libcall to
1614 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1616 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1617 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1621 if (Subtarget->isTargetWin64()) {
1622 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1623 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::SREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UREM, MVT::i128, Custom);
1626 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1627 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1630 // We have target-specific dag combine patterns for the following nodes:
1631 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1632 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1633 setTargetDAGCombine(ISD::VSELECT);
1634 setTargetDAGCombine(ISD::SELECT);
1635 setTargetDAGCombine(ISD::SHL);
1636 setTargetDAGCombine(ISD::SRA);
1637 setTargetDAGCombine(ISD::SRL);
1638 setTargetDAGCombine(ISD::OR);
1639 setTargetDAGCombine(ISD::AND);
1640 setTargetDAGCombine(ISD::ADD);
1641 setTargetDAGCombine(ISD::FADD);
1642 setTargetDAGCombine(ISD::FSUB);
1643 setTargetDAGCombine(ISD::FMA);
1644 setTargetDAGCombine(ISD::SUB);
1645 setTargetDAGCombine(ISD::LOAD);
1646 setTargetDAGCombine(ISD::STORE);
1647 setTargetDAGCombine(ISD::ZERO_EXTEND);
1648 setTargetDAGCombine(ISD::ANY_EXTEND);
1649 setTargetDAGCombine(ISD::SIGN_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1651 setTargetDAGCombine(ISD::TRUNCATE);
1652 setTargetDAGCombine(ISD::SINT_TO_FP);
1653 setTargetDAGCombine(ISD::SETCC);
1654 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1655 setTargetDAGCombine(ISD::BUILD_VECTOR);
1656 if (Subtarget->is64Bit())
1657 setTargetDAGCombine(ISD::MUL);
1658 setTargetDAGCombine(ISD::XOR);
1660 computeRegisterProperties();
1662 // On Darwin, -Os means optimize for size without hurting performance,
1663 // do not reduce the limit.
1664 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1665 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1666 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1667 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1669 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1670 setPrefLoopAlignment(4); // 2^4 bytes.
1672 // Predictable cmov don't hurt on atom because it's in-order.
1673 PredictableSelectIsExpensive = !Subtarget->isAtom();
1675 setPrefFunctionAlignment(4); // 2^4 bytes.
1677 verifyIntrinsicTables();
1680 // This has so far only been implemented for 64-bit MachO.
1681 bool X86TargetLowering::useLoadStackGuardNode() const {
1682 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1683 Subtarget->is64Bit();
1686 TargetLoweringBase::LegalizeTypeAction
1687 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1688 if (ExperimentalVectorWideningLegalization &&
1689 VT.getVectorNumElements() != 1 &&
1690 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1691 return TypeWidenVector;
1693 return TargetLoweringBase::getPreferredVectorAction(VT);
1696 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1698 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1700 const unsigned NumElts = VT.getVectorNumElements();
1701 const EVT EltVT = VT.getVectorElementType();
1702 if (VT.is512BitVector()) {
1703 if (Subtarget->hasAVX512())
1704 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1705 EltVT == MVT::f32 || EltVT == MVT::f64)
1707 case 8: return MVT::v8i1;
1708 case 16: return MVT::v16i1;
1710 if (Subtarget->hasBWI())
1711 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1713 case 32: return MVT::v32i1;
1714 case 64: return MVT::v64i1;
1718 if (VT.is256BitVector() || VT.is128BitVector()) {
1719 if (Subtarget->hasVLX())
1720 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1721 EltVT == MVT::f32 || EltVT == MVT::f64)
1723 case 2: return MVT::v2i1;
1724 case 4: return MVT::v4i1;
1725 case 8: return MVT::v8i1;
1727 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1728 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1730 case 8: return MVT::v8i1;
1731 case 16: return MVT::v16i1;
1732 case 32: return MVT::v32i1;
1736 return VT.changeVectorElementTypeToInteger();
1739 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1740 /// the desired ByVal argument alignment.
1741 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1744 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1745 if (VTy->getBitWidth() == 128)
1747 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1748 unsigned EltAlign = 0;
1749 getMaxByValAlign(ATy->getElementType(), EltAlign);
1750 if (EltAlign > MaxAlign)
1751 MaxAlign = EltAlign;
1752 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1753 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1754 unsigned EltAlign = 0;
1755 getMaxByValAlign(STy->getElementType(i), EltAlign);
1756 if (EltAlign > MaxAlign)
1757 MaxAlign = EltAlign;
1764 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1765 /// function arguments in the caller parameter area. For X86, aggregates
1766 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1767 /// are at 4-byte boundaries.
1768 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1769 if (Subtarget->is64Bit()) {
1770 // Max of 8 and alignment of type.
1771 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1778 if (Subtarget->hasSSE1())
1779 getMaxByValAlign(Ty, Align);
1783 /// getOptimalMemOpType - Returns the target specific optimal type for load
1784 /// and store operations as a result of memset, memcpy, and memmove
1785 /// lowering. If DstAlign is zero that means it's safe to destination
1786 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1787 /// means there isn't a need to check it against alignment requirement,
1788 /// probably because the source does not need to be loaded. If 'IsMemset' is
1789 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1790 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1791 /// source is constant so it does not need to be loaded.
1792 /// It returns EVT::Other if the type should be determined using generic
1793 /// target-independent logic.
1795 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1796 unsigned DstAlign, unsigned SrcAlign,
1797 bool IsMemset, bool ZeroMemset,
1799 MachineFunction &MF) const {
1800 const Function *F = MF.getFunction();
1801 if ((!IsMemset || ZeroMemset) &&
1802 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1803 Attribute::NoImplicitFloat)) {
1805 (Subtarget->isUnalignedMemAccessFast() ||
1806 ((DstAlign == 0 || DstAlign >= 16) &&
1807 (SrcAlign == 0 || SrcAlign >= 16)))) {
1809 if (Subtarget->hasInt256())
1811 if (Subtarget->hasFp256())
1814 if (Subtarget->hasSSE2())
1816 if (Subtarget->hasSSE1())
1818 } else if (!MemcpyStrSrc && Size >= 8 &&
1819 !Subtarget->is64Bit() &&
1820 Subtarget->hasSSE2()) {
1821 // Do not use f64 to lower memcpy if source is string constant. It's
1822 // better to use i32 to avoid the loads.
1826 if (Subtarget->is64Bit() && Size >= 8)
1831 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1833 return X86ScalarSSEf32;
1834 else if (VT == MVT::f64)
1835 return X86ScalarSSEf64;
1840 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1845 *Fast = Subtarget->isUnalignedMemAccessFast();
1849 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1850 /// current function. The returned value is a member of the
1851 /// MachineJumpTableInfo::JTEntryKind enum.
1852 unsigned X86TargetLowering::getJumpTableEncoding() const {
1853 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1855 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1856 Subtarget->isPICStyleGOT())
1857 return MachineJumpTableInfo::EK_Custom32;
1859 // Otherwise, use the normal jump table encoding heuristics.
1860 return TargetLowering::getJumpTableEncoding();
1864 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1865 const MachineBasicBlock *MBB,
1866 unsigned uid,MCContext &Ctx) const{
1867 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT());
1869 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1871 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1872 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1875 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1877 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1878 SelectionDAG &DAG) const {
1879 if (!Subtarget->is64Bit())
1880 // This doesn't have SDLoc associated with it, but is not really the
1881 // same as a Register.
1882 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1886 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1887 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1889 const MCExpr *X86TargetLowering::
1890 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1891 MCContext &Ctx) const {
1892 // X86-64 uses RIP relative addressing based on the jump table label.
1893 if (Subtarget->isPICStyleRIPRel())
1894 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1896 // Otherwise, the reference is relative to the PIC base.
1897 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1900 // FIXME: Why this routine is here? Move to RegInfo!
1901 std::pair<const TargetRegisterClass*, uint8_t>
1902 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1903 const TargetRegisterClass *RRC = nullptr;
1905 switch (VT.SimpleTy) {
1907 return TargetLowering::findRepresentativeClass(VT);
1908 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1909 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1912 RRC = &X86::VR64RegClass;
1914 case MVT::f32: case MVT::f64:
1915 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1916 case MVT::v4f32: case MVT::v2f64:
1917 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1919 RRC = &X86::VR128RegClass;
1922 return std::make_pair(RRC, Cost);
1925 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1926 unsigned &Offset) const {
1927 if (!Subtarget->isTargetLinux())
1930 if (Subtarget->is64Bit()) {
1931 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1933 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1945 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1946 unsigned DestAS) const {
1947 assert(SrcAS != DestAS && "Expected different address spaces!");
1949 return SrcAS < 256 && DestAS < 256;
1952 //===----------------------------------------------------------------------===//
1953 // Return Value Calling Convention Implementation
1954 //===----------------------------------------------------------------------===//
1956 #include "X86GenCallingConv.inc"
1959 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1960 MachineFunction &MF, bool isVarArg,
1961 const SmallVectorImpl<ISD::OutputArg> &Outs,
1962 LLVMContext &Context) const {
1963 SmallVector<CCValAssign, 16> RVLocs;
1964 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1965 return CCInfo.CheckReturn(Outs, RetCC_X86);
1968 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1969 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1974 X86TargetLowering::LowerReturn(SDValue Chain,
1975 CallingConv::ID CallConv, bool isVarArg,
1976 const SmallVectorImpl<ISD::OutputArg> &Outs,
1977 const SmallVectorImpl<SDValue> &OutVals,
1978 SDLoc dl, SelectionDAG &DAG) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1984 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1987 SmallVector<SDValue, 6> RetOps;
1988 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1989 // Operand #1 = Bytes To Pop
1990 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1993 // Copy the result values into the output registers.
1994 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 assert(VA.isRegLoc() && "Can only return in registers!");
1997 SDValue ValToCopy = OutVals[i];
1998 EVT ValVT = ValToCopy.getValueType();
2000 // Promote values to the appropriate types
2001 if (VA.getLocInfo() == CCValAssign::SExt)
2002 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::ZExt)
2004 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::AExt)
2006 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2007 else if (VA.getLocInfo() == CCValAssign::BCvt)
2008 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2010 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2011 "Unexpected FP-extend for return value.");
2013 // If this is x86-64, and we disabled SSE, we can't return FP values,
2014 // or SSE or MMX vectors.
2015 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2016 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2017 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2018 report_fatal_error("SSE register return with SSE disabled");
2020 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2021 // llvm-gcc has never done it right and no one has noticed, so this
2022 // should be OK for now.
2023 if (ValVT == MVT::f64 &&
2024 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2025 report_fatal_error("SSE2 register return with SSE2 disabled");
2027 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2028 // the RET instruction and handled by the FP Stackifier.
2029 if (VA.getLocReg() == X86::FP0 ||
2030 VA.getLocReg() == X86::FP1) {
2031 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2032 // change the value to the FP stack register class.
2033 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2034 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2035 RetOps.push_back(ValToCopy);
2036 // Don't emit a copytoreg.
2040 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2041 // which is returned in RAX / RDX.
2042 if (Subtarget->is64Bit()) {
2043 if (ValVT == MVT::x86mmx) {
2044 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2045 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2046 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2048 // If we don't have SSE2 available, convert to v4f32 so the generated
2049 // register is legal.
2050 if (!Subtarget->hasSSE2())
2051 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2056 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2057 Flag = Chain.getValue(1);
2058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2061 // The x86-64 ABIs require that for returning structs by value we copy
2062 // the sret argument into %rax/%eax (depending on ABI) for the return.
2063 // Win32 requires us to put the sret argument to %eax as well.
2064 // We saved the argument into a virtual register in the entry block,
2065 // so now we copy the value out and into %rax/%eax.
2066 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2067 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2070 unsigned Reg = FuncInfo->getSRetReturnReg();
2072 "SRetReturnReg should have been set in LowerFormalArguments().");
2073 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2076 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2077 X86::RAX : X86::EAX;
2078 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2079 Flag = Chain.getValue(1);
2081 // RAX/EAX now acts like a return value.
2082 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2085 RetOps[0] = Chain; // Update chain.
2087 // Add the flag if we have it.
2089 RetOps.push_back(Flag);
2091 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2094 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2095 if (N->getNumValues() != 1)
2097 if (!N->hasNUsesOfValue(1, 0))
2100 SDValue TCChain = Chain;
2101 SDNode *Copy = *N->use_begin();
2102 if (Copy->getOpcode() == ISD::CopyToReg) {
2103 // If the copy has a glue operand, we conservatively assume it isn't safe to
2104 // perform a tail call.
2105 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2107 TCChain = Copy->getOperand(0);
2108 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2111 bool HasRet = false;
2112 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2114 if (UI->getOpcode() != X86ISD::RET_FLAG)
2116 // If we are returning more than one value, we can definitely
2117 // not make a tail call see PR19530
2118 if (UI->getNumOperands() > 4)
2120 if (UI->getNumOperands() == 4 &&
2121 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2134 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2135 ISD::NodeType ExtendKind) const {
2137 // TODO: Is this also valid on 32-bit?
2138 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2139 ReturnMVT = MVT::i8;
2141 ReturnMVT = MVT::i32;
2143 EVT MinVT = getRegisterType(Context, ReturnMVT);
2144 return VT.bitsLT(MinVT) ? MinVT : VT;
2147 /// LowerCallResult - Lower the result values of a call into the
2148 /// appropriate copies out of appropriate physical registers.
2151 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2152 CallingConv::ID CallConv, bool isVarArg,
2153 const SmallVectorImpl<ISD::InputArg> &Ins,
2154 SDLoc dl, SelectionDAG &DAG,
2155 SmallVectorImpl<SDValue> &InVals) const {
2157 // Assign locations to each value returned by this call.
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 bool Is64Bit = Subtarget->is64Bit();
2160 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2162 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2164 // Copy all of the result registers out of their specified physreg.
2165 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = RVLocs[i];
2167 EVT CopyVT = VA.getValVT();
2169 // If this is x86-64, and we disabled SSE, we can't return FP values
2170 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2171 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2172 report_fatal_error("SSE register return with SSE disabled");
2175 // If we prefer to use the value in xmm registers, copy it out as f80 and
2176 // use a truncate to move it from fp stack reg to xmm reg.
2177 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2178 isScalarFPTypeInSSEReg(VA.getValVT()))
2181 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2182 CopyVT, InFlag).getValue(1);
2183 SDValue Val = Chain.getValue(0);
2185 if (CopyVT != VA.getValVT())
2186 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2187 // This truncation won't change the value.
2188 DAG.getIntPtrConstant(1));
2190 InFlag = Chain.getValue(2);
2191 InVals.push_back(Val);
2197 //===----------------------------------------------------------------------===//
2198 // C & StdCall & Fast Calling Convention implementation
2199 //===----------------------------------------------------------------------===//
2200 // StdCall calling convention seems to be standard for many Windows' API
2201 // routines and around. It differs from C calling convention just a little:
2202 // callee should clean up the stack, not caller. Symbols should be also
2203 // decorated in some fancy way :) It doesn't support any vector arguments.
2204 // For info on fast calling convention see Fast Calling Convention (tail call)
2205 // implementation LowerX86_32FastCCCallTo.
2207 /// CallIsStructReturn - Determines whether a call uses struct return
2209 enum StructReturnType {
2214 static StructReturnType
2215 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2217 return NotStructReturn;
2219 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2220 if (!Flags.isSRet())
2221 return NotStructReturn;
2222 if (Flags.isInReg())
2223 return RegStructReturn;
2224 return StackStructReturn;
2227 /// ArgsAreStructReturn - Determines whether a function uses struct
2228 /// return semantics.
2229 static StructReturnType
2230 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2232 return NotStructReturn;
2234 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2235 if (!Flags.isSRet())
2236 return NotStructReturn;
2237 if (Flags.isInReg())
2238 return RegStructReturn;
2239 return StackStructReturn;
2242 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2243 /// by "Src" to address "Dst" with size and alignment information specified by
2244 /// the specific parameter attribute. The copy will be passed as a byval
2245 /// function parameter.
2247 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2248 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2252 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2253 /*isVolatile*/false, /*AlwaysInline=*/true,
2254 MachinePointerInfo(), MachinePointerInfo());
2257 /// IsTailCallConvention - Return true if the calling convention is one that
2258 /// supports tail call optimization.
2259 static bool IsTailCallConvention(CallingConv::ID CC) {
2260 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2261 CC == CallingConv::HiPE);
2264 /// \brief Return true if the calling convention is a C calling convention.
2265 static bool IsCCallConvention(CallingConv::ID CC) {
2266 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2267 CC == CallingConv::X86_64_SysV);
2270 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2271 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2275 CallingConv::ID CalleeCC = CS.getCallingConv();
2276 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2282 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2283 /// a tailcall target by changing its ABI.
2284 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2285 bool GuaranteedTailCallOpt) {
2286 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2290 X86TargetLowering::LowerMemArgument(SDValue Chain,
2291 CallingConv::ID CallConv,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SDLoc dl, SelectionDAG &DAG,
2294 const CCValAssign &VA,
2295 MachineFrameInfo *MFI,
2297 // Create the nodes corresponding to a load from this parameter slot.
2298 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2299 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2300 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2301 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2304 // If value is passed by pointer we have address passed instead of the value
2306 if (VA.getLocInfo() == CCValAssign::Indirect)
2307 ValVT = VA.getLocVT();
2309 ValVT = VA.getValVT();
2311 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2312 // changed with more analysis.
2313 // In case of tail call optimization mark all arguments mutable. Since they
2314 // could be overwritten by lowering of arguments in case of a tail call.
2315 if (Flags.isByVal()) {
2316 unsigned Bytes = Flags.getByValSize();
2317 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2318 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2319 return DAG.getFrameIndex(FI, getPointerTy());
2321 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2322 VA.getLocMemOffset(), isImmutable);
2323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2324 return DAG.getLoad(ValVT, dl, Chain, FIN,
2325 MachinePointerInfo::getFixedStack(FI),
2326 false, false, false, 0);
2330 // FIXME: Get this from tablegen.
2331 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2332 const X86Subtarget *Subtarget) {
2333 assert(Subtarget->is64Bit());
2335 if (Subtarget->isCallingConvWin64(CallConv)) {
2336 static const MCPhysReg GPR64ArgRegsWin64[] = {
2337 X86::RCX, X86::RDX, X86::R8, X86::R9
2339 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2342 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2343 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2345 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2348 // FIXME: Get this from tablegen.
2349 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2350 CallingConv::ID CallConv,
2351 const X86Subtarget *Subtarget) {
2352 assert(Subtarget->is64Bit());
2353 if (Subtarget->isCallingConvWin64(CallConv)) {
2354 // The XMM registers which might contain var arg parameters are shadowed
2355 // in their paired GPR. So we only need to save the GPR to their home
2357 // TODO: __vectorcall will change this.
2361 const Function *Fn = MF.getFunction();
2362 bool NoImplicitFloatOps = Fn->getAttributes().
2363 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2364 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2365 "SSE register cannot be used when SSE is disabled!");
2366 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2367 !Subtarget->hasSSE1())
2368 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2372 static const MCPhysReg XMMArgRegs64Bit[] = {
2373 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2374 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2376 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2380 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2381 CallingConv::ID CallConv,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2386 SmallVectorImpl<SDValue> &InVals)
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2391 const Function* Fn = MF.getFunction();
2392 if (Fn->hasExternalLinkage() &&
2393 Subtarget->isTargetCygMing() &&
2394 Fn->getName() == "main")
2395 FuncInfo->setForceFramePointer(true);
2397 MachineFrameInfo *MFI = MF.getFrameInfo();
2398 bool Is64Bit = Subtarget->is64Bit();
2399 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2401 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2402 "Var args not supported with calling convention fastcc, ghc or hipe");
2404 // Assign locations to all of the incoming arguments.
2405 SmallVector<CCValAssign, 16> ArgLocs;
2406 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2408 // Allocate shadow area for Win64
2410 CCInfo.AllocateStack(32, 8);
2412 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2414 unsigned LastVal = ~0U;
2416 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2417 CCValAssign &VA = ArgLocs[i];
2418 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2420 assert(VA.getValNo() != LastVal &&
2421 "Don't support value assigned to multiple locs yet");
2423 LastVal = VA.getValNo();
2425 if (VA.isRegLoc()) {
2426 EVT RegVT = VA.getLocVT();
2427 const TargetRegisterClass *RC;
2428 if (RegVT == MVT::i32)
2429 RC = &X86::GR32RegClass;
2430 else if (Is64Bit && RegVT == MVT::i64)
2431 RC = &X86::GR64RegClass;
2432 else if (RegVT == MVT::f32)
2433 RC = &X86::FR32RegClass;
2434 else if (RegVT == MVT::f64)
2435 RC = &X86::FR64RegClass;
2436 else if (RegVT.is512BitVector())
2437 RC = &X86::VR512RegClass;
2438 else if (RegVT.is256BitVector())
2439 RC = &X86::VR256RegClass;
2440 else if (RegVT.is128BitVector())
2441 RC = &X86::VR128RegClass;
2442 else if (RegVT == MVT::x86mmx)
2443 RC = &X86::VR64RegClass;
2444 else if (RegVT == MVT::i1)
2445 RC = &X86::VK1RegClass;
2446 else if (RegVT == MVT::v8i1)
2447 RC = &X86::VK8RegClass;
2448 else if (RegVT == MVT::v16i1)
2449 RC = &X86::VK16RegClass;
2450 else if (RegVT == MVT::v32i1)
2451 RC = &X86::VK32RegClass;
2452 else if (RegVT == MVT::v64i1)
2453 RC = &X86::VK64RegClass;
2455 llvm_unreachable("Unknown argument type!");
2457 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2458 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2460 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2461 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2463 if (VA.getLocInfo() == CCValAssign::SExt)
2464 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::ZExt)
2467 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2468 DAG.getValueType(VA.getValVT()));
2469 else if (VA.getLocInfo() == CCValAssign::BCvt)
2470 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2472 if (VA.isExtInLoc()) {
2473 // Handle MMX values passed in XMM regs.
2474 if (RegVT.isVector())
2475 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2477 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2480 assert(VA.isMemLoc());
2481 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2484 // If value is passed via pointer - do a load.
2485 if (VA.getLocInfo() == CCValAssign::Indirect)
2486 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2487 MachinePointerInfo(), false, false, false, 0);
2489 InVals.push_back(ArgValue);
2492 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2493 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2494 // The x86-64 ABIs require that for returning structs by value we copy
2495 // the sret argument into %rax/%eax (depending on ABI) for the return.
2496 // Win32 requires us to put the sret argument to %eax as well.
2497 // Save the argument into a virtual register so that we can access it
2498 // from the return points.
2499 if (Ins[i].Flags.isSRet()) {
2500 unsigned Reg = FuncInfo->getSRetReturnReg();
2502 MVT PtrTy = getPointerTy();
2503 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2504 FuncInfo->setSRetReturnReg(Reg);
2506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2513 unsigned StackSize = CCInfo.getNextStackOffset();
2514 // Align stack specially for tail calls.
2515 if (FuncIsMadeTailCallSafe(CallConv,
2516 MF.getTarget().Options.GuaranteedTailCallOpt))
2517 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2519 // If the function takes variable number of arguments, make a frame index for
2520 // the start of the first vararg value... for expansion of llvm.va_start. We
2521 // can skip this if there are no va_start calls.
2522 if (MFI->hasVAStart() &&
2523 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2524 CallConv != CallingConv::X86_ThisCall))) {
2525 FuncInfo->setVarArgsFrameIndex(
2526 MFI->CreateFixedObject(1, StackSize, true));
2529 // 64-bit calling conventions support varargs and register parameters, so we
2530 // have to do extra work to spill them in the prologue or forward them to
2532 if (Is64Bit && isVarArg &&
2533 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2534 // Find the first unallocated argument registers.
2535 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2536 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2537 unsigned NumIntRegs =
2538 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2539 unsigned NumXMMRegs =
2540 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2541 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2542 "SSE register cannot be used when SSE is disabled!");
2544 // Gather all the live in physical registers.
2545 SmallVector<SDValue, 6> LiveGPRs;
2546 SmallVector<SDValue, 8> LiveXMMRegs;
2548 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2549 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2551 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2553 if (!ArgXMMs.empty()) {
2554 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2555 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2556 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2557 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2558 LiveXMMRegs.push_back(
2559 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2563 // Store them to the va_list returned by va_start.
2564 if (MFI->hasVAStart()) {
2566 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2567 // Get to the caller-allocated home save location. Add 8 to account
2568 // for the return address.
2569 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2570 FuncInfo->setRegSaveFrameIndex(
2571 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2572 // Fixup to set vararg frame on shadow area (4 x i64).
2574 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2576 // For X86-64, if there are vararg parameters that are passed via
2577 // registers, then we must store them to their spots on the stack so
2578 // they may be loaded by deferencing the result of va_next.
2579 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2580 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2581 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2582 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2585 // Store the integer parameter registers.
2586 SmallVector<SDValue, 8> MemOps;
2587 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2589 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2590 for (SDValue Val : LiveGPRs) {
2591 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2592 DAG.getIntPtrConstant(Offset));
2594 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2595 MachinePointerInfo::getFixedStack(
2596 FuncInfo->getRegSaveFrameIndex(), Offset),
2598 MemOps.push_back(Store);
2602 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2603 // Now store the XMM (fp + vector) parameter registers.
2604 SmallVector<SDValue, 12> SaveXMMOps;
2605 SaveXMMOps.push_back(Chain);
2606 SaveXMMOps.push_back(ALVal);
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getRegSaveFrameIndex()));
2609 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2610 FuncInfo->getVarArgsFPOffset()));
2611 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2613 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2614 MVT::Other, SaveXMMOps));
2617 if (!MemOps.empty())
2618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2620 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2621 // to the liveout set on a musttail call.
2622 assert(MFI->hasMustTailInVarArgFunc());
2623 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2624 typedef X86MachineFunctionInfo::Forward Forward;
2626 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2628 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2629 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2630 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2633 if (!ArgXMMs.empty()) {
2635 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2636 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2637 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2639 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2641 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2642 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2644 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2650 // Some CCs need callee pop.
2651 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2652 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2653 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2655 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2656 // If this is an sret function, the return should pop the hidden pointer.
2657 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2658 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2659 argsAreStructReturn(Ins) == StackStructReturn)
2660 FuncInfo->setBytesToPopOnReturn(4);
2664 // RegSaveFrameIndex is X86-64 only.
2665 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2666 if (CallConv == CallingConv::X86_FastCall ||
2667 CallConv == CallingConv::X86_ThisCall)
2668 // fastcc functions can't have varargs.
2669 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2672 FuncInfo->setArgumentStackSize(StackSize);
2678 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2679 SDValue StackPtr, SDValue Arg,
2680 SDLoc dl, SelectionDAG &DAG,
2681 const CCValAssign &VA,
2682 ISD::ArgFlagsTy Flags) const {
2683 unsigned LocMemOffset = VA.getLocMemOffset();
2684 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2685 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2686 if (Flags.isByVal())
2687 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2689 return DAG.getStore(Chain, dl, Arg, PtrOff,
2690 MachinePointerInfo::getStack(LocMemOffset),
2694 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2695 /// optimization is performed and it is required.
2697 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2698 SDValue &OutRetAddr, SDValue Chain,
2699 bool IsTailCall, bool Is64Bit,
2700 int FPDiff, SDLoc dl) const {
2701 // Adjust the Return address stack slot.
2702 EVT VT = getPointerTy();
2703 OutRetAddr = getReturnAddressFrameIndex(DAG);
2705 // Load the "old" Return address.
2706 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2707 false, false, false, 0);
2708 return SDValue(OutRetAddr.getNode(), 1);
2711 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2712 /// optimization is performed and it is required (FPDiff!=0).
2713 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2714 SDValue Chain, SDValue RetAddrFrIdx,
2715 EVT PtrVT, unsigned SlotSize,
2716 int FPDiff, SDLoc dl) {
2717 // Store the return address to the appropriate stack slot.
2718 if (!FPDiff) return Chain;
2719 // Calculate the new stack slot for the return address.
2720 int NewReturnAddrFI =
2721 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2723 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2724 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2725 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2731 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2732 SmallVectorImpl<SDValue> &InVals) const {
2733 SelectionDAG &DAG = CLI.DAG;
2735 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2736 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2737 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2738 SDValue Chain = CLI.Chain;
2739 SDValue Callee = CLI.Callee;
2740 CallingConv::ID CallConv = CLI.CallConv;
2741 bool &isTailCall = CLI.IsTailCall;
2742 bool isVarArg = CLI.IsVarArg;
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 bool Is64Bit = Subtarget->is64Bit();
2746 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2747 StructReturnType SR = callIsStructReturn(Outs);
2748 bool IsSibcall = false;
2749 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2751 if (MF.getTarget().Options.DisableTailCalls)
2754 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2756 // Force this to be a tail call. The verifier rules are enough to ensure
2757 // that we can lower this successfully without moving the return address
2760 } else if (isTailCall) {
2761 // Check if it's really possible to do a tail call.
2762 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2763 isVarArg, SR != NotStructReturn,
2764 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2765 Outs, OutVals, Ins, DAG);
2767 // Sibcalls are automatically detected tailcalls which do not require
2769 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2776 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2777 "Var args not supported with calling convention fastcc, ghc or hipe");
2779 // Analyze operands of the call, assigning locations to each operand.
2780 SmallVector<CCValAssign, 16> ArgLocs;
2781 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2783 // Allocate shadow area for Win64
2785 CCInfo.AllocateStack(32, 8);
2787 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2789 // Get a count of how many bytes are to be pushed on the stack.
2790 unsigned NumBytes = CCInfo.getNextStackOffset();
2792 // This is a sibcall. The memory operands are available in caller's
2793 // own caller's stack.
2795 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2796 IsTailCallConvention(CallConv))
2797 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2800 if (isTailCall && !IsSibcall && !IsMustTail) {
2801 // Lower arguments at fp - stackoffset + fpdiff.
2802 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2804 FPDiff = NumBytesCallerPushed - NumBytes;
2806 // Set the delta of movement of the returnaddr stackslot.
2807 // But only set if delta is greater than previous delta.
2808 if (FPDiff < X86Info->getTCReturnAddrDelta())
2809 X86Info->setTCReturnAddrDelta(FPDiff);
2812 unsigned NumBytesToPush = NumBytes;
2813 unsigned NumBytesToPop = NumBytes;
2815 // If we have an inalloca argument, all stack space has already been allocated
2816 // for us and be right at the top of the stack. We don't support multiple
2817 // arguments passed in memory when using inalloca.
2818 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2820 if (!ArgLocs.back().isMemLoc())
2821 report_fatal_error("cannot use inalloca attribute on a register "
2823 if (ArgLocs.back().getLocMemOffset() != 0)
2824 report_fatal_error("any parameter with the inalloca attribute must be "
2825 "the only memory argument");
2829 Chain = DAG.getCALLSEQ_START(
2830 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2832 SDValue RetAddrFrIdx;
2833 // Load return address for tail calls.
2834 if (isTailCall && FPDiff)
2835 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2836 Is64Bit, FPDiff, dl);
2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2839 SmallVector<SDValue, 8> MemOpChains;
2842 // Walk the register/memloc assignments, inserting copies/loads. In the case
2843 // of tail call optimization arguments are handle later.
2844 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2845 DAG.getSubtarget().getRegisterInfo());
2846 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2847 // Skip inalloca arguments, they have already been written.
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2849 if (Flags.isInAlloca())
2852 CCValAssign &VA = ArgLocs[i];
2853 EVT RegVT = VA.getLocVT();
2854 SDValue Arg = OutVals[i];
2855 bool isByVal = Flags.isByVal();
2857 // Promote the value if needed.
2858 switch (VA.getLocInfo()) {
2859 default: llvm_unreachable("Unknown loc info!");
2860 case CCValAssign::Full: break;
2861 case CCValAssign::SExt:
2862 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::ZExt:
2865 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2867 case CCValAssign::AExt:
2868 if (RegVT.is128BitVector()) {
2869 // Special case: passing MMX values in XMM registers.
2870 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2871 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2872 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2874 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2876 case CCValAssign::BCvt:
2877 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2879 case CCValAssign::Indirect: {
2880 // Store the argument.
2881 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2882 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2883 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2884 MachinePointerInfo::getFixedStack(FI),
2891 if (VA.isRegLoc()) {
2892 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2893 if (isVarArg && IsWin64) {
2894 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2895 // shadow reg if callee is a varargs function.
2896 unsigned ShadowReg = 0;
2897 switch (VA.getLocReg()) {
2898 case X86::XMM0: ShadowReg = X86::RCX; break;
2899 case X86::XMM1: ShadowReg = X86::RDX; break;
2900 case X86::XMM2: ShadowReg = X86::R8; break;
2901 case X86::XMM3: ShadowReg = X86::R9; break;
2904 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2906 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2907 assert(VA.isMemLoc());
2908 if (!StackPtr.getNode())
2909 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2911 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2912 dl, DAG, VA, Flags));
2916 if (!MemOpChains.empty())
2917 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2919 if (Subtarget->isPICStyleGOT()) {
2920 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2923 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2924 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2926 // If we are tail calling and generating PIC/GOT style code load the
2927 // address of the callee into ECX. The value in ecx is used as target of
2928 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2929 // for tail calls on PIC/GOT architectures. Normally we would just put the
2930 // address of GOT into ebx and then call target@PLT. But for tail calls
2931 // ebx would be restored (since ebx is callee saved) before jumping to the
2934 // Note: The actual moving to ECX is done further down.
2935 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2936 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2937 !G->getGlobal()->hasProtectedVisibility())
2938 Callee = LowerGlobalAddress(Callee, DAG);
2939 else if (isa<ExternalSymbolSDNode>(Callee))
2940 Callee = LowerExternalSymbol(Callee, DAG);
2944 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2945 // From AMD64 ABI document:
2946 // For calls that may call functions that use varargs or stdargs
2947 // (prototype-less calls or calls to functions containing ellipsis (...) in
2948 // the declaration) %al is used as hidden argument to specify the number
2949 // of SSE registers used. The contents of %al do not need to match exactly
2950 // the number of registers, but must be an ubound on the number of SSE
2951 // registers used and is in the range 0 - 8 inclusive.
2953 // Count the number of XMM registers allocated.
2954 static const MCPhysReg XMMArgRegs[] = {
2955 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2956 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2958 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2959 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2960 && "SSE registers cannot be used when SSE is disabled");
2962 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2963 DAG.getConstant(NumXMMRegs, MVT::i8)));
2966 if (Is64Bit && isVarArg && IsMustTail) {
2967 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2968 for (const auto &F : Forwards) {
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2970 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2974 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2975 // don't need this because the eligibility check rejects calls that require
2976 // shuffling arguments passed in memory.
2977 if (!IsSibcall && isTailCall) {
2978 // Force all the incoming stack arguments to be loaded from the stack
2979 // before any new outgoing arguments are stored to the stack, because the
2980 // outgoing stack slots may alias the incoming argument stack slots, and
2981 // the alias isn't otherwise explicit. This is slightly more conservative
2982 // than necessary, because it means that each store effectively depends
2983 // on every argument instead of just those arguments it would clobber.
2984 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2986 SmallVector<SDValue, 8> MemOpChains2;
2989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2990 CCValAssign &VA = ArgLocs[i];
2993 assert(VA.isMemLoc());
2994 SDValue Arg = OutVals[i];
2995 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2996 // Skip inalloca arguments. They don't require any work.
2997 if (Flags.isInAlloca())
2999 // Create frame index.
3000 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3001 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3002 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3003 FIN = DAG.getFrameIndex(FI, getPointerTy());
3005 if (Flags.isByVal()) {
3006 // Copy relative to framepointer.
3007 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3008 if (!StackPtr.getNode())
3009 StackPtr = DAG.getCopyFromReg(Chain, dl,
3010 RegInfo->getStackRegister(),
3012 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3014 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3018 // Store relative to framepointer.
3019 MemOpChains2.push_back(
3020 DAG.getStore(ArgChain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 if (!MemOpChains2.empty())
3027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3029 // Store the return address to the appropriate stack slot.
3030 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3031 getPointerTy(), RegInfo->getSlotSize(),
3035 // Build a sequence of copy-to-reg nodes chained together with token chain
3036 // and flag operands which copy the outgoing args into registers.
3038 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3039 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3040 RegsToPass[i].second, InFlag);
3041 InFlag = Chain.getValue(1);
3044 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3045 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3046 // In the 64-bit large code model, we have to make all calls
3047 // through a register, since the call instruction's 32-bit
3048 // pc-relative offset may not be large enough to hold the whole
3050 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3051 // If the callee is a GlobalAddress node (quite common, every direct call
3052 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3055 // We should use extra load for direct calls to dllimported functions in
3057 const GlobalValue *GV = G->getGlobal();
3058 if (!GV->hasDLLImportStorageClass()) {
3059 unsigned char OpFlags = 0;
3060 bool ExtraLoad = false;
3061 unsigned WrapperKind = ISD::DELETED_NODE;
3063 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3064 // external symbols most go through the PLT in PIC mode. If the symbol
3065 // has hidden or protected visibility, or if it is static or local, then
3066 // we don't need to use the PLT - we can directly call it.
3067 if (Subtarget->isTargetELF() &&
3068 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3069 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3070 OpFlags = X86II::MO_PLT;
3071 } else if (Subtarget->isPICStyleStubAny() &&
3072 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3073 (!Subtarget->getTargetTriple().isMacOSX() ||
3074 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3075 // PC-relative references to external symbols should go through $stub,
3076 // unless we're building with the leopard linker or later, which
3077 // automatically synthesizes these stubs.
3078 OpFlags = X86II::MO_DARWIN_STUB;
3079 } else if (Subtarget->isPICStyleRIPRel() &&
3080 isa<Function>(GV) &&
3081 cast<Function>(GV)->getAttributes().
3082 hasAttribute(AttributeSet::FunctionIndex,
3083 Attribute::NonLazyBind)) {
3084 // If the function is marked as non-lazy, generate an indirect call
3085 // which loads from the GOT directly. This avoids runtime overhead
3086 // at the cost of eager binding (and one extra byte of encoding).
3087 OpFlags = X86II::MO_GOTPCREL;
3088 WrapperKind = X86ISD::WrapperRIP;
3092 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3093 G->getOffset(), OpFlags);
3095 // Add a wrapper if needed.
3096 if (WrapperKind != ISD::DELETED_NODE)
3097 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3098 // Add extra indirection if needed.
3100 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3101 MachinePointerInfo::getGOT(),
3102 false, false, false, 0);
3104 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3105 unsigned char OpFlags = 0;
3107 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3108 // external symbols should go through the PLT.
3109 if (Subtarget->isTargetELF() &&
3110 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3111 OpFlags = X86II::MO_PLT;
3112 } else if (Subtarget->isPICStyleStubAny() &&
3113 (!Subtarget->getTargetTriple().isMacOSX() ||
3114 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3115 // PC-relative references to external symbols should go through $stub,
3116 // unless we're building with the leopard linker or later, which
3117 // automatically synthesizes these stubs.
3118 OpFlags = X86II::MO_DARWIN_STUB;
3121 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3123 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3124 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3125 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3128 // Returns a chain & a flag for retval copy to use.
3129 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3130 SmallVector<SDValue, 8> Ops;
3132 if (!IsSibcall && isTailCall) {
3133 Chain = DAG.getCALLSEQ_END(Chain,
3134 DAG.getIntPtrConstant(NumBytesToPop, true),
3135 DAG.getIntPtrConstant(0, true), InFlag, dl);
3136 InFlag = Chain.getValue(1);
3139 Ops.push_back(Chain);
3140 Ops.push_back(Callee);
3143 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3145 // Add argument registers to the end of the list so that they are known live
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3148 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3149 RegsToPass[i].second.getValueType()));
3151 // Add a register mask operand representing the call-preserved registers.
3152 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3153 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3154 assert(Mask && "Missing call preserved mask for calling convention");
3155 Ops.push_back(DAG.getRegisterMask(Mask));
3157 if (InFlag.getNode())
3158 Ops.push_back(InFlag);
3162 //// If this is the first return lowered for this function, add the regs
3163 //// to the liveout set for the function.
3164 // This isn't right, although it's probably harmless on x86; liveouts
3165 // should be computed from returns not tail calls. Consider a void
3166 // function making a tail call to a function returning int.
3167 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3170 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3171 InFlag = Chain.getValue(1);
3173 // Create the CALLSEQ_END node.
3174 unsigned NumBytesForCalleeToPop;
3175 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3176 DAG.getTarget().Options.GuaranteedTailCallOpt))
3177 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3178 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3179 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3180 SR == StackStructReturn)
3181 // If this is a call to a struct-return function, the callee
3182 // pops the hidden struct pointer, so we have to push it back.
3183 // This is common for Darwin/X86, Linux & Mingw32 targets.
3184 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3185 NumBytesForCalleeToPop = 4;
3187 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3189 // Returns a flag for retval copy to use.
3191 Chain = DAG.getCALLSEQ_END(Chain,
3192 DAG.getIntPtrConstant(NumBytesToPop, true),
3193 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3196 InFlag = Chain.getValue(1);
3199 // Handle result values, copying them out of physregs into vregs that we
3201 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3202 Ins, dl, DAG, InVals);
3205 //===----------------------------------------------------------------------===//
3206 // Fast Calling Convention (tail call) implementation
3207 //===----------------------------------------------------------------------===//
3209 // Like std call, callee cleans arguments, convention except that ECX is
3210 // reserved for storing the tail called function address. Only 2 registers are
3211 // free for argument passing (inreg). Tail call optimization is performed
3213 // * tailcallopt is enabled
3214 // * caller/callee are fastcc
3215 // On X86_64 architecture with GOT-style position independent code only local
3216 // (within module) calls are supported at the moment.
3217 // To keep the stack aligned according to platform abi the function
3218 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3219 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3220 // If a tail called function callee has more arguments than the caller the
3221 // caller needs to make sure that there is room to move the RETADDR to. This is
3222 // achieved by reserving an area the size of the argument delta right after the
3223 // original RETADDR, but before the saved framepointer or the spilled registers
3224 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3236 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3237 /// for a 16 byte align requirement.
3239 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3240 SelectionDAG& DAG) const {
3241 MachineFunction &MF = DAG.getMachineFunction();
3242 const TargetMachine &TM = MF.getTarget();
3243 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3244 TM.getSubtargetImpl()->getRegisterInfo());
3245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3246 unsigned StackAlignment = TFI.getStackAlignment();
3247 uint64_t AlignMask = StackAlignment - 1;
3248 int64_t Offset = StackSize;
3249 unsigned SlotSize = RegInfo->getSlotSize();
3250 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3251 // Number smaller than 12 so just add the difference.
3252 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3254 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3255 Offset = ((~AlignMask) & Offset) + StackAlignment +
3256 (StackAlignment-SlotSize);
3261 /// MatchingStackOffset - Return true if the given stack call argument is
3262 /// already available in the same position (relatively) of the caller's
3263 /// incoming argument stack.
3265 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3266 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3267 const X86InstrInfo *TII) {
3268 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3270 if (Arg.getOpcode() == ISD::CopyFromReg) {
3271 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3272 if (!TargetRegisterInfo::isVirtualRegister(VR))
3274 MachineInstr *Def = MRI->getVRegDef(VR);
3277 if (!Flags.isByVal()) {
3278 if (!TII->isLoadFromStackSlot(Def, FI))
3281 unsigned Opcode = Def->getOpcode();
3282 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3283 Def->getOperand(1).isFI()) {
3284 FI = Def->getOperand(1).getIndex();
3285 Bytes = Flags.getByValSize();
3289 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3290 if (Flags.isByVal())
3291 // ByVal argument is passed in as a pointer but it's now being
3292 // dereferenced. e.g.
3293 // define @foo(%struct.X* %A) {
3294 // tail call @bar(%struct.X* byval %A)
3297 SDValue Ptr = Ld->getBasePtr();
3298 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3301 FI = FINode->getIndex();
3302 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3303 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3304 FI = FINode->getIndex();
3305 Bytes = Flags.getByValSize();
3309 assert(FI != INT_MAX);
3310 if (!MFI->isFixedObjectIndex(FI))
3312 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3315 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3316 /// for tail call optimization. Targets which want to do tail call
3317 /// optimization should implement this function.
3319 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3320 CallingConv::ID CalleeCC,
3322 bool isCalleeStructRet,
3323 bool isCallerStructRet,
3325 const SmallVectorImpl<ISD::OutputArg> &Outs,
3326 const SmallVectorImpl<SDValue> &OutVals,
3327 const SmallVectorImpl<ISD::InputArg> &Ins,
3328 SelectionDAG &DAG) const {
3329 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3332 // If -tailcallopt is specified, make fastcc functions tail-callable.
3333 const MachineFunction &MF = DAG.getMachineFunction();
3334 const Function *CallerF = MF.getFunction();
3336 // If the function return type is x86_fp80 and the callee return type is not,
3337 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3338 // perform a tailcall optimization here.
3339 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3342 CallingConv::ID CallerCC = CallerF->getCallingConv();
3343 bool CCMatch = CallerCC == CalleeCC;
3344 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3345 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3347 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3348 if (IsTailCallConvention(CalleeCC) && CCMatch)
3353 // Look for obvious safe cases to perform tail call optimization that do not
3354 // require ABI changes. This is what gcc calls sibcall.
3356 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3357 // emit a special epilogue.
3358 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3359 DAG.getSubtarget().getRegisterInfo());
3360 if (RegInfo->needsStackRealignment(MF))
3363 // Also avoid sibcall optimization if either caller or callee uses struct
3364 // return semantics.
3365 if (isCalleeStructRet || isCallerStructRet)
3368 // An stdcall/thiscall caller is expected to clean up its arguments; the
3369 // callee isn't going to do that.
3370 // FIXME: this is more restrictive than needed. We could produce a tailcall
3371 // when the stack adjustment matches. For example, with a thiscall that takes
3372 // only one argument.
3373 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3374 CallerCC == CallingConv::X86_ThisCall))
3377 // Do not sibcall optimize vararg calls unless all arguments are passed via
3379 if (isVarArg && !Outs.empty()) {
3381 // Optimizing for varargs on Win64 is unlikely to be safe without
3382 // additional testing.
3383 if (IsCalleeWin64 || IsCallerWin64)
3386 SmallVector<CCValAssign, 16> ArgLocs;
3387 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3390 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3391 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3392 if (!ArgLocs[i].isRegLoc())
3396 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3397 // stack. Therefore, if it's not used by the call it is not safe to optimize
3398 // this into a sibcall.
3399 bool Unused = false;
3400 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3407 SmallVector<CCValAssign, 16> RVLocs;
3408 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3410 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3411 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3412 CCValAssign &VA = RVLocs[i];
3413 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3418 // If the calling conventions do not match, then we'd better make sure the
3419 // results are returned in the same way as what the caller expects.
3421 SmallVector<CCValAssign, 16> RVLocs1;
3422 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3424 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3426 SmallVector<CCValAssign, 16> RVLocs2;
3427 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3429 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3431 if (RVLocs1.size() != RVLocs2.size())
3433 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3434 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3436 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3438 if (RVLocs1[i].isRegLoc()) {
3439 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3442 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3448 // If the callee takes no arguments then go on to check the results of the
3450 if (!Outs.empty()) {
3451 // Check if stack adjustment is needed. For now, do not do this if any
3452 // argument is passed on the stack.
3453 SmallVector<CCValAssign, 16> ArgLocs;
3454 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3457 // Allocate shadow area for Win64
3459 CCInfo.AllocateStack(32, 8);
3461 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3462 if (CCInfo.getNextStackOffset()) {
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3467 // Check if the arguments are already laid out in the right way as
3468 // the caller's fixed stack objects.
3469 MachineFrameInfo *MFI = MF.getFrameInfo();
3470 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3471 const X86InstrInfo *TII =
3472 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3473 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3474 CCValAssign &VA = ArgLocs[i];
3475 SDValue Arg = OutVals[i];
3476 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3477 if (VA.getLocInfo() == CCValAssign::Indirect)
3479 if (!VA.isRegLoc()) {
3480 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3487 // If the tailcall address may be in a register, then make sure it's
3488 // possible to register allocate for it. In 32-bit, the call address can
3489 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3490 // callee-saved registers are restored. These happen to be the same
3491 // registers used to pass 'inreg' arguments so watch out for those.
3492 if (!Subtarget->is64Bit() &&
3493 ((!isa<GlobalAddressSDNode>(Callee) &&
3494 !isa<ExternalSymbolSDNode>(Callee)) ||
3495 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3496 unsigned NumInRegs = 0;
3497 // In PIC we need an extra register to formulate the address computation
3499 unsigned MaxInRegs =
3500 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3503 CCValAssign &VA = ArgLocs[i];
3506 unsigned Reg = VA.getLocReg();
3509 case X86::EAX: case X86::EDX: case X86::ECX:
3510 if (++NumInRegs == MaxInRegs)
3522 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3523 const TargetLibraryInfo *libInfo) const {
3524 return X86::createFastISel(funcInfo, libInfo);
3527 //===----------------------------------------------------------------------===//
3528 // Other Lowering Hooks
3529 //===----------------------------------------------------------------------===//
3531 static bool MayFoldLoad(SDValue Op) {
3532 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3535 static bool MayFoldIntoStore(SDValue Op) {
3536 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3539 static bool isTargetShuffle(unsigned Opcode) {
3541 default: return false;
3542 case X86ISD::BLENDI:
3543 case X86ISD::PSHUFB:
3544 case X86ISD::PSHUFD:
3545 case X86ISD::PSHUFHW:
3546 case X86ISD::PSHUFLW:
3548 case X86ISD::PALIGNR:
3549 case X86ISD::MOVLHPS:
3550 case X86ISD::MOVLHPD:
3551 case X86ISD::MOVHLPS:
3552 case X86ISD::MOVLPS:
3553 case X86ISD::MOVLPD:
3554 case X86ISD::MOVSHDUP:
3555 case X86ISD::MOVSLDUP:
3556 case X86ISD::MOVDDUP:
3559 case X86ISD::UNPCKL:
3560 case X86ISD::UNPCKH:
3561 case X86ISD::VPERMILPI:
3562 case X86ISD::VPERM2X128:
3563 case X86ISD::VPERMI:
3568 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3569 SDValue V1, SelectionDAG &DAG) {
3571 default: llvm_unreachable("Unknown x86 shuffle node");
3572 case X86ISD::MOVSHDUP:
3573 case X86ISD::MOVSLDUP:
3574 case X86ISD::MOVDDUP:
3575 return DAG.getNode(Opc, dl, VT, V1);
3579 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3580 SDValue V1, unsigned TargetMask,
3581 SelectionDAG &DAG) {
3583 default: llvm_unreachable("Unknown x86 shuffle node");
3584 case X86ISD::PSHUFD:
3585 case X86ISD::PSHUFHW:
3586 case X86ISD::PSHUFLW:
3587 case X86ISD::VPERMILPI:
3588 case X86ISD::VPERMI:
3589 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3593 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3594 SDValue V1, SDValue V2, unsigned TargetMask,
3595 SelectionDAG &DAG) {
3597 default: llvm_unreachable("Unknown x86 shuffle node");
3598 case X86ISD::PALIGNR:
3599 case X86ISD::VALIGN:
3601 case X86ISD::VPERM2X128:
3602 return DAG.getNode(Opc, dl, VT, V1, V2,
3603 DAG.getConstant(TargetMask, MVT::i8));
3607 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3608 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::MOVLHPS:
3612 case X86ISD::MOVLHPD:
3613 case X86ISD::MOVHLPS:
3614 case X86ISD::MOVLPS:
3615 case X86ISD::MOVLPD:
3618 case X86ISD::UNPCKL:
3619 case X86ISD::UNPCKH:
3620 return DAG.getNode(Opc, dl, VT, V1, V2);
3624 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3627 DAG.getSubtarget().getRegisterInfo());
3628 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3629 int ReturnAddrIndex = FuncInfo->getRAIndex();
3631 if (ReturnAddrIndex == 0) {
3632 // Set up a frame object for the return address.
3633 unsigned SlotSize = RegInfo->getSlotSize();
3634 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3637 FuncInfo->setRAIndex(ReturnAddrIndex);
3640 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3643 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3644 bool hasSymbolicDisplacement) {
3645 // Offset should fit into 32 bit immediate field.
3646 if (!isInt<32>(Offset))
3649 // If we don't have a symbolic displacement - we don't have any extra
3651 if (!hasSymbolicDisplacement)
3654 // FIXME: Some tweaks might be needed for medium code model.
3655 if (M != CodeModel::Small && M != CodeModel::Kernel)
3658 // For small code model we assume that latest object is 16MB before end of 31
3659 // bits boundary. We may also accept pretty large negative constants knowing
3660 // that all objects are in the positive half of address space.
3661 if (M == CodeModel::Small && Offset < 16*1024*1024)
3664 // For kernel code model we know that all object resist in the negative half
3665 // of 32bits address space. We may not accept negative offsets, since they may
3666 // be just off and we may accept pretty large positive ones.
3667 if (M == CodeModel::Kernel && Offset > 0)
3673 /// isCalleePop - Determines whether the callee is required to pop its
3674 /// own arguments. Callee pop is necessary to support tail calls.
3675 bool X86::isCalleePop(CallingConv::ID CallingConv,
3676 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3677 switch (CallingConv) {
3680 case CallingConv::X86_StdCall:
3681 case CallingConv::X86_FastCall:
3682 case CallingConv::X86_ThisCall:
3684 case CallingConv::Fast:
3685 case CallingConv::GHC:
3686 case CallingConv::HiPE:
3693 /// \brief Return true if the condition is an unsigned comparison operation.
3694 static bool isX86CCUnsigned(unsigned X86CC) {
3696 default: llvm_unreachable("Invalid integer condition!");
3697 case X86::COND_E: return true;
3698 case X86::COND_G: return false;
3699 case X86::COND_GE: return false;
3700 case X86::COND_L: return false;
3701 case X86::COND_LE: return false;
3702 case X86::COND_NE: return true;
3703 case X86::COND_B: return true;
3704 case X86::COND_A: return true;
3705 case X86::COND_BE: return true;
3706 case X86::COND_AE: return true;
3708 llvm_unreachable("covered switch fell through?!");
3711 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3712 /// specific condition code, returning the condition code and the LHS/RHS of the
3713 /// comparison to make.
3714 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3715 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3718 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3719 // X > -1 -> X == 0, jump !sign.
3720 RHS = DAG.getConstant(0, RHS.getValueType());
3721 return X86::COND_NS;
3723 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3724 // X < 0 -> X == 0, jump on sign.
3727 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3729 RHS = DAG.getConstant(0, RHS.getValueType());
3730 return X86::COND_LE;
3734 switch (SetCCOpcode) {
3735 default: llvm_unreachable("Invalid integer condition!");
3736 case ISD::SETEQ: return X86::COND_E;
3737 case ISD::SETGT: return X86::COND_G;
3738 case ISD::SETGE: return X86::COND_GE;
3739 case ISD::SETLT: return X86::COND_L;
3740 case ISD::SETLE: return X86::COND_LE;
3741 case ISD::SETNE: return X86::COND_NE;
3742 case ISD::SETULT: return X86::COND_B;
3743 case ISD::SETUGT: return X86::COND_A;
3744 case ISD::SETULE: return X86::COND_BE;
3745 case ISD::SETUGE: return X86::COND_AE;
3749 // First determine if it is required or is profitable to flip the operands.
3751 // If LHS is a foldable load, but RHS is not, flip the condition.
3752 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3753 !ISD::isNON_EXTLoad(RHS.getNode())) {
3754 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3755 std::swap(LHS, RHS);
3758 switch (SetCCOpcode) {
3764 std::swap(LHS, RHS);
3768 // On a floating point condition, the flags are set as follows:
3770 // 0 | 0 | 0 | X > Y
3771 // 0 | 0 | 1 | X < Y
3772 // 1 | 0 | 0 | X == Y
3773 // 1 | 1 | 1 | unordered
3774 switch (SetCCOpcode) {
3775 default: llvm_unreachable("Condcode should be pre-legalized away");
3777 case ISD::SETEQ: return X86::COND_E;
3778 case ISD::SETOLT: // flipped
3780 case ISD::SETGT: return X86::COND_A;
3781 case ISD::SETOLE: // flipped
3783 case ISD::SETGE: return X86::COND_AE;
3784 case ISD::SETUGT: // flipped
3786 case ISD::SETLT: return X86::COND_B;
3787 case ISD::SETUGE: // flipped
3789 case ISD::SETLE: return X86::COND_BE;
3791 case ISD::SETNE: return X86::COND_NE;
3792 case ISD::SETUO: return X86::COND_P;
3793 case ISD::SETO: return X86::COND_NP;
3795 case ISD::SETUNE: return X86::COND_INVALID;
3799 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3800 /// code. Current x86 isa includes the following FP cmov instructions:
3801 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3802 static bool hasFPCMov(unsigned X86CC) {
3818 /// isFPImmLegal - Returns true if the target can instruction select the
3819 /// specified FP immediate natively. If false, the legalizer will
3820 /// materialize the FP immediate as a load from a constant pool.
3821 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3822 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3823 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3829 /// \brief Returns true if it is beneficial to convert a load of a constant
3830 /// to just the constant itself.
3831 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3833 assert(Ty->isIntegerTy());
3835 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3836 if (BitSize == 0 || BitSize > 64)
3841 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3842 /// the specified range (L, H].
3843 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3844 return (Val < 0) || (Val >= Low && Val < Hi);
3847 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3848 /// specified value.
3849 static bool isUndefOrEqual(int Val, int CmpVal) {
3850 return (Val < 0 || Val == CmpVal);
3853 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3854 /// from position Pos and ending in Pos+Size, falls within the specified
3855 /// sequential range (L, L+Pos]. or is undef.
3856 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3857 unsigned Pos, unsigned Size, int Low) {
3858 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3859 if (!isUndefOrEqual(Mask[i], Low))
3864 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3865 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3866 /// the second operand.
3867 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3868 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3869 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3870 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3871 return (Mask[0] < 2 && Mask[1] < 2);
3875 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3876 /// is suitable for input to PSHUFHW.
3877 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3878 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3881 // Lower quadword copied in order or undef.
3882 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3885 // Upper quadword shuffled.
3886 for (unsigned i = 4; i != 8; ++i)
3887 if (!isUndefOrInRange(Mask[i], 4, 8))
3890 if (VT == MVT::v16i16) {
3891 // Lower quadword copied in order or undef.
3892 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3895 // Upper quadword shuffled.
3896 for (unsigned i = 12; i != 16; ++i)
3897 if (!isUndefOrInRange(Mask[i], 12, 16))
3904 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3905 /// is suitable for input to PSHUFLW.
3906 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3907 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3910 // Upper quadword copied in order.
3911 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3914 // Lower quadword shuffled.
3915 for (unsigned i = 0; i != 4; ++i)
3916 if (!isUndefOrInRange(Mask[i], 0, 4))
3919 if (VT == MVT::v16i16) {
3920 // Upper quadword copied in order.
3921 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3924 // Lower quadword shuffled.
3925 for (unsigned i = 8; i != 12; ++i)
3926 if (!isUndefOrInRange(Mask[i], 8, 12))
3933 /// \brief Return true if the mask specifies a shuffle of elements that is
3934 /// suitable for input to intralane (palignr) or interlane (valign) vector
3936 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3937 unsigned NumElts = VT.getVectorNumElements();
3938 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3939 unsigned NumLaneElts = NumElts/NumLanes;
3941 // Do not handle 64-bit element shuffles with palignr.
3942 if (NumLaneElts == 2)
3945 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3947 for (i = 0; i != NumLaneElts; ++i) {
3952 // Lane is all undef, go to next lane
3953 if (i == NumLaneElts)
3956 int Start = Mask[i+l];
3958 // Make sure its in this lane in one of the sources
3959 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3960 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3963 // If not lane 0, then we must match lane 0
3964 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3967 // Correct second source to be contiguous with first source
3968 if (Start >= (int)NumElts)
3969 Start -= NumElts - NumLaneElts;
3971 // Make sure we're shifting in the right direction.
3972 if (Start <= (int)(i+l))
3977 // Check the rest of the elements to see if they are consecutive.
3978 for (++i; i != NumLaneElts; ++i) {
3979 int Idx = Mask[i+l];
3981 // Make sure its in this lane
3982 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3983 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3986 // If not lane 0, then we must match lane 0
3987 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3990 if (Idx >= (int)NumElts)
3991 Idx -= NumElts - NumLaneElts;
3993 if (!isUndefOrEqual(Idx, Start+i))
4002 /// \brief Return true if the node specifies a shuffle of elements that is
4003 /// suitable for input to PALIGNR.
4004 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4005 const X86Subtarget *Subtarget) {
4006 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4007 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4008 VT.is512BitVector())
4009 // FIXME: Add AVX512BW.
4012 return isAlignrMask(Mask, VT, false);
4015 /// \brief Return true if the node specifies a shuffle of elements that is
4016 /// suitable for input to VALIGN.
4017 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4018 const X86Subtarget *Subtarget) {
4019 // FIXME: Add AVX512VL.
4020 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4022 return isAlignrMask(Mask, VT, true);
4025 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4026 /// the two vector operands have swapped position.
4027 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4028 unsigned NumElems) {
4029 for (unsigned i = 0; i != NumElems; ++i) {
4033 else if (idx < (int)NumElems)
4034 Mask[i] = idx + NumElems;
4036 Mask[i] = idx - NumElems;
4040 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4041 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4042 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4043 /// reverse of what x86 shuffles want.
4044 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4046 unsigned NumElems = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElems = NumElems/NumLanes;
4050 if (NumLaneElems != 2 && NumLaneElems != 4)
4053 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4054 bool symetricMaskRequired =
4055 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4057 // VSHUFPSY divides the resulting vector into 4 chunks.
4058 // The sources are also splitted into 4 chunks, and each destination
4059 // chunk must come from a different source chunk.
4061 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4062 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4064 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4065 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4067 // VSHUFPDY divides the resulting vector into 4 chunks.
4068 // The sources are also splitted into 4 chunks, and each destination
4069 // chunk must come from a different source chunk.
4071 // SRC1 => X3 X2 X1 X0
4072 // SRC2 => Y3 Y2 Y1 Y0
4074 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4076 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4077 unsigned HalfLaneElems = NumLaneElems/2;
4078 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4079 for (unsigned i = 0; i != NumLaneElems; ++i) {
4080 int Idx = Mask[i+l];
4081 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4082 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4084 // For VSHUFPSY, the mask of the second half must be the same as the
4085 // first but with the appropriate offsets. This works in the same way as
4086 // VPERMILPS works with masks.
4087 if (!symetricMaskRequired || Idx < 0)
4089 if (MaskVal[i] < 0) {
4090 MaskVal[i] = Idx - l;
4093 if ((signed)(Idx - l) != MaskVal[i])
4101 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4102 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4103 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4104 if (!VT.is128BitVector())
4107 unsigned NumElems = VT.getVectorNumElements();
4112 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4113 return isUndefOrEqual(Mask[0], 6) &&
4114 isUndefOrEqual(Mask[1], 7) &&
4115 isUndefOrEqual(Mask[2], 2) &&
4116 isUndefOrEqual(Mask[3], 3);
4119 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4120 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4122 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4123 if (!VT.is128BitVector())
4126 unsigned NumElems = VT.getVectorNumElements();
4131 return isUndefOrEqual(Mask[0], 2) &&
4132 isUndefOrEqual(Mask[1], 3) &&
4133 isUndefOrEqual(Mask[2], 2) &&
4134 isUndefOrEqual(Mask[3], 3);
4137 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4138 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4139 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4145 if (NumElems != 2 && NumElems != 4)
4148 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4149 if (!isUndefOrEqual(Mask[i], i + NumElems))
4152 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i))
4159 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4161 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4162 if (!VT.is128BitVector())
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4170 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4171 if (!isUndefOrEqual(Mask[i], i))
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4181 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4182 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4183 /// i. e: If all but one element come from the same vector.
4184 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4185 // TODO: Deal with AVX's VINSERTPS
4186 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4189 unsigned CorrectPosV1 = 0;
4190 unsigned CorrectPosV2 = 0;
4191 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4192 if (Mask[i] == -1) {
4200 else if (Mask[i] == i + 4)
4204 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4205 // We have 3 elements (undefs count as elements from any vector) from one
4206 // vector, and one from another.
4213 // Some special combinations that can be optimized.
4216 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4217 SelectionDAG &DAG) {
4218 MVT VT = SVOp->getSimpleValueType(0);
4221 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4224 ArrayRef<int> Mask = SVOp->getMask();
4226 // These are the special masks that may be optimized.
4227 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4228 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4229 bool MatchEvenMask = true;
4230 bool MatchOddMask = true;
4231 for (int i=0; i<8; ++i) {
4232 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4233 MatchEvenMask = false;
4234 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4235 MatchOddMask = false;
4238 if (!MatchEvenMask && !MatchOddMask)
4241 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4243 SDValue Op0 = SVOp->getOperand(0);
4244 SDValue Op1 = SVOp->getOperand(1);
4246 if (MatchEvenMask) {
4247 // Shift the second operand right to 32 bits.
4248 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4249 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4251 // Shift the first operand left to 32 bits.
4252 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4253 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4255 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4256 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4259 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4260 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4261 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4262 bool HasInt256, bool V2IsSplat = false) {
4264 assert(VT.getSizeInBits() >= 128 &&
4265 "Unsupported vector type for unpckl");
4267 unsigned NumElts = VT.getVectorNumElements();
4268 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4269 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4272 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4273 "Unsupported vector type for unpckh");
4275 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4276 unsigned NumLanes = VT.getSizeInBits()/128;
4277 unsigned NumLaneElts = NumElts/NumLanes;
4279 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4280 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4281 int BitI = Mask[l+i];
4282 int BitI1 = Mask[l+i+1];
4283 if (!isUndefOrEqual(BitI, j))
4286 if (!isUndefOrEqual(BitI1, NumElts))
4289 if (!isUndefOrEqual(BitI1, j + NumElts))
4298 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4300 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4301 bool HasInt256, bool V2IsSplat = false) {
4302 assert(VT.getSizeInBits() >= 128 &&
4303 "Unsupported vector type for unpckh");
4305 unsigned NumElts = VT.getVectorNumElements();
4306 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4307 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4310 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4311 "Unsupported vector type for unpckh");
4313 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4314 unsigned NumLanes = VT.getSizeInBits()/128;
4315 unsigned NumLaneElts = NumElts/NumLanes;
4317 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4318 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4319 int BitI = Mask[l+i];
4320 int BitI1 = Mask[l+i+1];
4321 if (!isUndefOrEqual(BitI, j))
4324 if (isUndefOrEqual(BitI1, NumElts))
4327 if (!isUndefOrEqual(BitI1, j+NumElts))
4335 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4336 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4338 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4339 unsigned NumElts = VT.getVectorNumElements();
4340 bool Is256BitVec = VT.is256BitVector();
4342 if (VT.is512BitVector())
4344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4345 "Unsupported vector type for unpckh");
4347 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4348 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4351 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4352 // FIXME: Need a better way to get rid of this, there's no latency difference
4353 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4354 // the former later. We should also remove the "_undef" special mask.
4355 if (NumElts == 4 && Is256BitVec)
4358 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4359 // independently on 128-bit lanes.
4360 unsigned NumLanes = VT.getSizeInBits()/128;
4361 unsigned NumLaneElts = NumElts/NumLanes;
4363 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4364 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4365 int BitI = Mask[l+i];
4366 int BitI1 = Mask[l+i+1];
4368 if (!isUndefOrEqual(BitI, j))
4370 if (!isUndefOrEqual(BitI1, j))
4378 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4379 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4381 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4382 unsigned NumElts = VT.getVectorNumElements();
4384 if (VT.is512BitVector())
4387 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4388 "Unsupported vector type for unpckh");
4390 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4391 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4394 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4395 // independently on 128-bit lanes.
4396 unsigned NumLanes = VT.getSizeInBits()/128;
4397 unsigned NumLaneElts = NumElts/NumLanes;
4399 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4400 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4401 int BitI = Mask[l+i];
4402 int BitI1 = Mask[l+i+1];
4403 if (!isUndefOrEqual(BitI, j))
4405 if (!isUndefOrEqual(BitI1, j))
4412 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4413 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4414 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4415 if (!VT.is512BitVector())
4418 unsigned NumElts = VT.getVectorNumElements();
4419 unsigned HalfSize = NumElts/2;
4420 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4421 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4435 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4436 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4437 /// MOVSD, and MOVD, i.e. setting the lowest element.
4438 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4439 if (VT.getVectorElementType().getSizeInBits() < 32)
4441 if (!VT.is128BitVector())
4444 unsigned NumElts = VT.getVectorNumElements();
4446 if (!isUndefOrEqual(Mask[0], NumElts))
4449 for (unsigned i = 1; i != NumElts; ++i)
4450 if (!isUndefOrEqual(Mask[i], i))
4456 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4457 /// as permutations between 128-bit chunks or halves. As an example: this
4459 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4460 /// The first half comes from the second half of V1 and the second half from the
4461 /// the second half of V2.
4462 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4463 if (!HasFp256 || !VT.is256BitVector())
4466 // The shuffle result is divided into half A and half B. In total the two
4467 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4468 // B must come from C, D, E or F.
4469 unsigned HalfSize = VT.getVectorNumElements()/2;
4470 bool MatchA = false, MatchB = false;
4472 // Check if A comes from one of C, D, E, F.
4473 for (unsigned Half = 0; Half != 4; ++Half) {
4474 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4480 // Check if B comes from one of C, D, E, F.
4481 for (unsigned Half = 0; Half != 4; ++Half) {
4482 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4488 return MatchA && MatchB;
4491 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4492 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4493 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4494 MVT VT = SVOp->getSimpleValueType(0);
4496 unsigned HalfSize = VT.getVectorNumElements()/2;
4498 unsigned FstHalf = 0, SndHalf = 0;
4499 for (unsigned i = 0; i < HalfSize; ++i) {
4500 if (SVOp->getMaskElt(i) > 0) {
4501 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4505 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4512 return (FstHalf | (SndHalf << 4));
4515 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4516 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4521 unsigned NumElts = VT.getVectorNumElements();
4523 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4524 for (unsigned i = 0; i != NumElts; ++i) {
4527 Imm8 |= Mask[i] << (i*2);
4532 unsigned LaneSize = 4;
4533 SmallVector<int, 4> MaskVal(LaneSize, -1);
4535 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4536 for (unsigned i = 0; i != LaneSize; ++i) {
4537 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4541 if (MaskVal[i] < 0) {
4542 MaskVal[i] = Mask[i+l] - l;
4543 Imm8 |= MaskVal[i] << (i*2);
4546 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4553 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4554 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4555 /// Note that VPERMIL mask matching is different depending whether theunderlying
4556 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4557 /// to the same elements of the low, but to the higher half of the source.
4558 /// In VPERMILPD the two lanes could be shuffled independently of each other
4559 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4560 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4561 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4562 if (VT.getSizeInBits() < 256 || EltSize < 32)
4564 bool symetricMaskRequired = (EltSize == 32);
4565 unsigned NumElts = VT.getVectorNumElements();
4567 unsigned NumLanes = VT.getSizeInBits()/128;
4568 unsigned LaneSize = NumElts/NumLanes;
4569 // 2 or 4 elements in one lane
4571 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4572 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4573 for (unsigned i = 0; i != LaneSize; ++i) {
4574 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4576 if (symetricMaskRequired) {
4577 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4578 ExpectedMaskVal[i] = Mask[i+l] - l;
4581 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4589 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4590 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4591 /// element of vector 2 and the other elements to come from vector 1 in order.
4592 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4593 bool V2IsSplat = false, bool V2IsUndef = false) {
4594 if (!VT.is128BitVector())
4597 unsigned NumOps = VT.getVectorNumElements();
4598 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4601 if (!isUndefOrEqual(Mask[0], 0))
4604 for (unsigned i = 1; i != NumOps; ++i)
4605 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4606 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4607 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4613 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4614 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4615 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4616 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4617 const X86Subtarget *Subtarget) {
4618 if (!Subtarget->hasSSE3())
4621 unsigned NumElems = VT.getVectorNumElements();
4623 if ((VT.is128BitVector() && NumElems != 4) ||
4624 (VT.is256BitVector() && NumElems != 8) ||
4625 (VT.is512BitVector() && NumElems != 16))
4628 // "i+1" is the value the indexed mask element must have
4629 for (unsigned i = 0; i != NumElems; i += 2)
4630 if (!isUndefOrEqual(Mask[i], i+1) ||
4631 !isUndefOrEqual(Mask[i+1], i+1))
4637 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4638 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4639 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4640 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4641 const X86Subtarget *Subtarget) {
4642 if (!Subtarget->hasSSE3())
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if ((VT.is128BitVector() && NumElems != 4) ||
4648 (VT.is256BitVector() && NumElems != 8) ||
4649 (VT.is512BitVector() && NumElems != 16))
4652 // "i" is the value the indexed mask element must have
4653 for (unsigned i = 0; i != NumElems; i += 2)
4654 if (!isUndefOrEqual(Mask[i], i) ||
4655 !isUndefOrEqual(Mask[i+1], i))
4661 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4662 /// specifies a shuffle of elements that is suitable for input to 256-bit
4663 /// version of MOVDDUP.
4664 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4665 if (!HasFp256 || !VT.is256BitVector())
4668 unsigned NumElts = VT.getVectorNumElements();
4672 for (unsigned i = 0; i != NumElts/2; ++i)
4673 if (!isUndefOrEqual(Mask[i], 0))
4675 for (unsigned i = NumElts/2; i != NumElts; ++i)
4676 if (!isUndefOrEqual(Mask[i], NumElts/2))
4681 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4682 /// specifies a shuffle of elements that is suitable for input to 128-bit
4683 /// version of MOVDDUP.
4684 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 unsigned e = VT.getVectorNumElements() / 2;
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[i], i))
4692 for (unsigned i = 0; i != e; ++i)
4693 if (!isUndefOrEqual(Mask[e+i], i))
4698 /// isVEXTRACTIndex - Return true if the specified
4699 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4700 /// suitable for instruction that extract 128 or 256 bit vectors
4701 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4702 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4703 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4706 // The index should be aligned on a vecWidth-bit boundary.
4708 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4710 MVT VT = N->getSimpleValueType(0);
4711 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4712 bool Result = (Index * ElSize) % vecWidth == 0;
4717 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4718 /// operand specifies a subvector insert that is suitable for input to
4719 /// insertion of 128 or 256-bit subvectors
4720 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4721 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4722 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4724 // The index should be aligned on a vecWidth-bit boundary.
4726 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4728 MVT VT = N->getSimpleValueType(0);
4729 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4730 bool Result = (Index * ElSize) % vecWidth == 0;
4735 bool X86::isVINSERT128Index(SDNode *N) {
4736 return isVINSERTIndex(N, 128);
4739 bool X86::isVINSERT256Index(SDNode *N) {
4740 return isVINSERTIndex(N, 256);
4743 bool X86::isVEXTRACT128Index(SDNode *N) {
4744 return isVEXTRACTIndex(N, 128);
4747 bool X86::isVEXTRACT256Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 256);
4751 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4752 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4753 /// Handles 128-bit and 256-bit.
4754 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4755 MVT VT = N->getSimpleValueType(0);
4757 assert((VT.getSizeInBits() >= 128) &&
4758 "Unsupported vector type for PSHUF/SHUFP");
4760 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4761 // independently on 128-bit lanes.
4762 unsigned NumElts = VT.getVectorNumElements();
4763 unsigned NumLanes = VT.getSizeInBits()/128;
4764 unsigned NumLaneElts = NumElts/NumLanes;
4766 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4767 "Only supports 2, 4 or 8 elements per lane");
4769 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4771 for (unsigned i = 0; i != NumElts; ++i) {
4772 int Elt = N->getMaskElt(i);
4773 if (Elt < 0) continue;
4774 Elt &= NumLaneElts - 1;
4775 unsigned ShAmt = (i << Shift) % 8;
4776 Mask |= Elt << ShAmt;
4782 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4783 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4784 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4785 MVT VT = N->getSimpleValueType(0);
4787 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4788 "Unsupported vector type for PSHUFHW");
4790 unsigned NumElts = VT.getVectorNumElements();
4793 for (unsigned l = 0; l != NumElts; l += 8) {
4794 // 8 nodes per lane, but we only care about the last 4.
4795 for (unsigned i = 0; i < 4; ++i) {
4796 int Elt = N->getMaskElt(l+i+4);
4797 if (Elt < 0) continue;
4798 Elt &= 0x3; // only 2-bits.
4799 Mask |= Elt << (i * 2);
4806 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4807 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4808 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4809 MVT VT = N->getSimpleValueType(0);
4811 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4812 "Unsupported vector type for PSHUFHW");
4814 unsigned NumElts = VT.getVectorNumElements();
4817 for (unsigned l = 0; l != NumElts; l += 8) {
4818 // 8 nodes per lane, but we only care about the first 4.
4819 for (unsigned i = 0; i < 4; ++i) {
4820 int Elt = N->getMaskElt(l+i);
4821 if (Elt < 0) continue;
4822 Elt &= 0x3; // only 2-bits
4823 Mask |= Elt << (i * 2);
4830 /// \brief Return the appropriate immediate to shuffle the specified
4831 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4832 /// VALIGN (if Interlane is true) instructions.
4833 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4835 MVT VT = SVOp->getSimpleValueType(0);
4836 unsigned EltSize = InterLane ? 1 :
4837 VT.getVectorElementType().getSizeInBits() >> 3;
4839 unsigned NumElts = VT.getVectorNumElements();
4840 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4841 unsigned NumLaneElts = NumElts/NumLanes;
4845 for (i = 0; i != NumElts; ++i) {
4846 Val = SVOp->getMaskElt(i);
4850 if (Val >= (int)NumElts)
4851 Val -= NumElts - NumLaneElts;
4853 assert(Val - i > 0 && "PALIGNR imm should be positive");
4854 return (Val - i) * EltSize;
4857 /// \brief Return the appropriate immediate to shuffle the specified
4858 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4859 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4860 return getShuffleAlignrImmediate(SVOp, false);
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4865 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, true);
4870 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4871 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4872 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4873 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4876 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4878 MVT VecVT = N->getOperand(0).getSimpleValueType();
4879 MVT ElVT = VecVT.getVectorElementType();
4881 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4882 return Index / NumElemsPerChunk;
4885 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4886 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4887 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4888 llvm_unreachable("Illegal insert subvector for VINSERT");
4891 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4893 MVT VecVT = N->getSimpleValueType(0);
4894 MVT ElVT = VecVT.getVectorElementType();
4896 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4897 return Index / NumElemsPerChunk;
4900 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4901 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4902 /// and VINSERTI128 instructions.
4903 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4904 return getExtractVEXTRACTImmediate(N, 128);
4907 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4909 /// and VINSERTI64x4 instructions.
4910 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 256);
4914 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4915 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4918 return getInsertVINSERTImmediate(N, 128);
4921 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 256);
4928 /// isZero - Returns true if Elt is a constant integer zero
4929 static bool isZero(SDValue V) {
4930 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4931 return C && C->isNullValue();
4934 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4936 bool X86::isZeroNode(SDValue Elt) {
4939 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4940 return CFP->getValueAPF().isPosZero();
4944 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4945 /// match movhlps. The lower half elements should come from upper half of
4946 /// V1 (and in order), and the upper half elements should come from the upper
4947 /// half of V2 (and in order).
4948 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4949 if (!VT.is128BitVector())
4951 if (VT.getVectorNumElements() != 4)
4953 for (unsigned i = 0, e = 2; i != e; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+2))
4956 for (unsigned i = 2; i != 4; ++i)
4957 if (!isUndefOrEqual(Mask[i], i+4))
4962 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4963 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4965 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4966 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4968 N = N->getOperand(0).getNode();
4969 if (!ISD::isNON_EXTLoad(N))
4972 *LD = cast<LoadSDNode>(N);
4976 // Test whether the given value is a vector value which will be legalized
4978 static bool WillBeConstantPoolLoad(SDNode *N) {
4979 if (N->getOpcode() != ISD::BUILD_VECTOR)
4982 // Check for any non-constant elements.
4983 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4984 switch (N->getOperand(i).getNode()->getOpcode()) {
4986 case ISD::ConstantFP:
4993 // Vectors of all-zeros and all-ones are materialized with special
4994 // instructions rather than being loaded.
4995 return !ISD::isBuildVectorAllZeros(N) &&
4996 !ISD::isBuildVectorAllOnes(N);
4999 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5000 /// match movlp{s|d}. The lower half elements should come from lower half of
5001 /// V1 (and in order), and the upper half elements should come from the upper
5002 /// half of V2 (and in order). And since V1 will become the source of the
5003 /// MOVLP, it must be either a vector load or a scalar load to vector.
5004 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5005 ArrayRef<int> Mask, MVT VT) {
5006 if (!VT.is128BitVector())
5009 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5011 // Is V2 is a vector load, don't do this transformation. We will try to use
5012 // load folding shufps op.
5013 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5016 unsigned NumElems = VT.getVectorNumElements();
5018 if (NumElems != 2 && NumElems != 4)
5020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i))
5023 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5024 if (!isUndefOrEqual(Mask[i], i+NumElems))
5029 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5030 /// to an zero vector.
5031 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5032 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5033 SDValue V1 = N->getOperand(0);
5034 SDValue V2 = N->getOperand(1);
5035 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5036 for (unsigned i = 0; i != NumElems; ++i) {
5037 int Idx = N->getMaskElt(i);
5038 if (Idx >= (int)NumElems) {
5039 unsigned Opc = V2.getOpcode();
5040 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5042 if (Opc != ISD::BUILD_VECTOR ||
5043 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5045 } else if (Idx >= 0) {
5046 unsigned Opc = V1.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V1.getOperand(Idx)))
5057 /// getZeroVector - Returns a vector of specified type with all zero elements.
5059 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5060 SelectionDAG &DAG, SDLoc dl) {
5061 assert(VT.isVector() && "Expected a vector type");
5063 // Always build SSE zero vectors as <4 x i32> bitcasted
5064 // to their dest type. This ensures they get CSE'd.
5066 if (VT.is128BitVector()) { // SSE
5067 if (Subtarget->hasSSE2()) { // SSE2
5068 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5071 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5072 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5074 } else if (VT.is256BitVector()) { // AVX
5075 if (Subtarget->hasInt256()) { // AVX2
5076 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5077 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5080 // 256-bit logic and arithmetic instructions in AVX are all
5081 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5082 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5086 } else if (VT.is512BitVector()) { // AVX-512
5087 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5088 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5089 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5091 } else if (VT.getScalarType() == MVT::i1) {
5092 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5093 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5094 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5095 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5097 llvm_unreachable("Unexpected vector type");
5099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5102 /// getOnesVector - Returns a vector of specified type with all bits set.
5103 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5104 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5105 /// Then bitcast to their original type, ensuring they get CSE'd.
5106 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5108 assert(VT.isVector() && "Expected a vector type");
5110 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5112 if (VT.is256BitVector()) {
5113 if (HasInt256) { // AVX2
5114 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5115 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5118 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5120 } else if (VT.is128BitVector()) {
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5123 llvm_unreachable("Unexpected vector type");
5125 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5128 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5129 /// that point to V2 points to its first element.
5130 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5131 for (unsigned i = 0; i != NumElems; ++i) {
5132 if (Mask[i] > (int)NumElems) {
5138 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5139 /// operation of specified width.
5140 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5142 unsigned NumElems = VT.getVectorNumElements();
5143 SmallVector<int, 8> Mask;
5144 Mask.push_back(NumElems);
5145 for (unsigned i = 1; i != NumElems; ++i)
5147 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5150 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5151 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5153 unsigned NumElems = VT.getVectorNumElements();
5154 SmallVector<int, 8> Mask;
5155 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5157 Mask.push_back(i + NumElems);
5159 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5162 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5163 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5165 unsigned NumElems = VT.getVectorNumElements();
5166 SmallVector<int, 8> Mask;
5167 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5168 Mask.push_back(i + Half);
5169 Mask.push_back(i + NumElems + Half);
5171 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5174 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5175 // a generic shuffle instruction because the target has no such instructions.
5176 // Generate shuffles which repeat i16 and i8 several times until they can be
5177 // represented by v4f32 and then be manipulated by target suported shuffles.
5178 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5179 MVT VT = V.getSimpleValueType();
5180 int NumElems = VT.getVectorNumElements();
5183 while (NumElems > 4) {
5184 if (EltNo < NumElems/2) {
5185 V = getUnpackl(DAG, dl, VT, V, V);
5187 V = getUnpackh(DAG, dl, VT, V, V);
5188 EltNo -= NumElems/2;
5195 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5196 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5197 MVT VT = V.getSimpleValueType();
5200 if (VT.is128BitVector()) {
5201 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5202 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5203 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5205 } else if (VT.is256BitVector()) {
5206 // To use VPERMILPS to splat scalars, the second half of indicies must
5207 // refer to the higher part, which is a duplication of the lower one,
5208 // because VPERMILPS can only handle in-lane permutations.
5209 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5210 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5212 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5213 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5216 llvm_unreachable("Vector size not supported");
5218 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5221 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5222 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5223 MVT SrcVT = SV->getSimpleValueType(0);
5224 SDValue V1 = SV->getOperand(0);
5227 int EltNo = SV->getSplatIndex();
5228 int NumElems = SrcVT.getVectorNumElements();
5229 bool Is256BitVec = SrcVT.is256BitVector();
5231 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5232 "Unknown how to promote splat for type");
5234 // Extract the 128-bit part containing the splat element and update
5235 // the splat element index when it refers to the higher register.
5237 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5238 if (EltNo >= NumElems/2)
5239 EltNo -= NumElems/2;
5242 // All i16 and i8 vector types can't be used directly by a generic shuffle
5243 // instruction because the target has no such instruction. Generate shuffles
5244 // which repeat i16 and i8 several times until they fit in i32, and then can
5245 // be manipulated by target suported shuffles.
5246 MVT EltVT = SrcVT.getVectorElementType();
5247 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5248 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5250 // Recreate the 256-bit vector and place the same 128-bit vector
5251 // into the low and high part. This is necessary because we want
5252 // to use VPERM* to shuffle the vectors
5254 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5257 return getLegalSplat(DAG, V1, EltNo);
5260 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5261 /// vector of zero or undef vector. This produces a shuffle where the low
5262 /// element of V2 is swizzled into the zero/undef vector, landing at element
5263 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5264 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5266 const X86Subtarget *Subtarget,
5267 SelectionDAG &DAG) {
5268 MVT VT = V2.getSimpleValueType();
5270 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5271 unsigned NumElems = VT.getVectorNumElements();
5272 SmallVector<int, 16> MaskVec;
5273 for (unsigned i = 0; i != NumElems; ++i)
5274 // If this is the insertion idx, put the low elt of V2 here.
5275 MaskVec.push_back(i == Idx ? NumElems : i);
5276 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5279 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5280 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5281 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5282 /// shuffles which use a single input multiple times, and in those cases it will
5283 /// adjust the mask to only have indices within that single input.
5284 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5285 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5286 unsigned NumElems = VT.getVectorNumElements();
5290 bool IsFakeUnary = false;
5291 switch(N->getOpcode()) {
5292 case X86ISD::BLENDI:
5293 ImmN = N->getOperand(N->getNumOperands()-1);
5294 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5299 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5301 case X86ISD::UNPCKH:
5302 DecodeUNPCKHMask(VT, Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKL:
5306 DecodeUNPCKLMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::MOVHLPS:
5310 DecodeMOVHLPSMask(NumElems, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVLHPS:
5314 DecodeMOVLHPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::PALIGNR:
5318 ImmN = N->getOperand(N->getNumOperands()-1);
5319 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5321 case X86ISD::PSHUFD:
5322 case X86ISD::VPERMILPI:
5323 ImmN = N->getOperand(N->getNumOperands()-1);
5324 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFHW:
5328 ImmN = N->getOperand(N->getNumOperands()-1);
5329 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5332 case X86ISD::PSHUFLW:
5333 ImmN = N->getOperand(N->getNumOperands()-1);
5334 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5337 case X86ISD::PSHUFB: {
5339 SDValue MaskNode = N->getOperand(1);
5340 while (MaskNode->getOpcode() == ISD::BITCAST)
5341 MaskNode = MaskNode->getOperand(0);
5343 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5344 // If we have a build-vector, then things are easy.
5345 EVT VT = MaskNode.getValueType();
5346 assert(VT.isVector() &&
5347 "Can't produce a non-vector with a build_vector!");
5348 if (!VT.isInteger())
5351 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5353 SmallVector<uint64_t, 32> RawMask;
5354 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5355 SDValue Op = MaskNode->getOperand(i);
5356 if (Op->getOpcode() == ISD::UNDEF) {
5357 RawMask.push_back((uint64_t)SM_SentinelUndef);
5360 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5363 APInt MaskElement = CN->getAPIntValue();
5365 // We now have to decode the element which could be any integer size and
5366 // extract each byte of it.
5367 for (int j = 0; j < NumBytesPerElement; ++j) {
5368 // Note that this is x86 and so always little endian: the low byte is
5369 // the first byte of the mask.
5370 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5371 MaskElement = MaskElement.lshr(8);
5374 DecodePSHUFBMask(RawMask, Mask);
5378 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5382 SDValue Ptr = MaskLoad->getBasePtr();
5383 if (Ptr->getOpcode() == X86ISD::Wrapper)
5384 Ptr = Ptr->getOperand(0);
5386 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5387 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5390 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5391 // FIXME: Support AVX-512 here.
5392 Type *Ty = C->getType();
5393 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5394 Ty->getVectorNumElements() != 32))
5397 DecodePSHUFBMask(C, Mask);
5403 case X86ISD::VPERMI:
5404 ImmN = N->getOperand(N->getNumOperands()-1);
5405 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5409 case X86ISD::MOVSD: {
5410 // The index 0 always comes from the first element of the second source,
5411 // this is why MOVSS and MOVSD are used in the first place. The other
5412 // elements come from the other positions of the first source vector
5413 Mask.push_back(NumElems);
5414 for (unsigned i = 1; i != NumElems; ++i) {
5419 case X86ISD::VPERM2X128:
5420 ImmN = N->getOperand(N->getNumOperands()-1);
5421 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5422 if (Mask.empty()) return false;
5424 case X86ISD::MOVSLDUP:
5425 DecodeMOVSLDUPMask(VT, Mask);
5427 case X86ISD::MOVSHDUP:
5428 DecodeMOVSHDUPMask(VT, Mask);
5430 case X86ISD::MOVDDUP:
5431 case X86ISD::MOVLHPD:
5432 case X86ISD::MOVLPD:
5433 case X86ISD::MOVLPS:
5434 // Not yet implemented
5436 default: llvm_unreachable("unknown target shuffle node");
5439 // If we have a fake unary shuffle, the shuffle mask is spread across two
5440 // inputs that are actually the same node. Re-map the mask to always point
5441 // into the first input.
5444 if (M >= (int)Mask.size())
5450 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5451 /// element of the result of the vector shuffle.
5452 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5455 return SDValue(); // Limit search depth.
5457 SDValue V = SDValue(N, 0);
5458 EVT VT = V.getValueType();
5459 unsigned Opcode = V.getOpcode();
5461 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5462 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5463 int Elt = SV->getMaskElt(Index);
5466 return DAG.getUNDEF(VT.getVectorElementType());
5468 unsigned NumElems = VT.getVectorNumElements();
5469 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5470 : SV->getOperand(1);
5471 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5474 // Recurse into target specific vector shuffles to find scalars.
5475 if (isTargetShuffle(Opcode)) {
5476 MVT ShufVT = V.getSimpleValueType();
5477 unsigned NumElems = ShufVT.getVectorNumElements();
5478 SmallVector<int, 16> ShuffleMask;
5481 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5484 int Elt = ShuffleMask[Index];
5486 return DAG.getUNDEF(ShufVT.getVectorElementType());
5488 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5490 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5494 // Actual nodes that may contain scalar elements
5495 if (Opcode == ISD::BITCAST) {
5496 V = V.getOperand(0);
5497 EVT SrcVT = V.getValueType();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5504 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5505 return (Index == 0) ? V.getOperand(0)
5506 : DAG.getUNDEF(VT.getVectorElementType());
5508 if (V.getOpcode() == ISD::BUILD_VECTOR)
5509 return V.getOperand(Index);
5514 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5515 /// shuffle operation which come from a consecutively from a zero. The
5516 /// search can start in two different directions, from left or right.
5517 /// We count undefs as zeros until PreferredNum is reached.
5518 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5519 unsigned NumElems, bool ZerosFromLeft,
5521 unsigned PreferredNum = -1U) {
5522 unsigned NumZeros = 0;
5523 for (unsigned i = 0; i != NumElems; ++i) {
5524 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5525 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5529 if (X86::isZeroNode(Elt))
5531 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5532 NumZeros = std::min(NumZeros + 1, PreferredNum);
5540 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5541 /// correspond consecutively to elements from one of the vector operands,
5542 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5544 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5545 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5546 unsigned NumElems, unsigned &OpNum) {
5547 bool SeenV1 = false;
5548 bool SeenV2 = false;
5550 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5551 int Idx = SVOp->getMaskElt(i);
5552 // Ignore undef indicies
5556 if (Idx < (int)NumElems)
5561 // Only accept consecutive elements from the same vector
5562 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5566 OpNum = SeenV1 ? 0 : 1;
5570 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5571 /// logical left shift of a vector.
5572 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5573 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5575 SVOp->getSimpleValueType(0).getVectorNumElements();
5576 unsigned NumZeros = getNumOfConsecutiveZeros(
5577 SVOp, NumElems, false /* check zeros from right */, DAG,
5578 SVOp->getMaskElt(0));
5584 // Considering the elements in the mask that are not consecutive zeros,
5585 // check if they consecutively come from only one of the source vectors.
5587 // V1 = {X, A, B, C} 0
5589 // vector_shuffle V1, V2 <1, 2, 3, X>
5591 if (!isShuffleMaskConsecutive(SVOp,
5592 0, // Mask Start Index
5593 NumElems-NumZeros, // Mask End Index(exclusive)
5594 NumZeros, // Where to start looking in the src vector
5595 NumElems, // Number of elements in vector
5596 OpSrc)) // Which source operand ?
5601 ShVal = SVOp->getOperand(OpSrc);
5605 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5606 /// logical left shift of a vector.
5607 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5608 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5610 SVOp->getSimpleValueType(0).getVectorNumElements();
5611 unsigned NumZeros = getNumOfConsecutiveZeros(
5612 SVOp, NumElems, true /* check zeros from left */, DAG,
5613 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5619 // Considering the elements in the mask that are not consecutive zeros,
5620 // check if they consecutively come from only one of the source vectors.
5622 // 0 { A, B, X, X } = V2
5624 // vector_shuffle V1, V2 <X, X, 4, 5>
5626 if (!isShuffleMaskConsecutive(SVOp,
5627 NumZeros, // Mask Start Index
5628 NumElems, // Mask End Index(exclusive)
5629 0, // Where to start looking in the src vector
5630 NumElems, // Number of elements in vector
5631 OpSrc)) // Which source operand ?
5636 ShVal = SVOp->getOperand(OpSrc);
5640 /// isVectorShift - Returns true if the shuffle can be implemented as a
5641 /// logical left or right shift of a vector.
5642 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5644 // Although the logic below support any bitwidth size, there are no
5645 // shift instructions which handle more than 128-bit vectors.
5646 if (!SVOp->getSimpleValueType(0).is128BitVector())
5649 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5650 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5656 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5658 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5659 unsigned NumNonZero, unsigned NumZero,
5661 const X86Subtarget* Subtarget,
5662 const TargetLowering &TLI) {
5669 for (unsigned i = 0; i < 16; ++i) {
5670 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5671 if (ThisIsNonZero && First) {
5673 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5675 V = DAG.getUNDEF(MVT::v8i16);
5680 SDValue ThisElt, LastElt;
5681 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5682 if (LastIsNonZero) {
5683 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5684 MVT::i16, Op.getOperand(i-1));
5686 if (ThisIsNonZero) {
5687 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5688 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5689 ThisElt, DAG.getConstant(8, MVT::i8));
5691 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5695 if (ThisElt.getNode())
5696 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5697 DAG.getIntPtrConstant(i/2));
5701 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5704 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5706 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5707 unsigned NumNonZero, unsigned NumZero,
5709 const X86Subtarget* Subtarget,
5710 const TargetLowering &TLI) {
5717 for (unsigned i = 0; i < 8; ++i) {
5718 bool isNonZero = (NonZeros & (1 << i)) != 0;
5722 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5724 V = DAG.getUNDEF(MVT::v8i16);
5727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5728 MVT::v8i16, V, Op.getOperand(i),
5729 DAG.getIntPtrConstant(i));
5736 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5737 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5738 unsigned NonZeros, unsigned NumNonZero,
5739 unsigned NumZero, SelectionDAG &DAG,
5740 const X86Subtarget *Subtarget,
5741 const TargetLowering &TLI) {
5742 // We know there's at least one non-zero element
5743 unsigned FirstNonZeroIdx = 0;
5744 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5745 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5746 X86::isZeroNode(FirstNonZero)) {
5748 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5752 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5755 SDValue V = FirstNonZero.getOperand(0);
5756 MVT VVT = V.getSimpleValueType();
5757 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5760 unsigned FirstNonZeroDst =
5761 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5762 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5763 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5764 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5766 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5767 SDValue Elem = Op.getOperand(Idx);
5768 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5771 // TODO: What else can be here? Deal with it.
5772 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5775 // TODO: Some optimizations are still possible here
5776 // ex: Getting one element from a vector, and the rest from another.
5777 if (Elem.getOperand(0) != V)
5780 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5783 else if (IncorrectIdx == -1U) {
5787 // There was already one element with an incorrect index.
5788 // We can't optimize this case to an insertps.
5792 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5794 EVT VT = Op.getSimpleValueType();
5795 unsigned ElementMoveMask = 0;
5796 if (IncorrectIdx == -1U)
5797 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5799 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5801 SDValue InsertpsMask =
5802 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5803 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5809 /// getVShift - Return a vector logical shift node.
5811 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5812 unsigned NumBits, SelectionDAG &DAG,
5813 const TargetLowering &TLI, SDLoc dl) {
5814 assert(VT.is128BitVector() && "Unknown type for VShift");
5815 EVT ShVT = MVT::v2i64;
5816 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5817 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5818 return DAG.getNode(ISD::BITCAST, dl, VT,
5819 DAG.getNode(Opc, dl, ShVT, SrcOp,
5820 DAG.getConstant(NumBits,
5821 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5825 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5827 // Check if the scalar load can be widened into a vector load. And if
5828 // the address is "base + cst" see if the cst can be "absorbed" into
5829 // the shuffle mask.
5830 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5831 SDValue Ptr = LD->getBasePtr();
5832 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5834 EVT PVT = LD->getValueType(0);
5835 if (PVT != MVT::i32 && PVT != MVT::f32)
5840 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5841 FI = FINode->getIndex();
5843 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5844 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5845 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5846 Offset = Ptr.getConstantOperandVal(1);
5847 Ptr = Ptr.getOperand(0);
5852 // FIXME: 256-bit vector instructions don't require a strict alignment,
5853 // improve this code to support it better.
5854 unsigned RequiredAlign = VT.getSizeInBits()/8;
5855 SDValue Chain = LD->getChain();
5856 // Make sure the stack object alignment is at least 16 or 32.
5857 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5858 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5859 if (MFI->isFixedObjectIndex(FI)) {
5860 // Can't change the alignment. FIXME: It's possible to compute
5861 // the exact stack offset and reference FI + adjust offset instead.
5862 // If someone *really* cares about this. That's the way to implement it.
5865 MFI->setObjectAlignment(FI, RequiredAlign);
5869 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5870 // Ptr + (Offset & ~15).
5873 if ((Offset % RequiredAlign) & 3)
5875 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5877 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5878 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5880 int EltNo = (Offset - StartOffset) >> 2;
5881 unsigned NumElems = VT.getVectorNumElements();
5883 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5884 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5885 LD->getPointerInfo().getWithOffset(StartOffset),
5886 false, false, false, 0);
5888 SmallVector<int, 8> Mask;
5889 for (unsigned i = 0; i != NumElems; ++i)
5890 Mask.push_back(EltNo);
5892 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5898 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5899 /// vector of type 'VT', see if the elements can be replaced by a single large
5900 /// load which has the same value as a build_vector whose operands are 'elts'.
5902 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5904 /// FIXME: we'd also like to handle the case where the last elements are zero
5905 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5906 /// There's even a handy isZeroNode for that purpose.
5907 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5908 SDLoc &DL, SelectionDAG &DAG,
5909 bool isAfterLegalize) {
5910 EVT EltVT = VT.getVectorElementType();
5911 unsigned NumElems = Elts.size();
5913 LoadSDNode *LDBase = nullptr;
5914 unsigned LastLoadedElt = -1U;
5916 // For each element in the initializer, see if we've found a load or an undef.
5917 // If we don't find an initial load element, or later load elements are
5918 // non-consecutive, bail out.
5919 for (unsigned i = 0; i < NumElems; ++i) {
5920 SDValue Elt = Elts[i];
5922 if (!Elt.getNode() ||
5923 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5926 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5928 LDBase = cast<LoadSDNode>(Elt.getNode());
5932 if (Elt.getOpcode() == ISD::UNDEF)
5935 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5936 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5941 // If we have found an entire vector of loads and undefs, then return a large
5942 // load of the entire vector width starting at the base pointer. If we found
5943 // consecutive loads for the low half, generate a vzext_load node.
5944 if (LastLoadedElt == NumElems - 1) {
5946 if (isAfterLegalize &&
5947 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5950 SDValue NewLd = SDValue();
5952 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5953 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5954 LDBase->getPointerInfo(),
5955 LDBase->isVolatile(), LDBase->isNonTemporal(),
5956 LDBase->isInvariant(), 0);
5957 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5958 LDBase->getPointerInfo(),
5959 LDBase->isVolatile(), LDBase->isNonTemporal(),
5960 LDBase->isInvariant(), LDBase->getAlignment());
5962 if (LDBase->hasAnyUseOfValue(1)) {
5963 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5965 SDValue(NewLd.getNode(), 1));
5966 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5967 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5968 SDValue(NewLd.getNode(), 1));
5973 if (NumElems == 4 && LastLoadedElt == 1 &&
5974 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5975 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5976 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5978 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5979 LDBase->getPointerInfo(),
5980 LDBase->getAlignment(),
5981 false/*isVolatile*/, true/*ReadMem*/,
5984 // Make sure the newly-created LOAD is in the same position as LDBase in
5985 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5986 // update uses of LDBase's output chain to use the TokenFactor.
5987 if (LDBase->hasAnyUseOfValue(1)) {
5988 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5989 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5990 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5991 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5992 SDValue(ResNode.getNode(), 1));
5995 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6000 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6001 /// to generate a splat value for the following cases:
6002 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6003 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6004 /// a scalar load, or a constant.
6005 /// The VBROADCAST node is returned when a pattern is found,
6006 /// or SDValue() otherwise.
6007 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6008 SelectionDAG &DAG) {
6009 // VBROADCAST requires AVX.
6010 // TODO: Splats could be generated for non-AVX CPUs using SSE
6011 // instructions, but there's less potential gain for only 128-bit vectors.
6012 if (!Subtarget->hasAVX())
6015 MVT VT = Op.getSimpleValueType();
6018 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6019 "Unsupported vector type for broadcast.");
6024 switch (Op.getOpcode()) {
6026 // Unknown pattern found.
6029 case ISD::BUILD_VECTOR: {
6030 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6031 BitVector UndefElements;
6032 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6034 // We need a splat of a single value to use broadcast, and it doesn't
6035 // make any sense if the value is only in one element of the vector.
6036 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6040 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6041 Ld.getOpcode() == ISD::ConstantFP);
6043 // Make sure that all of the users of a non-constant load are from the
6044 // BUILD_VECTOR node.
6045 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6050 case ISD::VECTOR_SHUFFLE: {
6051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6053 // Shuffles must have a splat mask where the first element is
6055 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6058 SDValue Sc = Op.getOperand(0);
6059 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6060 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6062 if (!Subtarget->hasInt256())
6065 // Use the register form of the broadcast instruction available on AVX2.
6066 if (VT.getSizeInBits() >= 256)
6067 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6068 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6071 Ld = Sc.getOperand(0);
6072 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6073 Ld.getOpcode() == ISD::ConstantFP);
6075 // The scalar_to_vector node and the suspected
6076 // load node must have exactly one user.
6077 // Constants may have multiple users.
6079 // AVX-512 has register version of the broadcast
6080 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6081 Ld.getValueType().getSizeInBits() >= 32;
6082 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6089 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6090 bool IsGE256 = (VT.getSizeInBits() >= 256);
6092 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6093 // instruction to save 8 or more bytes of constant pool data.
6094 // TODO: If multiple splats are generated to load the same constant,
6095 // it may be detrimental to overall size. There needs to be a way to detect
6096 // that condition to know if this is truly a size win.
6097 const Function *F = DAG.getMachineFunction().getFunction();
6098 bool OptForSize = F->getAttributes().
6099 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6101 // Handle broadcasting a single constant scalar from the constant pool
6103 // On Sandybridge (no AVX2), it is still better to load a constant vector
6104 // from the constant pool and not to broadcast it from a scalar.
6105 // But override that restriction when optimizing for size.
6106 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6107 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6108 EVT CVT = Ld.getValueType();
6109 assert(!CVT.isVector() && "Must not broadcast a vector type");
6111 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6112 // For size optimization, also splat v2f64 and v2i64, and for size opt
6113 // with AVX2, also splat i8 and i16.
6114 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6115 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6116 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6117 const Constant *C = nullptr;
6118 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6119 C = CI->getConstantIntValue();
6120 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6121 C = CF->getConstantFPValue();
6123 assert(C && "Invalid constant type");
6125 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6126 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6127 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6128 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6129 MachinePointerInfo::getConstantPool(),
6130 false, false, false, Alignment);
6132 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6136 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6138 // Handle AVX2 in-register broadcasts.
6139 if (!IsLoad && Subtarget->hasInt256() &&
6140 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6141 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6143 // The scalar source must be a normal load.
6147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6148 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6150 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6151 // double since there is no vbroadcastsd xmm
6152 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6153 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6157 // Unsupported broadcast.
6161 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6162 /// underlying vector and index.
6164 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6166 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6168 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6169 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6172 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6174 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6176 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6177 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6180 // In this case the vector is the extract_subvector expression and the index
6181 // is 2, as specified by the shuffle.
6182 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6183 SDValue ShuffleVec = SVOp->getOperand(0);
6184 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6185 assert(ShuffleVecVT.getVectorElementType() ==
6186 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6188 int ShuffleIdx = SVOp->getMaskElt(Idx);
6189 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6190 ExtractedFromVec = ShuffleVec;
6196 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6197 MVT VT = Op.getSimpleValueType();
6199 // Skip if insert_vec_elt is not supported.
6200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6201 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6205 unsigned NumElems = Op.getNumOperands();
6209 SmallVector<unsigned, 4> InsertIndices;
6210 SmallVector<int, 8> Mask(NumElems, -1);
6212 for (unsigned i = 0; i != NumElems; ++i) {
6213 unsigned Opc = Op.getOperand(i).getOpcode();
6215 if (Opc == ISD::UNDEF)
6218 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6219 // Quit if more than 1 elements need inserting.
6220 if (InsertIndices.size() > 1)
6223 InsertIndices.push_back(i);
6227 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6228 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6229 // Quit if non-constant index.
6230 if (!isa<ConstantSDNode>(ExtIdx))
6232 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6234 // Quit if extracted from vector of different type.
6235 if (ExtractedFromVec.getValueType() != VT)
6238 if (!VecIn1.getNode())
6239 VecIn1 = ExtractedFromVec;
6240 else if (VecIn1 != ExtractedFromVec) {
6241 if (!VecIn2.getNode())
6242 VecIn2 = ExtractedFromVec;
6243 else if (VecIn2 != ExtractedFromVec)
6244 // Quit if more than 2 vectors to shuffle
6248 if (ExtractedFromVec == VecIn1)
6250 else if (ExtractedFromVec == VecIn2)
6251 Mask[i] = Idx + NumElems;
6254 if (!VecIn1.getNode())
6257 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6258 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6259 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6260 unsigned Idx = InsertIndices[i];
6261 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6262 DAG.getIntPtrConstant(Idx));
6268 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6270 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6272 MVT VT = Op.getSimpleValueType();
6273 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6274 "Unexpected type in LowerBUILD_VECTORvXi1!");
6277 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6278 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6279 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6280 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6283 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 bool AllContants = true;
6290 uint64_t Immediate = 0;
6291 int NonConstIdx = -1;
6292 bool IsSplat = true;
6293 unsigned NumNonConsts = 0;
6294 unsigned NumConsts = 0;
6295 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6296 SDValue In = Op.getOperand(idx);
6297 if (In.getOpcode() == ISD::UNDEF)
6299 if (!isa<ConstantSDNode>(In)) {
6300 AllContants = false;
6306 if (cast<ConstantSDNode>(In)->getZExtValue())
6307 Immediate |= (1ULL << idx);
6309 if (In != Op.getOperand(0))
6314 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6315 DAG.getConstant(Immediate, MVT::i16));
6316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6317 DAG.getIntPtrConstant(0));
6320 if (NumNonConsts == 1 && NonConstIdx != 0) {
6323 SDValue VecAsImm = DAG.getConstant(Immediate,
6324 MVT::getIntegerVT(VT.getSizeInBits()));
6325 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6328 DstVec = DAG.getUNDEF(VT);
6329 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6330 Op.getOperand(NonConstIdx),
6331 DAG.getIntPtrConstant(NonConstIdx));
6333 if (!IsSplat && (NonConstIdx != 0))
6334 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6335 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6338 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6339 DAG.getConstant(-1, SelectVT),
6340 DAG.getConstant(0, SelectVT));
6342 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6343 DAG.getConstant((Immediate | 1), SelectVT),
6344 DAG.getConstant(Immediate, SelectVT));
6345 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6348 /// \brief Return true if \p N implements a horizontal binop and return the
6349 /// operands for the horizontal binop into V0 and V1.
6351 /// This is a helper function of PerformBUILD_VECTORCombine.
6352 /// This function checks that the build_vector \p N in input implements a
6353 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6354 /// operation to match.
6355 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6356 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6357 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6360 /// This function only analyzes elements of \p N whose indices are
6361 /// in range [BaseIdx, LastIdx).
6362 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6364 unsigned BaseIdx, unsigned LastIdx,
6365 SDValue &V0, SDValue &V1) {
6366 EVT VT = N->getValueType(0);
6368 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6369 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6370 "Invalid Vector in input!");
6372 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6373 bool CanFold = true;
6374 unsigned ExpectedVExtractIdx = BaseIdx;
6375 unsigned NumElts = LastIdx - BaseIdx;
6376 V0 = DAG.getUNDEF(VT);
6377 V1 = DAG.getUNDEF(VT);
6379 // Check if N implements a horizontal binop.
6380 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6381 SDValue Op = N->getOperand(i + BaseIdx);
6384 if (Op->getOpcode() == ISD::UNDEF) {
6385 // Update the expected vector extract index.
6386 if (i * 2 == NumElts)
6387 ExpectedVExtractIdx = BaseIdx;
6388 ExpectedVExtractIdx += 2;
6392 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6397 SDValue Op0 = Op.getOperand(0);
6398 SDValue Op1 = Op.getOperand(1);
6400 // Try to match the following pattern:
6401 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6402 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6403 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op0.getOperand(0) == Op1.getOperand(0) &&
6405 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6406 isa<ConstantSDNode>(Op1.getOperand(1)));
6410 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6411 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6413 if (i * 2 < NumElts) {
6414 if (V0.getOpcode() == ISD::UNDEF)
6415 V0 = Op0.getOperand(0);
6417 if (V1.getOpcode() == ISD::UNDEF)
6418 V1 = Op0.getOperand(0);
6419 if (i * 2 == NumElts)
6420 ExpectedVExtractIdx = BaseIdx;
6423 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6424 if (I0 == ExpectedVExtractIdx)
6425 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6426 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6427 // Try to match the following dag sequence:
6428 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6429 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6433 ExpectedVExtractIdx += 2;
6439 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6440 /// a concat_vector.
6442 /// This is a helper function of PerformBUILD_VECTORCombine.
6443 /// This function expects two 256-bit vectors called V0 and V1.
6444 /// At first, each vector is split into two separate 128-bit vectors.
6445 /// Then, the resulting 128-bit vectors are used to implement two
6446 /// horizontal binary operations.
6448 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6450 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6451 /// the two new horizontal binop.
6452 /// When Mode is set, the first horizontal binop dag node would take as input
6453 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6454 /// horizontal binop dag node would take as input the lower 128-bit of V1
6455 /// and the upper 128-bit of V1.
6457 /// HADD V0_LO, V0_HI
6458 /// HADD V1_LO, V1_HI
6460 /// Otherwise, the first horizontal binop dag node takes as input the lower
6461 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6462 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6464 /// HADD V0_LO, V1_LO
6465 /// HADD V0_HI, V1_HI
6467 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6468 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6469 /// the upper 128-bits of the result.
6470 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6471 SDLoc DL, SelectionDAG &DAG,
6472 unsigned X86Opcode, bool Mode,
6473 bool isUndefLO, bool isUndefHI) {
6474 EVT VT = V0.getValueType();
6475 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6476 "Invalid nodes in input!");
6478 unsigned NumElts = VT.getVectorNumElements();
6479 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6480 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6481 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6482 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6483 EVT NewVT = V0_LO.getValueType();
6485 SDValue LO = DAG.getUNDEF(NewVT);
6486 SDValue HI = DAG.getUNDEF(NewVT);
6489 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6490 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6491 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6492 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6493 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6497 V1_LO->getOpcode() != ISD::UNDEF))
6498 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6500 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6501 V1_HI->getOpcode() != ISD::UNDEF))
6502 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6505 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6508 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6509 /// sequence of 'vadd + vsub + blendi'.
6510 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6511 const X86Subtarget *Subtarget) {
6513 EVT VT = BV->getValueType(0);
6514 unsigned NumElts = VT.getVectorNumElements();
6515 SDValue InVec0 = DAG.getUNDEF(VT);
6516 SDValue InVec1 = DAG.getUNDEF(VT);
6518 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6519 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6521 // Odd-numbered elements in the input build vector are obtained from
6522 // adding two integer/float elements.
6523 // Even-numbered elements in the input build vector are obtained from
6524 // subtracting two integer/float elements.
6525 unsigned ExpectedOpcode = ISD::FSUB;
6526 unsigned NextExpectedOpcode = ISD::FADD;
6527 bool AddFound = false;
6528 bool SubFound = false;
6530 for (unsigned i = 0, e = NumElts; i != e; i++) {
6531 SDValue Op = BV->getOperand(i);
6533 // Skip 'undef' values.
6534 unsigned Opcode = Op.getOpcode();
6535 if (Opcode == ISD::UNDEF) {
6536 std::swap(ExpectedOpcode, NextExpectedOpcode);
6540 // Early exit if we found an unexpected opcode.
6541 if (Opcode != ExpectedOpcode)
6544 SDValue Op0 = Op.getOperand(0);
6545 SDValue Op1 = Op.getOperand(1);
6547 // Try to match the following pattern:
6548 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6549 // Early exit if we cannot match that sequence.
6550 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6551 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6553 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6554 Op0.getOperand(1) != Op1.getOperand(1))
6557 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6561 // We found a valid add/sub node. Update the information accordingly.
6567 // Update InVec0 and InVec1.
6568 if (InVec0.getOpcode() == ISD::UNDEF)
6569 InVec0 = Op0.getOperand(0);
6570 if (InVec1.getOpcode() == ISD::UNDEF)
6571 InVec1 = Op1.getOperand(0);
6573 // Make sure that operands in input to each add/sub node always
6574 // come from a same pair of vectors.
6575 if (InVec0 != Op0.getOperand(0)) {
6576 if (ExpectedOpcode == ISD::FSUB)
6579 // FADD is commutable. Try to commute the operands
6580 // and then test again.
6581 std::swap(Op0, Op1);
6582 if (InVec0 != Op0.getOperand(0))
6586 if (InVec1 != Op1.getOperand(0))
6589 // Update the pair of expected opcodes.
6590 std::swap(ExpectedOpcode, NextExpectedOpcode);
6593 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6594 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6595 InVec1.getOpcode() != ISD::UNDEF)
6596 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6601 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6602 const X86Subtarget *Subtarget) {
6604 EVT VT = N->getValueType(0);
6605 unsigned NumElts = VT.getVectorNumElements();
6606 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6607 SDValue InVec0, InVec1;
6609 // Try to match an ADDSUB.
6610 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6611 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6612 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6613 if (Value.getNode())
6617 // Try to match horizontal ADD/SUB.
6618 unsigned NumUndefsLO = 0;
6619 unsigned NumUndefsHI = 0;
6620 unsigned Half = NumElts/2;
6622 // Count the number of UNDEF operands in the build_vector in input.
6623 for (unsigned i = 0, e = Half; i != e; ++i)
6624 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6627 for (unsigned i = Half, e = NumElts; i != e; ++i)
6628 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6631 // Early exit if this is either a build_vector of all UNDEFs or all the
6632 // operands but one are UNDEF.
6633 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6636 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6637 // Try to match an SSE3 float HADD/HSUB.
6638 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6641 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6642 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6643 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6644 // Try to match an SSSE3 integer HADD/HSUB.
6645 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6648 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6649 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6652 if (!Subtarget->hasAVX())
6655 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6656 // Try to match an AVX horizontal add/sub of packed single/double
6657 // precision floating point values from 256-bit vectors.
6658 SDValue InVec2, InVec3;
6659 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6660 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6661 ((InVec0.getOpcode() == ISD::UNDEF ||
6662 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6663 ((InVec1.getOpcode() == ISD::UNDEF ||
6664 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6665 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6667 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6668 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6669 ((InVec0.getOpcode() == ISD::UNDEF ||
6670 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6671 ((InVec1.getOpcode() == ISD::UNDEF ||
6672 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6673 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6674 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6675 // Try to match an AVX2 horizontal add/sub of signed integers.
6676 SDValue InVec2, InVec3;
6678 bool CanFold = true;
6680 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6681 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6682 ((InVec0.getOpcode() == ISD::UNDEF ||
6683 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6684 ((InVec1.getOpcode() == ISD::UNDEF ||
6685 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6686 X86Opcode = X86ISD::HADD;
6687 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6688 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6689 ((InVec0.getOpcode() == ISD::UNDEF ||
6690 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6691 ((InVec1.getOpcode() == ISD::UNDEF ||
6692 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6693 X86Opcode = X86ISD::HSUB;
6698 // Fold this build_vector into a single horizontal add/sub.
6699 // Do this only if the target has AVX2.
6700 if (Subtarget->hasAVX2())
6701 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6703 // Do not try to expand this build_vector into a pair of horizontal
6704 // add/sub if we can emit a pair of scalar add/sub.
6705 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6708 // Convert this build_vector into a pair of horizontal binop followed by
6710 bool isUndefLO = NumUndefsLO == Half;
6711 bool isUndefHI = NumUndefsHI == Half;
6712 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6713 isUndefLO, isUndefHI);
6717 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6718 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6721 X86Opcode = X86ISD::HADD;
6722 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6723 X86Opcode = X86ISD::HSUB;
6724 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6725 X86Opcode = X86ISD::FHADD;
6726 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::FHSUB;
6731 // Don't try to expand this build_vector into a pair of horizontal add/sub
6732 // if we can simply emit a pair of scalar add/sub.
6733 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6736 // Convert this build_vector into two horizontal add/sub followed by
6738 bool isUndefLO = NumUndefsLO == Half;
6739 bool isUndefHI = NumUndefsHI == Half;
6740 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6741 isUndefLO, isUndefHI);
6748 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6751 MVT VT = Op.getSimpleValueType();
6752 MVT ExtVT = VT.getVectorElementType();
6753 unsigned NumElems = Op.getNumOperands();
6755 // Generate vectors for predicate vectors.
6756 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6757 return LowerBUILD_VECTORvXi1(Op, DAG);
6759 // Vectors containing all zeros can be matched by pxor and xorps later
6760 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6761 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6762 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6763 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6766 return getZeroVector(VT, Subtarget, DAG, dl);
6769 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6770 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6771 // vpcmpeqd on 256-bit vectors.
6772 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6773 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6776 if (!VT.is512BitVector())
6777 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6780 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6781 if (Broadcast.getNode())
6784 unsigned EVTBits = ExtVT.getSizeInBits();
6786 unsigned NumZero = 0;
6787 unsigned NumNonZero = 0;
6788 unsigned NonZeros = 0;
6789 bool IsAllConstants = true;
6790 SmallSet<SDValue, 8> Values;
6791 for (unsigned i = 0; i < NumElems; ++i) {
6792 SDValue Elt = Op.getOperand(i);
6793 if (Elt.getOpcode() == ISD::UNDEF)
6796 if (Elt.getOpcode() != ISD::Constant &&
6797 Elt.getOpcode() != ISD::ConstantFP)
6798 IsAllConstants = false;
6799 if (X86::isZeroNode(Elt))
6802 NonZeros |= (1 << i);
6807 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6808 if (NumNonZero == 0)
6809 return DAG.getUNDEF(VT);
6811 // Special case for single non-zero, non-undef, element.
6812 if (NumNonZero == 1) {
6813 unsigned Idx = countTrailingZeros(NonZeros);
6814 SDValue Item = Op.getOperand(Idx);
6816 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6817 // the value are obviously zero, truncate the value to i32 and do the
6818 // insertion that way. Only do this if the value is non-constant or if the
6819 // value is a constant being inserted into element 0. It is cheaper to do
6820 // a constant pool load than it is to do a movd + shuffle.
6821 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6822 (!IsAllConstants || Idx == 0)) {
6823 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6825 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6826 EVT VecVT = MVT::v4i32;
6827 unsigned VecElts = 4;
6829 // Truncate the value (which may itself be a constant) to i32, and
6830 // convert it to a vector with movd (S2V+shuffle to zero extend).
6831 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6832 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6834 // If using the new shuffle lowering, just directly insert this.
6835 if (ExperimentalVectorShuffleLowering)
6837 ISD::BITCAST, dl, VT,
6838 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6840 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6842 // Now we have our 32-bit value zero extended in the low element of
6843 // a vector. If Idx != 0, swizzle it into place.
6845 SmallVector<int, 4> Mask;
6846 Mask.push_back(Idx);
6847 for (unsigned i = 1; i != VecElts; ++i)
6849 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6852 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6856 // If we have a constant or non-constant insertion into the low element of
6857 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6858 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6859 // depending on what the source datatype is.
6862 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6864 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6865 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6866 if (VT.is256BitVector() || VT.is512BitVector()) {
6867 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6868 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6869 Item, DAG.getIntPtrConstant(0));
6871 assert(VT.is128BitVector() && "Expected an SSE value type!");
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6873 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6874 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6877 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6878 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6879 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6880 if (VT.is256BitVector()) {
6881 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6882 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6884 assert(VT.is128BitVector() && "Expected an SSE value type!");
6885 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6887 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6891 // Is it a vector logical left shift?
6892 if (NumElems == 2 && Idx == 1 &&
6893 X86::isZeroNode(Op.getOperand(0)) &&
6894 !X86::isZeroNode(Op.getOperand(1))) {
6895 unsigned NumBits = VT.getSizeInBits();
6896 return getVShift(true, VT,
6897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6898 VT, Op.getOperand(1)),
6899 NumBits/2, DAG, *this, dl);
6902 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6905 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6906 // is a non-constant being inserted into an element other than the low one,
6907 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6908 // movd/movss) to move this into the low element, then shuffle it into
6910 if (EVTBits == 32) {
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // If using the new shuffle lowering, just directly insert this.
6914 if (ExperimentalVectorShuffleLowering)
6915 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6917 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6918 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6919 SmallVector<int, 8> MaskVec;
6920 for (unsigned i = 0; i != NumElems; ++i)
6921 MaskVec.push_back(i == Idx ? 0 : 1);
6922 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6926 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6927 if (Values.size() == 1) {
6928 if (EVTBits == 32) {
6929 // Instead of a shuffle like this:
6930 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6931 // Check if it's possible to issue this instead.
6932 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6933 unsigned Idx = countTrailingZeros(NonZeros);
6934 SDValue Item = Op.getOperand(Idx);
6935 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6936 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6941 // A vector full of immediates; various special cases are already
6942 // handled, so this is best done with a single constant-pool load.
6946 // For AVX-length vectors, build the individual 128-bit pieces and use
6947 // shuffles to put them in place.
6948 if (VT.is256BitVector() || VT.is512BitVector()) {
6949 SmallVector<SDValue, 64> V;
6950 for (unsigned i = 0; i != NumElems; ++i)
6951 V.push_back(Op.getOperand(i));
6953 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6955 // Build both the lower and upper subvector.
6956 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6957 makeArrayRef(&V[0], NumElems/2));
6958 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6959 makeArrayRef(&V[NumElems / 2], NumElems/2));
6961 // Recreate the wider vector with the lower and upper part.
6962 if (VT.is256BitVector())
6963 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6967 // Let legalizer expand 2-wide build_vectors.
6968 if (EVTBits == 64) {
6969 if (NumNonZero == 1) {
6970 // One half is zero or undef.
6971 unsigned Idx = countTrailingZeros(NonZeros);
6972 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6973 Op.getOperand(Idx));
6974 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6979 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6980 if (EVTBits == 8 && NumElems == 16) {
6981 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6983 if (V.getNode()) return V;
6986 if (EVTBits == 16 && NumElems == 8) {
6987 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6993 if (EVTBits == 32 && NumElems == 4) {
6994 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6995 NumZero, DAG, Subtarget, *this);
7000 // If element VT is == 32 bits, turn it into a number of shuffles.
7001 SmallVector<SDValue, 8> V(NumElems);
7002 if (NumElems == 4 && NumZero > 0) {
7003 for (unsigned i = 0; i < 4; ++i) {
7004 bool isZero = !(NonZeros & (1 << i));
7006 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7008 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7011 for (unsigned i = 0; i < 2; ++i) {
7012 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7015 V[i] = V[i*2]; // Must be a zero vector.
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7021 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7024 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7029 bool Reverse1 = (NonZeros & 0x3) == 2;
7030 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7034 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7035 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7037 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7040 if (Values.size() > 1 && VT.is128BitVector()) {
7041 // Check for a build vector of consecutive loads.
7042 for (unsigned i = 0; i < NumElems; ++i)
7043 V[i] = Op.getOperand(i);
7045 // Check for elements which are consecutive loads.
7046 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7050 // Check for a build vector from mostly shuffle plus few inserting.
7051 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7055 // For SSE 4.1, use insertps to put the high elements into the low element.
7056 if (getSubtarget()->hasSSE41()) {
7058 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7059 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7061 Result = DAG.getUNDEF(VT);
7063 for (unsigned i = 1; i < NumElems; ++i) {
7064 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7065 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7066 Op.getOperand(i), DAG.getIntPtrConstant(i));
7071 // Otherwise, expand into a number of unpckl*, start by extending each of
7072 // our (non-undef) elements to the full vector width with the element in the
7073 // bottom slot of the vector (which generates no code for SSE).
7074 for (unsigned i = 0; i < NumElems; ++i) {
7075 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7076 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7078 V[i] = DAG.getUNDEF(VT);
7081 // Next, we iteratively mix elements, e.g. for v4f32:
7082 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7083 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7084 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7085 unsigned EltStride = NumElems >> 1;
7086 while (EltStride != 0) {
7087 for (unsigned i = 0; i < EltStride; ++i) {
7088 // If V[i+EltStride] is undef and this is the first round of mixing,
7089 // then it is safe to just drop this shuffle: V[i] is already in the
7090 // right place, the one element (since it's the first round) being
7091 // inserted as undef can be dropped. This isn't safe for successive
7092 // rounds because they will permute elements within both vectors.
7093 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7094 EltStride == NumElems/2)
7097 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7106 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7107 // to create 256-bit vectors from two other 128-bit ones.
7108 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7110 MVT ResVT = Op.getSimpleValueType();
7112 assert((ResVT.is256BitVector() ||
7113 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7115 SDValue V1 = Op.getOperand(0);
7116 SDValue V2 = Op.getOperand(1);
7117 unsigned NumElems = ResVT.getVectorNumElements();
7118 if(ResVT.is256BitVector())
7119 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7121 if (Op.getNumOperands() == 4) {
7122 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7123 ResVT.getVectorNumElements()/2);
7124 SDValue V3 = Op.getOperand(2);
7125 SDValue V4 = Op.getOperand(3);
7126 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7127 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7133 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7134 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7135 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7136 Op.getNumOperands() == 4)));
7138 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7139 // from two other 128-bit ones.
7141 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7142 return LowerAVXCONCAT_VECTORS(Op, DAG);
7146 //===----------------------------------------------------------------------===//
7147 // Vector shuffle lowering
7149 // This is an experimental code path for lowering vector shuffles on x86. It is
7150 // designed to handle arbitrary vector shuffles and blends, gracefully
7151 // degrading performance as necessary. It works hard to recognize idiomatic
7152 // shuffles and lower them to optimal instruction patterns without leaving
7153 // a framework that allows reasonably efficient handling of all vector shuffle
7155 //===----------------------------------------------------------------------===//
7157 /// \brief Tiny helper function to identify a no-op mask.
7159 /// This is a somewhat boring predicate function. It checks whether the mask
7160 /// array input, which is assumed to be a single-input shuffle mask of the kind
7161 /// used by the X86 shuffle instructions (not a fully general
7162 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7163 /// in-place shuffle are 'no-op's.
7164 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7165 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7166 if (Mask[i] != -1 && Mask[i] != i)
7171 /// \brief Helper function to classify a mask as a single-input mask.
7173 /// This isn't a generic single-input test because in the vector shuffle
7174 /// lowering we canonicalize single inputs to be the first input operand. This
7175 /// means we can more quickly test for a single input by only checking whether
7176 /// an input from the second operand exists. We also assume that the size of
7177 /// mask corresponds to the size of the input vectors which isn't true in the
7178 /// fully general case.
7179 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7181 if (M >= (int)Mask.size())
7186 /// \brief Test whether there are elements crossing 128-bit lanes in this
7189 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7190 /// and we routinely test for these.
7191 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7192 int LaneSize = 128 / VT.getScalarSizeInBits();
7193 int Size = Mask.size();
7194 for (int i = 0; i < Size; ++i)
7195 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7200 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7202 /// This checks a shuffle mask to see if it is performing the same
7203 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7204 /// that it is also not lane-crossing. It may however involve a blend from the
7205 /// same lane of a second vector.
7207 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7208 /// non-trivial to compute in the face of undef lanes. The representation is
7209 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7210 /// entries from both V1 and V2 inputs to the wider mask.
7212 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7213 SmallVectorImpl<int> &RepeatedMask) {
7214 int LaneSize = 128 / VT.getScalarSizeInBits();
7215 RepeatedMask.resize(LaneSize, -1);
7216 int Size = Mask.size();
7217 for (int i = 0; i < Size; ++i) {
7220 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7221 // This entry crosses lanes, so there is no way to model this shuffle.
7224 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7225 if (RepeatedMask[i % LaneSize] == -1)
7226 // This is the first non-undef entry in this slot of a 128-bit lane.
7227 RepeatedMask[i % LaneSize] =
7228 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7229 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7230 // Found a mismatch with the repeated mask.
7236 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7237 // 2013 will allow us to use it as a non-type template parameter.
7240 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7242 /// See its documentation for details.
7243 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7244 if (Mask.size() != Args.size())
7246 for (int i = 0, e = Mask.size(); i < e; ++i) {
7247 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7248 if (Mask[i] != -1 && Mask[i] != *Args[i])
7256 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7259 /// This is a fast way to test a shuffle mask against a fixed pattern:
7261 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7263 /// It returns true if the mask is exactly as wide as the argument list, and
7264 /// each element of the mask is either -1 (signifying undef) or the value given
7265 /// in the argument.
7266 static const VariadicFunction1<
7267 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7269 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7271 /// This helper function produces an 8-bit shuffle immediate corresponding to
7272 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7273 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7276 /// NB: We rely heavily on "undef" masks preserving the input lane.
7277 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7278 SelectionDAG &DAG) {
7279 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7280 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7281 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7282 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7283 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7286 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7287 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7288 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7289 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7290 return DAG.getConstant(Imm, MVT::i8);
7293 /// \brief Try to emit a blend instruction for a shuffle.
7295 /// This doesn't do any checks for the availability of instructions for blending
7296 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7297 /// be matched in the backend with the type given. What it does check for is
7298 /// that the shuffle mask is in fact a blend.
7299 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7300 SDValue V2, ArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget,
7302 SelectionDAG &DAG) {
7304 unsigned BlendMask = 0;
7305 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7306 if (Mask[i] >= Size) {
7307 if (Mask[i] != i + Size)
7308 return SDValue(); // Shuffled V2 input!
7309 BlendMask |= 1u << i;
7312 if (Mask[i] >= 0 && Mask[i] != i)
7313 return SDValue(); // Shuffled V1 input!
7315 switch (VT.SimpleTy) {
7320 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7321 DAG.getConstant(BlendMask, MVT::i8));
7325 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7329 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7330 // that instruction.
7331 if (Subtarget->hasAVX2()) {
7332 // Scale the blend by the number of 32-bit dwords per element.
7333 int Scale = VT.getScalarSizeInBits() / 32;
7335 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7336 if (Mask[i] >= Size)
7337 for (int j = 0; j < Scale; ++j)
7338 BlendMask |= 1u << (i * Scale + j);
7340 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7341 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7342 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7343 return DAG.getNode(ISD::BITCAST, DL, VT,
7344 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7345 DAG.getConstant(BlendMask, MVT::i8)));
7349 // For integer shuffles we need to expand the mask and cast the inputs to
7350 // v8i16s prior to blending.
7351 int Scale = 8 / VT.getVectorNumElements();
7353 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7354 if (Mask[i] >= Size)
7355 for (int j = 0; j < Scale; ++j)
7356 BlendMask |= 1u << (i * Scale + j);
7358 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7359 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7360 return DAG.getNode(ISD::BITCAST, DL, VT,
7361 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7362 DAG.getConstant(BlendMask, MVT::i8)));
7366 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 SmallVector<int, 8> RepeatedMask;
7368 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7369 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7370 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7372 for (int i = 0; i < 8; ++i)
7373 if (RepeatedMask[i] >= 16)
7374 BlendMask |= 1u << i;
7375 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7376 DAG.getConstant(BlendMask, MVT::i8));
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7382 // Scale the blend by the number of bytes per element.
7383 int Scale = VT.getScalarSizeInBits() / 8;
7384 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7386 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7387 // mix of LLVM's code generator and the x86 backend. We tell the code
7388 // generator that boolean values in the elements of an x86 vector register
7389 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7390 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7391 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7392 // of the element (the remaining are ignored) and 0 in that high bit would
7393 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7394 // the LLVM model for boolean values in vector elements gets the relevant
7395 // bit set, it is set backwards and over constrained relative to x86's
7397 SDValue VSELECTMask[32];
7398 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7399 for (int j = 0; j < Scale; ++j)
7400 VSELECTMask[Scale * i + j] =
7401 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7402 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7404 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7405 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7407 ISD::BITCAST, DL, VT,
7408 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7409 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7414 llvm_unreachable("Not a supported integer vector type!");
7418 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7419 /// unblended shuffles followed by an unshuffled blend.
7421 /// This matches the extremely common pattern for handling combined
7422 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7424 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7428 SelectionDAG &DAG) {
7429 // Shuffle the input elements into the desired positions in V1 and V2 and
7430 // blend them together.
7431 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7432 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7433 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7434 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7435 if (Mask[i] >= 0 && Mask[i] < Size) {
7436 V1Mask[i] = Mask[i];
7438 } else if (Mask[i] >= Size) {
7439 V2Mask[i] = Mask[i] - Size;
7440 BlendMask[i] = i + Size;
7443 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7444 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7445 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7448 /// \brief Try to lower a vector shuffle as a byte rotation.
7450 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7451 /// byte-rotation of the concatenation of two vectors. This routine will
7452 /// try to generically lower a vector shuffle through such an instruction. It
7453 /// does not check for the availability of PALIGNR-based lowerings, only the
7454 /// applicability of this strategy to the given mask. This matches shuffle
7455 /// vectors that look like:
7457 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7459 /// Essentially it concatenates V1 and V2, shifts right by some number of
7460 /// elements, and takes the low elements as the result. Note that while this is
7461 /// specified as a *right shift* because x86 is little-endian, it is a *left
7462 /// rotate* of the vector lanes.
7464 /// Note that this only handles 128-bit vector widths currently.
7465 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7468 SelectionDAG &DAG) {
7469 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7471 // We need to detect various ways of spelling a rotation:
7472 // [11, 12, 13, 14, 15, 0, 1, 2]
7473 // [-1, 12, 13, 14, -1, -1, 1, -1]
7474 // [-1, -1, -1, -1, -1, -1, 1, 2]
7475 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7476 // [-1, 4, 5, 6, -1, -1, 9, -1]
7477 // [-1, 4, 5, 6, -1, -1, -1, -1]
7480 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7483 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7485 // Based on the mod-Size value of this mask element determine where
7486 // a rotated vector would have started.
7487 int StartIdx = i - (Mask[i] % Size);
7489 // The identity rotation isn't interesting, stop.
7492 // If we found the tail of a vector the rotation must be the missing
7493 // front. If we found the head of a vector, it must be how much of the head.
7494 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7497 Rotation = CandidateRotation;
7498 else if (Rotation != CandidateRotation)
7499 // The rotations don't match, so we can't match this mask.
7502 // Compute which value this mask is pointing at.
7503 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7505 // Compute which of the two target values this index should be assigned to.
7506 // This reflects whether the high elements are remaining or the low elements
7508 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7510 // Either set up this value if we've not encountered it before, or check
7511 // that it remains consistent.
7514 else if (TargetV != MaskV)
7515 // This may be a rotation, but it pulls from the inputs in some
7516 // unsupported interleaving.
7520 // Check that we successfully analyzed the mask, and normalize the results.
7521 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7522 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7528 // Cast the inputs to v16i8 to match PALIGNR.
7529 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7530 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7532 assert(VT.getSizeInBits() == 128 &&
7533 "Rotate-based lowering only supports 128-bit lowering!");
7534 assert(Mask.size() <= 16 &&
7535 "Can shuffle at most 16 bytes in a 128-bit vector!");
7536 // The actual rotate instruction rotates bytes, so we need to scale the
7537 // rotation based on how many bytes are in the vector.
7538 int Scale = 16 / Mask.size();
7540 return DAG.getNode(ISD::BITCAST, DL, VT,
7541 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7542 DAG.getConstant(Rotation * Scale, MVT::i8)));
7545 /// \brief Compute whether each element of a shuffle is zeroable.
7547 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7548 /// Either it is an undef element in the shuffle mask, the element of the input
7549 /// referenced is undef, or the element of the input referenced is known to be
7550 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7551 /// as many lanes with this technique as possible to simplify the remaining
7553 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7554 SDValue V1, SDValue V2) {
7555 SmallBitVector Zeroable(Mask.size(), false);
7557 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7558 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7560 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7562 // Handle the easy cases.
7563 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7568 // If this is an index into a build_vector node, dig out the input value and
7570 SDValue V = M < Size ? V1 : V2;
7571 if (V.getOpcode() != ISD::BUILD_VECTOR)
7574 SDValue Input = V.getOperand(M % Size);
7575 // The UNDEF opcode check really should be dead code here, but not quite
7576 // worth asserting on (it isn't invalid, just unexpected).
7577 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7584 /// \brief Lower a vector shuffle as a zero or any extension.
7586 /// Given a specific number of elements, element bit width, and extension
7587 /// stride, produce either a zero or any extension based on the available
7588 /// features of the subtarget.
7589 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7590 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7591 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7592 assert(Scale > 1 && "Need a scale to extend.");
7593 int EltBits = VT.getSizeInBits() / NumElements;
7594 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7595 "Only 8, 16, and 32 bit elements can be extended.");
7596 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7598 // Found a valid zext mask! Try various lowering strategies based on the
7599 // input type and available ISA extensions.
7600 if (Subtarget->hasSSE41()) {
7601 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7602 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7603 NumElements / Scale);
7604 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7605 return DAG.getNode(ISD::BITCAST, DL, VT,
7606 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7609 // For any extends we can cheat for larger element sizes and use shuffle
7610 // instructions that can fold with a load and/or copy.
7611 if (AnyExt && EltBits == 32) {
7612 int PSHUFDMask[4] = {0, -1, 1, -1};
7614 ISD::BITCAST, DL, VT,
7615 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7616 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7619 if (AnyExt && EltBits == 16 && Scale > 2) {
7620 int PSHUFDMask[4] = {0, -1, 0, -1};
7621 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7622 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7623 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7624 int PSHUFHWMask[4] = {1, -1, -1, -1};
7626 ISD::BITCAST, DL, VT,
7627 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7628 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7629 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7632 // If this would require more than 2 unpack instructions to expand, use
7633 // pshufb when available. We can only use more than 2 unpack instructions
7634 // when zero extending i8 elements which also makes it easier to use pshufb.
7635 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7636 assert(NumElements == 16 && "Unexpected byte vector width!");
7637 SDValue PSHUFBMask[16];
7638 for (int i = 0; i < 16; ++i)
7640 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7641 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7642 return DAG.getNode(ISD::BITCAST, DL, VT,
7643 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7644 DAG.getNode(ISD::BUILD_VECTOR, DL,
7645 MVT::v16i8, PSHUFBMask)));
7648 // Otherwise emit a sequence of unpacks.
7650 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7651 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7652 : getZeroVector(InputVT, Subtarget, DAG, DL);
7653 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7654 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7658 } while (Scale > 1);
7659 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7662 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7664 /// This routine will try to do everything in its power to cleverly lower
7665 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7666 /// check for the profitability of this lowering, it tries to aggressively
7667 /// match this pattern. It will use all of the micro-architectural details it
7668 /// can to emit an efficient lowering. It handles both blends with all-zero
7669 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7670 /// masking out later).
7672 /// The reason we have dedicated lowering for zext-style shuffles is that they
7673 /// are both incredibly common and often quite performance sensitive.
7674 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7675 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7676 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7677 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7679 int Bits = VT.getSizeInBits();
7680 int NumElements = Mask.size();
7682 // Define a helper function to check a particular ext-scale and lower to it if
7684 auto Lower = [&](int Scale) -> SDValue {
7687 for (int i = 0; i < NumElements; ++i) {
7689 continue; // Valid anywhere but doesn't tell us anything.
7690 if (i % Scale != 0) {
7691 // Each of the extend elements needs to be zeroable.
7695 // We no lorger are in the anyext case.
7700 // Each of the base elements needs to be consecutive indices into the
7701 // same input vector.
7702 SDValue V = Mask[i] < NumElements ? V1 : V2;
7705 else if (InputV != V)
7706 return SDValue(); // Flip-flopping inputs.
7708 if (Mask[i] % NumElements != i / Scale)
7709 return SDValue(); // Non-consecutive strided elemenst.
7712 // If we fail to find an input, we have a zero-shuffle which should always
7713 // have already been handled.
7714 // FIXME: Maybe handle this here in case during blending we end up with one?
7718 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7719 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7722 // The widest scale possible for extending is to a 64-bit integer.
7723 assert(Bits % 64 == 0 &&
7724 "The number of bits in a vector must be divisible by 64 on x86!");
7725 int NumExtElements = Bits / 64;
7727 // Each iteration, try extending the elements half as much, but into twice as
7729 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7730 assert(NumElements % NumExtElements == 0 &&
7731 "The input vector size must be divisble by the extended size.");
7732 if (SDValue V = Lower(NumElements / NumExtElements))
7736 // No viable ext lowering found.
7740 /// \brief Try to get a scalar value for a specific element of a vector.
7742 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7743 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7744 SelectionDAG &DAG) {
7745 MVT VT = V.getSimpleValueType();
7746 MVT EltVT = VT.getVectorElementType();
7747 while (V.getOpcode() == ISD::BITCAST)
7748 V = V.getOperand(0);
7749 // If the bitcasts shift the element size, we can't extract an equivalent
7751 MVT NewVT = V.getSimpleValueType();
7752 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7755 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7756 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7757 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7762 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7764 /// This is particularly important because the set of instructions varies
7765 /// significantly based on whether the operand is a load or not.
7766 static bool isShuffleFoldableLoad(SDValue V) {
7767 while (V.getOpcode() == ISD::BITCAST)
7768 V = V.getOperand(0);
7770 return ISD::isNON_EXTLoad(V.getNode());
7773 /// \brief Try to lower insertion of a single element into a zero vector.
7775 /// This is a common pattern that we have especially efficient patterns to lower
7776 /// across all subtarget feature sets.
7777 static SDValue lowerVectorShuffleAsElementInsertion(
7778 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7779 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7780 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7782 MVT EltVT = VT.getVectorElementType();
7784 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7785 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7787 bool IsV1Zeroable = true;
7788 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7789 if (i != V2Index && !Zeroable[i]) {
7790 IsV1Zeroable = false;
7794 // Check for a single input from a SCALAR_TO_VECTOR node.
7795 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7796 // all the smarts here sunk into that routine. However, the current
7797 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7798 // vector shuffle lowering is dead.
7799 if (SDValue V2S = getScalarValueForVectorElement(
7800 V2, Mask[V2Index] - Mask.size(), DAG)) {
7801 // We need to zext the scalar if it is smaller than an i32.
7802 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7803 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7804 // Using zext to expand a narrow element won't work for non-zero
7809 // Zero-extend directly to i32.
7811 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7813 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7814 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7815 EltVT == MVT::i16) {
7816 // Either not inserting from the low element of the input or the input
7817 // element size is too small to use VZEXT_MOVL to clear the high bits.
7821 if (!IsV1Zeroable) {
7822 // If V1 can't be treated as a zero vector we have fewer options to lower
7823 // this. We can't support integer vectors or non-zero targets cheaply, and
7824 // the V1 elements can't be permuted in any way.
7825 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7826 if (!VT.isFloatingPoint() || V2Index != 0)
7828 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7829 V1Mask[V2Index] = -1;
7830 if (!isNoopShuffleMask(V1Mask))
7832 // This is essentially a special case blend operation, but if we have
7833 // general purpose blend operations, they are always faster. Bail and let
7834 // the rest of the lowering handle these as blends.
7835 if (Subtarget->hasSSE41())
7838 // Otherwise, use MOVSD or MOVSS.
7839 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7840 "Only two types of floating point element types to handle!");
7841 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7845 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7847 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7850 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7851 // the desired position. Otherwise it is more efficient to do a vector
7852 // shift left. We know that we can do a vector shift left because all
7853 // the inputs are zero.
7854 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7855 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7856 V2Shuffle[V2Index] = 0;
7857 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7859 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7861 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7863 V2Index * EltVT.getSizeInBits(),
7864 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7865 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7871 /// \brief Try to lower broadcast of a single element.
7873 /// For convenience, this code also bundles all of the subtarget feature set
7874 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7875 /// a convenient way to factor it out.
7876 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7878 const X86Subtarget *Subtarget,
7879 SelectionDAG &DAG) {
7880 if (!Subtarget->hasAVX())
7882 if (VT.isInteger() && !Subtarget->hasAVX2())
7885 // Check that the mask is a broadcast.
7886 int BroadcastIdx = -1;
7888 if (M >= 0 && BroadcastIdx == -1)
7890 else if (M >= 0 && M != BroadcastIdx)
7893 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7894 "a sorted mask where the broadcast "
7897 // Go up the chain of (vector) values to try and find a scalar load that
7898 // we can combine with the broadcast.
7900 switch (V.getOpcode()) {
7901 case ISD::CONCAT_VECTORS: {
7902 int OperandSize = Mask.size() / V.getNumOperands();
7903 V = V.getOperand(BroadcastIdx / OperandSize);
7904 BroadcastIdx %= OperandSize;
7908 case ISD::INSERT_SUBVECTOR: {
7909 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7910 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7914 int BeginIdx = (int)ConstantIdx->getZExtValue();
7916 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7917 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7918 BroadcastIdx -= BeginIdx;
7929 // Check if this is a broadcast of a scalar. We special case lowering
7930 // for scalars so that we can more effectively fold with loads.
7931 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7932 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7933 V = V.getOperand(BroadcastIdx);
7935 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7937 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7939 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7940 // We can't broadcast from a vector register w/o AVX2, and we can only
7941 // broadcast from the zero-element of a vector register.
7945 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7948 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7950 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7951 /// support for floating point shuffles but not integer shuffles. These
7952 /// instructions will incur a domain crossing penalty on some chips though so
7953 /// it is better to avoid lowering through this for integer vectors where
7955 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7956 const X86Subtarget *Subtarget,
7957 SelectionDAG &DAG) {
7959 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7960 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7961 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7962 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7963 ArrayRef<int> Mask = SVOp->getMask();
7964 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7966 if (isSingleInputShuffleMask(Mask)) {
7967 // Straight shuffle of a single input vector. Simulate this by using the
7968 // single input as both of the "inputs" to this instruction..
7969 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7971 if (Subtarget->hasAVX()) {
7972 // If we have AVX, we can use VPERMILPS which will allow folding a load
7973 // into the shuffle.
7974 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7975 DAG.getConstant(SHUFPDMask, MVT::i8));
7978 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7979 DAG.getConstant(SHUFPDMask, MVT::i8));
7981 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7982 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7984 // Use dedicated unpack instructions for masks that match their pattern.
7985 if (isShuffleEquivalent(Mask, 0, 2))
7986 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7987 if (isShuffleEquivalent(Mask, 1, 3))
7988 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7990 // If we have a single input, insert that into V1 if we can do so cheaply.
7991 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7992 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7993 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7995 // Try inverting the insertion since for v2 masks it is easy to do and we
7996 // can't reliably sort the mask one way or the other.
7997 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7998 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7999 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8000 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8004 // Try to use one of the special instruction patterns to handle two common
8005 // blend patterns if a zero-blend above didn't work.
8006 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8007 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8008 // We can either use a special instruction to load over the low double or
8009 // to move just the low double.
8011 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8013 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8015 if (Subtarget->hasSSE41())
8016 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8020 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8021 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8022 DAG.getConstant(SHUFPDMask, MVT::i8));
8025 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8027 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8028 /// the integer unit to minimize domain crossing penalties. However, for blends
8029 /// it falls back to the floating point shuffle operation with appropriate bit
8031 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8032 const X86Subtarget *Subtarget,
8033 SelectionDAG &DAG) {
8035 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8036 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8037 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8038 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8039 ArrayRef<int> Mask = SVOp->getMask();
8040 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8042 if (isSingleInputShuffleMask(Mask)) {
8043 // Check for being able to broadcast a single element.
8044 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8045 Mask, Subtarget, DAG))
8048 // Straight shuffle of a single input vector. For everything from SSE2
8049 // onward this has a single fast instruction with no scary immediates.
8050 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8051 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8052 int WidenedMask[4] = {
8053 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8054 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8056 ISD::BITCAST, DL, MVT::v2i64,
8057 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8058 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8061 // If we have a single input from V2 insert that into V1 if we can do so
8063 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8064 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8065 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8067 // Try inverting the insertion since for v2 masks it is easy to do and we
8068 // can't reliably sort the mask one way or the other.
8069 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8070 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8071 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8072 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8076 // Use dedicated unpack instructions for masks that match their pattern.
8077 if (isShuffleEquivalent(Mask, 0, 2))
8078 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8079 if (isShuffleEquivalent(Mask, 1, 3))
8080 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8082 if (Subtarget->hasSSE41())
8083 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8087 // Try to use rotation instructions if available.
8088 if (Subtarget->hasSSSE3())
8089 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8090 DL, MVT::v2i64, V1, V2, Mask, DAG))
8093 // We implement this with SHUFPD which is pretty lame because it will likely
8094 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8095 // However, all the alternatives are still more cycles and newer chips don't
8096 // have this problem. It would be really nice if x86 had better shuffles here.
8097 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8098 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8099 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8100 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8103 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8105 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8106 /// It makes no assumptions about whether this is the *best* lowering, it simply
8108 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8109 ArrayRef<int> Mask, SDValue V1,
8110 SDValue V2, SelectionDAG &DAG) {
8111 SDValue LowV = V1, HighV = V2;
8112 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8115 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8117 if (NumV2Elements == 1) {
8119 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8122 // Compute the index adjacent to V2Index and in the same half by toggling
8124 int V2AdjIndex = V2Index ^ 1;
8126 if (Mask[V2AdjIndex] == -1) {
8127 // Handles all the cases where we have a single V2 element and an undef.
8128 // This will only ever happen in the high lanes because we commute the
8129 // vector otherwise.
8131 std::swap(LowV, HighV);
8132 NewMask[V2Index] -= 4;
8134 // Handle the case where the V2 element ends up adjacent to a V1 element.
8135 // To make this work, blend them together as the first step.
8136 int V1Index = V2AdjIndex;
8137 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8138 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8139 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8141 // Now proceed to reconstruct the final blend as we have the necessary
8142 // high or low half formed.
8149 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8150 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8152 } else if (NumV2Elements == 2) {
8153 if (Mask[0] < 4 && Mask[1] < 4) {
8154 // Handle the easy case where we have V1 in the low lanes and V2 in the
8158 } else if (Mask[2] < 4 && Mask[3] < 4) {
8159 // We also handle the reversed case because this utility may get called
8160 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8161 // arrange things in the right direction.
8167 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8168 // trying to place elements directly, just blend them and set up the final
8169 // shuffle to place them.
8171 // The first two blend mask elements are for V1, the second two are for
8173 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8174 Mask[2] < 4 ? Mask[2] : Mask[3],
8175 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8176 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8177 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8178 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8180 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8183 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8184 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8185 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8186 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8189 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8190 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8193 /// \brief Lower 4-lane 32-bit floating point shuffles.
8195 /// Uses instructions exclusively from the floating point unit to minimize
8196 /// domain crossing penalties, as these are sufficient to implement all v4f32
8198 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8199 const X86Subtarget *Subtarget,
8200 SelectionDAG &DAG) {
8202 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8203 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8204 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8206 ArrayRef<int> Mask = SVOp->getMask();
8207 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8210 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8212 if (NumV2Elements == 0) {
8213 // Check for being able to broadcast a single element.
8214 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8215 Mask, Subtarget, DAG))
8218 if (Subtarget->hasAVX()) {
8219 // If we have AVX, we can use VPERMILPS which will allow folding a load
8220 // into the shuffle.
8221 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8222 getV4X86ShuffleImm8ForMask(Mask, DAG));
8225 // Otherwise, use a straight shuffle of a single input vector. We pass the
8226 // input vector to both operands to simulate this with a SHUFPS.
8227 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8228 getV4X86ShuffleImm8ForMask(Mask, DAG));
8231 // Use dedicated unpack instructions for masks that match their pattern.
8232 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8233 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8234 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8235 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8237 // There are special ways we can lower some single-element blends. However, we
8238 // have custom ways we can lower more complex single-element blends below that
8239 // we defer to if both this and BLENDPS fail to match, so restrict this to
8240 // when the V2 input is targeting element 0 of the mask -- that is the fast
8242 if (NumV2Elements == 1 && Mask[0] >= 4)
8243 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8244 Mask, Subtarget, DAG))
8247 if (Subtarget->hasSSE41())
8248 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8252 // Check for whether we can use INSERTPS to perform the blend. We only use
8253 // INSERTPS when the V1 elements are already in the correct locations
8254 // because otherwise we can just always use two SHUFPS instructions which
8255 // are much smaller to encode than a SHUFPS and an INSERTPS.
8256 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8258 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8261 // When using INSERTPS we can zero any lane of the destination. Collect
8262 // the zero inputs into a mask and drop them from the lanes of V1 which
8263 // actually need to be present as inputs to the INSERTPS.
8264 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8266 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8267 bool InsertNeedsShuffle = false;
8269 for (int i = 0; i < 4; ++i)
8273 } else if (Mask[i] != i) {
8274 InsertNeedsShuffle = true;
8279 // We don't want to use INSERTPS or other insertion techniques if it will
8280 // require shuffling anyways.
8281 if (!InsertNeedsShuffle) {
8282 // If all of V1 is zeroable, replace it with undef.
8283 if ((ZMask | 1 << V2Index) == 0xF)
8284 V1 = DAG.getUNDEF(MVT::v4f32);
8286 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8287 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8289 // Insert the V2 element into the desired position.
8290 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8291 DAG.getConstant(InsertPSMask, MVT::i8));
8295 // Otherwise fall back to a SHUFPS lowering strategy.
8296 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8299 /// \brief Lower 4-lane i32 vector shuffles.
8301 /// We try to handle these with integer-domain shuffles where we can, but for
8302 /// blends we use the floating point domain blend instructions.
8303 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8304 const X86Subtarget *Subtarget,
8305 SelectionDAG &DAG) {
8307 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8308 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8309 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8310 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8311 ArrayRef<int> Mask = SVOp->getMask();
8312 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8314 // Whenever we can lower this as a zext, that instruction is strictly faster
8315 // than any alternative. It also allows us to fold memory operands into the
8316 // shuffle in many cases.
8317 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8318 Mask, Subtarget, DAG))
8322 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8324 if (NumV2Elements == 0) {
8325 // Check for being able to broadcast a single element.
8326 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8327 Mask, Subtarget, DAG))
8330 // Straight shuffle of a single input vector. For everything from SSE2
8331 // onward this has a single fast instruction with no scary immediates.
8332 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8333 // but we aren't actually going to use the UNPCK instruction because doing
8334 // so prevents folding a load into this instruction or making a copy.
8335 const int UnpackLoMask[] = {0, 0, 1, 1};
8336 const int UnpackHiMask[] = {2, 2, 3, 3};
8337 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8338 Mask = UnpackLoMask;
8339 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8340 Mask = UnpackHiMask;
8342 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8343 getV4X86ShuffleImm8ForMask(Mask, DAG));
8346 // There are special ways we can lower some single-element blends.
8347 if (NumV2Elements == 1)
8348 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8349 Mask, Subtarget, DAG))
8352 // Use dedicated unpack instructions for masks that match their pattern.
8353 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8354 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8355 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8356 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8358 if (Subtarget->hasSSE41())
8359 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8363 // Try to use rotation instructions if available.
8364 if (Subtarget->hasSSSE3())
8365 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8366 DL, MVT::v4i32, V1, V2, Mask, DAG))
8369 // We implement this with SHUFPS because it can blend from two vectors.
8370 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8371 // up the inputs, bypassing domain shift penalties that we would encur if we
8372 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8374 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8375 DAG.getVectorShuffle(
8377 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8378 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8381 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8382 /// shuffle lowering, and the most complex part.
8384 /// The lowering strategy is to try to form pairs of input lanes which are
8385 /// targeted at the same half of the final vector, and then use a dword shuffle
8386 /// to place them onto the right half, and finally unpack the paired lanes into
8387 /// their final position.
8389 /// The exact breakdown of how to form these dword pairs and align them on the
8390 /// correct sides is really tricky. See the comments within the function for
8391 /// more of the details.
8392 static SDValue lowerV8I16SingleInputVectorShuffle(
8393 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8394 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8395 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8396 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8397 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8399 SmallVector<int, 4> LoInputs;
8400 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8401 [](int M) { return M >= 0; });
8402 std::sort(LoInputs.begin(), LoInputs.end());
8403 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8404 SmallVector<int, 4> HiInputs;
8405 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8406 [](int M) { return M >= 0; });
8407 std::sort(HiInputs.begin(), HiInputs.end());
8408 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8410 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8411 int NumHToL = LoInputs.size() - NumLToL;
8413 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8414 int NumHToH = HiInputs.size() - NumLToH;
8415 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8416 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8417 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8418 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8420 // Check for being able to broadcast a single element.
8421 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8422 Mask, Subtarget, DAG))
8425 // Use dedicated unpack instructions for masks that match their pattern.
8426 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8427 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8428 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8429 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8431 // Try to use rotation instructions if available.
8432 if (Subtarget->hasSSSE3())
8433 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8434 DL, MVT::v8i16, V, V, Mask, DAG))
8437 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8438 // such inputs we can swap two of the dwords across the half mark and end up
8439 // with <=2 inputs to each half in each half. Once there, we can fall through
8440 // to the generic code below. For example:
8442 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8443 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8445 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8446 // and an existing 2-into-2 on the other half. In this case we may have to
8447 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8448 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8449 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8450 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8451 // half than the one we target for fixing) will be fixed when we re-enter this
8452 // path. We will also combine away any sequence of PSHUFD instructions that
8453 // result into a single instruction. Here is an example of the tricky case:
8455 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8456 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8458 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8460 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8461 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8463 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8464 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8466 // The result is fine to be handled by the generic logic.
8467 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8468 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8469 int AOffset, int BOffset) {
8470 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8471 "Must call this with A having 3 or 1 inputs from the A half.");
8472 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8473 "Must call this with B having 1 or 3 inputs from the B half.");
8474 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8475 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8477 // Compute the index of dword with only one word among the three inputs in
8478 // a half by taking the sum of the half with three inputs and subtracting
8479 // the sum of the actual three inputs. The difference is the remaining
8482 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8483 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8484 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8485 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8486 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8487 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8488 int TripleNonInputIdx =
8489 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8490 TripleDWord = TripleNonInputIdx / 2;
8492 // We use xor with one to compute the adjacent DWord to whichever one the
8494 OneInputDWord = (OneInput / 2) ^ 1;
8496 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8497 // and BToA inputs. If there is also such a problem with the BToB and AToB
8498 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8499 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8500 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8501 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8502 // Compute how many inputs will be flipped by swapping these DWords. We
8504 // to balance this to ensure we don't form a 3-1 shuffle in the other
8506 int NumFlippedAToBInputs =
8507 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8508 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8509 int NumFlippedBToBInputs =
8510 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8511 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8512 if ((NumFlippedAToBInputs == 1 &&
8513 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8514 (NumFlippedBToBInputs == 1 &&
8515 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8516 // We choose whether to fix the A half or B half based on whether that
8517 // half has zero flipped inputs. At zero, we may not be able to fix it
8518 // with that half. We also bias towards fixing the B half because that
8519 // will more commonly be the high half, and we have to bias one way.
8520 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8521 ArrayRef<int> Inputs) {
8522 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8523 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8524 PinnedIdx ^ 1) != Inputs.end();
8525 // Determine whether the free index is in the flipped dword or the
8526 // unflipped dword based on where the pinned index is. We use this bit
8527 // in an xor to conditionally select the adjacent dword.
8528 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8529 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8530 FixFreeIdx) != Inputs.end();
8531 if (IsFixIdxInput == IsFixFreeIdxInput)
8533 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8534 FixFreeIdx) != Inputs.end();
8535 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8536 "We need to be changing the number of flipped inputs!");
8537 int PSHUFHalfMask[] = {0, 1, 2, 3};
8538 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8539 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8541 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8544 if (M != -1 && M == FixIdx)
8546 else if (M != -1 && M == FixFreeIdx)
8549 if (NumFlippedBToBInputs != 0) {
8551 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8552 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8554 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8556 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8557 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8562 int PSHUFDMask[] = {0, 1, 2, 3};
8563 PSHUFDMask[ADWord] = BDWord;
8564 PSHUFDMask[BDWord] = ADWord;
8565 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8566 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8567 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8568 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8570 // Adjust the mask to match the new locations of A and B.
8572 if (M != -1 && M/2 == ADWord)
8573 M = 2 * BDWord + M % 2;
8574 else if (M != -1 && M/2 == BDWord)
8575 M = 2 * ADWord + M % 2;
8577 // Recurse back into this routine to re-compute state now that this isn't
8578 // a 3 and 1 problem.
8579 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8582 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8583 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8584 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8585 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8587 // At this point there are at most two inputs to the low and high halves from
8588 // each half. That means the inputs can always be grouped into dwords and
8589 // those dwords can then be moved to the correct half with a dword shuffle.
8590 // We use at most one low and one high word shuffle to collect these paired
8591 // inputs into dwords, and finally a dword shuffle to place them.
8592 int PSHUFLMask[4] = {-1, -1, -1, -1};
8593 int PSHUFHMask[4] = {-1, -1, -1, -1};
8594 int PSHUFDMask[4] = {-1, -1, -1, -1};
8596 // First fix the masks for all the inputs that are staying in their
8597 // original halves. This will then dictate the targets of the cross-half
8599 auto fixInPlaceInputs =
8600 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8601 MutableArrayRef<int> SourceHalfMask,
8602 MutableArrayRef<int> HalfMask, int HalfOffset) {
8603 if (InPlaceInputs.empty())
8605 if (InPlaceInputs.size() == 1) {
8606 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8607 InPlaceInputs[0] - HalfOffset;
8608 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8611 if (IncomingInputs.empty()) {
8612 // Just fix all of the in place inputs.
8613 for (int Input : InPlaceInputs) {
8614 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8615 PSHUFDMask[Input / 2] = Input / 2;
8620 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8621 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8622 InPlaceInputs[0] - HalfOffset;
8623 // Put the second input next to the first so that they are packed into
8624 // a dword. We find the adjacent index by toggling the low bit.
8625 int AdjIndex = InPlaceInputs[0] ^ 1;
8626 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8627 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8628 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8630 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8631 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8633 // Now gather the cross-half inputs and place them into a free dword of
8634 // their target half.
8635 // FIXME: This operation could almost certainly be simplified dramatically to
8636 // look more like the 3-1 fixing operation.
8637 auto moveInputsToRightHalf = [&PSHUFDMask](
8638 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8639 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8640 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8642 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8643 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8645 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8647 int LowWord = Word & ~1;
8648 int HighWord = Word | 1;
8649 return isWordClobbered(SourceHalfMask, LowWord) ||
8650 isWordClobbered(SourceHalfMask, HighWord);
8653 if (IncomingInputs.empty())
8656 if (ExistingInputs.empty()) {
8657 // Map any dwords with inputs from them into the right half.
8658 for (int Input : IncomingInputs) {
8659 // If the source half mask maps over the inputs, turn those into
8660 // swaps and use the swapped lane.
8661 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8662 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8663 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8664 Input - SourceOffset;
8665 // We have to swap the uses in our half mask in one sweep.
8666 for (int &M : HalfMask)
8667 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8669 else if (M == Input)
8670 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8672 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8673 Input - SourceOffset &&
8674 "Previous placement doesn't match!");
8676 // Note that this correctly re-maps both when we do a swap and when
8677 // we observe the other side of the swap above. We rely on that to
8678 // avoid swapping the members of the input list directly.
8679 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8682 // Map the input's dword into the correct half.
8683 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8684 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8686 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8688 "Previous placement doesn't match!");
8691 // And just directly shift any other-half mask elements to be same-half
8692 // as we will have mirrored the dword containing the element into the
8693 // same position within that half.
8694 for (int &M : HalfMask)
8695 if (M >= SourceOffset && M < SourceOffset + 4) {
8696 M = M - SourceOffset + DestOffset;
8697 assert(M >= 0 && "This should never wrap below zero!");
8702 // Ensure we have the input in a viable dword of its current half. This
8703 // is particularly tricky because the original position may be clobbered
8704 // by inputs being moved and *staying* in that half.
8705 if (IncomingInputs.size() == 1) {
8706 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8707 int InputFixed = std::find(std::begin(SourceHalfMask),
8708 std::end(SourceHalfMask), -1) -
8709 std::begin(SourceHalfMask) + SourceOffset;
8710 SourceHalfMask[InputFixed - SourceOffset] =
8711 IncomingInputs[0] - SourceOffset;
8712 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8714 IncomingInputs[0] = InputFixed;
8716 } else if (IncomingInputs.size() == 2) {
8717 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8718 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8719 // We have two non-adjacent or clobbered inputs we need to extract from
8720 // the source half. To do this, we need to map them into some adjacent
8721 // dword slot in the source mask.
8722 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8723 IncomingInputs[1] - SourceOffset};
8725 // If there is a free slot in the source half mask adjacent to one of
8726 // the inputs, place the other input in it. We use (Index XOR 1) to
8727 // compute an adjacent index.
8728 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8729 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8730 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8731 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8732 InputsFixed[1] = InputsFixed[0] ^ 1;
8733 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8734 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8735 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8736 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8737 InputsFixed[0] = InputsFixed[1] ^ 1;
8738 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8739 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8740 // The two inputs are in the same DWord but it is clobbered and the
8741 // adjacent DWord isn't used at all. Move both inputs to the free
8743 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8744 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8745 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8746 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8748 // The only way we hit this point is if there is no clobbering
8749 // (because there are no off-half inputs to this half) and there is no
8750 // free slot adjacent to one of the inputs. In this case, we have to
8751 // swap an input with a non-input.
8752 for (int i = 0; i < 4; ++i)
8753 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8754 "We can't handle any clobbers here!");
8755 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8756 "Cannot have adjacent inputs here!");
8758 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8759 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8761 // We also have to update the final source mask in this case because
8762 // it may need to undo the above swap.
8763 for (int &M : FinalSourceHalfMask)
8764 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8765 M = InputsFixed[1] + SourceOffset;
8766 else if (M == InputsFixed[1] + SourceOffset)
8767 M = (InputsFixed[0] ^ 1) + SourceOffset;
8769 InputsFixed[1] = InputsFixed[0] ^ 1;
8772 // Point everything at the fixed inputs.
8773 for (int &M : HalfMask)
8774 if (M == IncomingInputs[0])
8775 M = InputsFixed[0] + SourceOffset;
8776 else if (M == IncomingInputs[1])
8777 M = InputsFixed[1] + SourceOffset;
8779 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8780 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8783 llvm_unreachable("Unhandled input size!");
8786 // Now hoist the DWord down to the right half.
8787 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8788 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8789 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8790 for (int &M : HalfMask)
8791 for (int Input : IncomingInputs)
8793 M = FreeDWord * 2 + Input % 2;
8795 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8796 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8797 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8798 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8800 // Now enact all the shuffles we've computed to move the inputs into their
8802 if (!isNoopShuffleMask(PSHUFLMask))
8803 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8804 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8805 if (!isNoopShuffleMask(PSHUFHMask))
8806 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8807 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8808 if (!isNoopShuffleMask(PSHUFDMask))
8809 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8810 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8811 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8812 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8814 // At this point, each half should contain all its inputs, and we can then
8815 // just shuffle them into their final position.
8816 assert(std::count_if(LoMask.begin(), LoMask.end(),
8817 [](int M) { return M >= 4; }) == 0 &&
8818 "Failed to lift all the high half inputs to the low mask!");
8819 assert(std::count_if(HiMask.begin(), HiMask.end(),
8820 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8821 "Failed to lift all the low half inputs to the high mask!");
8823 // Do a half shuffle for the low mask.
8824 if (!isNoopShuffleMask(LoMask))
8825 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8826 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8828 // Do a half shuffle with the high mask after shifting its values down.
8829 for (int &M : HiMask)
8832 if (!isNoopShuffleMask(HiMask))
8833 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8834 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8839 /// \brief Detect whether the mask pattern should be lowered through
8842 /// This essentially tests whether viewing the mask as an interleaving of two
8843 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8844 /// lowering it through interleaving is a significantly better strategy.
8845 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8846 int NumEvenInputs[2] = {0, 0};
8847 int NumOddInputs[2] = {0, 0};
8848 int NumLoInputs[2] = {0, 0};
8849 int NumHiInputs[2] = {0, 0};
8850 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8854 int InputIdx = Mask[i] >= Size;
8857 ++NumLoInputs[InputIdx];
8859 ++NumHiInputs[InputIdx];
8862 ++NumEvenInputs[InputIdx];
8864 ++NumOddInputs[InputIdx];
8867 // The minimum number of cross-input results for both the interleaved and
8868 // split cases. If interleaving results in fewer cross-input results, return
8870 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8871 NumEvenInputs[0] + NumOddInputs[1]);
8872 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8873 NumLoInputs[0] + NumHiInputs[1]);
8874 return InterleavedCrosses < SplitCrosses;
8877 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8879 /// This strategy only works when the inputs from each vector fit into a single
8880 /// half of that vector, and generally there are not so many inputs as to leave
8881 /// the in-place shuffles required highly constrained (and thus expensive). It
8882 /// shifts all the inputs into a single side of both input vectors and then
8883 /// uses an unpack to interleave these inputs in a single vector. At that
8884 /// point, we will fall back on the generic single input shuffle lowering.
8885 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8887 MutableArrayRef<int> Mask,
8888 const X86Subtarget *Subtarget,
8889 SelectionDAG &DAG) {
8890 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8891 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8892 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8893 for (int i = 0; i < 8; ++i)
8894 if (Mask[i] >= 0 && Mask[i] < 4)
8895 LoV1Inputs.push_back(i);
8896 else if (Mask[i] >= 4 && Mask[i] < 8)
8897 HiV1Inputs.push_back(i);
8898 else if (Mask[i] >= 8 && Mask[i] < 12)
8899 LoV2Inputs.push_back(i);
8900 else if (Mask[i] >= 12)
8901 HiV2Inputs.push_back(i);
8903 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8904 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8907 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8908 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8909 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8911 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8912 HiV1Inputs.size() + HiV2Inputs.size();
8914 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8915 ArrayRef<int> HiInputs, bool MoveToLo,
8917 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8918 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8919 if (BadInputs.empty())
8922 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8923 int MoveOffset = MoveToLo ? 0 : 4;
8925 if (GoodInputs.empty()) {
8926 for (int BadInput : BadInputs) {
8927 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8928 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8931 if (GoodInputs.size() == 2) {
8932 // If the low inputs are spread across two dwords, pack them into
8934 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8935 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8936 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8937 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8939 // Otherwise pin the good inputs.
8940 for (int GoodInput : GoodInputs)
8941 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8944 if (BadInputs.size() == 2) {
8945 // If we have two bad inputs then there may be either one or two good
8946 // inputs fixed in place. Find a fixed input, and then find the *other*
8947 // two adjacent indices by using modular arithmetic.
8949 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8950 [](int M) { return M >= 0; }) -
8951 std::begin(MoveMask);
8953 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8954 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8955 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8956 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8957 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8958 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8959 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8961 assert(BadInputs.size() == 1 && "All sizes handled");
8962 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8963 std::end(MoveMask), -1) -
8964 std::begin(MoveMask);
8965 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8966 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8970 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8973 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8975 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8978 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8979 // cross-half traffic in the final shuffle.
8981 // Munge the mask to be a single-input mask after the unpack merges the
8985 M = 2 * (M % 4) + (M / 8);
8987 return DAG.getVectorShuffle(
8988 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8989 DL, MVT::v8i16, V1, V2),
8990 DAG.getUNDEF(MVT::v8i16), Mask);
8993 /// \brief Generic lowering of 8-lane i16 shuffles.
8995 /// This handles both single-input shuffles and combined shuffle/blends with
8996 /// two inputs. The single input shuffles are immediately delegated to
8997 /// a dedicated lowering routine.
8999 /// The blends are lowered in one of three fundamental ways. If there are few
9000 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9001 /// of the input is significantly cheaper when lowered as an interleaving of
9002 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9003 /// halves of the inputs separately (making them have relatively few inputs)
9004 /// and then concatenate them.
9005 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9006 const X86Subtarget *Subtarget,
9007 SelectionDAG &DAG) {
9009 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9010 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9011 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9012 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9013 ArrayRef<int> OrigMask = SVOp->getMask();
9014 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9015 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9016 MutableArrayRef<int> Mask(MaskStorage);
9018 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9020 // Whenever we can lower this as a zext, that instruction is strictly faster
9021 // than any alternative.
9022 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9023 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9026 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9027 auto isV2 = [](int M) { return M >= 8; };
9029 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9030 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9032 if (NumV2Inputs == 0)
9033 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9035 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9036 "to be V1-input shuffles.");
9038 // There are special ways we can lower some single-element blends.
9039 if (NumV2Inputs == 1)
9040 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9041 Mask, Subtarget, DAG))
9044 if (Subtarget->hasSSE41())
9045 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9049 // Try to use rotation instructions if available.
9050 if (Subtarget->hasSSSE3())
9051 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9052 DL, MVT::v8i16, V1, V2, Mask, DAG))
9055 if (NumV1Inputs + NumV2Inputs <= 4)
9056 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9058 // Check whether an interleaving lowering is likely to be more efficient.
9059 // This isn't perfect but it is a strong heuristic that tends to work well on
9060 // the kinds of shuffles that show up in practice.
9062 // FIXME: Handle 1x, 2x, and 4x interleaving.
9063 if (shouldLowerAsInterleaving(Mask)) {
9064 // FIXME: Figure out whether we should pack these into the low or high
9067 int EMask[8], OMask[8];
9068 for (int i = 0; i < 4; ++i) {
9069 EMask[i] = Mask[2*i];
9070 OMask[i] = Mask[2*i + 1];
9075 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9076 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9078 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9081 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9082 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9084 for (int i = 0; i < 4; ++i) {
9085 LoBlendMask[i] = Mask[i];
9086 HiBlendMask[i] = Mask[i + 4];
9089 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9090 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9091 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9092 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9094 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9095 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9098 /// \brief Check whether a compaction lowering can be done by dropping even
9099 /// elements and compute how many times even elements must be dropped.
9101 /// This handles shuffles which take every Nth element where N is a power of
9102 /// two. Example shuffle masks:
9104 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9105 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9106 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9107 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9108 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9109 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9111 /// Any of these lanes can of course be undef.
9113 /// This routine only supports N <= 3.
9114 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9117 /// \returns N above, or the number of times even elements must be dropped if
9118 /// there is such a number. Otherwise returns zero.
9119 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9120 // Figure out whether we're looping over two inputs or just one.
9121 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9123 // The modulus for the shuffle vector entries is based on whether this is
9124 // a single input or not.
9125 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9126 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9127 "We should only be called with masks with a power-of-2 size!");
9129 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9131 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9132 // and 2^3 simultaneously. This is because we may have ambiguity with
9133 // partially undef inputs.
9134 bool ViableForN[3] = {true, true, true};
9136 for (int i = 0, e = Mask.size(); i < e; ++i) {
9137 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9142 bool IsAnyViable = false;
9143 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9144 if (ViableForN[j]) {
9147 // The shuffle mask must be equal to (i * 2^N) % M.
9148 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9151 ViableForN[j] = false;
9153 // Early exit if we exhaust the possible powers of two.
9158 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9162 // Return 0 as there is no viable power of two.
9166 /// \brief Generic lowering of v16i8 shuffles.
9168 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9169 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9170 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9171 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9173 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9174 const X86Subtarget *Subtarget,
9175 SelectionDAG &DAG) {
9177 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9178 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9179 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9181 ArrayRef<int> OrigMask = SVOp->getMask();
9182 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9184 // Try to use rotation instructions if available.
9185 if (Subtarget->hasSSSE3())
9186 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9187 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9190 // Try to use a zext lowering.
9191 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9192 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9195 int MaskStorage[16] = {
9196 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9197 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9198 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9199 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9200 MutableArrayRef<int> Mask(MaskStorage);
9201 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9202 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9205 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9207 // For single-input shuffles, there are some nicer lowering tricks we can use.
9208 if (NumV2Elements == 0) {
9209 // Check for being able to broadcast a single element.
9210 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9211 Mask, Subtarget, DAG))
9214 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9215 // Notably, this handles splat and partial-splat shuffles more efficiently.
9216 // However, it only makes sense if the pre-duplication shuffle simplifies
9217 // things significantly. Currently, this means we need to be able to
9218 // express the pre-duplication shuffle as an i16 shuffle.
9220 // FIXME: We should check for other patterns which can be widened into an
9221 // i16 shuffle as well.
9222 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9223 for (int i = 0; i < 16; i += 2)
9224 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9229 auto tryToWidenViaDuplication = [&]() -> SDValue {
9230 if (!canWidenViaDuplication(Mask))
9232 SmallVector<int, 4> LoInputs;
9233 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9234 [](int M) { return M >= 0 && M < 8; });
9235 std::sort(LoInputs.begin(), LoInputs.end());
9236 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9238 SmallVector<int, 4> HiInputs;
9239 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9240 [](int M) { return M >= 8; });
9241 std::sort(HiInputs.begin(), HiInputs.end());
9242 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9245 bool TargetLo = LoInputs.size() >= HiInputs.size();
9246 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9247 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9249 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9250 SmallDenseMap<int, int, 8> LaneMap;
9251 for (int I : InPlaceInputs) {
9252 PreDupI16Shuffle[I/2] = I/2;
9255 int j = TargetLo ? 0 : 4, je = j + 4;
9256 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9257 // Check if j is already a shuffle of this input. This happens when
9258 // there are two adjacent bytes after we move the low one.
9259 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9260 // If we haven't yet mapped the input, search for a slot into which
9262 while (j < je && PreDupI16Shuffle[j] != -1)
9266 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9269 // Map this input with the i16 shuffle.
9270 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9273 // Update the lane map based on the mapping we ended up with.
9274 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9277 ISD::BITCAST, DL, MVT::v16i8,
9278 DAG.getVectorShuffle(MVT::v8i16, DL,
9279 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9280 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9282 // Unpack the bytes to form the i16s that will be shuffled into place.
9283 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9284 MVT::v16i8, V1, V1);
9286 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9287 for (int i = 0; i < 16; ++i)
9288 if (Mask[i] != -1) {
9289 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9290 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9291 if (PostDupI16Shuffle[i / 2] == -1)
9292 PostDupI16Shuffle[i / 2] = MappedMask;
9294 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9295 "Conflicting entrties in the original shuffle!");
9298 ISD::BITCAST, DL, MVT::v16i8,
9299 DAG.getVectorShuffle(MVT::v8i16, DL,
9300 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9301 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9303 if (SDValue V = tryToWidenViaDuplication())
9307 // Check whether an interleaving lowering is likely to be more efficient.
9308 // This isn't perfect but it is a strong heuristic that tends to work well on
9309 // the kinds of shuffles that show up in practice.
9311 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9312 if (shouldLowerAsInterleaving(Mask)) {
9313 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9314 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9316 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9317 return (M >= 8 && M < 16) || M >= 24;
9319 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9320 -1, -1, -1, -1, -1, -1, -1, -1};
9321 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9322 -1, -1, -1, -1, -1, -1, -1, -1};
9323 bool UnpackLo = NumLoHalf >= NumHiHalf;
9324 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9325 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9326 for (int i = 0; i < 8; ++i) {
9327 TargetEMask[i] = Mask[2 * i];
9328 TargetOMask[i] = Mask[2 * i + 1];
9331 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9332 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9334 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9335 MVT::v16i8, Evens, Odds);
9338 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9339 // with PSHUFB. It is important to do this before we attempt to generate any
9340 // blends but after all of the single-input lowerings. If the single input
9341 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9342 // want to preserve that and we can DAG combine any longer sequences into
9343 // a PSHUFB in the end. But once we start blending from multiple inputs,
9344 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9345 // and there are *very* few patterns that would actually be faster than the
9346 // PSHUFB approach because of its ability to zero lanes.
9348 // FIXME: The only exceptions to the above are blends which are exact
9349 // interleavings with direct instructions supporting them. We currently don't
9350 // handle those well here.
9351 if (Subtarget->hasSSSE3()) {
9354 for (int i = 0; i < 16; ++i)
9355 if (Mask[i] == -1) {
9356 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9358 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9360 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9362 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9363 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9364 if (isSingleInputShuffleMask(Mask))
9365 return V1; // Single inputs are easy.
9367 // Otherwise, blend the two.
9368 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9369 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9370 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9373 // There are special ways we can lower some single-element blends.
9374 if (NumV2Elements == 1)
9375 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9376 Mask, Subtarget, DAG))
9379 // Check whether a compaction lowering can be done. This handles shuffles
9380 // which take every Nth element for some even N. See the helper function for
9383 // We special case these as they can be particularly efficiently handled with
9384 // the PACKUSB instruction on x86 and they show up in common patterns of
9385 // rearranging bytes to truncate wide elements.
9386 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9387 // NumEvenDrops is the power of two stride of the elements. Another way of
9388 // thinking about it is that we need to drop the even elements this many
9389 // times to get the original input.
9390 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9392 // First we need to zero all the dropped bytes.
9393 assert(NumEvenDrops <= 3 &&
9394 "No support for dropping even elements more than 3 times.");
9395 // We use the mask type to pick which bytes are preserved based on how many
9396 // elements are dropped.
9397 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9398 SDValue ByteClearMask =
9399 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9400 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9401 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9403 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9405 // Now pack things back together.
9406 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9407 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9408 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9409 for (int i = 1; i < NumEvenDrops; ++i) {
9410 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9411 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9417 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9418 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9419 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9420 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9422 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9423 MutableArrayRef<int> V1HalfBlendMask,
9424 MutableArrayRef<int> V2HalfBlendMask) {
9425 for (int i = 0; i < 8; ++i)
9426 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9427 V1HalfBlendMask[i] = HalfMask[i];
9429 } else if (HalfMask[i] >= 16) {
9430 V2HalfBlendMask[i] = HalfMask[i] - 16;
9431 HalfMask[i] = i + 8;
9434 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9435 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9437 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9439 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9440 MutableArrayRef<int> HiBlendMask) {
9442 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9443 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9445 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9446 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9447 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9448 [](int M) { return M >= 0 && M % 2 == 1; })) {
9449 // Use a mask to drop the high bytes.
9450 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9451 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9452 DAG.getConstant(0x00FF, MVT::v8i16));
9454 // This will be a single vector shuffle instead of a blend so nuke V2.
9455 V2 = DAG.getUNDEF(MVT::v8i16);
9457 // Squash the masks to point directly into V1.
9458 for (int &M : LoBlendMask)
9461 for (int &M : HiBlendMask)
9465 // Otherwise just unpack the low half of V into V1 and the high half into
9466 // V2 so that we can blend them as i16s.
9467 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9468 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9469 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9470 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9473 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9474 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9475 return std::make_pair(BlendedLo, BlendedHi);
9477 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9478 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9479 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9481 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9482 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9484 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9487 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9489 /// This routine breaks down the specific type of 128-bit shuffle and
9490 /// dispatches to the lowering routines accordingly.
9491 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9492 MVT VT, const X86Subtarget *Subtarget,
9493 SelectionDAG &DAG) {
9494 switch (VT.SimpleTy) {
9496 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9498 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9500 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9502 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9504 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9506 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9509 llvm_unreachable("Unimplemented!");
9513 /// \brief Helper function to test whether a shuffle mask could be
9514 /// simplified by widening the elements being shuffled.
9516 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9517 /// leaves it in an unspecified state.
9519 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9520 /// shuffle masks. The latter have the special property of a '-2' representing
9521 /// a zero-ed lane of a vector.
9522 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9523 SmallVectorImpl<int> &WidenedMask) {
9524 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9525 // If both elements are undef, its trivial.
9526 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9527 WidenedMask.push_back(SM_SentinelUndef);
9531 // Check for an undef mask and a mask value properly aligned to fit with
9532 // a pair of values. If we find such a case, use the non-undef mask's value.
9533 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9534 WidenedMask.push_back(Mask[i + 1] / 2);
9537 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9538 WidenedMask.push_back(Mask[i] / 2);
9542 // When zeroing, we need to spread the zeroing across both lanes to widen.
9543 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9544 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9545 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9546 WidenedMask.push_back(SM_SentinelZero);
9552 // Finally check if the two mask values are adjacent and aligned with
9554 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9555 WidenedMask.push_back(Mask[i] / 2);
9559 // Otherwise we can't safely widen the elements used in this shuffle.
9562 assert(WidenedMask.size() == Mask.size() / 2 &&
9563 "Incorrect size of mask after widening the elements!");
9568 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9570 /// This routine just extracts two subvectors, shuffles them independently, and
9571 /// then concatenates them back together. This should work effectively with all
9572 /// AVX vector shuffle types.
9573 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9574 SDValue V2, ArrayRef<int> Mask,
9575 SelectionDAG &DAG) {
9576 assert(VT.getSizeInBits() >= 256 &&
9577 "Only for 256-bit or wider vector shuffles!");
9578 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9579 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9581 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9582 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9584 int NumElements = VT.getVectorNumElements();
9585 int SplitNumElements = NumElements / 2;
9586 MVT ScalarVT = VT.getScalarType();
9587 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9589 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9590 DAG.getIntPtrConstant(0));
9591 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9592 DAG.getIntPtrConstant(SplitNumElements));
9593 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9594 DAG.getIntPtrConstant(0));
9595 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9596 DAG.getIntPtrConstant(SplitNumElements));
9598 // Now create two 4-way blends of these half-width vectors.
9599 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9600 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9601 for (int i = 0; i < SplitNumElements; ++i) {
9602 int M = HalfMask[i];
9603 if (M >= NumElements) {
9604 V2BlendMask.push_back(M - NumElements);
9605 V1BlendMask.push_back(-1);
9606 BlendMask.push_back(SplitNumElements + i);
9607 } else if (M >= 0) {
9608 V2BlendMask.push_back(-1);
9609 V1BlendMask.push_back(M);
9610 BlendMask.push_back(i);
9612 V2BlendMask.push_back(-1);
9613 V1BlendMask.push_back(-1);
9614 BlendMask.push_back(-1);
9618 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9620 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9621 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9623 SDValue Lo = HalfBlend(LoMask);
9624 SDValue Hi = HalfBlend(HiMask);
9625 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9628 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9629 /// a permutation and blend of those lanes.
9631 /// This essentially blends the out-of-lane inputs to each lane into the lane
9632 /// from a permuted copy of the vector. This lowering strategy results in four
9633 /// instructions in the worst case for a single-input cross lane shuffle which
9634 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9635 /// of. Special cases for each particular shuffle pattern should be handled
9636 /// prior to trying this lowering.
9637 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9638 SDValue V1, SDValue V2,
9640 SelectionDAG &DAG) {
9641 // FIXME: This should probably be generalized for 512-bit vectors as well.
9642 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9643 int LaneSize = Mask.size() / 2;
9645 // If there are only inputs from one 128-bit lane, splitting will in fact be
9646 // less expensive. The flags track wether the given lane contains an element
9647 // that crosses to another lane.
9648 bool LaneCrossing[2] = {false, false};
9649 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9650 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9651 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9652 if (!LaneCrossing[0] || !LaneCrossing[1])
9653 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9655 if (isSingleInputShuffleMask(Mask)) {
9656 SmallVector<int, 32> FlippedBlendMask;
9657 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9658 FlippedBlendMask.push_back(
9659 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9661 : Mask[i] % LaneSize +
9662 (i / LaneSize) * LaneSize + Size));
9664 // Flip the vector, and blend the results which should now be in-lane. The
9665 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9666 // 5 for the high source. The value 3 selects the high half of source 2 and
9667 // the value 2 selects the low half of source 2. We only use source 2 to
9668 // allow folding it into a memory operand.
9669 unsigned PERMMask = 3 | 2 << 4;
9670 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9671 V1, DAG.getConstant(PERMMask, MVT::i8));
9672 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9675 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9676 // will be handled by the above logic and a blend of the results, much like
9677 // other patterns in AVX.
9678 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9681 /// \brief Handle lowering 2-lane 128-bit shuffles.
9682 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9683 SDValue V2, ArrayRef<int> Mask,
9684 const X86Subtarget *Subtarget,
9685 SelectionDAG &DAG) {
9686 // Blends are faster and handle all the non-lane-crossing cases.
9687 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9691 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9692 VT.getVectorNumElements() / 2);
9693 // Check for patterns which can be matched with a single insert of a 128-bit
9695 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9696 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9697 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9698 DAG.getIntPtrConstant(0));
9699 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9700 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9701 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9703 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9704 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9705 DAG.getIntPtrConstant(0));
9706 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9707 DAG.getIntPtrConstant(2));
9708 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9711 // Otherwise form a 128-bit permutation.
9712 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9713 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9714 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9715 DAG.getConstant(PermMask, MVT::i8));
9718 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9720 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9721 /// isn't available.
9722 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9723 const X86Subtarget *Subtarget,
9724 SelectionDAG &DAG) {
9726 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9727 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9728 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9729 ArrayRef<int> Mask = SVOp->getMask();
9730 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9732 SmallVector<int, 4> WidenedMask;
9733 if (canWidenShuffleElements(Mask, WidenedMask))
9734 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9737 if (isSingleInputShuffleMask(Mask)) {
9738 // Check for being able to broadcast a single element.
9739 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9740 Mask, Subtarget, DAG))
9743 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9744 // Non-half-crossing single input shuffles can be lowerid with an
9745 // interleaved permutation.
9746 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9747 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9748 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9749 DAG.getConstant(VPERMILPMask, MVT::i8));
9752 // With AVX2 we have direct support for this permutation.
9753 if (Subtarget->hasAVX2())
9754 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9755 getV4X86ShuffleImm8ForMask(Mask, DAG));
9757 // Otherwise, fall back.
9758 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9762 // X86 has dedicated unpack instructions that can handle specific blend
9763 // operations: UNPCKH and UNPCKL.
9764 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9765 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9766 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9767 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9769 // If we have a single input to the zero element, insert that into V1 if we
9770 // can do so cheaply.
9772 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9773 if (NumV2Elements == 1 && Mask[0] >= 4)
9774 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9775 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9778 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9782 // Check if the blend happens to exactly fit that of SHUFPD.
9783 if ((Mask[0] == -1 || Mask[0] < 2) &&
9784 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9785 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9786 (Mask[3] == -1 || Mask[3] >= 6)) {
9787 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9788 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9789 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9790 DAG.getConstant(SHUFPDMask, MVT::i8));
9792 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9793 (Mask[1] == -1 || Mask[1] < 2) &&
9794 (Mask[2] == -1 || Mask[2] >= 6) &&
9795 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9796 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9797 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9798 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9799 DAG.getConstant(SHUFPDMask, MVT::i8));
9802 // Otherwise fall back on generic blend lowering.
9803 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9807 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9809 /// This routine is only called when we have AVX2 and thus a reasonable
9810 /// instruction set for v4i64 shuffling..
9811 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9812 const X86Subtarget *Subtarget,
9813 SelectionDAG &DAG) {
9815 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9816 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9817 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9818 ArrayRef<int> Mask = SVOp->getMask();
9819 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9820 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9822 SmallVector<int, 4> WidenedMask;
9823 if (canWidenShuffleElements(Mask, WidenedMask))
9824 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9827 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9831 // Check for being able to broadcast a single element.
9832 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9833 Mask, Subtarget, DAG))
9836 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9837 // use lower latency instructions that will operate on both 128-bit lanes.
9838 SmallVector<int, 2> RepeatedMask;
9839 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9840 if (isSingleInputShuffleMask(Mask)) {
9841 int PSHUFDMask[] = {-1, -1, -1, -1};
9842 for (int i = 0; i < 2; ++i)
9843 if (RepeatedMask[i] >= 0) {
9844 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9845 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9848 ISD::BITCAST, DL, MVT::v4i64,
9849 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9850 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9851 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9854 // Use dedicated unpack instructions for masks that match their pattern.
9855 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9856 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9857 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9858 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9861 // AVX2 provides a direct instruction for permuting a single input across
9863 if (isSingleInputShuffleMask(Mask))
9864 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9865 getV4X86ShuffleImm8ForMask(Mask, DAG));
9867 // Otherwise fall back on generic blend lowering.
9868 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9872 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9874 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9875 /// isn't available.
9876 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9877 const X86Subtarget *Subtarget,
9878 SelectionDAG &DAG) {
9880 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9881 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9882 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9883 ArrayRef<int> Mask = SVOp->getMask();
9884 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9886 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9890 // Check for being able to broadcast a single element.
9891 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9892 Mask, Subtarget, DAG))
9895 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9896 // options to efficiently lower the shuffle.
9897 SmallVector<int, 4> RepeatedMask;
9898 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9899 assert(RepeatedMask.size() == 4 &&
9900 "Repeated masks must be half the mask width!");
9901 if (isSingleInputShuffleMask(Mask))
9902 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9903 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9905 // Use dedicated unpack instructions for masks that match their pattern.
9906 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9907 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9908 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9909 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9911 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9912 // have already handled any direct blends. We also need to squash the
9913 // repeated mask into a simulated v4f32 mask.
9914 for (int i = 0; i < 4; ++i)
9915 if (RepeatedMask[i] >= 8)
9916 RepeatedMask[i] -= 4;
9917 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9920 // If we have a single input shuffle with different shuffle patterns in the
9921 // two 128-bit lanes use the variable mask to VPERMILPS.
9922 if (isSingleInputShuffleMask(Mask)) {
9923 SDValue VPermMask[8];
9924 for (int i = 0; i < 8; ++i)
9925 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9926 : DAG.getConstant(Mask[i], MVT::i32);
9927 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9929 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9930 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9932 if (Subtarget->hasAVX2())
9933 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9934 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9935 DAG.getNode(ISD::BUILD_VECTOR, DL,
9936 MVT::v8i32, VPermMask)),
9939 // Otherwise, fall back.
9940 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9944 // Otherwise fall back on generic blend lowering.
9945 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9949 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9951 /// This routine is only called when we have AVX2 and thus a reasonable
9952 /// instruction set for v8i32 shuffling..
9953 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9954 const X86Subtarget *Subtarget,
9955 SelectionDAG &DAG) {
9957 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9958 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9959 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9960 ArrayRef<int> Mask = SVOp->getMask();
9961 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9962 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9964 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9968 // Check for being able to broadcast a single element.
9969 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9970 Mask, Subtarget, DAG))
9973 // If the shuffle mask is repeated in each 128-bit lane we can use more
9974 // efficient instructions that mirror the shuffles across the two 128-bit
9976 SmallVector<int, 4> RepeatedMask;
9977 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9978 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9979 if (isSingleInputShuffleMask(Mask))
9980 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9981 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9983 // Use dedicated unpack instructions for masks that match their pattern.
9984 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9985 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9986 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9987 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9990 // If the shuffle patterns aren't repeated but it is a single input, directly
9991 // generate a cross-lane VPERMD instruction.
9992 if (isSingleInputShuffleMask(Mask)) {
9993 SDValue VPermMask[8];
9994 for (int i = 0; i < 8; ++i)
9995 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9996 : DAG.getConstant(Mask[i], MVT::i32);
9998 X86ISD::VPERMV, DL, MVT::v8i32,
9999 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10002 // Otherwise fall back on generic blend lowering.
10003 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10007 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10009 /// This routine is only called when we have AVX2 and thus a reasonable
10010 /// instruction set for v16i16 shuffling..
10011 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10012 const X86Subtarget *Subtarget,
10013 SelectionDAG &DAG) {
10015 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10016 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10017 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10018 ArrayRef<int> Mask = SVOp->getMask();
10019 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10020 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10022 // Check for being able to broadcast a single element.
10023 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10024 Mask, Subtarget, DAG))
10027 // There are no generalized cross-lane shuffle operations available on i16
10029 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10030 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10033 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10037 // Use dedicated unpack instructions for masks that match their pattern.
10038 if (isShuffleEquivalent(Mask,
10039 // First 128-bit lane:
10040 0, 16, 1, 17, 2, 18, 3, 19,
10041 // Second 128-bit lane:
10042 8, 24, 9, 25, 10, 26, 11, 27))
10043 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10044 if (isShuffleEquivalent(Mask,
10045 // First 128-bit lane:
10046 4, 20, 5, 21, 6, 22, 7, 23,
10047 // Second 128-bit lane:
10048 12, 28, 13, 29, 14, 30, 15, 31))
10049 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10051 if (isSingleInputShuffleMask(Mask)) {
10052 SDValue PSHUFBMask[32];
10053 for (int i = 0; i < 16; ++i) {
10054 if (Mask[i] == -1) {
10055 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10059 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10060 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10061 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10062 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10064 return DAG.getNode(
10065 ISD::BITCAST, DL, MVT::v16i16,
10067 X86ISD::PSHUFB, DL, MVT::v32i8,
10068 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10069 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10072 // Otherwise fall back on generic blend lowering.
10073 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
10077 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10079 /// This routine is only called when we have AVX2 and thus a reasonable
10080 /// instruction set for v32i8 shuffling..
10081 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10082 const X86Subtarget *Subtarget,
10083 SelectionDAG &DAG) {
10085 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10086 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10087 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10088 ArrayRef<int> Mask = SVOp->getMask();
10089 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10090 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10092 // Check for being able to broadcast a single element.
10093 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10094 Mask, Subtarget, DAG))
10097 // There are no generalized cross-lane shuffle operations available on i8
10099 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10100 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10103 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10107 // Use dedicated unpack instructions for masks that match their pattern.
10108 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10110 if (isShuffleEquivalent(
10112 // First 128-bit lane:
10113 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10114 // Second 128-bit lane:
10115 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10116 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10117 if (isShuffleEquivalent(
10119 // First 128-bit lane:
10120 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10121 // Second 128-bit lane:
10122 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10123 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10125 if (isSingleInputShuffleMask(Mask)) {
10126 SDValue PSHUFBMask[32];
10127 for (int i = 0; i < 32; ++i)
10130 ? DAG.getUNDEF(MVT::i8)
10131 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10133 return DAG.getNode(
10134 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10135 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10138 // Otherwise fall back on generic blend lowering.
10139 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
10143 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10145 /// This routine either breaks down the specific type of a 256-bit x86 vector
10146 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10147 /// together based on the available instructions.
10148 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10149 MVT VT, const X86Subtarget *Subtarget,
10150 SelectionDAG &DAG) {
10152 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10153 ArrayRef<int> Mask = SVOp->getMask();
10155 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10156 // check for those subtargets here and avoid much of the subtarget querying in
10157 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10158 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10159 // floating point types there eventually, just immediately cast everything to
10160 // a float and operate entirely in that domain.
10161 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10162 int ElementBits = VT.getScalarSizeInBits();
10163 if (ElementBits < 32)
10164 // No floating point type available, decompose into 128-bit vectors.
10165 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10167 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10168 VT.getVectorNumElements());
10169 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10170 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10171 return DAG.getNode(ISD::BITCAST, DL, VT,
10172 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10175 switch (VT.SimpleTy) {
10177 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10179 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10181 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10183 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10185 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10187 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10190 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10194 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10195 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10196 const X86Subtarget *Subtarget,
10197 SelectionDAG &DAG) {
10199 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10200 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10202 ArrayRef<int> Mask = SVOp->getMask();
10203 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10205 // FIXME: Implement direct support for this type!
10206 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10209 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10210 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10211 const X86Subtarget *Subtarget,
10212 SelectionDAG &DAG) {
10214 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10215 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10216 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10217 ArrayRef<int> Mask = SVOp->getMask();
10218 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10220 // FIXME: Implement direct support for this type!
10221 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10224 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10225 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10226 const X86Subtarget *Subtarget,
10227 SelectionDAG &DAG) {
10229 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10230 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10231 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10232 ArrayRef<int> Mask = SVOp->getMask();
10233 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10235 // FIXME: Implement direct support for this type!
10236 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10239 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10240 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10241 const X86Subtarget *Subtarget,
10242 SelectionDAG &DAG) {
10244 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10245 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10247 ArrayRef<int> Mask = SVOp->getMask();
10248 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10250 // FIXME: Implement direct support for this type!
10251 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10254 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10255 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10256 const X86Subtarget *Subtarget,
10257 SelectionDAG &DAG) {
10259 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10260 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10261 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10262 ArrayRef<int> Mask = SVOp->getMask();
10263 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10264 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10266 // FIXME: Implement direct support for this type!
10267 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10270 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10271 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10272 const X86Subtarget *Subtarget,
10273 SelectionDAG &DAG) {
10275 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10276 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10277 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10278 ArrayRef<int> Mask = SVOp->getMask();
10279 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10280 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10282 // FIXME: Implement direct support for this type!
10283 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10286 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10288 /// This routine either breaks down the specific type of a 512-bit x86 vector
10289 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10290 /// together based on the available instructions.
10291 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10292 MVT VT, const X86Subtarget *Subtarget,
10293 SelectionDAG &DAG) {
10295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10296 ArrayRef<int> Mask = SVOp->getMask();
10297 assert(Subtarget->hasAVX512() &&
10298 "Cannot lower 512-bit vectors w/ basic ISA!");
10300 // Check for being able to broadcast a single element.
10301 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10302 Mask, Subtarget, DAG))
10305 // Dispatch to each element type for lowering. If we don't have supprot for
10306 // specific element type shuffles at 512 bits, immediately split them and
10307 // lower them. Each lowering routine of a given type is allowed to assume that
10308 // the requisite ISA extensions for that element type are available.
10309 switch (VT.SimpleTy) {
10311 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10313 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10315 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10317 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10319 if (Subtarget->hasBWI())
10320 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10323 if (Subtarget->hasBWI())
10324 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10328 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10331 // Otherwise fall back on splitting.
10332 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10335 /// \brief Top-level lowering for x86 vector shuffles.
10337 /// This handles decomposition, canonicalization, and lowering of all x86
10338 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10339 /// above in helper routines. The canonicalization attempts to widen shuffles
10340 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10341 /// s.t. only one of the two inputs needs to be tested, etc.
10342 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10343 SelectionDAG &DAG) {
10344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10345 ArrayRef<int> Mask = SVOp->getMask();
10346 SDValue V1 = Op.getOperand(0);
10347 SDValue V2 = Op.getOperand(1);
10348 MVT VT = Op.getSimpleValueType();
10349 int NumElements = VT.getVectorNumElements();
10352 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10354 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10355 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10356 if (V1IsUndef && V2IsUndef)
10357 return DAG.getUNDEF(VT);
10359 // When we create a shuffle node we put the UNDEF node to second operand,
10360 // but in some cases the first operand may be transformed to UNDEF.
10361 // In this case we should just commute the node.
10363 return DAG.getCommutedVectorShuffle(*SVOp);
10365 // Check for non-undef masks pointing at an undef vector and make the masks
10366 // undef as well. This makes it easier to match the shuffle based solely on
10370 if (M >= NumElements) {
10371 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10372 for (int &M : NewMask)
10373 if (M >= NumElements)
10375 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10378 // Try to collapse shuffles into using a vector type with fewer elements but
10379 // wider element types. We cap this to not form integers or floating point
10380 // elements wider than 64 bits, but it might be interesting to form i128
10381 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10382 SmallVector<int, 16> WidenedMask;
10383 if (VT.getScalarSizeInBits() < 64 &&
10384 canWidenShuffleElements(Mask, WidenedMask)) {
10385 MVT NewEltVT = VT.isFloatingPoint()
10386 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10387 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10388 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10389 // Make sure that the new vector type is legal. For example, v2f64 isn't
10391 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10392 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10393 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10394 return DAG.getNode(ISD::BITCAST, dl, VT,
10395 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10399 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10400 for (int M : SVOp->getMask())
10402 ++NumUndefElements;
10403 else if (M < NumElements)
10408 // Commute the shuffle as needed such that more elements come from V1 than
10409 // V2. This allows us to match the shuffle pattern strictly on how many
10410 // elements come from V1 without handling the symmetric cases.
10411 if (NumV2Elements > NumV1Elements)
10412 return DAG.getCommutedVectorShuffle(*SVOp);
10414 // When the number of V1 and V2 elements are the same, try to minimize the
10415 // number of uses of V2 in the low half of the vector. When that is tied,
10416 // ensure that the sum of indices for V1 is equal to or lower than the sum
10418 if (NumV1Elements == NumV2Elements) {
10419 int LowV1Elements = 0, LowV2Elements = 0;
10420 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10421 if (M >= NumElements)
10425 if (LowV2Elements > LowV1Elements) {
10426 return DAG.getCommutedVectorShuffle(*SVOp);
10427 } else if (LowV2Elements == LowV1Elements) {
10428 int SumV1Indices = 0, SumV2Indices = 0;
10429 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10430 if (SVOp->getMask()[i] >= NumElements)
10432 else if (SVOp->getMask()[i] >= 0)
10434 if (SumV2Indices < SumV1Indices)
10435 return DAG.getCommutedVectorShuffle(*SVOp);
10439 // For each vector width, delegate to a specialized lowering routine.
10440 if (VT.getSizeInBits() == 128)
10441 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10443 if (VT.getSizeInBits() == 256)
10444 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10446 // Force AVX-512 vectors to be scalarized for now.
10447 // FIXME: Implement AVX-512 support!
10448 if (VT.getSizeInBits() == 512)
10449 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10451 llvm_unreachable("Unimplemented!");
10455 //===----------------------------------------------------------------------===//
10456 // Legacy vector shuffle lowering
10458 // This code is the legacy code handling vector shuffles until the above
10459 // replaces its functionality and performance.
10460 //===----------------------------------------------------------------------===//
10462 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10463 bool hasInt256, unsigned *MaskOut = nullptr) {
10464 MVT EltVT = VT.getVectorElementType();
10466 // There is no blend with immediate in AVX-512.
10467 if (VT.is512BitVector())
10470 if (!hasSSE41 || EltVT == MVT::i8)
10472 if (!hasInt256 && VT == MVT::v16i16)
10475 unsigned MaskValue = 0;
10476 unsigned NumElems = VT.getVectorNumElements();
10477 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10478 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10479 unsigned NumElemsInLane = NumElems / NumLanes;
10481 // Blend for v16i16 should be symetric for the both lanes.
10482 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10484 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10485 int EltIdx = MaskVals[i];
10487 if ((EltIdx < 0 || EltIdx == (int)i) &&
10488 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10491 if (((unsigned)EltIdx == (i + NumElems)) &&
10492 (SndLaneEltIdx < 0 ||
10493 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10494 MaskValue |= (1 << i);
10500 *MaskOut = MaskValue;
10504 // Try to lower a shuffle node into a simple blend instruction.
10505 // This function assumes isBlendMask returns true for this
10506 // SuffleVectorSDNode
10507 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10508 unsigned MaskValue,
10509 const X86Subtarget *Subtarget,
10510 SelectionDAG &DAG) {
10511 MVT VT = SVOp->getSimpleValueType(0);
10512 MVT EltVT = VT.getVectorElementType();
10513 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10514 Subtarget->hasInt256() && "Trying to lower a "
10515 "VECTOR_SHUFFLE to a Blend but "
10516 "with the wrong mask"));
10517 SDValue V1 = SVOp->getOperand(0);
10518 SDValue V2 = SVOp->getOperand(1);
10520 unsigned NumElems = VT.getVectorNumElements();
10522 // Convert i32 vectors to floating point if it is not AVX2.
10523 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10525 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10526 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10528 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10529 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10532 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10533 DAG.getConstant(MaskValue, MVT::i32));
10534 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10537 /// In vector type \p VT, return true if the element at index \p InputIdx
10538 /// falls on a different 128-bit lane than \p OutputIdx.
10539 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10540 unsigned OutputIdx) {
10541 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10542 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10545 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10546 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10547 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10548 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10550 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10551 SelectionDAG &DAG) {
10552 MVT VT = V1.getSimpleValueType();
10553 assert(VT.is128BitVector() || VT.is256BitVector());
10555 MVT EltVT = VT.getVectorElementType();
10556 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10557 unsigned NumElts = VT.getVectorNumElements();
10559 SmallVector<SDValue, 32> PshufbMask;
10560 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10561 int InputIdx = MaskVals[OutputIdx];
10562 unsigned InputByteIdx;
10564 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10565 InputByteIdx = 0x80;
10567 // Cross lane is not allowed.
10568 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10570 InputByteIdx = InputIdx * EltSizeInBytes;
10571 // Index is an byte offset within the 128-bit lane.
10572 InputByteIdx &= 0xf;
10575 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10576 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10577 if (InputByteIdx != 0x80)
10582 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10584 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10585 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10586 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10589 // v8i16 shuffles - Prefer shuffles in the following order:
10590 // 1. [all] pshuflw, pshufhw, optional move
10591 // 2. [ssse3] 1 x pshufb
10592 // 3. [ssse3] 2 x pshufb + 1 x por
10593 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10595 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10596 SelectionDAG &DAG) {
10597 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10598 SDValue V1 = SVOp->getOperand(0);
10599 SDValue V2 = SVOp->getOperand(1);
10601 SmallVector<int, 8> MaskVals;
10603 // Determine if more than 1 of the words in each of the low and high quadwords
10604 // of the result come from the same quadword of one of the two inputs. Undef
10605 // mask values count as coming from any quadword, for better codegen.
10607 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10608 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10609 unsigned LoQuad[] = { 0, 0, 0, 0 };
10610 unsigned HiQuad[] = { 0, 0, 0, 0 };
10611 // Indices of quads used.
10612 std::bitset<4> InputQuads;
10613 for (unsigned i = 0; i < 8; ++i) {
10614 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10615 int EltIdx = SVOp->getMaskElt(i);
10616 MaskVals.push_back(EltIdx);
10624 ++Quad[EltIdx / 4];
10625 InputQuads.set(EltIdx / 4);
10628 int BestLoQuad = -1;
10629 unsigned MaxQuad = 1;
10630 for (unsigned i = 0; i < 4; ++i) {
10631 if (LoQuad[i] > MaxQuad) {
10633 MaxQuad = LoQuad[i];
10637 int BestHiQuad = -1;
10639 for (unsigned i = 0; i < 4; ++i) {
10640 if (HiQuad[i] > MaxQuad) {
10642 MaxQuad = HiQuad[i];
10646 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10647 // of the two input vectors, shuffle them into one input vector so only a
10648 // single pshufb instruction is necessary. If there are more than 2 input
10649 // quads, disable the next transformation since it does not help SSSE3.
10650 bool V1Used = InputQuads[0] || InputQuads[1];
10651 bool V2Used = InputQuads[2] || InputQuads[3];
10652 if (Subtarget->hasSSSE3()) {
10653 if (InputQuads.count() == 2 && V1Used && V2Used) {
10654 BestLoQuad = InputQuads[0] ? 0 : 1;
10655 BestHiQuad = InputQuads[2] ? 2 : 3;
10657 if (InputQuads.count() > 2) {
10663 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10664 // the shuffle mask. If a quad is scored as -1, that means that it contains
10665 // words from all 4 input quadwords.
10667 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10669 BestLoQuad < 0 ? 0 : BestLoQuad,
10670 BestHiQuad < 0 ? 1 : BestHiQuad
10672 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10673 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10674 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10675 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10677 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10678 // source words for the shuffle, to aid later transformations.
10679 bool AllWordsInNewV = true;
10680 bool InOrder[2] = { true, true };
10681 for (unsigned i = 0; i != 8; ++i) {
10682 int idx = MaskVals[i];
10684 InOrder[i/4] = false;
10685 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10687 AllWordsInNewV = false;
10691 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10692 if (AllWordsInNewV) {
10693 for (int i = 0; i != 8; ++i) {
10694 int idx = MaskVals[i];
10697 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10698 if ((idx != i) && idx < 4)
10700 if ((idx != i) && idx > 3)
10709 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10710 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10711 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10712 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10713 unsigned TargetMask = 0;
10714 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10715 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10716 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10717 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10718 getShufflePSHUFLWImmediate(SVOp);
10719 V1 = NewV.getOperand(0);
10720 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10724 // Promote splats to a larger type which usually leads to more efficient code.
10725 // FIXME: Is this true if pshufb is available?
10726 if (SVOp->isSplat())
10727 return PromoteSplat(SVOp, DAG);
10729 // If we have SSSE3, and all words of the result are from 1 input vector,
10730 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10731 // is present, fall back to case 4.
10732 if (Subtarget->hasSSSE3()) {
10733 SmallVector<SDValue,16> pshufbMask;
10735 // If we have elements from both input vectors, set the high bit of the
10736 // shuffle mask element to zero out elements that come from V2 in the V1
10737 // mask, and elements that come from V1 in the V2 mask, so that the two
10738 // results can be OR'd together.
10739 bool TwoInputs = V1Used && V2Used;
10740 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10742 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10744 // Calculate the shuffle mask for the second input, shuffle it, and
10745 // OR it with the first shuffled input.
10746 CommuteVectorShuffleMask(MaskVals, 8);
10747 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10748 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10749 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10752 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10753 // and update MaskVals with new element order.
10754 std::bitset<8> InOrder;
10755 if (BestLoQuad >= 0) {
10756 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10757 for (int i = 0; i != 4; ++i) {
10758 int idx = MaskVals[i];
10761 } else if ((idx / 4) == BestLoQuad) {
10762 MaskV[i] = idx & 3;
10766 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10769 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10770 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10771 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10772 NewV.getOperand(0),
10773 getShufflePSHUFLWImmediate(SVOp), DAG);
10777 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10778 // and update MaskVals with the new element order.
10779 if (BestHiQuad >= 0) {
10780 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10781 for (unsigned i = 4; i != 8; ++i) {
10782 int idx = MaskVals[i];
10785 } else if ((idx / 4) == BestHiQuad) {
10786 MaskV[i] = (idx & 3) + 4;
10790 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10793 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10794 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10795 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10796 NewV.getOperand(0),
10797 getShufflePSHUFHWImmediate(SVOp), DAG);
10801 // In case BestHi & BestLo were both -1, which means each quadword has a word
10802 // from each of the four input quadwords, calculate the InOrder bitvector now
10803 // before falling through to the insert/extract cleanup.
10804 if (BestLoQuad == -1 && BestHiQuad == -1) {
10806 for (int i = 0; i != 8; ++i)
10807 if (MaskVals[i] < 0 || MaskVals[i] == i)
10811 // The other elements are put in the right place using pextrw and pinsrw.
10812 for (unsigned i = 0; i != 8; ++i) {
10815 int EltIdx = MaskVals[i];
10818 SDValue ExtOp = (EltIdx < 8) ?
10819 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10820 DAG.getIntPtrConstant(EltIdx)) :
10821 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10822 DAG.getIntPtrConstant(EltIdx - 8));
10823 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10824 DAG.getIntPtrConstant(i));
10829 /// \brief v16i16 shuffles
10831 /// FIXME: We only support generation of a single pshufb currently. We can
10832 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10833 /// well (e.g 2 x pshufb + 1 x por).
10835 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10836 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10837 SDValue V1 = SVOp->getOperand(0);
10838 SDValue V2 = SVOp->getOperand(1);
10841 if (V2.getOpcode() != ISD::UNDEF)
10844 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10845 return getPSHUFB(MaskVals, V1, dl, DAG);
10848 // v16i8 shuffles - Prefer shuffles in the following order:
10849 // 1. [ssse3] 1 x pshufb
10850 // 2. [ssse3] 2 x pshufb + 1 x por
10851 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10852 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10853 const X86Subtarget* Subtarget,
10854 SelectionDAG &DAG) {
10855 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10856 SDValue V1 = SVOp->getOperand(0);
10857 SDValue V2 = SVOp->getOperand(1);
10859 ArrayRef<int> MaskVals = SVOp->getMask();
10861 // Promote splats to a larger type which usually leads to more efficient code.
10862 // FIXME: Is this true if pshufb is available?
10863 if (SVOp->isSplat())
10864 return PromoteSplat(SVOp, DAG);
10866 // If we have SSSE3, case 1 is generated when all result bytes come from
10867 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10868 // present, fall back to case 3.
10870 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10871 if (Subtarget->hasSSSE3()) {
10872 SmallVector<SDValue,16> pshufbMask;
10874 // If all result elements are from one input vector, then only translate
10875 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10877 // Otherwise, we have elements from both input vectors, and must zero out
10878 // elements that come from V2 in the first mask, and V1 in the second mask
10879 // so that we can OR them together.
10880 for (unsigned i = 0; i != 16; ++i) {
10881 int EltIdx = MaskVals[i];
10882 if (EltIdx < 0 || EltIdx >= 16)
10884 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10886 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10887 DAG.getNode(ISD::BUILD_VECTOR, dl,
10888 MVT::v16i8, pshufbMask));
10890 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10891 // the 2nd operand if it's undefined or zero.
10892 if (V2.getOpcode() == ISD::UNDEF ||
10893 ISD::isBuildVectorAllZeros(V2.getNode()))
10896 // Calculate the shuffle mask for the second input, shuffle it, and
10897 // OR it with the first shuffled input.
10898 pshufbMask.clear();
10899 for (unsigned i = 0; i != 16; ++i) {
10900 int EltIdx = MaskVals[i];
10901 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10902 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10904 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10905 DAG.getNode(ISD::BUILD_VECTOR, dl,
10906 MVT::v16i8, pshufbMask));
10907 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10910 // No SSSE3 - Calculate in place words and then fix all out of place words
10911 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10912 // the 16 different words that comprise the two doublequadword input vectors.
10913 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10914 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10916 for (int i = 0; i != 8; ++i) {
10917 int Elt0 = MaskVals[i*2];
10918 int Elt1 = MaskVals[i*2+1];
10920 // This word of the result is all undef, skip it.
10921 if (Elt0 < 0 && Elt1 < 0)
10924 // This word of the result is already in the correct place, skip it.
10925 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10928 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10929 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10932 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10933 // using a single extract together, load it and store it.
10934 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10935 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10936 DAG.getIntPtrConstant(Elt1 / 2));
10937 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10938 DAG.getIntPtrConstant(i));
10942 // If Elt1 is defined, extract it from the appropriate source. If the
10943 // source byte is not also odd, shift the extracted word left 8 bits
10944 // otherwise clear the bottom 8 bits if we need to do an or.
10946 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10947 DAG.getIntPtrConstant(Elt1 / 2));
10948 if ((Elt1 & 1) == 0)
10949 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10951 TLI.getShiftAmountTy(InsElt.getValueType())));
10952 else if (Elt0 >= 0)
10953 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10954 DAG.getConstant(0xFF00, MVT::i16));
10956 // If Elt0 is defined, extract it from the appropriate source. If the
10957 // source byte is not also even, shift the extracted word right 8 bits. If
10958 // Elt1 was also defined, OR the extracted values together before
10959 // inserting them in the result.
10961 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10962 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10963 if ((Elt0 & 1) != 0)
10964 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10966 TLI.getShiftAmountTy(InsElt0.getValueType())));
10967 else if (Elt1 >= 0)
10968 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10969 DAG.getConstant(0x00FF, MVT::i16));
10970 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10973 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10974 DAG.getIntPtrConstant(i));
10976 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10979 // v32i8 shuffles - Translate to VPSHUFB if possible.
10981 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10982 const X86Subtarget *Subtarget,
10983 SelectionDAG &DAG) {
10984 MVT VT = SVOp->getSimpleValueType(0);
10985 SDValue V1 = SVOp->getOperand(0);
10986 SDValue V2 = SVOp->getOperand(1);
10988 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10990 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10991 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10992 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10994 // VPSHUFB may be generated if
10995 // (1) one of input vector is undefined or zeroinitializer.
10996 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10997 // And (2) the mask indexes don't cross the 128-bit lane.
10998 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10999 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11002 if (V1IsAllZero && !V2IsAllZero) {
11003 CommuteVectorShuffleMask(MaskVals, 32);
11006 return getPSHUFB(MaskVals, V1, dl, DAG);
11009 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11010 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11011 /// done when every pair / quad of shuffle mask elements point to elements in
11012 /// the right sequence. e.g.
11013 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11015 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11016 SelectionDAG &DAG) {
11017 MVT VT = SVOp->getSimpleValueType(0);
11019 unsigned NumElems = VT.getVectorNumElements();
11022 switch (VT.SimpleTy) {
11023 default: llvm_unreachable("Unexpected!");
11026 return SDValue(SVOp, 0);
11027 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11028 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11029 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11030 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11031 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11032 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11035 SmallVector<int, 8> MaskVec;
11036 for (unsigned i = 0; i != NumElems; i += Scale) {
11038 for (unsigned j = 0; j != Scale; ++j) {
11039 int EltIdx = SVOp->getMaskElt(i+j);
11043 StartIdx = (EltIdx / Scale);
11044 if (EltIdx != (int)(StartIdx*Scale + j))
11047 MaskVec.push_back(StartIdx);
11050 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11051 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11052 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11055 /// getVZextMovL - Return a zero-extending vector move low node.
11057 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11058 SDValue SrcOp, SelectionDAG &DAG,
11059 const X86Subtarget *Subtarget, SDLoc dl) {
11060 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11061 LoadSDNode *LD = nullptr;
11062 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11063 LD = dyn_cast<LoadSDNode>(SrcOp);
11065 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11067 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11068 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11069 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11070 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11071 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11073 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11074 return DAG.getNode(ISD::BITCAST, dl, VT,
11075 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11076 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11078 SrcOp.getOperand(0)
11084 return DAG.getNode(ISD::BITCAST, dl, VT,
11085 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11086 DAG.getNode(ISD::BITCAST, dl,
11090 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11091 /// which could not be matched by any known target speficic shuffle
11093 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11095 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11096 if (NewOp.getNode())
11099 MVT VT = SVOp->getSimpleValueType(0);
11101 unsigned NumElems = VT.getVectorNumElements();
11102 unsigned NumLaneElems = NumElems / 2;
11105 MVT EltVT = VT.getVectorElementType();
11106 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11109 SmallVector<int, 16> Mask;
11110 for (unsigned l = 0; l < 2; ++l) {
11111 // Build a shuffle mask for the output, discovering on the fly which
11112 // input vectors to use as shuffle operands (recorded in InputUsed).
11113 // If building a suitable shuffle vector proves too hard, then bail
11114 // out with UseBuildVector set.
11115 bool UseBuildVector = false;
11116 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11117 unsigned LaneStart = l * NumLaneElems;
11118 for (unsigned i = 0; i != NumLaneElems; ++i) {
11119 // The mask element. This indexes into the input.
11120 int Idx = SVOp->getMaskElt(i+LaneStart);
11122 // the mask element does not index into any input vector.
11123 Mask.push_back(-1);
11127 // The input vector this mask element indexes into.
11128 int Input = Idx / NumLaneElems;
11130 // Turn the index into an offset from the start of the input vector.
11131 Idx -= Input * NumLaneElems;
11133 // Find or create a shuffle vector operand to hold this input.
11135 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11136 if (InputUsed[OpNo] == Input)
11137 // This input vector is already an operand.
11139 if (InputUsed[OpNo] < 0) {
11140 // Create a new operand for this input vector.
11141 InputUsed[OpNo] = Input;
11146 if (OpNo >= array_lengthof(InputUsed)) {
11147 // More than two input vectors used! Give up on trying to create a
11148 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11149 UseBuildVector = true;
11153 // Add the mask index for the new shuffle vector.
11154 Mask.push_back(Idx + OpNo * NumLaneElems);
11157 if (UseBuildVector) {
11158 SmallVector<SDValue, 16> SVOps;
11159 for (unsigned i = 0; i != NumLaneElems; ++i) {
11160 // The mask element. This indexes into the input.
11161 int Idx = SVOp->getMaskElt(i+LaneStart);
11163 SVOps.push_back(DAG.getUNDEF(EltVT));
11167 // The input vector this mask element indexes into.
11168 int Input = Idx / NumElems;
11170 // Turn the index into an offset from the start of the input vector.
11171 Idx -= Input * NumElems;
11173 // Extract the vector element by hand.
11174 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11175 SVOp->getOperand(Input),
11176 DAG.getIntPtrConstant(Idx)));
11179 // Construct the output using a BUILD_VECTOR.
11180 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11181 } else if (InputUsed[0] < 0) {
11182 // No input vectors were used! The result is undefined.
11183 Output[l] = DAG.getUNDEF(NVT);
11185 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11186 (InputUsed[0] % 2) * NumLaneElems,
11188 // If only one input was used, use an undefined vector for the other.
11189 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11190 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11191 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11192 // At least one input vector was used. Create a new shuffle vector.
11193 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11199 // Concatenate the result back
11200 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11203 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11204 /// 4 elements, and match them with several different shuffle types.
11206 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11207 SDValue V1 = SVOp->getOperand(0);
11208 SDValue V2 = SVOp->getOperand(1);
11210 MVT VT = SVOp->getSimpleValueType(0);
11212 assert(VT.is128BitVector() && "Unsupported vector size");
11214 std::pair<int, int> Locs[4];
11215 int Mask1[] = { -1, -1, -1, -1 };
11216 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11218 unsigned NumHi = 0;
11219 unsigned NumLo = 0;
11220 for (unsigned i = 0; i != 4; ++i) {
11221 int Idx = PermMask[i];
11223 Locs[i] = std::make_pair(-1, -1);
11225 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11227 Locs[i] = std::make_pair(0, NumLo);
11228 Mask1[NumLo] = Idx;
11231 Locs[i] = std::make_pair(1, NumHi);
11233 Mask1[2+NumHi] = Idx;
11239 if (NumLo <= 2 && NumHi <= 2) {
11240 // If no more than two elements come from either vector. This can be
11241 // implemented with two shuffles. First shuffle gather the elements.
11242 // The second shuffle, which takes the first shuffle as both of its
11243 // vector operands, put the elements into the right order.
11244 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11246 int Mask2[] = { -1, -1, -1, -1 };
11248 for (unsigned i = 0; i != 4; ++i)
11249 if (Locs[i].first != -1) {
11250 unsigned Idx = (i < 2) ? 0 : 4;
11251 Idx += Locs[i].first * 2 + Locs[i].second;
11255 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11258 if (NumLo == 3 || NumHi == 3) {
11259 // Otherwise, we must have three elements from one vector, call it X, and
11260 // one element from the other, call it Y. First, use a shufps to build an
11261 // intermediate vector with the one element from Y and the element from X
11262 // that will be in the same half in the final destination (the indexes don't
11263 // matter). Then, use a shufps to build the final vector, taking the half
11264 // containing the element from Y from the intermediate, and the other half
11267 // Normalize it so the 3 elements come from V1.
11268 CommuteVectorShuffleMask(PermMask, 4);
11272 // Find the element from V2.
11274 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11275 int Val = PermMask[HiIndex];
11282 Mask1[0] = PermMask[HiIndex];
11284 Mask1[2] = PermMask[HiIndex^1];
11286 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11288 if (HiIndex >= 2) {
11289 Mask1[0] = PermMask[0];
11290 Mask1[1] = PermMask[1];
11291 Mask1[2] = HiIndex & 1 ? 6 : 4;
11292 Mask1[3] = HiIndex & 1 ? 4 : 6;
11293 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11296 Mask1[0] = HiIndex & 1 ? 2 : 0;
11297 Mask1[1] = HiIndex & 1 ? 0 : 2;
11298 Mask1[2] = PermMask[2];
11299 Mask1[3] = PermMask[3];
11304 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11307 // Break it into (shuffle shuffle_hi, shuffle_lo).
11308 int LoMask[] = { -1, -1, -1, -1 };
11309 int HiMask[] = { -1, -1, -1, -1 };
11311 int *MaskPtr = LoMask;
11312 unsigned MaskIdx = 0;
11313 unsigned LoIdx = 0;
11314 unsigned HiIdx = 2;
11315 for (unsigned i = 0; i != 4; ++i) {
11322 int Idx = PermMask[i];
11324 Locs[i] = std::make_pair(-1, -1);
11325 } else if (Idx < 4) {
11326 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11327 MaskPtr[LoIdx] = Idx;
11330 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11331 MaskPtr[HiIdx] = Idx;
11336 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11337 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11338 int MaskOps[] = { -1, -1, -1, -1 };
11339 for (unsigned i = 0; i != 4; ++i)
11340 if (Locs[i].first != -1)
11341 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11342 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11345 static bool MayFoldVectorLoad(SDValue V) {
11346 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11347 V = V.getOperand(0);
11349 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11350 V = V.getOperand(0);
11351 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11352 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11353 // BUILD_VECTOR (load), undef
11354 V = V.getOperand(0);
11356 return MayFoldLoad(V);
11360 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11361 MVT VT = Op.getSimpleValueType();
11363 // Canonizalize to v2f64.
11364 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11365 return DAG.getNode(ISD::BITCAST, dl, VT,
11366 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11371 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11373 SDValue V1 = Op.getOperand(0);
11374 SDValue V2 = Op.getOperand(1);
11375 MVT VT = Op.getSimpleValueType();
11377 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11379 if (HasSSE2 && VT == MVT::v2f64)
11380 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11382 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11383 return DAG.getNode(ISD::BITCAST, dl, VT,
11384 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11385 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11386 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11390 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11391 SDValue V1 = Op.getOperand(0);
11392 SDValue V2 = Op.getOperand(1);
11393 MVT VT = Op.getSimpleValueType();
11395 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11396 "unsupported shuffle type");
11398 if (V2.getOpcode() == ISD::UNDEF)
11402 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11406 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11407 SDValue V1 = Op.getOperand(0);
11408 SDValue V2 = Op.getOperand(1);
11409 MVT VT = Op.getSimpleValueType();
11410 unsigned NumElems = VT.getVectorNumElements();
11412 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11413 // operand of these instructions is only memory, so check if there's a
11414 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11416 bool CanFoldLoad = false;
11418 // Trivial case, when V2 comes from a load.
11419 if (MayFoldVectorLoad(V2))
11420 CanFoldLoad = true;
11422 // When V1 is a load, it can be folded later into a store in isel, example:
11423 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11425 // (MOVLPSmr addr:$src1, VR128:$src2)
11426 // So, recognize this potential and also use MOVLPS or MOVLPD
11427 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11428 CanFoldLoad = true;
11430 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11432 if (HasSSE2 && NumElems == 2)
11433 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11436 // If we don't care about the second element, proceed to use movss.
11437 if (SVOp->getMaskElt(1) != -1)
11438 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11441 // movl and movlp will both match v2i64, but v2i64 is never matched by
11442 // movl earlier because we make it strict to avoid messing with the movlp load
11443 // folding logic (see the code above getMOVLP call). Match it here then,
11444 // this is horrible, but will stay like this until we move all shuffle
11445 // matching to x86 specific nodes. Note that for the 1st condition all
11446 // types are matched with movsd.
11448 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11449 // as to remove this logic from here, as much as possible
11450 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11451 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11452 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11455 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11457 // Invert the operand order and use SHUFPS to match it.
11458 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11459 getShuffleSHUFImmediate(SVOp), DAG);
11462 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11463 SelectionDAG &DAG) {
11465 MVT VT = Load->getSimpleValueType(0);
11466 MVT EVT = VT.getVectorElementType();
11467 SDValue Addr = Load->getOperand(1);
11468 SDValue NewAddr = DAG.getNode(
11469 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11470 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11473 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11474 DAG.getMachineFunction().getMachineMemOperand(
11475 Load->getMemOperand(), 0, EVT.getStoreSize()));
11479 // It is only safe to call this function if isINSERTPSMask is true for
11480 // this shufflevector mask.
11481 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11482 SelectionDAG &DAG) {
11483 // Generate an insertps instruction when inserting an f32 from memory onto a
11484 // v4f32 or when copying a member from one v4f32 to another.
11485 // We also use it for transferring i32 from one register to another,
11486 // since it simply copies the same bits.
11487 // If we're transferring an i32 from memory to a specific element in a
11488 // register, we output a generic DAG that will match the PINSRD
11490 MVT VT = SVOp->getSimpleValueType(0);
11491 MVT EVT = VT.getVectorElementType();
11492 SDValue V1 = SVOp->getOperand(0);
11493 SDValue V2 = SVOp->getOperand(1);
11494 auto Mask = SVOp->getMask();
11495 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11496 "unsupported vector type for insertps/pinsrd");
11498 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11499 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11500 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11504 unsigned DestIndex;
11508 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11511 // If we have 1 element from each vector, we have to check if we're
11512 // changing V1's element's place. If so, we're done. Otherwise, we
11513 // should assume we're changing V2's element's place and behave
11515 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11516 assert(DestIndex <= INT32_MAX && "truncated destination index");
11517 if (FromV1 == FromV2 &&
11518 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11522 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11525 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11526 "More than one element from V1 and from V2, or no elements from one "
11527 "of the vectors. This case should not have returned true from "
11532 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11535 // Get an index into the source vector in the range [0,4) (the mask is
11536 // in the range [0,8) because it can address V1 and V2)
11537 unsigned SrcIndex = Mask[DestIndex] % 4;
11538 if (MayFoldLoad(From)) {
11539 // Trivial case, when From comes from a load and is only used by the
11540 // shuffle. Make it use insertps from the vector that we need from that
11543 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11544 if (!NewLoad.getNode())
11547 if (EVT == MVT::f32) {
11548 // Create this as a scalar to vector to match the instruction pattern.
11549 SDValue LoadScalarToVector =
11550 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11551 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11552 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11554 } else { // EVT == MVT::i32
11555 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11556 // instruction, to match the PINSRD instruction, which loads an i32 to a
11557 // certain vector element.
11558 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11559 DAG.getConstant(DestIndex, MVT::i32));
11563 // Vector-element-to-vector
11564 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11565 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11568 // Reduce a vector shuffle to zext.
11569 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11570 SelectionDAG &DAG) {
11571 // PMOVZX is only available from SSE41.
11572 if (!Subtarget->hasSSE41())
11575 MVT VT = Op.getSimpleValueType();
11577 // Only AVX2 support 256-bit vector integer extending.
11578 if (!Subtarget->hasInt256() && VT.is256BitVector())
11581 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11583 SDValue V1 = Op.getOperand(0);
11584 SDValue V2 = Op.getOperand(1);
11585 unsigned NumElems = VT.getVectorNumElements();
11587 // Extending is an unary operation and the element type of the source vector
11588 // won't be equal to or larger than i64.
11589 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11590 VT.getVectorElementType() == MVT::i64)
11593 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11594 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11595 while ((1U << Shift) < NumElems) {
11596 if (SVOp->getMaskElt(1U << Shift) == 1)
11599 // The maximal ratio is 8, i.e. from i8 to i64.
11604 // Check the shuffle mask.
11605 unsigned Mask = (1U << Shift) - 1;
11606 for (unsigned i = 0; i != NumElems; ++i) {
11607 int EltIdx = SVOp->getMaskElt(i);
11608 if ((i & Mask) != 0 && EltIdx != -1)
11610 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11614 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11615 MVT NeVT = MVT::getIntegerVT(NBits);
11616 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11618 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11621 return DAG.getNode(ISD::BITCAST, DL, VT,
11622 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11625 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11626 SelectionDAG &DAG) {
11627 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11628 MVT VT = Op.getSimpleValueType();
11630 SDValue V1 = Op.getOperand(0);
11631 SDValue V2 = Op.getOperand(1);
11633 if (isZeroShuffle(SVOp))
11634 return getZeroVector(VT, Subtarget, DAG, dl);
11636 // Handle splat operations
11637 if (SVOp->isSplat()) {
11638 // Use vbroadcast whenever the splat comes from a foldable load
11639 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11640 if (Broadcast.getNode())
11644 // Check integer expanding shuffles.
11645 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11646 if (NewOp.getNode())
11649 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11651 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11652 VT == MVT::v32i8) {
11653 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11654 if (NewOp.getNode())
11655 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11656 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11657 // FIXME: Figure out a cleaner way to do this.
11658 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11659 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11660 if (NewOp.getNode()) {
11661 MVT NewVT = NewOp.getSimpleValueType();
11662 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11663 NewVT, true, false))
11664 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11667 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11668 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11669 if (NewOp.getNode()) {
11670 MVT NewVT = NewOp.getSimpleValueType();
11671 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11672 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11681 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11682 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11683 SDValue V1 = Op.getOperand(0);
11684 SDValue V2 = Op.getOperand(1);
11685 MVT VT = Op.getSimpleValueType();
11687 unsigned NumElems = VT.getVectorNumElements();
11688 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11689 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11690 bool V1IsSplat = false;
11691 bool V2IsSplat = false;
11692 bool HasSSE2 = Subtarget->hasSSE2();
11693 bool HasFp256 = Subtarget->hasFp256();
11694 bool HasInt256 = Subtarget->hasInt256();
11695 MachineFunction &MF = DAG.getMachineFunction();
11696 bool OptForSize = MF.getFunction()->getAttributes().
11697 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11699 // Check if we should use the experimental vector shuffle lowering. If so,
11700 // delegate completely to that code path.
11701 if (ExperimentalVectorShuffleLowering)
11702 return lowerVectorShuffle(Op, Subtarget, DAG);
11704 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11706 if (V1IsUndef && V2IsUndef)
11707 return DAG.getUNDEF(VT);
11709 // When we create a shuffle node we put the UNDEF node to second operand,
11710 // but in some cases the first operand may be transformed to UNDEF.
11711 // In this case we should just commute the node.
11713 return DAG.getCommutedVectorShuffle(*SVOp);
11715 // Vector shuffle lowering takes 3 steps:
11717 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11718 // narrowing and commutation of operands should be handled.
11719 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11721 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11722 // so the shuffle can be broken into other shuffles and the legalizer can
11723 // try the lowering again.
11725 // The general idea is that no vector_shuffle operation should be left to
11726 // be matched during isel, all of them must be converted to a target specific
11729 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11730 // narrowing and commutation of operands should be handled. The actual code
11731 // doesn't include all of those, work in progress...
11732 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11733 if (NewOp.getNode())
11736 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11738 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11739 // unpckh_undef). Only use pshufd if speed is more important than size.
11740 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11741 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11742 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11743 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11745 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11746 V2IsUndef && MayFoldVectorLoad(V1))
11747 return getMOVDDup(Op, dl, V1, DAG);
11749 if (isMOVHLPS_v_undef_Mask(M, VT))
11750 return getMOVHighToLow(Op, dl, DAG);
11752 // Use to match splats
11753 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11754 (VT == MVT::v2f64 || VT == MVT::v2i64))
11755 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11757 if (isPSHUFDMask(M, VT)) {
11758 // The actual implementation will match the mask in the if above and then
11759 // during isel it can match several different instructions, not only pshufd
11760 // as its name says, sad but true, emulate the behavior for now...
11761 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11762 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11764 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11766 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11767 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11769 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11770 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11773 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11777 if (isPALIGNRMask(M, VT, Subtarget))
11778 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11779 getShufflePALIGNRImmediate(SVOp),
11782 if (isVALIGNMask(M, VT, Subtarget))
11783 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11784 getShuffleVALIGNImmediate(SVOp),
11787 // Check if this can be converted into a logical shift.
11788 bool isLeft = false;
11789 unsigned ShAmt = 0;
11791 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11792 if (isShift && ShVal.hasOneUse()) {
11793 // If the shifted value has multiple uses, it may be cheaper to use
11794 // v_set0 + movlhps or movhlps, etc.
11795 MVT EltVT = VT.getVectorElementType();
11796 ShAmt *= EltVT.getSizeInBits();
11797 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11800 if (isMOVLMask(M, VT)) {
11801 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11802 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11803 if (!isMOVLPMask(M, VT)) {
11804 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11805 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11807 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11808 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11812 // FIXME: fold these into legal mask.
11813 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11814 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11816 if (isMOVHLPSMask(M, VT))
11817 return getMOVHighToLow(Op, dl, DAG);
11819 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11820 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11822 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11823 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11825 if (isMOVLPMask(M, VT))
11826 return getMOVLP(Op, dl, DAG, HasSSE2);
11828 if (ShouldXformToMOVHLPS(M, VT) ||
11829 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11830 return DAG.getCommutedVectorShuffle(*SVOp);
11833 // No better options. Use a vshldq / vsrldq.
11834 MVT EltVT = VT.getVectorElementType();
11835 ShAmt *= EltVT.getSizeInBits();
11836 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11839 bool Commuted = false;
11840 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11841 // 1,1,1,1 -> v8i16 though.
11842 BitVector UndefElements;
11843 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11844 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11846 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11847 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11850 // Canonicalize the splat or undef, if present, to be on the RHS.
11851 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11852 CommuteVectorShuffleMask(M, NumElems);
11854 std::swap(V1IsSplat, V2IsSplat);
11858 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11859 // Shuffling low element of v1 into undef, just return v1.
11862 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11863 // the instruction selector will not match, so get a canonical MOVL with
11864 // swapped operands to undo the commute.
11865 return getMOVL(DAG, dl, VT, V2, V1);
11868 if (isUNPCKLMask(M, VT, HasInt256))
11869 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11871 if (isUNPCKHMask(M, VT, HasInt256))
11872 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11875 // Normalize mask so all entries that point to V2 points to its first
11876 // element then try to match unpck{h|l} again. If match, return a
11877 // new vector_shuffle with the corrected mask.p
11878 SmallVector<int, 8> NewMask(M.begin(), M.end());
11879 NormalizeMask(NewMask, NumElems);
11880 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11881 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11882 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11883 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11887 // Commute is back and try unpck* again.
11888 // FIXME: this seems wrong.
11889 CommuteVectorShuffleMask(M, NumElems);
11891 std::swap(V1IsSplat, V2IsSplat);
11893 if (isUNPCKLMask(M, VT, HasInt256))
11894 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11896 if (isUNPCKHMask(M, VT, HasInt256))
11897 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11900 // Normalize the node to match x86 shuffle ops if needed
11901 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11902 return DAG.getCommutedVectorShuffle(*SVOp);
11904 // The checks below are all present in isShuffleMaskLegal, but they are
11905 // inlined here right now to enable us to directly emit target specific
11906 // nodes, and remove one by one until they don't return Op anymore.
11908 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11909 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11910 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11911 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11914 if (isPSHUFHWMask(M, VT, HasInt256))
11915 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11916 getShufflePSHUFHWImmediate(SVOp),
11919 if (isPSHUFLWMask(M, VT, HasInt256))
11920 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11921 getShufflePSHUFLWImmediate(SVOp),
11924 unsigned MaskValue;
11925 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11927 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11929 if (isSHUFPMask(M, VT))
11930 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11931 getShuffleSHUFImmediate(SVOp), DAG);
11933 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11934 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11935 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11936 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11938 //===--------------------------------------------------------------------===//
11939 // Generate target specific nodes for 128 or 256-bit shuffles only
11940 // supported in the AVX instruction set.
11943 // Handle VMOVDDUPY permutations
11944 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11945 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11947 // Handle VPERMILPS/D* permutations
11948 if (isVPERMILPMask(M, VT)) {
11949 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11950 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11951 getShuffleSHUFImmediate(SVOp), DAG);
11952 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11953 getShuffleSHUFImmediate(SVOp), DAG);
11957 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11958 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11959 Idx*(NumElems/2), DAG, dl);
11961 // Handle VPERM2F128/VPERM2I128 permutations
11962 if (isVPERM2X128Mask(M, VT, HasFp256))
11963 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11964 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11966 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11967 return getINSERTPS(SVOp, dl, DAG);
11970 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11971 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11973 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11974 VT.is512BitVector()) {
11975 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11976 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11977 SmallVector<SDValue, 16> permclMask;
11978 for (unsigned i = 0; i != NumElems; ++i) {
11979 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11982 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11984 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11985 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11986 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11987 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11988 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11991 //===--------------------------------------------------------------------===//
11992 // Since no target specific shuffle was selected for this generic one,
11993 // lower it into other known shuffles. FIXME: this isn't true yet, but
11994 // this is the plan.
11997 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11998 if (VT == MVT::v8i16) {
11999 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12000 if (NewOp.getNode())
12004 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12005 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12006 if (NewOp.getNode())
12010 if (VT == MVT::v16i8) {
12011 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12012 if (NewOp.getNode())
12016 if (VT == MVT::v32i8) {
12017 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12018 if (NewOp.getNode())
12022 // Handle all 128-bit wide vectors with 4 elements, and match them with
12023 // several different shuffle types.
12024 if (NumElems == 4 && VT.is128BitVector())
12025 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12027 // Handle general 256-bit shuffles
12028 if (VT.is256BitVector())
12029 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12034 // This function assumes its argument is a BUILD_VECTOR of constants or
12035 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12037 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12038 unsigned &MaskValue) {
12040 unsigned NumElems = BuildVector->getNumOperands();
12041 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12042 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12043 unsigned NumElemsInLane = NumElems / NumLanes;
12045 // Blend for v16i16 should be symetric for the both lanes.
12046 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12047 SDValue EltCond = BuildVector->getOperand(i);
12048 SDValue SndLaneEltCond =
12049 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12051 int Lane1Cond = -1, Lane2Cond = -1;
12052 if (isa<ConstantSDNode>(EltCond))
12053 Lane1Cond = !isZero(EltCond);
12054 if (isa<ConstantSDNode>(SndLaneEltCond))
12055 Lane2Cond = !isZero(SndLaneEltCond);
12057 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12058 // Lane1Cond != 0, means we want the first argument.
12059 // Lane1Cond == 0, means we want the second argument.
12060 // The encoding of this argument is 0 for the first argument, 1
12061 // for the second. Therefore, invert the condition.
12062 MaskValue |= !Lane1Cond << i;
12063 else if (Lane1Cond < 0)
12064 MaskValue |= !Lane2Cond << i;
12071 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12073 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12074 SelectionDAG &DAG) {
12075 SDValue Cond = Op.getOperand(0);
12076 SDValue LHS = Op.getOperand(1);
12077 SDValue RHS = Op.getOperand(2);
12079 MVT VT = Op.getSimpleValueType();
12080 MVT EltVT = VT.getVectorElementType();
12081 unsigned NumElems = VT.getVectorNumElements();
12083 // There is no blend with immediate in AVX-512.
12084 if (VT.is512BitVector())
12087 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12089 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12092 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12095 // Check the mask for BLEND and build the value.
12096 unsigned MaskValue = 0;
12097 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12100 // Convert i32 vectors to floating point if it is not AVX2.
12101 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12103 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12104 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12106 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12107 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12110 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12111 DAG.getConstant(MaskValue, MVT::i32));
12112 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12115 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12116 // A vselect where all conditions and data are constants can be optimized into
12117 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12118 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12119 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12120 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12123 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12124 if (BlendOp.getNode())
12127 // Some types for vselect were previously set to Expand, not Legal or
12128 // Custom. Return an empty SDValue so we fall-through to Expand, after
12129 // the Custom lowering phase.
12130 MVT VT = Op.getSimpleValueType();
12131 switch (VT.SimpleTy) {
12136 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12141 // We couldn't create a "Blend with immediate" node.
12142 // This node should still be legal, but we'll have to emit a blendv*
12147 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12148 MVT VT = Op.getSimpleValueType();
12151 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12154 if (VT.getSizeInBits() == 8) {
12155 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12156 Op.getOperand(0), Op.getOperand(1));
12157 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12158 DAG.getValueType(VT));
12159 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12162 if (VT.getSizeInBits() == 16) {
12163 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12164 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12166 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12167 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12168 DAG.getNode(ISD::BITCAST, dl,
12171 Op.getOperand(1)));
12172 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12173 Op.getOperand(0), Op.getOperand(1));
12174 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12175 DAG.getValueType(VT));
12176 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12179 if (VT == MVT::f32) {
12180 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12181 // the result back to FR32 register. It's only worth matching if the
12182 // result has a single use which is a store or a bitcast to i32. And in
12183 // the case of a store, it's not worth it if the index is a constant 0,
12184 // because a MOVSSmr can be used instead, which is smaller and faster.
12185 if (!Op.hasOneUse())
12187 SDNode *User = *Op.getNode()->use_begin();
12188 if ((User->getOpcode() != ISD::STORE ||
12189 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12190 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12191 (User->getOpcode() != ISD::BITCAST ||
12192 User->getValueType(0) != MVT::i32))
12194 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12195 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12198 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12201 if (VT == MVT::i32 || VT == MVT::i64) {
12202 // ExtractPS/pextrq works with constant index.
12203 if (isa<ConstantSDNode>(Op.getOperand(1)))
12209 /// Extract one bit from mask vector, like v16i1 or v8i1.
12210 /// AVX-512 feature.
12212 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12213 SDValue Vec = Op.getOperand(0);
12215 MVT VecVT = Vec.getSimpleValueType();
12216 SDValue Idx = Op.getOperand(1);
12217 MVT EltVT = Op.getSimpleValueType();
12219 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12221 // variable index can't be handled in mask registers,
12222 // extend vector to VR512
12223 if (!isa<ConstantSDNode>(Idx)) {
12224 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12225 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12226 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12227 ExtVT.getVectorElementType(), Ext, Idx);
12228 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12231 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12232 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12233 unsigned MaxSift = rc->getSize()*8 - 1;
12234 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12235 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12236 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12237 DAG.getConstant(MaxSift, MVT::i8));
12238 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12239 DAG.getIntPtrConstant(0));
12243 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12244 SelectionDAG &DAG) const {
12246 SDValue Vec = Op.getOperand(0);
12247 MVT VecVT = Vec.getSimpleValueType();
12248 SDValue Idx = Op.getOperand(1);
12250 if (Op.getSimpleValueType() == MVT::i1)
12251 return ExtractBitFromMaskVector(Op, DAG);
12253 if (!isa<ConstantSDNode>(Idx)) {
12254 if (VecVT.is512BitVector() ||
12255 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12256 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12259 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12260 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12261 MaskEltVT.getSizeInBits());
12263 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12264 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12265 getZeroVector(MaskVT, Subtarget, DAG, dl),
12266 Idx, DAG.getConstant(0, getPointerTy()));
12267 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12268 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12269 Perm, DAG.getConstant(0, getPointerTy()));
12274 // If this is a 256-bit vector result, first extract the 128-bit vector and
12275 // then extract the element from the 128-bit vector.
12276 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12278 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12279 // Get the 128-bit vector.
12280 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12281 MVT EltVT = VecVT.getVectorElementType();
12283 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12285 //if (IdxVal >= NumElems/2)
12286 // IdxVal -= NumElems/2;
12287 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12288 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12289 DAG.getConstant(IdxVal, MVT::i32));
12292 assert(VecVT.is128BitVector() && "Unexpected vector length");
12294 if (Subtarget->hasSSE41()) {
12295 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12300 MVT VT = Op.getSimpleValueType();
12301 // TODO: handle v16i8.
12302 if (VT.getSizeInBits() == 16) {
12303 SDValue Vec = Op.getOperand(0);
12304 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12306 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12307 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12308 DAG.getNode(ISD::BITCAST, dl,
12310 Op.getOperand(1)));
12311 // Transform it so it match pextrw which produces a 32-bit result.
12312 MVT EltVT = MVT::i32;
12313 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12314 Op.getOperand(0), Op.getOperand(1));
12315 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12316 DAG.getValueType(VT));
12317 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12320 if (VT.getSizeInBits() == 32) {
12321 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12325 // SHUFPS the element to the lowest double word, then movss.
12326 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12327 MVT VVT = Op.getOperand(0).getSimpleValueType();
12328 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12329 DAG.getUNDEF(VVT), Mask);
12330 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12331 DAG.getIntPtrConstant(0));
12334 if (VT.getSizeInBits() == 64) {
12335 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12336 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12337 // to match extract_elt for f64.
12338 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12342 // UNPCKHPD the element to the lowest double word, then movsd.
12343 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12344 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12345 int Mask[2] = { 1, -1 };
12346 MVT VVT = Op.getOperand(0).getSimpleValueType();
12347 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12348 DAG.getUNDEF(VVT), Mask);
12349 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12350 DAG.getIntPtrConstant(0));
12356 /// Insert one bit to mask vector, like v16i1 or v8i1.
12357 /// AVX-512 feature.
12359 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12361 SDValue Vec = Op.getOperand(0);
12362 SDValue Elt = Op.getOperand(1);
12363 SDValue Idx = Op.getOperand(2);
12364 MVT VecVT = Vec.getSimpleValueType();
12366 if (!isa<ConstantSDNode>(Idx)) {
12367 // Non constant index. Extend source and destination,
12368 // insert element and then truncate the result.
12369 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12370 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12371 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12372 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12373 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12374 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12377 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12378 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12379 if (Vec.getOpcode() == ISD::UNDEF)
12380 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12381 DAG.getConstant(IdxVal, MVT::i8));
12382 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12383 unsigned MaxSift = rc->getSize()*8 - 1;
12384 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12385 DAG.getConstant(MaxSift, MVT::i8));
12386 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12387 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12388 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12391 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12392 SelectionDAG &DAG) const {
12393 MVT VT = Op.getSimpleValueType();
12394 MVT EltVT = VT.getVectorElementType();
12396 if (EltVT == MVT::i1)
12397 return InsertBitToMaskVector(Op, DAG);
12400 SDValue N0 = Op.getOperand(0);
12401 SDValue N1 = Op.getOperand(1);
12402 SDValue N2 = Op.getOperand(2);
12403 if (!isa<ConstantSDNode>(N2))
12405 auto *N2C = cast<ConstantSDNode>(N2);
12406 unsigned IdxVal = N2C->getZExtValue();
12408 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12409 // into that, and then insert the subvector back into the result.
12410 if (VT.is256BitVector() || VT.is512BitVector()) {
12411 // Get the desired 128-bit vector half.
12412 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12414 // Insert the element into the desired half.
12415 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12416 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12418 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12419 DAG.getConstant(IdxIn128, MVT::i32));
12421 // Insert the changed part back to the 256-bit vector
12422 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12424 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12426 if (Subtarget->hasSSE41()) {
12427 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12429 if (VT == MVT::v8i16) {
12430 Opc = X86ISD::PINSRW;
12432 assert(VT == MVT::v16i8);
12433 Opc = X86ISD::PINSRB;
12436 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12438 if (N1.getValueType() != MVT::i32)
12439 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12440 if (N2.getValueType() != MVT::i32)
12441 N2 = DAG.getIntPtrConstant(IdxVal);
12442 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12445 if (EltVT == MVT::f32) {
12446 // Bits [7:6] of the constant are the source select. This will always be
12447 // zero here. The DAG Combiner may combine an extract_elt index into
12449 // bits. For example (insert (extract, 3), 2) could be matched by
12451 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12452 // Bits [5:4] of the constant are the destination select. This is the
12453 // value of the incoming immediate.
12454 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12455 // combine either bitwise AND or insert of float 0.0 to set these bits.
12456 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12457 // Create this as a scalar to vector..
12458 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12459 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12462 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12463 // PINSR* works with constant index.
12468 if (EltVT == MVT::i8)
12471 if (EltVT.getSizeInBits() == 16) {
12472 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12473 // as its second argument.
12474 if (N1.getValueType() != MVT::i32)
12475 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12476 if (N2.getValueType() != MVT::i32)
12477 N2 = DAG.getIntPtrConstant(IdxVal);
12478 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12483 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12485 MVT OpVT = Op.getSimpleValueType();
12487 // If this is a 256-bit vector result, first insert into a 128-bit
12488 // vector and then insert into the 256-bit vector.
12489 if (!OpVT.is128BitVector()) {
12490 // Insert into a 128-bit vector.
12491 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12492 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12493 OpVT.getVectorNumElements() / SizeFactor);
12495 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12497 // Insert the 128-bit vector.
12498 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12501 if (OpVT == MVT::v1i64 &&
12502 Op.getOperand(0).getValueType() == MVT::i64)
12503 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12505 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12506 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12507 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12508 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12511 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12512 // a simple subregister reference or explicit instructions to grab
12513 // upper bits of a vector.
12514 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12515 SelectionDAG &DAG) {
12517 SDValue In = Op.getOperand(0);
12518 SDValue Idx = Op.getOperand(1);
12519 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12520 MVT ResVT = Op.getSimpleValueType();
12521 MVT InVT = In.getSimpleValueType();
12523 if (Subtarget->hasFp256()) {
12524 if (ResVT.is128BitVector() &&
12525 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12526 isa<ConstantSDNode>(Idx)) {
12527 return Extract128BitVector(In, IdxVal, DAG, dl);
12529 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12530 isa<ConstantSDNode>(Idx)) {
12531 return Extract256BitVector(In, IdxVal, DAG, dl);
12537 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12538 // simple superregister reference or explicit instructions to insert
12539 // the upper bits of a vector.
12540 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12541 SelectionDAG &DAG) {
12542 if (Subtarget->hasFp256()) {
12543 SDLoc dl(Op.getNode());
12544 SDValue Vec = Op.getNode()->getOperand(0);
12545 SDValue SubVec = Op.getNode()->getOperand(1);
12546 SDValue Idx = Op.getNode()->getOperand(2);
12548 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12549 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12550 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12551 isa<ConstantSDNode>(Idx)) {
12552 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12553 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12556 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12557 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12558 isa<ConstantSDNode>(Idx)) {
12559 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12560 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12566 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12567 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12568 // one of the above mentioned nodes. It has to be wrapped because otherwise
12569 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12570 // be used to form addressing mode. These wrapped nodes will be selected
12573 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12574 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12576 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12577 // global base reg.
12578 unsigned char OpFlag = 0;
12579 unsigned WrapperKind = X86ISD::Wrapper;
12580 CodeModel::Model M = DAG.getTarget().getCodeModel();
12582 if (Subtarget->isPICStyleRIPRel() &&
12583 (M == CodeModel::Small || M == CodeModel::Kernel))
12584 WrapperKind = X86ISD::WrapperRIP;
12585 else if (Subtarget->isPICStyleGOT())
12586 OpFlag = X86II::MO_GOTOFF;
12587 else if (Subtarget->isPICStyleStubPIC())
12588 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12590 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12591 CP->getAlignment(),
12592 CP->getOffset(), OpFlag);
12594 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12595 // With PIC, the address is actually $g + Offset.
12597 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12598 DAG.getNode(X86ISD::GlobalBaseReg,
12599 SDLoc(), getPointerTy()),
12606 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12607 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12609 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12610 // global base reg.
12611 unsigned char OpFlag = 0;
12612 unsigned WrapperKind = X86ISD::Wrapper;
12613 CodeModel::Model M = DAG.getTarget().getCodeModel();
12615 if (Subtarget->isPICStyleRIPRel() &&
12616 (M == CodeModel::Small || M == CodeModel::Kernel))
12617 WrapperKind = X86ISD::WrapperRIP;
12618 else if (Subtarget->isPICStyleGOT())
12619 OpFlag = X86II::MO_GOTOFF;
12620 else if (Subtarget->isPICStyleStubPIC())
12621 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12623 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12626 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12628 // With PIC, the address is actually $g + Offset.
12630 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12631 DAG.getNode(X86ISD::GlobalBaseReg,
12632 SDLoc(), getPointerTy()),
12639 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12640 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12642 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12643 // global base reg.
12644 unsigned char OpFlag = 0;
12645 unsigned WrapperKind = X86ISD::Wrapper;
12646 CodeModel::Model M = DAG.getTarget().getCodeModel();
12648 if (Subtarget->isPICStyleRIPRel() &&
12649 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12650 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12651 OpFlag = X86II::MO_GOTPCREL;
12652 WrapperKind = X86ISD::WrapperRIP;
12653 } else if (Subtarget->isPICStyleGOT()) {
12654 OpFlag = X86II::MO_GOT;
12655 } else if (Subtarget->isPICStyleStubPIC()) {
12656 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12657 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12658 OpFlag = X86II::MO_DARWIN_NONLAZY;
12661 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12664 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12666 // With PIC, the address is actually $g + Offset.
12667 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12668 !Subtarget->is64Bit()) {
12669 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12670 DAG.getNode(X86ISD::GlobalBaseReg,
12671 SDLoc(), getPointerTy()),
12675 // For symbols that require a load from a stub to get the address, emit the
12677 if (isGlobalStubReference(OpFlag))
12678 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12679 MachinePointerInfo::getGOT(), false, false, false, 0);
12685 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12686 // Create the TargetBlockAddressAddress node.
12687 unsigned char OpFlags =
12688 Subtarget->ClassifyBlockAddressReference();
12689 CodeModel::Model M = DAG.getTarget().getCodeModel();
12690 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12691 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12693 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12696 if (Subtarget->isPICStyleRIPRel() &&
12697 (M == CodeModel::Small || M == CodeModel::Kernel))
12698 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12700 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12702 // With PIC, the address is actually $g + Offset.
12703 if (isGlobalRelativeToPICBase(OpFlags)) {
12704 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12705 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12713 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12714 int64_t Offset, SelectionDAG &DAG) const {
12715 // Create the TargetGlobalAddress node, folding in the constant
12716 // offset if it is legal.
12717 unsigned char OpFlags =
12718 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12719 CodeModel::Model M = DAG.getTarget().getCodeModel();
12721 if (OpFlags == X86II::MO_NO_FLAG &&
12722 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12723 // A direct static reference to a global.
12724 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12727 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12730 if (Subtarget->isPICStyleRIPRel() &&
12731 (M == CodeModel::Small || M == CodeModel::Kernel))
12732 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12734 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12736 // With PIC, the address is actually $g + Offset.
12737 if (isGlobalRelativeToPICBase(OpFlags)) {
12738 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12739 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12743 // For globals that require a load from a stub to get the address, emit the
12745 if (isGlobalStubReference(OpFlags))
12746 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12747 MachinePointerInfo::getGOT(), false, false, false, 0);
12749 // If there was a non-zero offset that we didn't fold, create an explicit
12750 // addition for it.
12752 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12753 DAG.getConstant(Offset, getPointerTy()));
12759 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12760 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12761 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12762 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12766 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12767 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12768 unsigned char OperandFlags, bool LocalDynamic = false) {
12769 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12770 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12772 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12773 GA->getValueType(0),
12777 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12781 SDValue Ops[] = { Chain, TGA, *InFlag };
12782 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12784 SDValue Ops[] = { Chain, TGA };
12785 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12788 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12789 MFI->setAdjustsStack(true);
12791 SDValue Flag = Chain.getValue(1);
12792 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12795 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12797 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12800 SDLoc dl(GA); // ? function entry point might be better
12801 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12802 DAG.getNode(X86ISD::GlobalBaseReg,
12803 SDLoc(), PtrVT), InFlag);
12804 InFlag = Chain.getValue(1);
12806 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12809 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12811 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12813 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12814 X86::RAX, X86II::MO_TLSGD);
12817 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12823 // Get the start address of the TLS block for this module.
12824 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12825 .getInfo<X86MachineFunctionInfo>();
12826 MFI->incNumLocalDynamicTLSAccesses();
12830 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12831 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12834 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12835 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12836 InFlag = Chain.getValue(1);
12837 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12838 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12841 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12845 unsigned char OperandFlags = X86II::MO_DTPOFF;
12846 unsigned WrapperKind = X86ISD::Wrapper;
12847 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12848 GA->getValueType(0),
12849 GA->getOffset(), OperandFlags);
12850 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12852 // Add x@dtpoff with the base.
12853 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12856 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12857 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12858 const EVT PtrVT, TLSModel::Model model,
12859 bool is64Bit, bool isPIC) {
12862 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12863 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12864 is64Bit ? 257 : 256));
12866 SDValue ThreadPointer =
12867 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12868 MachinePointerInfo(Ptr), false, false, false, 0);
12870 unsigned char OperandFlags = 0;
12871 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12873 unsigned WrapperKind = X86ISD::Wrapper;
12874 if (model == TLSModel::LocalExec) {
12875 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12876 } else if (model == TLSModel::InitialExec) {
12878 OperandFlags = X86II::MO_GOTTPOFF;
12879 WrapperKind = X86ISD::WrapperRIP;
12881 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12884 llvm_unreachable("Unexpected model");
12887 // emit "addl x@ntpoff,%eax" (local exec)
12888 // or "addl x@indntpoff,%eax" (initial exec)
12889 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12891 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12892 GA->getOffset(), OperandFlags);
12893 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12895 if (model == TLSModel::InitialExec) {
12896 if (isPIC && !is64Bit) {
12897 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12898 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12902 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12903 MachinePointerInfo::getGOT(), false, false, false, 0);
12906 // The address of the thread local variable is the add of the thread
12907 // pointer with the offset of the variable.
12908 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12912 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12914 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12915 const GlobalValue *GV = GA->getGlobal();
12917 if (Subtarget->isTargetELF()) {
12918 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12921 case TLSModel::GeneralDynamic:
12922 if (Subtarget->is64Bit())
12923 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12924 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12925 case TLSModel::LocalDynamic:
12926 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12927 Subtarget->is64Bit());
12928 case TLSModel::InitialExec:
12929 case TLSModel::LocalExec:
12930 return LowerToTLSExecModel(
12931 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12932 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12934 llvm_unreachable("Unknown TLS model.");
12937 if (Subtarget->isTargetDarwin()) {
12938 // Darwin only has one model of TLS. Lower to that.
12939 unsigned char OpFlag = 0;
12940 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12941 X86ISD::WrapperRIP : X86ISD::Wrapper;
12943 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12944 // global base reg.
12945 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12946 !Subtarget->is64Bit();
12948 OpFlag = X86II::MO_TLVP_PIC_BASE;
12950 OpFlag = X86II::MO_TLVP;
12952 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12953 GA->getValueType(0),
12954 GA->getOffset(), OpFlag);
12955 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12957 // With PIC32, the address is actually $g + Offset.
12959 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12960 DAG.getNode(X86ISD::GlobalBaseReg,
12961 SDLoc(), getPointerTy()),
12964 // Lowering the machine isd will make sure everything is in the right
12966 SDValue Chain = DAG.getEntryNode();
12967 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12968 SDValue Args[] = { Chain, Offset };
12969 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12971 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12972 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12973 MFI->setAdjustsStack(true);
12975 // And our return value (tls address) is in the standard call return value
12977 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12978 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12979 Chain.getValue(1));
12982 if (Subtarget->isTargetKnownWindowsMSVC() ||
12983 Subtarget->isTargetWindowsGNU()) {
12984 // Just use the implicit TLS architecture
12985 // Need to generate someting similar to:
12986 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12988 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12989 // mov rcx, qword [rdx+rcx*8]
12990 // mov eax, .tls$:tlsvar
12991 // [rax+rcx] contains the address
12992 // Windows 64bit: gs:0x58
12993 // Windows 32bit: fs:__tls_array
12996 SDValue Chain = DAG.getEntryNode();
12998 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12999 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13000 // use its literal value of 0x2C.
13001 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13002 ? Type::getInt8PtrTy(*DAG.getContext(),
13004 : Type::getInt32PtrTy(*DAG.getContext(),
13008 Subtarget->is64Bit()
13009 ? DAG.getIntPtrConstant(0x58)
13010 : (Subtarget->isTargetWindowsGNU()
13011 ? DAG.getIntPtrConstant(0x2C)
13012 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13014 SDValue ThreadPointer =
13015 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13016 MachinePointerInfo(Ptr), false, false, false, 0);
13018 // Load the _tls_index variable
13019 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13020 if (Subtarget->is64Bit())
13021 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13022 IDX, MachinePointerInfo(), MVT::i32,
13023 false, false, false, 0);
13025 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13026 false, false, false, 0);
13028 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13030 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13032 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13033 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13034 false, false, false, 0);
13036 // Get the offset of start of .tls section
13037 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13038 GA->getValueType(0),
13039 GA->getOffset(), X86II::MO_SECREL);
13040 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13042 // The address of the thread local variable is the add of the thread
13043 // pointer with the offset of the variable.
13044 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13047 llvm_unreachable("TLS not implemented for this target.");
13050 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13051 /// and take a 2 x i32 value to shift plus a shift amount.
13052 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13053 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13054 MVT VT = Op.getSimpleValueType();
13055 unsigned VTBits = VT.getSizeInBits();
13057 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13058 SDValue ShOpLo = Op.getOperand(0);
13059 SDValue ShOpHi = Op.getOperand(1);
13060 SDValue ShAmt = Op.getOperand(2);
13061 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13062 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13064 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13065 DAG.getConstant(VTBits - 1, MVT::i8));
13066 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13067 DAG.getConstant(VTBits - 1, MVT::i8))
13068 : DAG.getConstant(0, VT);
13070 SDValue Tmp2, Tmp3;
13071 if (Op.getOpcode() == ISD::SHL_PARTS) {
13072 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13073 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13075 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13076 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13079 // If the shift amount is larger or equal than the width of a part we can't
13080 // rely on the results of shld/shrd. Insert a test and select the appropriate
13081 // values for large shift amounts.
13082 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13083 DAG.getConstant(VTBits, MVT::i8));
13084 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13085 AndNode, DAG.getConstant(0, MVT::i8));
13088 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13089 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13090 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13092 if (Op.getOpcode() == ISD::SHL_PARTS) {
13093 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13094 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13096 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13097 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13100 SDValue Ops[2] = { Lo, Hi };
13101 return DAG.getMergeValues(Ops, dl);
13104 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13105 SelectionDAG &DAG) const {
13106 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13108 if (SrcVT.isVector())
13111 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13112 "Unknown SINT_TO_FP to lower!");
13114 // These are really Legal; return the operand so the caller accepts it as
13116 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13118 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13119 Subtarget->is64Bit()) {
13124 unsigned Size = SrcVT.getSizeInBits()/8;
13125 MachineFunction &MF = DAG.getMachineFunction();
13126 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13127 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13128 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13130 MachinePointerInfo::getFixedStack(SSFI),
13132 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13135 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13137 SelectionDAG &DAG) const {
13141 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13143 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13145 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13147 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13149 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13150 MachineMemOperand *MMO;
13152 int SSFI = FI->getIndex();
13154 DAG.getMachineFunction()
13155 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13156 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13158 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13159 StackSlot = StackSlot.getOperand(1);
13161 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13162 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13164 Tys, Ops, SrcVT, MMO);
13167 Chain = Result.getValue(1);
13168 SDValue InFlag = Result.getValue(2);
13170 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13171 // shouldn't be necessary except that RFP cannot be live across
13172 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13173 MachineFunction &MF = DAG.getMachineFunction();
13174 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13175 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13176 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13177 Tys = DAG.getVTList(MVT::Other);
13179 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13181 MachineMemOperand *MMO =
13182 DAG.getMachineFunction()
13183 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13184 MachineMemOperand::MOStore, SSFISize, SSFISize);
13186 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13187 Ops, Op.getValueType(), MMO);
13188 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13189 MachinePointerInfo::getFixedStack(SSFI),
13190 false, false, false, 0);
13196 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13197 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13198 SelectionDAG &DAG) const {
13199 // This algorithm is not obvious. Here it is what we're trying to output:
13202 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13203 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13205 haddpd %xmm0, %xmm0
13207 pshufd $0x4e, %xmm0, %xmm1
13213 LLVMContext *Context = DAG.getContext();
13215 // Build some magic constants.
13216 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13217 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13218 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13220 SmallVector<Constant*,2> CV1;
13222 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13223 APInt(64, 0x4330000000000000ULL))));
13225 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13226 APInt(64, 0x4530000000000000ULL))));
13227 Constant *C1 = ConstantVector::get(CV1);
13228 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13230 // Load the 64-bit value into an XMM register.
13231 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13233 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13234 MachinePointerInfo::getConstantPool(),
13235 false, false, false, 16);
13236 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13237 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13240 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13241 MachinePointerInfo::getConstantPool(),
13242 false, false, false, 16);
13243 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13244 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13247 if (Subtarget->hasSSE3()) {
13248 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13249 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13251 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13252 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13254 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13255 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13259 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13260 DAG.getIntPtrConstant(0));
13263 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13264 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13265 SelectionDAG &DAG) const {
13267 // FP constant to bias correct the final result.
13268 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13271 // Load the 32-bit value into an XMM register.
13272 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13275 // Zero out the upper parts of the register.
13276 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13278 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13279 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13280 DAG.getIntPtrConstant(0));
13282 // Or the load with the bias.
13283 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13284 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13285 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13286 MVT::v2f64, Load)),
13287 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13288 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13289 MVT::v2f64, Bias)));
13290 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13291 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13292 DAG.getIntPtrConstant(0));
13294 // Subtract the bias.
13295 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13297 // Handle final rounding.
13298 EVT DestVT = Op.getValueType();
13300 if (DestVT.bitsLT(MVT::f64))
13301 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13302 DAG.getIntPtrConstant(0));
13303 if (DestVT.bitsGT(MVT::f64))
13304 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13306 // Handle final rounding.
13310 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13311 SelectionDAG &DAG) const {
13312 SDValue N0 = Op.getOperand(0);
13313 MVT SVT = N0.getSimpleValueType();
13316 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13317 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13318 "Custom UINT_TO_FP is not supported!");
13320 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13321 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13322 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13325 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13326 SelectionDAG &DAG) const {
13327 SDValue N0 = Op.getOperand(0);
13330 if (Op.getValueType().isVector())
13331 return lowerUINT_TO_FP_vec(Op, DAG);
13333 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13334 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13335 // the optimization here.
13336 if (DAG.SignBitIsZero(N0))
13337 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13339 MVT SrcVT = N0.getSimpleValueType();
13340 MVT DstVT = Op.getSimpleValueType();
13341 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13342 return LowerUINT_TO_FP_i64(Op, DAG);
13343 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13344 return LowerUINT_TO_FP_i32(Op, DAG);
13345 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13348 // Make a 64-bit buffer, and use it to build an FILD.
13349 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13350 if (SrcVT == MVT::i32) {
13351 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13352 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13353 getPointerTy(), StackSlot, WordOff);
13354 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13355 StackSlot, MachinePointerInfo(),
13357 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13358 OffsetSlot, MachinePointerInfo(),
13360 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13364 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13365 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13366 StackSlot, MachinePointerInfo(),
13368 // For i64 source, we need to add the appropriate power of 2 if the input
13369 // was negative. This is the same as the optimization in
13370 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13371 // we must be careful to do the computation in x87 extended precision, not
13372 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13373 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13374 MachineMemOperand *MMO =
13375 DAG.getMachineFunction()
13376 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13377 MachineMemOperand::MOLoad, 8, 8);
13379 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13380 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13381 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13384 APInt FF(32, 0x5F800000ULL);
13386 // Check whether the sign bit is set.
13387 SDValue SignSet = DAG.getSetCC(dl,
13388 getSetCCResultType(*DAG.getContext(), MVT::i64),
13389 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13392 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13393 SDValue FudgePtr = DAG.getConstantPool(
13394 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13397 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13398 SDValue Zero = DAG.getIntPtrConstant(0);
13399 SDValue Four = DAG.getIntPtrConstant(4);
13400 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13402 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13404 // Load the value out, extending it from f32 to f80.
13405 // FIXME: Avoid the extend by constructing the right constant pool?
13406 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13407 FudgePtr, MachinePointerInfo::getConstantPool(),
13408 MVT::f32, false, false, false, 4);
13409 // Extend everything to 80 bits to force it to be done on x87.
13410 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13411 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13414 std::pair<SDValue,SDValue>
13415 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13416 bool IsSigned, bool IsReplace) const {
13419 EVT DstTy = Op.getValueType();
13421 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13422 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13426 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13427 DstTy.getSimpleVT() >= MVT::i16 &&
13428 "Unknown FP_TO_INT to lower!");
13430 // These are really Legal.
13431 if (DstTy == MVT::i32 &&
13432 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13433 return std::make_pair(SDValue(), SDValue());
13434 if (Subtarget->is64Bit() &&
13435 DstTy == MVT::i64 &&
13436 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13437 return std::make_pair(SDValue(), SDValue());
13439 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13440 // stack slot, or into the FTOL runtime function.
13441 MachineFunction &MF = DAG.getMachineFunction();
13442 unsigned MemSize = DstTy.getSizeInBits()/8;
13443 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13444 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13447 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13448 Opc = X86ISD::WIN_FTOL;
13450 switch (DstTy.getSimpleVT().SimpleTy) {
13451 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13452 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13453 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13454 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13457 SDValue Chain = DAG.getEntryNode();
13458 SDValue Value = Op.getOperand(0);
13459 EVT TheVT = Op.getOperand(0).getValueType();
13460 // FIXME This causes a redundant load/store if the SSE-class value is already
13461 // in memory, such as if it is on the callstack.
13462 if (isScalarFPTypeInSSEReg(TheVT)) {
13463 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13464 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13465 MachinePointerInfo::getFixedStack(SSFI),
13467 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13469 Chain, StackSlot, DAG.getValueType(TheVT)
13472 MachineMemOperand *MMO =
13473 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13474 MachineMemOperand::MOLoad, MemSize, MemSize);
13475 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13476 Chain = Value.getValue(1);
13477 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13478 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13481 MachineMemOperand *MMO =
13482 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13483 MachineMemOperand::MOStore, MemSize, MemSize);
13485 if (Opc != X86ISD::WIN_FTOL) {
13486 // Build the FP_TO_INT*_IN_MEM
13487 SDValue Ops[] = { Chain, Value, StackSlot };
13488 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13490 return std::make_pair(FIST, StackSlot);
13492 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13493 DAG.getVTList(MVT::Other, MVT::Glue),
13495 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13496 MVT::i32, ftol.getValue(1));
13497 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13498 MVT::i32, eax.getValue(2));
13499 SDValue Ops[] = { eax, edx };
13500 SDValue pair = IsReplace
13501 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13502 : DAG.getMergeValues(Ops, DL);
13503 return std::make_pair(pair, SDValue());
13507 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13508 const X86Subtarget *Subtarget) {
13509 MVT VT = Op->getSimpleValueType(0);
13510 SDValue In = Op->getOperand(0);
13511 MVT InVT = In.getSimpleValueType();
13514 // Optimize vectors in AVX mode:
13517 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13518 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13519 // Concat upper and lower parts.
13522 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13523 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13524 // Concat upper and lower parts.
13527 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13528 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13529 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13532 if (Subtarget->hasInt256())
13533 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13535 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13536 SDValue Undef = DAG.getUNDEF(InVT);
13537 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13538 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13539 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13541 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13542 VT.getVectorNumElements()/2);
13544 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13545 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13547 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13550 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13551 SelectionDAG &DAG) {
13552 MVT VT = Op->getSimpleValueType(0);
13553 SDValue In = Op->getOperand(0);
13554 MVT InVT = In.getSimpleValueType();
13556 unsigned int NumElts = VT.getVectorNumElements();
13557 if (NumElts != 8 && NumElts != 16)
13560 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13561 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13563 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13564 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13565 // Now we have only mask extension
13566 assert(InVT.getVectorElementType() == MVT::i1);
13567 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13568 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13569 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13570 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13571 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13572 MachinePointerInfo::getConstantPool(),
13573 false, false, false, Alignment);
13575 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13576 if (VT.is512BitVector())
13578 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13581 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13582 SelectionDAG &DAG) {
13583 if (Subtarget->hasFp256()) {
13584 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13592 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13593 SelectionDAG &DAG) {
13595 MVT VT = Op.getSimpleValueType();
13596 SDValue In = Op.getOperand(0);
13597 MVT SVT = In.getSimpleValueType();
13599 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13600 return LowerZERO_EXTEND_AVX512(Op, DAG);
13602 if (Subtarget->hasFp256()) {
13603 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13608 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13609 VT.getVectorNumElements() != SVT.getVectorNumElements());
13613 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13615 MVT VT = Op.getSimpleValueType();
13616 SDValue In = Op.getOperand(0);
13617 MVT InVT = In.getSimpleValueType();
13619 if (VT == MVT::i1) {
13620 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13621 "Invalid scalar TRUNCATE operation");
13622 if (InVT.getSizeInBits() >= 32)
13624 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13625 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13627 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13628 "Invalid TRUNCATE operation");
13630 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13631 if (VT.getVectorElementType().getSizeInBits() >=8)
13632 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13634 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13635 unsigned NumElts = InVT.getVectorNumElements();
13636 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13637 if (InVT.getSizeInBits() < 512) {
13638 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13639 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13643 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13644 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13645 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13646 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13647 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13648 MachinePointerInfo::getConstantPool(),
13649 false, false, false, Alignment);
13650 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13651 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13652 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13655 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13656 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13657 if (Subtarget->hasInt256()) {
13658 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13659 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13660 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13662 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13663 DAG.getIntPtrConstant(0));
13666 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13667 DAG.getIntPtrConstant(0));
13668 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13669 DAG.getIntPtrConstant(2));
13670 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13671 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13672 static const int ShufMask[] = {0, 2, 4, 6};
13673 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13676 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13677 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13678 if (Subtarget->hasInt256()) {
13679 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13681 SmallVector<SDValue,32> pshufbMask;
13682 for (unsigned i = 0; i < 2; ++i) {
13683 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13684 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13685 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13686 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13687 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13688 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13689 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13690 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13691 for (unsigned j = 0; j < 8; ++j)
13692 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13694 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13695 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13696 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13698 static const int ShufMask[] = {0, 2, -1, -1};
13699 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13701 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13702 DAG.getIntPtrConstant(0));
13703 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13706 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13707 DAG.getIntPtrConstant(0));
13709 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13710 DAG.getIntPtrConstant(4));
13712 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13713 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13715 // The PSHUFB mask:
13716 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13717 -1, -1, -1, -1, -1, -1, -1, -1};
13719 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13720 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13721 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13723 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13724 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13726 // The MOVLHPS Mask:
13727 static const int ShufMask2[] = {0, 1, 4, 5};
13728 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13729 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13732 // Handle truncation of V256 to V128 using shuffles.
13733 if (!VT.is128BitVector() || !InVT.is256BitVector())
13736 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13738 unsigned NumElems = VT.getVectorNumElements();
13739 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13741 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13742 // Prepare truncation shuffle mask
13743 for (unsigned i = 0; i != NumElems; ++i)
13744 MaskVec[i] = i * 2;
13745 SDValue V = DAG.getVectorShuffle(NVT, DL,
13746 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13747 DAG.getUNDEF(NVT), &MaskVec[0]);
13748 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13749 DAG.getIntPtrConstant(0));
13752 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13753 SelectionDAG &DAG) const {
13754 assert(!Op.getSimpleValueType().isVector());
13756 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13757 /*IsSigned=*/ true, /*IsReplace=*/ false);
13758 SDValue FIST = Vals.first, StackSlot = Vals.second;
13759 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13760 if (!FIST.getNode()) return Op;
13762 if (StackSlot.getNode())
13763 // Load the result.
13764 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13765 FIST, StackSlot, MachinePointerInfo(),
13766 false, false, false, 0);
13768 // The node is the result.
13772 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13773 SelectionDAG &DAG) const {
13774 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13775 /*IsSigned=*/ false, /*IsReplace=*/ false);
13776 SDValue FIST = Vals.first, StackSlot = Vals.second;
13777 assert(FIST.getNode() && "Unexpected failure");
13779 if (StackSlot.getNode())
13780 // Load the result.
13781 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13782 FIST, StackSlot, MachinePointerInfo(),
13783 false, false, false, 0);
13785 // The node is the result.
13789 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13791 MVT VT = Op.getSimpleValueType();
13792 SDValue In = Op.getOperand(0);
13793 MVT SVT = In.getSimpleValueType();
13795 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13797 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13798 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13799 In, DAG.getUNDEF(SVT)));
13802 /// The only differences between FABS and FNEG are the mask and the logic op.
13803 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13804 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13805 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13806 "Wrong opcode for lowering FABS or FNEG.");
13808 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13810 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13811 // into an FNABS. We'll lower the FABS after that if it is still in use.
13813 for (SDNode *User : Op->uses())
13814 if (User->getOpcode() == ISD::FNEG)
13817 SDValue Op0 = Op.getOperand(0);
13818 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13821 MVT VT = Op.getSimpleValueType();
13822 // Assume scalar op for initialization; update for vector if needed.
13823 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13824 // generate a 16-byte vector constant and logic op even for the scalar case.
13825 // Using a 16-byte mask allows folding the load of the mask with
13826 // the logic op, so it can save (~4 bytes) on code size.
13828 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13829 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13830 // decide if we should generate a 16-byte constant mask when we only need 4 or
13831 // 8 bytes for the scalar case.
13832 if (VT.isVector()) {
13833 EltVT = VT.getVectorElementType();
13834 NumElts = VT.getVectorNumElements();
13837 unsigned EltBits = EltVT.getSizeInBits();
13838 LLVMContext *Context = DAG.getContext();
13839 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13841 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13842 Constant *C = ConstantInt::get(*Context, MaskElt);
13843 C = ConstantVector::getSplat(NumElts, C);
13844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13845 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13846 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13847 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13848 MachinePointerInfo::getConstantPool(),
13849 false, false, false, Alignment);
13851 if (VT.isVector()) {
13852 // For a vector, cast operands to a vector type, perform the logic op,
13853 // and cast the result back to the original value type.
13854 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13855 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13856 SDValue Operand = IsFNABS ?
13857 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
13858 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
13859 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
13860 return DAG.getNode(ISD::BITCAST, dl, VT,
13861 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
13864 // If not vector, then scalar.
13865 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13866 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13867 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
13870 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13871 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13872 LLVMContext *Context = DAG.getContext();
13873 SDValue Op0 = Op.getOperand(0);
13874 SDValue Op1 = Op.getOperand(1);
13876 MVT VT = Op.getSimpleValueType();
13877 MVT SrcVT = Op1.getSimpleValueType();
13879 // If second operand is smaller, extend it first.
13880 if (SrcVT.bitsLT(VT)) {
13881 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13884 // And if it is bigger, shrink it first.
13885 if (SrcVT.bitsGT(VT)) {
13886 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13890 // At this point the operands and the result should have the same
13891 // type, and that won't be f80 since that is not custom lowered.
13893 // First get the sign bit of second operand.
13894 SmallVector<Constant*,4> CV;
13895 if (SrcVT == MVT::f64) {
13896 const fltSemantics &Sem = APFloat::IEEEdouble;
13897 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13898 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13900 const fltSemantics &Sem = APFloat::IEEEsingle;
13901 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13902 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13903 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13904 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13906 Constant *C = ConstantVector::get(CV);
13907 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13908 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13909 MachinePointerInfo::getConstantPool(),
13910 false, false, false, 16);
13911 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13913 // Shift sign bit right or left if the two operands have different types.
13914 if (SrcVT.bitsGT(VT)) {
13915 // Op0 is MVT::f32, Op1 is MVT::f64.
13916 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13917 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13918 DAG.getConstant(32, MVT::i32));
13919 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13920 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13921 DAG.getIntPtrConstant(0));
13924 // Clear first operand sign bit.
13926 if (VT == MVT::f64) {
13927 const fltSemantics &Sem = APFloat::IEEEdouble;
13928 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13929 APInt(64, ~(1ULL << 63)))));
13930 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13932 const fltSemantics &Sem = APFloat::IEEEsingle;
13933 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13934 APInt(32, ~(1U << 31)))));
13935 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13936 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13937 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13939 C = ConstantVector::get(CV);
13940 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13941 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13942 MachinePointerInfo::getConstantPool(),
13943 false, false, false, 16);
13944 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13946 // Or the value with the sign bit.
13947 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13950 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13951 SDValue N0 = Op.getOperand(0);
13953 MVT VT = Op.getSimpleValueType();
13955 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13956 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13957 DAG.getConstant(1, VT));
13958 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13961 // Check whether an OR'd tree is PTEST-able.
13962 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13963 SelectionDAG &DAG) {
13964 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13966 if (!Subtarget->hasSSE41())
13969 if (!Op->hasOneUse())
13972 SDNode *N = Op.getNode();
13975 SmallVector<SDValue, 8> Opnds;
13976 DenseMap<SDValue, unsigned> VecInMap;
13977 SmallVector<SDValue, 8> VecIns;
13978 EVT VT = MVT::Other;
13980 // Recognize a special case where a vector is casted into wide integer to
13982 Opnds.push_back(N->getOperand(0));
13983 Opnds.push_back(N->getOperand(1));
13985 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13986 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13987 // BFS traverse all OR'd operands.
13988 if (I->getOpcode() == ISD::OR) {
13989 Opnds.push_back(I->getOperand(0));
13990 Opnds.push_back(I->getOperand(1));
13991 // Re-evaluate the number of nodes to be traversed.
13992 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13996 // Quit if a non-EXTRACT_VECTOR_ELT
13997 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14000 // Quit if without a constant index.
14001 SDValue Idx = I->getOperand(1);
14002 if (!isa<ConstantSDNode>(Idx))
14005 SDValue ExtractedFromVec = I->getOperand(0);
14006 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14007 if (M == VecInMap.end()) {
14008 VT = ExtractedFromVec.getValueType();
14009 // Quit if not 128/256-bit vector.
14010 if (!VT.is128BitVector() && !VT.is256BitVector())
14012 // Quit if not the same type.
14013 if (VecInMap.begin() != VecInMap.end() &&
14014 VT != VecInMap.begin()->first.getValueType())
14016 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14017 VecIns.push_back(ExtractedFromVec);
14019 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14022 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14023 "Not extracted from 128-/256-bit vector.");
14025 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14027 for (DenseMap<SDValue, unsigned>::const_iterator
14028 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14029 // Quit if not all elements are used.
14030 if (I->second != FullMask)
14034 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14036 // Cast all vectors into TestVT for PTEST.
14037 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14038 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14040 // If more than one full vectors are evaluated, OR them first before PTEST.
14041 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14042 // Each iteration will OR 2 nodes and append the result until there is only
14043 // 1 node left, i.e. the final OR'd value of all vectors.
14044 SDValue LHS = VecIns[Slot];
14045 SDValue RHS = VecIns[Slot + 1];
14046 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14049 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14050 VecIns.back(), VecIns.back());
14053 /// \brief return true if \c Op has a use that doesn't just read flags.
14054 static bool hasNonFlagsUse(SDValue Op) {
14055 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14057 SDNode *User = *UI;
14058 unsigned UOpNo = UI.getOperandNo();
14059 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14060 // Look pass truncate.
14061 UOpNo = User->use_begin().getOperandNo();
14062 User = *User->use_begin();
14065 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14066 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14072 /// Emit nodes that will be selected as "test Op0,Op0", or something
14074 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14075 SelectionDAG &DAG) const {
14076 if (Op.getValueType() == MVT::i1)
14077 // KORTEST instruction should be selected
14078 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14079 DAG.getConstant(0, Op.getValueType()));
14081 // CF and OF aren't always set the way we want. Determine which
14082 // of these we need.
14083 bool NeedCF = false;
14084 bool NeedOF = false;
14087 case X86::COND_A: case X86::COND_AE:
14088 case X86::COND_B: case X86::COND_BE:
14091 case X86::COND_G: case X86::COND_GE:
14092 case X86::COND_L: case X86::COND_LE:
14093 case X86::COND_O: case X86::COND_NO: {
14094 // Check if we really need to set the
14095 // Overflow flag. If NoSignedWrap is present
14096 // that is not actually needed.
14097 switch (Op->getOpcode()) {
14102 const BinaryWithFlagsSDNode *BinNode =
14103 cast<BinaryWithFlagsSDNode>(Op.getNode());
14104 if (BinNode->hasNoSignedWrap())
14114 // See if we can use the EFLAGS value from the operand instead of
14115 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14116 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14117 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14118 // Emit a CMP with 0, which is the TEST pattern.
14119 //if (Op.getValueType() == MVT::i1)
14120 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14121 // DAG.getConstant(0, MVT::i1));
14122 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14123 DAG.getConstant(0, Op.getValueType()));
14125 unsigned Opcode = 0;
14126 unsigned NumOperands = 0;
14128 // Truncate operations may prevent the merge of the SETCC instruction
14129 // and the arithmetic instruction before it. Attempt to truncate the operands
14130 // of the arithmetic instruction and use a reduced bit-width instruction.
14131 bool NeedTruncation = false;
14132 SDValue ArithOp = Op;
14133 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14134 SDValue Arith = Op->getOperand(0);
14135 // Both the trunc and the arithmetic op need to have one user each.
14136 if (Arith->hasOneUse())
14137 switch (Arith.getOpcode()) {
14144 NeedTruncation = true;
14150 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14151 // which may be the result of a CAST. We use the variable 'Op', which is the
14152 // non-casted variable when we check for possible users.
14153 switch (ArithOp.getOpcode()) {
14155 // Due to an isel shortcoming, be conservative if this add is likely to be
14156 // selected as part of a load-modify-store instruction. When the root node
14157 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14158 // uses of other nodes in the match, such as the ADD in this case. This
14159 // leads to the ADD being left around and reselected, with the result being
14160 // two adds in the output. Alas, even if none our users are stores, that
14161 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14162 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14163 // climbing the DAG back to the root, and it doesn't seem to be worth the
14165 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14166 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14167 if (UI->getOpcode() != ISD::CopyToReg &&
14168 UI->getOpcode() != ISD::SETCC &&
14169 UI->getOpcode() != ISD::STORE)
14172 if (ConstantSDNode *C =
14173 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14174 // An add of one will be selected as an INC.
14175 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14176 Opcode = X86ISD::INC;
14181 // An add of negative one (subtract of one) will be selected as a DEC.
14182 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14183 Opcode = X86ISD::DEC;
14189 // Otherwise use a regular EFLAGS-setting add.
14190 Opcode = X86ISD::ADD;
14195 // If we have a constant logical shift that's only used in a comparison
14196 // against zero turn it into an equivalent AND. This allows turning it into
14197 // a TEST instruction later.
14198 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14199 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14200 EVT VT = Op.getValueType();
14201 unsigned BitWidth = VT.getSizeInBits();
14202 unsigned ShAmt = Op->getConstantOperandVal(1);
14203 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14205 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14206 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14207 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14208 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14210 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14211 DAG.getConstant(Mask, VT));
14212 DAG.ReplaceAllUsesWith(Op, New);
14218 // If the primary and result isn't used, don't bother using X86ISD::AND,
14219 // because a TEST instruction will be better.
14220 if (!hasNonFlagsUse(Op))
14226 // Due to the ISEL shortcoming noted above, be conservative if this op is
14227 // likely to be selected as part of a load-modify-store instruction.
14228 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14229 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14230 if (UI->getOpcode() == ISD::STORE)
14233 // Otherwise use a regular EFLAGS-setting instruction.
14234 switch (ArithOp.getOpcode()) {
14235 default: llvm_unreachable("unexpected operator!");
14236 case ISD::SUB: Opcode = X86ISD::SUB; break;
14237 case ISD::XOR: Opcode = X86ISD::XOR; break;
14238 case ISD::AND: Opcode = X86ISD::AND; break;
14240 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14241 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14242 if (EFLAGS.getNode())
14245 Opcode = X86ISD::OR;
14259 return SDValue(Op.getNode(), 1);
14265 // If we found that truncation is beneficial, perform the truncation and
14267 if (NeedTruncation) {
14268 EVT VT = Op.getValueType();
14269 SDValue WideVal = Op->getOperand(0);
14270 EVT WideVT = WideVal.getValueType();
14271 unsigned ConvertedOp = 0;
14272 // Use a target machine opcode to prevent further DAGCombine
14273 // optimizations that may separate the arithmetic operations
14274 // from the setcc node.
14275 switch (WideVal.getOpcode()) {
14277 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14278 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14279 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14280 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14281 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14285 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14286 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14287 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14288 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14289 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14295 // Emit a CMP with 0, which is the TEST pattern.
14296 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14297 DAG.getConstant(0, Op.getValueType()));
14299 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14300 SmallVector<SDValue, 4> Ops;
14301 for (unsigned i = 0; i != NumOperands; ++i)
14302 Ops.push_back(Op.getOperand(i));
14304 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14305 DAG.ReplaceAllUsesWith(Op, New);
14306 return SDValue(New.getNode(), 1);
14309 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14311 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14312 SDLoc dl, SelectionDAG &DAG) const {
14313 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14314 if (C->getAPIntValue() == 0)
14315 return EmitTest(Op0, X86CC, dl, DAG);
14317 if (Op0.getValueType() == MVT::i1)
14318 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14321 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14322 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14323 // Do the comparison at i32 if it's smaller, besides the Atom case.
14324 // This avoids subregister aliasing issues. Keep the smaller reference
14325 // if we're optimizing for size, however, as that'll allow better folding
14326 // of memory operations.
14327 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14328 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14329 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14330 !Subtarget->isAtom()) {
14331 unsigned ExtendOp =
14332 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14333 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14334 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14336 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14337 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14338 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14340 return SDValue(Sub.getNode(), 1);
14342 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14345 /// Convert a comparison if required by the subtarget.
14346 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14347 SelectionDAG &DAG) const {
14348 // If the subtarget does not support the FUCOMI instruction, floating-point
14349 // comparisons have to be converted.
14350 if (Subtarget->hasCMov() ||
14351 Cmp.getOpcode() != X86ISD::CMP ||
14352 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14353 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14356 // The instruction selector will select an FUCOM instruction instead of
14357 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14358 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14359 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14361 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14362 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14363 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14364 DAG.getConstant(8, MVT::i8));
14365 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14366 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14369 /// The minimum architected relative accuracy is 2^-12. We need one
14370 /// Newton-Raphson step to have a good float result (24 bits of precision).
14371 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14372 DAGCombinerInfo &DCI,
14373 unsigned &RefinementSteps,
14374 bool &UseOneConstNR) const {
14375 // FIXME: We should use instruction latency models to calculate the cost of
14376 // each potential sequence, but this is very hard to do reliably because
14377 // at least Intel's Core* chips have variable timing based on the number of
14378 // significant digits in the divisor and/or sqrt operand.
14379 if (!Subtarget->useSqrtEst())
14382 EVT VT = Op.getValueType();
14384 // SSE1 has rsqrtss and rsqrtps.
14385 // TODO: Add support for AVX512 (v16f32).
14386 // It is likely not profitable to do this for f64 because a double-precision
14387 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14388 // instructions: convert to single, rsqrtss, convert back to double, refine
14389 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14390 // along with FMA, this could be a throughput win.
14391 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14392 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14393 RefinementSteps = 1;
14394 UseOneConstNR = false;
14395 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14400 static bool isAllOnes(SDValue V) {
14401 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14402 return C && C->isAllOnesValue();
14405 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14406 /// if it's possible.
14407 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14408 SDLoc dl, SelectionDAG &DAG) const {
14409 SDValue Op0 = And.getOperand(0);
14410 SDValue Op1 = And.getOperand(1);
14411 if (Op0.getOpcode() == ISD::TRUNCATE)
14412 Op0 = Op0.getOperand(0);
14413 if (Op1.getOpcode() == ISD::TRUNCATE)
14414 Op1 = Op1.getOperand(0);
14417 if (Op1.getOpcode() == ISD::SHL)
14418 std::swap(Op0, Op1);
14419 if (Op0.getOpcode() == ISD::SHL) {
14420 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14421 if (And00C->getZExtValue() == 1) {
14422 // If we looked past a truncate, check that it's only truncating away
14424 unsigned BitWidth = Op0.getValueSizeInBits();
14425 unsigned AndBitWidth = And.getValueSizeInBits();
14426 if (BitWidth > AndBitWidth) {
14428 DAG.computeKnownBits(Op0, Zeros, Ones);
14429 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14433 RHS = Op0.getOperand(1);
14435 } else if (Op1.getOpcode() == ISD::Constant) {
14436 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14437 uint64_t AndRHSVal = AndRHS->getZExtValue();
14438 SDValue AndLHS = Op0;
14440 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14441 LHS = AndLHS.getOperand(0);
14442 RHS = AndLHS.getOperand(1);
14445 // Use BT if the immediate can't be encoded in a TEST instruction.
14446 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14448 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14452 if (LHS.getNode()) {
14453 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14454 // instruction. Since the shift amount is in-range-or-undefined, we know
14455 // that doing a bittest on the i32 value is ok. We extend to i32 because
14456 // the encoding for the i16 version is larger than the i32 version.
14457 // Also promote i16 to i32 for performance / code size reason.
14458 if (LHS.getValueType() == MVT::i8 ||
14459 LHS.getValueType() == MVT::i16)
14460 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14462 // If the operand types disagree, extend the shift amount to match. Since
14463 // BT ignores high bits (like shifts) we can use anyextend.
14464 if (LHS.getValueType() != RHS.getValueType())
14465 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14467 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14468 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14469 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14470 DAG.getConstant(Cond, MVT::i8), BT);
14476 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14478 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14483 // SSE Condition code mapping:
14492 switch (SetCCOpcode) {
14493 default: llvm_unreachable("Unexpected SETCC condition");
14495 case ISD::SETEQ: SSECC = 0; break;
14497 case ISD::SETGT: Swap = true; // Fallthrough
14499 case ISD::SETOLT: SSECC = 1; break;
14501 case ISD::SETGE: Swap = true; // Fallthrough
14503 case ISD::SETOLE: SSECC = 2; break;
14504 case ISD::SETUO: SSECC = 3; break;
14506 case ISD::SETNE: SSECC = 4; break;
14507 case ISD::SETULE: Swap = true; // Fallthrough
14508 case ISD::SETUGE: SSECC = 5; break;
14509 case ISD::SETULT: Swap = true; // Fallthrough
14510 case ISD::SETUGT: SSECC = 6; break;
14511 case ISD::SETO: SSECC = 7; break;
14513 case ISD::SETONE: SSECC = 8; break;
14516 std::swap(Op0, Op1);
14521 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14522 // ones, and then concatenate the result back.
14523 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14524 MVT VT = Op.getSimpleValueType();
14526 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14527 "Unsupported value type for operation");
14529 unsigned NumElems = VT.getVectorNumElements();
14531 SDValue CC = Op.getOperand(2);
14533 // Extract the LHS vectors
14534 SDValue LHS = Op.getOperand(0);
14535 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14536 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14538 // Extract the RHS vectors
14539 SDValue RHS = Op.getOperand(1);
14540 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14541 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14543 // Issue the operation on the smaller types and concatenate the result back
14544 MVT EltVT = VT.getVectorElementType();
14545 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14546 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14547 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14548 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14551 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14552 const X86Subtarget *Subtarget) {
14553 SDValue Op0 = Op.getOperand(0);
14554 SDValue Op1 = Op.getOperand(1);
14555 SDValue CC = Op.getOperand(2);
14556 MVT VT = Op.getSimpleValueType();
14559 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14560 Op.getValueType().getScalarType() == MVT::i1 &&
14561 "Cannot set masked compare for this operation");
14563 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14565 bool Unsigned = false;
14568 switch (SetCCOpcode) {
14569 default: llvm_unreachable("Unexpected SETCC condition");
14570 case ISD::SETNE: SSECC = 4; break;
14571 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14572 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14573 case ISD::SETLT: Swap = true; //fall-through
14574 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14575 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14576 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14577 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14578 case ISD::SETULE: Unsigned = true; //fall-through
14579 case ISD::SETLE: SSECC = 2; break;
14583 std::swap(Op0, Op1);
14585 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14586 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14587 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14588 DAG.getConstant(SSECC, MVT::i8));
14591 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14592 /// operand \p Op1. If non-trivial (for example because it's not constant)
14593 /// return an empty value.
14594 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14596 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14600 MVT VT = Op1.getSimpleValueType();
14601 MVT EVT = VT.getVectorElementType();
14602 unsigned n = VT.getVectorNumElements();
14603 SmallVector<SDValue, 8> ULTOp1;
14605 for (unsigned i = 0; i < n; ++i) {
14606 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14607 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14610 // Avoid underflow.
14611 APInt Val = Elt->getAPIntValue();
14615 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14618 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14621 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14622 SelectionDAG &DAG) {
14623 SDValue Op0 = Op.getOperand(0);
14624 SDValue Op1 = Op.getOperand(1);
14625 SDValue CC = Op.getOperand(2);
14626 MVT VT = Op.getSimpleValueType();
14627 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14628 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14633 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14634 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14637 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14638 unsigned Opc = X86ISD::CMPP;
14639 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14640 assert(VT.getVectorNumElements() <= 16);
14641 Opc = X86ISD::CMPM;
14643 // In the two special cases we can't handle, emit two comparisons.
14646 unsigned CombineOpc;
14647 if (SetCCOpcode == ISD::SETUEQ) {
14648 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14650 assert(SetCCOpcode == ISD::SETONE);
14651 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14654 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14655 DAG.getConstant(CC0, MVT::i8));
14656 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14657 DAG.getConstant(CC1, MVT::i8));
14658 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14660 // Handle all other FP comparisons here.
14661 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14662 DAG.getConstant(SSECC, MVT::i8));
14665 // Break 256-bit integer vector compare into smaller ones.
14666 if (VT.is256BitVector() && !Subtarget->hasInt256())
14667 return Lower256IntVSETCC(Op, DAG);
14669 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14670 EVT OpVT = Op1.getValueType();
14671 if (Subtarget->hasAVX512()) {
14672 if (Op1.getValueType().is512BitVector() ||
14673 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14674 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14675 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14677 // In AVX-512 architecture setcc returns mask with i1 elements,
14678 // But there is no compare instruction for i8 and i16 elements in KNL.
14679 // We are not talking about 512-bit operands in this case, these
14680 // types are illegal.
14682 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14683 OpVT.getVectorElementType().getSizeInBits() >= 8))
14684 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14685 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14688 // We are handling one of the integer comparisons here. Since SSE only has
14689 // GT and EQ comparisons for integer, swapping operands and multiple
14690 // operations may be required for some comparisons.
14692 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14693 bool Subus = false;
14695 switch (SetCCOpcode) {
14696 default: llvm_unreachable("Unexpected SETCC condition");
14697 case ISD::SETNE: Invert = true;
14698 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14699 case ISD::SETLT: Swap = true;
14700 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14701 case ISD::SETGE: Swap = true;
14702 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14703 Invert = true; break;
14704 case ISD::SETULT: Swap = true;
14705 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14706 FlipSigns = true; break;
14707 case ISD::SETUGE: Swap = true;
14708 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14709 FlipSigns = true; Invert = true; break;
14712 // Special case: Use min/max operations for SETULE/SETUGE
14713 MVT VET = VT.getVectorElementType();
14715 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14716 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14719 switch (SetCCOpcode) {
14721 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14722 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14725 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14728 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14729 if (!MinMax && hasSubus) {
14730 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14732 // t = psubus Op0, Op1
14733 // pcmpeq t, <0..0>
14734 switch (SetCCOpcode) {
14736 case ISD::SETULT: {
14737 // If the comparison is against a constant we can turn this into a
14738 // setule. With psubus, setule does not require a swap. This is
14739 // beneficial because the constant in the register is no longer
14740 // destructed as the destination so it can be hoisted out of a loop.
14741 // Only do this pre-AVX since vpcmp* is no longer destructive.
14742 if (Subtarget->hasAVX())
14744 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14745 if (ULEOp1.getNode()) {
14747 Subus = true; Invert = false; Swap = false;
14751 // Psubus is better than flip-sign because it requires no inversion.
14752 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14753 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14757 Opc = X86ISD::SUBUS;
14763 std::swap(Op0, Op1);
14765 // Check that the operation in question is available (most are plain SSE2,
14766 // but PCMPGTQ and PCMPEQQ have different requirements).
14767 if (VT == MVT::v2i64) {
14768 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14769 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14771 // First cast everything to the right type.
14772 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14773 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14775 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14776 // bits of the inputs before performing those operations. The lower
14777 // compare is always unsigned.
14780 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14782 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14783 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14784 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14785 Sign, Zero, Sign, Zero);
14787 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14788 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14790 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14791 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14792 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14794 // Create masks for only the low parts/high parts of the 64 bit integers.
14795 static const int MaskHi[] = { 1, 1, 3, 3 };
14796 static const int MaskLo[] = { 0, 0, 2, 2 };
14797 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14798 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14799 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14801 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14802 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14805 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14807 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14810 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14811 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14812 // pcmpeqd + pshufd + pand.
14813 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14815 // First cast everything to the right type.
14816 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14817 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14820 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14822 // Make sure the lower and upper halves are both all-ones.
14823 static const int Mask[] = { 1, 0, 3, 2 };
14824 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14825 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14828 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14830 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14834 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14835 // bits of the inputs before performing those operations.
14837 EVT EltVT = VT.getVectorElementType();
14838 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14839 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14840 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14843 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14845 // If the logical-not of the result is required, perform that now.
14847 Result = DAG.getNOT(dl, Result, VT);
14850 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14853 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14854 getZeroVector(VT, Subtarget, DAG, dl));
14859 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14861 MVT VT = Op.getSimpleValueType();
14863 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14865 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14866 && "SetCC type must be 8-bit or 1-bit integer");
14867 SDValue Op0 = Op.getOperand(0);
14868 SDValue Op1 = Op.getOperand(1);
14870 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14872 // Optimize to BT if possible.
14873 // Lower (X & (1 << N)) == 0 to BT(X, N).
14874 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14875 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14876 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14877 Op1.getOpcode() == ISD::Constant &&
14878 cast<ConstantSDNode>(Op1)->isNullValue() &&
14879 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14880 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14881 if (NewSetCC.getNode())
14885 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14887 if (Op1.getOpcode() == ISD::Constant &&
14888 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14889 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14890 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14892 // If the input is a setcc, then reuse the input setcc or use a new one with
14893 // the inverted condition.
14894 if (Op0.getOpcode() == X86ISD::SETCC) {
14895 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14896 bool Invert = (CC == ISD::SETNE) ^
14897 cast<ConstantSDNode>(Op1)->isNullValue();
14901 CCode = X86::GetOppositeBranchCondition(CCode);
14902 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14903 DAG.getConstant(CCode, MVT::i8),
14904 Op0.getOperand(1));
14906 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14910 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14911 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14912 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14914 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14915 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14918 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14919 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14920 if (X86CC == X86::COND_INVALID)
14923 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14924 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14925 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14926 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14928 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14932 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14933 static bool isX86LogicalCmp(SDValue Op) {
14934 unsigned Opc = Op.getNode()->getOpcode();
14935 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14936 Opc == X86ISD::SAHF)
14938 if (Op.getResNo() == 1 &&
14939 (Opc == X86ISD::ADD ||
14940 Opc == X86ISD::SUB ||
14941 Opc == X86ISD::ADC ||
14942 Opc == X86ISD::SBB ||
14943 Opc == X86ISD::SMUL ||
14944 Opc == X86ISD::UMUL ||
14945 Opc == X86ISD::INC ||
14946 Opc == X86ISD::DEC ||
14947 Opc == X86ISD::OR ||
14948 Opc == X86ISD::XOR ||
14949 Opc == X86ISD::AND))
14952 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14958 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14959 if (V.getOpcode() != ISD::TRUNCATE)
14962 SDValue VOp0 = V.getOperand(0);
14963 unsigned InBits = VOp0.getValueSizeInBits();
14964 unsigned Bits = V.getValueSizeInBits();
14965 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14968 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14969 bool addTest = true;
14970 SDValue Cond = Op.getOperand(0);
14971 SDValue Op1 = Op.getOperand(1);
14972 SDValue Op2 = Op.getOperand(2);
14974 EVT VT = Op1.getValueType();
14977 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14978 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14979 // sequence later on.
14980 if (Cond.getOpcode() == ISD::SETCC &&
14981 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14982 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14983 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14984 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14985 int SSECC = translateX86FSETCC(
14986 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14989 if (Subtarget->hasAVX512()) {
14990 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14991 DAG.getConstant(SSECC, MVT::i8));
14992 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14994 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14995 DAG.getConstant(SSECC, MVT::i8));
14996 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14997 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14998 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15002 if (Cond.getOpcode() == ISD::SETCC) {
15003 SDValue NewCond = LowerSETCC(Cond, DAG);
15004 if (NewCond.getNode())
15008 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15009 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15010 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15011 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15012 if (Cond.getOpcode() == X86ISD::SETCC &&
15013 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15014 isZero(Cond.getOperand(1).getOperand(1))) {
15015 SDValue Cmp = Cond.getOperand(1);
15017 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15019 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15020 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15021 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15023 SDValue CmpOp0 = Cmp.getOperand(0);
15024 // Apply further optimizations for special cases
15025 // (select (x != 0), -1, 0) -> neg & sbb
15026 // (select (x == 0), 0, -1) -> neg & sbb
15027 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15028 if (YC->isNullValue() &&
15029 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15030 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15031 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15032 DAG.getConstant(0, CmpOp0.getValueType()),
15034 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15035 DAG.getConstant(X86::COND_B, MVT::i8),
15036 SDValue(Neg.getNode(), 1));
15040 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15041 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15042 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15044 SDValue Res = // Res = 0 or -1.
15045 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15046 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15048 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15049 Res = DAG.getNOT(DL, Res, Res.getValueType());
15051 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15052 if (!N2C || !N2C->isNullValue())
15053 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15058 // Look past (and (setcc_carry (cmp ...)), 1).
15059 if (Cond.getOpcode() == ISD::AND &&
15060 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15061 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15062 if (C && C->getAPIntValue() == 1)
15063 Cond = Cond.getOperand(0);
15066 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15067 // setting operand in place of the X86ISD::SETCC.
15068 unsigned CondOpcode = Cond.getOpcode();
15069 if (CondOpcode == X86ISD::SETCC ||
15070 CondOpcode == X86ISD::SETCC_CARRY) {
15071 CC = Cond.getOperand(0);
15073 SDValue Cmp = Cond.getOperand(1);
15074 unsigned Opc = Cmp.getOpcode();
15075 MVT VT = Op.getSimpleValueType();
15077 bool IllegalFPCMov = false;
15078 if (VT.isFloatingPoint() && !VT.isVector() &&
15079 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15080 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15082 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15083 Opc == X86ISD::BT) { // FIXME
15087 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15088 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15089 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15090 Cond.getOperand(0).getValueType() != MVT::i8)) {
15091 SDValue LHS = Cond.getOperand(0);
15092 SDValue RHS = Cond.getOperand(1);
15093 unsigned X86Opcode;
15096 switch (CondOpcode) {
15097 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15098 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15099 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15100 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15101 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15102 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15103 default: llvm_unreachable("unexpected overflowing operator");
15105 if (CondOpcode == ISD::UMULO)
15106 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15109 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15111 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15113 if (CondOpcode == ISD::UMULO)
15114 Cond = X86Op.getValue(2);
15116 Cond = X86Op.getValue(1);
15118 CC = DAG.getConstant(X86Cond, MVT::i8);
15123 // Look pass the truncate if the high bits are known zero.
15124 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15125 Cond = Cond.getOperand(0);
15127 // We know the result of AND is compared against zero. Try to match
15129 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15130 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15131 if (NewSetCC.getNode()) {
15132 CC = NewSetCC.getOperand(0);
15133 Cond = NewSetCC.getOperand(1);
15140 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15141 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15144 // a < b ? -1 : 0 -> RES = ~setcc_carry
15145 // a < b ? 0 : -1 -> RES = setcc_carry
15146 // a >= b ? -1 : 0 -> RES = setcc_carry
15147 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15148 if (Cond.getOpcode() == X86ISD::SUB) {
15149 Cond = ConvertCmpIfNecessary(Cond, DAG);
15150 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15152 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15153 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15154 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15155 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15156 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15157 return DAG.getNOT(DL, Res, Res.getValueType());
15162 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15163 // widen the cmov and push the truncate through. This avoids introducing a new
15164 // branch during isel and doesn't add any extensions.
15165 if (Op.getValueType() == MVT::i8 &&
15166 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15167 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15168 if (T1.getValueType() == T2.getValueType() &&
15169 // Blacklist CopyFromReg to avoid partial register stalls.
15170 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15171 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15172 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15173 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15177 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15178 // condition is true.
15179 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15180 SDValue Ops[] = { Op2, Op1, CC, Cond };
15181 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15184 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15185 SelectionDAG &DAG) {
15186 MVT VT = Op->getSimpleValueType(0);
15187 SDValue In = Op->getOperand(0);
15188 MVT InVT = In.getSimpleValueType();
15189 MVT VTElt = VT.getVectorElementType();
15190 MVT InVTElt = InVT.getVectorElementType();
15194 if ((InVTElt == MVT::i1) &&
15195 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15196 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15198 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15199 VTElt.getSizeInBits() <= 16)) ||
15201 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15202 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15204 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15205 VTElt.getSizeInBits() >= 32))))
15206 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15208 unsigned int NumElts = VT.getVectorNumElements();
15210 if (NumElts != 8 && NumElts != 16)
15213 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15214 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15216 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15217 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15219 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15220 Constant *C = ConstantInt::get(*DAG.getContext(),
15221 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15223 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15224 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15225 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15226 MachinePointerInfo::getConstantPool(),
15227 false, false, false, Alignment);
15228 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15229 if (VT.is512BitVector())
15231 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15234 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15235 SelectionDAG &DAG) {
15236 MVT VT = Op->getSimpleValueType(0);
15237 SDValue In = Op->getOperand(0);
15238 MVT InVT = In.getSimpleValueType();
15241 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15242 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15244 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15245 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15246 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15249 if (Subtarget->hasInt256())
15250 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15252 // Optimize vectors in AVX mode
15253 // Sign extend v8i16 to v8i32 and
15256 // Divide input vector into two parts
15257 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15258 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15259 // concat the vectors to original VT
15261 unsigned NumElems = InVT.getVectorNumElements();
15262 SDValue Undef = DAG.getUNDEF(InVT);
15264 SmallVector<int,8> ShufMask1(NumElems, -1);
15265 for (unsigned i = 0; i != NumElems/2; ++i)
15268 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15270 SmallVector<int,8> ShufMask2(NumElems, -1);
15271 for (unsigned i = 0; i != NumElems/2; ++i)
15272 ShufMask2[i] = i + NumElems/2;
15274 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15276 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15277 VT.getVectorNumElements()/2);
15279 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15280 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15282 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15285 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15286 // may emit an illegal shuffle but the expansion is still better than scalar
15287 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15288 // we'll emit a shuffle and a arithmetic shift.
15289 // TODO: It is possible to support ZExt by zeroing the undef values during
15290 // the shuffle phase or after the shuffle.
15291 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15292 SelectionDAG &DAG) {
15293 MVT RegVT = Op.getSimpleValueType();
15294 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15295 assert(RegVT.isInteger() &&
15296 "We only custom lower integer vector sext loads.");
15298 // Nothing useful we can do without SSE2 shuffles.
15299 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15301 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15303 EVT MemVT = Ld->getMemoryVT();
15304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15305 unsigned RegSz = RegVT.getSizeInBits();
15307 ISD::LoadExtType Ext = Ld->getExtensionType();
15309 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15310 && "Only anyext and sext are currently implemented.");
15311 assert(MemVT != RegVT && "Cannot extend to the same type");
15312 assert(MemVT.isVector() && "Must load a vector from memory");
15314 unsigned NumElems = RegVT.getVectorNumElements();
15315 unsigned MemSz = MemVT.getSizeInBits();
15316 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15318 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15319 // The only way in which we have a legal 256-bit vector result but not the
15320 // integer 256-bit operations needed to directly lower a sextload is if we
15321 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15322 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15323 // correctly legalized. We do this late to allow the canonical form of
15324 // sextload to persist throughout the rest of the DAG combiner -- it wants
15325 // to fold together any extensions it can, and so will fuse a sign_extend
15326 // of an sextload into a sextload targeting a wider value.
15328 if (MemSz == 128) {
15329 // Just switch this to a normal load.
15330 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15331 "it must be a legal 128-bit vector "
15333 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15334 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15335 Ld->isInvariant(), Ld->getAlignment());
15337 assert(MemSz < 128 &&
15338 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15339 // Do an sext load to a 128-bit vector type. We want to use the same
15340 // number of elements, but elements half as wide. This will end up being
15341 // recursively lowered by this routine, but will succeed as we definitely
15342 // have all the necessary features if we're using AVX1.
15344 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15345 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15347 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15348 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15349 Ld->isNonTemporal(), Ld->isInvariant(),
15350 Ld->getAlignment());
15353 // Replace chain users with the new chain.
15354 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15355 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15357 // Finally, do a normal sign-extend to the desired register.
15358 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15361 // All sizes must be a power of two.
15362 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15363 "Non-power-of-two elements are not custom lowered!");
15365 // Attempt to load the original value using scalar loads.
15366 // Find the largest scalar type that divides the total loaded size.
15367 MVT SclrLoadTy = MVT::i8;
15368 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15369 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15370 MVT Tp = (MVT::SimpleValueType)tp;
15371 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15376 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15377 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15379 SclrLoadTy = MVT::f64;
15381 // Calculate the number of scalar loads that we need to perform
15382 // in order to load our vector from memory.
15383 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15385 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15386 "Can only lower sext loads with a single scalar load!");
15388 unsigned loadRegZize = RegSz;
15389 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15392 // Represent our vector as a sequence of elements which are the
15393 // largest scalar that we can load.
15394 EVT LoadUnitVecVT = EVT::getVectorVT(
15395 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15397 // Represent the data using the same element type that is stored in
15398 // memory. In practice, we ''widen'' MemVT.
15400 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15401 loadRegZize / MemVT.getScalarType().getSizeInBits());
15403 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15404 "Invalid vector type");
15406 // We can't shuffle using an illegal type.
15407 assert(TLI.isTypeLegal(WideVecVT) &&
15408 "We only lower types that form legal widened vector types");
15410 SmallVector<SDValue, 8> Chains;
15411 SDValue Ptr = Ld->getBasePtr();
15412 SDValue Increment =
15413 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15414 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15416 for (unsigned i = 0; i < NumLoads; ++i) {
15417 // Perform a single load.
15418 SDValue ScalarLoad =
15419 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15420 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15421 Ld->getAlignment());
15422 Chains.push_back(ScalarLoad.getValue(1));
15423 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15424 // another round of DAGCombining.
15426 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15428 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15429 ScalarLoad, DAG.getIntPtrConstant(i));
15431 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15434 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15436 // Bitcast the loaded value to a vector of the original element type, in
15437 // the size of the target vector type.
15438 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15439 unsigned SizeRatio = RegSz / MemSz;
15441 if (Ext == ISD::SEXTLOAD) {
15442 // If we have SSE4.1, we can directly emit a VSEXT node.
15443 if (Subtarget->hasSSE41()) {
15444 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15445 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15449 // Otherwise we'll shuffle the small elements in the high bits of the
15450 // larger type and perform an arithmetic shift. If the shift is not legal
15451 // it's better to scalarize.
15452 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15453 "We can't implement a sext load without an arithmetic right shift!");
15455 // Redistribute the loaded elements into the different locations.
15456 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15457 for (unsigned i = 0; i != NumElems; ++i)
15458 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15460 SDValue Shuff = DAG.getVectorShuffle(
15461 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15463 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15465 // Build the arithmetic shift.
15466 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15467 MemVT.getVectorElementType().getSizeInBits();
15469 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15471 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15475 // Redistribute the loaded elements into the different locations.
15476 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15477 for (unsigned i = 0; i != NumElems; ++i)
15478 ShuffleVec[i * SizeRatio] = i;
15480 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15481 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15483 // Bitcast to the requested type.
15484 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15485 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15489 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15490 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15491 // from the AND / OR.
15492 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15493 Opc = Op.getOpcode();
15494 if (Opc != ISD::OR && Opc != ISD::AND)
15496 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15497 Op.getOperand(0).hasOneUse() &&
15498 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15499 Op.getOperand(1).hasOneUse());
15502 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15503 // 1 and that the SETCC node has a single use.
15504 static bool isXor1OfSetCC(SDValue Op) {
15505 if (Op.getOpcode() != ISD::XOR)
15507 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15508 if (N1C && N1C->getAPIntValue() == 1) {
15509 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15510 Op.getOperand(0).hasOneUse();
15515 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15516 bool addTest = true;
15517 SDValue Chain = Op.getOperand(0);
15518 SDValue Cond = Op.getOperand(1);
15519 SDValue Dest = Op.getOperand(2);
15522 bool Inverted = false;
15524 if (Cond.getOpcode() == ISD::SETCC) {
15525 // Check for setcc([su]{add,sub,mul}o == 0).
15526 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15527 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15528 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15529 Cond.getOperand(0).getResNo() == 1 &&
15530 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15531 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15532 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15533 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15534 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15535 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15537 Cond = Cond.getOperand(0);
15539 SDValue NewCond = LowerSETCC(Cond, DAG);
15540 if (NewCond.getNode())
15545 // FIXME: LowerXALUO doesn't handle these!!
15546 else if (Cond.getOpcode() == X86ISD::ADD ||
15547 Cond.getOpcode() == X86ISD::SUB ||
15548 Cond.getOpcode() == X86ISD::SMUL ||
15549 Cond.getOpcode() == X86ISD::UMUL)
15550 Cond = LowerXALUO(Cond, DAG);
15553 // Look pass (and (setcc_carry (cmp ...)), 1).
15554 if (Cond.getOpcode() == ISD::AND &&
15555 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15556 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15557 if (C && C->getAPIntValue() == 1)
15558 Cond = Cond.getOperand(0);
15561 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15562 // setting operand in place of the X86ISD::SETCC.
15563 unsigned CondOpcode = Cond.getOpcode();
15564 if (CondOpcode == X86ISD::SETCC ||
15565 CondOpcode == X86ISD::SETCC_CARRY) {
15566 CC = Cond.getOperand(0);
15568 SDValue Cmp = Cond.getOperand(1);
15569 unsigned Opc = Cmp.getOpcode();
15570 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15571 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15575 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15579 // These can only come from an arithmetic instruction with overflow,
15580 // e.g. SADDO, UADDO.
15581 Cond = Cond.getNode()->getOperand(1);
15587 CondOpcode = Cond.getOpcode();
15588 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15589 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15590 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15591 Cond.getOperand(0).getValueType() != MVT::i8)) {
15592 SDValue LHS = Cond.getOperand(0);
15593 SDValue RHS = Cond.getOperand(1);
15594 unsigned X86Opcode;
15597 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15598 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15600 switch (CondOpcode) {
15601 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15603 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15605 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15608 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15609 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15613 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15616 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15617 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15618 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15619 default: llvm_unreachable("unexpected overflowing operator");
15622 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15623 if (CondOpcode == ISD::UMULO)
15624 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15627 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15629 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15631 if (CondOpcode == ISD::UMULO)
15632 Cond = X86Op.getValue(2);
15634 Cond = X86Op.getValue(1);
15636 CC = DAG.getConstant(X86Cond, MVT::i8);
15640 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15641 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15642 if (CondOpc == ISD::OR) {
15643 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15644 // two branches instead of an explicit OR instruction with a
15646 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15647 isX86LogicalCmp(Cmp)) {
15648 CC = Cond.getOperand(0).getOperand(0);
15649 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15650 Chain, Dest, CC, Cmp);
15651 CC = Cond.getOperand(1).getOperand(0);
15655 } else { // ISD::AND
15656 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15657 // two branches instead of an explicit AND instruction with a
15658 // separate test. However, we only do this if this block doesn't
15659 // have a fall-through edge, because this requires an explicit
15660 // jmp when the condition is false.
15661 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15662 isX86LogicalCmp(Cmp) &&
15663 Op.getNode()->hasOneUse()) {
15664 X86::CondCode CCode =
15665 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15666 CCode = X86::GetOppositeBranchCondition(CCode);
15667 CC = DAG.getConstant(CCode, MVT::i8);
15668 SDNode *User = *Op.getNode()->use_begin();
15669 // Look for an unconditional branch following this conditional branch.
15670 // We need this because we need to reverse the successors in order
15671 // to implement FCMP_OEQ.
15672 if (User->getOpcode() == ISD::BR) {
15673 SDValue FalseBB = User->getOperand(1);
15675 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15676 assert(NewBR == User);
15680 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15681 Chain, Dest, CC, Cmp);
15682 X86::CondCode CCode =
15683 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15684 CCode = X86::GetOppositeBranchCondition(CCode);
15685 CC = DAG.getConstant(CCode, MVT::i8);
15691 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15692 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15693 // It should be transformed during dag combiner except when the condition
15694 // is set by a arithmetics with overflow node.
15695 X86::CondCode CCode =
15696 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15697 CCode = X86::GetOppositeBranchCondition(CCode);
15698 CC = DAG.getConstant(CCode, MVT::i8);
15699 Cond = Cond.getOperand(0).getOperand(1);
15701 } else if (Cond.getOpcode() == ISD::SETCC &&
15702 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15703 // For FCMP_OEQ, we can emit
15704 // two branches instead of an explicit AND instruction with a
15705 // separate test. However, we only do this if this block doesn't
15706 // have a fall-through edge, because this requires an explicit
15707 // jmp when the condition is false.
15708 if (Op.getNode()->hasOneUse()) {
15709 SDNode *User = *Op.getNode()->use_begin();
15710 // Look for an unconditional branch following this conditional branch.
15711 // We need this because we need to reverse the successors in order
15712 // to implement FCMP_OEQ.
15713 if (User->getOpcode() == ISD::BR) {
15714 SDValue FalseBB = User->getOperand(1);
15716 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15717 assert(NewBR == User);
15721 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15722 Cond.getOperand(0), Cond.getOperand(1));
15723 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15724 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15725 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15726 Chain, Dest, CC, Cmp);
15727 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15732 } else if (Cond.getOpcode() == ISD::SETCC &&
15733 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15734 // For FCMP_UNE, we can emit
15735 // two branches instead of an explicit AND instruction with a
15736 // separate test. However, we only do this if this block doesn't
15737 // have a fall-through edge, because this requires an explicit
15738 // jmp when the condition is false.
15739 if (Op.getNode()->hasOneUse()) {
15740 SDNode *User = *Op.getNode()->use_begin();
15741 // Look for an unconditional branch following this conditional branch.
15742 // We need this because we need to reverse the successors in order
15743 // to implement FCMP_UNE.
15744 if (User->getOpcode() == ISD::BR) {
15745 SDValue FalseBB = User->getOperand(1);
15747 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15748 assert(NewBR == User);
15751 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15752 Cond.getOperand(0), Cond.getOperand(1));
15753 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15754 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15755 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15756 Chain, Dest, CC, Cmp);
15757 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15767 // Look pass the truncate if the high bits are known zero.
15768 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15769 Cond = Cond.getOperand(0);
15771 // We know the result of AND is compared against zero. Try to match
15773 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15774 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15775 if (NewSetCC.getNode()) {
15776 CC = NewSetCC.getOperand(0);
15777 Cond = NewSetCC.getOperand(1);
15784 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15785 CC = DAG.getConstant(X86Cond, MVT::i8);
15786 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15788 Cond = ConvertCmpIfNecessary(Cond, DAG);
15789 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15790 Chain, Dest, CC, Cond);
15793 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15794 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15795 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15796 // that the guard pages used by the OS virtual memory manager are allocated in
15797 // correct sequence.
15799 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15800 SelectionDAG &DAG) const {
15801 MachineFunction &MF = DAG.getMachineFunction();
15802 bool SplitStack = MF.shouldSplitStack();
15803 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15809 SDNode* Node = Op.getNode();
15811 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15812 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15813 " not tell us which reg is the stack pointer!");
15814 EVT VT = Node->getValueType(0);
15815 SDValue Tmp1 = SDValue(Node, 0);
15816 SDValue Tmp2 = SDValue(Node, 1);
15817 SDValue Tmp3 = Node->getOperand(2);
15818 SDValue Chain = Tmp1.getOperand(0);
15820 // Chain the dynamic stack allocation so that it doesn't modify the stack
15821 // pointer when other instructions are using the stack.
15822 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15825 SDValue Size = Tmp2.getOperand(1);
15826 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15827 Chain = SP.getValue(1);
15828 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15829 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15830 unsigned StackAlign = TFI.getStackAlignment();
15831 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15832 if (Align > StackAlign)
15833 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15834 DAG.getConstant(-(uint64_t)Align, VT));
15835 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15837 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15838 DAG.getIntPtrConstant(0, true), SDValue(),
15841 SDValue Ops[2] = { Tmp1, Tmp2 };
15842 return DAG.getMergeValues(Ops, dl);
15846 SDValue Chain = Op.getOperand(0);
15847 SDValue Size = Op.getOperand(1);
15848 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15849 EVT VT = Op.getNode()->getValueType(0);
15851 bool Is64Bit = Subtarget->is64Bit();
15852 EVT SPTy = getPointerTy();
15855 MachineRegisterInfo &MRI = MF.getRegInfo();
15858 // The 64 bit implementation of segmented stacks needs to clobber both r10
15859 // r11. This makes it impossible to use it along with nested parameters.
15860 const Function *F = MF.getFunction();
15862 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15864 if (I->hasNestAttr())
15865 report_fatal_error("Cannot use segmented stacks with functions that "
15866 "have nested arguments.");
15869 const TargetRegisterClass *AddrRegClass =
15870 getRegClassFor(getPointerTy());
15871 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15872 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15873 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15874 DAG.getRegister(Vreg, SPTy));
15875 SDValue Ops1[2] = { Value, Chain };
15876 return DAG.getMergeValues(Ops1, dl);
15879 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15881 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15882 Flag = Chain.getValue(1);
15883 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15885 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15887 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15888 DAG.getSubtarget().getRegisterInfo());
15889 unsigned SPReg = RegInfo->getStackRegister();
15890 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15891 Chain = SP.getValue(1);
15894 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15895 DAG.getConstant(-(uint64_t)Align, VT));
15896 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15899 SDValue Ops1[2] = { SP, Chain };
15900 return DAG.getMergeValues(Ops1, dl);
15904 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15905 MachineFunction &MF = DAG.getMachineFunction();
15906 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15908 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15911 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15912 // vastart just stores the address of the VarArgsFrameIndex slot into the
15913 // memory location argument.
15914 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15916 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15917 MachinePointerInfo(SV), false, false, 0);
15921 // gp_offset (0 - 6 * 8)
15922 // fp_offset (48 - 48 + 8 * 16)
15923 // overflow_arg_area (point to parameters coming in memory).
15925 SmallVector<SDValue, 8> MemOps;
15926 SDValue FIN = Op.getOperand(1);
15928 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15929 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15931 FIN, MachinePointerInfo(SV), false, false, 0);
15932 MemOps.push_back(Store);
15935 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15936 FIN, DAG.getIntPtrConstant(4));
15937 Store = DAG.getStore(Op.getOperand(0), DL,
15938 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15940 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15941 MemOps.push_back(Store);
15943 // Store ptr to overflow_arg_area
15944 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15945 FIN, DAG.getIntPtrConstant(4));
15946 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15948 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15949 MachinePointerInfo(SV, 8),
15951 MemOps.push_back(Store);
15953 // Store ptr to reg_save_area.
15954 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15955 FIN, DAG.getIntPtrConstant(8));
15956 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15958 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15959 MachinePointerInfo(SV, 16), false, false, 0);
15960 MemOps.push_back(Store);
15961 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15964 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15965 assert(Subtarget->is64Bit() &&
15966 "LowerVAARG only handles 64-bit va_arg!");
15967 assert((Subtarget->isTargetLinux() ||
15968 Subtarget->isTargetDarwin()) &&
15969 "Unhandled target in LowerVAARG");
15970 assert(Op.getNode()->getNumOperands() == 4);
15971 SDValue Chain = Op.getOperand(0);
15972 SDValue SrcPtr = Op.getOperand(1);
15973 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15974 unsigned Align = Op.getConstantOperandVal(3);
15977 EVT ArgVT = Op.getNode()->getValueType(0);
15978 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15979 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15982 // Decide which area this value should be read from.
15983 // TODO: Implement the AMD64 ABI in its entirety. This simple
15984 // selection mechanism works only for the basic types.
15985 if (ArgVT == MVT::f80) {
15986 llvm_unreachable("va_arg for f80 not yet implemented");
15987 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15988 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15989 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15990 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15992 llvm_unreachable("Unhandled argument type in LowerVAARG");
15995 if (ArgMode == 2) {
15996 // Sanity Check: Make sure using fp_offset makes sense.
15997 assert(!DAG.getTarget().Options.UseSoftFloat &&
15998 !(DAG.getMachineFunction()
15999 .getFunction()->getAttributes()
16000 .hasAttribute(AttributeSet::FunctionIndex,
16001 Attribute::NoImplicitFloat)) &&
16002 Subtarget->hasSSE1());
16005 // Insert VAARG_64 node into the DAG
16006 // VAARG_64 returns two values: Variable Argument Address, Chain
16007 SmallVector<SDValue, 11> InstOps;
16008 InstOps.push_back(Chain);
16009 InstOps.push_back(SrcPtr);
16010 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16011 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16012 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16013 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16014 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16015 VTs, InstOps, MVT::i64,
16016 MachinePointerInfo(SV),
16018 /*Volatile=*/false,
16020 /*WriteMem=*/true);
16021 Chain = VAARG.getValue(1);
16023 // Load the next argument and return it
16024 return DAG.getLoad(ArgVT, dl,
16027 MachinePointerInfo(),
16028 false, false, false, 0);
16031 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16032 SelectionDAG &DAG) {
16033 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16034 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16035 SDValue Chain = Op.getOperand(0);
16036 SDValue DstPtr = Op.getOperand(1);
16037 SDValue SrcPtr = Op.getOperand(2);
16038 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16039 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16042 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16043 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16045 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16048 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16049 // amount is a constant. Takes immediate version of shift as input.
16050 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16051 SDValue SrcOp, uint64_t ShiftAmt,
16052 SelectionDAG &DAG) {
16053 MVT ElementType = VT.getVectorElementType();
16055 // Fold this packed shift into its first operand if ShiftAmt is 0.
16059 // Check for ShiftAmt >= element width
16060 if (ShiftAmt >= ElementType.getSizeInBits()) {
16061 if (Opc == X86ISD::VSRAI)
16062 ShiftAmt = ElementType.getSizeInBits() - 1;
16064 return DAG.getConstant(0, VT);
16067 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16068 && "Unknown target vector shift-by-constant node");
16070 // Fold this packed vector shift into a build vector if SrcOp is a
16071 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16072 if (VT == SrcOp.getSimpleValueType() &&
16073 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16074 SmallVector<SDValue, 8> Elts;
16075 unsigned NumElts = SrcOp->getNumOperands();
16076 ConstantSDNode *ND;
16079 default: llvm_unreachable(nullptr);
16080 case X86ISD::VSHLI:
16081 for (unsigned i=0; i!=NumElts; ++i) {
16082 SDValue CurrentOp = SrcOp->getOperand(i);
16083 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16084 Elts.push_back(CurrentOp);
16087 ND = cast<ConstantSDNode>(CurrentOp);
16088 const APInt &C = ND->getAPIntValue();
16089 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16092 case X86ISD::VSRLI:
16093 for (unsigned i=0; i!=NumElts; ++i) {
16094 SDValue CurrentOp = SrcOp->getOperand(i);
16095 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16096 Elts.push_back(CurrentOp);
16099 ND = cast<ConstantSDNode>(CurrentOp);
16100 const APInt &C = ND->getAPIntValue();
16101 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16104 case X86ISD::VSRAI:
16105 for (unsigned i=0; i!=NumElts; ++i) {
16106 SDValue CurrentOp = SrcOp->getOperand(i);
16107 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16108 Elts.push_back(CurrentOp);
16111 ND = cast<ConstantSDNode>(CurrentOp);
16112 const APInt &C = ND->getAPIntValue();
16113 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16118 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16121 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16124 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16125 // may or may not be a constant. Takes immediate version of shift as input.
16126 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16127 SDValue SrcOp, SDValue ShAmt,
16128 SelectionDAG &DAG) {
16129 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16131 // Catch shift-by-constant.
16132 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16133 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16134 CShAmt->getZExtValue(), DAG);
16136 // Change opcode to non-immediate version
16138 default: llvm_unreachable("Unknown target vector shift node");
16139 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16140 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16141 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16144 // Need to build a vector containing shift amount
16145 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16148 ShOps[1] = DAG.getConstant(0, MVT::i32);
16149 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16150 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16152 // The return type has to be a 128-bit type with the same element
16153 // type as the input type.
16154 MVT EltVT = VT.getVectorElementType();
16155 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16157 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16158 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16161 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16162 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16163 /// necessary casting for \p Mask when lowering masking intrinsics.
16164 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16165 SDValue PreservedSrc, SelectionDAG &DAG) {
16166 EVT VT = Op.getValueType();
16167 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16168 MVT::i1, VT.getVectorNumElements());
16169 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16170 Mask.getValueType().getSizeInBits());
16173 assert(MaskVT.isSimple() && "invalid mask type");
16175 if (isAllOnes(Mask))
16178 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16179 // are extracted by EXTRACT_SUBVECTOR.
16180 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16181 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16182 DAG.getIntPtrConstant(0));
16184 switch (Op.getOpcode()) {
16186 case X86ISD::PCMPEQM:
16187 case X86ISD::PCMPGTM:
16189 case X86ISD::CMPMU:
16190 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16193 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16196 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16198 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16199 case Intrinsic::x86_fma_vfmadd_ps:
16200 case Intrinsic::x86_fma_vfmadd_pd:
16201 case Intrinsic::x86_fma_vfmadd_ps_256:
16202 case Intrinsic::x86_fma_vfmadd_pd_256:
16203 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16204 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16205 return X86ISD::FMADD;
16206 case Intrinsic::x86_fma_vfmsub_ps:
16207 case Intrinsic::x86_fma_vfmsub_pd:
16208 case Intrinsic::x86_fma_vfmsub_ps_256:
16209 case Intrinsic::x86_fma_vfmsub_pd_256:
16210 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16211 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16212 return X86ISD::FMSUB;
16213 case Intrinsic::x86_fma_vfnmadd_ps:
16214 case Intrinsic::x86_fma_vfnmadd_pd:
16215 case Intrinsic::x86_fma_vfnmadd_ps_256:
16216 case Intrinsic::x86_fma_vfnmadd_pd_256:
16217 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16218 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16219 return X86ISD::FNMADD;
16220 case Intrinsic::x86_fma_vfnmsub_ps:
16221 case Intrinsic::x86_fma_vfnmsub_pd:
16222 case Intrinsic::x86_fma_vfnmsub_ps_256:
16223 case Intrinsic::x86_fma_vfnmsub_pd_256:
16224 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16225 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16226 return X86ISD::FNMSUB;
16227 case Intrinsic::x86_fma_vfmaddsub_ps:
16228 case Intrinsic::x86_fma_vfmaddsub_pd:
16229 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16230 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16231 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16232 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16233 return X86ISD::FMADDSUB;
16234 case Intrinsic::x86_fma_vfmsubadd_ps:
16235 case Intrinsic::x86_fma_vfmsubadd_pd:
16236 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16237 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16238 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16239 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16240 return X86ISD::FMSUBADD;
16244 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
16246 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16248 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16250 switch(IntrData->Type) {
16251 case INTR_TYPE_1OP:
16252 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16253 case INTR_TYPE_2OP:
16254 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16256 case INTR_TYPE_3OP:
16257 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16258 Op.getOperand(2), Op.getOperand(3));
16260 case CMP_MASK_CC: {
16261 // Comparison intrinsics with masks.
16262 // Example of transformation:
16263 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16264 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16266 // (v8i1 (insert_subvector undef,
16267 // (v2i1 (and (PCMPEQM %a, %b),
16268 // (extract_subvector
16269 // (v8i1 (bitcast %mask)), 0))), 0))))
16270 EVT VT = Op.getOperand(1).getValueType();
16271 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16272 VT.getVectorNumElements());
16273 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16274 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16275 Mask.getValueType().getSizeInBits());
16277 if (IntrData->Type == CMP_MASK_CC) {
16278 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16279 Op.getOperand(2), Op.getOperand(3));
16281 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16282 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16285 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16286 DAG.getTargetConstant(0, MaskVT), DAG);
16287 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16288 DAG.getUNDEF(BitcastVT), CmpMask,
16289 DAG.getIntPtrConstant(0));
16290 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16292 case COMI: { // Comparison intrinsics
16293 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16294 SDValue LHS = Op.getOperand(1);
16295 SDValue RHS = Op.getOperand(2);
16296 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16297 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16298 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16299 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16300 DAG.getConstant(X86CC, MVT::i8), Cond);
16301 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16304 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16305 Op.getOperand(1), Op.getOperand(2), DAG);
16312 default: return SDValue(); // Don't custom lower most intrinsics.
16314 // Arithmetic intrinsics.
16315 case Intrinsic::x86_sse2_pmulu_dq:
16316 case Intrinsic::x86_avx2_pmulu_dq:
16317 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16318 Op.getOperand(1), Op.getOperand(2));
16320 case Intrinsic::x86_sse41_pmuldq:
16321 case Intrinsic::x86_avx2_pmul_dq:
16322 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16323 Op.getOperand(1), Op.getOperand(2));
16325 case Intrinsic::x86_sse2_pmulhu_w:
16326 case Intrinsic::x86_avx2_pmulhu_w:
16327 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16328 Op.getOperand(1), Op.getOperand(2));
16330 case Intrinsic::x86_sse2_pmulh_w:
16331 case Intrinsic::x86_avx2_pmulh_w:
16332 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16333 Op.getOperand(1), Op.getOperand(2));
16335 // SSE/SSE2/AVX floating point max/min intrinsics.
16336 case Intrinsic::x86_sse_max_ps:
16337 case Intrinsic::x86_sse2_max_pd:
16338 case Intrinsic::x86_avx_max_ps_256:
16339 case Intrinsic::x86_avx_max_pd_256:
16340 case Intrinsic::x86_sse_min_ps:
16341 case Intrinsic::x86_sse2_min_pd:
16342 case Intrinsic::x86_avx_min_ps_256:
16343 case Intrinsic::x86_avx_min_pd_256: {
16346 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16347 case Intrinsic::x86_sse_max_ps:
16348 case Intrinsic::x86_sse2_max_pd:
16349 case Intrinsic::x86_avx_max_ps_256:
16350 case Intrinsic::x86_avx_max_pd_256:
16351 Opcode = X86ISD::FMAX;
16353 case Intrinsic::x86_sse_min_ps:
16354 case Intrinsic::x86_sse2_min_pd:
16355 case Intrinsic::x86_avx_min_ps_256:
16356 case Intrinsic::x86_avx_min_pd_256:
16357 Opcode = X86ISD::FMIN;
16360 return DAG.getNode(Opcode, dl, Op.getValueType(),
16361 Op.getOperand(1), Op.getOperand(2));
16364 // AVX2 variable shift intrinsics
16365 case Intrinsic::x86_avx2_psllv_d:
16366 case Intrinsic::x86_avx2_psllv_q:
16367 case Intrinsic::x86_avx2_psllv_d_256:
16368 case Intrinsic::x86_avx2_psllv_q_256:
16369 case Intrinsic::x86_avx2_psrlv_d:
16370 case Intrinsic::x86_avx2_psrlv_q:
16371 case Intrinsic::x86_avx2_psrlv_d_256:
16372 case Intrinsic::x86_avx2_psrlv_q_256:
16373 case Intrinsic::x86_avx2_psrav_d:
16374 case Intrinsic::x86_avx2_psrav_d_256: {
16377 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16378 case Intrinsic::x86_avx2_psllv_d:
16379 case Intrinsic::x86_avx2_psllv_q:
16380 case Intrinsic::x86_avx2_psllv_d_256:
16381 case Intrinsic::x86_avx2_psllv_q_256:
16384 case Intrinsic::x86_avx2_psrlv_d:
16385 case Intrinsic::x86_avx2_psrlv_q:
16386 case Intrinsic::x86_avx2_psrlv_d_256:
16387 case Intrinsic::x86_avx2_psrlv_q_256:
16390 case Intrinsic::x86_avx2_psrav_d:
16391 case Intrinsic::x86_avx2_psrav_d_256:
16395 return DAG.getNode(Opcode, dl, Op.getValueType(),
16396 Op.getOperand(1), Op.getOperand(2));
16399 case Intrinsic::x86_sse2_packssdw_128:
16400 case Intrinsic::x86_sse2_packsswb_128:
16401 case Intrinsic::x86_avx2_packssdw:
16402 case Intrinsic::x86_avx2_packsswb:
16403 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16404 Op.getOperand(1), Op.getOperand(2));
16406 case Intrinsic::x86_sse2_packuswb_128:
16407 case Intrinsic::x86_sse41_packusdw:
16408 case Intrinsic::x86_avx2_packuswb:
16409 case Intrinsic::x86_avx2_packusdw:
16410 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16411 Op.getOperand(1), Op.getOperand(2));
16413 case Intrinsic::x86_ssse3_pshuf_b_128:
16414 case Intrinsic::x86_avx2_pshuf_b:
16415 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16416 Op.getOperand(1), Op.getOperand(2));
16418 case Intrinsic::x86_sse2_pshuf_d:
16419 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16420 Op.getOperand(1), Op.getOperand(2));
16422 case Intrinsic::x86_sse2_pshufl_w:
16423 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16424 Op.getOperand(1), Op.getOperand(2));
16426 case Intrinsic::x86_sse2_pshufh_w:
16427 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16428 Op.getOperand(1), Op.getOperand(2));
16430 case Intrinsic::x86_ssse3_psign_b_128:
16431 case Intrinsic::x86_ssse3_psign_w_128:
16432 case Intrinsic::x86_ssse3_psign_d_128:
16433 case Intrinsic::x86_avx2_psign_b:
16434 case Intrinsic::x86_avx2_psign_w:
16435 case Intrinsic::x86_avx2_psign_d:
16436 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16437 Op.getOperand(1), Op.getOperand(2));
16439 case Intrinsic::x86_avx2_permd:
16440 case Intrinsic::x86_avx2_permps:
16441 // Operands intentionally swapped. Mask is last operand to intrinsic,
16442 // but second operand for node/instruction.
16443 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16444 Op.getOperand(2), Op.getOperand(1));
16446 case Intrinsic::x86_avx512_mask_valign_q_512:
16447 case Intrinsic::x86_avx512_mask_valign_d_512:
16448 // Vector source operands are swapped.
16449 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16450 Op.getValueType(), Op.getOperand(2),
16453 Op.getOperand(5), Op.getOperand(4), DAG);
16455 // ptest and testp intrinsics. The intrinsic these come from are designed to
16456 // return an integer value, not just an instruction so lower it to the ptest
16457 // or testp pattern and a setcc for the result.
16458 case Intrinsic::x86_sse41_ptestz:
16459 case Intrinsic::x86_sse41_ptestc:
16460 case Intrinsic::x86_sse41_ptestnzc:
16461 case Intrinsic::x86_avx_ptestz_256:
16462 case Intrinsic::x86_avx_ptestc_256:
16463 case Intrinsic::x86_avx_ptestnzc_256:
16464 case Intrinsic::x86_avx_vtestz_ps:
16465 case Intrinsic::x86_avx_vtestc_ps:
16466 case Intrinsic::x86_avx_vtestnzc_ps:
16467 case Intrinsic::x86_avx_vtestz_pd:
16468 case Intrinsic::x86_avx_vtestc_pd:
16469 case Intrinsic::x86_avx_vtestnzc_pd:
16470 case Intrinsic::x86_avx_vtestz_ps_256:
16471 case Intrinsic::x86_avx_vtestc_ps_256:
16472 case Intrinsic::x86_avx_vtestnzc_ps_256:
16473 case Intrinsic::x86_avx_vtestz_pd_256:
16474 case Intrinsic::x86_avx_vtestc_pd_256:
16475 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16476 bool IsTestPacked = false;
16479 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16480 case Intrinsic::x86_avx_vtestz_ps:
16481 case Intrinsic::x86_avx_vtestz_pd:
16482 case Intrinsic::x86_avx_vtestz_ps_256:
16483 case Intrinsic::x86_avx_vtestz_pd_256:
16484 IsTestPacked = true; // Fallthrough
16485 case Intrinsic::x86_sse41_ptestz:
16486 case Intrinsic::x86_avx_ptestz_256:
16488 X86CC = X86::COND_E;
16490 case Intrinsic::x86_avx_vtestc_ps:
16491 case Intrinsic::x86_avx_vtestc_pd:
16492 case Intrinsic::x86_avx_vtestc_ps_256:
16493 case Intrinsic::x86_avx_vtestc_pd_256:
16494 IsTestPacked = true; // Fallthrough
16495 case Intrinsic::x86_sse41_ptestc:
16496 case Intrinsic::x86_avx_ptestc_256:
16498 X86CC = X86::COND_B;
16500 case Intrinsic::x86_avx_vtestnzc_ps:
16501 case Intrinsic::x86_avx_vtestnzc_pd:
16502 case Intrinsic::x86_avx_vtestnzc_ps_256:
16503 case Intrinsic::x86_avx_vtestnzc_pd_256:
16504 IsTestPacked = true; // Fallthrough
16505 case Intrinsic::x86_sse41_ptestnzc:
16506 case Intrinsic::x86_avx_ptestnzc_256:
16508 X86CC = X86::COND_A;
16512 SDValue LHS = Op.getOperand(1);
16513 SDValue RHS = Op.getOperand(2);
16514 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16515 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16516 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16517 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16518 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16520 case Intrinsic::x86_avx512_kortestz_w:
16521 case Intrinsic::x86_avx512_kortestc_w: {
16522 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16523 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16524 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16525 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16526 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16527 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16528 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16531 case Intrinsic::x86_sse42_pcmpistria128:
16532 case Intrinsic::x86_sse42_pcmpestria128:
16533 case Intrinsic::x86_sse42_pcmpistric128:
16534 case Intrinsic::x86_sse42_pcmpestric128:
16535 case Intrinsic::x86_sse42_pcmpistrio128:
16536 case Intrinsic::x86_sse42_pcmpestrio128:
16537 case Intrinsic::x86_sse42_pcmpistris128:
16538 case Intrinsic::x86_sse42_pcmpestris128:
16539 case Intrinsic::x86_sse42_pcmpistriz128:
16540 case Intrinsic::x86_sse42_pcmpestriz128: {
16544 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16545 case Intrinsic::x86_sse42_pcmpistria128:
16546 Opcode = X86ISD::PCMPISTRI;
16547 X86CC = X86::COND_A;
16549 case Intrinsic::x86_sse42_pcmpestria128:
16550 Opcode = X86ISD::PCMPESTRI;
16551 X86CC = X86::COND_A;
16553 case Intrinsic::x86_sse42_pcmpistric128:
16554 Opcode = X86ISD::PCMPISTRI;
16555 X86CC = X86::COND_B;
16557 case Intrinsic::x86_sse42_pcmpestric128:
16558 Opcode = X86ISD::PCMPESTRI;
16559 X86CC = X86::COND_B;
16561 case Intrinsic::x86_sse42_pcmpistrio128:
16562 Opcode = X86ISD::PCMPISTRI;
16563 X86CC = X86::COND_O;
16565 case Intrinsic::x86_sse42_pcmpestrio128:
16566 Opcode = X86ISD::PCMPESTRI;
16567 X86CC = X86::COND_O;
16569 case Intrinsic::x86_sse42_pcmpistris128:
16570 Opcode = X86ISD::PCMPISTRI;
16571 X86CC = X86::COND_S;
16573 case Intrinsic::x86_sse42_pcmpestris128:
16574 Opcode = X86ISD::PCMPESTRI;
16575 X86CC = X86::COND_S;
16577 case Intrinsic::x86_sse42_pcmpistriz128:
16578 Opcode = X86ISD::PCMPISTRI;
16579 X86CC = X86::COND_E;
16581 case Intrinsic::x86_sse42_pcmpestriz128:
16582 Opcode = X86ISD::PCMPESTRI;
16583 X86CC = X86::COND_E;
16586 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16587 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16588 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16589 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16590 DAG.getConstant(X86CC, MVT::i8),
16591 SDValue(PCMP.getNode(), 1));
16592 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16595 case Intrinsic::x86_sse42_pcmpistri128:
16596 case Intrinsic::x86_sse42_pcmpestri128: {
16598 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16599 Opcode = X86ISD::PCMPISTRI;
16601 Opcode = X86ISD::PCMPESTRI;
16603 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16604 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16605 return DAG.getNode(Opcode, dl, VTs, NewOps);
16608 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16609 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16610 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16611 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16612 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16613 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16614 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16615 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16616 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16617 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16618 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16619 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16620 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16621 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16622 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16623 dl, Op.getValueType(),
16627 Op.getOperand(4), Op.getOperand(1), DAG);
16632 case Intrinsic::x86_fma_vfmadd_ps:
16633 case Intrinsic::x86_fma_vfmadd_pd:
16634 case Intrinsic::x86_fma_vfmsub_ps:
16635 case Intrinsic::x86_fma_vfmsub_pd:
16636 case Intrinsic::x86_fma_vfnmadd_ps:
16637 case Intrinsic::x86_fma_vfnmadd_pd:
16638 case Intrinsic::x86_fma_vfnmsub_ps:
16639 case Intrinsic::x86_fma_vfnmsub_pd:
16640 case Intrinsic::x86_fma_vfmaddsub_ps:
16641 case Intrinsic::x86_fma_vfmaddsub_pd:
16642 case Intrinsic::x86_fma_vfmsubadd_ps:
16643 case Intrinsic::x86_fma_vfmsubadd_pd:
16644 case Intrinsic::x86_fma_vfmadd_ps_256:
16645 case Intrinsic::x86_fma_vfmadd_pd_256:
16646 case Intrinsic::x86_fma_vfmsub_ps_256:
16647 case Intrinsic::x86_fma_vfmsub_pd_256:
16648 case Intrinsic::x86_fma_vfnmadd_ps_256:
16649 case Intrinsic::x86_fma_vfnmadd_pd_256:
16650 case Intrinsic::x86_fma_vfnmsub_ps_256:
16651 case Intrinsic::x86_fma_vfnmsub_pd_256:
16652 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16653 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16654 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16655 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16656 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16657 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16661 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16662 SDValue Src, SDValue Mask, SDValue Base,
16663 SDValue Index, SDValue ScaleOp, SDValue Chain,
16664 const X86Subtarget * Subtarget) {
16666 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16667 assert(C && "Invalid scale type");
16668 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16669 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16670 Index.getSimpleValueType().getVectorNumElements());
16672 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16674 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16676 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16677 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16678 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16679 SDValue Segment = DAG.getRegister(0, MVT::i32);
16680 if (Src.getOpcode() == ISD::UNDEF)
16681 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16682 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16683 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16684 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16685 return DAG.getMergeValues(RetOps, dl);
16688 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16689 SDValue Src, SDValue Mask, SDValue Base,
16690 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16692 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16693 assert(C && "Invalid scale type");
16694 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16695 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16696 SDValue Segment = DAG.getRegister(0, MVT::i32);
16697 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16698 Index.getSimpleValueType().getVectorNumElements());
16700 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16702 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16704 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16705 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16706 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16707 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16708 return SDValue(Res, 1);
16711 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16712 SDValue Mask, SDValue Base, SDValue Index,
16713 SDValue ScaleOp, SDValue Chain) {
16715 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16716 assert(C && "Invalid scale type");
16717 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16718 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16719 SDValue Segment = DAG.getRegister(0, MVT::i32);
16721 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16723 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16725 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16727 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16728 //SDVTList VTs = DAG.getVTList(MVT::Other);
16729 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16730 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16731 return SDValue(Res, 0);
16734 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16735 // read performance monitor counters (x86_rdpmc).
16736 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16737 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16738 SmallVectorImpl<SDValue> &Results) {
16739 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16740 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16743 // The ECX register is used to select the index of the performance counter
16745 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16747 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16749 // Reads the content of a 64-bit performance counter and returns it in the
16750 // registers EDX:EAX.
16751 if (Subtarget->is64Bit()) {
16752 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16753 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16756 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16757 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16760 Chain = HI.getValue(1);
16762 if (Subtarget->is64Bit()) {
16763 // The EAX register is loaded with the low-order 32 bits. The EDX register
16764 // is loaded with the supported high-order bits of the counter.
16765 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16766 DAG.getConstant(32, MVT::i8));
16767 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16768 Results.push_back(Chain);
16772 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16773 SDValue Ops[] = { LO, HI };
16774 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16775 Results.push_back(Pair);
16776 Results.push_back(Chain);
16779 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16780 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16781 // also used to custom lower READCYCLECOUNTER nodes.
16782 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16783 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16784 SmallVectorImpl<SDValue> &Results) {
16785 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16786 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16789 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16790 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16791 // and the EAX register is loaded with the low-order 32 bits.
16792 if (Subtarget->is64Bit()) {
16793 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16794 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16797 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16798 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16801 SDValue Chain = HI.getValue(1);
16803 if (Opcode == X86ISD::RDTSCP_DAG) {
16804 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16806 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16807 // the ECX register. Add 'ecx' explicitly to the chain.
16808 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16810 // Explicitly store the content of ECX at the location passed in input
16811 // to the 'rdtscp' intrinsic.
16812 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16813 MachinePointerInfo(), false, false, 0);
16816 if (Subtarget->is64Bit()) {
16817 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16818 // the EAX register is loaded with the low-order 32 bits.
16819 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16820 DAG.getConstant(32, MVT::i8));
16821 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16822 Results.push_back(Chain);
16826 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16827 SDValue Ops[] = { LO, HI };
16828 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16829 Results.push_back(Pair);
16830 Results.push_back(Chain);
16833 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16834 SelectionDAG &DAG) {
16835 SmallVector<SDValue, 2> Results;
16837 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16839 return DAG.getMergeValues(Results, DL);
16843 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16844 SelectionDAG &DAG) {
16845 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16847 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16852 switch(IntrData->Type) {
16854 llvm_unreachable("Unknown Intrinsic Type");
16858 // Emit the node with the right value type.
16859 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16860 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16862 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16863 // Otherwise return the value from Rand, which is always 0, casted to i32.
16864 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16865 DAG.getConstant(1, Op->getValueType(1)),
16866 DAG.getConstant(X86::COND_B, MVT::i32),
16867 SDValue(Result.getNode(), 1) };
16868 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16869 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16872 // Return { result, isValid, chain }.
16873 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16874 SDValue(Result.getNode(), 2));
16877 //gather(v1, mask, index, base, scale);
16878 SDValue Chain = Op.getOperand(0);
16879 SDValue Src = Op.getOperand(2);
16880 SDValue Base = Op.getOperand(3);
16881 SDValue Index = Op.getOperand(4);
16882 SDValue Mask = Op.getOperand(5);
16883 SDValue Scale = Op.getOperand(6);
16884 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16888 //scatter(base, mask, index, v1, scale);
16889 SDValue Chain = Op.getOperand(0);
16890 SDValue Base = Op.getOperand(2);
16891 SDValue Mask = Op.getOperand(3);
16892 SDValue Index = Op.getOperand(4);
16893 SDValue Src = Op.getOperand(5);
16894 SDValue Scale = Op.getOperand(6);
16895 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16898 SDValue Hint = Op.getOperand(6);
16900 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16901 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16902 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16903 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16904 SDValue Chain = Op.getOperand(0);
16905 SDValue Mask = Op.getOperand(2);
16906 SDValue Index = Op.getOperand(3);
16907 SDValue Base = Op.getOperand(4);
16908 SDValue Scale = Op.getOperand(5);
16909 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16911 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16913 SmallVector<SDValue, 2> Results;
16914 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16915 return DAG.getMergeValues(Results, dl);
16917 // Read Performance Monitoring Counters.
16919 SmallVector<SDValue, 2> Results;
16920 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16921 return DAG.getMergeValues(Results, dl);
16923 // XTEST intrinsics.
16925 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16926 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16927 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16928 DAG.getConstant(X86::COND_NE, MVT::i8),
16930 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16931 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16932 Ret, SDValue(InTrans.getNode(), 1));
16936 SmallVector<SDValue, 2> Results;
16937 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16938 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16939 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16940 DAG.getConstant(-1, MVT::i8));
16941 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16942 Op.getOperand(4), GenCF.getValue(1));
16943 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16944 Op.getOperand(5), MachinePointerInfo(),
16946 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16947 DAG.getConstant(X86::COND_B, MVT::i8),
16949 Results.push_back(SetCC);
16950 Results.push_back(Store);
16951 return DAG.getMergeValues(Results, dl);
16956 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16957 SelectionDAG &DAG) const {
16958 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16959 MFI->setReturnAddressIsTaken(true);
16961 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16964 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16966 EVT PtrVT = getPointerTy();
16969 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16970 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16971 DAG.getSubtarget().getRegisterInfo());
16972 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16973 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16974 DAG.getNode(ISD::ADD, dl, PtrVT,
16975 FrameAddr, Offset),
16976 MachinePointerInfo(), false, false, false, 0);
16979 // Just load the return address.
16980 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16981 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16982 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16985 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16986 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16987 MFI->setFrameAddressIsTaken(true);
16989 EVT VT = Op.getValueType();
16990 SDLoc dl(Op); // FIXME probably not meaningful
16991 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16992 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16993 DAG.getSubtarget().getRegisterInfo());
16994 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16995 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16996 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16997 "Invalid Frame Register!");
16998 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17000 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17001 MachinePointerInfo(),
17002 false, false, false, 0);
17006 // FIXME? Maybe this could be a TableGen attribute on some registers and
17007 // this table could be generated automatically from RegInfo.
17008 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17010 unsigned Reg = StringSwitch<unsigned>(RegName)
17011 .Case("esp", X86::ESP)
17012 .Case("rsp", X86::RSP)
17016 report_fatal_error("Invalid register name global variable");
17019 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17020 SelectionDAG &DAG) const {
17021 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17022 DAG.getSubtarget().getRegisterInfo());
17023 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17026 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17027 SDValue Chain = Op.getOperand(0);
17028 SDValue Offset = Op.getOperand(1);
17029 SDValue Handler = Op.getOperand(2);
17032 EVT PtrVT = getPointerTy();
17033 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17034 DAG.getSubtarget().getRegisterInfo());
17035 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17036 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17037 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17038 "Invalid Frame Register!");
17039 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17040 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17042 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17043 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17044 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17045 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17047 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17049 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17050 DAG.getRegister(StoreAddrReg, PtrVT));
17053 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17054 SelectionDAG &DAG) const {
17056 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17057 DAG.getVTList(MVT::i32, MVT::Other),
17058 Op.getOperand(0), Op.getOperand(1));
17061 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17062 SelectionDAG &DAG) const {
17064 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17065 Op.getOperand(0), Op.getOperand(1));
17068 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17069 return Op.getOperand(0);
17072 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17073 SelectionDAG &DAG) const {
17074 SDValue Root = Op.getOperand(0);
17075 SDValue Trmp = Op.getOperand(1); // trampoline
17076 SDValue FPtr = Op.getOperand(2); // nested function
17077 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17080 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17081 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17083 if (Subtarget->is64Bit()) {
17084 SDValue OutChains[6];
17086 // Large code-model.
17087 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17088 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17090 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17091 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17093 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17095 // Load the pointer to the nested function into R11.
17096 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17097 SDValue Addr = Trmp;
17098 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17099 Addr, MachinePointerInfo(TrmpAddr),
17102 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17103 DAG.getConstant(2, MVT::i64));
17104 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17105 MachinePointerInfo(TrmpAddr, 2),
17108 // Load the 'nest' parameter value into R10.
17109 // R10 is specified in X86CallingConv.td
17110 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17111 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17112 DAG.getConstant(10, MVT::i64));
17113 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17114 Addr, MachinePointerInfo(TrmpAddr, 10),
17117 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17118 DAG.getConstant(12, MVT::i64));
17119 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17120 MachinePointerInfo(TrmpAddr, 12),
17123 // Jump to the nested function.
17124 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17125 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17126 DAG.getConstant(20, MVT::i64));
17127 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17128 Addr, MachinePointerInfo(TrmpAddr, 20),
17131 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17132 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17133 DAG.getConstant(22, MVT::i64));
17134 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17135 MachinePointerInfo(TrmpAddr, 22),
17138 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17140 const Function *Func =
17141 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17142 CallingConv::ID CC = Func->getCallingConv();
17147 llvm_unreachable("Unsupported calling convention");
17148 case CallingConv::C:
17149 case CallingConv::X86_StdCall: {
17150 // Pass 'nest' parameter in ECX.
17151 // Must be kept in sync with X86CallingConv.td
17152 NestReg = X86::ECX;
17154 // Check that ECX wasn't needed by an 'inreg' parameter.
17155 FunctionType *FTy = Func->getFunctionType();
17156 const AttributeSet &Attrs = Func->getAttributes();
17158 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17159 unsigned InRegCount = 0;
17162 for (FunctionType::param_iterator I = FTy->param_begin(),
17163 E = FTy->param_end(); I != E; ++I, ++Idx)
17164 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17165 // FIXME: should only count parameters that are lowered to integers.
17166 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17168 if (InRegCount > 2) {
17169 report_fatal_error("Nest register in use - reduce number of inreg"
17175 case CallingConv::X86_FastCall:
17176 case CallingConv::X86_ThisCall:
17177 case CallingConv::Fast:
17178 // Pass 'nest' parameter in EAX.
17179 // Must be kept in sync with X86CallingConv.td
17180 NestReg = X86::EAX;
17184 SDValue OutChains[4];
17185 SDValue Addr, Disp;
17187 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17188 DAG.getConstant(10, MVT::i32));
17189 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17191 // This is storing the opcode for MOV32ri.
17192 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17193 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17194 OutChains[0] = DAG.getStore(Root, dl,
17195 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17196 Trmp, MachinePointerInfo(TrmpAddr),
17199 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17200 DAG.getConstant(1, MVT::i32));
17201 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17202 MachinePointerInfo(TrmpAddr, 1),
17205 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17206 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17207 DAG.getConstant(5, MVT::i32));
17208 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17209 MachinePointerInfo(TrmpAddr, 5),
17212 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17213 DAG.getConstant(6, MVT::i32));
17214 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17215 MachinePointerInfo(TrmpAddr, 6),
17218 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17222 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17223 SelectionDAG &DAG) const {
17225 The rounding mode is in bits 11:10 of FPSR, and has the following
17227 00 Round to nearest
17232 FLT_ROUNDS, on the other hand, expects the following:
17239 To perform the conversion, we do:
17240 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17243 MachineFunction &MF = DAG.getMachineFunction();
17244 const TargetMachine &TM = MF.getTarget();
17245 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17246 unsigned StackAlignment = TFI.getStackAlignment();
17247 MVT VT = Op.getSimpleValueType();
17250 // Save FP Control Word to stack slot
17251 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17252 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17254 MachineMemOperand *MMO =
17255 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17256 MachineMemOperand::MOStore, 2, 2);
17258 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17259 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17260 DAG.getVTList(MVT::Other),
17261 Ops, MVT::i16, MMO);
17263 // Load FP Control Word from stack slot
17264 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17265 MachinePointerInfo(), false, false, false, 0);
17267 // Transform as necessary
17269 DAG.getNode(ISD::SRL, DL, MVT::i16,
17270 DAG.getNode(ISD::AND, DL, MVT::i16,
17271 CWD, DAG.getConstant(0x800, MVT::i16)),
17272 DAG.getConstant(11, MVT::i8));
17274 DAG.getNode(ISD::SRL, DL, MVT::i16,
17275 DAG.getNode(ISD::AND, DL, MVT::i16,
17276 CWD, DAG.getConstant(0x400, MVT::i16)),
17277 DAG.getConstant(9, MVT::i8));
17280 DAG.getNode(ISD::AND, DL, MVT::i16,
17281 DAG.getNode(ISD::ADD, DL, MVT::i16,
17282 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17283 DAG.getConstant(1, MVT::i16)),
17284 DAG.getConstant(3, MVT::i16));
17286 return DAG.getNode((VT.getSizeInBits() < 16 ?
17287 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17290 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17291 MVT VT = Op.getSimpleValueType();
17293 unsigned NumBits = VT.getSizeInBits();
17296 Op = Op.getOperand(0);
17297 if (VT == MVT::i8) {
17298 // Zero extend to i32 since there is not an i8 bsr.
17300 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17303 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17304 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17305 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17307 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17310 DAG.getConstant(NumBits+NumBits-1, OpVT),
17311 DAG.getConstant(X86::COND_E, MVT::i8),
17314 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17316 // Finally xor with NumBits-1.
17317 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17320 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17324 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17325 MVT VT = Op.getSimpleValueType();
17327 unsigned NumBits = VT.getSizeInBits();
17330 Op = Op.getOperand(0);
17331 if (VT == MVT::i8) {
17332 // Zero extend to i32 since there is not an i8 bsr.
17334 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17337 // Issue a bsr (scan bits in reverse).
17338 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17339 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17341 // And xor with NumBits-1.
17342 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17345 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17349 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17350 MVT VT = Op.getSimpleValueType();
17351 unsigned NumBits = VT.getSizeInBits();
17353 Op = Op.getOperand(0);
17355 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17356 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17357 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17359 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17362 DAG.getConstant(NumBits, VT),
17363 DAG.getConstant(X86::COND_E, MVT::i8),
17366 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17369 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17370 // ones, and then concatenate the result back.
17371 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17372 MVT VT = Op.getSimpleValueType();
17374 assert(VT.is256BitVector() && VT.isInteger() &&
17375 "Unsupported value type for operation");
17377 unsigned NumElems = VT.getVectorNumElements();
17380 // Extract the LHS vectors
17381 SDValue LHS = Op.getOperand(0);
17382 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17383 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17385 // Extract the RHS vectors
17386 SDValue RHS = Op.getOperand(1);
17387 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17388 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17390 MVT EltVT = VT.getVectorElementType();
17391 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17393 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17394 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17395 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17398 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17399 assert(Op.getSimpleValueType().is256BitVector() &&
17400 Op.getSimpleValueType().isInteger() &&
17401 "Only handle AVX 256-bit vector integer operation");
17402 return Lower256IntArith(Op, DAG);
17405 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17406 assert(Op.getSimpleValueType().is256BitVector() &&
17407 Op.getSimpleValueType().isInteger() &&
17408 "Only handle AVX 256-bit vector integer operation");
17409 return Lower256IntArith(Op, DAG);
17412 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17413 SelectionDAG &DAG) {
17415 MVT VT = Op.getSimpleValueType();
17417 // Decompose 256-bit ops into smaller 128-bit ops.
17418 if (VT.is256BitVector() && !Subtarget->hasInt256())
17419 return Lower256IntArith(Op, DAG);
17421 SDValue A = Op.getOperand(0);
17422 SDValue B = Op.getOperand(1);
17424 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17425 if (VT == MVT::v4i32) {
17426 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17427 "Should not custom lower when pmuldq is available!");
17429 // Extract the odd parts.
17430 static const int UnpackMask[] = { 1, -1, 3, -1 };
17431 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17432 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17434 // Multiply the even parts.
17435 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17436 // Now multiply odd parts.
17437 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17439 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17440 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17442 // Merge the two vectors back together with a shuffle. This expands into 2
17444 static const int ShufMask[] = { 0, 4, 2, 6 };
17445 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17448 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17449 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17451 // Ahi = psrlqi(a, 32);
17452 // Bhi = psrlqi(b, 32);
17454 // AloBlo = pmuludq(a, b);
17455 // AloBhi = pmuludq(a, Bhi);
17456 // AhiBlo = pmuludq(Ahi, b);
17458 // AloBhi = psllqi(AloBhi, 32);
17459 // AhiBlo = psllqi(AhiBlo, 32);
17460 // return AloBlo + AloBhi + AhiBlo;
17462 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17463 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17465 // Bit cast to 32-bit vectors for MULUDQ
17466 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17467 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17468 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17469 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17470 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17471 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17473 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17474 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17475 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17477 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17478 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17480 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17481 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17484 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17485 assert(Subtarget->isTargetWin64() && "Unexpected target");
17486 EVT VT = Op.getValueType();
17487 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17488 "Unexpected return type for lowering");
17492 switch (Op->getOpcode()) {
17493 default: llvm_unreachable("Unexpected request for libcall!");
17494 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17495 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17496 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17497 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17498 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17499 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17503 SDValue InChain = DAG.getEntryNode();
17505 TargetLowering::ArgListTy Args;
17506 TargetLowering::ArgListEntry Entry;
17507 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17508 EVT ArgVT = Op->getOperand(i).getValueType();
17509 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17510 "Unexpected argument type for lowering");
17511 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17512 Entry.Node = StackPtr;
17513 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17515 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17516 Entry.Ty = PointerType::get(ArgTy,0);
17517 Entry.isSExt = false;
17518 Entry.isZExt = false;
17519 Args.push_back(Entry);
17522 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17525 TargetLowering::CallLoweringInfo CLI(DAG);
17526 CLI.setDebugLoc(dl).setChain(InChain)
17527 .setCallee(getLibcallCallingConv(LC),
17528 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17529 Callee, std::move(Args), 0)
17530 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17532 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17533 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17536 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17537 SelectionDAG &DAG) {
17538 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17539 EVT VT = Op0.getValueType();
17542 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17543 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17545 // PMULxD operations multiply each even value (starting at 0) of LHS with
17546 // the related value of RHS and produce a widen result.
17547 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17548 // => <2 x i64> <ae|cg>
17550 // In other word, to have all the results, we need to perform two PMULxD:
17551 // 1. one with the even values.
17552 // 2. one with the odd values.
17553 // To achieve #2, with need to place the odd values at an even position.
17555 // Place the odd value at an even position (basically, shift all values 1
17556 // step to the left):
17557 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17558 // <a|b|c|d> => <b|undef|d|undef>
17559 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17560 // <e|f|g|h> => <f|undef|h|undef>
17561 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17563 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17565 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17566 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17568 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17569 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17570 // => <2 x i64> <ae|cg>
17571 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17572 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17573 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17574 // => <2 x i64> <bf|dh>
17575 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17576 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17578 // Shuffle it back into the right order.
17579 SDValue Highs, Lows;
17580 if (VT == MVT::v8i32) {
17581 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17582 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17583 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17584 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17586 const int HighMask[] = {1, 5, 3, 7};
17587 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17588 const int LowMask[] = {0, 4, 2, 6};
17589 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17592 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17593 // unsigned multiply.
17594 if (IsSigned && !Subtarget->hasSSE41()) {
17596 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17597 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17598 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17599 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17600 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17602 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17603 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17606 // The first result of MUL_LOHI is actually the low value, followed by the
17608 SDValue Ops[] = {Lows, Highs};
17609 return DAG.getMergeValues(Ops, dl);
17612 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17613 const X86Subtarget *Subtarget) {
17614 MVT VT = Op.getSimpleValueType();
17616 SDValue R = Op.getOperand(0);
17617 SDValue Amt = Op.getOperand(1);
17619 // Optimize shl/srl/sra with constant shift amount.
17620 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17621 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17622 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17624 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17625 (Subtarget->hasInt256() &&
17626 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17627 (Subtarget->hasAVX512() &&
17628 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17629 if (Op.getOpcode() == ISD::SHL)
17630 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17632 if (Op.getOpcode() == ISD::SRL)
17633 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17635 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17636 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17640 if (VT == MVT::v16i8) {
17641 if (Op.getOpcode() == ISD::SHL) {
17642 // Make a large shift.
17643 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17644 MVT::v8i16, R, ShiftAmt,
17646 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17647 // Zero out the rightmost bits.
17648 SmallVector<SDValue, 16> V(16,
17649 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17651 return DAG.getNode(ISD::AND, dl, VT, SHL,
17652 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17654 if (Op.getOpcode() == ISD::SRL) {
17655 // Make a large shift.
17656 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17657 MVT::v8i16, R, ShiftAmt,
17659 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17660 // Zero out the leftmost bits.
17661 SmallVector<SDValue, 16> V(16,
17662 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17664 return DAG.getNode(ISD::AND, dl, VT, SRL,
17665 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17667 if (Op.getOpcode() == ISD::SRA) {
17668 if (ShiftAmt == 7) {
17669 // R s>> 7 === R s< 0
17670 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17671 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17674 // R s>> a === ((R u>> a) ^ m) - m
17675 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17676 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17678 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17679 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17680 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17683 llvm_unreachable("Unknown shift opcode.");
17686 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17687 if (Op.getOpcode() == ISD::SHL) {
17688 // Make a large shift.
17689 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17690 MVT::v16i16, R, ShiftAmt,
17692 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17693 // Zero out the rightmost bits.
17694 SmallVector<SDValue, 32> V(32,
17695 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17697 return DAG.getNode(ISD::AND, dl, VT, SHL,
17698 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17700 if (Op.getOpcode() == ISD::SRL) {
17701 // Make a large shift.
17702 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17703 MVT::v16i16, R, ShiftAmt,
17705 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17706 // Zero out the leftmost bits.
17707 SmallVector<SDValue, 32> V(32,
17708 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17710 return DAG.getNode(ISD::AND, dl, VT, SRL,
17711 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17713 if (Op.getOpcode() == ISD::SRA) {
17714 if (ShiftAmt == 7) {
17715 // R s>> 7 === R s< 0
17716 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17717 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17720 // R s>> a === ((R u>> a) ^ m) - m
17721 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17722 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17724 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17725 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17726 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17729 llvm_unreachable("Unknown shift opcode.");
17734 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17735 if (!Subtarget->is64Bit() &&
17736 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17737 Amt.getOpcode() == ISD::BITCAST &&
17738 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17739 Amt = Amt.getOperand(0);
17740 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17741 VT.getVectorNumElements();
17742 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17743 uint64_t ShiftAmt = 0;
17744 for (unsigned i = 0; i != Ratio; ++i) {
17745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17749 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17751 // Check remaining shift amounts.
17752 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17753 uint64_t ShAmt = 0;
17754 for (unsigned j = 0; j != Ratio; ++j) {
17755 ConstantSDNode *C =
17756 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17760 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17762 if (ShAmt != ShiftAmt)
17765 switch (Op.getOpcode()) {
17767 llvm_unreachable("Unknown shift opcode!");
17769 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17772 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17775 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17783 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17784 const X86Subtarget* Subtarget) {
17785 MVT VT = Op.getSimpleValueType();
17787 SDValue R = Op.getOperand(0);
17788 SDValue Amt = Op.getOperand(1);
17790 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17791 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17792 (Subtarget->hasInt256() &&
17793 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17794 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17795 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17797 EVT EltVT = VT.getVectorElementType();
17799 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17800 unsigned NumElts = VT.getVectorNumElements();
17802 for (i = 0; i != NumElts; ++i) {
17803 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17807 for (j = i; j != NumElts; ++j) {
17808 SDValue Arg = Amt.getOperand(j);
17809 if (Arg.getOpcode() == ISD::UNDEF) continue;
17810 if (Arg != Amt.getOperand(i))
17813 if (i != NumElts && j == NumElts)
17814 BaseShAmt = Amt.getOperand(i);
17816 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17817 Amt = Amt.getOperand(0);
17818 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17819 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17820 SDValue InVec = Amt.getOperand(0);
17821 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17822 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17824 for (; i != NumElts; ++i) {
17825 SDValue Arg = InVec.getOperand(i);
17826 if (Arg.getOpcode() == ISD::UNDEF) continue;
17830 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17831 if (ConstantSDNode *C =
17832 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17833 unsigned SplatIdx =
17834 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17835 if (C->getZExtValue() == SplatIdx)
17836 BaseShAmt = InVec.getOperand(1);
17839 if (!BaseShAmt.getNode())
17840 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17841 DAG.getIntPtrConstant(0));
17845 if (BaseShAmt.getNode()) {
17846 if (EltVT.bitsGT(MVT::i32))
17847 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17848 else if (EltVT.bitsLT(MVT::i32))
17849 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17851 switch (Op.getOpcode()) {
17853 llvm_unreachable("Unknown shift opcode!");
17855 switch (VT.SimpleTy) {
17856 default: return SDValue();
17865 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17868 switch (VT.SimpleTy) {
17869 default: return SDValue();
17876 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17879 switch (VT.SimpleTy) {
17880 default: return SDValue();
17889 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17895 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17896 if (!Subtarget->is64Bit() &&
17897 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17898 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17899 Amt.getOpcode() == ISD::BITCAST &&
17900 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17901 Amt = Amt.getOperand(0);
17902 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17903 VT.getVectorNumElements();
17904 std::vector<SDValue> Vals(Ratio);
17905 for (unsigned i = 0; i != Ratio; ++i)
17906 Vals[i] = Amt.getOperand(i);
17907 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17908 for (unsigned j = 0; j != Ratio; ++j)
17909 if (Vals[j] != Amt.getOperand(i + j))
17912 switch (Op.getOpcode()) {
17914 llvm_unreachable("Unknown shift opcode!");
17916 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17918 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17920 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17927 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17928 SelectionDAG &DAG) {
17929 MVT VT = Op.getSimpleValueType();
17931 SDValue R = Op.getOperand(0);
17932 SDValue Amt = Op.getOperand(1);
17935 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17936 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17938 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17942 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17946 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17948 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17949 if (Subtarget->hasInt256()) {
17950 if (Op.getOpcode() == ISD::SRL &&
17951 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17952 VT == MVT::v4i64 || VT == MVT::v8i32))
17954 if (Op.getOpcode() == ISD::SHL &&
17955 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17956 VT == MVT::v4i64 || VT == MVT::v8i32))
17958 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17962 // If possible, lower this packed shift into a vector multiply instead of
17963 // expanding it into a sequence of scalar shifts.
17964 // Do this only if the vector shift count is a constant build_vector.
17965 if (Op.getOpcode() == ISD::SHL &&
17966 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17967 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17968 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17969 SmallVector<SDValue, 8> Elts;
17970 EVT SVT = VT.getScalarType();
17971 unsigned SVTBits = SVT.getSizeInBits();
17972 const APInt &One = APInt(SVTBits, 1);
17973 unsigned NumElems = VT.getVectorNumElements();
17975 for (unsigned i=0; i !=NumElems; ++i) {
17976 SDValue Op = Amt->getOperand(i);
17977 if (Op->getOpcode() == ISD::UNDEF) {
17978 Elts.push_back(Op);
17982 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17983 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17984 uint64_t ShAmt = C.getZExtValue();
17985 if (ShAmt >= SVTBits) {
17986 Elts.push_back(DAG.getUNDEF(SVT));
17989 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17991 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17992 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17995 // Lower SHL with variable shift amount.
17996 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17997 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17999 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18000 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18001 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18002 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18005 // If possible, lower this shift as a sequence of two shifts by
18006 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18008 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18010 // Could be rewritten as:
18011 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18013 // The advantage is that the two shifts from the example would be
18014 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18015 // the vector shift into four scalar shifts plus four pairs of vector
18017 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18018 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18019 unsigned TargetOpcode = X86ISD::MOVSS;
18020 bool CanBeSimplified;
18021 // The splat value for the first packed shift (the 'X' from the example).
18022 SDValue Amt1 = Amt->getOperand(0);
18023 // The splat value for the second packed shift (the 'Y' from the example).
18024 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18025 Amt->getOperand(2);
18027 // See if it is possible to replace this node with a sequence of
18028 // two shifts followed by a MOVSS/MOVSD
18029 if (VT == MVT::v4i32) {
18030 // Check if it is legal to use a MOVSS.
18031 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18032 Amt2 == Amt->getOperand(3);
18033 if (!CanBeSimplified) {
18034 // Otherwise, check if we can still simplify this node using a MOVSD.
18035 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18036 Amt->getOperand(2) == Amt->getOperand(3);
18037 TargetOpcode = X86ISD::MOVSD;
18038 Amt2 = Amt->getOperand(2);
18041 // Do similar checks for the case where the machine value type
18043 CanBeSimplified = Amt1 == Amt->getOperand(1);
18044 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18045 CanBeSimplified = Amt2 == Amt->getOperand(i);
18047 if (!CanBeSimplified) {
18048 TargetOpcode = X86ISD::MOVSD;
18049 CanBeSimplified = true;
18050 Amt2 = Amt->getOperand(4);
18051 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18052 CanBeSimplified = Amt1 == Amt->getOperand(i);
18053 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18054 CanBeSimplified = Amt2 == Amt->getOperand(j);
18058 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18059 isa<ConstantSDNode>(Amt2)) {
18060 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18061 EVT CastVT = MVT::v4i32;
18063 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18064 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18066 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18067 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18068 if (TargetOpcode == X86ISD::MOVSD)
18069 CastVT = MVT::v2i64;
18070 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18071 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18072 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18074 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18078 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18079 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18082 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18083 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18085 // Turn 'a' into a mask suitable for VSELECT
18086 SDValue VSelM = DAG.getConstant(0x80, VT);
18087 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18088 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18090 SDValue CM1 = DAG.getConstant(0x0f, VT);
18091 SDValue CM2 = DAG.getConstant(0x3f, VT);
18093 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18094 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18095 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18096 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18097 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18100 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18101 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18102 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18104 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18105 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18106 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18107 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18108 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18111 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18112 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18113 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18115 // return VSELECT(r, r+r, a);
18116 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18117 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18121 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18122 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18123 // solution better.
18124 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18125 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18127 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18128 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18129 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18130 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18131 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18134 // Decompose 256-bit shifts into smaller 128-bit shifts.
18135 if (VT.is256BitVector()) {
18136 unsigned NumElems = VT.getVectorNumElements();
18137 MVT EltVT = VT.getVectorElementType();
18138 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18140 // Extract the two vectors
18141 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18142 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18144 // Recreate the shift amount vectors
18145 SDValue Amt1, Amt2;
18146 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18147 // Constant shift amount
18148 SmallVector<SDValue, 4> Amt1Csts;
18149 SmallVector<SDValue, 4> Amt2Csts;
18150 for (unsigned i = 0; i != NumElems/2; ++i)
18151 Amt1Csts.push_back(Amt->getOperand(i));
18152 for (unsigned i = NumElems/2; i != NumElems; ++i)
18153 Amt2Csts.push_back(Amt->getOperand(i));
18155 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18156 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18158 // Variable shift amount
18159 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18160 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18163 // Issue new vector shifts for the smaller types
18164 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18165 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18167 // Concatenate the result back
18168 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18174 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18175 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18176 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18177 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18178 // has only one use.
18179 SDNode *N = Op.getNode();
18180 SDValue LHS = N->getOperand(0);
18181 SDValue RHS = N->getOperand(1);
18182 unsigned BaseOp = 0;
18185 switch (Op.getOpcode()) {
18186 default: llvm_unreachable("Unknown ovf instruction!");
18188 // A subtract of one will be selected as a INC. Note that INC doesn't
18189 // set CF, so we can't do this for UADDO.
18190 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18192 BaseOp = X86ISD::INC;
18193 Cond = X86::COND_O;
18196 BaseOp = X86ISD::ADD;
18197 Cond = X86::COND_O;
18200 BaseOp = X86ISD::ADD;
18201 Cond = X86::COND_B;
18204 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18205 // set CF, so we can't do this for USUBO.
18206 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18208 BaseOp = X86ISD::DEC;
18209 Cond = X86::COND_O;
18212 BaseOp = X86ISD::SUB;
18213 Cond = X86::COND_O;
18216 BaseOp = X86ISD::SUB;
18217 Cond = X86::COND_B;
18220 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18221 Cond = X86::COND_O;
18223 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18224 if (N->getValueType(0) == MVT::i8) {
18225 BaseOp = X86ISD::UMUL8;
18226 Cond = X86::COND_O;
18229 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18231 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18234 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18235 DAG.getConstant(X86::COND_O, MVT::i32),
18236 SDValue(Sum.getNode(), 2));
18238 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18242 // Also sets EFLAGS.
18243 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18244 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18247 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18248 DAG.getConstant(Cond, MVT::i32),
18249 SDValue(Sum.getNode(), 1));
18251 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18254 // Sign extension of the low part of vector elements. This may be used either
18255 // when sign extend instructions are not available or if the vector element
18256 // sizes already match the sign-extended size. If the vector elements are in
18257 // their pre-extended size and sign extend instructions are available, that will
18258 // be handled by LowerSIGN_EXTEND.
18259 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18260 SelectionDAG &DAG) const {
18262 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18263 MVT VT = Op.getSimpleValueType();
18265 if (!Subtarget->hasSSE2() || !VT.isVector())
18268 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18269 ExtraVT.getScalarType().getSizeInBits();
18271 switch (VT.SimpleTy) {
18272 default: return SDValue();
18275 if (!Subtarget->hasFp256())
18277 if (!Subtarget->hasInt256()) {
18278 // needs to be split
18279 unsigned NumElems = VT.getVectorNumElements();
18281 // Extract the LHS vectors
18282 SDValue LHS = Op.getOperand(0);
18283 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18284 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18286 MVT EltVT = VT.getVectorElementType();
18287 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18289 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18290 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18291 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18293 SDValue Extra = DAG.getValueType(ExtraVT);
18295 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18296 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18298 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18303 SDValue Op0 = Op.getOperand(0);
18305 // This is a sign extension of some low part of vector elements without
18306 // changing the size of the vector elements themselves:
18307 // Shift-Left + Shift-Right-Algebraic.
18308 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18310 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18316 /// Returns true if the operand type is exactly twice the native width, and
18317 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18318 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18319 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18320 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18321 const X86Subtarget &Subtarget =
18322 getTargetMachine().getSubtarget<X86Subtarget>();
18323 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18326 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18327 else if (OpWidth == 128)
18328 return Subtarget.hasCmpxchg16b();
18333 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18334 return needsCmpXchgNb(SI->getValueOperand()->getType());
18337 // Note: this turns large loads into lock cmpxchg8b/16b.
18338 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18339 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18340 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18341 return needsCmpXchgNb(PTy->getElementType());
18344 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18345 const X86Subtarget &Subtarget =
18346 getTargetMachine().getSubtarget<X86Subtarget>();
18347 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18348 const Type *MemType = AI->getType();
18350 // If the operand is too big, we must see if cmpxchg8/16b is available
18351 // and default to library calls otherwise.
18352 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18353 return needsCmpXchgNb(MemType);
18355 AtomicRMWInst::BinOp Op = AI->getOperation();
18358 llvm_unreachable("Unknown atomic operation");
18359 case AtomicRMWInst::Xchg:
18360 case AtomicRMWInst::Add:
18361 case AtomicRMWInst::Sub:
18362 // It's better to use xadd, xsub or xchg for these in all cases.
18364 case AtomicRMWInst::Or:
18365 case AtomicRMWInst::And:
18366 case AtomicRMWInst::Xor:
18367 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18368 // prefix to a normal instruction for these operations.
18369 return !AI->use_empty();
18370 case AtomicRMWInst::Nand:
18371 case AtomicRMWInst::Max:
18372 case AtomicRMWInst::Min:
18373 case AtomicRMWInst::UMax:
18374 case AtomicRMWInst::UMin:
18375 // These always require a non-trivial set of data operations on x86. We must
18376 // use a cmpxchg loop.
18381 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18382 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18383 // no-sse2). There isn't any reason to disable it if the target processor
18385 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18389 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18390 const X86Subtarget &Subtarget =
18391 getTargetMachine().getSubtarget<X86Subtarget>();
18392 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18393 const Type *MemType = AI->getType();
18394 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18395 // there is no benefit in turning such RMWs into loads, and it is actually
18396 // harmful as it introduces a mfence.
18397 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18400 auto Builder = IRBuilder<>(AI);
18401 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18402 auto SynchScope = AI->getSynchScope();
18403 // We must restrict the ordering to avoid generating loads with Release or
18404 // ReleaseAcquire orderings.
18405 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18406 auto Ptr = AI->getPointerOperand();
18408 // Before the load we need a fence. Here is an example lifted from
18409 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18412 // x.store(1, relaxed);
18413 // r1 = y.fetch_add(0, release);
18415 // y.fetch_add(42, acquire);
18416 // r2 = x.load(relaxed);
18417 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18418 // lowered to just a load without a fence. A mfence flushes the store buffer,
18419 // making the optimization clearly correct.
18420 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18421 // otherwise, we might be able to be more agressive on relaxed idempotent
18422 // rmw. In practice, they do not look useful, so we don't try to be
18423 // especially clever.
18424 if (SynchScope == SingleThread) {
18425 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18426 // the IR level, so we must wrap it in an intrinsic.
18428 } else if (hasMFENCE(Subtarget)) {
18429 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18430 Intrinsic::x86_sse2_mfence);
18431 Builder.CreateCall(MFence);
18433 // FIXME: it might make sense to use a locked operation here but on a
18434 // different cache-line to prevent cache-line bouncing. In practice it
18435 // is probably a small win, and x86 processors without mfence are rare
18436 // enough that we do not bother.
18440 // Finally we can emit the atomic load.
18441 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18442 AI->getType()->getPrimitiveSizeInBits());
18443 Loaded->setAtomic(Order, SynchScope);
18444 AI->replaceAllUsesWith(Loaded);
18445 AI->eraseFromParent();
18449 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18450 SelectionDAG &DAG) {
18452 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18453 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18454 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18455 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18457 // The only fence that needs an instruction is a sequentially-consistent
18458 // cross-thread fence.
18459 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18460 if (hasMFENCE(*Subtarget))
18461 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18463 SDValue Chain = Op.getOperand(0);
18464 SDValue Zero = DAG.getConstant(0, MVT::i32);
18466 DAG.getRegister(X86::ESP, MVT::i32), // Base
18467 DAG.getTargetConstant(1, MVT::i8), // Scale
18468 DAG.getRegister(0, MVT::i32), // Index
18469 DAG.getTargetConstant(0, MVT::i32), // Disp
18470 DAG.getRegister(0, MVT::i32), // Segment.
18474 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18475 return SDValue(Res, 0);
18478 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18479 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18482 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18483 SelectionDAG &DAG) {
18484 MVT T = Op.getSimpleValueType();
18488 switch(T.SimpleTy) {
18489 default: llvm_unreachable("Invalid value type!");
18490 case MVT::i8: Reg = X86::AL; size = 1; break;
18491 case MVT::i16: Reg = X86::AX; size = 2; break;
18492 case MVT::i32: Reg = X86::EAX; size = 4; break;
18494 assert(Subtarget->is64Bit() && "Node not type legal!");
18495 Reg = X86::RAX; size = 8;
18498 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18499 Op.getOperand(2), SDValue());
18500 SDValue Ops[] = { cpIn.getValue(0),
18503 DAG.getTargetConstant(size, MVT::i8),
18504 cpIn.getValue(1) };
18505 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18506 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18507 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18511 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18512 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18513 MVT::i32, cpOut.getValue(2));
18514 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18515 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18517 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18518 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18519 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18523 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18524 SelectionDAG &DAG) {
18525 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18526 MVT DstVT = Op.getSimpleValueType();
18528 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18529 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18530 if (DstVT != MVT::f64)
18531 // This conversion needs to be expanded.
18534 SDValue InVec = Op->getOperand(0);
18536 unsigned NumElts = SrcVT.getVectorNumElements();
18537 EVT SVT = SrcVT.getVectorElementType();
18539 // Widen the vector in input in the case of MVT::v2i32.
18540 // Example: from MVT::v2i32 to MVT::v4i32.
18541 SmallVector<SDValue, 16> Elts;
18542 for (unsigned i = 0, e = NumElts; i != e; ++i)
18543 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18544 DAG.getIntPtrConstant(i)));
18546 // Explicitly mark the extra elements as Undef.
18547 SDValue Undef = DAG.getUNDEF(SVT);
18548 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18549 Elts.push_back(Undef);
18551 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18552 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18553 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18554 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18555 DAG.getIntPtrConstant(0));
18558 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18559 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18560 assert((DstVT == MVT::i64 ||
18561 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18562 "Unexpected custom BITCAST");
18563 // i64 <=> MMX conversions are Legal.
18564 if (SrcVT==MVT::i64 && DstVT.isVector())
18566 if (DstVT==MVT::i64 && SrcVT.isVector())
18568 // MMX <=> MMX conversions are Legal.
18569 if (SrcVT.isVector() && DstVT.isVector())
18571 // All other conversions need to be expanded.
18575 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18576 SDNode *Node = Op.getNode();
18578 EVT T = Node->getValueType(0);
18579 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18580 DAG.getConstant(0, T), Node->getOperand(2));
18581 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18582 cast<AtomicSDNode>(Node)->getMemoryVT(),
18583 Node->getOperand(0),
18584 Node->getOperand(1), negOp,
18585 cast<AtomicSDNode>(Node)->getMemOperand(),
18586 cast<AtomicSDNode>(Node)->getOrdering(),
18587 cast<AtomicSDNode>(Node)->getSynchScope());
18590 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18591 SDNode *Node = Op.getNode();
18593 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18595 // Convert seq_cst store -> xchg
18596 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18597 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18598 // (The only way to get a 16-byte store is cmpxchg16b)
18599 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18600 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18601 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18602 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18603 cast<AtomicSDNode>(Node)->getMemoryVT(),
18604 Node->getOperand(0),
18605 Node->getOperand(1), Node->getOperand(2),
18606 cast<AtomicSDNode>(Node)->getMemOperand(),
18607 cast<AtomicSDNode>(Node)->getOrdering(),
18608 cast<AtomicSDNode>(Node)->getSynchScope());
18609 return Swap.getValue(1);
18611 // Other atomic stores have a simple pattern.
18615 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18616 EVT VT = Op.getNode()->getSimpleValueType(0);
18618 // Let legalize expand this if it isn't a legal type yet.
18619 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18622 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18625 bool ExtraOp = false;
18626 switch (Op.getOpcode()) {
18627 default: llvm_unreachable("Invalid code");
18628 case ISD::ADDC: Opc = X86ISD::ADD; break;
18629 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18630 case ISD::SUBC: Opc = X86ISD::SUB; break;
18631 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18635 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18637 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18638 Op.getOperand(1), Op.getOperand(2));
18641 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18642 SelectionDAG &DAG) {
18643 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18645 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18646 // which returns the values as { float, float } (in XMM0) or
18647 // { double, double } (which is returned in XMM0, XMM1).
18649 SDValue Arg = Op.getOperand(0);
18650 EVT ArgVT = Arg.getValueType();
18651 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18653 TargetLowering::ArgListTy Args;
18654 TargetLowering::ArgListEntry Entry;
18658 Entry.isSExt = false;
18659 Entry.isZExt = false;
18660 Args.push_back(Entry);
18662 bool isF64 = ArgVT == MVT::f64;
18663 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18664 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18665 // the results are returned via SRet in memory.
18666 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18667 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18668 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18670 Type *RetTy = isF64
18671 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18672 : (Type*)VectorType::get(ArgTy, 4);
18674 TargetLowering::CallLoweringInfo CLI(DAG);
18675 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18676 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18678 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18681 // Returned in xmm0 and xmm1.
18682 return CallResult.first;
18684 // Returned in bits 0:31 and 32:64 xmm0.
18685 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18686 CallResult.first, DAG.getIntPtrConstant(0));
18687 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18688 CallResult.first, DAG.getIntPtrConstant(1));
18689 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18690 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18693 /// LowerOperation - Provide custom lowering hooks for some operations.
18695 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18696 switch (Op.getOpcode()) {
18697 default: llvm_unreachable("Should not custom lower this!");
18698 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18699 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18700 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18701 return LowerCMP_SWAP(Op, Subtarget, DAG);
18702 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18703 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18704 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18705 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18706 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18707 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18708 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18709 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18710 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18711 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18712 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18713 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18714 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18715 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18716 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18717 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18718 case ISD::SHL_PARTS:
18719 case ISD::SRA_PARTS:
18720 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18721 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18722 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18723 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18724 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18725 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18726 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18727 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18728 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18729 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18730 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18732 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18733 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18734 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18735 case ISD::SETCC: return LowerSETCC(Op, DAG);
18736 case ISD::SELECT: return LowerSELECT(Op, DAG);
18737 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18738 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18739 case ISD::VASTART: return LowerVASTART(Op, DAG);
18740 case ISD::VAARG: return LowerVAARG(Op, DAG);
18741 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18742 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18743 case ISD::INTRINSIC_VOID:
18744 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18745 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18746 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18747 case ISD::FRAME_TO_ARGS_OFFSET:
18748 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18749 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18750 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18751 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18752 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18753 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18754 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18755 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18756 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18757 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18758 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18759 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18760 case ISD::UMUL_LOHI:
18761 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18764 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18770 case ISD::UMULO: return LowerXALUO(Op, DAG);
18771 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18772 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18776 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18777 case ISD::ADD: return LowerADD(Op, DAG);
18778 case ISD::SUB: return LowerSUB(Op, DAG);
18779 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18783 /// ReplaceNodeResults - Replace a node with an illegal result type
18784 /// with a new node built out of custom code.
18785 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18786 SmallVectorImpl<SDValue>&Results,
18787 SelectionDAG &DAG) const {
18789 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18790 switch (N->getOpcode()) {
18792 llvm_unreachable("Do not know how to custom type legalize this operation!");
18793 case ISD::SIGN_EXTEND_INREG:
18798 // We don't want to expand or promote these.
18805 case ISD::UDIVREM: {
18806 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18807 Results.push_back(V);
18810 case ISD::FP_TO_SINT:
18811 case ISD::FP_TO_UINT: {
18812 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18814 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18817 std::pair<SDValue,SDValue> Vals =
18818 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18819 SDValue FIST = Vals.first, StackSlot = Vals.second;
18820 if (FIST.getNode()) {
18821 EVT VT = N->getValueType(0);
18822 // Return a load from the stack slot.
18823 if (StackSlot.getNode())
18824 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18825 MachinePointerInfo(),
18826 false, false, false, 0));
18828 Results.push_back(FIST);
18832 case ISD::UINT_TO_FP: {
18833 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18834 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18835 N->getValueType(0) != MVT::v2f32)
18837 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18839 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18841 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18842 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18843 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18844 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18845 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18846 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18849 case ISD::FP_ROUND: {
18850 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18852 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18853 Results.push_back(V);
18856 case ISD::INTRINSIC_W_CHAIN: {
18857 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18859 default : llvm_unreachable("Do not know how to custom type "
18860 "legalize this intrinsic operation!");
18861 case Intrinsic::x86_rdtsc:
18862 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18864 case Intrinsic::x86_rdtscp:
18865 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18867 case Intrinsic::x86_rdpmc:
18868 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18871 case ISD::READCYCLECOUNTER: {
18872 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18875 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18876 EVT T = N->getValueType(0);
18877 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18878 bool Regs64bit = T == MVT::i128;
18879 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18880 SDValue cpInL, cpInH;
18881 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18882 DAG.getConstant(0, HalfT));
18883 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18884 DAG.getConstant(1, HalfT));
18885 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18886 Regs64bit ? X86::RAX : X86::EAX,
18888 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18889 Regs64bit ? X86::RDX : X86::EDX,
18890 cpInH, cpInL.getValue(1));
18891 SDValue swapInL, swapInH;
18892 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18893 DAG.getConstant(0, HalfT));
18894 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18895 DAG.getConstant(1, HalfT));
18896 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18897 Regs64bit ? X86::RBX : X86::EBX,
18898 swapInL, cpInH.getValue(1));
18899 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18900 Regs64bit ? X86::RCX : X86::ECX,
18901 swapInH, swapInL.getValue(1));
18902 SDValue Ops[] = { swapInH.getValue(0),
18904 swapInH.getValue(1) };
18905 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18906 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18907 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18908 X86ISD::LCMPXCHG8_DAG;
18909 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18910 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18911 Regs64bit ? X86::RAX : X86::EAX,
18912 HalfT, Result.getValue(1));
18913 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18914 Regs64bit ? X86::RDX : X86::EDX,
18915 HalfT, cpOutL.getValue(2));
18916 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18918 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18919 MVT::i32, cpOutH.getValue(2));
18921 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18922 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18923 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18925 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18926 Results.push_back(Success);
18927 Results.push_back(EFLAGS.getValue(1));
18930 case ISD::ATOMIC_SWAP:
18931 case ISD::ATOMIC_LOAD_ADD:
18932 case ISD::ATOMIC_LOAD_SUB:
18933 case ISD::ATOMIC_LOAD_AND:
18934 case ISD::ATOMIC_LOAD_OR:
18935 case ISD::ATOMIC_LOAD_XOR:
18936 case ISD::ATOMIC_LOAD_NAND:
18937 case ISD::ATOMIC_LOAD_MIN:
18938 case ISD::ATOMIC_LOAD_MAX:
18939 case ISD::ATOMIC_LOAD_UMIN:
18940 case ISD::ATOMIC_LOAD_UMAX:
18941 case ISD::ATOMIC_LOAD: {
18942 // Delegate to generic TypeLegalization. Situations we can really handle
18943 // should have already been dealt with by AtomicExpandPass.cpp.
18946 case ISD::BITCAST: {
18947 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18948 EVT DstVT = N->getValueType(0);
18949 EVT SrcVT = N->getOperand(0)->getValueType(0);
18951 if (SrcVT != MVT::f64 ||
18952 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18955 unsigned NumElts = DstVT.getVectorNumElements();
18956 EVT SVT = DstVT.getVectorElementType();
18957 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18958 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18959 MVT::v2f64, N->getOperand(0));
18960 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18962 if (ExperimentalVectorWideningLegalization) {
18963 // If we are legalizing vectors by widening, we already have the desired
18964 // legal vector type, just return it.
18965 Results.push_back(ToVecInt);
18969 SmallVector<SDValue, 8> Elts;
18970 for (unsigned i = 0, e = NumElts; i != e; ++i)
18971 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18972 ToVecInt, DAG.getIntPtrConstant(i)));
18974 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18979 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18981 default: return nullptr;
18982 case X86ISD::BSF: return "X86ISD::BSF";
18983 case X86ISD::BSR: return "X86ISD::BSR";
18984 case X86ISD::SHLD: return "X86ISD::SHLD";
18985 case X86ISD::SHRD: return "X86ISD::SHRD";
18986 case X86ISD::FAND: return "X86ISD::FAND";
18987 case X86ISD::FANDN: return "X86ISD::FANDN";
18988 case X86ISD::FOR: return "X86ISD::FOR";
18989 case X86ISD::FXOR: return "X86ISD::FXOR";
18990 case X86ISD::FSRL: return "X86ISD::FSRL";
18991 case X86ISD::FILD: return "X86ISD::FILD";
18992 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18993 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18994 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18995 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18996 case X86ISD::FLD: return "X86ISD::FLD";
18997 case X86ISD::FST: return "X86ISD::FST";
18998 case X86ISD::CALL: return "X86ISD::CALL";
18999 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19000 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19001 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19002 case X86ISD::BT: return "X86ISD::BT";
19003 case X86ISD::CMP: return "X86ISD::CMP";
19004 case X86ISD::COMI: return "X86ISD::COMI";
19005 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19006 case X86ISD::CMPM: return "X86ISD::CMPM";
19007 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19008 case X86ISD::SETCC: return "X86ISD::SETCC";
19009 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19010 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19011 case X86ISD::CMOV: return "X86ISD::CMOV";
19012 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19013 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19014 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19015 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19016 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19017 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19018 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19019 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19020 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19021 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19022 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19023 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19024 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19025 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19026 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19027 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19028 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19029 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19030 case X86ISD::HADD: return "X86ISD::HADD";
19031 case X86ISD::HSUB: return "X86ISD::HSUB";
19032 case X86ISD::FHADD: return "X86ISD::FHADD";
19033 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19034 case X86ISD::UMAX: return "X86ISD::UMAX";
19035 case X86ISD::UMIN: return "X86ISD::UMIN";
19036 case X86ISD::SMAX: return "X86ISD::SMAX";
19037 case X86ISD::SMIN: return "X86ISD::SMIN";
19038 case X86ISD::FMAX: return "X86ISD::FMAX";
19039 case X86ISD::FMIN: return "X86ISD::FMIN";
19040 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19041 case X86ISD::FMINC: return "X86ISD::FMINC";
19042 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19043 case X86ISD::FRCP: return "X86ISD::FRCP";
19044 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19045 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19046 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19047 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19048 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19049 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19050 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19051 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19052 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19053 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19054 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19055 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19056 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19057 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19058 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19059 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19060 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19061 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19062 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19063 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19064 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19065 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19066 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19067 case X86ISD::VSHL: return "X86ISD::VSHL";
19068 case X86ISD::VSRL: return "X86ISD::VSRL";
19069 case X86ISD::VSRA: return "X86ISD::VSRA";
19070 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19071 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19072 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19073 case X86ISD::CMPP: return "X86ISD::CMPP";
19074 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19075 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19076 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19077 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19078 case X86ISD::ADD: return "X86ISD::ADD";
19079 case X86ISD::SUB: return "X86ISD::SUB";
19080 case X86ISD::ADC: return "X86ISD::ADC";
19081 case X86ISD::SBB: return "X86ISD::SBB";
19082 case X86ISD::SMUL: return "X86ISD::SMUL";
19083 case X86ISD::UMUL: return "X86ISD::UMUL";
19084 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19085 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19086 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19087 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19088 case X86ISD::INC: return "X86ISD::INC";
19089 case X86ISD::DEC: return "X86ISD::DEC";
19090 case X86ISD::OR: return "X86ISD::OR";
19091 case X86ISD::XOR: return "X86ISD::XOR";
19092 case X86ISD::AND: return "X86ISD::AND";
19093 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19094 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19095 case X86ISD::PTEST: return "X86ISD::PTEST";
19096 case X86ISD::TESTP: return "X86ISD::TESTP";
19097 case X86ISD::TESTM: return "X86ISD::TESTM";
19098 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19099 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19100 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19101 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19102 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19103 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19104 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19105 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19106 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19107 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19108 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19109 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19110 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19111 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19112 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19113 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19114 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19115 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19116 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19117 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19118 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19119 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19120 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19121 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19122 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19123 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19124 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19125 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19126 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19127 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19128 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19129 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19130 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19131 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19132 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19133 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19134 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19135 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19136 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19137 case X86ISD::SAHF: return "X86ISD::SAHF";
19138 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19139 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19140 case X86ISD::FMADD: return "X86ISD::FMADD";
19141 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19142 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19143 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19144 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19145 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19146 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19147 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19148 case X86ISD::XTEST: return "X86ISD::XTEST";
19152 // isLegalAddressingMode - Return true if the addressing mode represented
19153 // by AM is legal for this target, for a load/store of the specified type.
19154 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19156 // X86 supports extremely general addressing modes.
19157 CodeModel::Model M = getTargetMachine().getCodeModel();
19158 Reloc::Model R = getTargetMachine().getRelocationModel();
19160 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19161 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19166 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19168 // If a reference to this global requires an extra load, we can't fold it.
19169 if (isGlobalStubReference(GVFlags))
19172 // If BaseGV requires a register for the PIC base, we cannot also have a
19173 // BaseReg specified.
19174 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19177 // If lower 4G is not available, then we must use rip-relative addressing.
19178 if ((M != CodeModel::Small || R != Reloc::Static) &&
19179 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19183 switch (AM.Scale) {
19189 // These scales always work.
19194 // These scales are formed with basereg+scalereg. Only accept if there is
19199 default: // Other stuff never works.
19206 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19207 unsigned Bits = Ty->getScalarSizeInBits();
19209 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19210 // particularly cheaper than those without.
19214 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19215 // variable shifts just as cheap as scalar ones.
19216 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19219 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19220 // fully general vector.
19224 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19225 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19227 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19228 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19229 return NumBits1 > NumBits2;
19232 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19233 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19236 if (!isTypeLegal(EVT::getEVT(Ty1)))
19239 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19241 // Assuming the caller doesn't have a zeroext or signext return parameter,
19242 // truncation all the way down to i1 is valid.
19246 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19247 return isInt<32>(Imm);
19250 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19251 // Can also use sub to handle negated immediates.
19252 return isInt<32>(Imm);
19255 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19256 if (!VT1.isInteger() || !VT2.isInteger())
19258 unsigned NumBits1 = VT1.getSizeInBits();
19259 unsigned NumBits2 = VT2.getSizeInBits();
19260 return NumBits1 > NumBits2;
19263 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19264 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19265 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19268 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19269 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19270 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19273 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19274 EVT VT1 = Val.getValueType();
19275 if (isZExtFree(VT1, VT2))
19278 if (Val.getOpcode() != ISD::LOAD)
19281 if (!VT1.isSimple() || !VT1.isInteger() ||
19282 !VT2.isSimple() || !VT2.isInteger())
19285 switch (VT1.getSimpleVT().SimpleTy) {
19290 // X86 has 8, 16, and 32-bit zero-extending loads.
19298 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19299 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19302 VT = VT.getScalarType();
19304 if (!VT.isSimple())
19307 switch (VT.getSimpleVT().SimpleTy) {
19318 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19319 // i16 instructions are longer (0x66 prefix) and potentially slower.
19320 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19323 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19324 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19325 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19326 /// are assumed to be legal.
19328 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19330 if (!VT.isSimple())
19333 MVT SVT = VT.getSimpleVT();
19335 // Very little shuffling can be done for 64-bit vectors right now.
19336 if (VT.getSizeInBits() == 64)
19339 // If this is a single-input shuffle with no 128 bit lane crossings we can
19340 // lower it into pshufb.
19341 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19342 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19343 bool isLegal = true;
19344 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19345 if (M[I] >= (int)SVT.getVectorNumElements() ||
19346 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19355 // FIXME: blends, shifts.
19356 return (SVT.getVectorNumElements() == 2 ||
19357 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19358 isMOVLMask(M, SVT) ||
19359 isMOVHLPSMask(M, SVT) ||
19360 isSHUFPMask(M, SVT) ||
19361 isPSHUFDMask(M, SVT) ||
19362 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19363 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19364 isPALIGNRMask(M, SVT, Subtarget) ||
19365 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19366 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19367 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19368 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19369 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19373 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19375 if (!VT.isSimple())
19378 MVT SVT = VT.getSimpleVT();
19379 unsigned NumElts = SVT.getVectorNumElements();
19380 // FIXME: This collection of masks seems suspect.
19383 if (NumElts == 4 && SVT.is128BitVector()) {
19384 return (isMOVLMask(Mask, SVT) ||
19385 isCommutedMOVLMask(Mask, SVT, true) ||
19386 isSHUFPMask(Mask, SVT) ||
19387 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19388 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19389 Subtarget->hasInt256()));
19394 //===----------------------------------------------------------------------===//
19395 // X86 Scheduler Hooks
19396 //===----------------------------------------------------------------------===//
19398 /// Utility function to emit xbegin specifying the start of an RTM region.
19399 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19400 const TargetInstrInfo *TII) {
19401 DebugLoc DL = MI->getDebugLoc();
19403 const BasicBlock *BB = MBB->getBasicBlock();
19404 MachineFunction::iterator I = MBB;
19407 // For the v = xbegin(), we generate
19418 MachineBasicBlock *thisMBB = MBB;
19419 MachineFunction *MF = MBB->getParent();
19420 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19421 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19422 MF->insert(I, mainMBB);
19423 MF->insert(I, sinkMBB);
19425 // Transfer the remainder of BB and its successor edges to sinkMBB.
19426 sinkMBB->splice(sinkMBB->begin(), MBB,
19427 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19428 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19432 // # fallthrough to mainMBB
19433 // # abortion to sinkMBB
19434 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19435 thisMBB->addSuccessor(mainMBB);
19436 thisMBB->addSuccessor(sinkMBB);
19440 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19441 mainMBB->addSuccessor(sinkMBB);
19444 // EAX is live into the sinkMBB
19445 sinkMBB->addLiveIn(X86::EAX);
19446 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19447 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19450 MI->eraseFromParent();
19454 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19455 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19456 // in the .td file.
19457 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19458 const TargetInstrInfo *TII) {
19460 switch (MI->getOpcode()) {
19461 default: llvm_unreachable("illegal opcode!");
19462 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19463 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19464 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19465 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19466 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19467 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19468 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19469 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19472 DebugLoc dl = MI->getDebugLoc();
19473 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19475 unsigned NumArgs = MI->getNumOperands();
19476 for (unsigned i = 1; i < NumArgs; ++i) {
19477 MachineOperand &Op = MI->getOperand(i);
19478 if (!(Op.isReg() && Op.isImplicit()))
19479 MIB.addOperand(Op);
19481 if (MI->hasOneMemOperand())
19482 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19484 BuildMI(*BB, MI, dl,
19485 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19486 .addReg(X86::XMM0);
19488 MI->eraseFromParent();
19492 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19493 // defs in an instruction pattern
19494 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19495 const TargetInstrInfo *TII) {
19497 switch (MI->getOpcode()) {
19498 default: llvm_unreachable("illegal opcode!");
19499 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19500 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19501 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19502 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19503 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19504 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19505 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19506 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19509 DebugLoc dl = MI->getDebugLoc();
19510 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19512 unsigned NumArgs = MI->getNumOperands(); // remove the results
19513 for (unsigned i = 1; i < NumArgs; ++i) {
19514 MachineOperand &Op = MI->getOperand(i);
19515 if (!(Op.isReg() && Op.isImplicit()))
19516 MIB.addOperand(Op);
19518 if (MI->hasOneMemOperand())
19519 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19521 BuildMI(*BB, MI, dl,
19522 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19525 MI->eraseFromParent();
19529 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19530 const TargetInstrInfo *TII,
19531 const X86Subtarget* Subtarget) {
19532 DebugLoc dl = MI->getDebugLoc();
19534 // Address into RAX/EAX, other two args into ECX, EDX.
19535 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19536 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19537 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19538 for (int i = 0; i < X86::AddrNumOperands; ++i)
19539 MIB.addOperand(MI->getOperand(i));
19541 unsigned ValOps = X86::AddrNumOperands;
19542 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19543 .addReg(MI->getOperand(ValOps).getReg());
19544 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19545 .addReg(MI->getOperand(ValOps+1).getReg());
19547 // The instruction doesn't actually take any operands though.
19548 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19550 MI->eraseFromParent(); // The pseudo is gone now.
19554 MachineBasicBlock *
19555 X86TargetLowering::EmitVAARG64WithCustomInserter(
19557 MachineBasicBlock *MBB) const {
19558 // Emit va_arg instruction on X86-64.
19560 // Operands to this pseudo-instruction:
19561 // 0 ) Output : destination address (reg)
19562 // 1-5) Input : va_list address (addr, i64mem)
19563 // 6 ) ArgSize : Size (in bytes) of vararg type
19564 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19565 // 8 ) Align : Alignment of type
19566 // 9 ) EFLAGS (implicit-def)
19568 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19569 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19571 unsigned DestReg = MI->getOperand(0).getReg();
19572 MachineOperand &Base = MI->getOperand(1);
19573 MachineOperand &Scale = MI->getOperand(2);
19574 MachineOperand &Index = MI->getOperand(3);
19575 MachineOperand &Disp = MI->getOperand(4);
19576 MachineOperand &Segment = MI->getOperand(5);
19577 unsigned ArgSize = MI->getOperand(6).getImm();
19578 unsigned ArgMode = MI->getOperand(7).getImm();
19579 unsigned Align = MI->getOperand(8).getImm();
19581 // Memory Reference
19582 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19583 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19584 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19586 // Machine Information
19587 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19588 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19589 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19590 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19591 DebugLoc DL = MI->getDebugLoc();
19593 // struct va_list {
19596 // i64 overflow_area (address)
19597 // i64 reg_save_area (address)
19599 // sizeof(va_list) = 24
19600 // alignment(va_list) = 8
19602 unsigned TotalNumIntRegs = 6;
19603 unsigned TotalNumXMMRegs = 8;
19604 bool UseGPOffset = (ArgMode == 1);
19605 bool UseFPOffset = (ArgMode == 2);
19606 unsigned MaxOffset = TotalNumIntRegs * 8 +
19607 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19609 /* Align ArgSize to a multiple of 8 */
19610 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19611 bool NeedsAlign = (Align > 8);
19613 MachineBasicBlock *thisMBB = MBB;
19614 MachineBasicBlock *overflowMBB;
19615 MachineBasicBlock *offsetMBB;
19616 MachineBasicBlock *endMBB;
19618 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19619 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19620 unsigned OffsetReg = 0;
19622 if (!UseGPOffset && !UseFPOffset) {
19623 // If we only pull from the overflow region, we don't create a branch.
19624 // We don't need to alter control flow.
19625 OffsetDestReg = 0; // unused
19626 OverflowDestReg = DestReg;
19628 offsetMBB = nullptr;
19629 overflowMBB = thisMBB;
19632 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19633 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19634 // If not, pull from overflow_area. (branch to overflowMBB)
19639 // offsetMBB overflowMBB
19644 // Registers for the PHI in endMBB
19645 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19646 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19648 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19649 MachineFunction *MF = MBB->getParent();
19650 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19651 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19652 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19654 MachineFunction::iterator MBBIter = MBB;
19657 // Insert the new basic blocks
19658 MF->insert(MBBIter, offsetMBB);
19659 MF->insert(MBBIter, overflowMBB);
19660 MF->insert(MBBIter, endMBB);
19662 // Transfer the remainder of MBB and its successor edges to endMBB.
19663 endMBB->splice(endMBB->begin(), thisMBB,
19664 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19665 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19667 // Make offsetMBB and overflowMBB successors of thisMBB
19668 thisMBB->addSuccessor(offsetMBB);
19669 thisMBB->addSuccessor(overflowMBB);
19671 // endMBB is a successor of both offsetMBB and overflowMBB
19672 offsetMBB->addSuccessor(endMBB);
19673 overflowMBB->addSuccessor(endMBB);
19675 // Load the offset value into a register
19676 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19677 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19681 .addDisp(Disp, UseFPOffset ? 4 : 0)
19682 .addOperand(Segment)
19683 .setMemRefs(MMOBegin, MMOEnd);
19685 // Check if there is enough room left to pull this argument.
19686 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19688 .addImm(MaxOffset + 8 - ArgSizeA8);
19690 // Branch to "overflowMBB" if offset >= max
19691 // Fall through to "offsetMBB" otherwise
19692 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19693 .addMBB(overflowMBB);
19696 // In offsetMBB, emit code to use the reg_save_area.
19698 assert(OffsetReg != 0);
19700 // Read the reg_save_area address.
19701 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19702 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19707 .addOperand(Segment)
19708 .setMemRefs(MMOBegin, MMOEnd);
19710 // Zero-extend the offset
19711 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19712 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19715 .addImm(X86::sub_32bit);
19717 // Add the offset to the reg_save_area to get the final address.
19718 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19719 .addReg(OffsetReg64)
19720 .addReg(RegSaveReg);
19722 // Compute the offset for the next argument
19723 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19724 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19726 .addImm(UseFPOffset ? 16 : 8);
19728 // Store it back into the va_list.
19729 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19733 .addDisp(Disp, UseFPOffset ? 4 : 0)
19734 .addOperand(Segment)
19735 .addReg(NextOffsetReg)
19736 .setMemRefs(MMOBegin, MMOEnd);
19739 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19744 // Emit code to use overflow area
19747 // Load the overflow_area address into a register.
19748 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19749 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19754 .addOperand(Segment)
19755 .setMemRefs(MMOBegin, MMOEnd);
19757 // If we need to align it, do so. Otherwise, just copy the address
19758 // to OverflowDestReg.
19760 // Align the overflow address
19761 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19762 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19764 // aligned_addr = (addr + (align-1)) & ~(align-1)
19765 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19766 .addReg(OverflowAddrReg)
19769 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19771 .addImm(~(uint64_t)(Align-1));
19773 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19774 .addReg(OverflowAddrReg);
19777 // Compute the next overflow address after this argument.
19778 // (the overflow address should be kept 8-byte aligned)
19779 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19780 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19781 .addReg(OverflowDestReg)
19782 .addImm(ArgSizeA8);
19784 // Store the new overflow address.
19785 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19790 .addOperand(Segment)
19791 .addReg(NextAddrReg)
19792 .setMemRefs(MMOBegin, MMOEnd);
19794 // If we branched, emit the PHI to the front of endMBB.
19796 BuildMI(*endMBB, endMBB->begin(), DL,
19797 TII->get(X86::PHI), DestReg)
19798 .addReg(OffsetDestReg).addMBB(offsetMBB)
19799 .addReg(OverflowDestReg).addMBB(overflowMBB);
19802 // Erase the pseudo instruction
19803 MI->eraseFromParent();
19808 MachineBasicBlock *
19809 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19811 MachineBasicBlock *MBB) const {
19812 // Emit code to save XMM registers to the stack. The ABI says that the
19813 // number of registers to save is given in %al, so it's theoretically
19814 // possible to do an indirect jump trick to avoid saving all of them,
19815 // however this code takes a simpler approach and just executes all
19816 // of the stores if %al is non-zero. It's less code, and it's probably
19817 // easier on the hardware branch predictor, and stores aren't all that
19818 // expensive anyway.
19820 // Create the new basic blocks. One block contains all the XMM stores,
19821 // and one block is the final destination regardless of whether any
19822 // stores were performed.
19823 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19824 MachineFunction *F = MBB->getParent();
19825 MachineFunction::iterator MBBIter = MBB;
19827 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19828 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19829 F->insert(MBBIter, XMMSaveMBB);
19830 F->insert(MBBIter, EndMBB);
19832 // Transfer the remainder of MBB and its successor edges to EndMBB.
19833 EndMBB->splice(EndMBB->begin(), MBB,
19834 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19835 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19837 // The original block will now fall through to the XMM save block.
19838 MBB->addSuccessor(XMMSaveMBB);
19839 // The XMMSaveMBB will fall through to the end block.
19840 XMMSaveMBB->addSuccessor(EndMBB);
19842 // Now add the instructions.
19843 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19844 DebugLoc DL = MI->getDebugLoc();
19846 unsigned CountReg = MI->getOperand(0).getReg();
19847 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19848 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19850 if (!Subtarget->isTargetWin64()) {
19851 // If %al is 0, branch around the XMM save block.
19852 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19853 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19854 MBB->addSuccessor(EndMBB);
19857 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19858 // that was just emitted, but clearly shouldn't be "saved".
19859 assert((MI->getNumOperands() <= 3 ||
19860 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19861 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19862 && "Expected last argument to be EFLAGS");
19863 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19864 // In the XMM save block, save all the XMM argument registers.
19865 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19866 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19867 MachineMemOperand *MMO =
19868 F->getMachineMemOperand(
19869 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19870 MachineMemOperand::MOStore,
19871 /*Size=*/16, /*Align=*/16);
19872 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19873 .addFrameIndex(RegSaveFrameIndex)
19874 .addImm(/*Scale=*/1)
19875 .addReg(/*IndexReg=*/0)
19876 .addImm(/*Disp=*/Offset)
19877 .addReg(/*Segment=*/0)
19878 .addReg(MI->getOperand(i).getReg())
19879 .addMemOperand(MMO);
19882 MI->eraseFromParent(); // The pseudo instruction is gone now.
19887 // The EFLAGS operand of SelectItr might be missing a kill marker
19888 // because there were multiple uses of EFLAGS, and ISel didn't know
19889 // which to mark. Figure out whether SelectItr should have had a
19890 // kill marker, and set it if it should. Returns the correct kill
19892 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19893 MachineBasicBlock* BB,
19894 const TargetRegisterInfo* TRI) {
19895 // Scan forward through BB for a use/def of EFLAGS.
19896 MachineBasicBlock::iterator miI(std::next(SelectItr));
19897 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19898 const MachineInstr& mi = *miI;
19899 if (mi.readsRegister(X86::EFLAGS))
19901 if (mi.definesRegister(X86::EFLAGS))
19902 break; // Should have kill-flag - update below.
19905 // If we hit the end of the block, check whether EFLAGS is live into a
19907 if (miI == BB->end()) {
19908 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19909 sEnd = BB->succ_end();
19910 sItr != sEnd; ++sItr) {
19911 MachineBasicBlock* succ = *sItr;
19912 if (succ->isLiveIn(X86::EFLAGS))
19917 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19918 // out. SelectMI should have a kill flag on EFLAGS.
19919 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19923 MachineBasicBlock *
19924 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19925 MachineBasicBlock *BB) const {
19926 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19927 DebugLoc DL = MI->getDebugLoc();
19929 // To "insert" a SELECT_CC instruction, we actually have to insert the
19930 // diamond control-flow pattern. The incoming instruction knows the
19931 // destination vreg to set, the condition code register to branch on, the
19932 // true/false values to select between, and a branch opcode to use.
19933 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19934 MachineFunction::iterator It = BB;
19940 // cmpTY ccX, r1, r2
19942 // fallthrough --> copy0MBB
19943 MachineBasicBlock *thisMBB = BB;
19944 MachineFunction *F = BB->getParent();
19945 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19946 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19947 F->insert(It, copy0MBB);
19948 F->insert(It, sinkMBB);
19950 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19951 // live into the sink and copy blocks.
19952 const TargetRegisterInfo *TRI =
19953 BB->getParent()->getSubtarget().getRegisterInfo();
19954 if (!MI->killsRegister(X86::EFLAGS) &&
19955 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19956 copy0MBB->addLiveIn(X86::EFLAGS);
19957 sinkMBB->addLiveIn(X86::EFLAGS);
19960 // Transfer the remainder of BB and its successor edges to sinkMBB.
19961 sinkMBB->splice(sinkMBB->begin(), BB,
19962 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19963 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19965 // Add the true and fallthrough blocks as its successors.
19966 BB->addSuccessor(copy0MBB);
19967 BB->addSuccessor(sinkMBB);
19969 // Create the conditional branch instruction.
19971 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19972 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19975 // %FalseValue = ...
19976 // # fallthrough to sinkMBB
19977 copy0MBB->addSuccessor(sinkMBB);
19980 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19982 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19983 TII->get(X86::PHI), MI->getOperand(0).getReg())
19984 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19985 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19987 MI->eraseFromParent(); // The pseudo instruction is gone now.
19991 MachineBasicBlock *
19992 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19993 MachineBasicBlock *BB) const {
19994 MachineFunction *MF = BB->getParent();
19995 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19996 DebugLoc DL = MI->getDebugLoc();
19997 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19999 assert(MF->shouldSplitStack());
20001 const bool Is64Bit = Subtarget->is64Bit();
20002 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20004 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20005 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20008 // ... [Till the alloca]
20009 // If stacklet is not large enough, jump to mallocMBB
20012 // Allocate by subtracting from RSP
20013 // Jump to continueMBB
20016 // Allocate by call to runtime
20020 // [rest of original BB]
20023 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20024 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20025 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20027 MachineRegisterInfo &MRI = MF->getRegInfo();
20028 const TargetRegisterClass *AddrRegClass =
20029 getRegClassFor(getPointerTy());
20031 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20032 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20033 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20034 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20035 sizeVReg = MI->getOperand(1).getReg(),
20036 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20038 MachineFunction::iterator MBBIter = BB;
20041 MF->insert(MBBIter, bumpMBB);
20042 MF->insert(MBBIter, mallocMBB);
20043 MF->insert(MBBIter, continueMBB);
20045 continueMBB->splice(continueMBB->begin(), BB,
20046 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20047 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20049 // Add code to the main basic block to check if the stack limit has been hit,
20050 // and if so, jump to mallocMBB otherwise to bumpMBB.
20051 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20052 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20053 .addReg(tmpSPVReg).addReg(sizeVReg);
20054 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20055 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20056 .addReg(SPLimitVReg);
20057 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20059 // bumpMBB simply decreases the stack pointer, since we know the current
20060 // stacklet has enough space.
20061 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20062 .addReg(SPLimitVReg);
20063 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20064 .addReg(SPLimitVReg);
20065 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20067 // Calls into a routine in libgcc to allocate more space from the heap.
20068 const uint32_t *RegMask = MF->getTarget()
20069 .getSubtargetImpl()
20070 ->getRegisterInfo()
20071 ->getCallPreservedMask(CallingConv::C);
20073 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20075 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20076 .addExternalSymbol("__morestack_allocate_stack_space")
20077 .addRegMask(RegMask)
20078 .addReg(X86::RDI, RegState::Implicit)
20079 .addReg(X86::RAX, RegState::ImplicitDefine);
20080 } else if (Is64Bit) {
20081 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20083 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20084 .addExternalSymbol("__morestack_allocate_stack_space")
20085 .addRegMask(RegMask)
20086 .addReg(X86::EDI, RegState::Implicit)
20087 .addReg(X86::EAX, RegState::ImplicitDefine);
20089 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20091 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20092 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20093 .addExternalSymbol("__morestack_allocate_stack_space")
20094 .addRegMask(RegMask)
20095 .addReg(X86::EAX, RegState::ImplicitDefine);
20099 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20102 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20103 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20104 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20106 // Set up the CFG correctly.
20107 BB->addSuccessor(bumpMBB);
20108 BB->addSuccessor(mallocMBB);
20109 mallocMBB->addSuccessor(continueMBB);
20110 bumpMBB->addSuccessor(continueMBB);
20112 // Take care of the PHI nodes.
20113 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20114 MI->getOperand(0).getReg())
20115 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20116 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20118 // Delete the original pseudo instruction.
20119 MI->eraseFromParent();
20122 return continueMBB;
20125 MachineBasicBlock *
20126 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20127 MachineBasicBlock *BB) const {
20128 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20129 DebugLoc DL = MI->getDebugLoc();
20131 assert(!Subtarget->isTargetMacho());
20133 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20134 // non-trivial part is impdef of ESP.
20136 if (Subtarget->isTargetWin64()) {
20137 if (Subtarget->isTargetCygMing()) {
20138 // ___chkstk(Mingw64):
20139 // Clobbers R10, R11, RAX and EFLAGS.
20141 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20142 .addExternalSymbol("___chkstk")
20143 .addReg(X86::RAX, RegState::Implicit)
20144 .addReg(X86::RSP, RegState::Implicit)
20145 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20146 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20147 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20149 // __chkstk(MSVCRT): does not update stack pointer.
20150 // Clobbers R10, R11 and EFLAGS.
20151 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20152 .addExternalSymbol("__chkstk")
20153 .addReg(X86::RAX, RegState::Implicit)
20154 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20155 // RAX has the offset to be subtracted from RSP.
20156 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20161 const char *StackProbeSymbol =
20162 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20164 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20165 .addExternalSymbol(StackProbeSymbol)
20166 .addReg(X86::EAX, RegState::Implicit)
20167 .addReg(X86::ESP, RegState::Implicit)
20168 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20169 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20170 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20173 MI->eraseFromParent(); // The pseudo instruction is gone now.
20177 MachineBasicBlock *
20178 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20179 MachineBasicBlock *BB) const {
20180 // This is pretty easy. We're taking the value that we received from
20181 // our load from the relocation, sticking it in either RDI (x86-64)
20182 // or EAX and doing an indirect call. The return value will then
20183 // be in the normal return register.
20184 MachineFunction *F = BB->getParent();
20185 const X86InstrInfo *TII =
20186 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20187 DebugLoc DL = MI->getDebugLoc();
20189 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20190 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20192 // Get a register mask for the lowered call.
20193 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20194 // proper register mask.
20195 const uint32_t *RegMask = F->getTarget()
20196 .getSubtargetImpl()
20197 ->getRegisterInfo()
20198 ->getCallPreservedMask(CallingConv::C);
20199 if (Subtarget->is64Bit()) {
20200 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20201 TII->get(X86::MOV64rm), X86::RDI)
20203 .addImm(0).addReg(0)
20204 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20205 MI->getOperand(3).getTargetFlags())
20207 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20208 addDirectMem(MIB, X86::RDI);
20209 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20210 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20211 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20212 TII->get(X86::MOV32rm), X86::EAX)
20214 .addImm(0).addReg(0)
20215 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20216 MI->getOperand(3).getTargetFlags())
20218 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20219 addDirectMem(MIB, X86::EAX);
20220 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20222 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20223 TII->get(X86::MOV32rm), X86::EAX)
20224 .addReg(TII->getGlobalBaseReg(F))
20225 .addImm(0).addReg(0)
20226 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20227 MI->getOperand(3).getTargetFlags())
20229 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20230 addDirectMem(MIB, X86::EAX);
20231 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20234 MI->eraseFromParent(); // The pseudo instruction is gone now.
20238 MachineBasicBlock *
20239 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20240 MachineBasicBlock *MBB) const {
20241 DebugLoc DL = MI->getDebugLoc();
20242 MachineFunction *MF = MBB->getParent();
20243 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20244 MachineRegisterInfo &MRI = MF->getRegInfo();
20246 const BasicBlock *BB = MBB->getBasicBlock();
20247 MachineFunction::iterator I = MBB;
20250 // Memory Reference
20251 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20252 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20255 unsigned MemOpndSlot = 0;
20257 unsigned CurOp = 0;
20259 DstReg = MI->getOperand(CurOp++).getReg();
20260 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20261 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20262 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20263 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20265 MemOpndSlot = CurOp;
20267 MVT PVT = getPointerTy();
20268 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20269 "Invalid Pointer Size!");
20271 // For v = setjmp(buf), we generate
20274 // buf[LabelOffset] = restoreMBB
20275 // SjLjSetup restoreMBB
20281 // v = phi(main, restore)
20286 MachineBasicBlock *thisMBB = MBB;
20287 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20288 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20289 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20290 MF->insert(I, mainMBB);
20291 MF->insert(I, sinkMBB);
20292 MF->push_back(restoreMBB);
20294 MachineInstrBuilder MIB;
20296 // Transfer the remainder of BB and its successor edges to sinkMBB.
20297 sinkMBB->splice(sinkMBB->begin(), MBB,
20298 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20299 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20302 unsigned PtrStoreOpc = 0;
20303 unsigned LabelReg = 0;
20304 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20305 Reloc::Model RM = MF->getTarget().getRelocationModel();
20306 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20307 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20309 // Prepare IP either in reg or imm.
20310 if (!UseImmLabel) {
20311 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20312 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20313 LabelReg = MRI.createVirtualRegister(PtrRC);
20314 if (Subtarget->is64Bit()) {
20315 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20319 .addMBB(restoreMBB)
20322 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20323 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20324 .addReg(XII->getGlobalBaseReg(MF))
20327 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20331 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20333 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20334 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20335 if (i == X86::AddrDisp)
20336 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20338 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20341 MIB.addReg(LabelReg);
20343 MIB.addMBB(restoreMBB);
20344 MIB.setMemRefs(MMOBegin, MMOEnd);
20346 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20347 .addMBB(restoreMBB);
20349 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20350 MF->getSubtarget().getRegisterInfo());
20351 MIB.addRegMask(RegInfo->getNoPreservedMask());
20352 thisMBB->addSuccessor(mainMBB);
20353 thisMBB->addSuccessor(restoreMBB);
20357 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20358 mainMBB->addSuccessor(sinkMBB);
20361 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20362 TII->get(X86::PHI), DstReg)
20363 .addReg(mainDstReg).addMBB(mainMBB)
20364 .addReg(restoreDstReg).addMBB(restoreMBB);
20367 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20368 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20369 restoreMBB->addSuccessor(sinkMBB);
20371 MI->eraseFromParent();
20375 MachineBasicBlock *
20376 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20377 MachineBasicBlock *MBB) const {
20378 DebugLoc DL = MI->getDebugLoc();
20379 MachineFunction *MF = MBB->getParent();
20380 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20381 MachineRegisterInfo &MRI = MF->getRegInfo();
20383 // Memory Reference
20384 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20385 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20387 MVT PVT = getPointerTy();
20388 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20389 "Invalid Pointer Size!");
20391 const TargetRegisterClass *RC =
20392 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20393 unsigned Tmp = MRI.createVirtualRegister(RC);
20394 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20395 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20396 MF->getSubtarget().getRegisterInfo());
20397 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20398 unsigned SP = RegInfo->getStackRegister();
20400 MachineInstrBuilder MIB;
20402 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20403 const int64_t SPOffset = 2 * PVT.getStoreSize();
20405 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20406 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20409 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20410 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20411 MIB.addOperand(MI->getOperand(i));
20412 MIB.setMemRefs(MMOBegin, MMOEnd);
20414 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20415 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20416 if (i == X86::AddrDisp)
20417 MIB.addDisp(MI->getOperand(i), LabelOffset);
20419 MIB.addOperand(MI->getOperand(i));
20421 MIB.setMemRefs(MMOBegin, MMOEnd);
20423 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20424 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20425 if (i == X86::AddrDisp)
20426 MIB.addDisp(MI->getOperand(i), SPOffset);
20428 MIB.addOperand(MI->getOperand(i));
20430 MIB.setMemRefs(MMOBegin, MMOEnd);
20432 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20434 MI->eraseFromParent();
20438 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20439 // accumulator loops. Writing back to the accumulator allows the coalescer
20440 // to remove extra copies in the loop.
20441 MachineBasicBlock *
20442 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20443 MachineBasicBlock *MBB) const {
20444 MachineOperand &AddendOp = MI->getOperand(3);
20446 // Bail out early if the addend isn't a register - we can't switch these.
20447 if (!AddendOp.isReg())
20450 MachineFunction &MF = *MBB->getParent();
20451 MachineRegisterInfo &MRI = MF.getRegInfo();
20453 // Check whether the addend is defined by a PHI:
20454 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20455 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20456 if (!AddendDef.isPHI())
20459 // Look for the following pattern:
20461 // %addend = phi [%entry, 0], [%loop, %result]
20463 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20467 // %addend = phi [%entry, 0], [%loop, %result]
20469 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20471 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20472 assert(AddendDef.getOperand(i).isReg());
20473 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20474 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20475 if (&PHISrcInst == MI) {
20476 // Found a matching instruction.
20477 unsigned NewFMAOpc = 0;
20478 switch (MI->getOpcode()) {
20479 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20480 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20481 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20482 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20483 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20484 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20485 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20486 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20487 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20488 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20489 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20490 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20491 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20492 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20493 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20494 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20495 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20496 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20497 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20498 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20500 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20501 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20502 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20503 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20504 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20505 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20506 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20507 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20508 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20509 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20510 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20511 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20512 default: llvm_unreachable("Unrecognized FMA variant.");
20515 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20516 MachineInstrBuilder MIB =
20517 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20518 .addOperand(MI->getOperand(0))
20519 .addOperand(MI->getOperand(3))
20520 .addOperand(MI->getOperand(2))
20521 .addOperand(MI->getOperand(1));
20522 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20523 MI->eraseFromParent();
20530 MachineBasicBlock *
20531 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20532 MachineBasicBlock *BB) const {
20533 switch (MI->getOpcode()) {
20534 default: llvm_unreachable("Unexpected instr type to insert");
20535 case X86::TAILJMPd64:
20536 case X86::TAILJMPr64:
20537 case X86::TAILJMPm64:
20538 llvm_unreachable("TAILJMP64 would not be touched here.");
20539 case X86::TCRETURNdi64:
20540 case X86::TCRETURNri64:
20541 case X86::TCRETURNmi64:
20543 case X86::WIN_ALLOCA:
20544 return EmitLoweredWinAlloca(MI, BB);
20545 case X86::SEG_ALLOCA_32:
20546 case X86::SEG_ALLOCA_64:
20547 return EmitLoweredSegAlloca(MI, BB);
20548 case X86::TLSCall_32:
20549 case X86::TLSCall_64:
20550 return EmitLoweredTLSCall(MI, BB);
20551 case X86::CMOV_GR8:
20552 case X86::CMOV_FR32:
20553 case X86::CMOV_FR64:
20554 case X86::CMOV_V4F32:
20555 case X86::CMOV_V2F64:
20556 case X86::CMOV_V2I64:
20557 case X86::CMOV_V8F32:
20558 case X86::CMOV_V4F64:
20559 case X86::CMOV_V4I64:
20560 case X86::CMOV_V16F32:
20561 case X86::CMOV_V8F64:
20562 case X86::CMOV_V8I64:
20563 case X86::CMOV_GR16:
20564 case X86::CMOV_GR32:
20565 case X86::CMOV_RFP32:
20566 case X86::CMOV_RFP64:
20567 case X86::CMOV_RFP80:
20568 return EmitLoweredSelect(MI, BB);
20570 case X86::FP32_TO_INT16_IN_MEM:
20571 case X86::FP32_TO_INT32_IN_MEM:
20572 case X86::FP32_TO_INT64_IN_MEM:
20573 case X86::FP64_TO_INT16_IN_MEM:
20574 case X86::FP64_TO_INT32_IN_MEM:
20575 case X86::FP64_TO_INT64_IN_MEM:
20576 case X86::FP80_TO_INT16_IN_MEM:
20577 case X86::FP80_TO_INT32_IN_MEM:
20578 case X86::FP80_TO_INT64_IN_MEM: {
20579 MachineFunction *F = BB->getParent();
20580 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20581 DebugLoc DL = MI->getDebugLoc();
20583 // Change the floating point control register to use "round towards zero"
20584 // mode when truncating to an integer value.
20585 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20586 addFrameReference(BuildMI(*BB, MI, DL,
20587 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20589 // Load the old value of the high byte of the control word...
20591 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20592 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20595 // Set the high part to be round to zero...
20596 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20599 // Reload the modified control word now...
20600 addFrameReference(BuildMI(*BB, MI, DL,
20601 TII->get(X86::FLDCW16m)), CWFrameIdx);
20603 // Restore the memory image of control word to original value
20604 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20607 // Get the X86 opcode to use.
20609 switch (MI->getOpcode()) {
20610 default: llvm_unreachable("illegal opcode!");
20611 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20612 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20613 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20614 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20615 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20616 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20617 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20618 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20619 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20623 MachineOperand &Op = MI->getOperand(0);
20625 AM.BaseType = X86AddressMode::RegBase;
20626 AM.Base.Reg = Op.getReg();
20628 AM.BaseType = X86AddressMode::FrameIndexBase;
20629 AM.Base.FrameIndex = Op.getIndex();
20631 Op = MI->getOperand(1);
20633 AM.Scale = Op.getImm();
20634 Op = MI->getOperand(2);
20636 AM.IndexReg = Op.getImm();
20637 Op = MI->getOperand(3);
20638 if (Op.isGlobal()) {
20639 AM.GV = Op.getGlobal();
20641 AM.Disp = Op.getImm();
20643 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20644 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20646 // Reload the original control word now.
20647 addFrameReference(BuildMI(*BB, MI, DL,
20648 TII->get(X86::FLDCW16m)), CWFrameIdx);
20650 MI->eraseFromParent(); // The pseudo instruction is gone now.
20653 // String/text processing lowering.
20654 case X86::PCMPISTRM128REG:
20655 case X86::VPCMPISTRM128REG:
20656 case X86::PCMPISTRM128MEM:
20657 case X86::VPCMPISTRM128MEM:
20658 case X86::PCMPESTRM128REG:
20659 case X86::VPCMPESTRM128REG:
20660 case X86::PCMPESTRM128MEM:
20661 case X86::VPCMPESTRM128MEM:
20662 assert(Subtarget->hasSSE42() &&
20663 "Target must have SSE4.2 or AVX features enabled");
20664 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20666 // String/text processing lowering.
20667 case X86::PCMPISTRIREG:
20668 case X86::VPCMPISTRIREG:
20669 case X86::PCMPISTRIMEM:
20670 case X86::VPCMPISTRIMEM:
20671 case X86::PCMPESTRIREG:
20672 case X86::VPCMPESTRIREG:
20673 case X86::PCMPESTRIMEM:
20674 case X86::VPCMPESTRIMEM:
20675 assert(Subtarget->hasSSE42() &&
20676 "Target must have SSE4.2 or AVX features enabled");
20677 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20679 // Thread synchronization.
20681 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20686 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20688 case X86::VASTART_SAVE_XMM_REGS:
20689 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20691 case X86::VAARG_64:
20692 return EmitVAARG64WithCustomInserter(MI, BB);
20694 case X86::EH_SjLj_SetJmp32:
20695 case X86::EH_SjLj_SetJmp64:
20696 return emitEHSjLjSetJmp(MI, BB);
20698 case X86::EH_SjLj_LongJmp32:
20699 case X86::EH_SjLj_LongJmp64:
20700 return emitEHSjLjLongJmp(MI, BB);
20702 case TargetOpcode::STACKMAP:
20703 case TargetOpcode::PATCHPOINT:
20704 return emitPatchPoint(MI, BB);
20706 case X86::VFMADDPDr213r:
20707 case X86::VFMADDPSr213r:
20708 case X86::VFMADDSDr213r:
20709 case X86::VFMADDSSr213r:
20710 case X86::VFMSUBPDr213r:
20711 case X86::VFMSUBPSr213r:
20712 case X86::VFMSUBSDr213r:
20713 case X86::VFMSUBSSr213r:
20714 case X86::VFNMADDPDr213r:
20715 case X86::VFNMADDPSr213r:
20716 case X86::VFNMADDSDr213r:
20717 case X86::VFNMADDSSr213r:
20718 case X86::VFNMSUBPDr213r:
20719 case X86::VFNMSUBPSr213r:
20720 case X86::VFNMSUBSDr213r:
20721 case X86::VFNMSUBSSr213r:
20722 case X86::VFMADDSUBPDr213r:
20723 case X86::VFMADDSUBPSr213r:
20724 case X86::VFMSUBADDPDr213r:
20725 case X86::VFMSUBADDPSr213r:
20726 case X86::VFMADDPDr213rY:
20727 case X86::VFMADDPSr213rY:
20728 case X86::VFMSUBPDr213rY:
20729 case X86::VFMSUBPSr213rY:
20730 case X86::VFNMADDPDr213rY:
20731 case X86::VFNMADDPSr213rY:
20732 case X86::VFNMSUBPDr213rY:
20733 case X86::VFNMSUBPSr213rY:
20734 case X86::VFMADDSUBPDr213rY:
20735 case X86::VFMADDSUBPSr213rY:
20736 case X86::VFMSUBADDPDr213rY:
20737 case X86::VFMSUBADDPSr213rY:
20738 return emitFMA3Instr(MI, BB);
20742 //===----------------------------------------------------------------------===//
20743 // X86 Optimization Hooks
20744 //===----------------------------------------------------------------------===//
20746 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20749 const SelectionDAG &DAG,
20750 unsigned Depth) const {
20751 unsigned BitWidth = KnownZero.getBitWidth();
20752 unsigned Opc = Op.getOpcode();
20753 assert((Opc >= ISD::BUILTIN_OP_END ||
20754 Opc == ISD::INTRINSIC_WO_CHAIN ||
20755 Opc == ISD::INTRINSIC_W_CHAIN ||
20756 Opc == ISD::INTRINSIC_VOID) &&
20757 "Should use MaskedValueIsZero if you don't know whether Op"
20758 " is a target node!");
20760 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20774 // These nodes' second result is a boolean.
20775 if (Op.getResNo() == 0)
20778 case X86ISD::SETCC:
20779 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20781 case ISD::INTRINSIC_WO_CHAIN: {
20782 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20783 unsigned NumLoBits = 0;
20786 case Intrinsic::x86_sse_movmsk_ps:
20787 case Intrinsic::x86_avx_movmsk_ps_256:
20788 case Intrinsic::x86_sse2_movmsk_pd:
20789 case Intrinsic::x86_avx_movmsk_pd_256:
20790 case Intrinsic::x86_mmx_pmovmskb:
20791 case Intrinsic::x86_sse2_pmovmskb_128:
20792 case Intrinsic::x86_avx2_pmovmskb: {
20793 // High bits of movmskp{s|d}, pmovmskb are known zero.
20795 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20796 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20797 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20798 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20799 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20800 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20801 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20802 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20804 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20813 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20815 const SelectionDAG &,
20816 unsigned Depth) const {
20817 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20818 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20819 return Op.getValueType().getScalarType().getSizeInBits();
20825 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20826 /// node is a GlobalAddress + offset.
20827 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20828 const GlobalValue* &GA,
20829 int64_t &Offset) const {
20830 if (N->getOpcode() == X86ISD::Wrapper) {
20831 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20832 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20833 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20837 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20840 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20841 /// same as extracting the high 128-bit part of 256-bit vector and then
20842 /// inserting the result into the low part of a new 256-bit vector
20843 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20844 EVT VT = SVOp->getValueType(0);
20845 unsigned NumElems = VT.getVectorNumElements();
20847 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20848 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20849 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20850 SVOp->getMaskElt(j) >= 0)
20856 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20857 /// same as extracting the low 128-bit part of 256-bit vector and then
20858 /// inserting the result into the high part of a new 256-bit vector
20859 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20860 EVT VT = SVOp->getValueType(0);
20861 unsigned NumElems = VT.getVectorNumElements();
20863 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20864 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20865 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20866 SVOp->getMaskElt(j) >= 0)
20872 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20873 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20874 TargetLowering::DAGCombinerInfo &DCI,
20875 const X86Subtarget* Subtarget) {
20877 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20878 SDValue V1 = SVOp->getOperand(0);
20879 SDValue V2 = SVOp->getOperand(1);
20880 EVT VT = SVOp->getValueType(0);
20881 unsigned NumElems = VT.getVectorNumElements();
20883 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20884 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20888 // V UNDEF BUILD_VECTOR UNDEF
20890 // CONCAT_VECTOR CONCAT_VECTOR
20893 // RESULT: V + zero extended
20895 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20896 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20897 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20900 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20903 // To match the shuffle mask, the first half of the mask should
20904 // be exactly the first vector, and all the rest a splat with the
20905 // first element of the second one.
20906 for (unsigned i = 0; i != NumElems/2; ++i)
20907 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20908 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20911 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20912 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20913 if (Ld->hasNUsesOfValue(1, 0)) {
20914 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20915 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20917 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20919 Ld->getPointerInfo(),
20920 Ld->getAlignment(),
20921 false/*isVolatile*/, true/*ReadMem*/,
20922 false/*WriteMem*/);
20924 // Make sure the newly-created LOAD is in the same position as Ld in
20925 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20926 // and update uses of Ld's output chain to use the TokenFactor.
20927 if (Ld->hasAnyUseOfValue(1)) {
20928 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20929 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20930 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20931 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20932 SDValue(ResNode.getNode(), 1));
20935 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20939 // Emit a zeroed vector and insert the desired subvector on its
20941 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20942 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20943 return DCI.CombineTo(N, InsV);
20946 //===--------------------------------------------------------------------===//
20947 // Combine some shuffles into subvector extracts and inserts:
20950 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20951 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20952 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20953 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20954 return DCI.CombineTo(N, InsV);
20957 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20958 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20959 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20960 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20961 return DCI.CombineTo(N, InsV);
20967 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20970 /// This is the leaf of the recursive combinine below. When we have found some
20971 /// chain of single-use x86 shuffle instructions and accumulated the combined
20972 /// shuffle mask represented by them, this will try to pattern match that mask
20973 /// into either a single instruction if there is a special purpose instruction
20974 /// for this operation, or into a PSHUFB instruction which is a fully general
20975 /// instruction but should only be used to replace chains over a certain depth.
20976 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20977 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20978 TargetLowering::DAGCombinerInfo &DCI,
20979 const X86Subtarget *Subtarget) {
20980 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20982 // Find the operand that enters the chain. Note that multiple uses are OK
20983 // here, we're not going to remove the operand we find.
20984 SDValue Input = Op.getOperand(0);
20985 while (Input.getOpcode() == ISD::BITCAST)
20986 Input = Input.getOperand(0);
20988 MVT VT = Input.getSimpleValueType();
20989 MVT RootVT = Root.getSimpleValueType();
20992 // Just remove no-op shuffle masks.
20993 if (Mask.size() == 1) {
20994 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20999 // Use the float domain if the operand type is a floating point type.
21000 bool FloatDomain = VT.isFloatingPoint();
21002 // For floating point shuffles, we don't have free copies in the shuffle
21003 // instructions or the ability to load as part of the instruction, so
21004 // canonicalize their shuffles to UNPCK or MOV variants.
21006 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21007 // vectors because it can have a load folded into it that UNPCK cannot. This
21008 // doesn't preclude something switching to the shorter encoding post-RA.
21010 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21011 bool Lo = Mask.equals(0, 0);
21014 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21015 // is no slower than UNPCKLPD but has the option to fold the input operand
21016 // into even an unaligned memory load.
21017 if (Lo && Subtarget->hasSSE3()) {
21018 Shuffle = X86ISD::MOVDDUP;
21019 ShuffleVT = MVT::v2f64;
21021 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21022 // than the UNPCK variants.
21023 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21024 ShuffleVT = MVT::v4f32;
21026 if (Depth == 1 && Root->getOpcode() == Shuffle)
21027 return false; // Nothing to do!
21028 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21029 DCI.AddToWorklist(Op.getNode());
21030 if (Shuffle == X86ISD::MOVDDUP)
21031 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21033 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21034 DCI.AddToWorklist(Op.getNode());
21035 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21039 if (Subtarget->hasSSE3() &&
21040 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21041 bool Lo = Mask.equals(0, 0, 2, 2);
21042 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21043 MVT ShuffleVT = MVT::v4f32;
21044 if (Depth == 1 && Root->getOpcode() == Shuffle)
21045 return false; // Nothing to do!
21046 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21047 DCI.AddToWorklist(Op.getNode());
21048 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21049 DCI.AddToWorklist(Op.getNode());
21050 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21054 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21055 bool Lo = Mask.equals(0, 0, 1, 1);
21056 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21057 MVT ShuffleVT = MVT::v4f32;
21058 if (Depth == 1 && Root->getOpcode() == Shuffle)
21059 return false; // Nothing to do!
21060 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21061 DCI.AddToWorklist(Op.getNode());
21062 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21063 DCI.AddToWorklist(Op.getNode());
21064 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21070 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21071 // variants as none of these have single-instruction variants that are
21072 // superior to the UNPCK formulation.
21073 if (!FloatDomain &&
21074 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21075 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21076 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21077 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21079 bool Lo = Mask[0] == 0;
21080 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21081 if (Depth == 1 && Root->getOpcode() == Shuffle)
21082 return false; // Nothing to do!
21084 switch (Mask.size()) {
21086 ShuffleVT = MVT::v8i16;
21089 ShuffleVT = MVT::v16i8;
21092 llvm_unreachable("Impossible mask size!");
21094 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21095 DCI.AddToWorklist(Op.getNode());
21096 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21097 DCI.AddToWorklist(Op.getNode());
21098 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21103 // Don't try to re-form single instruction chains under any circumstances now
21104 // that we've done encoding canonicalization for them.
21108 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21109 // can replace them with a single PSHUFB instruction profitably. Intel's
21110 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21111 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21112 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21113 SmallVector<SDValue, 16> PSHUFBMask;
21114 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21115 int Ratio = 16 / Mask.size();
21116 for (unsigned i = 0; i < 16; ++i) {
21117 if (Mask[i / Ratio] == SM_SentinelUndef) {
21118 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21121 int M = Mask[i / Ratio] != SM_SentinelZero
21122 ? Ratio * Mask[i / Ratio] + i % Ratio
21124 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21126 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21127 DCI.AddToWorklist(Op.getNode());
21128 SDValue PSHUFBMaskOp =
21129 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21130 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21131 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21132 DCI.AddToWorklist(Op.getNode());
21133 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21138 // Failed to find any combines.
21142 /// \brief Fully generic combining of x86 shuffle instructions.
21144 /// This should be the last combine run over the x86 shuffle instructions. Once
21145 /// they have been fully optimized, this will recursively consider all chains
21146 /// of single-use shuffle instructions, build a generic model of the cumulative
21147 /// shuffle operation, and check for simpler instructions which implement this
21148 /// operation. We use this primarily for two purposes:
21150 /// 1) Collapse generic shuffles to specialized single instructions when
21151 /// equivalent. In most cases, this is just an encoding size win, but
21152 /// sometimes we will collapse multiple generic shuffles into a single
21153 /// special-purpose shuffle.
21154 /// 2) Look for sequences of shuffle instructions with 3 or more total
21155 /// instructions, and replace them with the slightly more expensive SSSE3
21156 /// PSHUFB instruction if available. We do this as the last combining step
21157 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21158 /// a suitable short sequence of other instructions. The PHUFB will either
21159 /// use a register or have to read from memory and so is slightly (but only
21160 /// slightly) more expensive than the other shuffle instructions.
21162 /// Because this is inherently a quadratic operation (for each shuffle in
21163 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21164 /// This should never be an issue in practice as the shuffle lowering doesn't
21165 /// produce sequences of more than 8 instructions.
21167 /// FIXME: We will currently miss some cases where the redundant shuffling
21168 /// would simplify under the threshold for PSHUFB formation because of
21169 /// combine-ordering. To fix this, we should do the redundant instruction
21170 /// combining in this recursive walk.
21171 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21172 ArrayRef<int> RootMask,
21173 int Depth, bool HasPSHUFB,
21175 TargetLowering::DAGCombinerInfo &DCI,
21176 const X86Subtarget *Subtarget) {
21177 // Bound the depth of our recursive combine because this is ultimately
21178 // quadratic in nature.
21182 // Directly rip through bitcasts to find the underlying operand.
21183 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21184 Op = Op.getOperand(0);
21186 MVT VT = Op.getSimpleValueType();
21187 if (!VT.isVector())
21188 return false; // Bail if we hit a non-vector.
21189 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21190 // version should be added.
21191 if (VT.getSizeInBits() != 128)
21194 assert(Root.getSimpleValueType().isVector() &&
21195 "Shuffles operate on vector types!");
21196 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21197 "Can only combine shuffles of the same vector register size.");
21199 if (!isTargetShuffle(Op.getOpcode()))
21201 SmallVector<int, 16> OpMask;
21203 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21204 // We only can combine unary shuffles which we can decode the mask for.
21205 if (!HaveMask || !IsUnary)
21208 assert(VT.getVectorNumElements() == OpMask.size() &&
21209 "Different mask size from vector size!");
21210 assert(((RootMask.size() > OpMask.size() &&
21211 RootMask.size() % OpMask.size() == 0) ||
21212 (OpMask.size() > RootMask.size() &&
21213 OpMask.size() % RootMask.size() == 0) ||
21214 OpMask.size() == RootMask.size()) &&
21215 "The smaller number of elements must divide the larger.");
21216 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21217 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21218 assert(((RootRatio == 1 && OpRatio == 1) ||
21219 (RootRatio == 1) != (OpRatio == 1)) &&
21220 "Must not have a ratio for both incoming and op masks!");
21222 SmallVector<int, 16> Mask;
21223 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21225 // Merge this shuffle operation's mask into our accumulated mask. Note that
21226 // this shuffle's mask will be the first applied to the input, followed by the
21227 // root mask to get us all the way to the root value arrangement. The reason
21228 // for this order is that we are recursing up the operation chain.
21229 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21230 int RootIdx = i / RootRatio;
21231 if (RootMask[RootIdx] < 0) {
21232 // This is a zero or undef lane, we're done.
21233 Mask.push_back(RootMask[RootIdx]);
21237 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21238 int OpIdx = RootMaskedIdx / OpRatio;
21239 if (OpMask[OpIdx] < 0) {
21240 // The incoming lanes are zero or undef, it doesn't matter which ones we
21242 Mask.push_back(OpMask[OpIdx]);
21246 // Ok, we have non-zero lanes, map them through.
21247 Mask.push_back(OpMask[OpIdx] * OpRatio +
21248 RootMaskedIdx % OpRatio);
21251 // See if we can recurse into the operand to combine more things.
21252 switch (Op.getOpcode()) {
21253 case X86ISD::PSHUFB:
21255 case X86ISD::PSHUFD:
21256 case X86ISD::PSHUFHW:
21257 case X86ISD::PSHUFLW:
21258 if (Op.getOperand(0).hasOneUse() &&
21259 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21260 HasPSHUFB, DAG, DCI, Subtarget))
21264 case X86ISD::UNPCKL:
21265 case X86ISD::UNPCKH:
21266 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21267 // We can't check for single use, we have to check that this shuffle is the only user.
21268 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21269 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21270 HasPSHUFB, DAG, DCI, Subtarget))
21275 // Minor canonicalization of the accumulated shuffle mask to make it easier
21276 // to match below. All this does is detect masks with squential pairs of
21277 // elements, and shrink them to the half-width mask. It does this in a loop
21278 // so it will reduce the size of the mask to the minimal width mask which
21279 // performs an equivalent shuffle.
21280 SmallVector<int, 16> WidenedMask;
21281 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21282 Mask = std::move(WidenedMask);
21283 WidenedMask.clear();
21286 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21290 /// \brief Get the PSHUF-style mask from PSHUF node.
21292 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21293 /// PSHUF-style masks that can be reused with such instructions.
21294 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21295 SmallVector<int, 4> Mask;
21297 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21301 switch (N.getOpcode()) {
21302 case X86ISD::PSHUFD:
21304 case X86ISD::PSHUFLW:
21307 case X86ISD::PSHUFHW:
21308 Mask.erase(Mask.begin(), Mask.begin() + 4);
21309 for (int &M : Mask)
21313 llvm_unreachable("No valid shuffle instruction found!");
21317 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21319 /// We walk up the chain and look for a combinable shuffle, skipping over
21320 /// shuffles that we could hoist this shuffle's transformation past without
21321 /// altering anything.
21323 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21325 TargetLowering::DAGCombinerInfo &DCI) {
21326 assert(N.getOpcode() == X86ISD::PSHUFD &&
21327 "Called with something other than an x86 128-bit half shuffle!");
21330 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21331 // of the shuffles in the chain so that we can form a fresh chain to replace
21333 SmallVector<SDValue, 8> Chain;
21334 SDValue V = N.getOperand(0);
21335 for (; V.hasOneUse(); V = V.getOperand(0)) {
21336 switch (V.getOpcode()) {
21338 return SDValue(); // Nothing combined!
21341 // Skip bitcasts as we always know the type for the target specific
21345 case X86ISD::PSHUFD:
21346 // Found another dword shuffle.
21349 case X86ISD::PSHUFLW:
21350 // Check that the low words (being shuffled) are the identity in the
21351 // dword shuffle, and the high words are self-contained.
21352 if (Mask[0] != 0 || Mask[1] != 1 ||
21353 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21356 Chain.push_back(V);
21359 case X86ISD::PSHUFHW:
21360 // Check that the high words (being shuffled) are the identity in the
21361 // dword shuffle, and the low words are self-contained.
21362 if (Mask[2] != 2 || Mask[3] != 3 ||
21363 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21366 Chain.push_back(V);
21369 case X86ISD::UNPCKL:
21370 case X86ISD::UNPCKH:
21371 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21372 // shuffle into a preceding word shuffle.
21373 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21376 // Search for a half-shuffle which we can combine with.
21377 unsigned CombineOp =
21378 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21379 if (V.getOperand(0) != V.getOperand(1) ||
21380 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21382 Chain.push_back(V);
21383 V = V.getOperand(0);
21385 switch (V.getOpcode()) {
21387 return SDValue(); // Nothing to combine.
21389 case X86ISD::PSHUFLW:
21390 case X86ISD::PSHUFHW:
21391 if (V.getOpcode() == CombineOp)
21394 Chain.push_back(V);
21398 V = V.getOperand(0);
21402 } while (V.hasOneUse());
21405 // Break out of the loop if we break out of the switch.
21409 if (!V.hasOneUse())
21410 // We fell out of the loop without finding a viable combining instruction.
21413 // Merge this node's mask and our incoming mask.
21414 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21415 for (int &M : Mask)
21417 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21418 getV4X86ShuffleImm8ForMask(Mask, DAG));
21420 // Rebuild the chain around this new shuffle.
21421 while (!Chain.empty()) {
21422 SDValue W = Chain.pop_back_val();
21424 if (V.getValueType() != W.getOperand(0).getValueType())
21425 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21427 switch (W.getOpcode()) {
21429 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21431 case X86ISD::UNPCKL:
21432 case X86ISD::UNPCKH:
21433 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21436 case X86ISD::PSHUFD:
21437 case X86ISD::PSHUFLW:
21438 case X86ISD::PSHUFHW:
21439 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21443 if (V.getValueType() != N.getValueType())
21444 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21446 // Return the new chain to replace N.
21450 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21452 /// We walk up the chain, skipping shuffles of the other half and looking
21453 /// through shuffles which switch halves trying to find a shuffle of the same
21454 /// pair of dwords.
21455 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21457 TargetLowering::DAGCombinerInfo &DCI) {
21459 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21460 "Called with something other than an x86 128-bit half shuffle!");
21462 unsigned CombineOpcode = N.getOpcode();
21464 // Walk up a single-use chain looking for a combinable shuffle.
21465 SDValue V = N.getOperand(0);
21466 for (; V.hasOneUse(); V = V.getOperand(0)) {
21467 switch (V.getOpcode()) {
21469 return false; // Nothing combined!
21472 // Skip bitcasts as we always know the type for the target specific
21476 case X86ISD::PSHUFLW:
21477 case X86ISD::PSHUFHW:
21478 if (V.getOpcode() == CombineOpcode)
21481 // Other-half shuffles are no-ops.
21484 // Break out of the loop if we break out of the switch.
21488 if (!V.hasOneUse())
21489 // We fell out of the loop without finding a viable combining instruction.
21492 // Combine away the bottom node as its shuffle will be accumulated into
21493 // a preceding shuffle.
21494 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21496 // Record the old value.
21499 // Merge this node's mask and our incoming mask (adjusted to account for all
21500 // the pshufd instructions encountered).
21501 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21502 for (int &M : Mask)
21504 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21505 getV4X86ShuffleImm8ForMask(Mask, DAG));
21507 // Check that the shuffles didn't cancel each other out. If not, we need to
21508 // combine to the new one.
21510 // Replace the combinable shuffle with the combined one, updating all users
21511 // so that we re-evaluate the chain here.
21512 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21517 /// \brief Try to combine x86 target specific shuffles.
21518 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21519 TargetLowering::DAGCombinerInfo &DCI,
21520 const X86Subtarget *Subtarget) {
21522 MVT VT = N.getSimpleValueType();
21523 SmallVector<int, 4> Mask;
21525 switch (N.getOpcode()) {
21526 case X86ISD::PSHUFD:
21527 case X86ISD::PSHUFLW:
21528 case X86ISD::PSHUFHW:
21529 Mask = getPSHUFShuffleMask(N);
21530 assert(Mask.size() == 4);
21536 // Nuke no-op shuffles that show up after combining.
21537 if (isNoopShuffleMask(Mask))
21538 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21540 // Look for simplifications involving one or two shuffle instructions.
21541 SDValue V = N.getOperand(0);
21542 switch (N.getOpcode()) {
21545 case X86ISD::PSHUFLW:
21546 case X86ISD::PSHUFHW:
21547 assert(VT == MVT::v8i16);
21550 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21551 return SDValue(); // We combined away this shuffle, so we're done.
21553 // See if this reduces to a PSHUFD which is no more expensive and can
21554 // combine with more operations. Note that it has to at least flip the
21555 // dwords as otherwise it would have been removed as a no-op.
21556 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21557 int DMask[] = {0, 1, 2, 3};
21558 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21559 DMask[DOffset + 0] = DOffset + 1;
21560 DMask[DOffset + 1] = DOffset + 0;
21561 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21562 DCI.AddToWorklist(V.getNode());
21563 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21564 getV4X86ShuffleImm8ForMask(DMask, DAG));
21565 DCI.AddToWorklist(V.getNode());
21566 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21569 // Look for shuffle patterns which can be implemented as a single unpack.
21570 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21571 // only works when we have a PSHUFD followed by two half-shuffles.
21572 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21573 (V.getOpcode() == X86ISD::PSHUFLW ||
21574 V.getOpcode() == X86ISD::PSHUFHW) &&
21575 V.getOpcode() != N.getOpcode() &&
21577 SDValue D = V.getOperand(0);
21578 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21579 D = D.getOperand(0);
21580 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21581 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21582 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21583 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21584 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21586 for (int i = 0; i < 4; ++i) {
21587 WordMask[i + NOffset] = Mask[i] + NOffset;
21588 WordMask[i + VOffset] = VMask[i] + VOffset;
21590 // Map the word mask through the DWord mask.
21592 for (int i = 0; i < 8; ++i)
21593 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21594 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21595 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21596 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21597 std::begin(UnpackLoMask)) ||
21598 std::equal(std::begin(MappedMask), std::end(MappedMask),
21599 std::begin(UnpackHiMask))) {
21600 // We can replace all three shuffles with an unpack.
21601 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21602 DCI.AddToWorklist(V.getNode());
21603 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21605 DL, MVT::v8i16, V, V);
21612 case X86ISD::PSHUFD:
21613 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21622 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21624 /// We combine this directly on the abstract vector shuffle nodes so it is
21625 /// easier to generically match. We also insert dummy vector shuffle nodes for
21626 /// the operands which explicitly discard the lanes which are unused by this
21627 /// operation to try to flow through the rest of the combiner the fact that
21628 /// they're unused.
21629 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21631 EVT VT = N->getValueType(0);
21633 // We only handle target-independent shuffles.
21634 // FIXME: It would be easy and harmless to use the target shuffle mask
21635 // extraction tool to support more.
21636 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21639 auto *SVN = cast<ShuffleVectorSDNode>(N);
21640 ArrayRef<int> Mask = SVN->getMask();
21641 SDValue V1 = N->getOperand(0);
21642 SDValue V2 = N->getOperand(1);
21644 // We require the first shuffle operand to be the SUB node, and the second to
21645 // be the ADD node.
21646 // FIXME: We should support the commuted patterns.
21647 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21650 // If there are other uses of these operations we can't fold them.
21651 if (!V1->hasOneUse() || !V2->hasOneUse())
21654 // Ensure that both operations have the same operands. Note that we can
21655 // commute the FADD operands.
21656 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21657 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21658 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21661 // We're looking for blends between FADD and FSUB nodes. We insist on these
21662 // nodes being lined up in a specific expected pattern.
21663 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21664 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21665 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21668 // Only specific types are legal at this point, assert so we notice if and
21669 // when these change.
21670 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21671 VT == MVT::v4f64) &&
21672 "Unknown vector type encountered!");
21674 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21677 /// PerformShuffleCombine - Performs several different shuffle combines.
21678 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21679 TargetLowering::DAGCombinerInfo &DCI,
21680 const X86Subtarget *Subtarget) {
21682 SDValue N0 = N->getOperand(0);
21683 SDValue N1 = N->getOperand(1);
21684 EVT VT = N->getValueType(0);
21686 // Don't create instructions with illegal types after legalize types has run.
21687 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21688 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21691 // If we have legalized the vector types, look for blends of FADD and FSUB
21692 // nodes that we can fuse into an ADDSUB node.
21693 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21694 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21697 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21698 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21699 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21700 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21702 // During Type Legalization, when promoting illegal vector types,
21703 // the backend might introduce new shuffle dag nodes and bitcasts.
21705 // This code performs the following transformation:
21706 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21707 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21709 // We do this only if both the bitcast and the BINOP dag nodes have
21710 // one use. Also, perform this transformation only if the new binary
21711 // operation is legal. This is to avoid introducing dag nodes that
21712 // potentially need to be further expanded (or custom lowered) into a
21713 // less optimal sequence of dag nodes.
21714 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21715 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21716 N0.getOpcode() == ISD::BITCAST) {
21717 SDValue BC0 = N0.getOperand(0);
21718 EVT SVT = BC0.getValueType();
21719 unsigned Opcode = BC0.getOpcode();
21720 unsigned NumElts = VT.getVectorNumElements();
21722 if (BC0.hasOneUse() && SVT.isVector() &&
21723 SVT.getVectorNumElements() * 2 == NumElts &&
21724 TLI.isOperationLegal(Opcode, VT)) {
21725 bool CanFold = false;
21737 unsigned SVTNumElts = SVT.getVectorNumElements();
21738 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21739 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21740 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21741 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21742 CanFold = SVOp->getMaskElt(i) < 0;
21745 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21746 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21747 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21748 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21753 // Only handle 128 wide vector from here on.
21754 if (!VT.is128BitVector())
21757 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21758 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21759 // consecutive, non-overlapping, and in the right order.
21760 SmallVector<SDValue, 16> Elts;
21761 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21762 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21764 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21768 if (isTargetShuffle(N->getOpcode())) {
21770 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21771 if (Shuffle.getNode())
21774 // Try recursively combining arbitrary sequences of x86 shuffle
21775 // instructions into higher-order shuffles. We do this after combining
21776 // specific PSHUF instruction sequences into their minimal form so that we
21777 // can evaluate how many specialized shuffle instructions are involved in
21778 // a particular chain.
21779 SmallVector<int, 1> NonceMask; // Just a placeholder.
21780 NonceMask.push_back(0);
21781 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21782 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21784 return SDValue(); // This routine will use CombineTo to replace N.
21790 /// PerformTruncateCombine - Converts truncate operation to
21791 /// a sequence of vector shuffle operations.
21792 /// It is possible when we truncate 256-bit vector to 128-bit vector
21793 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21794 TargetLowering::DAGCombinerInfo &DCI,
21795 const X86Subtarget *Subtarget) {
21799 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21800 /// specific shuffle of a load can be folded into a single element load.
21801 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21802 /// shuffles have been custom lowered so we need to handle those here.
21803 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21804 TargetLowering::DAGCombinerInfo &DCI) {
21805 if (DCI.isBeforeLegalizeOps())
21808 SDValue InVec = N->getOperand(0);
21809 SDValue EltNo = N->getOperand(1);
21811 if (!isa<ConstantSDNode>(EltNo))
21814 EVT OriginalVT = InVec.getValueType();
21816 if (InVec.getOpcode() == ISD::BITCAST) {
21817 // Don't duplicate a load with other uses.
21818 if (!InVec.hasOneUse())
21820 EVT BCVT = InVec.getOperand(0).getValueType();
21821 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21823 InVec = InVec.getOperand(0);
21826 EVT CurrentVT = InVec.getValueType();
21828 if (!isTargetShuffle(InVec.getOpcode()))
21831 // Don't duplicate a load with other uses.
21832 if (!InVec.hasOneUse())
21835 SmallVector<int, 16> ShuffleMask;
21837 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21838 ShuffleMask, UnaryShuffle))
21841 // Select the input vector, guarding against out of range extract vector.
21842 unsigned NumElems = CurrentVT.getVectorNumElements();
21843 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21844 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21845 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21846 : InVec.getOperand(1);
21848 // If inputs to shuffle are the same for both ops, then allow 2 uses
21849 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21851 if (LdNode.getOpcode() == ISD::BITCAST) {
21852 // Don't duplicate a load with other uses.
21853 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21856 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21857 LdNode = LdNode.getOperand(0);
21860 if (!ISD::isNormalLoad(LdNode.getNode()))
21863 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21865 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21868 EVT EltVT = N->getValueType(0);
21869 // If there's a bitcast before the shuffle, check if the load type and
21870 // alignment is valid.
21871 unsigned Align = LN0->getAlignment();
21872 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21873 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21874 EltVT.getTypeForEVT(*DAG.getContext()));
21876 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21879 // All checks match so transform back to vector_shuffle so that DAG combiner
21880 // can finish the job
21883 // Create shuffle node taking into account the case that its a unary shuffle
21884 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21885 : InVec.getOperand(1);
21886 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21887 InVec.getOperand(0), Shuffle,
21889 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
21890 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21894 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21895 /// generation and convert it from being a bunch of shuffles and extracts
21896 /// to a simple store and scalar loads to extract the elements.
21897 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21898 TargetLowering::DAGCombinerInfo &DCI) {
21899 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21900 if (NewOp.getNode())
21903 SDValue InputVector = N->getOperand(0);
21905 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21906 // from mmx to v2i32 has a single usage.
21907 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21908 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21909 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21910 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21911 N->getValueType(0),
21912 InputVector.getNode()->getOperand(0));
21914 // Only operate on vectors of 4 elements, where the alternative shuffling
21915 // gets to be more expensive.
21916 if (InputVector.getValueType() != MVT::v4i32)
21919 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21920 // single use which is a sign-extend or zero-extend, and all elements are
21922 SmallVector<SDNode *, 4> Uses;
21923 unsigned ExtractedElements = 0;
21924 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21925 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21926 if (UI.getUse().getResNo() != InputVector.getResNo())
21929 SDNode *Extract = *UI;
21930 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21933 if (Extract->getValueType(0) != MVT::i32)
21935 if (!Extract->hasOneUse())
21937 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21938 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21940 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21943 // Record which element was extracted.
21944 ExtractedElements |=
21945 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21947 Uses.push_back(Extract);
21950 // If not all the elements were used, this may not be worthwhile.
21951 if (ExtractedElements != 15)
21954 // Ok, we've now decided to do the transformation.
21955 SDLoc dl(InputVector);
21957 // Store the value to a temporary stack slot.
21958 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21959 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21960 MachinePointerInfo(), false, false, 0);
21962 // Replace each use (extract) with a load of the appropriate element.
21963 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21964 UE = Uses.end(); UI != UE; ++UI) {
21965 SDNode *Extract = *UI;
21967 // cOMpute the element's address.
21968 SDValue Idx = Extract->getOperand(1);
21970 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21971 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21973 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21975 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21976 StackPtr, OffsetVal);
21978 // Load the scalar.
21979 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21980 ScalarAddr, MachinePointerInfo(),
21981 false, false, false, 0);
21983 // Replace the exact with the load.
21984 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21987 // The replacement was made in place; don't return anything.
21991 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21992 static std::pair<unsigned, bool>
21993 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21994 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21995 if (!VT.isVector())
21996 return std::make_pair(0, false);
21998 bool NeedSplit = false;
21999 switch (VT.getSimpleVT().SimpleTy) {
22000 default: return std::make_pair(0, false);
22004 if (!Subtarget->hasAVX2())
22006 if (!Subtarget->hasAVX())
22007 return std::make_pair(0, false);
22012 if (!Subtarget->hasSSE2())
22013 return std::make_pair(0, false);
22016 // SSE2 has only a small subset of the operations.
22017 bool hasUnsigned = Subtarget->hasSSE41() ||
22018 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22019 bool hasSigned = Subtarget->hasSSE41() ||
22020 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22022 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22025 // Check for x CC y ? x : y.
22026 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22027 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22032 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22035 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22038 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22041 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22043 // Check for x CC y ? y : x -- a min/max with reversed arms.
22044 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22045 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22050 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22053 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22056 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22059 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22063 return std::make_pair(Opc, NeedSplit);
22067 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22068 const X86Subtarget *Subtarget) {
22070 SDValue Cond = N->getOperand(0);
22071 SDValue LHS = N->getOperand(1);
22072 SDValue RHS = N->getOperand(2);
22074 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22075 SDValue CondSrc = Cond->getOperand(0);
22076 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22077 Cond = CondSrc->getOperand(0);
22080 MVT VT = N->getSimpleValueType(0);
22081 MVT EltVT = VT.getVectorElementType();
22082 unsigned NumElems = VT.getVectorNumElements();
22083 // There is no blend with immediate in AVX-512.
22084 if (VT.is512BitVector())
22087 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22089 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22092 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22095 // A vselect where all conditions and data are constants can be optimized into
22096 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22097 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22098 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22101 unsigned MaskValue = 0;
22102 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22105 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22106 for (unsigned i = 0; i < NumElems; ++i) {
22107 // Be sure we emit undef where we can.
22108 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22109 ShuffleMask[i] = -1;
22111 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22114 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22117 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22119 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22120 TargetLowering::DAGCombinerInfo &DCI,
22121 const X86Subtarget *Subtarget) {
22123 SDValue Cond = N->getOperand(0);
22124 // Get the LHS/RHS of the select.
22125 SDValue LHS = N->getOperand(1);
22126 SDValue RHS = N->getOperand(2);
22127 EVT VT = LHS.getValueType();
22128 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22130 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22131 // instructions match the semantics of the common C idiom x<y?x:y but not
22132 // x<=y?x:y, because of how they handle negative zero (which can be
22133 // ignored in unsafe-math mode).
22134 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22135 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22136 (Subtarget->hasSSE2() ||
22137 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22138 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22140 unsigned Opcode = 0;
22141 // Check for x CC y ? x : y.
22142 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22143 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22147 // Converting this to a min would handle NaNs incorrectly, and swapping
22148 // the operands would cause it to handle comparisons between positive
22149 // and negative zero incorrectly.
22150 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22151 if (!DAG.getTarget().Options.UnsafeFPMath &&
22152 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22154 std::swap(LHS, RHS);
22156 Opcode = X86ISD::FMIN;
22159 // Converting this to a min would handle comparisons between positive
22160 // and negative zero incorrectly.
22161 if (!DAG.getTarget().Options.UnsafeFPMath &&
22162 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22164 Opcode = X86ISD::FMIN;
22167 // Converting this to a min would handle both negative zeros and NaNs
22168 // incorrectly, but we can swap the operands to fix both.
22169 std::swap(LHS, RHS);
22173 Opcode = X86ISD::FMIN;
22177 // Converting this to a max would handle comparisons between positive
22178 // and negative zero incorrectly.
22179 if (!DAG.getTarget().Options.UnsafeFPMath &&
22180 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22182 Opcode = X86ISD::FMAX;
22185 // Converting this to a max would handle NaNs incorrectly, and swapping
22186 // the operands would cause it to handle comparisons between positive
22187 // and negative zero incorrectly.
22188 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22189 if (!DAG.getTarget().Options.UnsafeFPMath &&
22190 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22192 std::swap(LHS, RHS);
22194 Opcode = X86ISD::FMAX;
22197 // Converting this to a max would handle both negative zeros and NaNs
22198 // incorrectly, but we can swap the operands to fix both.
22199 std::swap(LHS, RHS);
22203 Opcode = X86ISD::FMAX;
22206 // Check for x CC y ? y : x -- a min/max with reversed arms.
22207 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22208 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22212 // Converting this to a min would handle comparisons between positive
22213 // and negative zero incorrectly, and swapping the operands would
22214 // cause it to handle NaNs incorrectly.
22215 if (!DAG.getTarget().Options.UnsafeFPMath &&
22216 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22217 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22219 std::swap(LHS, RHS);
22221 Opcode = X86ISD::FMIN;
22224 // Converting this to a min would handle NaNs incorrectly.
22225 if (!DAG.getTarget().Options.UnsafeFPMath &&
22226 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22228 Opcode = X86ISD::FMIN;
22231 // Converting this to a min would handle both negative zeros and NaNs
22232 // incorrectly, but we can swap the operands to fix both.
22233 std::swap(LHS, RHS);
22237 Opcode = X86ISD::FMIN;
22241 // Converting this to a max would handle NaNs incorrectly.
22242 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22244 Opcode = X86ISD::FMAX;
22247 // Converting this to a max would handle comparisons between positive
22248 // and negative zero incorrectly, and swapping the operands would
22249 // cause it to handle NaNs incorrectly.
22250 if (!DAG.getTarget().Options.UnsafeFPMath &&
22251 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22252 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22254 std::swap(LHS, RHS);
22256 Opcode = X86ISD::FMAX;
22259 // Converting this to a max would handle both negative zeros and NaNs
22260 // incorrectly, but we can swap the operands to fix both.
22261 std::swap(LHS, RHS);
22265 Opcode = X86ISD::FMAX;
22271 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22274 EVT CondVT = Cond.getValueType();
22275 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22276 CondVT.getVectorElementType() == MVT::i1) {
22277 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22278 // lowering on KNL. In this case we convert it to
22279 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22280 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22281 // Since SKX these selects have a proper lowering.
22282 EVT OpVT = LHS.getValueType();
22283 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22284 (OpVT.getVectorElementType() == MVT::i8 ||
22285 OpVT.getVectorElementType() == MVT::i16) &&
22286 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22287 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22288 DCI.AddToWorklist(Cond.getNode());
22289 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22292 // If this is a select between two integer constants, try to do some
22294 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22295 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22296 // Don't do this for crazy integer types.
22297 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22298 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22299 // so that TrueC (the true value) is larger than FalseC.
22300 bool NeedsCondInvert = false;
22302 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22303 // Efficiently invertible.
22304 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22305 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22306 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22307 NeedsCondInvert = true;
22308 std::swap(TrueC, FalseC);
22311 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22312 if (FalseC->getAPIntValue() == 0 &&
22313 TrueC->getAPIntValue().isPowerOf2()) {
22314 if (NeedsCondInvert) // Invert the condition if needed.
22315 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22316 DAG.getConstant(1, Cond.getValueType()));
22318 // Zero extend the condition if needed.
22319 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22321 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22322 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22323 DAG.getConstant(ShAmt, MVT::i8));
22326 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22327 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22328 if (NeedsCondInvert) // Invert the condition if needed.
22329 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22330 DAG.getConstant(1, Cond.getValueType()));
22332 // Zero extend the condition if needed.
22333 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22334 FalseC->getValueType(0), Cond);
22335 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22336 SDValue(FalseC, 0));
22339 // Optimize cases that will turn into an LEA instruction. This requires
22340 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22341 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22342 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22343 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22345 bool isFastMultiplier = false;
22347 switch ((unsigned char)Diff) {
22349 case 1: // result = add base, cond
22350 case 2: // result = lea base( , cond*2)
22351 case 3: // result = lea base(cond, cond*2)
22352 case 4: // result = lea base( , cond*4)
22353 case 5: // result = lea base(cond, cond*4)
22354 case 8: // result = lea base( , cond*8)
22355 case 9: // result = lea base(cond, cond*8)
22356 isFastMultiplier = true;
22361 if (isFastMultiplier) {
22362 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22363 if (NeedsCondInvert) // Invert the condition if needed.
22364 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22365 DAG.getConstant(1, Cond.getValueType()));
22367 // Zero extend the condition if needed.
22368 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22370 // Scale the condition by the difference.
22372 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22373 DAG.getConstant(Diff, Cond.getValueType()));
22375 // Add the base if non-zero.
22376 if (FalseC->getAPIntValue() != 0)
22377 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22378 SDValue(FalseC, 0));
22385 // Canonicalize max and min:
22386 // (x > y) ? x : y -> (x >= y) ? x : y
22387 // (x < y) ? x : y -> (x <= y) ? x : y
22388 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22389 // the need for an extra compare
22390 // against zero. e.g.
22391 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22393 // testl %edi, %edi
22395 // cmovgl %edi, %eax
22399 // cmovsl %eax, %edi
22400 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22401 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22402 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22403 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22408 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22409 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22410 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22411 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22416 // Early exit check
22417 if (!TLI.isTypeLegal(VT))
22420 // Match VSELECTs into subs with unsigned saturation.
22421 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22422 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22423 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22424 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22425 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22427 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22428 // left side invert the predicate to simplify logic below.
22430 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22432 CC = ISD::getSetCCInverse(CC, true);
22433 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22437 if (Other.getNode() && Other->getNumOperands() == 2 &&
22438 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22439 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22440 SDValue CondRHS = Cond->getOperand(1);
22442 // Look for a general sub with unsigned saturation first.
22443 // x >= y ? x-y : 0 --> subus x, y
22444 // x > y ? x-y : 0 --> subus x, y
22445 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22446 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22447 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22449 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22450 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22451 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22452 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22453 // If the RHS is a constant we have to reverse the const
22454 // canonicalization.
22455 // x > C-1 ? x+-C : 0 --> subus x, C
22456 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22457 CondRHSConst->getAPIntValue() ==
22458 (-OpRHSConst->getAPIntValue() - 1))
22459 return DAG.getNode(
22460 X86ISD::SUBUS, DL, VT, OpLHS,
22461 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22463 // Another special case: If C was a sign bit, the sub has been
22464 // canonicalized into a xor.
22465 // FIXME: Would it be better to use computeKnownBits to determine
22466 // whether it's safe to decanonicalize the xor?
22467 // x s< 0 ? x^C : 0 --> subus x, C
22468 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22469 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22470 OpRHSConst->getAPIntValue().isSignBit())
22471 // Note that we have to rebuild the RHS constant here to ensure we
22472 // don't rely on particular values of undef lanes.
22473 return DAG.getNode(
22474 X86ISD::SUBUS, DL, VT, OpLHS,
22475 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22480 // Try to match a min/max vector operation.
22481 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22482 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22483 unsigned Opc = ret.first;
22484 bool NeedSplit = ret.second;
22486 if (Opc && NeedSplit) {
22487 unsigned NumElems = VT.getVectorNumElements();
22488 // Extract the LHS vectors
22489 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22490 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22492 // Extract the RHS vectors
22493 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22494 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22496 // Create min/max for each subvector
22497 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22498 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22500 // Merge the result
22501 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22503 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22506 // Simplify vector selection if condition value type matches vselect
22508 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22509 assert(Cond.getValueType().isVector() &&
22510 "vector select expects a vector selector!");
22512 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22513 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22515 // Try invert the condition if true value is not all 1s and false value
22517 if (!TValIsAllOnes && !FValIsAllZeros &&
22518 // Check if the selector will be produced by CMPP*/PCMP*
22519 Cond.getOpcode() == ISD::SETCC &&
22520 // Check if SETCC has already been promoted
22521 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22522 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22523 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22525 if (TValIsAllZeros || FValIsAllOnes) {
22526 SDValue CC = Cond.getOperand(2);
22527 ISD::CondCode NewCC =
22528 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22529 Cond.getOperand(0).getValueType().isInteger());
22530 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22531 std::swap(LHS, RHS);
22532 TValIsAllOnes = FValIsAllOnes;
22533 FValIsAllZeros = TValIsAllZeros;
22537 if (TValIsAllOnes || FValIsAllZeros) {
22540 if (TValIsAllOnes && FValIsAllZeros)
22542 else if (TValIsAllOnes)
22543 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22544 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22545 else if (FValIsAllZeros)
22546 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22547 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22549 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22553 // Try to fold this VSELECT into a MOVSS/MOVSD
22554 if (N->getOpcode() == ISD::VSELECT &&
22555 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22556 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22557 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22558 bool CanFold = false;
22559 unsigned NumElems = Cond.getNumOperands();
22563 if (isZero(Cond.getOperand(0))) {
22566 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22567 // fold (vselect <0,-1> -> (movsd A, B)
22568 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22569 CanFold = isAllOnes(Cond.getOperand(i));
22570 } else if (isAllOnes(Cond.getOperand(0))) {
22574 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22575 // fold (vselect <-1,0> -> (movsd B, A)
22576 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22577 CanFold = isZero(Cond.getOperand(i));
22581 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22582 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22583 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22586 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22587 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22588 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22589 // (v2i64 (bitcast B)))))
22591 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22592 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22593 // (v2f64 (bitcast B)))))
22595 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22596 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22597 // (v2i64 (bitcast A)))))
22599 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22600 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22601 // (v2f64 (bitcast A)))))
22603 CanFold = (isZero(Cond.getOperand(0)) &&
22604 isZero(Cond.getOperand(1)) &&
22605 isAllOnes(Cond.getOperand(2)) &&
22606 isAllOnes(Cond.getOperand(3)));
22608 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22609 isAllOnes(Cond.getOperand(1)) &&
22610 isZero(Cond.getOperand(2)) &&
22611 isZero(Cond.getOperand(3))) {
22613 std::swap(LHS, RHS);
22617 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22618 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22619 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22620 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22622 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22628 // If we know that this node is legal then we know that it is going to be
22629 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22630 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22631 // to simplify previous instructions.
22632 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22633 !DCI.isBeforeLegalize() &&
22634 // We explicitly check against v8i16 and v16i16 because, although
22635 // they're marked as Custom, they might only be legal when Cond is a
22636 // build_vector of constants. This will be taken care in a later
22638 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22639 VT != MVT::v8i16) &&
22640 // Don't optimize vector of constants. Those are handled by
22641 // the generic code and all the bits must be properly set for
22642 // the generic optimizer.
22643 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22644 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22646 // Don't optimize vector selects that map to mask-registers.
22650 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22651 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22653 APInt KnownZero, KnownOne;
22654 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22655 DCI.isBeforeLegalizeOps());
22656 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22657 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22659 // If we changed the computation somewhere in the DAG, this change
22660 // will affect all users of Cond.
22661 // Make sure it is fine and update all the nodes so that we do not
22662 // use the generic VSELECT anymore. Otherwise, we may perform
22663 // wrong optimizations as we messed up with the actual expectation
22664 // for the vector boolean values.
22665 if (Cond != TLO.Old) {
22666 // Check all uses of that condition operand to check whether it will be
22667 // consumed by non-BLEND instructions, which may depend on all bits are
22669 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22671 if (I->getOpcode() != ISD::VSELECT)
22672 // TODO: Add other opcodes eventually lowered into BLEND.
22675 // Update all the users of the condition, before committing the change,
22676 // so that the VSELECT optimizations that expect the correct vector
22677 // boolean value will not be triggered.
22678 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22680 DAG.ReplaceAllUsesOfValueWith(
22682 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22683 Cond, I->getOperand(1), I->getOperand(2)));
22684 DCI.CommitTargetLoweringOpt(TLO);
22687 // At this point, only Cond is changed. Change the condition
22688 // just for N to keep the opportunity to optimize all other
22689 // users their own way.
22690 DAG.ReplaceAllUsesOfValueWith(
22692 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22693 TLO.New, N->getOperand(1), N->getOperand(2)));
22698 // We should generate an X86ISD::BLENDI from a vselect if its argument
22699 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22700 // constants. This specific pattern gets generated when we split a
22701 // selector for a 512 bit vector in a machine without AVX512 (but with
22702 // 256-bit vectors), during legalization:
22704 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22706 // Iff we find this pattern and the build_vectors are built from
22707 // constants, we translate the vselect into a shuffle_vector that we
22708 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22709 if ((N->getOpcode() == ISD::VSELECT ||
22710 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22711 !DCI.isBeforeLegalize()) {
22712 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22713 if (Shuffle.getNode())
22720 // Check whether a boolean test is testing a boolean value generated by
22721 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22724 // Simplify the following patterns:
22725 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22726 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22727 // to (Op EFLAGS Cond)
22729 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22730 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22731 // to (Op EFLAGS !Cond)
22733 // where Op could be BRCOND or CMOV.
22735 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22736 // Quit if not CMP and SUB with its value result used.
22737 if (Cmp.getOpcode() != X86ISD::CMP &&
22738 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22741 // Quit if not used as a boolean value.
22742 if (CC != X86::COND_E && CC != X86::COND_NE)
22745 // Check CMP operands. One of them should be 0 or 1 and the other should be
22746 // an SetCC or extended from it.
22747 SDValue Op1 = Cmp.getOperand(0);
22748 SDValue Op2 = Cmp.getOperand(1);
22751 const ConstantSDNode* C = nullptr;
22752 bool needOppositeCond = (CC == X86::COND_E);
22753 bool checkAgainstTrue = false; // Is it a comparison against 1?
22755 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22757 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22759 else // Quit if all operands are not constants.
22762 if (C->getZExtValue() == 1) {
22763 needOppositeCond = !needOppositeCond;
22764 checkAgainstTrue = true;
22765 } else if (C->getZExtValue() != 0)
22766 // Quit if the constant is neither 0 or 1.
22769 bool truncatedToBoolWithAnd = false;
22770 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22771 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22772 SetCC.getOpcode() == ISD::TRUNCATE ||
22773 SetCC.getOpcode() == ISD::AND) {
22774 if (SetCC.getOpcode() == ISD::AND) {
22776 ConstantSDNode *CS;
22777 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22778 CS->getZExtValue() == 1)
22780 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22781 CS->getZExtValue() == 1)
22785 SetCC = SetCC.getOperand(OpIdx);
22786 truncatedToBoolWithAnd = true;
22788 SetCC = SetCC.getOperand(0);
22791 switch (SetCC.getOpcode()) {
22792 case X86ISD::SETCC_CARRY:
22793 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22794 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22795 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22796 // truncated to i1 using 'and'.
22797 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22799 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22800 "Invalid use of SETCC_CARRY!");
22802 case X86ISD::SETCC:
22803 // Set the condition code or opposite one if necessary.
22804 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22805 if (needOppositeCond)
22806 CC = X86::GetOppositeBranchCondition(CC);
22807 return SetCC.getOperand(1);
22808 case X86ISD::CMOV: {
22809 // Check whether false/true value has canonical one, i.e. 0 or 1.
22810 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22811 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22812 // Quit if true value is not a constant.
22815 // Quit if false value is not a constant.
22817 SDValue Op = SetCC.getOperand(0);
22818 // Skip 'zext' or 'trunc' node.
22819 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22820 Op.getOpcode() == ISD::TRUNCATE)
22821 Op = Op.getOperand(0);
22822 // A special case for rdrand/rdseed, where 0 is set if false cond is
22824 if ((Op.getOpcode() != X86ISD::RDRAND &&
22825 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22828 // Quit if false value is not the constant 0 or 1.
22829 bool FValIsFalse = true;
22830 if (FVal && FVal->getZExtValue() != 0) {
22831 if (FVal->getZExtValue() != 1)
22833 // If FVal is 1, opposite cond is needed.
22834 needOppositeCond = !needOppositeCond;
22835 FValIsFalse = false;
22837 // Quit if TVal is not the constant opposite of FVal.
22838 if (FValIsFalse && TVal->getZExtValue() != 1)
22840 if (!FValIsFalse && TVal->getZExtValue() != 0)
22842 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22843 if (needOppositeCond)
22844 CC = X86::GetOppositeBranchCondition(CC);
22845 return SetCC.getOperand(3);
22852 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22853 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22854 TargetLowering::DAGCombinerInfo &DCI,
22855 const X86Subtarget *Subtarget) {
22858 // If the flag operand isn't dead, don't touch this CMOV.
22859 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22862 SDValue FalseOp = N->getOperand(0);
22863 SDValue TrueOp = N->getOperand(1);
22864 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22865 SDValue Cond = N->getOperand(3);
22867 if (CC == X86::COND_E || CC == X86::COND_NE) {
22868 switch (Cond.getOpcode()) {
22872 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22873 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22874 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22880 Flags = checkBoolTestSetCCCombine(Cond, CC);
22881 if (Flags.getNode() &&
22882 // Extra check as FCMOV only supports a subset of X86 cond.
22883 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22884 SDValue Ops[] = { FalseOp, TrueOp,
22885 DAG.getConstant(CC, MVT::i8), Flags };
22886 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22889 // If this is a select between two integer constants, try to do some
22890 // optimizations. Note that the operands are ordered the opposite of SELECT
22892 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22893 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22894 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22895 // larger than FalseC (the false value).
22896 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22897 CC = X86::GetOppositeBranchCondition(CC);
22898 std::swap(TrueC, FalseC);
22899 std::swap(TrueOp, FalseOp);
22902 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22903 // This is efficient for any integer data type (including i8/i16) and
22905 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22906 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22907 DAG.getConstant(CC, MVT::i8), Cond);
22909 // Zero extend the condition if needed.
22910 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22912 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22913 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22914 DAG.getConstant(ShAmt, MVT::i8));
22915 if (N->getNumValues() == 2) // Dead flag value?
22916 return DCI.CombineTo(N, Cond, SDValue());
22920 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22921 // for any integer data type, including i8/i16.
22922 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22923 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22924 DAG.getConstant(CC, MVT::i8), Cond);
22926 // Zero extend the condition if needed.
22927 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22928 FalseC->getValueType(0), Cond);
22929 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22930 SDValue(FalseC, 0));
22932 if (N->getNumValues() == 2) // Dead flag value?
22933 return DCI.CombineTo(N, Cond, SDValue());
22937 // Optimize cases that will turn into an LEA instruction. This requires
22938 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22939 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22940 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22941 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22943 bool isFastMultiplier = false;
22945 switch ((unsigned char)Diff) {
22947 case 1: // result = add base, cond
22948 case 2: // result = lea base( , cond*2)
22949 case 3: // result = lea base(cond, cond*2)
22950 case 4: // result = lea base( , cond*4)
22951 case 5: // result = lea base(cond, cond*4)
22952 case 8: // result = lea base( , cond*8)
22953 case 9: // result = lea base(cond, cond*8)
22954 isFastMultiplier = true;
22959 if (isFastMultiplier) {
22960 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22961 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22962 DAG.getConstant(CC, MVT::i8), Cond);
22963 // Zero extend the condition if needed.
22964 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22966 // Scale the condition by the difference.
22968 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22969 DAG.getConstant(Diff, Cond.getValueType()));
22971 // Add the base if non-zero.
22972 if (FalseC->getAPIntValue() != 0)
22973 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22974 SDValue(FalseC, 0));
22975 if (N->getNumValues() == 2) // Dead flag value?
22976 return DCI.CombineTo(N, Cond, SDValue());
22983 // Handle these cases:
22984 // (select (x != c), e, c) -> select (x != c), e, x),
22985 // (select (x == c), c, e) -> select (x == c), x, e)
22986 // where the c is an integer constant, and the "select" is the combination
22987 // of CMOV and CMP.
22989 // The rationale for this change is that the conditional-move from a constant
22990 // needs two instructions, however, conditional-move from a register needs
22991 // only one instruction.
22993 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22994 // some instruction-combining opportunities. This opt needs to be
22995 // postponed as late as possible.
22997 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22998 // the DCI.xxxx conditions are provided to postpone the optimization as
22999 // late as possible.
23001 ConstantSDNode *CmpAgainst = nullptr;
23002 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23003 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23004 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23006 if (CC == X86::COND_NE &&
23007 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23008 CC = X86::GetOppositeBranchCondition(CC);
23009 std::swap(TrueOp, FalseOp);
23012 if (CC == X86::COND_E &&
23013 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23014 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23015 DAG.getConstant(CC, MVT::i8), Cond };
23016 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23024 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23025 const X86Subtarget *Subtarget) {
23026 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23028 default: return SDValue();
23029 // SSE/AVX/AVX2 blend intrinsics.
23030 case Intrinsic::x86_avx2_pblendvb:
23031 case Intrinsic::x86_avx2_pblendw:
23032 case Intrinsic::x86_avx2_pblendd_128:
23033 case Intrinsic::x86_avx2_pblendd_256:
23034 // Don't try to simplify this intrinsic if we don't have AVX2.
23035 if (!Subtarget->hasAVX2())
23038 case Intrinsic::x86_avx_blend_pd_256:
23039 case Intrinsic::x86_avx_blend_ps_256:
23040 case Intrinsic::x86_avx_blendv_pd_256:
23041 case Intrinsic::x86_avx_blendv_ps_256:
23042 // Don't try to simplify this intrinsic if we don't have AVX.
23043 if (!Subtarget->hasAVX())
23046 case Intrinsic::x86_sse41_pblendw:
23047 case Intrinsic::x86_sse41_blendpd:
23048 case Intrinsic::x86_sse41_blendps:
23049 case Intrinsic::x86_sse41_blendvps:
23050 case Intrinsic::x86_sse41_blendvpd:
23051 case Intrinsic::x86_sse41_pblendvb: {
23052 SDValue Op0 = N->getOperand(1);
23053 SDValue Op1 = N->getOperand(2);
23054 SDValue Mask = N->getOperand(3);
23056 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23057 if (!Subtarget->hasSSE41())
23060 // fold (blend A, A, Mask) -> A
23063 // fold (blend A, B, allZeros) -> A
23064 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23066 // fold (blend A, B, allOnes) -> B
23067 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23070 // Simplify the case where the mask is a constant i32 value.
23071 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23072 if (C->isNullValue())
23074 if (C->isAllOnesValue())
23081 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23082 case Intrinsic::x86_sse2_psrai_w:
23083 case Intrinsic::x86_sse2_psrai_d:
23084 case Intrinsic::x86_avx2_psrai_w:
23085 case Intrinsic::x86_avx2_psrai_d:
23086 case Intrinsic::x86_sse2_psra_w:
23087 case Intrinsic::x86_sse2_psra_d:
23088 case Intrinsic::x86_avx2_psra_w:
23089 case Intrinsic::x86_avx2_psra_d: {
23090 SDValue Op0 = N->getOperand(1);
23091 SDValue Op1 = N->getOperand(2);
23092 EVT VT = Op0.getValueType();
23093 assert(VT.isVector() && "Expected a vector type!");
23095 if (isa<BuildVectorSDNode>(Op1))
23096 Op1 = Op1.getOperand(0);
23098 if (!isa<ConstantSDNode>(Op1))
23101 EVT SVT = VT.getVectorElementType();
23102 unsigned SVTBits = SVT.getSizeInBits();
23104 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23105 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23106 uint64_t ShAmt = C.getZExtValue();
23108 // Don't try to convert this shift into a ISD::SRA if the shift
23109 // count is bigger than or equal to the element size.
23110 if (ShAmt >= SVTBits)
23113 // Trivial case: if the shift count is zero, then fold this
23114 // into the first operand.
23118 // Replace this packed shift intrinsic with a target independent
23120 SDValue Splat = DAG.getConstant(C, VT);
23121 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23126 /// PerformMulCombine - Optimize a single multiply with constant into two
23127 /// in order to implement it with two cheaper instructions, e.g.
23128 /// LEA + SHL, LEA + LEA.
23129 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23130 TargetLowering::DAGCombinerInfo &DCI) {
23131 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23134 EVT VT = N->getValueType(0);
23135 if (VT != MVT::i64)
23138 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23141 uint64_t MulAmt = C->getZExtValue();
23142 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23145 uint64_t MulAmt1 = 0;
23146 uint64_t MulAmt2 = 0;
23147 if ((MulAmt % 9) == 0) {
23149 MulAmt2 = MulAmt / 9;
23150 } else if ((MulAmt % 5) == 0) {
23152 MulAmt2 = MulAmt / 5;
23153 } else if ((MulAmt % 3) == 0) {
23155 MulAmt2 = MulAmt / 3;
23158 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23161 if (isPowerOf2_64(MulAmt2) &&
23162 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23163 // If second multiplifer is pow2, issue it first. We want the multiply by
23164 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23166 std::swap(MulAmt1, MulAmt2);
23169 if (isPowerOf2_64(MulAmt1))
23170 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23171 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23173 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23174 DAG.getConstant(MulAmt1, VT));
23176 if (isPowerOf2_64(MulAmt2))
23177 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23178 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23180 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23181 DAG.getConstant(MulAmt2, VT));
23183 // Do not add new nodes to DAG combiner worklist.
23184 DCI.CombineTo(N, NewMul, false);
23189 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23190 SDValue N0 = N->getOperand(0);
23191 SDValue N1 = N->getOperand(1);
23192 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23193 EVT VT = N0.getValueType();
23195 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23196 // since the result of setcc_c is all zero's or all ones.
23197 if (VT.isInteger() && !VT.isVector() &&
23198 N1C && N0.getOpcode() == ISD::AND &&
23199 N0.getOperand(1).getOpcode() == ISD::Constant) {
23200 SDValue N00 = N0.getOperand(0);
23201 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23202 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23203 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23204 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23205 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23206 APInt ShAmt = N1C->getAPIntValue();
23207 Mask = Mask.shl(ShAmt);
23209 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23210 N00, DAG.getConstant(Mask, VT));
23214 // Hardware support for vector shifts is sparse which makes us scalarize the
23215 // vector operations in many cases. Also, on sandybridge ADD is faster than
23217 // (shl V, 1) -> add V,V
23218 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23219 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23220 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23221 // We shift all of the values by one. In many cases we do not have
23222 // hardware support for this operation. This is better expressed as an ADD
23224 if (N1SplatC->getZExtValue() == 1)
23225 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23231 /// \brief Returns a vector of 0s if the node in input is a vector logical
23232 /// shift by a constant amount which is known to be bigger than or equal
23233 /// to the vector element size in bits.
23234 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23235 const X86Subtarget *Subtarget) {
23236 EVT VT = N->getValueType(0);
23238 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23239 (!Subtarget->hasInt256() ||
23240 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23243 SDValue Amt = N->getOperand(1);
23245 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23246 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23247 APInt ShiftAmt = AmtSplat->getAPIntValue();
23248 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23250 // SSE2/AVX2 logical shifts always return a vector of 0s
23251 // if the shift amount is bigger than or equal to
23252 // the element size. The constant shift amount will be
23253 // encoded as a 8-bit immediate.
23254 if (ShiftAmt.trunc(8).uge(MaxAmount))
23255 return getZeroVector(VT, Subtarget, DAG, DL);
23261 /// PerformShiftCombine - Combine shifts.
23262 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23263 TargetLowering::DAGCombinerInfo &DCI,
23264 const X86Subtarget *Subtarget) {
23265 if (N->getOpcode() == ISD::SHL) {
23266 SDValue V = PerformSHLCombine(N, DAG);
23267 if (V.getNode()) return V;
23270 if (N->getOpcode() != ISD::SRA) {
23271 // Try to fold this logical shift into a zero vector.
23272 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23273 if (V.getNode()) return V;
23279 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23280 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23281 // and friends. Likewise for OR -> CMPNEQSS.
23282 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23283 TargetLowering::DAGCombinerInfo &DCI,
23284 const X86Subtarget *Subtarget) {
23287 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23288 // we're requiring SSE2 for both.
23289 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23290 SDValue N0 = N->getOperand(0);
23291 SDValue N1 = N->getOperand(1);
23292 SDValue CMP0 = N0->getOperand(1);
23293 SDValue CMP1 = N1->getOperand(1);
23296 // The SETCCs should both refer to the same CMP.
23297 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23300 SDValue CMP00 = CMP0->getOperand(0);
23301 SDValue CMP01 = CMP0->getOperand(1);
23302 EVT VT = CMP00.getValueType();
23304 if (VT == MVT::f32 || VT == MVT::f64) {
23305 bool ExpectingFlags = false;
23306 // Check for any users that want flags:
23307 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23308 !ExpectingFlags && UI != UE; ++UI)
23309 switch (UI->getOpcode()) {
23314 ExpectingFlags = true;
23316 case ISD::CopyToReg:
23317 case ISD::SIGN_EXTEND:
23318 case ISD::ZERO_EXTEND:
23319 case ISD::ANY_EXTEND:
23323 if (!ExpectingFlags) {
23324 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23325 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23327 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23328 X86::CondCode tmp = cc0;
23333 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23334 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23335 // FIXME: need symbolic constants for these magic numbers.
23336 // See X86ATTInstPrinter.cpp:printSSECC().
23337 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23338 if (Subtarget->hasAVX512()) {
23339 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23340 CMP01, DAG.getConstant(x86cc, MVT::i8));
23341 if (N->getValueType(0) != MVT::i1)
23342 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23346 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23347 CMP00.getValueType(), CMP00, CMP01,
23348 DAG.getConstant(x86cc, MVT::i8));
23350 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23351 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23353 if (is64BitFP && !Subtarget->is64Bit()) {
23354 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23355 // 64-bit integer, since that's not a legal type. Since
23356 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23357 // bits, but can do this little dance to extract the lowest 32 bits
23358 // and work with those going forward.
23359 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23361 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23363 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23364 Vector32, DAG.getIntPtrConstant(0));
23368 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23369 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23370 DAG.getConstant(1, IntVT));
23371 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23372 return OneBitOfTruth;
23380 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23381 /// so it can be folded inside ANDNP.
23382 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23383 EVT VT = N->getValueType(0);
23385 // Match direct AllOnes for 128 and 256-bit vectors
23386 if (ISD::isBuildVectorAllOnes(N))
23389 // Look through a bit convert.
23390 if (N->getOpcode() == ISD::BITCAST)
23391 N = N->getOperand(0).getNode();
23393 // Sometimes the operand may come from a insert_subvector building a 256-bit
23395 if (VT.is256BitVector() &&
23396 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23397 SDValue V1 = N->getOperand(0);
23398 SDValue V2 = N->getOperand(1);
23400 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23401 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23402 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23403 ISD::isBuildVectorAllOnes(V2.getNode()))
23410 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23411 // register. In most cases we actually compare or select YMM-sized registers
23412 // and mixing the two types creates horrible code. This method optimizes
23413 // some of the transition sequences.
23414 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23415 TargetLowering::DAGCombinerInfo &DCI,
23416 const X86Subtarget *Subtarget) {
23417 EVT VT = N->getValueType(0);
23418 if (!VT.is256BitVector())
23421 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23422 N->getOpcode() == ISD::ZERO_EXTEND ||
23423 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23425 SDValue Narrow = N->getOperand(0);
23426 EVT NarrowVT = Narrow->getValueType(0);
23427 if (!NarrowVT.is128BitVector())
23430 if (Narrow->getOpcode() != ISD::XOR &&
23431 Narrow->getOpcode() != ISD::AND &&
23432 Narrow->getOpcode() != ISD::OR)
23435 SDValue N0 = Narrow->getOperand(0);
23436 SDValue N1 = Narrow->getOperand(1);
23439 // The Left side has to be a trunc.
23440 if (N0.getOpcode() != ISD::TRUNCATE)
23443 // The type of the truncated inputs.
23444 EVT WideVT = N0->getOperand(0)->getValueType(0);
23448 // The right side has to be a 'trunc' or a constant vector.
23449 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23450 ConstantSDNode *RHSConstSplat = nullptr;
23451 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23452 RHSConstSplat = RHSBV->getConstantSplatNode();
23453 if (!RHSTrunc && !RHSConstSplat)
23456 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23458 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23461 // Set N0 and N1 to hold the inputs to the new wide operation.
23462 N0 = N0->getOperand(0);
23463 if (RHSConstSplat) {
23464 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23465 SDValue(RHSConstSplat, 0));
23466 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23467 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23468 } else if (RHSTrunc) {
23469 N1 = N1->getOperand(0);
23472 // Generate the wide operation.
23473 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23474 unsigned Opcode = N->getOpcode();
23476 case ISD::ANY_EXTEND:
23478 case ISD::ZERO_EXTEND: {
23479 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23480 APInt Mask = APInt::getAllOnesValue(InBits);
23481 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23482 return DAG.getNode(ISD::AND, DL, VT,
23483 Op, DAG.getConstant(Mask, VT));
23485 case ISD::SIGN_EXTEND:
23486 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23487 Op, DAG.getValueType(NarrowVT));
23489 llvm_unreachable("Unexpected opcode");
23493 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23494 TargetLowering::DAGCombinerInfo &DCI,
23495 const X86Subtarget *Subtarget) {
23496 EVT VT = N->getValueType(0);
23497 if (DCI.isBeforeLegalizeOps())
23500 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23504 // Create BEXTR instructions
23505 // BEXTR is ((X >> imm) & (2**size-1))
23506 if (VT == MVT::i32 || VT == MVT::i64) {
23507 SDValue N0 = N->getOperand(0);
23508 SDValue N1 = N->getOperand(1);
23511 // Check for BEXTR.
23512 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23513 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23514 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23515 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23516 if (MaskNode && ShiftNode) {
23517 uint64_t Mask = MaskNode->getZExtValue();
23518 uint64_t Shift = ShiftNode->getZExtValue();
23519 if (isMask_64(Mask)) {
23520 uint64_t MaskSize = CountPopulation_64(Mask);
23521 if (Shift + MaskSize <= VT.getSizeInBits())
23522 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23523 DAG.getConstant(Shift | (MaskSize << 8), VT));
23531 // Want to form ANDNP nodes:
23532 // 1) In the hopes of then easily combining them with OR and AND nodes
23533 // to form PBLEND/PSIGN.
23534 // 2) To match ANDN packed intrinsics
23535 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23538 SDValue N0 = N->getOperand(0);
23539 SDValue N1 = N->getOperand(1);
23542 // Check LHS for vnot
23543 if (N0.getOpcode() == ISD::XOR &&
23544 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23545 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23546 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23548 // Check RHS for vnot
23549 if (N1.getOpcode() == ISD::XOR &&
23550 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23551 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23552 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23557 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23558 TargetLowering::DAGCombinerInfo &DCI,
23559 const X86Subtarget *Subtarget) {
23560 if (DCI.isBeforeLegalizeOps())
23563 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23567 SDValue N0 = N->getOperand(0);
23568 SDValue N1 = N->getOperand(1);
23569 EVT VT = N->getValueType(0);
23571 // look for psign/blend
23572 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23573 if (!Subtarget->hasSSSE3() ||
23574 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23577 // Canonicalize pandn to RHS
23578 if (N0.getOpcode() == X86ISD::ANDNP)
23580 // or (and (m, y), (pandn m, x))
23581 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23582 SDValue Mask = N1.getOperand(0);
23583 SDValue X = N1.getOperand(1);
23585 if (N0.getOperand(0) == Mask)
23586 Y = N0.getOperand(1);
23587 if (N0.getOperand(1) == Mask)
23588 Y = N0.getOperand(0);
23590 // Check to see if the mask appeared in both the AND and ANDNP and
23594 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23595 // Look through mask bitcast.
23596 if (Mask.getOpcode() == ISD::BITCAST)
23597 Mask = Mask.getOperand(0);
23598 if (X.getOpcode() == ISD::BITCAST)
23599 X = X.getOperand(0);
23600 if (Y.getOpcode() == ISD::BITCAST)
23601 Y = Y.getOperand(0);
23603 EVT MaskVT = Mask.getValueType();
23605 // Validate that the Mask operand is a vector sra node.
23606 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23607 // there is no psrai.b
23608 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23609 unsigned SraAmt = ~0;
23610 if (Mask.getOpcode() == ISD::SRA) {
23611 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23612 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23613 SraAmt = AmtConst->getZExtValue();
23614 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23615 SDValue SraC = Mask.getOperand(1);
23616 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23618 if ((SraAmt + 1) != EltBits)
23623 // Now we know we at least have a plendvb with the mask val. See if
23624 // we can form a psignb/w/d.
23625 // psign = x.type == y.type == mask.type && y = sub(0, x);
23626 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23627 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23628 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23629 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23630 "Unsupported VT for PSIGN");
23631 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23632 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23634 // PBLENDVB only available on SSE 4.1
23635 if (!Subtarget->hasSSE41())
23638 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23640 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23641 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23642 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23643 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23644 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23648 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23651 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23652 MachineFunction &MF = DAG.getMachineFunction();
23653 bool OptForSize = MF.getFunction()->getAttributes().
23654 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23656 // SHLD/SHRD instructions have lower register pressure, but on some
23657 // platforms they have higher latency than the equivalent
23658 // series of shifts/or that would otherwise be generated.
23659 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23660 // have higher latencies and we are not optimizing for size.
23661 if (!OptForSize && Subtarget->isSHLDSlow())
23664 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23666 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23668 if (!N0.hasOneUse() || !N1.hasOneUse())
23671 SDValue ShAmt0 = N0.getOperand(1);
23672 if (ShAmt0.getValueType() != MVT::i8)
23674 SDValue ShAmt1 = N1.getOperand(1);
23675 if (ShAmt1.getValueType() != MVT::i8)
23677 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23678 ShAmt0 = ShAmt0.getOperand(0);
23679 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23680 ShAmt1 = ShAmt1.getOperand(0);
23683 unsigned Opc = X86ISD::SHLD;
23684 SDValue Op0 = N0.getOperand(0);
23685 SDValue Op1 = N1.getOperand(0);
23686 if (ShAmt0.getOpcode() == ISD::SUB) {
23687 Opc = X86ISD::SHRD;
23688 std::swap(Op0, Op1);
23689 std::swap(ShAmt0, ShAmt1);
23692 unsigned Bits = VT.getSizeInBits();
23693 if (ShAmt1.getOpcode() == ISD::SUB) {
23694 SDValue Sum = ShAmt1.getOperand(0);
23695 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23696 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23697 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23698 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23699 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23700 return DAG.getNode(Opc, DL, VT,
23702 DAG.getNode(ISD::TRUNCATE, DL,
23705 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23706 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23708 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23709 return DAG.getNode(Opc, DL, VT,
23710 N0.getOperand(0), N1.getOperand(0),
23711 DAG.getNode(ISD::TRUNCATE, DL,
23718 // Generate NEG and CMOV for integer abs.
23719 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23720 EVT VT = N->getValueType(0);
23722 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23723 // 8-bit integer abs to NEG and CMOV.
23724 if (VT.isInteger() && VT.getSizeInBits() == 8)
23727 SDValue N0 = N->getOperand(0);
23728 SDValue N1 = N->getOperand(1);
23731 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23732 // and change it to SUB and CMOV.
23733 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23734 N0.getOpcode() == ISD::ADD &&
23735 N0.getOperand(1) == N1 &&
23736 N1.getOpcode() == ISD::SRA &&
23737 N1.getOperand(0) == N0.getOperand(0))
23738 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23739 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23740 // Generate SUB & CMOV.
23741 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23742 DAG.getConstant(0, VT), N0.getOperand(0));
23744 SDValue Ops[] = { N0.getOperand(0), Neg,
23745 DAG.getConstant(X86::COND_GE, MVT::i8),
23746 SDValue(Neg.getNode(), 1) };
23747 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23752 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23753 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23754 TargetLowering::DAGCombinerInfo &DCI,
23755 const X86Subtarget *Subtarget) {
23756 if (DCI.isBeforeLegalizeOps())
23759 if (Subtarget->hasCMov()) {
23760 SDValue RV = performIntegerAbsCombine(N, DAG);
23768 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23769 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23770 TargetLowering::DAGCombinerInfo &DCI,
23771 const X86Subtarget *Subtarget) {
23772 LoadSDNode *Ld = cast<LoadSDNode>(N);
23773 EVT RegVT = Ld->getValueType(0);
23774 EVT MemVT = Ld->getMemoryVT();
23776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23778 // On Sandybridge unaligned 256bit loads are inefficient.
23779 ISD::LoadExtType Ext = Ld->getExtensionType();
23780 unsigned Alignment = Ld->getAlignment();
23781 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23782 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23783 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23784 unsigned NumElems = RegVT.getVectorNumElements();
23788 SDValue Ptr = Ld->getBasePtr();
23789 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23791 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23793 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23794 Ld->getPointerInfo(), Ld->isVolatile(),
23795 Ld->isNonTemporal(), Ld->isInvariant(),
23797 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23798 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23799 Ld->getPointerInfo(), Ld->isVolatile(),
23800 Ld->isNonTemporal(), Ld->isInvariant(),
23801 std::min(16U, Alignment));
23802 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23804 Load2.getValue(1));
23806 SDValue NewVec = DAG.getUNDEF(RegVT);
23807 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23808 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23809 return DCI.CombineTo(N, NewVec, TF, true);
23815 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23816 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23817 const X86Subtarget *Subtarget) {
23818 StoreSDNode *St = cast<StoreSDNode>(N);
23819 EVT VT = St->getValue().getValueType();
23820 EVT StVT = St->getMemoryVT();
23822 SDValue StoredVal = St->getOperand(1);
23823 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23825 // If we are saving a concatenation of two XMM registers, perform two stores.
23826 // On Sandy Bridge, 256-bit memory operations are executed by two
23827 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23828 // memory operation.
23829 unsigned Alignment = St->getAlignment();
23830 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23831 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23832 StVT == VT && !IsAligned) {
23833 unsigned NumElems = VT.getVectorNumElements();
23837 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23838 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23840 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23841 SDValue Ptr0 = St->getBasePtr();
23842 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23844 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23845 St->getPointerInfo(), St->isVolatile(),
23846 St->isNonTemporal(), Alignment);
23847 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23848 St->getPointerInfo(), St->isVolatile(),
23849 St->isNonTemporal(),
23850 std::min(16U, Alignment));
23851 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23854 // Optimize trunc store (of multiple scalars) to shuffle and store.
23855 // First, pack all of the elements in one place. Next, store to memory
23856 // in fewer chunks.
23857 if (St->isTruncatingStore() && VT.isVector()) {
23858 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23859 unsigned NumElems = VT.getVectorNumElements();
23860 assert(StVT != VT && "Cannot truncate to the same type");
23861 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23862 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23864 // From, To sizes and ElemCount must be pow of two
23865 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23866 // We are going to use the original vector elt for storing.
23867 // Accumulated smaller vector elements must be a multiple of the store size.
23868 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23870 unsigned SizeRatio = FromSz / ToSz;
23872 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23874 // Create a type on which we perform the shuffle
23875 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23876 StVT.getScalarType(), NumElems*SizeRatio);
23878 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23880 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23881 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23882 for (unsigned i = 0; i != NumElems; ++i)
23883 ShuffleVec[i] = i * SizeRatio;
23885 // Can't shuffle using an illegal type.
23886 if (!TLI.isTypeLegal(WideVecVT))
23889 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23890 DAG.getUNDEF(WideVecVT),
23892 // At this point all of the data is stored at the bottom of the
23893 // register. We now need to save it to mem.
23895 // Find the largest store unit
23896 MVT StoreType = MVT::i8;
23897 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23898 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23899 MVT Tp = (MVT::SimpleValueType)tp;
23900 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23904 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23905 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23906 (64 <= NumElems * ToSz))
23907 StoreType = MVT::f64;
23909 // Bitcast the original vector into a vector of store-size units
23910 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23911 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23912 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23913 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23914 SmallVector<SDValue, 8> Chains;
23915 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23916 TLI.getPointerTy());
23917 SDValue Ptr = St->getBasePtr();
23919 // Perform one or more big stores into memory.
23920 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23921 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23922 StoreType, ShuffWide,
23923 DAG.getIntPtrConstant(i));
23924 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23925 St->getPointerInfo(), St->isVolatile(),
23926 St->isNonTemporal(), St->getAlignment());
23927 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23928 Chains.push_back(Ch);
23931 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23934 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23935 // the FP state in cases where an emms may be missing.
23936 // A preferable solution to the general problem is to figure out the right
23937 // places to insert EMMS. This qualifies as a quick hack.
23939 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23940 if (VT.getSizeInBits() != 64)
23943 const Function *F = DAG.getMachineFunction().getFunction();
23944 bool NoImplicitFloatOps = F->getAttributes().
23945 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23946 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23947 && Subtarget->hasSSE2();
23948 if ((VT.isVector() ||
23949 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23950 isa<LoadSDNode>(St->getValue()) &&
23951 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23952 St->getChain().hasOneUse() && !St->isVolatile()) {
23953 SDNode* LdVal = St->getValue().getNode();
23954 LoadSDNode *Ld = nullptr;
23955 int TokenFactorIndex = -1;
23956 SmallVector<SDValue, 8> Ops;
23957 SDNode* ChainVal = St->getChain().getNode();
23958 // Must be a store of a load. We currently handle two cases: the load
23959 // is a direct child, and it's under an intervening TokenFactor. It is
23960 // possible to dig deeper under nested TokenFactors.
23961 if (ChainVal == LdVal)
23962 Ld = cast<LoadSDNode>(St->getChain());
23963 else if (St->getValue().hasOneUse() &&
23964 ChainVal->getOpcode() == ISD::TokenFactor) {
23965 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23966 if (ChainVal->getOperand(i).getNode() == LdVal) {
23967 TokenFactorIndex = i;
23968 Ld = cast<LoadSDNode>(St->getValue());
23970 Ops.push_back(ChainVal->getOperand(i));
23974 if (!Ld || !ISD::isNormalLoad(Ld))
23977 // If this is not the MMX case, i.e. we are just turning i64 load/store
23978 // into f64 load/store, avoid the transformation if there are multiple
23979 // uses of the loaded value.
23980 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23985 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23986 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23988 if (Subtarget->is64Bit() || F64IsLegal) {
23989 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23990 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23991 Ld->getPointerInfo(), Ld->isVolatile(),
23992 Ld->isNonTemporal(), Ld->isInvariant(),
23993 Ld->getAlignment());
23994 SDValue NewChain = NewLd.getValue(1);
23995 if (TokenFactorIndex != -1) {
23996 Ops.push_back(NewChain);
23997 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23999 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24000 St->getPointerInfo(),
24001 St->isVolatile(), St->isNonTemporal(),
24002 St->getAlignment());
24005 // Otherwise, lower to two pairs of 32-bit loads / stores.
24006 SDValue LoAddr = Ld->getBasePtr();
24007 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24008 DAG.getConstant(4, MVT::i32));
24010 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24011 Ld->getPointerInfo(),
24012 Ld->isVolatile(), Ld->isNonTemporal(),
24013 Ld->isInvariant(), Ld->getAlignment());
24014 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24015 Ld->getPointerInfo().getWithOffset(4),
24016 Ld->isVolatile(), Ld->isNonTemporal(),
24018 MinAlign(Ld->getAlignment(), 4));
24020 SDValue NewChain = LoLd.getValue(1);
24021 if (TokenFactorIndex != -1) {
24022 Ops.push_back(LoLd);
24023 Ops.push_back(HiLd);
24024 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24027 LoAddr = St->getBasePtr();
24028 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24029 DAG.getConstant(4, MVT::i32));
24031 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24032 St->getPointerInfo(),
24033 St->isVolatile(), St->isNonTemporal(),
24034 St->getAlignment());
24035 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24036 St->getPointerInfo().getWithOffset(4),
24038 St->isNonTemporal(),
24039 MinAlign(St->getAlignment(), 4));
24040 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24045 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24046 /// and return the operands for the horizontal operation in LHS and RHS. A
24047 /// horizontal operation performs the binary operation on successive elements
24048 /// of its first operand, then on successive elements of its second operand,
24049 /// returning the resulting values in a vector. For example, if
24050 /// A = < float a0, float a1, float a2, float a3 >
24052 /// B = < float b0, float b1, float b2, float b3 >
24053 /// then the result of doing a horizontal operation on A and B is
24054 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24055 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24056 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24057 /// set to A, RHS to B, and the routine returns 'true'.
24058 /// Note that the binary operation should have the property that if one of the
24059 /// operands is UNDEF then the result is UNDEF.
24060 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24061 // Look for the following pattern: if
24062 // A = < float a0, float a1, float a2, float a3 >
24063 // B = < float b0, float b1, float b2, float b3 >
24065 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24066 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24067 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24068 // which is A horizontal-op B.
24070 // At least one of the operands should be a vector shuffle.
24071 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24072 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24075 MVT VT = LHS.getSimpleValueType();
24077 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24078 "Unsupported vector type for horizontal add/sub");
24080 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24081 // operate independently on 128-bit lanes.
24082 unsigned NumElts = VT.getVectorNumElements();
24083 unsigned NumLanes = VT.getSizeInBits()/128;
24084 unsigned NumLaneElts = NumElts / NumLanes;
24085 assert((NumLaneElts % 2 == 0) &&
24086 "Vector type should have an even number of elements in each lane");
24087 unsigned HalfLaneElts = NumLaneElts/2;
24089 // View LHS in the form
24090 // LHS = VECTOR_SHUFFLE A, B, LMask
24091 // If LHS is not a shuffle then pretend it is the shuffle
24092 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24093 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24096 SmallVector<int, 16> LMask(NumElts);
24097 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24098 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24099 A = LHS.getOperand(0);
24100 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24101 B = LHS.getOperand(1);
24102 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24103 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24105 if (LHS.getOpcode() != ISD::UNDEF)
24107 for (unsigned i = 0; i != NumElts; ++i)
24111 // Likewise, view RHS in the form
24112 // RHS = VECTOR_SHUFFLE C, D, RMask
24114 SmallVector<int, 16> RMask(NumElts);
24115 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24116 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24117 C = RHS.getOperand(0);
24118 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24119 D = RHS.getOperand(1);
24120 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24121 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24123 if (RHS.getOpcode() != ISD::UNDEF)
24125 for (unsigned i = 0; i != NumElts; ++i)
24129 // Check that the shuffles are both shuffling the same vectors.
24130 if (!(A == C && B == D) && !(A == D && B == C))
24133 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24134 if (!A.getNode() && !B.getNode())
24137 // If A and B occur in reverse order in RHS, then "swap" them (which means
24138 // rewriting the mask).
24140 CommuteVectorShuffleMask(RMask, NumElts);
24142 // At this point LHS and RHS are equivalent to
24143 // LHS = VECTOR_SHUFFLE A, B, LMask
24144 // RHS = VECTOR_SHUFFLE A, B, RMask
24145 // Check that the masks correspond to performing a horizontal operation.
24146 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24147 for (unsigned i = 0; i != NumLaneElts; ++i) {
24148 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24150 // Ignore any UNDEF components.
24151 if (LIdx < 0 || RIdx < 0 ||
24152 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24153 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24156 // Check that successive elements are being operated on. If not, this is
24157 // not a horizontal operation.
24158 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24159 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24160 if (!(LIdx == Index && RIdx == Index + 1) &&
24161 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24166 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24167 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24171 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24172 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24173 const X86Subtarget *Subtarget) {
24174 EVT VT = N->getValueType(0);
24175 SDValue LHS = N->getOperand(0);
24176 SDValue RHS = N->getOperand(1);
24178 // Try to synthesize horizontal adds from adds of shuffles.
24179 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24180 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24181 isHorizontalBinOp(LHS, RHS, true))
24182 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24186 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24187 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24188 const X86Subtarget *Subtarget) {
24189 EVT VT = N->getValueType(0);
24190 SDValue LHS = N->getOperand(0);
24191 SDValue RHS = N->getOperand(1);
24193 // Try to synthesize horizontal subs from subs of shuffles.
24194 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24195 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24196 isHorizontalBinOp(LHS, RHS, false))
24197 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24201 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24202 /// X86ISD::FXOR nodes.
24203 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24204 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24205 // F[X]OR(0.0, x) -> x
24206 // F[X]OR(x, 0.0) -> x
24207 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24208 if (C->getValueAPF().isPosZero())
24209 return N->getOperand(1);
24210 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24211 if (C->getValueAPF().isPosZero())
24212 return N->getOperand(0);
24216 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24217 /// X86ISD::FMAX nodes.
24218 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24219 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24221 // Only perform optimizations if UnsafeMath is used.
24222 if (!DAG.getTarget().Options.UnsafeFPMath)
24225 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24226 // into FMINC and FMAXC, which are Commutative operations.
24227 unsigned NewOp = 0;
24228 switch (N->getOpcode()) {
24229 default: llvm_unreachable("unknown opcode");
24230 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24231 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24234 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24235 N->getOperand(0), N->getOperand(1));
24238 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24239 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24240 // FAND(0.0, x) -> 0.0
24241 // FAND(x, 0.0) -> 0.0
24242 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24243 if (C->getValueAPF().isPosZero())
24244 return N->getOperand(0);
24245 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24246 if (C->getValueAPF().isPosZero())
24247 return N->getOperand(1);
24251 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24252 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24253 // FANDN(x, 0.0) -> 0.0
24254 // FANDN(0.0, x) -> x
24255 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24256 if (C->getValueAPF().isPosZero())
24257 return N->getOperand(1);
24258 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24259 if (C->getValueAPF().isPosZero())
24260 return N->getOperand(1);
24264 static SDValue PerformBTCombine(SDNode *N,
24266 TargetLowering::DAGCombinerInfo &DCI) {
24267 // BT ignores high bits in the bit index operand.
24268 SDValue Op1 = N->getOperand(1);
24269 if (Op1.hasOneUse()) {
24270 unsigned BitWidth = Op1.getValueSizeInBits();
24271 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24272 APInt KnownZero, KnownOne;
24273 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24274 !DCI.isBeforeLegalizeOps());
24275 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24276 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24277 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24278 DCI.CommitTargetLoweringOpt(TLO);
24283 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24284 SDValue Op = N->getOperand(0);
24285 if (Op.getOpcode() == ISD::BITCAST)
24286 Op = Op.getOperand(0);
24287 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24288 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24289 VT.getVectorElementType().getSizeInBits() ==
24290 OpVT.getVectorElementType().getSizeInBits()) {
24291 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24296 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24297 const X86Subtarget *Subtarget) {
24298 EVT VT = N->getValueType(0);
24299 if (!VT.isVector())
24302 SDValue N0 = N->getOperand(0);
24303 SDValue N1 = N->getOperand(1);
24304 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24307 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24308 // both SSE and AVX2 since there is no sign-extended shift right
24309 // operation on a vector with 64-bit elements.
24310 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24311 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24312 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24313 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24314 SDValue N00 = N0.getOperand(0);
24316 // EXTLOAD has a better solution on AVX2,
24317 // it may be replaced with X86ISD::VSEXT node.
24318 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24319 if (!ISD::isNormalLoad(N00.getNode()))
24322 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24323 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24325 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24331 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24332 TargetLowering::DAGCombinerInfo &DCI,
24333 const X86Subtarget *Subtarget) {
24334 SDValue N0 = N->getOperand(0);
24335 EVT VT = N->getValueType(0);
24337 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24338 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24339 // This exposes the sext to the sdivrem lowering, so that it directly extends
24340 // from AH (which we otherwise need to do contortions to access).
24341 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24342 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24344 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24345 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24346 N0.getOperand(0), N0.getOperand(1));
24347 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24348 return R.getValue(1);
24351 if (!DCI.isBeforeLegalizeOps())
24354 if (!Subtarget->hasFp256())
24357 if (VT.isVector() && VT.getSizeInBits() == 256) {
24358 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24366 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24367 const X86Subtarget* Subtarget) {
24369 EVT VT = N->getValueType(0);
24371 // Let legalize expand this if it isn't a legal type yet.
24372 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24375 EVT ScalarVT = VT.getScalarType();
24376 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24377 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24380 SDValue A = N->getOperand(0);
24381 SDValue B = N->getOperand(1);
24382 SDValue C = N->getOperand(2);
24384 bool NegA = (A.getOpcode() == ISD::FNEG);
24385 bool NegB = (B.getOpcode() == ISD::FNEG);
24386 bool NegC = (C.getOpcode() == ISD::FNEG);
24388 // Negative multiplication when NegA xor NegB
24389 bool NegMul = (NegA != NegB);
24391 A = A.getOperand(0);
24393 B = B.getOperand(0);
24395 C = C.getOperand(0);
24399 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24401 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24403 return DAG.getNode(Opcode, dl, VT, A, B, C);
24406 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24407 TargetLowering::DAGCombinerInfo &DCI,
24408 const X86Subtarget *Subtarget) {
24409 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24410 // (and (i32 x86isd::setcc_carry), 1)
24411 // This eliminates the zext. This transformation is necessary because
24412 // ISD::SETCC is always legalized to i8.
24414 SDValue N0 = N->getOperand(0);
24415 EVT VT = N->getValueType(0);
24417 if (N0.getOpcode() == ISD::AND &&
24419 N0.getOperand(0).hasOneUse()) {
24420 SDValue N00 = N0.getOperand(0);
24421 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24422 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24423 if (!C || C->getZExtValue() != 1)
24425 return DAG.getNode(ISD::AND, dl, VT,
24426 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24427 N00.getOperand(0), N00.getOperand(1)),
24428 DAG.getConstant(1, VT));
24432 if (N0.getOpcode() == ISD::TRUNCATE &&
24434 N0.getOperand(0).hasOneUse()) {
24435 SDValue N00 = N0.getOperand(0);
24436 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24437 return DAG.getNode(ISD::AND, dl, VT,
24438 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24439 N00.getOperand(0), N00.getOperand(1)),
24440 DAG.getConstant(1, VT));
24443 if (VT.is256BitVector()) {
24444 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24449 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24450 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24451 // This exposes the zext to the udivrem lowering, so that it directly extends
24452 // from AH (which we otherwise need to do contortions to access).
24453 if (N0.getOpcode() == ISD::UDIVREM &&
24454 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24455 (VT == MVT::i32 || VT == MVT::i64)) {
24456 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24457 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24458 N0.getOperand(0), N0.getOperand(1));
24459 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24460 return R.getValue(1);
24466 // Optimize x == -y --> x+y == 0
24467 // x != -y --> x+y != 0
24468 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24469 const X86Subtarget* Subtarget) {
24470 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24471 SDValue LHS = N->getOperand(0);
24472 SDValue RHS = N->getOperand(1);
24473 EVT VT = N->getValueType(0);
24476 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24477 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24478 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24479 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24480 LHS.getValueType(), RHS, LHS.getOperand(1));
24481 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24482 addV, DAG.getConstant(0, addV.getValueType()), CC);
24484 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24485 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24486 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24487 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24488 RHS.getValueType(), LHS, RHS.getOperand(1));
24489 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24490 addV, DAG.getConstant(0, addV.getValueType()), CC);
24493 if (VT.getScalarType() == MVT::i1) {
24494 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24495 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24496 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24497 if (!IsSEXT0 && !IsVZero0)
24499 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24500 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24501 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24503 if (!IsSEXT1 && !IsVZero1)
24506 if (IsSEXT0 && IsVZero1) {
24507 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24508 if (CC == ISD::SETEQ)
24509 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24510 return LHS.getOperand(0);
24512 if (IsSEXT1 && IsVZero0) {
24513 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24514 if (CC == ISD::SETEQ)
24515 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24516 return RHS.getOperand(0);
24523 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24524 const X86Subtarget *Subtarget) {
24526 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24527 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24528 "X86insertps is only defined for v4x32");
24530 SDValue Ld = N->getOperand(1);
24531 if (MayFoldLoad(Ld)) {
24532 // Extract the countS bits from the immediate so we can get the proper
24533 // address when narrowing the vector load to a specific element.
24534 // When the second source op is a memory address, interps doesn't use
24535 // countS and just gets an f32 from that address.
24536 unsigned DestIndex =
24537 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24538 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24542 // Create this as a scalar to vector to match the instruction pattern.
24543 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24544 // countS bits are ignored when loading from memory on insertps, which
24545 // means we don't need to explicitly set them to 0.
24546 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24547 LoadScalarToVector, N->getOperand(2));
24550 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24551 // as "sbb reg,reg", since it can be extended without zext and produces
24552 // an all-ones bit which is more useful than 0/1 in some cases.
24553 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24556 return DAG.getNode(ISD::AND, DL, VT,
24557 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24558 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24559 DAG.getConstant(1, VT));
24560 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24561 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24562 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24563 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24566 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24567 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24568 TargetLowering::DAGCombinerInfo &DCI,
24569 const X86Subtarget *Subtarget) {
24571 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24572 SDValue EFLAGS = N->getOperand(1);
24574 if (CC == X86::COND_A) {
24575 // Try to convert COND_A into COND_B in an attempt to facilitate
24576 // materializing "setb reg".
24578 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24579 // cannot take an immediate as its first operand.
24581 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24582 EFLAGS.getValueType().isInteger() &&
24583 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24584 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24585 EFLAGS.getNode()->getVTList(),
24586 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24587 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24588 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24592 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24593 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24595 if (CC == X86::COND_B)
24596 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24600 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24601 if (Flags.getNode()) {
24602 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24603 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24609 // Optimize branch condition evaluation.
24611 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24612 TargetLowering::DAGCombinerInfo &DCI,
24613 const X86Subtarget *Subtarget) {
24615 SDValue Chain = N->getOperand(0);
24616 SDValue Dest = N->getOperand(1);
24617 SDValue EFLAGS = N->getOperand(3);
24618 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24622 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24623 if (Flags.getNode()) {
24624 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24625 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24632 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24633 SelectionDAG &DAG) {
24634 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24635 // optimize away operation when it's from a constant.
24637 // The general transformation is:
24638 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24639 // AND(VECTOR_CMP(x,y), constant2)
24640 // constant2 = UNARYOP(constant)
24642 // Early exit if this isn't a vector operation, the operand of the
24643 // unary operation isn't a bitwise AND, or if the sizes of the operations
24644 // aren't the same.
24645 EVT VT = N->getValueType(0);
24646 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24647 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24648 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24651 // Now check that the other operand of the AND is a constant. We could
24652 // make the transformation for non-constant splats as well, but it's unclear
24653 // that would be a benefit as it would not eliminate any operations, just
24654 // perform one more step in scalar code before moving to the vector unit.
24655 if (BuildVectorSDNode *BV =
24656 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24657 // Bail out if the vector isn't a constant.
24658 if (!BV->isConstant())
24661 // Everything checks out. Build up the new and improved node.
24663 EVT IntVT = BV->getValueType(0);
24664 // Create a new constant of the appropriate type for the transformed
24666 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24667 // The AND node needs bitcasts to/from an integer vector type around it.
24668 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24669 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24670 N->getOperand(0)->getOperand(0), MaskConst);
24671 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24678 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24679 const X86TargetLowering *XTLI) {
24680 // First try to optimize away the conversion entirely when it's
24681 // conditionally from a constant. Vectors only.
24682 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24683 if (Res != SDValue())
24686 // Now move on to more general possibilities.
24687 SDValue Op0 = N->getOperand(0);
24688 EVT InVT = Op0->getValueType(0);
24690 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24691 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24693 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24694 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24695 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24698 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24699 // a 32-bit target where SSE doesn't support i64->FP operations.
24700 if (Op0.getOpcode() == ISD::LOAD) {
24701 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24702 EVT VT = Ld->getValueType(0);
24703 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24704 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24705 !XTLI->getSubtarget()->is64Bit() &&
24707 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24708 Ld->getChain(), Op0, DAG);
24709 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24716 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24717 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24718 X86TargetLowering::DAGCombinerInfo &DCI) {
24719 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24720 // the result is either zero or one (depending on the input carry bit).
24721 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24722 if (X86::isZeroNode(N->getOperand(0)) &&
24723 X86::isZeroNode(N->getOperand(1)) &&
24724 // We don't have a good way to replace an EFLAGS use, so only do this when
24726 SDValue(N, 1).use_empty()) {
24728 EVT VT = N->getValueType(0);
24729 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24730 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24731 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24732 DAG.getConstant(X86::COND_B,MVT::i8),
24734 DAG.getConstant(1, VT));
24735 return DCI.CombineTo(N, Res1, CarryOut);
24741 // fold (add Y, (sete X, 0)) -> adc 0, Y
24742 // (add Y, (setne X, 0)) -> sbb -1, Y
24743 // (sub (sete X, 0), Y) -> sbb 0, Y
24744 // (sub (setne X, 0), Y) -> adc -1, Y
24745 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24748 // Look through ZExts.
24749 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24750 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24753 SDValue SetCC = Ext.getOperand(0);
24754 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24757 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24758 if (CC != X86::COND_E && CC != X86::COND_NE)
24761 SDValue Cmp = SetCC.getOperand(1);
24762 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24763 !X86::isZeroNode(Cmp.getOperand(1)) ||
24764 !Cmp.getOperand(0).getValueType().isInteger())
24767 SDValue CmpOp0 = Cmp.getOperand(0);
24768 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24769 DAG.getConstant(1, CmpOp0.getValueType()));
24771 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24772 if (CC == X86::COND_NE)
24773 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24774 DL, OtherVal.getValueType(), OtherVal,
24775 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24776 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24777 DL, OtherVal.getValueType(), OtherVal,
24778 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24781 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24782 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24783 const X86Subtarget *Subtarget) {
24784 EVT VT = N->getValueType(0);
24785 SDValue Op0 = N->getOperand(0);
24786 SDValue Op1 = N->getOperand(1);
24788 // Try to synthesize horizontal adds from adds of shuffles.
24789 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24790 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24791 isHorizontalBinOp(Op0, Op1, true))
24792 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24794 return OptimizeConditionalInDecrement(N, DAG);
24797 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24798 const X86Subtarget *Subtarget) {
24799 SDValue Op0 = N->getOperand(0);
24800 SDValue Op1 = N->getOperand(1);
24802 // X86 can't encode an immediate LHS of a sub. See if we can push the
24803 // negation into a preceding instruction.
24804 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24805 // If the RHS of the sub is a XOR with one use and a constant, invert the
24806 // immediate. Then add one to the LHS of the sub so we can turn
24807 // X-Y -> X+~Y+1, saving one register.
24808 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24809 isa<ConstantSDNode>(Op1.getOperand(1))) {
24810 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24811 EVT VT = Op0.getValueType();
24812 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24814 DAG.getConstant(~XorC, VT));
24815 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24816 DAG.getConstant(C->getAPIntValue()+1, VT));
24820 // Try to synthesize horizontal adds from adds of shuffles.
24821 EVT VT = N->getValueType(0);
24822 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24823 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24824 isHorizontalBinOp(Op0, Op1, true))
24825 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24827 return OptimizeConditionalInDecrement(N, DAG);
24830 /// performVZEXTCombine - Performs build vector combines
24831 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24832 TargetLowering::DAGCombinerInfo &DCI,
24833 const X86Subtarget *Subtarget) {
24835 MVT VT = N->getSimpleValueType(0);
24836 SDValue Op = N->getOperand(0);
24837 MVT OpVT = Op.getSimpleValueType();
24838 MVT OpEltVT = OpVT.getVectorElementType();
24839 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24841 // (vzext (bitcast (vzext (x)) -> (vzext x)
24843 while (V.getOpcode() == ISD::BITCAST)
24844 V = V.getOperand(0);
24846 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24847 MVT InnerVT = V.getSimpleValueType();
24848 MVT InnerEltVT = InnerVT.getVectorElementType();
24850 // If the element sizes match exactly, we can just do one larger vzext. This
24851 // is always an exact type match as vzext operates on integer types.
24852 if (OpEltVT == InnerEltVT) {
24853 assert(OpVT == InnerVT && "Types must match for vzext!");
24854 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24857 // The only other way we can combine them is if only a single element of the
24858 // inner vzext is used in the input to the outer vzext.
24859 if (InnerEltVT.getSizeInBits() < InputBits)
24862 // In this case, the inner vzext is completely dead because we're going to
24863 // only look at bits inside of the low element. Just do the outer vzext on
24864 // a bitcast of the input to the inner.
24865 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24866 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24869 // Check if we can bypass extracting and re-inserting an element of an input
24870 // vector. Essentialy:
24871 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24872 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24873 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24874 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24875 SDValue ExtractedV = V.getOperand(0);
24876 SDValue OrigV = ExtractedV.getOperand(0);
24877 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24878 if (ExtractIdx->getZExtValue() == 0) {
24879 MVT OrigVT = OrigV.getSimpleValueType();
24880 // Extract a subvector if necessary...
24881 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24882 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24883 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24884 OrigVT.getVectorNumElements() / Ratio);
24885 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24886 DAG.getIntPtrConstant(0));
24888 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24889 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24896 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24897 DAGCombinerInfo &DCI) const {
24898 SelectionDAG &DAG = DCI.DAG;
24899 switch (N->getOpcode()) {
24901 case ISD::EXTRACT_VECTOR_ELT:
24902 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24905 case X86ISD::SHRUNKBLEND:
24906 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24907 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24908 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24909 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24910 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24911 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24914 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24915 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24916 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24917 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24918 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24919 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24920 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24921 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24922 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24924 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24926 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24927 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24928 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24929 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24930 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24931 case ISD::ANY_EXTEND:
24932 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24933 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24934 case ISD::SIGN_EXTEND_INREG:
24935 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24936 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24937 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24938 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24939 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24940 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24941 case X86ISD::SHUFP: // Handle all target specific shuffles
24942 case X86ISD::PALIGNR:
24943 case X86ISD::UNPCKH:
24944 case X86ISD::UNPCKL:
24945 case X86ISD::MOVHLPS:
24946 case X86ISD::MOVLHPS:
24947 case X86ISD::PSHUFB:
24948 case X86ISD::PSHUFD:
24949 case X86ISD::PSHUFHW:
24950 case X86ISD::PSHUFLW:
24951 case X86ISD::MOVSS:
24952 case X86ISD::MOVSD:
24953 case X86ISD::VPERMILPI:
24954 case X86ISD::VPERM2X128:
24955 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24956 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24957 case ISD::INTRINSIC_WO_CHAIN:
24958 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24959 case X86ISD::INSERTPS:
24960 return PerformINSERTPSCombine(N, DAG, Subtarget);
24961 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24967 /// isTypeDesirableForOp - Return true if the target has native support for
24968 /// the specified value type and it is 'desirable' to use the type for the
24969 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24970 /// instruction encodings are longer and some i16 instructions are slow.
24971 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24972 if (!isTypeLegal(VT))
24974 if (VT != MVT::i16)
24981 case ISD::SIGN_EXTEND:
24982 case ISD::ZERO_EXTEND:
24983 case ISD::ANY_EXTEND:
24996 /// IsDesirableToPromoteOp - This method query the target whether it is
24997 /// beneficial for dag combiner to promote the specified node. If true, it
24998 /// should return the desired promotion type by reference.
24999 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25000 EVT VT = Op.getValueType();
25001 if (VT != MVT::i16)
25004 bool Promote = false;
25005 bool Commute = false;
25006 switch (Op.getOpcode()) {
25009 LoadSDNode *LD = cast<LoadSDNode>(Op);
25010 // If the non-extending load has a single use and it's not live out, then it
25011 // might be folded.
25012 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25013 Op.hasOneUse()*/) {
25014 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25015 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25016 // The only case where we'd want to promote LOAD (rather then it being
25017 // promoted as an operand is when it's only use is liveout.
25018 if (UI->getOpcode() != ISD::CopyToReg)
25025 case ISD::SIGN_EXTEND:
25026 case ISD::ZERO_EXTEND:
25027 case ISD::ANY_EXTEND:
25032 SDValue N0 = Op.getOperand(0);
25033 // Look out for (store (shl (load), x)).
25034 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25047 SDValue N0 = Op.getOperand(0);
25048 SDValue N1 = Op.getOperand(1);
25049 if (!Commute && MayFoldLoad(N1))
25051 // Avoid disabling potential load folding opportunities.
25052 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25054 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25064 //===----------------------------------------------------------------------===//
25065 // X86 Inline Assembly Support
25066 //===----------------------------------------------------------------------===//
25069 // Helper to match a string separated by whitespace.
25070 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25071 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25073 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25074 StringRef piece(*args[i]);
25075 if (!s.startswith(piece)) // Check if the piece matches.
25078 s = s.substr(piece.size());
25079 StringRef::size_type pos = s.find_first_not_of(" \t");
25080 if (pos == 0) // We matched a prefix.
25088 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25091 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25093 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25094 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25095 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25096 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25098 if (AsmPieces.size() == 3)
25100 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25107 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25108 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25110 std::string AsmStr = IA->getAsmString();
25112 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25113 if (!Ty || Ty->getBitWidth() % 16 != 0)
25116 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25117 SmallVector<StringRef, 4> AsmPieces;
25118 SplitString(AsmStr, AsmPieces, ";\n");
25120 switch (AsmPieces.size()) {
25121 default: return false;
25123 // FIXME: this should verify that we are targeting a 486 or better. If not,
25124 // we will turn this bswap into something that will be lowered to logical
25125 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25126 // lower so don't worry about this.
25128 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25129 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25130 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25131 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25132 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25133 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25134 // No need to check constraints, nothing other than the equivalent of
25135 // "=r,0" would be valid here.
25136 return IntrinsicLowering::LowerToByteSwap(CI);
25139 // rorw $$8, ${0:w} --> llvm.bswap.i16
25140 if (CI->getType()->isIntegerTy(16) &&
25141 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25142 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25143 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25145 const std::string &ConstraintsStr = IA->getConstraintString();
25146 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25147 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25148 if (clobbersFlagRegisters(AsmPieces))
25149 return IntrinsicLowering::LowerToByteSwap(CI);
25153 if (CI->getType()->isIntegerTy(32) &&
25154 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25155 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25156 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25157 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25159 const std::string &ConstraintsStr = IA->getConstraintString();
25160 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25161 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25162 if (clobbersFlagRegisters(AsmPieces))
25163 return IntrinsicLowering::LowerToByteSwap(CI);
25166 if (CI->getType()->isIntegerTy(64)) {
25167 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25168 if (Constraints.size() >= 2 &&
25169 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25170 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25171 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25172 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25173 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25174 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25175 return IntrinsicLowering::LowerToByteSwap(CI);
25183 /// getConstraintType - Given a constraint letter, return the type of
25184 /// constraint it is for this target.
25185 X86TargetLowering::ConstraintType
25186 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25187 if (Constraint.size() == 1) {
25188 switch (Constraint[0]) {
25199 return C_RegisterClass;
25223 return TargetLowering::getConstraintType(Constraint);
25226 /// Examine constraint type and operand type and determine a weight value.
25227 /// This object must already have been set up with the operand type
25228 /// and the current alternative constraint selected.
25229 TargetLowering::ConstraintWeight
25230 X86TargetLowering::getSingleConstraintMatchWeight(
25231 AsmOperandInfo &info, const char *constraint) const {
25232 ConstraintWeight weight = CW_Invalid;
25233 Value *CallOperandVal = info.CallOperandVal;
25234 // If we don't have a value, we can't do a match,
25235 // but allow it at the lowest weight.
25236 if (!CallOperandVal)
25238 Type *type = CallOperandVal->getType();
25239 // Look at the constraint type.
25240 switch (*constraint) {
25242 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25253 if (CallOperandVal->getType()->isIntegerTy())
25254 weight = CW_SpecificReg;
25259 if (type->isFloatingPointTy())
25260 weight = CW_SpecificReg;
25263 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25264 weight = CW_SpecificReg;
25268 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25269 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25270 weight = CW_Register;
25273 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25274 if (C->getZExtValue() <= 31)
25275 weight = CW_Constant;
25279 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25280 if (C->getZExtValue() <= 63)
25281 weight = CW_Constant;
25285 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25286 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25287 weight = CW_Constant;
25291 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25292 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25293 weight = CW_Constant;
25297 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25298 if (C->getZExtValue() <= 3)
25299 weight = CW_Constant;
25303 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25304 if (C->getZExtValue() <= 0xff)
25305 weight = CW_Constant;
25310 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25311 weight = CW_Constant;
25315 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25316 if ((C->getSExtValue() >= -0x80000000LL) &&
25317 (C->getSExtValue() <= 0x7fffffffLL))
25318 weight = CW_Constant;
25322 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25323 if (C->getZExtValue() <= 0xffffffff)
25324 weight = CW_Constant;
25331 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25332 /// with another that has more specific requirements based on the type of the
25333 /// corresponding operand.
25334 const char *X86TargetLowering::
25335 LowerXConstraint(EVT ConstraintVT) const {
25336 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25337 // 'f' like normal targets.
25338 if (ConstraintVT.isFloatingPoint()) {
25339 if (Subtarget->hasSSE2())
25341 if (Subtarget->hasSSE1())
25345 return TargetLowering::LowerXConstraint(ConstraintVT);
25348 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25349 /// vector. If it is invalid, don't add anything to Ops.
25350 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25351 std::string &Constraint,
25352 std::vector<SDValue>&Ops,
25353 SelectionDAG &DAG) const {
25356 // Only support length 1 constraints for now.
25357 if (Constraint.length() > 1) return;
25359 char ConstraintLetter = Constraint[0];
25360 switch (ConstraintLetter) {
25363 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25364 if (C->getZExtValue() <= 31) {
25365 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25371 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25372 if (C->getZExtValue() <= 63) {
25373 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25379 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25380 if (isInt<8>(C->getSExtValue())) {
25381 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25387 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25388 if (C->getZExtValue() <= 255) {
25389 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25395 // 32-bit signed value
25396 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25397 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25398 C->getSExtValue())) {
25399 // Widen to 64 bits here to get it sign extended.
25400 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25403 // FIXME gcc accepts some relocatable values here too, but only in certain
25404 // memory models; it's complicated.
25409 // 32-bit unsigned value
25410 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25411 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25412 C->getZExtValue())) {
25413 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25417 // FIXME gcc accepts some relocatable values here too, but only in certain
25418 // memory models; it's complicated.
25422 // Literal immediates are always ok.
25423 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25424 // Widen to 64 bits here to get it sign extended.
25425 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25429 // In any sort of PIC mode addresses need to be computed at runtime by
25430 // adding in a register or some sort of table lookup. These can't
25431 // be used as immediates.
25432 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25435 // If we are in non-pic codegen mode, we allow the address of a global (with
25436 // an optional displacement) to be used with 'i'.
25437 GlobalAddressSDNode *GA = nullptr;
25438 int64_t Offset = 0;
25440 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25442 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25443 Offset += GA->getOffset();
25445 } else if (Op.getOpcode() == ISD::ADD) {
25446 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25447 Offset += C->getZExtValue();
25448 Op = Op.getOperand(0);
25451 } else if (Op.getOpcode() == ISD::SUB) {
25452 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25453 Offset += -C->getZExtValue();
25454 Op = Op.getOperand(0);
25459 // Otherwise, this isn't something we can handle, reject it.
25463 const GlobalValue *GV = GA->getGlobal();
25464 // If we require an extra load to get this address, as in PIC mode, we
25465 // can't accept it.
25466 if (isGlobalStubReference(
25467 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25470 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25471 GA->getValueType(0), Offset);
25476 if (Result.getNode()) {
25477 Ops.push_back(Result);
25480 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25483 std::pair<unsigned, const TargetRegisterClass*>
25484 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25486 // First, see if this is a constraint that directly corresponds to an LLVM
25488 if (Constraint.size() == 1) {
25489 // GCC Constraint Letters
25490 switch (Constraint[0]) {
25492 // TODO: Slight differences here in allocation order and leaving
25493 // RIP in the class. Do they matter any more here than they do
25494 // in the normal allocation?
25495 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25496 if (Subtarget->is64Bit()) {
25497 if (VT == MVT::i32 || VT == MVT::f32)
25498 return std::make_pair(0U, &X86::GR32RegClass);
25499 if (VT == MVT::i16)
25500 return std::make_pair(0U, &X86::GR16RegClass);
25501 if (VT == MVT::i8 || VT == MVT::i1)
25502 return std::make_pair(0U, &X86::GR8RegClass);
25503 if (VT == MVT::i64 || VT == MVT::f64)
25504 return std::make_pair(0U, &X86::GR64RegClass);
25507 // 32-bit fallthrough
25508 case 'Q': // Q_REGS
25509 if (VT == MVT::i32 || VT == MVT::f32)
25510 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25511 if (VT == MVT::i16)
25512 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25513 if (VT == MVT::i8 || VT == MVT::i1)
25514 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25515 if (VT == MVT::i64)
25516 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25518 case 'r': // GENERAL_REGS
25519 case 'l': // INDEX_REGS
25520 if (VT == MVT::i8 || VT == MVT::i1)
25521 return std::make_pair(0U, &X86::GR8RegClass);
25522 if (VT == MVT::i16)
25523 return std::make_pair(0U, &X86::GR16RegClass);
25524 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25525 return std::make_pair(0U, &X86::GR32RegClass);
25526 return std::make_pair(0U, &X86::GR64RegClass);
25527 case 'R': // LEGACY_REGS
25528 if (VT == MVT::i8 || VT == MVT::i1)
25529 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25530 if (VT == MVT::i16)
25531 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25532 if (VT == MVT::i32 || !Subtarget->is64Bit())
25533 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25534 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25535 case 'f': // FP Stack registers.
25536 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25537 // value to the correct fpstack register class.
25538 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25539 return std::make_pair(0U, &X86::RFP32RegClass);
25540 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25541 return std::make_pair(0U, &X86::RFP64RegClass);
25542 return std::make_pair(0U, &X86::RFP80RegClass);
25543 case 'y': // MMX_REGS if MMX allowed.
25544 if (!Subtarget->hasMMX()) break;
25545 return std::make_pair(0U, &X86::VR64RegClass);
25546 case 'Y': // SSE_REGS if SSE2 allowed
25547 if (!Subtarget->hasSSE2()) break;
25549 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25550 if (!Subtarget->hasSSE1()) break;
25552 switch (VT.SimpleTy) {
25554 // Scalar SSE types.
25557 return std::make_pair(0U, &X86::FR32RegClass);
25560 return std::make_pair(0U, &X86::FR64RegClass);
25568 return std::make_pair(0U, &X86::VR128RegClass);
25576 return std::make_pair(0U, &X86::VR256RegClass);
25581 return std::make_pair(0U, &X86::VR512RegClass);
25587 // Use the default implementation in TargetLowering to convert the register
25588 // constraint into a member of a register class.
25589 std::pair<unsigned, const TargetRegisterClass*> Res;
25590 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25592 // Not found as a standard register?
25594 // Map st(0) -> st(7) -> ST0
25595 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25596 tolower(Constraint[1]) == 's' &&
25597 tolower(Constraint[2]) == 't' &&
25598 Constraint[3] == '(' &&
25599 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25600 Constraint[5] == ')' &&
25601 Constraint[6] == '}') {
25603 Res.first = X86::FP0+Constraint[4]-'0';
25604 Res.second = &X86::RFP80RegClass;
25608 // GCC allows "st(0)" to be called just plain "st".
25609 if (StringRef("{st}").equals_lower(Constraint)) {
25610 Res.first = X86::FP0;
25611 Res.second = &X86::RFP80RegClass;
25616 if (StringRef("{flags}").equals_lower(Constraint)) {
25617 Res.first = X86::EFLAGS;
25618 Res.second = &X86::CCRRegClass;
25622 // 'A' means EAX + EDX.
25623 if (Constraint == "A") {
25624 Res.first = X86::EAX;
25625 Res.second = &X86::GR32_ADRegClass;
25631 // Otherwise, check to see if this is a register class of the wrong value
25632 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25633 // turn into {ax},{dx}.
25634 if (Res.second->hasType(VT))
25635 return Res; // Correct type already, nothing to do.
25637 // All of the single-register GCC register classes map their values onto
25638 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25639 // really want an 8-bit or 32-bit register, map to the appropriate register
25640 // class and return the appropriate register.
25641 if (Res.second == &X86::GR16RegClass) {
25642 if (VT == MVT::i8 || VT == MVT::i1) {
25643 unsigned DestReg = 0;
25644 switch (Res.first) {
25646 case X86::AX: DestReg = X86::AL; break;
25647 case X86::DX: DestReg = X86::DL; break;
25648 case X86::CX: DestReg = X86::CL; break;
25649 case X86::BX: DestReg = X86::BL; break;
25652 Res.first = DestReg;
25653 Res.second = &X86::GR8RegClass;
25655 } else if (VT == MVT::i32 || VT == MVT::f32) {
25656 unsigned DestReg = 0;
25657 switch (Res.first) {
25659 case X86::AX: DestReg = X86::EAX; break;
25660 case X86::DX: DestReg = X86::EDX; break;
25661 case X86::CX: DestReg = X86::ECX; break;
25662 case X86::BX: DestReg = X86::EBX; break;
25663 case X86::SI: DestReg = X86::ESI; break;
25664 case X86::DI: DestReg = X86::EDI; break;
25665 case X86::BP: DestReg = X86::EBP; break;
25666 case X86::SP: DestReg = X86::ESP; break;
25669 Res.first = DestReg;
25670 Res.second = &X86::GR32RegClass;
25672 } else if (VT == MVT::i64 || VT == MVT::f64) {
25673 unsigned DestReg = 0;
25674 switch (Res.first) {
25676 case X86::AX: DestReg = X86::RAX; break;
25677 case X86::DX: DestReg = X86::RDX; break;
25678 case X86::CX: DestReg = X86::RCX; break;
25679 case X86::BX: DestReg = X86::RBX; break;
25680 case X86::SI: DestReg = X86::RSI; break;
25681 case X86::DI: DestReg = X86::RDI; break;
25682 case X86::BP: DestReg = X86::RBP; break;
25683 case X86::SP: DestReg = X86::RSP; break;
25686 Res.first = DestReg;
25687 Res.second = &X86::GR64RegClass;
25690 } else if (Res.second == &X86::FR32RegClass ||
25691 Res.second == &X86::FR64RegClass ||
25692 Res.second == &X86::VR128RegClass ||
25693 Res.second == &X86::VR256RegClass ||
25694 Res.second == &X86::FR32XRegClass ||
25695 Res.second == &X86::FR64XRegClass ||
25696 Res.second == &X86::VR128XRegClass ||
25697 Res.second == &X86::VR256XRegClass ||
25698 Res.second == &X86::VR512RegClass) {
25699 // Handle references to XMM physical registers that got mapped into the
25700 // wrong class. This can happen with constraints like {xmm0} where the
25701 // target independent register mapper will just pick the first match it can
25702 // find, ignoring the required type.
25704 if (VT == MVT::f32 || VT == MVT::i32)
25705 Res.second = &X86::FR32RegClass;
25706 else if (VT == MVT::f64 || VT == MVT::i64)
25707 Res.second = &X86::FR64RegClass;
25708 else if (X86::VR128RegClass.hasType(VT))
25709 Res.second = &X86::VR128RegClass;
25710 else if (X86::VR256RegClass.hasType(VT))
25711 Res.second = &X86::VR256RegClass;
25712 else if (X86::VR512RegClass.hasType(VT))
25713 Res.second = &X86::VR512RegClass;
25719 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25721 // Scaling factors are not free at all.
25722 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25723 // will take 2 allocations in the out of order engine instead of 1
25724 // for plain addressing mode, i.e. inst (reg1).
25726 // vaddps (%rsi,%drx), %ymm0, %ymm1
25727 // Requires two allocations (one for the load, one for the computation)
25729 // vaddps (%rsi), %ymm0, %ymm1
25730 // Requires just 1 allocation, i.e., freeing allocations for other operations
25731 // and having less micro operations to execute.
25733 // For some X86 architectures, this is even worse because for instance for
25734 // stores, the complex addressing mode forces the instruction to use the
25735 // "load" ports instead of the dedicated "store" port.
25736 // E.g., on Haswell:
25737 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25738 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25739 if (isLegalAddressingMode(AM, Ty))
25740 // Scale represents reg2 * scale, thus account for 1
25741 // as soon as we use a second register.
25742 return AM.Scale != 0;
25746 bool X86TargetLowering::isTargetFTOL() const {
25747 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();