1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
526 // There's never any support for operations beyond MVT::f32.
527 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
532 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
537 if (Subtarget->hasPOPCNT()) {
538 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
540 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
547 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
549 if (!Subtarget->hasMOVBE())
550 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
552 // These should be promoted to a larger select which is supported.
553 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554 // X86 wants to expand cmov itself.
555 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567 if (Subtarget->is64Bit()) {
568 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
571 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574 // support continuation, user-level threading, and etc.. As a result, no
575 // other SjLj exception interfaces are implemented and please don't build
576 // your own exception handling based on them.
577 // LLVM/Clang supports zero-cost DWARF exception handling.
578 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
582 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586 if (Subtarget->is64Bit())
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
597 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601 if (Subtarget->is64Bit()) {
602 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
607 if (Subtarget->hasSSE1())
608 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
610 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
612 // Expand certain atomics
613 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
615 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
620 if (Subtarget->hasCmpxchg16b()) {
621 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
624 // FIXME - use subtarget debug flags
625 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
630 if (Subtarget->is64Bit()) {
631 setExceptionPointerRegister(X86::RAX);
632 setExceptionSelectorRegister(X86::RDX);
634 setExceptionPointerRegister(X86::EAX);
635 setExceptionSelectorRegister(X86::EDX);
637 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
640 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
643 setOperationAction(ISD::TRAP, MVT::Other, Legal);
644 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
646 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647 setOperationAction(ISD::VASTART , MVT::Other, Custom);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650 // TargetInfo::X86_64ABIBuiltinVaList
651 setOperationAction(ISD::VAARG , MVT::Other, Custom);
652 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
654 // TargetInfo::CharPtrBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Expand);
656 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
662 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
664 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
665 // f32 and f64 use SSE.
666 // Set up the FP register classes.
667 addRegisterClass(MVT::f32, &X86::FR32RegClass);
668 addRegisterClass(MVT::f64, &X86::FR64RegClass);
670 // Use ANDPD to simulate FABS.
671 setOperationAction(ISD::FABS , MVT::f64, Custom);
672 setOperationAction(ISD::FABS , MVT::f32, Custom);
674 // Use XORP to simulate FNEG.
675 setOperationAction(ISD::FNEG , MVT::f64, Custom);
676 setOperationAction(ISD::FNEG , MVT::f32, Custom);
678 // Use ANDPD and ORPD to simulate FCOPYSIGN.
679 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
680 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
682 // Lower this to FGETSIGNx86 plus an AND.
683 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
684 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
686 // We don't support sin/cos/fmod
687 setOperationAction(ISD::FSIN , MVT::f64, Expand);
688 setOperationAction(ISD::FCOS , MVT::f64, Expand);
689 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
690 setOperationAction(ISD::FSIN , MVT::f32, Expand);
691 setOperationAction(ISD::FCOS , MVT::f32, Expand);
692 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
694 // Expand FP immediates into loads from the stack, except for the special
696 addLegalFPImmediate(APFloat(+0.0)); // xorpd
697 addLegalFPImmediate(APFloat(+0.0f)); // xorps
698 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
699 // Use SSE for f32, x87 for f64.
700 // Set up the FP register classes.
701 addRegisterClass(MVT::f32, &X86::FR32RegClass);
702 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
704 // Use ANDPS to simulate FABS.
705 setOperationAction(ISD::FABS , MVT::f32, Custom);
707 // Use XORP to simulate FNEG.
708 setOperationAction(ISD::FNEG , MVT::f32, Custom);
710 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
712 // Use ANDPS and ORPS to simulate FCOPYSIGN.
713 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
714 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
716 // We don't support sin/cos/fmod
717 setOperationAction(ISD::FSIN , MVT::f32, Expand);
718 setOperationAction(ISD::FCOS , MVT::f32, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
721 // Special cases we handle for FP constants.
722 addLegalFPImmediate(APFloat(+0.0f)); // xorps
723 addLegalFPImmediate(APFloat(+0.0)); // FLD0
724 addLegalFPImmediate(APFloat(+1.0)); // FLD1
725 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
726 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
728 if (!TM.Options.UnsafeFPMath) {
729 setOperationAction(ISD::FSIN , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f64, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
733 } else if (!TM.Options.UseSoftFloat) {
734 // f32 and f64 in x87.
735 // Set up the FP register classes.
736 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
737 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
739 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
740 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
741 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
744 if (!TM.Options.UnsafeFPMath) {
745 setOperationAction(ISD::FSIN , MVT::f64, Expand);
746 setOperationAction(ISD::FSIN , MVT::f32, Expand);
747 setOperationAction(ISD::FCOS , MVT::f64, Expand);
748 setOperationAction(ISD::FCOS , MVT::f32, Expand);
749 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
752 addLegalFPImmediate(APFloat(+0.0)); // FLD0
753 addLegalFPImmediate(APFloat(+1.0)); // FLD1
754 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
755 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
756 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
762 // We don't support FMA.
763 setOperationAction(ISD::FMA, MVT::f64, Expand);
764 setOperationAction(ISD::FMA, MVT::f32, Expand);
766 // Long double always uses X87.
767 if (!TM.Options.UseSoftFloat) {
768 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
769 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
770 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
772 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
773 addLegalFPImmediate(TmpFlt); // FLD0
775 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
778 APFloat TmpFlt2(+1.0);
779 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
781 addLegalFPImmediate(TmpFlt2); // FLD1
782 TmpFlt2.changeSign();
783 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
786 if (!TM.Options.UnsafeFPMath) {
787 setOperationAction(ISD::FSIN , MVT::f80, Expand);
788 setOperationAction(ISD::FCOS , MVT::f80, Expand);
789 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
792 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
793 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
794 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
795 setOperationAction(ISD::FRINT, MVT::f80, Expand);
796 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
797 setOperationAction(ISD::FMA, MVT::f80, Expand);
800 // Always use a library call for pow.
801 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
802 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
805 setOperationAction(ISD::FLOG, MVT::f80, Expand);
806 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
808 setOperationAction(ISD::FEXP, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
811 // First set operation action for all vector types to either promote
812 // (for widening) or expand (for scalarization). Then we will selectively
813 // turn on ones that can be effectively codegen'd.
814 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
815 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
816 MVT VT = (MVT::SimpleValueType)i;
817 setOperationAction(ISD::ADD , VT, Expand);
818 setOperationAction(ISD::SUB , VT, Expand);
819 setOperationAction(ISD::FADD, VT, Expand);
820 setOperationAction(ISD::FNEG, VT, Expand);
821 setOperationAction(ISD::FSUB, VT, Expand);
822 setOperationAction(ISD::MUL , VT, Expand);
823 setOperationAction(ISD::FMUL, VT, Expand);
824 setOperationAction(ISD::SDIV, VT, Expand);
825 setOperationAction(ISD::UDIV, VT, Expand);
826 setOperationAction(ISD::FDIV, VT, Expand);
827 setOperationAction(ISD::SREM, VT, Expand);
828 setOperationAction(ISD::UREM, VT, Expand);
829 setOperationAction(ISD::LOAD, VT, Expand);
830 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
831 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
833 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
834 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::FABS, VT, Expand);
836 setOperationAction(ISD::FSIN, VT, Expand);
837 setOperationAction(ISD::FSINCOS, VT, Expand);
838 setOperationAction(ISD::FCOS, VT, Expand);
839 setOperationAction(ISD::FSINCOS, VT, Expand);
840 setOperationAction(ISD::FREM, VT, Expand);
841 setOperationAction(ISD::FMA, VT, Expand);
842 setOperationAction(ISD::FPOWI, VT, Expand);
843 setOperationAction(ISD::FSQRT, VT, Expand);
844 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
845 setOperationAction(ISD::FFLOOR, VT, Expand);
846 setOperationAction(ISD::FCEIL, VT, Expand);
847 setOperationAction(ISD::FTRUNC, VT, Expand);
848 setOperationAction(ISD::FRINT, VT, Expand);
849 setOperationAction(ISD::FNEARBYINT, VT, Expand);
850 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
851 setOperationAction(ISD::MULHS, VT, Expand);
852 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
853 setOperationAction(ISD::MULHU, VT, Expand);
854 setOperationAction(ISD::SDIVREM, VT, Expand);
855 setOperationAction(ISD::UDIVREM, VT, Expand);
856 setOperationAction(ISD::FPOW, VT, Expand);
857 setOperationAction(ISD::CTPOP, VT, Expand);
858 setOperationAction(ISD::CTTZ, VT, Expand);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
860 setOperationAction(ISD::CTLZ, VT, Expand);
861 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
862 setOperationAction(ISD::SHL, VT, Expand);
863 setOperationAction(ISD::SRA, VT, Expand);
864 setOperationAction(ISD::SRL, VT, Expand);
865 setOperationAction(ISD::ROTL, VT, Expand);
866 setOperationAction(ISD::ROTR, VT, Expand);
867 setOperationAction(ISD::BSWAP, VT, Expand);
868 setOperationAction(ISD::SETCC, VT, Expand);
869 setOperationAction(ISD::FLOG, VT, Expand);
870 setOperationAction(ISD::FLOG2, VT, Expand);
871 setOperationAction(ISD::FLOG10, VT, Expand);
872 setOperationAction(ISD::FEXP, VT, Expand);
873 setOperationAction(ISD::FEXP2, VT, Expand);
874 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
875 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
876 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
877 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
879 setOperationAction(ISD::TRUNCATE, VT, Expand);
880 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
881 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
882 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
883 setOperationAction(ISD::VSELECT, VT, Expand);
884 setOperationAction(ISD::SELECT_CC, VT, Expand);
885 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
886 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
887 setTruncStoreAction(VT,
888 (MVT::SimpleValueType)InnerVT, Expand);
889 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
890 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
892 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
893 // we have to deal with them whether we ask for Expansion or not. Setting
894 // Expand causes its own optimisation problems though, so leave them legal.
895 if (VT.getVectorElementType() == MVT::i1)
896 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
899 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
900 // with -msoft-float, disable use of MMX as well.
901 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
902 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
903 // No operations on x86mmx supported, everything uses intrinsics.
906 // MMX-sized vectors (other than x86mmx) are expected to be expanded
907 // into smaller operations.
908 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
909 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
910 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
911 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
912 setOperationAction(ISD::AND, MVT::v8i8, Expand);
913 setOperationAction(ISD::AND, MVT::v4i16, Expand);
914 setOperationAction(ISD::AND, MVT::v2i32, Expand);
915 setOperationAction(ISD::AND, MVT::v1i64, Expand);
916 setOperationAction(ISD::OR, MVT::v8i8, Expand);
917 setOperationAction(ISD::OR, MVT::v4i16, Expand);
918 setOperationAction(ISD::OR, MVT::v2i32, Expand);
919 setOperationAction(ISD::OR, MVT::v1i64, Expand);
920 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
921 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
922 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
923 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
924 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
929 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
930 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
931 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
932 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
933 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
938 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
939 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
941 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
942 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
943 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
944 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
945 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
946 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
947 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
948 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
949 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
950 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
951 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
952 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
955 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
956 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
959 // registers cannot be used even for integer operations.
960 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
961 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
962 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
963 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
966 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
967 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
968 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
969 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
970 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
971 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
972 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
974 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
975 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
976 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
977 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
978 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
979 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
980 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
981 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
982 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
983 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
984 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
985 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
986 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
990 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
991 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1000 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1001 MVT VT = (MVT::SimpleValueType)i;
1002 // Do not attempt to custom lower non-power-of-2 vectors
1003 if (!isPowerOf2_32(VT.getVectorNumElements()))
1005 // Do not attempt to custom lower non-128-bit vectors
1006 if (!VT.is128BitVector())
1008 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1009 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1013 // We support custom legalizing of sext and anyext loads for specific
1014 // memory vector types which we can load as a scalar (or sequence of
1015 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1016 // loads these must work with a single scalar load.
1017 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1018 if (Subtarget->is64Bit()) {
1019 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1022 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1029 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1031 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1033 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1034 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1036 if (Subtarget->is64Bit()) {
1037 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1041 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1042 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1043 MVT VT = (MVT::SimpleValueType)i;
1045 // Do not attempt to promote non-128-bit vectors
1046 if (!VT.is128BitVector())
1049 setOperationAction(ISD::AND, VT, Promote);
1050 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1051 setOperationAction(ISD::OR, VT, Promote);
1052 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1053 setOperationAction(ISD::XOR, VT, Promote);
1054 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1055 setOperationAction(ISD::LOAD, VT, Promote);
1056 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1057 setOperationAction(ISD::SELECT, VT, Promote);
1058 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1061 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1531 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1534 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1535 // of this type with custom code.
1536 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1537 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1538 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1542 // We want to custom lower some of our intrinsics.
1543 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1544 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1545 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1546 if (!Subtarget->is64Bit())
1547 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1549 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1550 // handle type legalization for these operations here.
1552 // FIXME: We really should do custom legalization for addition and
1553 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1554 // than generic legalization for 64-bit multiplication-with-overflow, though.
1555 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1556 // Add/Sub/Mul with overflow operations are custom lowered.
1558 setOperationAction(ISD::SADDO, VT, Custom);
1559 setOperationAction(ISD::UADDO, VT, Custom);
1560 setOperationAction(ISD::SSUBO, VT, Custom);
1561 setOperationAction(ISD::USUBO, VT, Custom);
1562 setOperationAction(ISD::SMULO, VT, Custom);
1563 setOperationAction(ISD::UMULO, VT, Custom);
1566 // There are no 8-bit 3-address imul/mul instructions
1567 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1568 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1570 if (!Subtarget->is64Bit()) {
1571 // These libcalls are not available in 32-bit.
1572 setLibcallName(RTLIB::SHL_I128, nullptr);
1573 setLibcallName(RTLIB::SRL_I128, nullptr);
1574 setLibcallName(RTLIB::SRA_I128, nullptr);
1577 // Combine sin / cos into one node or libcall if possible.
1578 if (Subtarget->hasSinCos()) {
1579 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1580 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1581 if (Subtarget->isTargetDarwin()) {
1582 // For MacOSX, we don't want to the normal expansion of a libcall to
1583 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1585 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1586 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1590 if (Subtarget->isTargetWin64()) {
1591 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1592 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1593 setOperationAction(ISD::SREM, MVT::i128, Custom);
1594 setOperationAction(ISD::UREM, MVT::i128, Custom);
1595 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1596 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1599 // We have target-specific dag combine patterns for the following nodes:
1600 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1601 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1602 setTargetDAGCombine(ISD::VSELECT);
1603 setTargetDAGCombine(ISD::SELECT);
1604 setTargetDAGCombine(ISD::SHL);
1605 setTargetDAGCombine(ISD::SRA);
1606 setTargetDAGCombine(ISD::SRL);
1607 setTargetDAGCombine(ISD::OR);
1608 setTargetDAGCombine(ISD::AND);
1609 setTargetDAGCombine(ISD::ADD);
1610 setTargetDAGCombine(ISD::FADD);
1611 setTargetDAGCombine(ISD::FSUB);
1612 setTargetDAGCombine(ISD::FMA);
1613 setTargetDAGCombine(ISD::SUB);
1614 setTargetDAGCombine(ISD::LOAD);
1615 setTargetDAGCombine(ISD::STORE);
1616 setTargetDAGCombine(ISD::ZERO_EXTEND);
1617 setTargetDAGCombine(ISD::ANY_EXTEND);
1618 setTargetDAGCombine(ISD::SIGN_EXTEND);
1619 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1620 setTargetDAGCombine(ISD::TRUNCATE);
1621 setTargetDAGCombine(ISD::SINT_TO_FP);
1622 setTargetDAGCombine(ISD::SETCC);
1623 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1624 setTargetDAGCombine(ISD::BUILD_VECTOR);
1625 if (Subtarget->is64Bit())
1626 setTargetDAGCombine(ISD::MUL);
1627 setTargetDAGCombine(ISD::XOR);
1629 computeRegisterProperties();
1631 // On Darwin, -Os means optimize for size without hurting performance,
1632 // do not reduce the limit.
1633 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1634 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1635 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1636 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1637 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1638 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1639 setPrefLoopAlignment(4); // 2^4 bytes.
1641 // Predictable cmov don't hurt on atom because it's in-order.
1642 PredictableSelectIsExpensive = !Subtarget->isAtom();
1644 setPrefFunctionAlignment(4); // 2^4 bytes.
1647 // This has so far only been implemented for 64-bit MachO.
1648 bool X86TargetLowering::useLoadStackGuardNode() const {
1649 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1650 Subtarget->is64Bit();
1653 TargetLoweringBase::LegalizeTypeAction
1654 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1655 if (ExperimentalVectorWideningLegalization &&
1656 VT.getVectorNumElements() != 1 &&
1657 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1658 return TypeWidenVector;
1660 return TargetLoweringBase::getPreferredVectorAction(VT);
1663 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1665 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1667 if (Subtarget->hasAVX512())
1668 switch(VT.getVectorNumElements()) {
1669 case 8: return MVT::v8i1;
1670 case 16: return MVT::v16i1;
1673 return VT.changeVectorElementTypeToInteger();
1676 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1677 /// the desired ByVal argument alignment.
1678 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1681 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1682 if (VTy->getBitWidth() == 128)
1684 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1685 unsigned EltAlign = 0;
1686 getMaxByValAlign(ATy->getElementType(), EltAlign);
1687 if (EltAlign > MaxAlign)
1688 MaxAlign = EltAlign;
1689 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1690 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1691 unsigned EltAlign = 0;
1692 getMaxByValAlign(STy->getElementType(i), EltAlign);
1693 if (EltAlign > MaxAlign)
1694 MaxAlign = EltAlign;
1701 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1702 /// function arguments in the caller parameter area. For X86, aggregates
1703 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1704 /// are at 4-byte boundaries.
1705 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1706 if (Subtarget->is64Bit()) {
1707 // Max of 8 and alignment of type.
1708 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1715 if (Subtarget->hasSSE1())
1716 getMaxByValAlign(Ty, Align);
1720 /// getOptimalMemOpType - Returns the target specific optimal type for load
1721 /// and store operations as a result of memset, memcpy, and memmove
1722 /// lowering. If DstAlign is zero that means it's safe to destination
1723 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1724 /// means there isn't a need to check it against alignment requirement,
1725 /// probably because the source does not need to be loaded. If 'IsMemset' is
1726 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1727 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1728 /// source is constant so it does not need to be loaded.
1729 /// It returns EVT::Other if the type should be determined using generic
1730 /// target-independent logic.
1732 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1733 unsigned DstAlign, unsigned SrcAlign,
1734 bool IsMemset, bool ZeroMemset,
1736 MachineFunction &MF) const {
1737 const Function *F = MF.getFunction();
1738 if ((!IsMemset || ZeroMemset) &&
1739 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1740 Attribute::NoImplicitFloat)) {
1742 (Subtarget->isUnalignedMemAccessFast() ||
1743 ((DstAlign == 0 || DstAlign >= 16) &&
1744 (SrcAlign == 0 || SrcAlign >= 16)))) {
1746 if (Subtarget->hasInt256())
1748 if (Subtarget->hasFp256())
1751 if (Subtarget->hasSSE2())
1753 if (Subtarget->hasSSE1())
1755 } else if (!MemcpyStrSrc && Size >= 8 &&
1756 !Subtarget->is64Bit() &&
1757 Subtarget->hasSSE2()) {
1758 // Do not use f64 to lower memcpy if source is string constant. It's
1759 // better to use i32 to avoid the loads.
1763 if (Subtarget->is64Bit() && Size >= 8)
1768 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1770 return X86ScalarSSEf32;
1771 else if (VT == MVT::f64)
1772 return X86ScalarSSEf64;
1777 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1782 *Fast = Subtarget->isUnalignedMemAccessFast();
1786 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1787 /// current function. The returned value is a member of the
1788 /// MachineJumpTableInfo::JTEntryKind enum.
1789 unsigned X86TargetLowering::getJumpTableEncoding() const {
1790 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1792 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1793 Subtarget->isPICStyleGOT())
1794 return MachineJumpTableInfo::EK_Custom32;
1796 // Otherwise, use the normal jump table encoding heuristics.
1797 return TargetLowering::getJumpTableEncoding();
1801 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1802 const MachineBasicBlock *MBB,
1803 unsigned uid,MCContext &Ctx) const{
1804 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1805 Subtarget->isPICStyleGOT());
1806 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1808 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1809 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1812 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1814 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1815 SelectionDAG &DAG) const {
1816 if (!Subtarget->is64Bit())
1817 // This doesn't have SDLoc associated with it, but is not really the
1818 // same as a Register.
1819 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1823 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1824 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1826 const MCExpr *X86TargetLowering::
1827 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1828 MCContext &Ctx) const {
1829 // X86-64 uses RIP relative addressing based on the jump table label.
1830 if (Subtarget->isPICStyleRIPRel())
1831 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1833 // Otherwise, the reference is relative to the PIC base.
1834 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1837 // FIXME: Why this routine is here? Move to RegInfo!
1838 std::pair<const TargetRegisterClass*, uint8_t>
1839 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1840 const TargetRegisterClass *RRC = nullptr;
1842 switch (VT.SimpleTy) {
1844 return TargetLowering::findRepresentativeClass(VT);
1845 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1846 RRC = Subtarget->is64Bit() ?
1847 (const TargetRegisterClass*)&X86::GR64RegClass :
1848 (const TargetRegisterClass*)&X86::GR32RegClass;
1851 RRC = &X86::VR64RegClass;
1853 case MVT::f32: case MVT::f64:
1854 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1855 case MVT::v4f32: case MVT::v2f64:
1856 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1858 RRC = &X86::VR128RegClass;
1861 return std::make_pair(RRC, Cost);
1864 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1865 unsigned &Offset) const {
1866 if (!Subtarget->isTargetLinux())
1869 if (Subtarget->is64Bit()) {
1870 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1872 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1884 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1885 unsigned DestAS) const {
1886 assert(SrcAS != DestAS && "Expected different address spaces!");
1888 return SrcAS < 256 && DestAS < 256;
1891 //===----------------------------------------------------------------------===//
1892 // Return Value Calling Convention Implementation
1893 //===----------------------------------------------------------------------===//
1895 #include "X86GenCallingConv.inc"
1898 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1899 MachineFunction &MF, bool isVarArg,
1900 const SmallVectorImpl<ISD::OutputArg> &Outs,
1901 LLVMContext &Context) const {
1902 SmallVector<CCValAssign, 16> RVLocs;
1903 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1904 return CCInfo.CheckReturn(Outs, RetCC_X86);
1907 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1908 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1913 X86TargetLowering::LowerReturn(SDValue Chain,
1914 CallingConv::ID CallConv, bool isVarArg,
1915 const SmallVectorImpl<ISD::OutputArg> &Outs,
1916 const SmallVectorImpl<SDValue> &OutVals,
1917 SDLoc dl, SelectionDAG &DAG) const {
1918 MachineFunction &MF = DAG.getMachineFunction();
1919 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1921 SmallVector<CCValAssign, 16> RVLocs;
1922 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1923 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1926 SmallVector<SDValue, 6> RetOps;
1927 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1928 // Operand #1 = Bytes To Pop
1929 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1932 // Copy the result values into the output registers.
1933 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1934 CCValAssign &VA = RVLocs[i];
1935 assert(VA.isRegLoc() && "Can only return in registers!");
1936 SDValue ValToCopy = OutVals[i];
1937 EVT ValVT = ValToCopy.getValueType();
1939 // Promote values to the appropriate types
1940 if (VA.getLocInfo() == CCValAssign::SExt)
1941 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1942 else if (VA.getLocInfo() == CCValAssign::ZExt)
1943 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1944 else if (VA.getLocInfo() == CCValAssign::AExt)
1945 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1946 else if (VA.getLocInfo() == CCValAssign::BCvt)
1947 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1949 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1950 "Unexpected FP-extend for return value.");
1952 // If this is x86-64, and we disabled SSE, we can't return FP values,
1953 // or SSE or MMX vectors.
1954 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1955 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1956 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1957 report_fatal_error("SSE register return with SSE disabled");
1959 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1960 // llvm-gcc has never done it right and no one has noticed, so this
1961 // should be OK for now.
1962 if (ValVT == MVT::f64 &&
1963 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1964 report_fatal_error("SSE2 register return with SSE2 disabled");
1966 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1967 // the RET instruction and handled by the FP Stackifier.
1968 if (VA.getLocReg() == X86::FP0 ||
1969 VA.getLocReg() == X86::FP1) {
1970 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1971 // change the value to the FP stack register class.
1972 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1973 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1974 RetOps.push_back(ValToCopy);
1975 // Don't emit a copytoreg.
1979 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1980 // which is returned in RAX / RDX.
1981 if (Subtarget->is64Bit()) {
1982 if (ValVT == MVT::x86mmx) {
1983 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1984 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1985 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1987 // If we don't have SSE2 available, convert to v4f32 so the generated
1988 // register is legal.
1989 if (!Subtarget->hasSSE2())
1990 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1995 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1996 Flag = Chain.getValue(1);
1997 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2000 // The x86-64 ABIs require that for returning structs by value we copy
2001 // the sret argument into %rax/%eax (depending on ABI) for the return.
2002 // Win32 requires us to put the sret argument to %eax as well.
2003 // We saved the argument into a virtual register in the entry block,
2004 // so now we copy the value out and into %rax/%eax.
2005 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2006 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2007 MachineFunction &MF = DAG.getMachineFunction();
2008 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2009 unsigned Reg = FuncInfo->getSRetReturnReg();
2011 "SRetReturnReg should have been set in LowerFormalArguments().");
2012 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2015 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2016 X86::RAX : X86::EAX;
2017 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2018 Flag = Chain.getValue(1);
2020 // RAX/EAX now acts like a return value.
2021 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2024 RetOps[0] = Chain; // Update chain.
2026 // Add the flag if we have it.
2028 RetOps.push_back(Flag);
2030 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2033 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2034 if (N->getNumValues() != 1)
2036 if (!N->hasNUsesOfValue(1, 0))
2039 SDValue TCChain = Chain;
2040 SDNode *Copy = *N->use_begin();
2041 if (Copy->getOpcode() == ISD::CopyToReg) {
2042 // If the copy has a glue operand, we conservatively assume it isn't safe to
2043 // perform a tail call.
2044 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2046 TCChain = Copy->getOperand(0);
2047 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2050 bool HasRet = false;
2051 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2053 if (UI->getOpcode() != X86ISD::RET_FLAG)
2066 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2067 ISD::NodeType ExtendKind) const {
2069 // TODO: Is this also valid on 32-bit?
2070 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2071 ReturnMVT = MVT::i8;
2073 ReturnMVT = MVT::i32;
2075 EVT MinVT = getRegisterType(Context, ReturnMVT);
2076 return VT.bitsLT(MinVT) ? MinVT : VT;
2079 /// LowerCallResult - Lower the result values of a call into the
2080 /// appropriate copies out of appropriate physical registers.
2083 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2084 CallingConv::ID CallConv, bool isVarArg,
2085 const SmallVectorImpl<ISD::InputArg> &Ins,
2086 SDLoc dl, SelectionDAG &DAG,
2087 SmallVectorImpl<SDValue> &InVals) const {
2089 // Assign locations to each value returned by this call.
2090 SmallVector<CCValAssign, 16> RVLocs;
2091 bool Is64Bit = Subtarget->is64Bit();
2092 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2094 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2096 // Copy all of the result registers out of their specified physreg.
2097 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2098 CCValAssign &VA = RVLocs[i];
2099 EVT CopyVT = VA.getValVT();
2101 // If this is x86-64, and we disabled SSE, we can't return FP values
2102 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2103 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2104 report_fatal_error("SSE register return with SSE disabled");
2107 // If we prefer to use the value in xmm registers, copy it out as f80 and
2108 // use a truncate to move it from fp stack reg to xmm reg.
2109 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2110 isScalarFPTypeInSSEReg(VA.getValVT()))
2113 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2114 CopyVT, InFlag).getValue(1);
2115 SDValue Val = Chain.getValue(0);
2117 if (CopyVT != VA.getValVT())
2118 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2119 // This truncation won't change the value.
2120 DAG.getIntPtrConstant(1));
2122 InFlag = Chain.getValue(2);
2123 InVals.push_back(Val);
2129 //===----------------------------------------------------------------------===//
2130 // C & StdCall & Fast Calling Convention implementation
2131 //===----------------------------------------------------------------------===//
2132 // StdCall calling convention seems to be standard for many Windows' API
2133 // routines and around. It differs from C calling convention just a little:
2134 // callee should clean up the stack, not caller. Symbols should be also
2135 // decorated in some fancy way :) It doesn't support any vector arguments.
2136 // For info on fast calling convention see Fast Calling Convention (tail call)
2137 // implementation LowerX86_32FastCCCallTo.
2139 /// CallIsStructReturn - Determines whether a call uses struct return
2141 enum StructReturnType {
2146 static StructReturnType
2147 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2149 return NotStructReturn;
2151 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2152 if (!Flags.isSRet())
2153 return NotStructReturn;
2154 if (Flags.isInReg())
2155 return RegStructReturn;
2156 return StackStructReturn;
2159 /// ArgsAreStructReturn - Determines whether a function uses struct
2160 /// return semantics.
2161 static StructReturnType
2162 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2164 return NotStructReturn;
2166 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2167 if (!Flags.isSRet())
2168 return NotStructReturn;
2169 if (Flags.isInReg())
2170 return RegStructReturn;
2171 return StackStructReturn;
2174 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2175 /// by "Src" to address "Dst" with size and alignment information specified by
2176 /// the specific parameter attribute. The copy will be passed as a byval
2177 /// function parameter.
2179 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2180 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2182 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2184 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2185 /*isVolatile*/false, /*AlwaysInline=*/true,
2186 MachinePointerInfo(), MachinePointerInfo());
2189 /// IsTailCallConvention - Return true if the calling convention is one that
2190 /// supports tail call optimization.
2191 static bool IsTailCallConvention(CallingConv::ID CC) {
2192 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2193 CC == CallingConv::HiPE);
2196 /// \brief Return true if the calling convention is a C calling convention.
2197 static bool IsCCallConvention(CallingConv::ID CC) {
2198 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2199 CC == CallingConv::X86_64_SysV);
2202 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2203 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2207 CallingConv::ID CalleeCC = CS.getCallingConv();
2208 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2214 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2215 /// a tailcall target by changing its ABI.
2216 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2217 bool GuaranteedTailCallOpt) {
2218 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2222 X86TargetLowering::LowerMemArgument(SDValue Chain,
2223 CallingConv::ID CallConv,
2224 const SmallVectorImpl<ISD::InputArg> &Ins,
2225 SDLoc dl, SelectionDAG &DAG,
2226 const CCValAssign &VA,
2227 MachineFrameInfo *MFI,
2229 // Create the nodes corresponding to a load from this parameter slot.
2230 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2231 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2232 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2233 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2236 // If value is passed by pointer we have address passed instead of the value
2238 if (VA.getLocInfo() == CCValAssign::Indirect)
2239 ValVT = VA.getLocVT();
2241 ValVT = VA.getValVT();
2243 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2244 // changed with more analysis.
2245 // In case of tail call optimization mark all arguments mutable. Since they
2246 // could be overwritten by lowering of arguments in case of a tail call.
2247 if (Flags.isByVal()) {
2248 unsigned Bytes = Flags.getByValSize();
2249 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2250 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2251 return DAG.getFrameIndex(FI, getPointerTy());
2253 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2254 VA.getLocMemOffset(), isImmutable);
2255 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2256 return DAG.getLoad(ValVT, dl, Chain, FIN,
2257 MachinePointerInfo::getFixedStack(FI),
2258 false, false, false, 0);
2263 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2264 CallingConv::ID CallConv,
2266 const SmallVectorImpl<ISD::InputArg> &Ins,
2269 SmallVectorImpl<SDValue> &InVals)
2271 MachineFunction &MF = DAG.getMachineFunction();
2272 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2274 const Function* Fn = MF.getFunction();
2275 if (Fn->hasExternalLinkage() &&
2276 Subtarget->isTargetCygMing() &&
2277 Fn->getName() == "main")
2278 FuncInfo->setForceFramePointer(true);
2280 MachineFrameInfo *MFI = MF.getFrameInfo();
2281 bool Is64Bit = Subtarget->is64Bit();
2282 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2284 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2285 "Var args not supported with calling convention fastcc, ghc or hipe");
2287 // Assign locations to all of the incoming arguments.
2288 SmallVector<CCValAssign, 16> ArgLocs;
2289 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2291 // Allocate shadow area for Win64
2293 CCInfo.AllocateStack(32, 8);
2295 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2297 unsigned LastVal = ~0U;
2299 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2300 CCValAssign &VA = ArgLocs[i];
2301 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2303 assert(VA.getValNo() != LastVal &&
2304 "Don't support value assigned to multiple locs yet");
2306 LastVal = VA.getValNo();
2308 if (VA.isRegLoc()) {
2309 EVT RegVT = VA.getLocVT();
2310 const TargetRegisterClass *RC;
2311 if (RegVT == MVT::i32)
2312 RC = &X86::GR32RegClass;
2313 else if (Is64Bit && RegVT == MVT::i64)
2314 RC = &X86::GR64RegClass;
2315 else if (RegVT == MVT::f32)
2316 RC = &X86::FR32RegClass;
2317 else if (RegVT == MVT::f64)
2318 RC = &X86::FR64RegClass;
2319 else if (RegVT.is512BitVector())
2320 RC = &X86::VR512RegClass;
2321 else if (RegVT.is256BitVector())
2322 RC = &X86::VR256RegClass;
2323 else if (RegVT.is128BitVector())
2324 RC = &X86::VR128RegClass;
2325 else if (RegVT == MVT::x86mmx)
2326 RC = &X86::VR64RegClass;
2327 else if (RegVT == MVT::i1)
2328 RC = &X86::VK1RegClass;
2329 else if (RegVT == MVT::v8i1)
2330 RC = &X86::VK8RegClass;
2331 else if (RegVT == MVT::v16i1)
2332 RC = &X86::VK16RegClass;
2333 else if (RegVT == MVT::v32i1)
2334 RC = &X86::VK32RegClass;
2335 else if (RegVT == MVT::v64i1)
2336 RC = &X86::VK64RegClass;
2338 llvm_unreachable("Unknown argument type!");
2340 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2341 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2343 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2344 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2346 if (VA.getLocInfo() == CCValAssign::SExt)
2347 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2348 DAG.getValueType(VA.getValVT()));
2349 else if (VA.getLocInfo() == CCValAssign::ZExt)
2350 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2351 DAG.getValueType(VA.getValVT()));
2352 else if (VA.getLocInfo() == CCValAssign::BCvt)
2353 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2355 if (VA.isExtInLoc()) {
2356 // Handle MMX values passed in XMM regs.
2357 if (RegVT.isVector())
2358 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2360 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2363 assert(VA.isMemLoc());
2364 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2367 // If value is passed via pointer - do a load.
2368 if (VA.getLocInfo() == CCValAssign::Indirect)
2369 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2370 MachinePointerInfo(), false, false, false, 0);
2372 InVals.push_back(ArgValue);
2375 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2376 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2377 // The x86-64 ABIs require that for returning structs by value we copy
2378 // the sret argument into %rax/%eax (depending on ABI) for the return.
2379 // Win32 requires us to put the sret argument to %eax as well.
2380 // Save the argument into a virtual register so that we can access it
2381 // from the return points.
2382 if (Ins[i].Flags.isSRet()) {
2383 unsigned Reg = FuncInfo->getSRetReturnReg();
2385 MVT PtrTy = getPointerTy();
2386 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2387 FuncInfo->setSRetReturnReg(Reg);
2389 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2390 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2396 unsigned StackSize = CCInfo.getNextStackOffset();
2397 // Align stack specially for tail calls.
2398 if (FuncIsMadeTailCallSafe(CallConv,
2399 MF.getTarget().Options.GuaranteedTailCallOpt))
2400 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2402 // If the function takes variable number of arguments, make a frame index for
2403 // the start of the first vararg value... for expansion of llvm.va_start.
2405 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2406 CallConv != CallingConv::X86_ThisCall)) {
2407 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2410 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2412 // FIXME: We should really autogenerate these arrays
2413 static const MCPhysReg GPR64ArgRegsWin64[] = {
2414 X86::RCX, X86::RDX, X86::R8, X86::R9
2416 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2417 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2419 static const MCPhysReg XMMArgRegs64Bit[] = {
2420 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2421 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2423 const MCPhysReg *GPR64ArgRegs;
2424 unsigned NumXMMRegs = 0;
2427 // The XMM registers which might contain var arg parameters are shadowed
2428 // in their paired GPR. So we only need to save the GPR to their home
2430 TotalNumIntRegs = 4;
2431 GPR64ArgRegs = GPR64ArgRegsWin64;
2433 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2434 GPR64ArgRegs = GPR64ArgRegs64Bit;
2436 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2439 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2442 bool NoImplicitFloatOps = Fn->getAttributes().
2443 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2444 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2445 "SSE register cannot be used when SSE is disabled!");
2446 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2447 NoImplicitFloatOps) &&
2448 "SSE register cannot be used when SSE is disabled!");
2449 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2450 !Subtarget->hasSSE1())
2451 // Kernel mode asks for SSE to be disabled, so don't push them
2453 TotalNumXMMRegs = 0;
2456 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2457 // Get to the caller-allocated home save location. Add 8 to account
2458 // for the return address.
2459 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2460 FuncInfo->setRegSaveFrameIndex(
2461 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2462 // Fixup to set vararg frame on shadow area (4 x i64).
2464 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2466 // For X86-64, if there are vararg parameters that are passed via
2467 // registers, then we must store them to their spots on the stack so
2468 // they may be loaded by deferencing the result of va_next.
2469 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2470 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2471 FuncInfo->setRegSaveFrameIndex(
2472 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2476 // Store the integer parameter registers.
2477 SmallVector<SDValue, 8> MemOps;
2478 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2480 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2481 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2482 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2483 DAG.getIntPtrConstant(Offset));
2484 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2485 &X86::GR64RegClass);
2486 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2488 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2489 MachinePointerInfo::getFixedStack(
2490 FuncInfo->getRegSaveFrameIndex(), Offset),
2492 MemOps.push_back(Store);
2496 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2497 // Now store the XMM (fp + vector) parameter registers.
2498 SmallVector<SDValue, 12> SaveXMMOps;
2499 SaveXMMOps.push_back(Chain);
2501 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2502 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2503 SaveXMMOps.push_back(ALVal);
2505 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2506 FuncInfo->getRegSaveFrameIndex()));
2507 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2508 FuncInfo->getVarArgsFPOffset()));
2510 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2511 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2512 &X86::VR128RegClass);
2513 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2514 SaveXMMOps.push_back(Val);
2516 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2517 MVT::Other, SaveXMMOps));
2520 if (!MemOps.empty())
2521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2525 // Some CCs need callee pop.
2526 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2527 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2528 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2530 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2531 // If this is an sret function, the return should pop the hidden pointer.
2532 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2533 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2534 argsAreStructReturn(Ins) == StackStructReturn)
2535 FuncInfo->setBytesToPopOnReturn(4);
2539 // RegSaveFrameIndex is X86-64 only.
2540 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2541 if (CallConv == CallingConv::X86_FastCall ||
2542 CallConv == CallingConv::X86_ThisCall)
2543 // fastcc functions can't have varargs.
2544 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2547 FuncInfo->setArgumentStackSize(StackSize);
2553 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2554 SDValue StackPtr, SDValue Arg,
2555 SDLoc dl, SelectionDAG &DAG,
2556 const CCValAssign &VA,
2557 ISD::ArgFlagsTy Flags) const {
2558 unsigned LocMemOffset = VA.getLocMemOffset();
2559 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2560 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2561 if (Flags.isByVal())
2562 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2564 return DAG.getStore(Chain, dl, Arg, PtrOff,
2565 MachinePointerInfo::getStack(LocMemOffset),
2569 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2570 /// optimization is performed and it is required.
2572 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2573 SDValue &OutRetAddr, SDValue Chain,
2574 bool IsTailCall, bool Is64Bit,
2575 int FPDiff, SDLoc dl) const {
2576 // Adjust the Return address stack slot.
2577 EVT VT = getPointerTy();
2578 OutRetAddr = getReturnAddressFrameIndex(DAG);
2580 // Load the "old" Return address.
2581 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2582 false, false, false, 0);
2583 return SDValue(OutRetAddr.getNode(), 1);
2586 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2587 /// optimization is performed and it is required (FPDiff!=0).
2588 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2589 SDValue Chain, SDValue RetAddrFrIdx,
2590 EVT PtrVT, unsigned SlotSize,
2591 int FPDiff, SDLoc dl) {
2592 // Store the return address to the appropriate stack slot.
2593 if (!FPDiff) return Chain;
2594 // Calculate the new stack slot for the return address.
2595 int NewReturnAddrFI =
2596 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2598 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2599 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2600 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2606 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2607 SmallVectorImpl<SDValue> &InVals) const {
2608 SelectionDAG &DAG = CLI.DAG;
2610 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2611 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2612 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2613 SDValue Chain = CLI.Chain;
2614 SDValue Callee = CLI.Callee;
2615 CallingConv::ID CallConv = CLI.CallConv;
2616 bool &isTailCall = CLI.IsTailCall;
2617 bool isVarArg = CLI.IsVarArg;
2619 MachineFunction &MF = DAG.getMachineFunction();
2620 bool Is64Bit = Subtarget->is64Bit();
2621 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2622 StructReturnType SR = callIsStructReturn(Outs);
2623 bool IsSibcall = false;
2625 if (MF.getTarget().Options.DisableTailCalls)
2628 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2630 // Force this to be a tail call. The verifier rules are enough to ensure
2631 // that we can lower this successfully without moving the return address
2634 } else if (isTailCall) {
2635 // Check if it's really possible to do a tail call.
2636 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2637 isVarArg, SR != NotStructReturn,
2638 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2639 Outs, OutVals, Ins, DAG);
2641 // Sibcalls are automatically detected tailcalls which do not require
2643 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2650 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2651 "Var args not supported with calling convention fastcc, ghc or hipe");
2653 // Analyze operands of the call, assigning locations to each operand.
2654 SmallVector<CCValAssign, 16> ArgLocs;
2655 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2657 // Allocate shadow area for Win64
2659 CCInfo.AllocateStack(32, 8);
2661 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2663 // Get a count of how many bytes are to be pushed on the stack.
2664 unsigned NumBytes = CCInfo.getNextStackOffset();
2666 // This is a sibcall. The memory operands are available in caller's
2667 // own caller's stack.
2669 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2670 IsTailCallConvention(CallConv))
2671 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2674 if (isTailCall && !IsSibcall && !IsMustTail) {
2675 // Lower arguments at fp - stackoffset + fpdiff.
2676 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2677 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2679 FPDiff = NumBytesCallerPushed - NumBytes;
2681 // Set the delta of movement of the returnaddr stackslot.
2682 // But only set if delta is greater than previous delta.
2683 if (FPDiff < X86Info->getTCReturnAddrDelta())
2684 X86Info->setTCReturnAddrDelta(FPDiff);
2687 unsigned NumBytesToPush = NumBytes;
2688 unsigned NumBytesToPop = NumBytes;
2690 // If we have an inalloca argument, all stack space has already been allocated
2691 // for us and be right at the top of the stack. We don't support multiple
2692 // arguments passed in memory when using inalloca.
2693 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2695 if (!ArgLocs.back().isMemLoc())
2696 report_fatal_error("cannot use inalloca attribute on a register "
2698 if (ArgLocs.back().getLocMemOffset() != 0)
2699 report_fatal_error("any parameter with the inalloca attribute must be "
2700 "the only memory argument");
2704 Chain = DAG.getCALLSEQ_START(
2705 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2707 SDValue RetAddrFrIdx;
2708 // Load return address for tail calls.
2709 if (isTailCall && FPDiff)
2710 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2711 Is64Bit, FPDiff, dl);
2713 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2714 SmallVector<SDValue, 8> MemOpChains;
2717 // Walk the register/memloc assignments, inserting copies/loads. In the case
2718 // of tail call optimization arguments are handle later.
2719 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2720 DAG.getSubtarget().getRegisterInfo());
2721 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2722 // Skip inalloca arguments, they have already been written.
2723 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2724 if (Flags.isInAlloca())
2727 CCValAssign &VA = ArgLocs[i];
2728 EVT RegVT = VA.getLocVT();
2729 SDValue Arg = OutVals[i];
2730 bool isByVal = Flags.isByVal();
2732 // Promote the value if needed.
2733 switch (VA.getLocInfo()) {
2734 default: llvm_unreachable("Unknown loc info!");
2735 case CCValAssign::Full: break;
2736 case CCValAssign::SExt:
2737 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2739 case CCValAssign::ZExt:
2740 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2742 case CCValAssign::AExt:
2743 if (RegVT.is128BitVector()) {
2744 // Special case: passing MMX values in XMM registers.
2745 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2746 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2747 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2749 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2751 case CCValAssign::BCvt:
2752 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2754 case CCValAssign::Indirect: {
2755 // Store the argument.
2756 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2757 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2758 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2759 MachinePointerInfo::getFixedStack(FI),
2766 if (VA.isRegLoc()) {
2767 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2768 if (isVarArg && IsWin64) {
2769 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2770 // shadow reg if callee is a varargs function.
2771 unsigned ShadowReg = 0;
2772 switch (VA.getLocReg()) {
2773 case X86::XMM0: ShadowReg = X86::RCX; break;
2774 case X86::XMM1: ShadowReg = X86::RDX; break;
2775 case X86::XMM2: ShadowReg = X86::R8; break;
2776 case X86::XMM3: ShadowReg = X86::R9; break;
2779 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2781 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2782 assert(VA.isMemLoc());
2783 if (!StackPtr.getNode())
2784 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2786 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2787 dl, DAG, VA, Flags));
2791 if (!MemOpChains.empty())
2792 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2794 if (Subtarget->isPICStyleGOT()) {
2795 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2798 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2799 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2801 // If we are tail calling and generating PIC/GOT style code load the
2802 // address of the callee into ECX. The value in ecx is used as target of
2803 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2804 // for tail calls on PIC/GOT architectures. Normally we would just put the
2805 // address of GOT into ebx and then call target@PLT. But for tail calls
2806 // ebx would be restored (since ebx is callee saved) before jumping to the
2809 // Note: The actual moving to ECX is done further down.
2810 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2811 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2812 !G->getGlobal()->hasProtectedVisibility())
2813 Callee = LowerGlobalAddress(Callee, DAG);
2814 else if (isa<ExternalSymbolSDNode>(Callee))
2815 Callee = LowerExternalSymbol(Callee, DAG);
2819 if (Is64Bit && isVarArg && !IsWin64) {
2820 // From AMD64 ABI document:
2821 // For calls that may call functions that use varargs or stdargs
2822 // (prototype-less calls or calls to functions containing ellipsis (...) in
2823 // the declaration) %al is used as hidden argument to specify the number
2824 // of SSE registers used. The contents of %al do not need to match exactly
2825 // the number of registers, but must be an ubound on the number of SSE
2826 // registers used and is in the range 0 - 8 inclusive.
2828 // Count the number of XMM registers allocated.
2829 static const MCPhysReg XMMArgRegs[] = {
2830 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2831 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2833 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2834 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2835 && "SSE registers cannot be used when SSE is disabled");
2837 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2838 DAG.getConstant(NumXMMRegs, MVT::i8)));
2841 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2842 // don't need this because the eligibility check rejects calls that require
2843 // shuffling arguments passed in memory.
2844 if (!IsSibcall && isTailCall) {
2845 // Force all the incoming stack arguments to be loaded from the stack
2846 // before any new outgoing arguments are stored to the stack, because the
2847 // outgoing stack slots may alias the incoming argument stack slots, and
2848 // the alias isn't otherwise explicit. This is slightly more conservative
2849 // than necessary, because it means that each store effectively depends
2850 // on every argument instead of just those arguments it would clobber.
2851 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2853 SmallVector<SDValue, 8> MemOpChains2;
2856 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2857 CCValAssign &VA = ArgLocs[i];
2860 assert(VA.isMemLoc());
2861 SDValue Arg = OutVals[i];
2862 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2863 // Skip inalloca arguments. They don't require any work.
2864 if (Flags.isInAlloca())
2866 // Create frame index.
2867 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2868 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2869 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2870 FIN = DAG.getFrameIndex(FI, getPointerTy());
2872 if (Flags.isByVal()) {
2873 // Copy relative to framepointer.
2874 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2875 if (!StackPtr.getNode())
2876 StackPtr = DAG.getCopyFromReg(Chain, dl,
2877 RegInfo->getStackRegister(),
2879 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2881 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2885 // Store relative to framepointer.
2886 MemOpChains2.push_back(
2887 DAG.getStore(ArgChain, dl, Arg, FIN,
2888 MachinePointerInfo::getFixedStack(FI),
2893 if (!MemOpChains2.empty())
2894 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2896 // Store the return address to the appropriate stack slot.
2897 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2898 getPointerTy(), RegInfo->getSlotSize(),
2902 // Build a sequence of copy-to-reg nodes chained together with token chain
2903 // and flag operands which copy the outgoing args into registers.
2905 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2906 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2907 RegsToPass[i].second, InFlag);
2908 InFlag = Chain.getValue(1);
2911 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2912 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2913 // In the 64-bit large code model, we have to make all calls
2914 // through a register, since the call instruction's 32-bit
2915 // pc-relative offset may not be large enough to hold the whole
2917 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2918 // If the callee is a GlobalAddress node (quite common, every direct call
2919 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2922 // We should use extra load for direct calls to dllimported functions in
2924 const GlobalValue *GV = G->getGlobal();
2925 if (!GV->hasDLLImportStorageClass()) {
2926 unsigned char OpFlags = 0;
2927 bool ExtraLoad = false;
2928 unsigned WrapperKind = ISD::DELETED_NODE;
2930 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2931 // external symbols most go through the PLT in PIC mode. If the symbol
2932 // has hidden or protected visibility, or if it is static or local, then
2933 // we don't need to use the PLT - we can directly call it.
2934 if (Subtarget->isTargetELF() &&
2935 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2936 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2937 OpFlags = X86II::MO_PLT;
2938 } else if (Subtarget->isPICStyleStubAny() &&
2939 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2940 (!Subtarget->getTargetTriple().isMacOSX() ||
2941 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2942 // PC-relative references to external symbols should go through $stub,
2943 // unless we're building with the leopard linker or later, which
2944 // automatically synthesizes these stubs.
2945 OpFlags = X86II::MO_DARWIN_STUB;
2946 } else if (Subtarget->isPICStyleRIPRel() &&
2947 isa<Function>(GV) &&
2948 cast<Function>(GV)->getAttributes().
2949 hasAttribute(AttributeSet::FunctionIndex,
2950 Attribute::NonLazyBind)) {
2951 // If the function is marked as non-lazy, generate an indirect call
2952 // which loads from the GOT directly. This avoids runtime overhead
2953 // at the cost of eager binding (and one extra byte of encoding).
2954 OpFlags = X86II::MO_GOTPCREL;
2955 WrapperKind = X86ISD::WrapperRIP;
2959 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2960 G->getOffset(), OpFlags);
2962 // Add a wrapper if needed.
2963 if (WrapperKind != ISD::DELETED_NODE)
2964 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2965 // Add extra indirection if needed.
2967 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2968 MachinePointerInfo::getGOT(),
2969 false, false, false, 0);
2971 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2972 unsigned char OpFlags = 0;
2974 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2975 // external symbols should go through the PLT.
2976 if (Subtarget->isTargetELF() &&
2977 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2978 OpFlags = X86II::MO_PLT;
2979 } else if (Subtarget->isPICStyleStubAny() &&
2980 (!Subtarget->getTargetTriple().isMacOSX() ||
2981 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2982 // PC-relative references to external symbols should go through $stub,
2983 // unless we're building with the leopard linker or later, which
2984 // automatically synthesizes these stubs.
2985 OpFlags = X86II::MO_DARWIN_STUB;
2988 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2992 // Returns a chain & a flag for retval copy to use.
2993 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2994 SmallVector<SDValue, 8> Ops;
2996 if (!IsSibcall && isTailCall) {
2997 Chain = DAG.getCALLSEQ_END(Chain,
2998 DAG.getIntPtrConstant(NumBytesToPop, true),
2999 DAG.getIntPtrConstant(0, true), InFlag, dl);
3000 InFlag = Chain.getValue(1);
3003 Ops.push_back(Chain);
3004 Ops.push_back(Callee);
3007 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3009 // Add argument registers to the end of the list so that they are known live
3011 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3012 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3013 RegsToPass[i].second.getValueType()));
3015 // Add a register mask operand representing the call-preserved registers.
3016 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3017 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3018 assert(Mask && "Missing call preserved mask for calling convention");
3019 Ops.push_back(DAG.getRegisterMask(Mask));
3021 if (InFlag.getNode())
3022 Ops.push_back(InFlag);
3026 //// If this is the first return lowered for this function, add the regs
3027 //// to the liveout set for the function.
3028 // This isn't right, although it's probably harmless on x86; liveouts
3029 // should be computed from returns not tail calls. Consider a void
3030 // function making a tail call to a function returning int.
3031 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3034 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3035 InFlag = Chain.getValue(1);
3037 // Create the CALLSEQ_END node.
3038 unsigned NumBytesForCalleeToPop;
3039 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3040 DAG.getTarget().Options.GuaranteedTailCallOpt))
3041 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3042 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3043 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3044 SR == StackStructReturn)
3045 // If this is a call to a struct-return function, the callee
3046 // pops the hidden struct pointer, so we have to push it back.
3047 // This is common for Darwin/X86, Linux & Mingw32 targets.
3048 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3049 NumBytesForCalleeToPop = 4;
3051 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3053 // Returns a flag for retval copy to use.
3055 Chain = DAG.getCALLSEQ_END(Chain,
3056 DAG.getIntPtrConstant(NumBytesToPop, true),
3057 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3060 InFlag = Chain.getValue(1);
3063 // Handle result values, copying them out of physregs into vregs that we
3065 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3066 Ins, dl, DAG, InVals);
3069 //===----------------------------------------------------------------------===//
3070 // Fast Calling Convention (tail call) implementation
3071 //===----------------------------------------------------------------------===//
3073 // Like std call, callee cleans arguments, convention except that ECX is
3074 // reserved for storing the tail called function address. Only 2 registers are
3075 // free for argument passing (inreg). Tail call optimization is performed
3077 // * tailcallopt is enabled
3078 // * caller/callee are fastcc
3079 // On X86_64 architecture with GOT-style position independent code only local
3080 // (within module) calls are supported at the moment.
3081 // To keep the stack aligned according to platform abi the function
3082 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3083 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3084 // If a tail called function callee has more arguments than the caller the
3085 // caller needs to make sure that there is room to move the RETADDR to. This is
3086 // achieved by reserving an area the size of the argument delta right after the
3087 // original RETADDR, but before the saved framepointer or the spilled registers
3088 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3100 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3101 /// for a 16 byte align requirement.
3103 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3104 SelectionDAG& DAG) const {
3105 MachineFunction &MF = DAG.getMachineFunction();
3106 const TargetMachine &TM = MF.getTarget();
3107 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3108 TM.getSubtargetImpl()->getRegisterInfo());
3109 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3110 unsigned StackAlignment = TFI.getStackAlignment();
3111 uint64_t AlignMask = StackAlignment - 1;
3112 int64_t Offset = StackSize;
3113 unsigned SlotSize = RegInfo->getSlotSize();
3114 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3115 // Number smaller than 12 so just add the difference.
3116 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3118 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3119 Offset = ((~AlignMask) & Offset) + StackAlignment +
3120 (StackAlignment-SlotSize);
3125 /// MatchingStackOffset - Return true if the given stack call argument is
3126 /// already available in the same position (relatively) of the caller's
3127 /// incoming argument stack.
3129 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3130 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3131 const X86InstrInfo *TII) {
3132 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3134 if (Arg.getOpcode() == ISD::CopyFromReg) {
3135 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3136 if (!TargetRegisterInfo::isVirtualRegister(VR))
3138 MachineInstr *Def = MRI->getVRegDef(VR);
3141 if (!Flags.isByVal()) {
3142 if (!TII->isLoadFromStackSlot(Def, FI))
3145 unsigned Opcode = Def->getOpcode();
3146 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3147 Def->getOperand(1).isFI()) {
3148 FI = Def->getOperand(1).getIndex();
3149 Bytes = Flags.getByValSize();
3153 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3154 if (Flags.isByVal())
3155 // ByVal argument is passed in as a pointer but it's now being
3156 // dereferenced. e.g.
3157 // define @foo(%struct.X* %A) {
3158 // tail call @bar(%struct.X* byval %A)
3161 SDValue Ptr = Ld->getBasePtr();
3162 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3165 FI = FINode->getIndex();
3166 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3167 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3168 FI = FINode->getIndex();
3169 Bytes = Flags.getByValSize();
3173 assert(FI != INT_MAX);
3174 if (!MFI->isFixedObjectIndex(FI))
3176 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3179 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3180 /// for tail call optimization. Targets which want to do tail call
3181 /// optimization should implement this function.
3183 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3184 CallingConv::ID CalleeCC,
3186 bool isCalleeStructRet,
3187 bool isCallerStructRet,
3189 const SmallVectorImpl<ISD::OutputArg> &Outs,
3190 const SmallVectorImpl<SDValue> &OutVals,
3191 const SmallVectorImpl<ISD::InputArg> &Ins,
3192 SelectionDAG &DAG) const {
3193 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3196 // If -tailcallopt is specified, make fastcc functions tail-callable.
3197 const MachineFunction &MF = DAG.getMachineFunction();
3198 const Function *CallerF = MF.getFunction();
3200 // If the function return type is x86_fp80 and the callee return type is not,
3201 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3202 // perform a tailcall optimization here.
3203 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3206 CallingConv::ID CallerCC = CallerF->getCallingConv();
3207 bool CCMatch = CallerCC == CalleeCC;
3208 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3209 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3211 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3212 if (IsTailCallConvention(CalleeCC) && CCMatch)
3217 // Look for obvious safe cases to perform tail call optimization that do not
3218 // require ABI changes. This is what gcc calls sibcall.
3220 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3221 // emit a special epilogue.
3222 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3223 DAG.getSubtarget().getRegisterInfo());
3224 if (RegInfo->needsStackRealignment(MF))
3227 // Also avoid sibcall optimization if either caller or callee uses struct
3228 // return semantics.
3229 if (isCalleeStructRet || isCallerStructRet)
3232 // An stdcall/thiscall caller is expected to clean up its arguments; the
3233 // callee isn't going to do that.
3234 // FIXME: this is more restrictive than needed. We could produce a tailcall
3235 // when the stack adjustment matches. For example, with a thiscall that takes
3236 // only one argument.
3237 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3238 CallerCC == CallingConv::X86_ThisCall))
3241 // Do not sibcall optimize vararg calls unless all arguments are passed via
3243 if (isVarArg && !Outs.empty()) {
3245 // Optimizing for varargs on Win64 is unlikely to be safe without
3246 // additional testing.
3247 if (IsCalleeWin64 || IsCallerWin64)
3250 SmallVector<CCValAssign, 16> ArgLocs;
3251 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3254 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3255 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3256 if (!ArgLocs[i].isRegLoc())
3260 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3261 // stack. Therefore, if it's not used by the call it is not safe to optimize
3262 // this into a sibcall.
3263 bool Unused = false;
3264 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3271 SmallVector<CCValAssign, 16> RVLocs;
3272 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3274 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3275 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3276 CCValAssign &VA = RVLocs[i];
3277 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3282 // If the calling conventions do not match, then we'd better make sure the
3283 // results are returned in the same way as what the caller expects.
3285 SmallVector<CCValAssign, 16> RVLocs1;
3286 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3288 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3290 SmallVector<CCValAssign, 16> RVLocs2;
3291 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3293 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3295 if (RVLocs1.size() != RVLocs2.size())
3297 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3298 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3300 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3302 if (RVLocs1[i].isRegLoc()) {
3303 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3306 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3312 // If the callee takes no arguments then go on to check the results of the
3314 if (!Outs.empty()) {
3315 // Check if stack adjustment is needed. For now, do not do this if any
3316 // argument is passed on the stack.
3317 SmallVector<CCValAssign, 16> ArgLocs;
3318 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3321 // Allocate shadow area for Win64
3323 CCInfo.AllocateStack(32, 8);
3325 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3326 if (CCInfo.getNextStackOffset()) {
3327 MachineFunction &MF = DAG.getMachineFunction();
3328 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3331 // Check if the arguments are already laid out in the right way as
3332 // the caller's fixed stack objects.
3333 MachineFrameInfo *MFI = MF.getFrameInfo();
3334 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3335 const X86InstrInfo *TII =
3336 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3337 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3338 CCValAssign &VA = ArgLocs[i];
3339 SDValue Arg = OutVals[i];
3340 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3341 if (VA.getLocInfo() == CCValAssign::Indirect)
3343 if (!VA.isRegLoc()) {
3344 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3351 // If the tailcall address may be in a register, then make sure it's
3352 // possible to register allocate for it. In 32-bit, the call address can
3353 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3354 // callee-saved registers are restored. These happen to be the same
3355 // registers used to pass 'inreg' arguments so watch out for those.
3356 if (!Subtarget->is64Bit() &&
3357 ((!isa<GlobalAddressSDNode>(Callee) &&
3358 !isa<ExternalSymbolSDNode>(Callee)) ||
3359 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3360 unsigned NumInRegs = 0;
3361 // In PIC we need an extra register to formulate the address computation
3363 unsigned MaxInRegs =
3364 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3366 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3367 CCValAssign &VA = ArgLocs[i];
3370 unsigned Reg = VA.getLocReg();
3373 case X86::EAX: case X86::EDX: case X86::ECX:
3374 if (++NumInRegs == MaxInRegs)
3386 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3387 const TargetLibraryInfo *libInfo) const {
3388 return X86::createFastISel(funcInfo, libInfo);
3391 //===----------------------------------------------------------------------===//
3392 // Other Lowering Hooks
3393 //===----------------------------------------------------------------------===//
3395 static bool MayFoldLoad(SDValue Op) {
3396 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3399 static bool MayFoldIntoStore(SDValue Op) {
3400 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3403 static bool isTargetShuffle(unsigned Opcode) {
3405 default: return false;
3406 case X86ISD::PSHUFB:
3407 case X86ISD::PSHUFD:
3408 case X86ISD::PSHUFHW:
3409 case X86ISD::PSHUFLW:
3411 case X86ISD::PALIGNR:
3412 case X86ISD::MOVLHPS:
3413 case X86ISD::MOVLHPD:
3414 case X86ISD::MOVHLPS:
3415 case X86ISD::MOVLPS:
3416 case X86ISD::MOVLPD:
3417 case X86ISD::MOVSHDUP:
3418 case X86ISD::MOVSLDUP:
3419 case X86ISD::MOVDDUP:
3422 case X86ISD::UNPCKL:
3423 case X86ISD::UNPCKH:
3424 case X86ISD::VPERMILP:
3425 case X86ISD::VPERM2X128:
3426 case X86ISD::VPERMI:
3431 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3432 SDValue V1, SelectionDAG &DAG) {
3434 default: llvm_unreachable("Unknown x86 shuffle node");
3435 case X86ISD::MOVSHDUP:
3436 case X86ISD::MOVSLDUP:
3437 case X86ISD::MOVDDUP:
3438 return DAG.getNode(Opc, dl, VT, V1);
3442 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3443 SDValue V1, unsigned TargetMask,
3444 SelectionDAG &DAG) {
3446 default: llvm_unreachable("Unknown x86 shuffle node");
3447 case X86ISD::PSHUFD:
3448 case X86ISD::PSHUFHW:
3449 case X86ISD::PSHUFLW:
3450 case X86ISD::VPERMILP:
3451 case X86ISD::VPERMI:
3452 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3456 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3457 SDValue V1, SDValue V2, unsigned TargetMask,
3458 SelectionDAG &DAG) {
3460 default: llvm_unreachable("Unknown x86 shuffle node");
3461 case X86ISD::PALIGNR:
3462 case X86ISD::VALIGN:
3464 case X86ISD::VPERM2X128:
3465 return DAG.getNode(Opc, dl, VT, V1, V2,
3466 DAG.getConstant(TargetMask, MVT::i8));
3470 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3471 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3473 default: llvm_unreachable("Unknown x86 shuffle node");
3474 case X86ISD::MOVLHPS:
3475 case X86ISD::MOVLHPD:
3476 case X86ISD::MOVHLPS:
3477 case X86ISD::MOVLPS:
3478 case X86ISD::MOVLPD:
3481 case X86ISD::UNPCKL:
3482 case X86ISD::UNPCKH:
3483 return DAG.getNode(Opc, dl, VT, V1, V2);
3487 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3488 MachineFunction &MF = DAG.getMachineFunction();
3489 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3490 DAG.getSubtarget().getRegisterInfo());
3491 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3492 int ReturnAddrIndex = FuncInfo->getRAIndex();
3494 if (ReturnAddrIndex == 0) {
3495 // Set up a frame object for the return address.
3496 unsigned SlotSize = RegInfo->getSlotSize();
3497 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3500 FuncInfo->setRAIndex(ReturnAddrIndex);
3503 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3506 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3507 bool hasSymbolicDisplacement) {
3508 // Offset should fit into 32 bit immediate field.
3509 if (!isInt<32>(Offset))
3512 // If we don't have a symbolic displacement - we don't have any extra
3514 if (!hasSymbolicDisplacement)
3517 // FIXME: Some tweaks might be needed for medium code model.
3518 if (M != CodeModel::Small && M != CodeModel::Kernel)
3521 // For small code model we assume that latest object is 16MB before end of 31
3522 // bits boundary. We may also accept pretty large negative constants knowing
3523 // that all objects are in the positive half of address space.
3524 if (M == CodeModel::Small && Offset < 16*1024*1024)
3527 // For kernel code model we know that all object resist in the negative half
3528 // of 32bits address space. We may not accept negative offsets, since they may
3529 // be just off and we may accept pretty large positive ones.
3530 if (M == CodeModel::Kernel && Offset > 0)
3536 /// isCalleePop - Determines whether the callee is required to pop its
3537 /// own arguments. Callee pop is necessary to support tail calls.
3538 bool X86::isCalleePop(CallingConv::ID CallingConv,
3539 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3543 switch (CallingConv) {
3546 case CallingConv::X86_StdCall:
3548 case CallingConv::X86_FastCall:
3550 case CallingConv::X86_ThisCall:
3552 case CallingConv::Fast:
3554 case CallingConv::GHC:
3556 case CallingConv::HiPE:
3561 /// \brief Return true if the condition is an unsigned comparison operation.
3562 static bool isX86CCUnsigned(unsigned X86CC) {
3564 default: llvm_unreachable("Invalid integer condition!");
3565 case X86::COND_E: return true;
3566 case X86::COND_G: return false;
3567 case X86::COND_GE: return false;
3568 case X86::COND_L: return false;
3569 case X86::COND_LE: return false;
3570 case X86::COND_NE: return true;
3571 case X86::COND_B: return true;
3572 case X86::COND_A: return true;
3573 case X86::COND_BE: return true;
3574 case X86::COND_AE: return true;
3576 llvm_unreachable("covered switch fell through?!");
3579 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3580 /// specific condition code, returning the condition code and the LHS/RHS of the
3581 /// comparison to make.
3582 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3583 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3585 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3586 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3587 // X > -1 -> X == 0, jump !sign.
3588 RHS = DAG.getConstant(0, RHS.getValueType());
3589 return X86::COND_NS;
3591 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3592 // X < 0 -> X == 0, jump on sign.
3595 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3597 RHS = DAG.getConstant(0, RHS.getValueType());
3598 return X86::COND_LE;
3602 switch (SetCCOpcode) {
3603 default: llvm_unreachable("Invalid integer condition!");
3604 case ISD::SETEQ: return X86::COND_E;
3605 case ISD::SETGT: return X86::COND_G;
3606 case ISD::SETGE: return X86::COND_GE;
3607 case ISD::SETLT: return X86::COND_L;
3608 case ISD::SETLE: return X86::COND_LE;
3609 case ISD::SETNE: return X86::COND_NE;
3610 case ISD::SETULT: return X86::COND_B;
3611 case ISD::SETUGT: return X86::COND_A;
3612 case ISD::SETULE: return X86::COND_BE;
3613 case ISD::SETUGE: return X86::COND_AE;
3617 // First determine if it is required or is profitable to flip the operands.
3619 // If LHS is a foldable load, but RHS is not, flip the condition.
3620 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3621 !ISD::isNON_EXTLoad(RHS.getNode())) {
3622 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3623 std::swap(LHS, RHS);
3626 switch (SetCCOpcode) {
3632 std::swap(LHS, RHS);
3636 // On a floating point condition, the flags are set as follows:
3638 // 0 | 0 | 0 | X > Y
3639 // 0 | 0 | 1 | X < Y
3640 // 1 | 0 | 0 | X == Y
3641 // 1 | 1 | 1 | unordered
3642 switch (SetCCOpcode) {
3643 default: llvm_unreachable("Condcode should be pre-legalized away");
3645 case ISD::SETEQ: return X86::COND_E;
3646 case ISD::SETOLT: // flipped
3648 case ISD::SETGT: return X86::COND_A;
3649 case ISD::SETOLE: // flipped
3651 case ISD::SETGE: return X86::COND_AE;
3652 case ISD::SETUGT: // flipped
3654 case ISD::SETLT: return X86::COND_B;
3655 case ISD::SETUGE: // flipped
3657 case ISD::SETLE: return X86::COND_BE;
3659 case ISD::SETNE: return X86::COND_NE;
3660 case ISD::SETUO: return X86::COND_P;
3661 case ISD::SETO: return X86::COND_NP;
3663 case ISD::SETUNE: return X86::COND_INVALID;
3667 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3668 /// code. Current x86 isa includes the following FP cmov instructions:
3669 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3670 static bool hasFPCMov(unsigned X86CC) {
3686 /// isFPImmLegal - Returns true if the target can instruction select the
3687 /// specified FP immediate natively. If false, the legalizer will
3688 /// materialize the FP immediate as a load from a constant pool.
3689 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3690 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3691 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3697 /// \brief Returns true if it is beneficial to convert a load of a constant
3698 /// to just the constant itself.
3699 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3701 assert(Ty->isIntegerTy());
3703 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3704 if (BitSize == 0 || BitSize > 64)
3709 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3710 /// the specified range (L, H].
3711 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3712 return (Val < 0) || (Val >= Low && Val < Hi);
3715 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3716 /// specified value.
3717 static bool isUndefOrEqual(int Val, int CmpVal) {
3718 return (Val < 0 || Val == CmpVal);
3721 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3722 /// from position Pos and ending in Pos+Size, falls within the specified
3723 /// sequential range (L, L+Pos]. or is undef.
3724 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3725 unsigned Pos, unsigned Size, int Low) {
3726 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3727 if (!isUndefOrEqual(Mask[i], Low))
3732 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3733 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3734 /// the second operand.
3735 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3736 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3737 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3738 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3739 return (Mask[0] < 2 && Mask[1] < 2);
3743 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3744 /// is suitable for input to PSHUFHW.
3745 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3746 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3749 // Lower quadword copied in order or undef.
3750 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3753 // Upper quadword shuffled.
3754 for (unsigned i = 4; i != 8; ++i)
3755 if (!isUndefOrInRange(Mask[i], 4, 8))
3758 if (VT == MVT::v16i16) {
3759 // Lower quadword copied in order or undef.
3760 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3763 // Upper quadword shuffled.
3764 for (unsigned i = 12; i != 16; ++i)
3765 if (!isUndefOrInRange(Mask[i], 12, 16))
3772 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3773 /// is suitable for input to PSHUFLW.
3774 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3775 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3778 // Upper quadword copied in order.
3779 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3782 // Lower quadword shuffled.
3783 for (unsigned i = 0; i != 4; ++i)
3784 if (!isUndefOrInRange(Mask[i], 0, 4))
3787 if (VT == MVT::v16i16) {
3788 // Upper quadword copied in order.
3789 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3792 // Lower quadword shuffled.
3793 for (unsigned i = 8; i != 12; ++i)
3794 if (!isUndefOrInRange(Mask[i], 8, 12))
3801 /// \brief Return true if the mask specifies a shuffle of elements that is
3802 /// suitable for input to intralane (palignr) or interlane (valign) vector
3804 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3805 unsigned NumElts = VT.getVectorNumElements();
3806 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3807 unsigned NumLaneElts = NumElts/NumLanes;
3809 // Do not handle 64-bit element shuffles with palignr.
3810 if (NumLaneElts == 2)
3813 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3815 for (i = 0; i != NumLaneElts; ++i) {
3820 // Lane is all undef, go to next lane
3821 if (i == NumLaneElts)
3824 int Start = Mask[i+l];
3826 // Make sure its in this lane in one of the sources
3827 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3828 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3831 // If not lane 0, then we must match lane 0
3832 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3835 // Correct second source to be contiguous with first source
3836 if (Start >= (int)NumElts)
3837 Start -= NumElts - NumLaneElts;
3839 // Make sure we're shifting in the right direction.
3840 if (Start <= (int)(i+l))
3845 // Check the rest of the elements to see if they are consecutive.
3846 for (++i; i != NumLaneElts; ++i) {
3847 int Idx = Mask[i+l];
3849 // Make sure its in this lane
3850 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3851 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3854 // If not lane 0, then we must match lane 0
3855 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3858 if (Idx >= (int)NumElts)
3859 Idx -= NumElts - NumLaneElts;
3861 if (!isUndefOrEqual(Idx, Start+i))
3870 /// \brief Return true if the node specifies a shuffle of elements that is
3871 /// suitable for input to PALIGNR.
3872 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3873 const X86Subtarget *Subtarget) {
3874 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3875 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
3876 VT.is512BitVector())
3877 // FIXME: Add AVX512BW.
3880 return isAlignrMask(Mask, VT, false);
3883 /// \brief Return true if the node specifies a shuffle of elements that is
3884 /// suitable for input to VALIGN.
3885 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
3886 const X86Subtarget *Subtarget) {
3887 // FIXME: Add AVX512VL.
3888 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
3890 return isAlignrMask(Mask, VT, true);
3893 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3894 /// the two vector operands have swapped position.
3895 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3896 unsigned NumElems) {
3897 for (unsigned i = 0; i != NumElems; ++i) {
3901 else if (idx < (int)NumElems)
3902 Mask[i] = idx + NumElems;
3904 Mask[i] = idx - NumElems;
3908 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3909 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3910 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3911 /// reverse of what x86 shuffles want.
3912 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3914 unsigned NumElems = VT.getVectorNumElements();
3915 unsigned NumLanes = VT.getSizeInBits()/128;
3916 unsigned NumLaneElems = NumElems/NumLanes;
3918 if (NumLaneElems != 2 && NumLaneElems != 4)
3921 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3922 bool symetricMaskRequired =
3923 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3925 // VSHUFPSY divides the resulting vector into 4 chunks.
3926 // The sources are also splitted into 4 chunks, and each destination
3927 // chunk must come from a different source chunk.
3929 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3930 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3932 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3933 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3935 // VSHUFPDY divides the resulting vector into 4 chunks.
3936 // The sources are also splitted into 4 chunks, and each destination
3937 // chunk must come from a different source chunk.
3939 // SRC1 => X3 X2 X1 X0
3940 // SRC2 => Y3 Y2 Y1 Y0
3942 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3944 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3945 unsigned HalfLaneElems = NumLaneElems/2;
3946 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3947 for (unsigned i = 0; i != NumLaneElems; ++i) {
3948 int Idx = Mask[i+l];
3949 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3950 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3952 // For VSHUFPSY, the mask of the second half must be the same as the
3953 // first but with the appropriate offsets. This works in the same way as
3954 // VPERMILPS works with masks.
3955 if (!symetricMaskRequired || Idx < 0)
3957 if (MaskVal[i] < 0) {
3958 MaskVal[i] = Idx - l;
3961 if ((signed)(Idx - l) != MaskVal[i])
3969 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3970 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3971 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3972 if (!VT.is128BitVector())
3975 unsigned NumElems = VT.getVectorNumElements();
3980 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3981 return isUndefOrEqual(Mask[0], 6) &&
3982 isUndefOrEqual(Mask[1], 7) &&
3983 isUndefOrEqual(Mask[2], 2) &&
3984 isUndefOrEqual(Mask[3], 3);
3987 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3988 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3990 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3991 if (!VT.is128BitVector())
3994 unsigned NumElems = VT.getVectorNumElements();
3999 return isUndefOrEqual(Mask[0], 2) &&
4000 isUndefOrEqual(Mask[1], 3) &&
4001 isUndefOrEqual(Mask[2], 2) &&
4002 isUndefOrEqual(Mask[3], 3);
4005 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4006 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4007 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4008 if (!VT.is128BitVector())
4011 unsigned NumElems = VT.getVectorNumElements();
4013 if (NumElems != 2 && NumElems != 4)
4016 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4017 if (!isUndefOrEqual(Mask[i], i + NumElems))
4020 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4021 if (!isUndefOrEqual(Mask[i], i))
4027 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4028 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4029 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4030 if (!VT.is128BitVector())
4033 unsigned NumElems = VT.getVectorNumElements();
4035 if (NumElems != 2 && NumElems != 4)
4038 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4039 if (!isUndefOrEqual(Mask[i], i))
4042 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4043 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4049 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4050 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4051 /// i. e: If all but one element come from the same vector.
4052 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4053 // TODO: Deal with AVX's VINSERTPS
4054 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4057 unsigned CorrectPosV1 = 0;
4058 unsigned CorrectPosV2 = 0;
4059 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4060 if (Mask[i] == -1) {
4068 else if (Mask[i] == i + 4)
4072 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4073 // We have 3 elements (undefs count as elements from any vector) from one
4074 // vector, and one from another.
4081 // Some special combinations that can be optimized.
4084 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4085 SelectionDAG &DAG) {
4086 MVT VT = SVOp->getSimpleValueType(0);
4089 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4092 ArrayRef<int> Mask = SVOp->getMask();
4094 // These are the special masks that may be optimized.
4095 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4096 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4097 bool MatchEvenMask = true;
4098 bool MatchOddMask = true;
4099 for (int i=0; i<8; ++i) {
4100 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4101 MatchEvenMask = false;
4102 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4103 MatchOddMask = false;
4106 if (!MatchEvenMask && !MatchOddMask)
4109 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4111 SDValue Op0 = SVOp->getOperand(0);
4112 SDValue Op1 = SVOp->getOperand(1);
4114 if (MatchEvenMask) {
4115 // Shift the second operand right to 32 bits.
4116 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4117 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4119 // Shift the first operand left to 32 bits.
4120 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4121 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4123 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4124 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4127 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4128 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4129 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4130 bool HasInt256, bool V2IsSplat = false) {
4132 assert(VT.getSizeInBits() >= 128 &&
4133 "Unsupported vector type for unpckl");
4135 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4137 unsigned NumOf256BitLanes;
4138 unsigned NumElts = VT.getVectorNumElements();
4139 if (VT.is256BitVector()) {
4140 if (NumElts != 4 && NumElts != 8 &&
4141 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4144 NumOf256BitLanes = 1;
4145 } else if (VT.is512BitVector()) {
4146 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4147 "Unsupported vector type for unpckh");
4149 NumOf256BitLanes = 2;
4152 NumOf256BitLanes = 1;
4155 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4156 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4158 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4159 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4160 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4161 int BitI = Mask[l256*NumEltsInStride+l+i];
4162 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4163 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4165 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4167 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4175 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4176 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4177 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4178 bool HasInt256, bool V2IsSplat = false) {
4179 assert(VT.getSizeInBits() >= 128 &&
4180 "Unsupported vector type for unpckh");
4182 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4184 unsigned NumOf256BitLanes;
4185 unsigned NumElts = VT.getVectorNumElements();
4186 if (VT.is256BitVector()) {
4187 if (NumElts != 4 && NumElts != 8 &&
4188 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4191 NumOf256BitLanes = 1;
4192 } else if (VT.is512BitVector()) {
4193 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4194 "Unsupported vector type for unpckh");
4196 NumOf256BitLanes = 2;
4199 NumOf256BitLanes = 1;
4202 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4203 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4205 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4206 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4207 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4208 int BitI = Mask[l256*NumEltsInStride+l+i];
4209 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4210 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4212 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4214 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4222 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4223 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4225 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4226 unsigned NumElts = VT.getVectorNumElements();
4227 bool Is256BitVec = VT.is256BitVector();
4229 if (VT.is512BitVector())
4231 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4232 "Unsupported vector type for unpckh");
4234 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4235 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4238 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4239 // FIXME: Need a better way to get rid of this, there's no latency difference
4240 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4241 // the former later. We should also remove the "_undef" special mask.
4242 if (NumElts == 4 && Is256BitVec)
4245 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4246 // independently on 128-bit lanes.
4247 unsigned NumLanes = VT.getSizeInBits()/128;
4248 unsigned NumLaneElts = NumElts/NumLanes;
4250 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4251 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4252 int BitI = Mask[l+i];
4253 int BitI1 = Mask[l+i+1];
4255 if (!isUndefOrEqual(BitI, j))
4257 if (!isUndefOrEqual(BitI1, j))
4265 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4266 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4268 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4269 unsigned NumElts = VT.getVectorNumElements();
4271 if (VT.is512BitVector())
4274 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4275 "Unsupported vector type for unpckh");
4277 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4278 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4281 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4282 // independently on 128-bit lanes.
4283 unsigned NumLanes = VT.getSizeInBits()/128;
4284 unsigned NumLaneElts = NumElts/NumLanes;
4286 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l+i];
4289 int BitI1 = Mask[l+i+1];
4290 if (!isUndefOrEqual(BitI, j))
4292 if (!isUndefOrEqual(BitI1, j))
4299 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4300 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4301 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4302 if (!VT.is512BitVector())
4305 unsigned NumElts = VT.getVectorNumElements();
4306 unsigned HalfSize = NumElts/2;
4307 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4308 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4313 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4314 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4322 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4323 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4324 /// MOVSD, and MOVD, i.e. setting the lowest element.
4325 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4326 if (VT.getVectorElementType().getSizeInBits() < 32)
4328 if (!VT.is128BitVector())
4331 unsigned NumElts = VT.getVectorNumElements();
4333 if (!isUndefOrEqual(Mask[0], NumElts))
4336 for (unsigned i = 1; i != NumElts; ++i)
4337 if (!isUndefOrEqual(Mask[i], i))
4343 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4344 /// as permutations between 128-bit chunks or halves. As an example: this
4346 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4347 /// The first half comes from the second half of V1 and the second half from the
4348 /// the second half of V2.
4349 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4350 if (!HasFp256 || !VT.is256BitVector())
4353 // The shuffle result is divided into half A and half B. In total the two
4354 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4355 // B must come from C, D, E or F.
4356 unsigned HalfSize = VT.getVectorNumElements()/2;
4357 bool MatchA = false, MatchB = false;
4359 // Check if A comes from one of C, D, E, F.
4360 for (unsigned Half = 0; Half != 4; ++Half) {
4361 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4367 // Check if B comes from one of C, D, E, F.
4368 for (unsigned Half = 0; Half != 4; ++Half) {
4369 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4375 return MatchA && MatchB;
4378 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4379 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4380 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4381 MVT VT = SVOp->getSimpleValueType(0);
4383 unsigned HalfSize = VT.getVectorNumElements()/2;
4385 unsigned FstHalf = 0, SndHalf = 0;
4386 for (unsigned i = 0; i < HalfSize; ++i) {
4387 if (SVOp->getMaskElt(i) > 0) {
4388 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4392 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4393 if (SVOp->getMaskElt(i) > 0) {
4394 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4399 return (FstHalf | (SndHalf << 4));
4402 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4403 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4404 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4408 unsigned NumElts = VT.getVectorNumElements();
4410 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4411 for (unsigned i = 0; i != NumElts; ++i) {
4414 Imm8 |= Mask[i] << (i*2);
4419 unsigned LaneSize = 4;
4420 SmallVector<int, 4> MaskVal(LaneSize, -1);
4422 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4423 for (unsigned i = 0; i != LaneSize; ++i) {
4424 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4428 if (MaskVal[i] < 0) {
4429 MaskVal[i] = Mask[i+l] - l;
4430 Imm8 |= MaskVal[i] << (i*2);
4433 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4440 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4441 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4442 /// Note that VPERMIL mask matching is different depending whether theunderlying
4443 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4444 /// to the same elements of the low, but to the higher half of the source.
4445 /// In VPERMILPD the two lanes could be shuffled independently of each other
4446 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4447 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4448 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4449 if (VT.getSizeInBits() < 256 || EltSize < 32)
4451 bool symetricMaskRequired = (EltSize == 32);
4452 unsigned NumElts = VT.getVectorNumElements();
4454 unsigned NumLanes = VT.getSizeInBits()/128;
4455 unsigned LaneSize = NumElts/NumLanes;
4456 // 2 or 4 elements in one lane
4458 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4459 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4460 for (unsigned i = 0; i != LaneSize; ++i) {
4461 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4463 if (symetricMaskRequired) {
4464 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4465 ExpectedMaskVal[i] = Mask[i+l] - l;
4468 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4476 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4477 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4478 /// element of vector 2 and the other elements to come from vector 1 in order.
4479 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4480 bool V2IsSplat = false, bool V2IsUndef = false) {
4481 if (!VT.is128BitVector())
4484 unsigned NumOps = VT.getVectorNumElements();
4485 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4488 if (!isUndefOrEqual(Mask[0], 0))
4491 for (unsigned i = 1; i != NumOps; ++i)
4492 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4493 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4494 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4500 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4501 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4502 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4503 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4504 const X86Subtarget *Subtarget) {
4505 if (!Subtarget->hasSSE3())
4508 unsigned NumElems = VT.getVectorNumElements();
4510 if ((VT.is128BitVector() && NumElems != 4) ||
4511 (VT.is256BitVector() && NumElems != 8) ||
4512 (VT.is512BitVector() && NumElems != 16))
4515 // "i+1" is the value the indexed mask element must have
4516 for (unsigned i = 0; i != NumElems; i += 2)
4517 if (!isUndefOrEqual(Mask[i], i+1) ||
4518 !isUndefOrEqual(Mask[i+1], i+1))
4524 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4525 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4526 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4527 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4528 const X86Subtarget *Subtarget) {
4529 if (!Subtarget->hasSSE3())
4532 unsigned NumElems = VT.getVectorNumElements();
4534 if ((VT.is128BitVector() && NumElems != 4) ||
4535 (VT.is256BitVector() && NumElems != 8) ||
4536 (VT.is512BitVector() && NumElems != 16))
4539 // "i" is the value the indexed mask element must have
4540 for (unsigned i = 0; i != NumElems; i += 2)
4541 if (!isUndefOrEqual(Mask[i], i) ||
4542 !isUndefOrEqual(Mask[i+1], i))
4548 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4549 /// specifies a shuffle of elements that is suitable for input to 256-bit
4550 /// version of MOVDDUP.
4551 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4552 if (!HasFp256 || !VT.is256BitVector())
4555 unsigned NumElts = VT.getVectorNumElements();
4559 for (unsigned i = 0; i != NumElts/2; ++i)
4560 if (!isUndefOrEqual(Mask[i], 0))
4562 for (unsigned i = NumElts/2; i != NumElts; ++i)
4563 if (!isUndefOrEqual(Mask[i], NumElts/2))
4568 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4569 /// specifies a shuffle of elements that is suitable for input to 128-bit
4570 /// version of MOVDDUP.
4571 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4572 if (!VT.is128BitVector())
4575 unsigned e = VT.getVectorNumElements() / 2;
4576 for (unsigned i = 0; i != e; ++i)
4577 if (!isUndefOrEqual(Mask[i], i))
4579 for (unsigned i = 0; i != e; ++i)
4580 if (!isUndefOrEqual(Mask[e+i], i))
4585 /// isVEXTRACTIndex - Return true if the specified
4586 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4587 /// suitable for instruction that extract 128 or 256 bit vectors
4588 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4589 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4590 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4593 // The index should be aligned on a vecWidth-bit boundary.
4595 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4597 MVT VT = N->getSimpleValueType(0);
4598 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4599 bool Result = (Index * ElSize) % vecWidth == 0;
4604 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4605 /// operand specifies a subvector insert that is suitable for input to
4606 /// insertion of 128 or 256-bit subvectors
4607 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4608 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4609 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4611 // The index should be aligned on a vecWidth-bit boundary.
4613 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4615 MVT VT = N->getSimpleValueType(0);
4616 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4617 bool Result = (Index * ElSize) % vecWidth == 0;
4622 bool X86::isVINSERT128Index(SDNode *N) {
4623 return isVINSERTIndex(N, 128);
4626 bool X86::isVINSERT256Index(SDNode *N) {
4627 return isVINSERTIndex(N, 256);
4630 bool X86::isVEXTRACT128Index(SDNode *N) {
4631 return isVEXTRACTIndex(N, 128);
4634 bool X86::isVEXTRACT256Index(SDNode *N) {
4635 return isVEXTRACTIndex(N, 256);
4638 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4639 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4640 /// Handles 128-bit and 256-bit.
4641 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4642 MVT VT = N->getSimpleValueType(0);
4644 assert((VT.getSizeInBits() >= 128) &&
4645 "Unsupported vector type for PSHUF/SHUFP");
4647 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4648 // independently on 128-bit lanes.
4649 unsigned NumElts = VT.getVectorNumElements();
4650 unsigned NumLanes = VT.getSizeInBits()/128;
4651 unsigned NumLaneElts = NumElts/NumLanes;
4653 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4654 "Only supports 2, 4 or 8 elements per lane");
4656 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4658 for (unsigned i = 0; i != NumElts; ++i) {
4659 int Elt = N->getMaskElt(i);
4660 if (Elt < 0) continue;
4661 Elt &= NumLaneElts - 1;
4662 unsigned ShAmt = (i << Shift) % 8;
4663 Mask |= Elt << ShAmt;
4669 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4670 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4671 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4672 MVT VT = N->getSimpleValueType(0);
4674 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4675 "Unsupported vector type for PSHUFHW");
4677 unsigned NumElts = VT.getVectorNumElements();
4680 for (unsigned l = 0; l != NumElts; l += 8) {
4681 // 8 nodes per lane, but we only care about the last 4.
4682 for (unsigned i = 0; i < 4; ++i) {
4683 int Elt = N->getMaskElt(l+i+4);
4684 if (Elt < 0) continue;
4685 Elt &= 0x3; // only 2-bits.
4686 Mask |= Elt << (i * 2);
4693 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4694 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4695 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4696 MVT VT = N->getSimpleValueType(0);
4698 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4699 "Unsupported vector type for PSHUFHW");
4701 unsigned NumElts = VT.getVectorNumElements();
4704 for (unsigned l = 0; l != NumElts; l += 8) {
4705 // 8 nodes per lane, but we only care about the first 4.
4706 for (unsigned i = 0; i < 4; ++i) {
4707 int Elt = N->getMaskElt(l+i);
4708 if (Elt < 0) continue;
4709 Elt &= 0x3; // only 2-bits
4710 Mask |= Elt << (i * 2);
4717 /// \brief Return the appropriate immediate to shuffle the specified
4718 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4719 /// VALIGN (if Interlane is true) instructions.
4720 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4722 MVT VT = SVOp->getSimpleValueType(0);
4723 unsigned EltSize = InterLane ? 1 :
4724 VT.getVectorElementType().getSizeInBits() >> 3;
4726 unsigned NumElts = VT.getVectorNumElements();
4727 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4728 unsigned NumLaneElts = NumElts/NumLanes;
4732 for (i = 0; i != NumElts; ++i) {
4733 Val = SVOp->getMaskElt(i);
4737 if (Val >= (int)NumElts)
4738 Val -= NumElts - NumLaneElts;
4740 assert(Val - i > 0 && "PALIGNR imm should be positive");
4741 return (Val - i) * EltSize;
4744 /// \brief Return the appropriate immediate to shuffle the specified
4745 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4746 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4747 return getShuffleAlignrImmediate(SVOp, false);
4750 /// \brief Return the appropriate immediate to shuffle the specified
4751 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4752 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4753 return getShuffleAlignrImmediate(SVOp, true);
4757 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4758 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4759 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4760 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4763 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4765 MVT VecVT = N->getOperand(0).getSimpleValueType();
4766 MVT ElVT = VecVT.getVectorElementType();
4768 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4769 return Index / NumElemsPerChunk;
4772 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4773 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4774 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4775 llvm_unreachable("Illegal insert subvector for VINSERT");
4778 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4780 MVT VecVT = N->getSimpleValueType(0);
4781 MVT ElVT = VecVT.getVectorElementType();
4783 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4784 return Index / NumElemsPerChunk;
4787 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4788 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4789 /// and VINSERTI128 instructions.
4790 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4791 return getExtractVEXTRACTImmediate(N, 128);
4794 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4795 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4796 /// and VINSERTI64x4 instructions.
4797 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4798 return getExtractVEXTRACTImmediate(N, 256);
4801 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4802 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4803 /// and VINSERTI128 instructions.
4804 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4805 return getInsertVINSERTImmediate(N, 128);
4808 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4809 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4810 /// and VINSERTI64x4 instructions.
4811 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4812 return getInsertVINSERTImmediate(N, 256);
4815 /// isZero - Returns true if Elt is a constant integer zero
4816 static bool isZero(SDValue V) {
4817 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4818 return C && C->isNullValue();
4821 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4823 bool X86::isZeroNode(SDValue Elt) {
4826 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4827 return CFP->getValueAPF().isPosZero();
4831 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4832 /// match movhlps. The lower half elements should come from upper half of
4833 /// V1 (and in order), and the upper half elements should come from the upper
4834 /// half of V2 (and in order).
4835 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4836 if (!VT.is128BitVector())
4838 if (VT.getVectorNumElements() != 4)
4840 for (unsigned i = 0, e = 2; i != e; ++i)
4841 if (!isUndefOrEqual(Mask[i], i+2))
4843 for (unsigned i = 2; i != 4; ++i)
4844 if (!isUndefOrEqual(Mask[i], i+4))
4849 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4850 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4852 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4853 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4855 N = N->getOperand(0).getNode();
4856 if (!ISD::isNON_EXTLoad(N))
4859 *LD = cast<LoadSDNode>(N);
4863 // Test whether the given value is a vector value which will be legalized
4865 static bool WillBeConstantPoolLoad(SDNode *N) {
4866 if (N->getOpcode() != ISD::BUILD_VECTOR)
4869 // Check for any non-constant elements.
4870 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4871 switch (N->getOperand(i).getNode()->getOpcode()) {
4873 case ISD::ConstantFP:
4880 // Vectors of all-zeros and all-ones are materialized with special
4881 // instructions rather than being loaded.
4882 return !ISD::isBuildVectorAllZeros(N) &&
4883 !ISD::isBuildVectorAllOnes(N);
4886 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4887 /// match movlp{s|d}. The lower half elements should come from lower half of
4888 /// V1 (and in order), and the upper half elements should come from the upper
4889 /// half of V2 (and in order). And since V1 will become the source of the
4890 /// MOVLP, it must be either a vector load or a scalar load to vector.
4891 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4892 ArrayRef<int> Mask, MVT VT) {
4893 if (!VT.is128BitVector())
4896 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4898 // Is V2 is a vector load, don't do this transformation. We will try to use
4899 // load folding shufps op.
4900 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4903 unsigned NumElems = VT.getVectorNumElements();
4905 if (NumElems != 2 && NumElems != 4)
4907 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4908 if (!isUndefOrEqual(Mask[i], i))
4910 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4911 if (!isUndefOrEqual(Mask[i], i+NumElems))
4916 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4917 /// to an zero vector.
4918 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4919 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4920 SDValue V1 = N->getOperand(0);
4921 SDValue V2 = N->getOperand(1);
4922 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4923 for (unsigned i = 0; i != NumElems; ++i) {
4924 int Idx = N->getMaskElt(i);
4925 if (Idx >= (int)NumElems) {
4926 unsigned Opc = V2.getOpcode();
4927 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4929 if (Opc != ISD::BUILD_VECTOR ||
4930 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4932 } else if (Idx >= 0) {
4933 unsigned Opc = V1.getOpcode();
4934 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4936 if (Opc != ISD::BUILD_VECTOR ||
4937 !X86::isZeroNode(V1.getOperand(Idx)))
4944 /// getZeroVector - Returns a vector of specified type with all zero elements.
4946 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4947 SelectionDAG &DAG, SDLoc dl) {
4948 assert(VT.isVector() && "Expected a vector type");
4950 // Always build SSE zero vectors as <4 x i32> bitcasted
4951 // to their dest type. This ensures they get CSE'd.
4953 if (VT.is128BitVector()) { // SSE
4954 if (Subtarget->hasSSE2()) { // SSE2
4955 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4956 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4958 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4959 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4961 } else if (VT.is256BitVector()) { // AVX
4962 if (Subtarget->hasInt256()) { // AVX2
4963 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4964 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4965 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4967 // 256-bit logic and arithmetic instructions in AVX are all
4968 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4969 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4970 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4971 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4973 } else if (VT.is512BitVector()) { // AVX-512
4974 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4975 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4976 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4977 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4978 } else if (VT.getScalarType() == MVT::i1) {
4979 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4980 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4981 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4982 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4984 llvm_unreachable("Unexpected vector type");
4986 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4989 /// getOnesVector - Returns a vector of specified type with all bits set.
4990 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4991 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4992 /// Then bitcast to their original type, ensuring they get CSE'd.
4993 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4995 assert(VT.isVector() && "Expected a vector type");
4997 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4999 if (VT.is256BitVector()) {
5000 if (HasInt256) { // AVX2
5001 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5002 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5004 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5005 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5007 } else if (VT.is128BitVector()) {
5008 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5010 llvm_unreachable("Unexpected vector type");
5012 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5015 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5016 /// that point to V2 points to its first element.
5017 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5018 for (unsigned i = 0; i != NumElems; ++i) {
5019 if (Mask[i] > (int)NumElems) {
5025 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5026 /// operation of specified width.
5027 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5029 unsigned NumElems = VT.getVectorNumElements();
5030 SmallVector<int, 8> Mask;
5031 Mask.push_back(NumElems);
5032 for (unsigned i = 1; i != NumElems; ++i)
5034 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5037 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5038 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5040 unsigned NumElems = VT.getVectorNumElements();
5041 SmallVector<int, 8> Mask;
5042 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5044 Mask.push_back(i + NumElems);
5046 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5049 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5050 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5052 unsigned NumElems = VT.getVectorNumElements();
5053 SmallVector<int, 8> Mask;
5054 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5055 Mask.push_back(i + Half);
5056 Mask.push_back(i + NumElems + Half);
5058 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5061 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5062 // a generic shuffle instruction because the target has no such instructions.
5063 // Generate shuffles which repeat i16 and i8 several times until they can be
5064 // represented by v4f32 and then be manipulated by target suported shuffles.
5065 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5066 MVT VT = V.getSimpleValueType();
5067 int NumElems = VT.getVectorNumElements();
5070 while (NumElems > 4) {
5071 if (EltNo < NumElems/2) {
5072 V = getUnpackl(DAG, dl, VT, V, V);
5074 V = getUnpackh(DAG, dl, VT, V, V);
5075 EltNo -= NumElems/2;
5082 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5083 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5084 MVT VT = V.getSimpleValueType();
5087 if (VT.is128BitVector()) {
5088 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5089 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5090 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5092 } else if (VT.is256BitVector()) {
5093 // To use VPERMILPS to splat scalars, the second half of indicies must
5094 // refer to the higher part, which is a duplication of the lower one,
5095 // because VPERMILPS can only handle in-lane permutations.
5096 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5097 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5099 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5100 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5103 llvm_unreachable("Vector size not supported");
5105 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5108 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5109 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5110 MVT SrcVT = SV->getSimpleValueType(0);
5111 SDValue V1 = SV->getOperand(0);
5114 int EltNo = SV->getSplatIndex();
5115 int NumElems = SrcVT.getVectorNumElements();
5116 bool Is256BitVec = SrcVT.is256BitVector();
5118 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5119 "Unknown how to promote splat for type");
5121 // Extract the 128-bit part containing the splat element and update
5122 // the splat element index when it refers to the higher register.
5124 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5125 if (EltNo >= NumElems/2)
5126 EltNo -= NumElems/2;
5129 // All i16 and i8 vector types can't be used directly by a generic shuffle
5130 // instruction because the target has no such instruction. Generate shuffles
5131 // which repeat i16 and i8 several times until they fit in i32, and then can
5132 // be manipulated by target suported shuffles.
5133 MVT EltVT = SrcVT.getVectorElementType();
5134 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5135 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5137 // Recreate the 256-bit vector and place the same 128-bit vector
5138 // into the low and high part. This is necessary because we want
5139 // to use VPERM* to shuffle the vectors
5141 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5144 return getLegalSplat(DAG, V1, EltNo);
5147 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5148 /// vector of zero or undef vector. This produces a shuffle where the low
5149 /// element of V2 is swizzled into the zero/undef vector, landing at element
5150 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5151 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5153 const X86Subtarget *Subtarget,
5154 SelectionDAG &DAG) {
5155 MVT VT = V2.getSimpleValueType();
5157 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5158 unsigned NumElems = VT.getVectorNumElements();
5159 SmallVector<int, 16> MaskVec;
5160 for (unsigned i = 0; i != NumElems; ++i)
5161 // If this is the insertion idx, put the low elt of V2 here.
5162 MaskVec.push_back(i == Idx ? NumElems : i);
5163 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5166 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5167 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5168 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5169 /// shuffles which use a single input multiple times, and in those cases it will
5170 /// adjust the mask to only have indices within that single input.
5171 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5172 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5173 unsigned NumElems = VT.getVectorNumElements();
5177 bool IsFakeUnary = false;
5178 switch(N->getOpcode()) {
5180 ImmN = N->getOperand(N->getNumOperands()-1);
5181 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5182 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5184 case X86ISD::UNPCKH:
5185 DecodeUNPCKHMask(VT, Mask);
5186 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5188 case X86ISD::UNPCKL:
5189 DecodeUNPCKLMask(VT, Mask);
5190 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5192 case X86ISD::MOVHLPS:
5193 DecodeMOVHLPSMask(NumElems, Mask);
5194 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5196 case X86ISD::MOVLHPS:
5197 DecodeMOVLHPSMask(NumElems, Mask);
5198 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5200 case X86ISD::PALIGNR:
5201 ImmN = N->getOperand(N->getNumOperands()-1);
5202 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5204 case X86ISD::PSHUFD:
5205 case X86ISD::VPERMILP:
5206 ImmN = N->getOperand(N->getNumOperands()-1);
5207 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5210 case X86ISD::PSHUFHW:
5211 ImmN = N->getOperand(N->getNumOperands()-1);
5212 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5215 case X86ISD::PSHUFLW:
5216 ImmN = N->getOperand(N->getNumOperands()-1);
5217 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5220 case X86ISD::PSHUFB: {
5222 SDValue MaskNode = N->getOperand(1);
5223 while (MaskNode->getOpcode() == ISD::BITCAST)
5224 MaskNode = MaskNode->getOperand(0);
5226 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5227 // If we have a build-vector, then things are easy.
5228 EVT VT = MaskNode.getValueType();
5229 assert(VT.isVector() &&
5230 "Can't produce a non-vector with a build_vector!");
5231 if (!VT.isInteger())
5234 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5236 SmallVector<uint64_t, 32> RawMask;
5237 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5238 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5241 APInt MaskElement = CN->getAPIntValue();
5243 // We now have to decode the element which could be any integer size and
5244 // extract each byte of it.
5245 for (int j = 0; j < NumBytesPerElement; ++j) {
5246 // Note that this is x86 and so always little endian: the low byte is
5247 // the first byte of the mask.
5248 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5249 MaskElement = MaskElement.lshr(8);
5252 DecodePSHUFBMask(RawMask, Mask);
5256 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5260 SDValue Ptr = MaskLoad->getBasePtr();
5261 if (Ptr->getOpcode() == X86ISD::Wrapper)
5262 Ptr = Ptr->getOperand(0);
5264 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5265 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5268 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5269 // FIXME: Support AVX-512 here.
5270 if (!C->getType()->isVectorTy() ||
5271 (C->getNumElements() != 16 && C->getNumElements() != 32))
5274 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5275 DecodePSHUFBMask(C, Mask);
5281 case X86ISD::VPERMI:
5282 ImmN = N->getOperand(N->getNumOperands()-1);
5283 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5287 case X86ISD::MOVSD: {
5288 // The index 0 always comes from the first element of the second source,
5289 // this is why MOVSS and MOVSD are used in the first place. The other
5290 // elements come from the other positions of the first source vector
5291 Mask.push_back(NumElems);
5292 for (unsigned i = 1; i != NumElems; ++i) {
5297 case X86ISD::VPERM2X128:
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 if (Mask.empty()) return false;
5302 case X86ISD::MOVDDUP:
5303 case X86ISD::MOVLHPD:
5304 case X86ISD::MOVLPD:
5305 case X86ISD::MOVLPS:
5306 case X86ISD::MOVSHDUP:
5307 case X86ISD::MOVSLDUP:
5308 // Not yet implemented
5310 default: llvm_unreachable("unknown target shuffle node");
5313 // If we have a fake unary shuffle, the shuffle mask is spread across two
5314 // inputs that are actually the same node. Re-map the mask to always point
5315 // into the first input.
5318 if (M >= (int)Mask.size())
5324 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5325 /// element of the result of the vector shuffle.
5326 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5329 return SDValue(); // Limit search depth.
5331 SDValue V = SDValue(N, 0);
5332 EVT VT = V.getValueType();
5333 unsigned Opcode = V.getOpcode();
5335 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5336 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5337 int Elt = SV->getMaskElt(Index);
5340 return DAG.getUNDEF(VT.getVectorElementType());
5342 unsigned NumElems = VT.getVectorNumElements();
5343 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5344 : SV->getOperand(1);
5345 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5348 // Recurse into target specific vector shuffles to find scalars.
5349 if (isTargetShuffle(Opcode)) {
5350 MVT ShufVT = V.getSimpleValueType();
5351 unsigned NumElems = ShufVT.getVectorNumElements();
5352 SmallVector<int, 16> ShuffleMask;
5355 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5358 int Elt = ShuffleMask[Index];
5360 return DAG.getUNDEF(ShufVT.getVectorElementType());
5362 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5364 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5368 // Actual nodes that may contain scalar elements
5369 if (Opcode == ISD::BITCAST) {
5370 V = V.getOperand(0);
5371 EVT SrcVT = V.getValueType();
5372 unsigned NumElems = VT.getVectorNumElements();
5374 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5378 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5379 return (Index == 0) ? V.getOperand(0)
5380 : DAG.getUNDEF(VT.getVectorElementType());
5382 if (V.getOpcode() == ISD::BUILD_VECTOR)
5383 return V.getOperand(Index);
5388 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5389 /// shuffle operation which come from a consecutively from a zero. The
5390 /// search can start in two different directions, from left or right.
5391 /// We count undefs as zeros until PreferredNum is reached.
5392 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5393 unsigned NumElems, bool ZerosFromLeft,
5395 unsigned PreferredNum = -1U) {
5396 unsigned NumZeros = 0;
5397 for (unsigned i = 0; i != NumElems; ++i) {
5398 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5399 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5403 if (X86::isZeroNode(Elt))
5405 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5406 NumZeros = std::min(NumZeros + 1, PreferredNum);
5414 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5415 /// correspond consecutively to elements from one of the vector operands,
5416 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5418 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5419 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5420 unsigned NumElems, unsigned &OpNum) {
5421 bool SeenV1 = false;
5422 bool SeenV2 = false;
5424 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5425 int Idx = SVOp->getMaskElt(i);
5426 // Ignore undef indicies
5430 if (Idx < (int)NumElems)
5435 // Only accept consecutive elements from the same vector
5436 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5440 OpNum = SeenV1 ? 0 : 1;
5444 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5445 /// logical left shift of a vector.
5446 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5447 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5449 SVOp->getSimpleValueType(0).getVectorNumElements();
5450 unsigned NumZeros = getNumOfConsecutiveZeros(
5451 SVOp, NumElems, false /* check zeros from right */, DAG,
5452 SVOp->getMaskElt(0));
5458 // Considering the elements in the mask that are not consecutive zeros,
5459 // check if they consecutively come from only one of the source vectors.
5461 // V1 = {X, A, B, C} 0
5463 // vector_shuffle V1, V2 <1, 2, 3, X>
5465 if (!isShuffleMaskConsecutive(SVOp,
5466 0, // Mask Start Index
5467 NumElems-NumZeros, // Mask End Index(exclusive)
5468 NumZeros, // Where to start looking in the src vector
5469 NumElems, // Number of elements in vector
5470 OpSrc)) // Which source operand ?
5475 ShVal = SVOp->getOperand(OpSrc);
5479 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5480 /// logical left shift of a vector.
5481 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5482 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5484 SVOp->getSimpleValueType(0).getVectorNumElements();
5485 unsigned NumZeros = getNumOfConsecutiveZeros(
5486 SVOp, NumElems, true /* check zeros from left */, DAG,
5487 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5493 // Considering the elements in the mask that are not consecutive zeros,
5494 // check if they consecutively come from only one of the source vectors.
5496 // 0 { A, B, X, X } = V2
5498 // vector_shuffle V1, V2 <X, X, 4, 5>
5500 if (!isShuffleMaskConsecutive(SVOp,
5501 NumZeros, // Mask Start Index
5502 NumElems, // Mask End Index(exclusive)
5503 0, // Where to start looking in the src vector
5504 NumElems, // Number of elements in vector
5505 OpSrc)) // Which source operand ?
5510 ShVal = SVOp->getOperand(OpSrc);
5514 /// isVectorShift - Returns true if the shuffle can be implemented as a
5515 /// logical left or right shift of a vector.
5516 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5517 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5518 // Although the logic below support any bitwidth size, there are no
5519 // shift instructions which handle more than 128-bit vectors.
5520 if (!SVOp->getSimpleValueType(0).is128BitVector())
5523 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5524 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5530 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5532 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5533 unsigned NumNonZero, unsigned NumZero,
5535 const X86Subtarget* Subtarget,
5536 const TargetLowering &TLI) {
5543 for (unsigned i = 0; i < 16; ++i) {
5544 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5545 if (ThisIsNonZero && First) {
5547 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5549 V = DAG.getUNDEF(MVT::v8i16);
5554 SDValue ThisElt, LastElt;
5555 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5556 if (LastIsNonZero) {
5557 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5558 MVT::i16, Op.getOperand(i-1));
5560 if (ThisIsNonZero) {
5561 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5562 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5563 ThisElt, DAG.getConstant(8, MVT::i8));
5565 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5569 if (ThisElt.getNode())
5570 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5571 DAG.getIntPtrConstant(i/2));
5575 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5578 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5580 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5581 unsigned NumNonZero, unsigned NumZero,
5583 const X86Subtarget* Subtarget,
5584 const TargetLowering &TLI) {
5591 for (unsigned i = 0; i < 8; ++i) {
5592 bool isNonZero = (NonZeros & (1 << i)) != 0;
5596 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5598 V = DAG.getUNDEF(MVT::v8i16);
5601 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5602 MVT::v8i16, V, Op.getOperand(i),
5603 DAG.getIntPtrConstant(i));
5610 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5611 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5612 unsigned NonZeros, unsigned NumNonZero,
5613 unsigned NumZero, SelectionDAG &DAG,
5614 const X86Subtarget *Subtarget,
5615 const TargetLowering &TLI) {
5616 // We know there's at least one non-zero element
5617 unsigned FirstNonZeroIdx = 0;
5618 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5619 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5620 X86::isZeroNode(FirstNonZero)) {
5622 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5625 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5626 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5629 SDValue V = FirstNonZero.getOperand(0);
5630 MVT VVT = V.getSimpleValueType();
5631 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5634 unsigned FirstNonZeroDst =
5635 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5636 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5637 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5638 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5640 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5641 SDValue Elem = Op.getOperand(Idx);
5642 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5645 // TODO: What else can be here? Deal with it.
5646 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5649 // TODO: Some optimizations are still possible here
5650 // ex: Getting one element from a vector, and the rest from another.
5651 if (Elem.getOperand(0) != V)
5654 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5657 else if (IncorrectIdx == -1U) {
5661 // There was already one element with an incorrect index.
5662 // We can't optimize this case to an insertps.
5666 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5668 EVT VT = Op.getSimpleValueType();
5669 unsigned ElementMoveMask = 0;
5670 if (IncorrectIdx == -1U)
5671 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5673 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5675 SDValue InsertpsMask =
5676 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5677 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5683 /// getVShift - Return a vector logical shift node.
5685 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5686 unsigned NumBits, SelectionDAG &DAG,
5687 const TargetLowering &TLI, SDLoc dl) {
5688 assert(VT.is128BitVector() && "Unknown type for VShift");
5689 EVT ShVT = MVT::v2i64;
5690 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5691 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5692 return DAG.getNode(ISD::BITCAST, dl, VT,
5693 DAG.getNode(Opc, dl, ShVT, SrcOp,
5694 DAG.getConstant(NumBits,
5695 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5699 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5701 // Check if the scalar load can be widened into a vector load. And if
5702 // the address is "base + cst" see if the cst can be "absorbed" into
5703 // the shuffle mask.
5704 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5705 SDValue Ptr = LD->getBasePtr();
5706 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5708 EVT PVT = LD->getValueType(0);
5709 if (PVT != MVT::i32 && PVT != MVT::f32)
5714 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5715 FI = FINode->getIndex();
5717 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5718 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5719 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5720 Offset = Ptr.getConstantOperandVal(1);
5721 Ptr = Ptr.getOperand(0);
5726 // FIXME: 256-bit vector instructions don't require a strict alignment,
5727 // improve this code to support it better.
5728 unsigned RequiredAlign = VT.getSizeInBits()/8;
5729 SDValue Chain = LD->getChain();
5730 // Make sure the stack object alignment is at least 16 or 32.
5731 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5732 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5733 if (MFI->isFixedObjectIndex(FI)) {
5734 // Can't change the alignment. FIXME: It's possible to compute
5735 // the exact stack offset and reference FI + adjust offset instead.
5736 // If someone *really* cares about this. That's the way to implement it.
5739 MFI->setObjectAlignment(FI, RequiredAlign);
5743 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5744 // Ptr + (Offset & ~15).
5747 if ((Offset % RequiredAlign) & 3)
5749 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5751 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5752 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5754 int EltNo = (Offset - StartOffset) >> 2;
5755 unsigned NumElems = VT.getVectorNumElements();
5757 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5758 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5759 LD->getPointerInfo().getWithOffset(StartOffset),
5760 false, false, false, 0);
5762 SmallVector<int, 8> Mask;
5763 for (unsigned i = 0; i != NumElems; ++i)
5764 Mask.push_back(EltNo);
5766 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5772 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5773 /// vector of type 'VT', see if the elements can be replaced by a single large
5774 /// load which has the same value as a build_vector whose operands are 'elts'.
5776 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5778 /// FIXME: we'd also like to handle the case where the last elements are zero
5779 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5780 /// There's even a handy isZeroNode for that purpose.
5781 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5782 SDLoc &DL, SelectionDAG &DAG,
5783 bool isAfterLegalize) {
5784 EVT EltVT = VT.getVectorElementType();
5785 unsigned NumElems = Elts.size();
5787 LoadSDNode *LDBase = nullptr;
5788 unsigned LastLoadedElt = -1U;
5790 // For each element in the initializer, see if we've found a load or an undef.
5791 // If we don't find an initial load element, or later load elements are
5792 // non-consecutive, bail out.
5793 for (unsigned i = 0; i < NumElems; ++i) {
5794 SDValue Elt = Elts[i];
5796 if (!Elt.getNode() ||
5797 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5800 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5802 LDBase = cast<LoadSDNode>(Elt.getNode());
5806 if (Elt.getOpcode() == ISD::UNDEF)
5809 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5810 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5815 // If we have found an entire vector of loads and undefs, then return a large
5816 // load of the entire vector width starting at the base pointer. If we found
5817 // consecutive loads for the low half, generate a vzext_load node.
5818 if (LastLoadedElt == NumElems - 1) {
5820 if (isAfterLegalize &&
5821 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5824 SDValue NewLd = SDValue();
5826 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5827 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5828 LDBase->getPointerInfo(),
5829 LDBase->isVolatile(), LDBase->isNonTemporal(),
5830 LDBase->isInvariant(), 0);
5831 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5832 LDBase->getPointerInfo(),
5833 LDBase->isVolatile(), LDBase->isNonTemporal(),
5834 LDBase->isInvariant(), LDBase->getAlignment());
5836 if (LDBase->hasAnyUseOfValue(1)) {
5837 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5839 SDValue(NewLd.getNode(), 1));
5840 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5841 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5842 SDValue(NewLd.getNode(), 1));
5847 if (NumElems == 4 && LastLoadedElt == 1 &&
5848 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5849 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5850 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5852 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5853 LDBase->getPointerInfo(),
5854 LDBase->getAlignment(),
5855 false/*isVolatile*/, true/*ReadMem*/,
5858 // Make sure the newly-created LOAD is in the same position as LDBase in
5859 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5860 // update uses of LDBase's output chain to use the TokenFactor.
5861 if (LDBase->hasAnyUseOfValue(1)) {
5862 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5863 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5864 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5865 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5866 SDValue(ResNode.getNode(), 1));
5869 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5874 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5875 /// to generate a splat value for the following cases:
5876 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5877 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5878 /// a scalar load, or a constant.
5879 /// The VBROADCAST node is returned when a pattern is found,
5880 /// or SDValue() otherwise.
5881 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5882 SelectionDAG &DAG) {
5883 if (!Subtarget->hasFp256())
5886 MVT VT = Op.getSimpleValueType();
5889 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5890 "Unsupported vector type for broadcast.");
5895 switch (Op.getOpcode()) {
5897 // Unknown pattern found.
5900 case ISD::BUILD_VECTOR: {
5901 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5902 BitVector UndefElements;
5903 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5905 // We need a splat of a single value to use broadcast, and it doesn't
5906 // make any sense if the value is only in one element of the vector.
5907 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5911 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5912 Ld.getOpcode() == ISD::ConstantFP);
5914 // Make sure that all of the users of a non-constant load are from the
5915 // BUILD_VECTOR node.
5916 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5921 case ISD::VECTOR_SHUFFLE: {
5922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5924 // Shuffles must have a splat mask where the first element is
5926 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5929 SDValue Sc = Op.getOperand(0);
5930 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5931 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5933 if (!Subtarget->hasInt256())
5936 // Use the register form of the broadcast instruction available on AVX2.
5937 if (VT.getSizeInBits() >= 256)
5938 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5939 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5942 Ld = Sc.getOperand(0);
5943 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5944 Ld.getOpcode() == ISD::ConstantFP);
5946 // The scalar_to_vector node and the suspected
5947 // load node must have exactly one user.
5948 // Constants may have multiple users.
5950 // AVX-512 has register version of the broadcast
5951 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5952 Ld.getValueType().getSizeInBits() >= 32;
5953 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5960 bool IsGE256 = (VT.getSizeInBits() >= 256);
5962 // Handle the broadcasting a single constant scalar from the constant pool
5963 // into a vector. On Sandybridge it is still better to load a constant vector
5964 // from the constant pool and not to broadcast it from a scalar.
5965 if (ConstSplatVal && Subtarget->hasInt256()) {
5966 EVT CVT = Ld.getValueType();
5967 assert(!CVT.isVector() && "Must not broadcast a vector type");
5968 unsigned ScalarSize = CVT.getSizeInBits();
5970 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5971 const Constant *C = nullptr;
5972 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5973 C = CI->getConstantIntValue();
5974 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5975 C = CF->getConstantFPValue();
5977 assert(C && "Invalid constant type");
5979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5980 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5981 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5982 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5983 MachinePointerInfo::getConstantPool(),
5984 false, false, false, Alignment);
5986 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5990 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5991 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5993 // Handle AVX2 in-register broadcasts.
5994 if (!IsLoad && Subtarget->hasInt256() &&
5995 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5996 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5998 // The scalar source must be a normal load.
6002 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6003 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6005 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6006 // double since there is no vbroadcastsd xmm
6007 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6008 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6009 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6012 // Unsupported broadcast.
6016 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6017 /// underlying vector and index.
6019 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6021 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6023 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6024 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6027 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6029 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6031 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6032 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6035 // In this case the vector is the extract_subvector expression and the index
6036 // is 2, as specified by the shuffle.
6037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6038 SDValue ShuffleVec = SVOp->getOperand(0);
6039 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6040 assert(ShuffleVecVT.getVectorElementType() ==
6041 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6043 int ShuffleIdx = SVOp->getMaskElt(Idx);
6044 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6045 ExtractedFromVec = ShuffleVec;
6051 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6052 MVT VT = Op.getSimpleValueType();
6054 // Skip if insert_vec_elt is not supported.
6055 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6056 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6060 unsigned NumElems = Op.getNumOperands();
6064 SmallVector<unsigned, 4> InsertIndices;
6065 SmallVector<int, 8> Mask(NumElems, -1);
6067 for (unsigned i = 0; i != NumElems; ++i) {
6068 unsigned Opc = Op.getOperand(i).getOpcode();
6070 if (Opc == ISD::UNDEF)
6073 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6074 // Quit if more than 1 elements need inserting.
6075 if (InsertIndices.size() > 1)
6078 InsertIndices.push_back(i);
6082 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6083 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6084 // Quit if non-constant index.
6085 if (!isa<ConstantSDNode>(ExtIdx))
6087 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6089 // Quit if extracted from vector of different type.
6090 if (ExtractedFromVec.getValueType() != VT)
6093 if (!VecIn1.getNode())
6094 VecIn1 = ExtractedFromVec;
6095 else if (VecIn1 != ExtractedFromVec) {
6096 if (!VecIn2.getNode())
6097 VecIn2 = ExtractedFromVec;
6098 else if (VecIn2 != ExtractedFromVec)
6099 // Quit if more than 2 vectors to shuffle
6103 if (ExtractedFromVec == VecIn1)
6105 else if (ExtractedFromVec == VecIn2)
6106 Mask[i] = Idx + NumElems;
6109 if (!VecIn1.getNode())
6112 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6113 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6114 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6115 unsigned Idx = InsertIndices[i];
6116 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6117 DAG.getIntPtrConstant(Idx));
6123 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6125 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6127 MVT VT = Op.getSimpleValueType();
6128 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6129 "Unexpected type in LowerBUILD_VECTORvXi1!");
6132 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6133 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6134 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6135 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6138 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6139 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6140 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6141 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6144 bool AllContants = true;
6145 uint64_t Immediate = 0;
6146 int NonConstIdx = -1;
6147 bool IsSplat = true;
6148 unsigned NumNonConsts = 0;
6149 unsigned NumConsts = 0;
6150 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6151 SDValue In = Op.getOperand(idx);
6152 if (In.getOpcode() == ISD::UNDEF)
6154 if (!isa<ConstantSDNode>(In)) {
6155 AllContants = false;
6161 if (cast<ConstantSDNode>(In)->getZExtValue())
6162 Immediate |= (1ULL << idx);
6164 if (In != Op.getOperand(0))
6169 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6170 DAG.getConstant(Immediate, MVT::i16));
6171 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6172 DAG.getIntPtrConstant(0));
6175 if (NumNonConsts == 1 && NonConstIdx != 0) {
6178 SDValue VecAsImm = DAG.getConstant(Immediate,
6179 MVT::getIntegerVT(VT.getSizeInBits()));
6180 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6183 DstVec = DAG.getUNDEF(VT);
6184 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6185 Op.getOperand(NonConstIdx),
6186 DAG.getIntPtrConstant(NonConstIdx));
6188 if (!IsSplat && (NonConstIdx != 0))
6189 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6190 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6193 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6194 DAG.getConstant(-1, SelectVT),
6195 DAG.getConstant(0, SelectVT));
6197 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6198 DAG.getConstant((Immediate | 1), SelectVT),
6199 DAG.getConstant(Immediate, SelectVT));
6200 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6203 /// \brief Return true if \p N implements a horizontal binop and return the
6204 /// operands for the horizontal binop into V0 and V1.
6206 /// This is a helper function of PerformBUILD_VECTORCombine.
6207 /// This function checks that the build_vector \p N in input implements a
6208 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6209 /// operation to match.
6210 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6211 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6212 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6215 /// This function only analyzes elements of \p N whose indices are
6216 /// in range [BaseIdx, LastIdx).
6217 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6219 unsigned BaseIdx, unsigned LastIdx,
6220 SDValue &V0, SDValue &V1) {
6221 EVT VT = N->getValueType(0);
6223 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6224 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6225 "Invalid Vector in input!");
6227 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6228 bool CanFold = true;
6229 unsigned ExpectedVExtractIdx = BaseIdx;
6230 unsigned NumElts = LastIdx - BaseIdx;
6231 V0 = DAG.getUNDEF(VT);
6232 V1 = DAG.getUNDEF(VT);
6234 // Check if N implements a horizontal binop.
6235 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6236 SDValue Op = N->getOperand(i + BaseIdx);
6239 if (Op->getOpcode() == ISD::UNDEF) {
6240 // Update the expected vector extract index.
6241 if (i * 2 == NumElts)
6242 ExpectedVExtractIdx = BaseIdx;
6243 ExpectedVExtractIdx += 2;
6247 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6252 SDValue Op0 = Op.getOperand(0);
6253 SDValue Op1 = Op.getOperand(1);
6255 // Try to match the following pattern:
6256 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6257 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6258 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6259 Op0.getOperand(0) == Op1.getOperand(0) &&
6260 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6261 isa<ConstantSDNode>(Op1.getOperand(1)));
6265 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6266 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6268 if (i * 2 < NumElts) {
6269 if (V0.getOpcode() == ISD::UNDEF)
6270 V0 = Op0.getOperand(0);
6272 if (V1.getOpcode() == ISD::UNDEF)
6273 V1 = Op0.getOperand(0);
6274 if (i * 2 == NumElts)
6275 ExpectedVExtractIdx = BaseIdx;
6278 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6279 if (I0 == ExpectedVExtractIdx)
6280 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6281 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6282 // Try to match the following dag sequence:
6283 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6284 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6288 ExpectedVExtractIdx += 2;
6294 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6295 /// a concat_vector.
6297 /// This is a helper function of PerformBUILD_VECTORCombine.
6298 /// This function expects two 256-bit vectors called V0 and V1.
6299 /// At first, each vector is split into two separate 128-bit vectors.
6300 /// Then, the resulting 128-bit vectors are used to implement two
6301 /// horizontal binary operations.
6303 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6305 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6306 /// the two new horizontal binop.
6307 /// When Mode is set, the first horizontal binop dag node would take as input
6308 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6309 /// horizontal binop dag node would take as input the lower 128-bit of V1
6310 /// and the upper 128-bit of V1.
6312 /// HADD V0_LO, V0_HI
6313 /// HADD V1_LO, V1_HI
6315 /// Otherwise, the first horizontal binop dag node takes as input the lower
6316 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6317 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6319 /// HADD V0_LO, V1_LO
6320 /// HADD V0_HI, V1_HI
6322 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6323 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6324 /// the upper 128-bits of the result.
6325 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6326 SDLoc DL, SelectionDAG &DAG,
6327 unsigned X86Opcode, bool Mode,
6328 bool isUndefLO, bool isUndefHI) {
6329 EVT VT = V0.getValueType();
6330 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6331 "Invalid nodes in input!");
6333 unsigned NumElts = VT.getVectorNumElements();
6334 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6335 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6336 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6337 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6338 EVT NewVT = V0_LO.getValueType();
6340 SDValue LO = DAG.getUNDEF(NewVT);
6341 SDValue HI = DAG.getUNDEF(NewVT);
6344 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6345 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6346 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6347 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6348 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6350 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6351 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6352 V1_LO->getOpcode() != ISD::UNDEF))
6353 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6355 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6356 V1_HI->getOpcode() != ISD::UNDEF))
6357 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6360 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6363 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6364 /// sequence of 'vadd + vsub + blendi'.
6365 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6366 const X86Subtarget *Subtarget) {
6368 EVT VT = BV->getValueType(0);
6369 unsigned NumElts = VT.getVectorNumElements();
6370 SDValue InVec0 = DAG.getUNDEF(VT);
6371 SDValue InVec1 = DAG.getUNDEF(VT);
6373 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6374 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6376 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6378 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6381 // Odd-numbered elements in the input build vector are obtained from
6382 // adding two integer/float elements.
6383 // Even-numbered elements in the input build vector are obtained from
6384 // subtracting two integer/float elements.
6385 unsigned ExpectedOpcode = ISD::FSUB;
6386 unsigned NextExpectedOpcode = ISD::FADD;
6387 bool AddFound = false;
6388 bool SubFound = false;
6390 for (unsigned i = 0, e = NumElts; i != e; i++) {
6391 SDValue Op = BV->getOperand(i);
6393 // Skip 'undef' values.
6394 unsigned Opcode = Op.getOpcode();
6395 if (Opcode == ISD::UNDEF) {
6396 std::swap(ExpectedOpcode, NextExpectedOpcode);
6400 // Early exit if we found an unexpected opcode.
6401 if (Opcode != ExpectedOpcode)
6404 SDValue Op0 = Op.getOperand(0);
6405 SDValue Op1 = Op.getOperand(1);
6407 // Try to match the following pattern:
6408 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6409 // Early exit if we cannot match that sequence.
6410 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6411 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6412 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6413 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6414 Op0.getOperand(1) != Op1.getOperand(1))
6417 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6421 // We found a valid add/sub node. Update the information accordingly.
6427 // Update InVec0 and InVec1.
6428 if (InVec0.getOpcode() == ISD::UNDEF)
6429 InVec0 = Op0.getOperand(0);
6430 if (InVec1.getOpcode() == ISD::UNDEF)
6431 InVec1 = Op1.getOperand(0);
6433 // Make sure that operands in input to each add/sub node always
6434 // come from a same pair of vectors.
6435 if (InVec0 != Op0.getOperand(0)) {
6436 if (ExpectedOpcode == ISD::FSUB)
6439 // FADD is commutable. Try to commute the operands
6440 // and then test again.
6441 std::swap(Op0, Op1);
6442 if (InVec0 != Op0.getOperand(0))
6446 if (InVec1 != Op1.getOperand(0))
6449 // Update the pair of expected opcodes.
6450 std::swap(ExpectedOpcode, NextExpectedOpcode);
6453 // Don't try to fold this build_vector into a VSELECT if it has
6454 // too many UNDEF operands.
6455 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6456 InVec1.getOpcode() != ISD::UNDEF) {
6457 // Emit a sequence of vector add and sub followed by a VSELECT.
6458 // The new VSELECT will be lowered into a BLENDI.
6459 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6460 // and emit a single ADDSUB instruction.
6461 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6462 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6464 // Construct the VSELECT mask.
6465 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6466 EVT SVT = MaskVT.getVectorElementType();
6467 unsigned SVTBits = SVT.getSizeInBits();
6468 SmallVector<SDValue, 8> Ops;
6470 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6471 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6472 APInt::getAllOnesValue(SVTBits);
6473 SDValue Constant = DAG.getConstant(Value, SVT);
6474 Ops.push_back(Constant);
6477 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6478 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6484 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6485 const X86Subtarget *Subtarget) {
6487 EVT VT = N->getValueType(0);
6488 unsigned NumElts = VT.getVectorNumElements();
6489 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6490 SDValue InVec0, InVec1;
6492 // Try to match an ADDSUB.
6493 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6494 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6495 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6496 if (Value.getNode())
6500 // Try to match horizontal ADD/SUB.
6501 unsigned NumUndefsLO = 0;
6502 unsigned NumUndefsHI = 0;
6503 unsigned Half = NumElts/2;
6505 // Count the number of UNDEF operands in the build_vector in input.
6506 for (unsigned i = 0, e = Half; i != e; ++i)
6507 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6510 for (unsigned i = Half, e = NumElts; i != e; ++i)
6511 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6514 // Early exit if this is either a build_vector of all UNDEFs or all the
6515 // operands but one are UNDEF.
6516 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6519 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6520 // Try to match an SSE3 float HADD/HSUB.
6521 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6522 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6524 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6525 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6526 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6527 // Try to match an SSSE3 integer HADD/HSUB.
6528 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6529 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6531 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6532 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6535 if (!Subtarget->hasAVX())
6538 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6539 // Try to match an AVX horizontal add/sub of packed single/double
6540 // precision floating point values from 256-bit vectors.
6541 SDValue InVec2, InVec3;
6542 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6543 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6544 ((InVec0.getOpcode() == ISD::UNDEF ||
6545 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6546 ((InVec1.getOpcode() == ISD::UNDEF ||
6547 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6548 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6550 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6551 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6552 ((InVec0.getOpcode() == ISD::UNDEF ||
6553 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6554 ((InVec1.getOpcode() == ISD::UNDEF ||
6555 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6556 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6557 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6558 // Try to match an AVX2 horizontal add/sub of signed integers.
6559 SDValue InVec2, InVec3;
6561 bool CanFold = true;
6563 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6564 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6565 ((InVec0.getOpcode() == ISD::UNDEF ||
6566 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6567 ((InVec1.getOpcode() == ISD::UNDEF ||
6568 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6569 X86Opcode = X86ISD::HADD;
6570 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6571 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6572 ((InVec0.getOpcode() == ISD::UNDEF ||
6573 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6574 ((InVec1.getOpcode() == ISD::UNDEF ||
6575 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6576 X86Opcode = X86ISD::HSUB;
6581 // Fold this build_vector into a single horizontal add/sub.
6582 // Do this only if the target has AVX2.
6583 if (Subtarget->hasAVX2())
6584 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6586 // Do not try to expand this build_vector into a pair of horizontal
6587 // add/sub if we can emit a pair of scalar add/sub.
6588 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6591 // Convert this build_vector into a pair of horizontal binop followed by
6593 bool isUndefLO = NumUndefsLO == Half;
6594 bool isUndefHI = NumUndefsHI == Half;
6595 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6596 isUndefLO, isUndefHI);
6600 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6601 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6603 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6604 X86Opcode = X86ISD::HADD;
6605 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6606 X86Opcode = X86ISD::HSUB;
6607 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6608 X86Opcode = X86ISD::FHADD;
6609 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6610 X86Opcode = X86ISD::FHSUB;
6614 // Don't try to expand this build_vector into a pair of horizontal add/sub
6615 // if we can simply emit a pair of scalar add/sub.
6616 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6619 // Convert this build_vector into two horizontal add/sub followed by
6621 bool isUndefLO = NumUndefsLO == Half;
6622 bool isUndefHI = NumUndefsHI == Half;
6623 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6624 isUndefLO, isUndefHI);
6631 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6634 MVT VT = Op.getSimpleValueType();
6635 MVT ExtVT = VT.getVectorElementType();
6636 unsigned NumElems = Op.getNumOperands();
6638 // Generate vectors for predicate vectors.
6639 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6640 return LowerBUILD_VECTORvXi1(Op, DAG);
6642 // Vectors containing all zeros can be matched by pxor and xorps later
6643 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6644 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6645 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6646 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6649 return getZeroVector(VT, Subtarget, DAG, dl);
6652 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6653 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6654 // vpcmpeqd on 256-bit vectors.
6655 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6656 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6659 if (!VT.is512BitVector())
6660 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6663 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6664 if (Broadcast.getNode())
6667 unsigned EVTBits = ExtVT.getSizeInBits();
6669 unsigned NumZero = 0;
6670 unsigned NumNonZero = 0;
6671 unsigned NonZeros = 0;
6672 bool IsAllConstants = true;
6673 SmallSet<SDValue, 8> Values;
6674 for (unsigned i = 0; i < NumElems; ++i) {
6675 SDValue Elt = Op.getOperand(i);
6676 if (Elt.getOpcode() == ISD::UNDEF)
6679 if (Elt.getOpcode() != ISD::Constant &&
6680 Elt.getOpcode() != ISD::ConstantFP)
6681 IsAllConstants = false;
6682 if (X86::isZeroNode(Elt))
6685 NonZeros |= (1 << i);
6690 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6691 if (NumNonZero == 0)
6692 return DAG.getUNDEF(VT);
6694 // Special case for single non-zero, non-undef, element.
6695 if (NumNonZero == 1) {
6696 unsigned Idx = countTrailingZeros(NonZeros);
6697 SDValue Item = Op.getOperand(Idx);
6699 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6700 // the value are obviously zero, truncate the value to i32 and do the
6701 // insertion that way. Only do this if the value is non-constant or if the
6702 // value is a constant being inserted into element 0. It is cheaper to do
6703 // a constant pool load than it is to do a movd + shuffle.
6704 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6705 (!IsAllConstants || Idx == 0)) {
6706 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6708 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6709 EVT VecVT = MVT::v4i32;
6710 unsigned VecElts = 4;
6712 // Truncate the value (which may itself be a constant) to i32, and
6713 // convert it to a vector with movd (S2V+shuffle to zero extend).
6714 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6715 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6716 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6718 // Now we have our 32-bit value zero extended in the low element of
6719 // a vector. If Idx != 0, swizzle it into place.
6721 SmallVector<int, 4> Mask;
6722 Mask.push_back(Idx);
6723 for (unsigned i = 1; i != VecElts; ++i)
6725 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6728 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6732 // If we have a constant or non-constant insertion into the low element of
6733 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6734 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6735 // depending on what the source datatype is.
6738 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6740 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6741 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6742 if (VT.is256BitVector() || VT.is512BitVector()) {
6743 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6744 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6745 Item, DAG.getIntPtrConstant(0));
6747 assert(VT.is128BitVector() && "Expected an SSE value type!");
6748 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6749 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6750 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6753 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6754 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6755 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6756 if (VT.is256BitVector()) {
6757 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6758 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6760 assert(VT.is128BitVector() && "Expected an SSE value type!");
6761 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6763 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6767 // Is it a vector logical left shift?
6768 if (NumElems == 2 && Idx == 1 &&
6769 X86::isZeroNode(Op.getOperand(0)) &&
6770 !X86::isZeroNode(Op.getOperand(1))) {
6771 unsigned NumBits = VT.getSizeInBits();
6772 return getVShift(true, VT,
6773 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6774 VT, Op.getOperand(1)),
6775 NumBits/2, DAG, *this, dl);
6778 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6781 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6782 // is a non-constant being inserted into an element other than the low one,
6783 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6784 // movd/movss) to move this into the low element, then shuffle it into
6786 if (EVTBits == 32) {
6787 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6789 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6790 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6791 SmallVector<int, 8> MaskVec;
6792 for (unsigned i = 0; i != NumElems; ++i)
6793 MaskVec.push_back(i == Idx ? 0 : 1);
6794 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6798 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6799 if (Values.size() == 1) {
6800 if (EVTBits == 32) {
6801 // Instead of a shuffle like this:
6802 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6803 // Check if it's possible to issue this instead.
6804 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6805 unsigned Idx = countTrailingZeros(NonZeros);
6806 SDValue Item = Op.getOperand(Idx);
6807 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6808 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6813 // A vector full of immediates; various special cases are already
6814 // handled, so this is best done with a single constant-pool load.
6818 // For AVX-length vectors, build the individual 128-bit pieces and use
6819 // shuffles to put them in place.
6820 if (VT.is256BitVector() || VT.is512BitVector()) {
6821 SmallVector<SDValue, 64> V;
6822 for (unsigned i = 0; i != NumElems; ++i)
6823 V.push_back(Op.getOperand(i));
6825 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6827 // Build both the lower and upper subvector.
6828 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6829 makeArrayRef(&V[0], NumElems/2));
6830 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6831 makeArrayRef(&V[NumElems / 2], NumElems/2));
6833 // Recreate the wider vector with the lower and upper part.
6834 if (VT.is256BitVector())
6835 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6836 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6839 // Let legalizer expand 2-wide build_vectors.
6840 if (EVTBits == 64) {
6841 if (NumNonZero == 1) {
6842 // One half is zero or undef.
6843 unsigned Idx = countTrailingZeros(NonZeros);
6844 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6845 Op.getOperand(Idx));
6846 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6851 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6852 if (EVTBits == 8 && NumElems == 16) {
6853 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6855 if (V.getNode()) return V;
6858 if (EVTBits == 16 && NumElems == 8) {
6859 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6861 if (V.getNode()) return V;
6864 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6865 if (EVTBits == 32 && NumElems == 4) {
6866 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6867 NumZero, DAG, Subtarget, *this);
6872 // If element VT is == 32 bits, turn it into a number of shuffles.
6873 SmallVector<SDValue, 8> V(NumElems);
6874 if (NumElems == 4 && NumZero > 0) {
6875 for (unsigned i = 0; i < 4; ++i) {
6876 bool isZero = !(NonZeros & (1 << i));
6878 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6880 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6883 for (unsigned i = 0; i < 2; ++i) {
6884 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6887 V[i] = V[i*2]; // Must be a zero vector.
6890 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6893 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6896 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6901 bool Reverse1 = (NonZeros & 0x3) == 2;
6902 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6906 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6907 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6909 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6912 if (Values.size() > 1 && VT.is128BitVector()) {
6913 // Check for a build vector of consecutive loads.
6914 for (unsigned i = 0; i < NumElems; ++i)
6915 V[i] = Op.getOperand(i);
6917 // Check for elements which are consecutive loads.
6918 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6922 // Check for a build vector from mostly shuffle plus few inserting.
6923 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6927 // For SSE 4.1, use insertps to put the high elements into the low element.
6928 if (getSubtarget()->hasSSE41()) {
6930 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6931 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6933 Result = DAG.getUNDEF(VT);
6935 for (unsigned i = 1; i < NumElems; ++i) {
6936 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6937 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6938 Op.getOperand(i), DAG.getIntPtrConstant(i));
6943 // Otherwise, expand into a number of unpckl*, start by extending each of
6944 // our (non-undef) elements to the full vector width with the element in the
6945 // bottom slot of the vector (which generates no code for SSE).
6946 for (unsigned i = 0; i < NumElems; ++i) {
6947 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6948 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6950 V[i] = DAG.getUNDEF(VT);
6953 // Next, we iteratively mix elements, e.g. for v4f32:
6954 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6955 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6956 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6957 unsigned EltStride = NumElems >> 1;
6958 while (EltStride != 0) {
6959 for (unsigned i = 0; i < EltStride; ++i) {
6960 // If V[i+EltStride] is undef and this is the first round of mixing,
6961 // then it is safe to just drop this shuffle: V[i] is already in the
6962 // right place, the one element (since it's the first round) being
6963 // inserted as undef can be dropped. This isn't safe for successive
6964 // rounds because they will permute elements within both vectors.
6965 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6966 EltStride == NumElems/2)
6969 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6978 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6979 // to create 256-bit vectors from two other 128-bit ones.
6980 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6982 MVT ResVT = Op.getSimpleValueType();
6984 assert((ResVT.is256BitVector() ||
6985 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6987 SDValue V1 = Op.getOperand(0);
6988 SDValue V2 = Op.getOperand(1);
6989 unsigned NumElems = ResVT.getVectorNumElements();
6990 if(ResVT.is256BitVector())
6991 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6993 if (Op.getNumOperands() == 4) {
6994 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6995 ResVT.getVectorNumElements()/2);
6996 SDValue V3 = Op.getOperand(2);
6997 SDValue V4 = Op.getOperand(3);
6998 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6999 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7001 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7004 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7005 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7006 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7007 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7008 Op.getNumOperands() == 4)));
7010 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7011 // from two other 128-bit ones.
7013 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7014 return LowerAVXCONCAT_VECTORS(Op, DAG);
7018 //===----------------------------------------------------------------------===//
7019 // Vector shuffle lowering
7021 // This is an experimental code path for lowering vector shuffles on x86. It is
7022 // designed to handle arbitrary vector shuffles and blends, gracefully
7023 // degrading performance as necessary. It works hard to recognize idiomatic
7024 // shuffles and lower them to optimal instruction patterns without leaving
7025 // a framework that allows reasonably efficient handling of all vector shuffle
7027 //===----------------------------------------------------------------------===//
7029 /// \brief Tiny helper function to identify a no-op mask.
7031 /// This is a somewhat boring predicate function. It checks whether the mask
7032 /// array input, which is assumed to be a single-input shuffle mask of the kind
7033 /// used by the X86 shuffle instructions (not a fully general
7034 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7035 /// in-place shuffle are 'no-op's.
7036 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7037 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7038 if (Mask[i] != -1 && Mask[i] != i)
7043 /// \brief Helper function to classify a mask as a single-input mask.
7045 /// This isn't a generic single-input test because in the vector shuffle
7046 /// lowering we canonicalize single inputs to be the first input operand. This
7047 /// means we can more quickly test for a single input by only checking whether
7048 /// an input from the second operand exists. We also assume that the size of
7049 /// mask corresponds to the size of the input vectors which isn't true in the
7050 /// fully general case.
7051 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7053 if (M >= (int)Mask.size())
7058 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7060 /// This helper function produces an 8-bit shuffle immediate corresponding to
7061 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7062 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7065 /// NB: We rely heavily on "undef" masks preserving the input lane.
7066 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7067 SelectionDAG &DAG) {
7068 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7069 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7070 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7071 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7072 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7075 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7076 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7077 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7078 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7079 return DAG.getConstant(Imm, MVT::i8);
7082 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7084 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7085 /// support for floating point shuffles but not integer shuffles. These
7086 /// instructions will incur a domain crossing penalty on some chips though so
7087 /// it is better to avoid lowering through this for integer vectors where
7089 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7090 const X86Subtarget *Subtarget,
7091 SelectionDAG &DAG) {
7093 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7094 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7095 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7097 ArrayRef<int> Mask = SVOp->getMask();
7098 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7100 if (isSingleInputShuffleMask(Mask)) {
7101 // Straight shuffle of a single input vector. Simulate this by using the
7102 // single input as both of the "inputs" to this instruction..
7103 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7104 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7105 DAG.getConstant(SHUFPDMask, MVT::i8));
7107 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7108 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7110 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7111 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7112 DAG.getConstant(SHUFPDMask, MVT::i8));
7115 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7117 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7118 /// the integer unit to minimize domain crossing penalties. However, for blends
7119 /// it falls back to the floating point shuffle operation with appropriate bit
7121 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7122 const X86Subtarget *Subtarget,
7123 SelectionDAG &DAG) {
7125 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7126 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7127 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7128 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7129 ArrayRef<int> Mask = SVOp->getMask();
7130 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7132 if (isSingleInputShuffleMask(Mask)) {
7133 // Straight shuffle of a single input vector. For everything from SSE2
7134 // onward this has a single fast instruction with no scary immediates.
7135 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7136 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7137 int WidenedMask[4] = {
7138 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7139 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7141 ISD::BITCAST, DL, MVT::v2i64,
7142 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7143 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7146 // We implement this with SHUFPD which is pretty lame because it will likely
7147 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7148 // However, all the alternatives are still more cycles and newer chips don't
7149 // have this problem. It would be really nice if x86 had better shuffles here.
7150 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7151 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7152 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7153 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7156 /// \brief Lower 4-lane 32-bit floating point shuffles.
7158 /// Uses instructions exclusively from the floating point unit to minimize
7159 /// domain crossing penalties, as these are sufficient to implement all v4f32
7161 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7162 const X86Subtarget *Subtarget,
7163 SelectionDAG &DAG) {
7165 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7166 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7167 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7168 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7169 ArrayRef<int> Mask = SVOp->getMask();
7170 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7172 SDValue LowV = V1, HighV = V2;
7173 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7176 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7178 if (NumV2Elements == 0)
7179 // Straight shuffle of a single input vector. We pass the input vector to
7180 // both operands to simulate this with a SHUFPS.
7181 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7182 getV4X86ShuffleImm8ForMask(Mask, DAG));
7184 if (NumV2Elements == 1) {
7186 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7188 // Compute the index adjacent to V2Index and in the same half by toggling
7190 int V2AdjIndex = V2Index ^ 1;
7192 if (Mask[V2AdjIndex] == -1) {
7193 // Handles all the cases where we have a single V2 element and an undef.
7194 // This will only ever happen in the high lanes because we commute the
7195 // vector otherwise.
7197 std::swap(LowV, HighV);
7198 NewMask[V2Index] -= 4;
7200 // Handle the case where the V2 element ends up adjacent to a V1 element.
7201 // To make this work, blend them together as the first step.
7202 int V1Index = V2AdjIndex;
7203 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7204 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7205 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7207 // Now proceed to reconstruct the final blend as we have the necessary
7208 // high or low half formed.
7215 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7216 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7218 } else if (NumV2Elements == 2) {
7219 if (Mask[0] < 4 && Mask[1] < 4) {
7220 // Handle the easy case where we have V1 in the low lanes and V2 in the
7221 // high lanes. We never see this reversed because we sort the shuffle.
7225 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7226 // trying to place elements directly, just blend them and set up the final
7227 // shuffle to place them.
7229 // The first two blend mask elements are for V1, the second two are for
7231 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7232 Mask[2] < 4 ? Mask[2] : Mask[3],
7233 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7234 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7235 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7236 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7238 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7241 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7242 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7243 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7244 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7247 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7248 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7251 /// \brief Lower 4-lane i32 vector shuffles.
7253 /// We try to handle these with integer-domain shuffles where we can, but for
7254 /// blends we use the floating point domain blend instructions.
7255 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7256 const X86Subtarget *Subtarget,
7257 SelectionDAG &DAG) {
7259 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7260 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7261 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7262 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7263 ArrayRef<int> Mask = SVOp->getMask();
7264 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7266 if (isSingleInputShuffleMask(Mask))
7267 // Straight shuffle of a single input vector. For everything from SSE2
7268 // onward this has a single fast instruction with no scary immediates.
7269 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7270 getV4X86ShuffleImm8ForMask(Mask, DAG));
7272 // We implement this with SHUFPS because it can blend from two vectors.
7273 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7274 // up the inputs, bypassing domain shift penalties that we would encur if we
7275 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7277 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7278 DAG.getVectorShuffle(
7280 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7281 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7284 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7285 /// shuffle lowering, and the most complex part.
7287 /// The lowering strategy is to try to form pairs of input lanes which are
7288 /// targeted at the same half of the final vector, and then use a dword shuffle
7289 /// to place them onto the right half, and finally unpack the paired lanes into
7290 /// their final position.
7292 /// The exact breakdown of how to form these dword pairs and align them on the
7293 /// correct sides is really tricky. See the comments within the function for
7294 /// more of the details.
7295 static SDValue lowerV8I16SingleInputVectorShuffle(
7296 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7297 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7298 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7299 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7300 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7302 SmallVector<int, 4> LoInputs;
7303 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7304 [](int M) { return M >= 0; });
7305 std::sort(LoInputs.begin(), LoInputs.end());
7306 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7307 SmallVector<int, 4> HiInputs;
7308 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7309 [](int M) { return M >= 0; });
7310 std::sort(HiInputs.begin(), HiInputs.end());
7311 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7313 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7314 int NumHToL = LoInputs.size() - NumLToL;
7316 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7317 int NumHToH = HiInputs.size() - NumLToH;
7318 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7319 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7320 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7321 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7323 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7324 // such inputs we can swap two of the dwords across the half mark and end up
7325 // with <=2 inputs to each half in each half. Once there, we can fall through
7326 // to the generic code below. For example:
7328 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7329 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7331 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7332 // and an existing 2-into-2 on the other half. In this case we may have to
7333 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7334 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7335 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7336 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7337 // half than the one we target for fixing) will be fixed when we re-enter this
7338 // path. We will also combine away any sequence of PSHUFD instructions that
7339 // result into a single instruction. Here is an example of the tricky case:
7341 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7342 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7344 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7346 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7347 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7349 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7350 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7352 // The result is fine to be handled by the generic logic.
7353 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7354 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7355 int AOffset, int BOffset) {
7356 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7357 "Must call this with A having 3 or 1 inputs from the A half.");
7358 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7359 "Must call this with B having 1 or 3 inputs from the B half.");
7360 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7361 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7363 // Compute the index of dword with only one word among the three inputs in
7364 // a half by taking the sum of the half with three inputs and subtracting
7365 // the sum of the actual three inputs. The difference is the remaining
7368 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7369 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7370 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7371 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7372 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7373 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7374 int TripleNonInputIdx =
7375 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7376 TripleDWord = TripleNonInputIdx / 2;
7378 // We use xor with one to compute the adjacent DWord to whichever one the
7380 OneInputDWord = (OneInput / 2) ^ 1;
7382 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7383 // and BToA inputs. If there is also such a problem with the BToB and AToB
7384 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7385 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7386 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7387 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7388 // Compute how many inputs will be flipped by swapping these DWords. We
7390 // to balance this to ensure we don't form a 3-1 shuffle in the other
7392 int NumFlippedAToBInputs =
7393 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7394 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7395 int NumFlippedBToBInputs =
7396 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7397 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7398 if ((NumFlippedAToBInputs == 1 &&
7399 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7400 (NumFlippedBToBInputs == 1 &&
7401 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7402 // We choose whether to fix the A half or B half based on whether that
7403 // half has zero flipped inputs. At zero, we may not be able to fix it
7404 // with that half. We also bias towards fixing the B half because that
7405 // will more commonly be the high half, and we have to bias one way.
7406 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7407 ArrayRef<int> Inputs) {
7408 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7409 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7410 PinnedIdx ^ 1) != Inputs.end();
7411 // Determine whether the free index is in the flipped dword or the
7412 // unflipped dword based on where the pinned index is. We use this bit
7413 // in an xor to conditionally select the adjacent dword.
7414 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7415 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7416 FixFreeIdx) != Inputs.end();
7417 if (IsFixIdxInput == IsFixFreeIdxInput)
7419 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7420 FixFreeIdx) != Inputs.end();
7421 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7422 "We need to be changing the number of flipped inputs!");
7423 int PSHUFHalfMask[] = {0, 1, 2, 3};
7424 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7425 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7427 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7430 if (M != -1 && M == FixIdx)
7432 else if (M != -1 && M == FixFreeIdx)
7435 if (NumFlippedBToBInputs != 0) {
7437 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7438 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7440 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7442 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7443 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7448 int PSHUFDMask[] = {0, 1, 2, 3};
7449 PSHUFDMask[ADWord] = BDWord;
7450 PSHUFDMask[BDWord] = ADWord;
7451 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7452 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7453 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7454 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7456 // Adjust the mask to match the new locations of A and B.
7458 if (M != -1 && M/2 == ADWord)
7459 M = 2 * BDWord + M % 2;
7460 else if (M != -1 && M/2 == BDWord)
7461 M = 2 * ADWord + M % 2;
7463 // Recurse back into this routine to re-compute state now that this isn't
7464 // a 3 and 1 problem.
7465 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7468 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
7469 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
7470 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
7471 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
7473 // At this point there are at most two inputs to the low and high halves from
7474 // each half. That means the inputs can always be grouped into dwords and
7475 // those dwords can then be moved to the correct half with a dword shuffle.
7476 // We use at most one low and one high word shuffle to collect these paired
7477 // inputs into dwords, and finally a dword shuffle to place them.
7478 int PSHUFLMask[4] = {-1, -1, -1, -1};
7479 int PSHUFHMask[4] = {-1, -1, -1, -1};
7480 int PSHUFDMask[4] = {-1, -1, -1, -1};
7482 // First fix the masks for all the inputs that are staying in their
7483 // original halves. This will then dictate the targets of the cross-half
7485 auto fixInPlaceInputs =
7486 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
7487 MutableArrayRef<int> SourceHalfMask,
7488 MutableArrayRef<int> HalfMask, int HalfOffset) {
7489 if (InPlaceInputs.empty())
7491 if (InPlaceInputs.size() == 1) {
7492 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7493 InPlaceInputs[0] - HalfOffset;
7494 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7497 if (IncomingInputs.empty()) {
7498 // Just fix all of the in place inputs.
7499 for (int Input : InPlaceInputs) {
7500 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
7501 PSHUFDMask[Input / 2] = Input / 2;
7506 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7507 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7508 InPlaceInputs[0] - HalfOffset;
7509 // Put the second input next to the first so that they are packed into
7510 // a dword. We find the adjacent index by toggling the low bit.
7511 int AdjIndex = InPlaceInputs[0] ^ 1;
7512 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7513 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7514 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7516 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
7517 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
7519 // Now gather the cross-half inputs and place them into a free dword of
7520 // their target half.
7521 // FIXME: This operation could almost certainly be simplified dramatically to
7522 // look more like the 3-1 fixing operation.
7523 auto moveInputsToRightHalf = [&PSHUFDMask](
7524 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7525 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7526 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
7528 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7529 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7531 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7533 int LowWord = Word & ~1;
7534 int HighWord = Word | 1;
7535 return isWordClobbered(SourceHalfMask, LowWord) ||
7536 isWordClobbered(SourceHalfMask, HighWord);
7539 if (IncomingInputs.empty())
7542 if (ExistingInputs.empty()) {
7543 // Map any dwords with inputs from them into the right half.
7544 for (int Input : IncomingInputs) {
7545 // If the source half mask maps over the inputs, turn those into
7546 // swaps and use the swapped lane.
7547 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7548 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7549 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7550 Input - SourceOffset;
7551 // We have to swap the uses in our half mask in one sweep.
7552 for (int &M : HalfMask)
7553 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
7555 else if (M == Input)
7556 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7558 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7559 Input - SourceOffset &&
7560 "Previous placement doesn't match!");
7562 // Note that this correctly re-maps both when we do a swap and when
7563 // we observe the other side of the swap above. We rely on that to
7564 // avoid swapping the members of the input list directly.
7565 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7568 // Map the input's dword into the correct half.
7569 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7570 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7572 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7574 "Previous placement doesn't match!");
7577 // And just directly shift any other-half mask elements to be same-half
7578 // as we will have mirrored the dword containing the element into the
7579 // same position within that half.
7580 for (int &M : HalfMask)
7581 if (M >= SourceOffset && M < SourceOffset + 4) {
7582 M = M - SourceOffset + DestOffset;
7583 assert(M >= 0 && "This should never wrap below zero!");
7588 // Ensure we have the input in a viable dword of its current half. This
7589 // is particularly tricky because the original position may be clobbered
7590 // by inputs being moved and *staying* in that half.
7591 if (IncomingInputs.size() == 1) {
7592 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7593 int InputFixed = std::find(std::begin(SourceHalfMask),
7594 std::end(SourceHalfMask), -1) -
7595 std::begin(SourceHalfMask) + SourceOffset;
7596 SourceHalfMask[InputFixed - SourceOffset] =
7597 IncomingInputs[0] - SourceOffset;
7598 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7600 IncomingInputs[0] = InputFixed;
7602 } else if (IncomingInputs.size() == 2) {
7603 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7604 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7605 // We have two non-adjacent or clobbered inputs we need to extract from
7606 // the source half. To do this, we need to map them into some adjacent
7607 // dword slot in the source mask.
7608 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
7609 IncomingInputs[1] - SourceOffset};
7611 // If there is a free slot in the source half mask adjacent to one of
7612 // the inputs, place the other input in it. We use (Index XOR 1) to
7613 // compute an adjacent index.
7614 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
7615 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
7616 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
7617 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7618 InputsFixed[1] = InputsFixed[0] ^ 1;
7619 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
7620 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
7621 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
7622 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
7623 InputsFixed[0] = InputsFixed[1] ^ 1;
7624 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
7625 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
7626 // The two inputs are in the same DWord but it is clobbered and the
7627 // adjacent DWord isn't used at all. Move both inputs to the free
7629 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
7630 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
7631 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
7632 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
7634 // The only way we hit this point is if there is no clobbering
7635 // (because there are no off-half inputs to this half) and there is no
7636 // free slot adjacent to one of the inputs. In this case, we have to
7637 // swap an input with a non-input.
7638 for (int i = 0; i < 4; ++i)
7639 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
7640 "We can't handle any clobbers here!");
7641 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
7642 "Cannot have adjacent inputs here!");
7644 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
7645 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
7647 // We also have to update the final source mask in this case because
7648 // it may need to undo the above swap.
7649 for (int &M : FinalSourceHalfMask)
7650 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
7651 M = InputsFixed[1] + SourceOffset;
7652 else if (M == InputsFixed[1] + SourceOffset)
7653 M = (InputsFixed[0] ^ 1) + SourceOffset;
7655 InputsFixed[1] = InputsFixed[0] ^ 1;
7658 // Point everything at the fixed inputs.
7659 for (int &M : HalfMask)
7660 if (M == IncomingInputs[0])
7661 M = InputsFixed[0] + SourceOffset;
7662 else if (M == IncomingInputs[1])
7663 M = InputsFixed[1] + SourceOffset;
7665 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
7666 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
7669 llvm_unreachable("Unhandled input size!");
7672 // Now hoist the DWord down to the right half.
7673 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7674 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7675 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7676 for (int &M : HalfMask)
7677 for (int Input : IncomingInputs)
7679 M = FreeDWord * 2 + Input % 2;
7681 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
7682 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7683 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
7684 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7686 // Now enact all the shuffles we've computed to move the inputs into their
7688 if (!isNoopShuffleMask(PSHUFLMask))
7689 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7690 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7691 if (!isNoopShuffleMask(PSHUFHMask))
7692 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7693 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7694 if (!isNoopShuffleMask(PSHUFDMask))
7695 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7696 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7697 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7698 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7700 // At this point, each half should contain all its inputs, and we can then
7701 // just shuffle them into their final position.
7702 assert(std::count_if(LoMask.begin(), LoMask.end(),
7703 [](int M) { return M >= 4; }) == 0 &&
7704 "Failed to lift all the high half inputs to the low mask!");
7705 assert(std::count_if(HiMask.begin(), HiMask.end(),
7706 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7707 "Failed to lift all the low half inputs to the high mask!");
7709 // Do a half shuffle for the low mask.
7710 if (!isNoopShuffleMask(LoMask))
7711 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7712 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7714 // Do a half shuffle with the high mask after shifting its values down.
7715 for (int &M : HiMask)
7718 if (!isNoopShuffleMask(HiMask))
7719 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7720 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7725 /// \brief Detect whether the mask pattern should be lowered through
7728 /// This essentially tests whether viewing the mask as an interleaving of two
7729 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7730 /// lowering it through interleaving is a significantly better strategy.
7731 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7732 int NumEvenInputs[2] = {0, 0};
7733 int NumOddInputs[2] = {0, 0};
7734 int NumLoInputs[2] = {0, 0};
7735 int NumHiInputs[2] = {0, 0};
7736 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7740 int InputIdx = Mask[i] >= Size;
7743 ++NumLoInputs[InputIdx];
7745 ++NumHiInputs[InputIdx];
7748 ++NumEvenInputs[InputIdx];
7750 ++NumOddInputs[InputIdx];
7753 // The minimum number of cross-input results for both the interleaved and
7754 // split cases. If interleaving results in fewer cross-input results, return
7756 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7757 NumEvenInputs[0] + NumOddInputs[1]);
7758 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7759 NumLoInputs[0] + NumHiInputs[1]);
7760 return InterleavedCrosses < SplitCrosses;
7763 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7765 /// This strategy only works when the inputs from each vector fit into a single
7766 /// half of that vector, and generally there are not so many inputs as to leave
7767 /// the in-place shuffles required highly constrained (and thus expensive). It
7768 /// shifts all the inputs into a single side of both input vectors and then
7769 /// uses an unpack to interleave these inputs in a single vector. At that
7770 /// point, we will fall back on the generic single input shuffle lowering.
7771 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7773 MutableArrayRef<int> Mask,
7774 const X86Subtarget *Subtarget,
7775 SelectionDAG &DAG) {
7776 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7777 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7778 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7779 for (int i = 0; i < 8; ++i)
7780 if (Mask[i] >= 0 && Mask[i] < 4)
7781 LoV1Inputs.push_back(i);
7782 else if (Mask[i] >= 4 && Mask[i] < 8)
7783 HiV1Inputs.push_back(i);
7784 else if (Mask[i] >= 8 && Mask[i] < 12)
7785 LoV2Inputs.push_back(i);
7786 else if (Mask[i] >= 12)
7787 HiV2Inputs.push_back(i);
7789 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7790 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7793 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7794 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7795 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7797 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7798 HiV1Inputs.size() + HiV2Inputs.size();
7800 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7801 ArrayRef<int> HiInputs, bool MoveToLo,
7803 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7804 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7805 if (BadInputs.empty())
7808 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7809 int MoveOffset = MoveToLo ? 0 : 4;
7811 if (GoodInputs.empty()) {
7812 for (int BadInput : BadInputs) {
7813 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7814 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7817 if (GoodInputs.size() == 2) {
7818 // If the low inputs are spread across two dwords, pack them into
7820 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
7821 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
7822 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
7823 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
7825 // Otherwise pin the good inputs.
7826 for (int GoodInput : GoodInputs)
7827 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7830 if (BadInputs.size() == 2) {
7831 // If we have two bad inputs then there may be either one or two good
7832 // inputs fixed in place. Find a fixed input, and then find the *other*
7833 // two adjacent indices by using modular arithmetic.
7835 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
7836 [](int M) { return M >= 0; }) -
7837 std::begin(MoveMask);
7839 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
7840 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7841 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7842 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7843 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
7844 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7845 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
7847 assert(BadInputs.size() == 1 && "All sizes handled");
7848 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
7849 std::end(MoveMask), -1) -
7850 std::begin(MoveMask);
7851 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7852 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7856 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7859 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7861 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7864 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7865 // cross-half traffic in the final shuffle.
7867 // Munge the mask to be a single-input mask after the unpack merges the
7871 M = 2 * (M % 4) + (M / 8);
7873 return DAG.getVectorShuffle(
7874 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7875 DL, MVT::v8i16, V1, V2),
7876 DAG.getUNDEF(MVT::v8i16), Mask);
7879 /// \brief Generic lowering of 8-lane i16 shuffles.
7881 /// This handles both single-input shuffles and combined shuffle/blends with
7882 /// two inputs. The single input shuffles are immediately delegated to
7883 /// a dedicated lowering routine.
7885 /// The blends are lowered in one of three fundamental ways. If there are few
7886 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7887 /// of the input is significantly cheaper when lowered as an interleaving of
7888 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7889 /// halves of the inputs separately (making them have relatively few inputs)
7890 /// and then concatenate them.
7891 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7892 const X86Subtarget *Subtarget,
7893 SelectionDAG &DAG) {
7895 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7896 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7897 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7898 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7899 ArrayRef<int> OrigMask = SVOp->getMask();
7900 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7901 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7902 MutableArrayRef<int> Mask(MaskStorage);
7904 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7906 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7907 auto isV2 = [](int M) { return M >= 8; };
7909 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7910 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7912 if (NumV2Inputs == 0)
7913 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7915 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7916 "to be V1-input shuffles.");
7918 if (NumV1Inputs + NumV2Inputs <= 4)
7919 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7921 // Check whether an interleaving lowering is likely to be more efficient.
7922 // This isn't perfect but it is a strong heuristic that tends to work well on
7923 // the kinds of shuffles that show up in practice.
7925 // FIXME: Handle 1x, 2x, and 4x interleaving.
7926 if (shouldLowerAsInterleaving(Mask)) {
7927 // FIXME: Figure out whether we should pack these into the low or high
7930 int EMask[8], OMask[8];
7931 for (int i = 0; i < 4; ++i) {
7932 EMask[i] = Mask[2*i];
7933 OMask[i] = Mask[2*i + 1];
7938 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7939 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7941 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7944 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7945 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7947 for (int i = 0; i < 4; ++i) {
7948 LoBlendMask[i] = Mask[i];
7949 HiBlendMask[i] = Mask[i + 4];
7952 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7953 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7954 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7955 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7957 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7958 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7961 /// \brief Check whether a compaction lowering can be done by dropping even
7962 /// elements and compute how many times even elements must be dropped.
7964 /// This handles shuffles which take every Nth element where N is a power of
7965 /// two. Example shuffle masks:
7967 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
7968 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
7969 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
7970 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
7971 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
7972 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
7974 /// Any of these lanes can of course be undef.
7976 /// This routine only supports N <= 3.
7977 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
7980 /// \returns N above, or the number of times even elements must be dropped if
7981 /// there is such a number. Otherwise returns zero.
7982 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
7983 // Figure out whether we're looping over two inputs or just one.
7984 bool IsSingleInput = isSingleInputShuffleMask(Mask);
7986 // The modulus for the shuffle vector entries is based on whether this is
7987 // a single input or not.
7988 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
7989 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
7990 "We should only be called with masks with a power-of-2 size!");
7992 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
7994 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
7995 // and 2^3 simultaneously. This is because we may have ambiguity with
7996 // partially undef inputs.
7997 bool ViableForN[3] = {true, true, true};
7999 for (int i = 0, e = Mask.size(); i < e; ++i) {
8000 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8005 bool IsAnyViable = false;
8006 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8007 if (ViableForN[j]) {
8010 // The shuffle mask must be equal to (i * 2^N) % M.
8011 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8014 ViableForN[j] = false;
8016 // Early exit if we exhaust the possible powers of two.
8021 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8025 // Return 0 as there is no viable power of two.
8029 /// \brief Generic lowering of v16i8 shuffles.
8031 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8032 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8033 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8034 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8036 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8037 const X86Subtarget *Subtarget,
8038 SelectionDAG &DAG) {
8040 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8041 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8042 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8044 ArrayRef<int> OrigMask = SVOp->getMask();
8045 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8046 int MaskStorage[16] = {
8047 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8048 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
8049 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
8050 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
8051 MutableArrayRef<int> Mask(MaskStorage);
8052 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
8053 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
8055 // For single-input shuffles, there are some nicer lowering tricks we can use.
8056 if (isSingleInputShuffleMask(Mask)) {
8057 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8058 // Notably, this handles splat and partial-splat shuffles more efficiently.
8059 // However, it only makes sense if the pre-duplication shuffle simplifies
8060 // things significantly. Currently, this means we need to be able to
8061 // express the pre-duplication shuffle as an i16 shuffle.
8063 // FIXME: We should check for other patterns which can be widened into an
8064 // i16 shuffle as well.
8065 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8066 for (int i = 0; i < 16; i += 2) {
8067 if (Mask[i] != Mask[i + 1])
8072 auto tryToWidenViaDuplication = [&]() -> SDValue {
8073 if (!canWidenViaDuplication(Mask))
8075 SmallVector<int, 4> LoInputs;
8076 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8077 [](int M) { return M >= 0 && M < 8; });
8078 std::sort(LoInputs.begin(), LoInputs.end());
8079 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8081 SmallVector<int, 4> HiInputs;
8082 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8083 [](int M) { return M >= 8; });
8084 std::sort(HiInputs.begin(), HiInputs.end());
8085 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8088 bool TargetLo = LoInputs.size() >= HiInputs.size();
8089 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8090 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8092 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8093 SmallDenseMap<int, int, 8> LaneMap;
8094 for (int I : InPlaceInputs) {
8095 PreDupI16Shuffle[I/2] = I/2;
8098 int j = TargetLo ? 0 : 4, je = j + 4;
8099 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8100 // Check if j is already a shuffle of this input. This happens when
8101 // there are two adjacent bytes after we move the low one.
8102 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8103 // If we haven't yet mapped the input, search for a slot into which
8105 while (j < je && PreDupI16Shuffle[j] != -1)
8109 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8112 // Map this input with the i16 shuffle.
8113 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8116 // Update the lane map based on the mapping we ended up with.
8117 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8120 ISD::BITCAST, DL, MVT::v16i8,
8121 DAG.getVectorShuffle(MVT::v8i16, DL,
8122 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8123 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8125 // Unpack the bytes to form the i16s that will be shuffled into place.
8126 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8127 MVT::v16i8, V1, V1);
8129 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8130 for (int i = 0; i < 16; i += 2) {
8132 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8133 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
8136 ISD::BITCAST, DL, MVT::v16i8,
8137 DAG.getVectorShuffle(MVT::v8i16, DL,
8138 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8139 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8141 if (SDValue V = tryToWidenViaDuplication())
8145 // Check whether an interleaving lowering is likely to be more efficient.
8146 // This isn't perfect but it is a strong heuristic that tends to work well on
8147 // the kinds of shuffles that show up in practice.
8149 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
8150 if (shouldLowerAsInterleaving(Mask)) {
8151 // FIXME: Figure out whether we should pack these into the low or high
8154 int EMask[16], OMask[16];
8155 for (int i = 0; i < 8; ++i) {
8156 EMask[i] = Mask[2*i];
8157 OMask[i] = Mask[2*i + 1];
8162 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8163 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8165 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8168 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8169 // with PSHUFB. It is important to do this before we attempt to generate any
8170 // blends but after all of the single-input lowerings. If the single input
8171 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8172 // want to preserve that and we can DAG combine any longer sequences into
8173 // a PSHUFB in the end. But once we start blending from multiple inputs,
8174 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8175 // and there are *very* few patterns that would actually be faster than the
8176 // PSHUFB approach because of its ability to zero lanes.
8178 // FIXME: The only exceptions to the above are blends which are exact
8179 // interleavings with direct instructions supporting them. We currently don't
8180 // handle those well here.
8181 if (Subtarget->hasSSSE3()) {
8184 for (int i = 0; i < 16; ++i)
8185 if (Mask[i] == -1) {
8186 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8188 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8190 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8192 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8193 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8194 if (isSingleInputShuffleMask(Mask))
8195 return V1; // Single inputs are easy.
8197 // Otherwise, blend the two.
8198 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8199 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8200 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8203 // Check whether a compaction lowering can be done. This handles shuffles
8204 // which take every Nth element for some even N. See the helper function for
8207 // We special case these as they can be particularly efficiently handled with
8208 // the PACKUSB instruction on x86 and they show up in common patterns of
8209 // rearranging bytes to truncate wide elements.
8210 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8211 // NumEvenDrops is the power of two stride of the elements. Another way of
8212 // thinking about it is that we need to drop the even elements this many
8213 // times to get the original input.
8214 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8216 // First we need to zero all the dropped bytes.
8217 assert(NumEvenDrops <= 3 &&
8218 "No support for dropping even elements more than 3 times.");
8219 // We use the mask type to pick which bytes are preserved based on how many
8220 // elements are dropped.
8221 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8222 SDValue ByteClearMask =
8223 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8224 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8225 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8227 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8229 // Now pack things back together.
8230 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8231 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8232 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8233 for (int i = 1; i < NumEvenDrops; ++i) {
8234 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8235 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8241 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8242 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8243 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8244 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8246 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8247 MutableArrayRef<int> V1HalfBlendMask,
8248 MutableArrayRef<int> V2HalfBlendMask) {
8249 for (int i = 0; i < 8; ++i)
8250 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8251 V1HalfBlendMask[i] = HalfMask[i];
8253 } else if (HalfMask[i] >= 16) {
8254 V2HalfBlendMask[i] = HalfMask[i] - 16;
8255 HalfMask[i] = i + 8;
8258 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8259 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8261 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8263 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8264 MutableArrayRef<int> HiBlendMask) {
8266 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8267 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8269 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8270 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8271 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8272 [](int M) { return M >= 0 && M % 2 == 1; })) {
8273 // Use a mask to drop the high bytes.
8274 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8275 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8276 DAG.getConstant(0x00FF, MVT::v8i16));
8278 // This will be a single vector shuffle instead of a blend so nuke V2.
8279 V2 = DAG.getUNDEF(MVT::v8i16);
8281 // Squash the masks to point directly into V1.
8282 for (int &M : LoBlendMask)
8285 for (int &M : HiBlendMask)
8289 // Otherwise just unpack the low half of V into V1 and the high half into
8290 // V2 so that we can blend them as i16s.
8291 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8292 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8293 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8294 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8297 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8298 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8299 return std::make_pair(BlendedLo, BlendedHi);
8301 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8302 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8303 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8305 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8306 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8308 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8311 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8313 /// This routine breaks down the specific type of 128-bit shuffle and
8314 /// dispatches to the lowering routines accordingly.
8315 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8316 MVT VT, const X86Subtarget *Subtarget,
8317 SelectionDAG &DAG) {
8318 switch (VT.SimpleTy) {
8320 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8322 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8324 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8326 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8328 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8330 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8333 llvm_unreachable("Unimplemented!");
8337 static bool isHalfCrossingShuffleMask(ArrayRef<int> Mask) {
8338 int Size = Mask.size();
8339 for (int M : Mask.slice(0, Size / 2))
8340 if (M >= 0 && (M % Size) >= Size / 2)
8342 for (int M : Mask.slice(Size / 2, Size / 2))
8343 if (M >= 0 && (M % Size) < Size / 2)
8348 /// \brief Generic routine to split a 256-bit vector shuffle into 128-bit
8351 /// There is a severely limited set of shuffles available in AVX1 for 256-bit
8352 /// vectors resulting in routinely needing to split the shuffle into two 128-bit
8353 /// shuffles. This can be done generically for any 256-bit vector shuffle and so
8354 /// we encode the logic here for specific shuffle lowering routines to bail to
8355 /// when they exhaust the features avaible to more directly handle the shuffle.
8356 static SDValue splitAndLower256BitVectorShuffle(SDValue Op, SDValue V1,
8358 const X86Subtarget *Subtarget,
8359 SelectionDAG &DAG) {
8361 MVT VT = Op.getSimpleValueType();
8362 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
8363 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8364 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8366 ArrayRef<int> Mask = SVOp->getMask();
8368 ArrayRef<int> LoMask = Mask.slice(0, Mask.size()/2);
8369 ArrayRef<int> HiMask = Mask.slice(Mask.size()/2);
8371 int NumElements = VT.getVectorNumElements();
8372 int SplitNumElements = NumElements / 2;
8373 MVT ScalarVT = VT.getScalarType();
8374 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8376 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8377 DAG.getIntPtrConstant(0));
8378 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
8379 DAG.getIntPtrConstant(SplitNumElements));
8380 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8381 DAG.getIntPtrConstant(0));
8382 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
8383 DAG.getIntPtrConstant(SplitNumElements));
8385 // Now create two 4-way blends of these half-width vectors.
8386 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8387 SmallVector<int, 16> V1BlendMask, V2BlendMask, BlendMask;
8388 for (int i = 0; i < SplitNumElements; ++i) {
8389 int M = HalfMask[i];
8390 if (M >= NumElements) {
8391 V2BlendMask.push_back(M - NumElements);
8392 V1BlendMask.push_back(-1);
8393 BlendMask.push_back(SplitNumElements + i);
8394 } else if (M >= 0) {
8395 V2BlendMask.push_back(-1);
8396 V1BlendMask.push_back(M);
8397 BlendMask.push_back(i);
8399 V2BlendMask.push_back(-1);
8400 V1BlendMask.push_back(-1);
8401 BlendMask.push_back(-1);
8404 SDValue V1Blend = DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8405 SDValue V2Blend = DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8406 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
8408 SDValue Lo = HalfBlend(LoMask);
8409 SDValue Hi = HalfBlend(HiMask);
8410 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
8413 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
8415 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
8416 /// isn't available.
8417 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8418 const X86Subtarget *Subtarget,
8419 SelectionDAG &DAG) {
8421 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8422 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
8423 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8424 ArrayRef<int> Mask = SVOp->getMask();
8425 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8427 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8428 // shuffles aren't a problem and FP and int have the same patterns.
8430 // FIXME: We can handle these more cleverly than splitting for v4f64.
8431 if (isHalfCrossingShuffleMask(Mask))
8432 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8434 if (isSingleInputShuffleMask(Mask)) {
8435 // Non-half-crossing single input shuffles can be lowerid with an
8436 // interleaved permutation.
8437 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
8438 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
8439 return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f64, V1,
8440 DAG.getConstant(VPERMILPMask, MVT::i8));
8443 // Check if the blend happens to exactly fit that of SHUFPD.
8444 if (Mask[0] < 4 && (Mask[1] == -1 || Mask[1] >= 4) &&
8445 Mask[2] < 4 && (Mask[3] == -1 || Mask[3] >= 4)) {
8446 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
8447 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
8448 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
8449 DAG.getConstant(SHUFPDMask, MVT::i8));
8451 if ((Mask[0] == -1 || Mask[0] >= 4) && Mask[1] < 4 &&
8452 (Mask[2] == -1 || Mask[2] >= 4) && Mask[3] < 4) {
8453 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
8454 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
8455 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
8456 DAG.getConstant(SHUFPDMask, MVT::i8));
8459 // Shuffle the input elements into the desired positions in V1 and V2 and
8460 // blend them together.
8461 int V1Mask[] = {-1, -1, -1, -1};
8462 int V2Mask[] = {-1, -1, -1, -1};
8463 for (int i = 0; i < 4; ++i)
8464 if (Mask[i] >= 0 && Mask[i] < 4)
8465 V1Mask[i] = Mask[i];
8466 else if (Mask[i] >= 4)
8467 V2Mask[i] = Mask[i] - 4;
8469 V1 = DAG.getVectorShuffle(MVT::v4f64, DL, V1, DAG.getUNDEF(MVT::v4f64), V1Mask);
8470 V2 = DAG.getVectorShuffle(MVT::v4f64, DL, V2, DAG.getUNDEF(MVT::v4f64), V2Mask);
8472 unsigned BlendMask = 0;
8473 for (int i = 0; i < 4; ++i)
8475 BlendMask |= 1 << i;
8477 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v4f64, V1, V2,
8478 DAG.getConstant(BlendMask, MVT::i8));
8481 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
8483 /// Largely delegates to common code when we have AVX2 and to the floating-point
8484 /// code when we only have AVX.
8485 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8486 const X86Subtarget *Subtarget,
8487 SelectionDAG &DAG) {
8489 assert(Op.getSimpleValueType() == MVT::v4i64 && "Bad shuffle type!");
8490 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8491 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
8492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8493 ArrayRef<int> Mask = SVOp->getMask();
8494 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8496 // FIXME: If we have AVX2, we should delegate to generic code as crossing
8497 // shuffles aren't a problem and FP and int have the same patterns.
8499 if (isHalfCrossingShuffleMask(Mask))
8500 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8502 // AVX1 doesn't provide any facilities for v4i64 shuffles, bitcast and
8503 // delegate to floating point code.
8504 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V1);
8505 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f64, V2);
8506 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i64,
8507 lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG));
8510 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
8512 /// This routine either breaks down the specific type of a 256-bit x86 vector
8513 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
8514 /// together based on the available instructions.
8515 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8516 MVT VT, const X86Subtarget *Subtarget,
8517 SelectionDAG &DAG) {
8518 switch (VT.SimpleTy) {
8520 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8522 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8527 // Fall back to the basic pattern of extracting the high half and forming
8529 // FIXME: Add targeted lowering for each type that can document rationale
8530 // for delegating to this when necessary.
8531 return splitAndLower256BitVectorShuffle(Op, V1, V2, Subtarget, DAG);
8534 llvm_unreachable("Not a valid 256-bit x86 vector type!");
8538 /// \brief Tiny helper function to test whether a shuffle mask could be
8539 /// simplified by widening the elements being shuffled.
8540 static bool canWidenShuffleElements(ArrayRef<int> Mask) {
8541 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8542 if (Mask[i] % 2 != 0 || Mask[i] + 1 != Mask[i+1])
8548 /// \brief Top-level lowering for x86 vector shuffles.
8550 /// This handles decomposition, canonicalization, and lowering of all x86
8551 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8552 /// above in helper routines. The canonicalization attempts to widen shuffles
8553 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8554 /// s.t. only one of the two inputs needs to be tested, etc.
8555 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8556 SelectionDAG &DAG) {
8557 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8558 ArrayRef<int> Mask = SVOp->getMask();
8559 SDValue V1 = Op.getOperand(0);
8560 SDValue V2 = Op.getOperand(1);
8561 MVT VT = Op.getSimpleValueType();
8562 int NumElements = VT.getVectorNumElements();
8565 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8567 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8568 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8569 if (V1IsUndef && V2IsUndef)
8570 return DAG.getUNDEF(VT);
8572 // When we create a shuffle node we put the UNDEF node to second operand,
8573 // but in some cases the first operand may be transformed to UNDEF.
8574 // In this case we should just commute the node.
8576 return DAG.getCommutedVectorShuffle(*SVOp);
8578 // Check for non-undef masks pointing at an undef vector and make the masks
8579 // undef as well. This makes it easier to match the shuffle based solely on
8583 if (M >= NumElements) {
8584 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8585 for (int &M : NewMask)
8586 if (M >= NumElements)
8588 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8591 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8592 // lanes but wider integers. We cap this to not form integers larger than i64
8593 // but it might be interesting to form i128 integers to handle flipping the
8594 // low and high halves of AVX 256-bit vectors.
8595 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8596 canWidenShuffleElements(Mask)) {
8597 SmallVector<int, 8> NewMask;
8598 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8599 NewMask.push_back(Mask[i] / 2);
8601 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8602 VT.getVectorNumElements() / 2);
8603 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8604 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8605 return DAG.getNode(ISD::BITCAST, dl, VT,
8606 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8609 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8610 for (int M : SVOp->getMask())
8613 else if (M < NumElements)
8618 // Commute the shuffle as needed such that more elements come from V1 than
8619 // V2. This allows us to match the shuffle pattern strictly on how many
8620 // elements come from V1 without handling the symmetric cases.
8621 if (NumV2Elements > NumV1Elements)
8622 return DAG.getCommutedVectorShuffle(*SVOp);
8624 // When the number of V1 and V2 elements are the same, try to minimize the
8625 // number of uses of V2 in the low half of the vector.
8626 if (NumV1Elements == NumV2Elements) {
8627 int LowV1Elements = 0, LowV2Elements = 0;
8628 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8629 if (M >= NumElements)
8633 if (LowV2Elements > LowV1Elements)
8634 return DAG.getCommutedVectorShuffle(*SVOp);
8637 // For each vector width, delegate to a specialized lowering routine.
8638 if (VT.getSizeInBits() == 128)
8639 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8641 if (VT.getSizeInBits() == 256)
8642 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8644 llvm_unreachable("Unimplemented!");
8648 //===----------------------------------------------------------------------===//
8649 // Legacy vector shuffle lowering
8651 // This code is the legacy code handling vector shuffles until the above
8652 // replaces its functionality and performance.
8653 //===----------------------------------------------------------------------===//
8655 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8656 bool hasInt256, unsigned *MaskOut = nullptr) {
8657 MVT EltVT = VT.getVectorElementType();
8659 // There is no blend with immediate in AVX-512.
8660 if (VT.is512BitVector())
8663 if (!hasSSE41 || EltVT == MVT::i8)
8665 if (!hasInt256 && VT == MVT::v16i16)
8668 unsigned MaskValue = 0;
8669 unsigned NumElems = VT.getVectorNumElements();
8670 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8671 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8672 unsigned NumElemsInLane = NumElems / NumLanes;
8674 // Blend for v16i16 should be symetric for the both lanes.
8675 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8677 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8678 int EltIdx = MaskVals[i];
8680 if ((EltIdx < 0 || EltIdx == (int)i) &&
8681 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8684 if (((unsigned)EltIdx == (i + NumElems)) &&
8685 (SndLaneEltIdx < 0 ||
8686 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8687 MaskValue |= (1 << i);
8693 *MaskOut = MaskValue;
8697 // Try to lower a shuffle node into a simple blend instruction.
8698 // This function assumes isBlendMask returns true for this
8699 // SuffleVectorSDNode
8700 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8702 const X86Subtarget *Subtarget,
8703 SelectionDAG &DAG) {
8704 MVT VT = SVOp->getSimpleValueType(0);
8705 MVT EltVT = VT.getVectorElementType();
8706 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8707 Subtarget->hasInt256() && "Trying to lower a "
8708 "VECTOR_SHUFFLE to a Blend but "
8709 "with the wrong mask"));
8710 SDValue V1 = SVOp->getOperand(0);
8711 SDValue V2 = SVOp->getOperand(1);
8713 unsigned NumElems = VT.getVectorNumElements();
8715 // Convert i32 vectors to floating point if it is not AVX2.
8716 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8718 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8719 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8721 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8722 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8725 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8726 DAG.getConstant(MaskValue, MVT::i32));
8727 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8730 /// In vector type \p VT, return true if the element at index \p InputIdx
8731 /// falls on a different 128-bit lane than \p OutputIdx.
8732 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8733 unsigned OutputIdx) {
8734 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8735 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8738 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8739 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8740 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8741 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8743 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8744 SelectionDAG &DAG) {
8745 MVT VT = V1.getSimpleValueType();
8746 assert(VT.is128BitVector() || VT.is256BitVector());
8748 MVT EltVT = VT.getVectorElementType();
8749 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8750 unsigned NumElts = VT.getVectorNumElements();
8752 SmallVector<SDValue, 32> PshufbMask;
8753 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8754 int InputIdx = MaskVals[OutputIdx];
8755 unsigned InputByteIdx;
8757 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8758 InputByteIdx = 0x80;
8760 // Cross lane is not allowed.
8761 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8763 InputByteIdx = InputIdx * EltSizeInBytes;
8764 // Index is an byte offset within the 128-bit lane.
8765 InputByteIdx &= 0xf;
8768 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8769 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8770 if (InputByteIdx != 0x80)
8775 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8777 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8778 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8779 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8782 // v8i16 shuffles - Prefer shuffles in the following order:
8783 // 1. [all] pshuflw, pshufhw, optional move
8784 // 2. [ssse3] 1 x pshufb
8785 // 3. [ssse3] 2 x pshufb + 1 x por
8786 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8788 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8789 SelectionDAG &DAG) {
8790 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8791 SDValue V1 = SVOp->getOperand(0);
8792 SDValue V2 = SVOp->getOperand(1);
8794 SmallVector<int, 8> MaskVals;
8796 // Determine if more than 1 of the words in each of the low and high quadwords
8797 // of the result come from the same quadword of one of the two inputs. Undef
8798 // mask values count as coming from any quadword, for better codegen.
8800 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8801 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8802 unsigned LoQuad[] = { 0, 0, 0, 0 };
8803 unsigned HiQuad[] = { 0, 0, 0, 0 };
8804 // Indices of quads used.
8805 std::bitset<4> InputQuads;
8806 for (unsigned i = 0; i < 8; ++i) {
8807 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8808 int EltIdx = SVOp->getMaskElt(i);
8809 MaskVals.push_back(EltIdx);
8818 InputQuads.set(EltIdx / 4);
8821 int BestLoQuad = -1;
8822 unsigned MaxQuad = 1;
8823 for (unsigned i = 0; i < 4; ++i) {
8824 if (LoQuad[i] > MaxQuad) {
8826 MaxQuad = LoQuad[i];
8830 int BestHiQuad = -1;
8832 for (unsigned i = 0; i < 4; ++i) {
8833 if (HiQuad[i] > MaxQuad) {
8835 MaxQuad = HiQuad[i];
8839 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8840 // of the two input vectors, shuffle them into one input vector so only a
8841 // single pshufb instruction is necessary. If there are more than 2 input
8842 // quads, disable the next transformation since it does not help SSSE3.
8843 bool V1Used = InputQuads[0] || InputQuads[1];
8844 bool V2Used = InputQuads[2] || InputQuads[3];
8845 if (Subtarget->hasSSSE3()) {
8846 if (InputQuads.count() == 2 && V1Used && V2Used) {
8847 BestLoQuad = InputQuads[0] ? 0 : 1;
8848 BestHiQuad = InputQuads[2] ? 2 : 3;
8850 if (InputQuads.count() > 2) {
8856 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8857 // the shuffle mask. If a quad is scored as -1, that means that it contains
8858 // words from all 4 input quadwords.
8860 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8862 BestLoQuad < 0 ? 0 : BestLoQuad,
8863 BestHiQuad < 0 ? 1 : BestHiQuad
8865 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8866 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8867 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8868 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8870 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8871 // source words for the shuffle, to aid later transformations.
8872 bool AllWordsInNewV = true;
8873 bool InOrder[2] = { true, true };
8874 for (unsigned i = 0; i != 8; ++i) {
8875 int idx = MaskVals[i];
8877 InOrder[i/4] = false;
8878 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8880 AllWordsInNewV = false;
8884 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8885 if (AllWordsInNewV) {
8886 for (int i = 0; i != 8; ++i) {
8887 int idx = MaskVals[i];
8890 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8891 if ((idx != i) && idx < 4)
8893 if ((idx != i) && idx > 3)
8902 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8903 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8904 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8905 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8906 unsigned TargetMask = 0;
8907 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8908 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8909 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8910 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8911 getShufflePSHUFLWImmediate(SVOp);
8912 V1 = NewV.getOperand(0);
8913 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8917 // Promote splats to a larger type which usually leads to more efficient code.
8918 // FIXME: Is this true if pshufb is available?
8919 if (SVOp->isSplat())
8920 return PromoteSplat(SVOp, DAG);
8922 // If we have SSSE3, and all words of the result are from 1 input vector,
8923 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8924 // is present, fall back to case 4.
8925 if (Subtarget->hasSSSE3()) {
8926 SmallVector<SDValue,16> pshufbMask;
8928 // If we have elements from both input vectors, set the high bit of the
8929 // shuffle mask element to zero out elements that come from V2 in the V1
8930 // mask, and elements that come from V1 in the V2 mask, so that the two
8931 // results can be OR'd together.
8932 bool TwoInputs = V1Used && V2Used;
8933 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8935 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8937 // Calculate the shuffle mask for the second input, shuffle it, and
8938 // OR it with the first shuffled input.
8939 CommuteVectorShuffleMask(MaskVals, 8);
8940 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8941 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8942 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8945 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8946 // and update MaskVals with new element order.
8947 std::bitset<8> InOrder;
8948 if (BestLoQuad >= 0) {
8949 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8950 for (int i = 0; i != 4; ++i) {
8951 int idx = MaskVals[i];
8954 } else if ((idx / 4) == BestLoQuad) {
8959 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8962 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8963 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8964 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8966 getShufflePSHUFLWImmediate(SVOp), DAG);
8970 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8971 // and update MaskVals with the new element order.
8972 if (BestHiQuad >= 0) {
8973 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8974 for (unsigned i = 4; i != 8; ++i) {
8975 int idx = MaskVals[i];
8978 } else if ((idx / 4) == BestHiQuad) {
8979 MaskV[i] = (idx & 3) + 4;
8983 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8986 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8987 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8988 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8990 getShufflePSHUFHWImmediate(SVOp), DAG);
8994 // In case BestHi & BestLo were both -1, which means each quadword has a word
8995 // from each of the four input quadwords, calculate the InOrder bitvector now
8996 // before falling through to the insert/extract cleanup.
8997 if (BestLoQuad == -1 && BestHiQuad == -1) {
8999 for (int i = 0; i != 8; ++i)
9000 if (MaskVals[i] < 0 || MaskVals[i] == i)
9004 // The other elements are put in the right place using pextrw and pinsrw.
9005 for (unsigned i = 0; i != 8; ++i) {
9008 int EltIdx = MaskVals[i];
9011 SDValue ExtOp = (EltIdx < 8) ?
9012 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
9013 DAG.getIntPtrConstant(EltIdx)) :
9014 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
9015 DAG.getIntPtrConstant(EltIdx - 8));
9016 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
9017 DAG.getIntPtrConstant(i));
9022 /// \brief v16i16 shuffles
9024 /// FIXME: We only support generation of a single pshufb currently. We can
9025 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
9026 /// well (e.g 2 x pshufb + 1 x por).
9028 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
9029 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9030 SDValue V1 = SVOp->getOperand(0);
9031 SDValue V2 = SVOp->getOperand(1);
9034 if (V2.getOpcode() != ISD::UNDEF)
9037 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9038 return getPSHUFB(MaskVals, V1, dl, DAG);
9041 // v16i8 shuffles - Prefer shuffles in the following order:
9042 // 1. [ssse3] 1 x pshufb
9043 // 2. [ssse3] 2 x pshufb + 1 x por
9044 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
9045 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
9046 const X86Subtarget* Subtarget,
9047 SelectionDAG &DAG) {
9048 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9049 SDValue V1 = SVOp->getOperand(0);
9050 SDValue V2 = SVOp->getOperand(1);
9052 ArrayRef<int> MaskVals = SVOp->getMask();
9054 // Promote splats to a larger type which usually leads to more efficient code.
9055 // FIXME: Is this true if pshufb is available?
9056 if (SVOp->isSplat())
9057 return PromoteSplat(SVOp, DAG);
9059 // If we have SSSE3, case 1 is generated when all result bytes come from
9060 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
9061 // present, fall back to case 3.
9063 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
9064 if (Subtarget->hasSSSE3()) {
9065 SmallVector<SDValue,16> pshufbMask;
9067 // If all result elements are from one input vector, then only translate
9068 // undef mask values to 0x80 (zero out result) in the pshufb mask.
9070 // Otherwise, we have elements from both input vectors, and must zero out
9071 // elements that come from V2 in the first mask, and V1 in the second mask
9072 // so that we can OR them together.
9073 for (unsigned i = 0; i != 16; ++i) {
9074 int EltIdx = MaskVals[i];
9075 if (EltIdx < 0 || EltIdx >= 16)
9077 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9079 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
9080 DAG.getNode(ISD::BUILD_VECTOR, dl,
9081 MVT::v16i8, pshufbMask));
9083 // As PSHUFB will zero elements with negative indices, it's safe to ignore
9084 // the 2nd operand if it's undefined or zero.
9085 if (V2.getOpcode() == ISD::UNDEF ||
9086 ISD::isBuildVectorAllZeros(V2.getNode()))
9089 // Calculate the shuffle mask for the second input, shuffle it, and
9090 // OR it with the first shuffled input.
9092 for (unsigned i = 0; i != 16; ++i) {
9093 int EltIdx = MaskVals[i];
9094 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
9095 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
9097 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
9098 DAG.getNode(ISD::BUILD_VECTOR, dl,
9099 MVT::v16i8, pshufbMask));
9100 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
9103 // No SSSE3 - Calculate in place words and then fix all out of place words
9104 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
9105 // the 16 different words that comprise the two doublequadword input vectors.
9106 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
9107 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
9109 for (int i = 0; i != 8; ++i) {
9110 int Elt0 = MaskVals[i*2];
9111 int Elt1 = MaskVals[i*2+1];
9113 // This word of the result is all undef, skip it.
9114 if (Elt0 < 0 && Elt1 < 0)
9117 // This word of the result is already in the correct place, skip it.
9118 if ((Elt0 == i*2) && (Elt1 == i*2+1))
9121 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
9122 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
9125 // If Elt0 and Elt1 are defined, are consecutive, and can be load
9126 // using a single extract together, load it and store it.
9127 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
9128 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9129 DAG.getIntPtrConstant(Elt1 / 2));
9130 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9131 DAG.getIntPtrConstant(i));
9135 // If Elt1 is defined, extract it from the appropriate source. If the
9136 // source byte is not also odd, shift the extracted word left 8 bits
9137 // otherwise clear the bottom 8 bits if we need to do an or.
9139 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
9140 DAG.getIntPtrConstant(Elt1 / 2));
9141 if ((Elt1 & 1) == 0)
9142 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
9144 TLI.getShiftAmountTy(InsElt.getValueType())));
9146 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
9147 DAG.getConstant(0xFF00, MVT::i16));
9149 // If Elt0 is defined, extract it from the appropriate source. If the
9150 // source byte is not also even, shift the extracted word right 8 bits. If
9151 // Elt1 was also defined, OR the extracted values together before
9152 // inserting them in the result.
9154 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
9155 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
9156 if ((Elt0 & 1) != 0)
9157 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
9159 TLI.getShiftAmountTy(InsElt0.getValueType())));
9161 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
9162 DAG.getConstant(0x00FF, MVT::i16));
9163 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
9166 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
9167 DAG.getIntPtrConstant(i));
9169 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
9172 // v32i8 shuffles - Translate to VPSHUFB if possible.
9174 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
9175 const X86Subtarget *Subtarget,
9176 SelectionDAG &DAG) {
9177 MVT VT = SVOp->getSimpleValueType(0);
9178 SDValue V1 = SVOp->getOperand(0);
9179 SDValue V2 = SVOp->getOperand(1);
9181 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
9183 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9184 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
9185 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
9187 // VPSHUFB may be generated if
9188 // (1) one of input vector is undefined or zeroinitializer.
9189 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
9190 // And (2) the mask indexes don't cross the 128-bit lane.
9191 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
9192 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
9195 if (V1IsAllZero && !V2IsAllZero) {
9196 CommuteVectorShuffleMask(MaskVals, 32);
9199 return getPSHUFB(MaskVals, V1, dl, DAG);
9202 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
9203 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
9204 /// done when every pair / quad of shuffle mask elements point to elements in
9205 /// the right sequence. e.g.
9206 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
9208 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
9209 SelectionDAG &DAG) {
9210 MVT VT = SVOp->getSimpleValueType(0);
9212 unsigned NumElems = VT.getVectorNumElements();
9215 switch (VT.SimpleTy) {
9216 default: llvm_unreachable("Unexpected!");
9219 return SDValue(SVOp, 0);
9220 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
9221 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
9222 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
9223 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
9224 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
9225 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
9228 SmallVector<int, 8> MaskVec;
9229 for (unsigned i = 0; i != NumElems; i += Scale) {
9231 for (unsigned j = 0; j != Scale; ++j) {
9232 int EltIdx = SVOp->getMaskElt(i+j);
9236 StartIdx = (EltIdx / Scale);
9237 if (EltIdx != (int)(StartIdx*Scale + j))
9240 MaskVec.push_back(StartIdx);
9243 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
9244 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
9245 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
9248 /// getVZextMovL - Return a zero-extending vector move low node.
9250 static SDValue getVZextMovL(MVT VT, MVT OpVT,
9251 SDValue SrcOp, SelectionDAG &DAG,
9252 const X86Subtarget *Subtarget, SDLoc dl) {
9253 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
9254 LoadSDNode *LD = nullptr;
9255 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
9256 LD = dyn_cast<LoadSDNode>(SrcOp);
9258 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
9260 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
9261 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
9262 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
9263 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
9264 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
9266 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
9267 return DAG.getNode(ISD::BITCAST, dl, VT,
9268 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9269 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
9277 return DAG.getNode(ISD::BITCAST, dl, VT,
9278 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
9279 DAG.getNode(ISD::BITCAST, dl,
9283 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
9284 /// which could not be matched by any known target speficic shuffle
9286 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9288 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
9289 if (NewOp.getNode())
9292 MVT VT = SVOp->getSimpleValueType(0);
9294 unsigned NumElems = VT.getVectorNumElements();
9295 unsigned NumLaneElems = NumElems / 2;
9298 MVT EltVT = VT.getVectorElementType();
9299 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
9302 SmallVector<int, 16> Mask;
9303 for (unsigned l = 0; l < 2; ++l) {
9304 // Build a shuffle mask for the output, discovering on the fly which
9305 // input vectors to use as shuffle operands (recorded in InputUsed).
9306 // If building a suitable shuffle vector proves too hard, then bail
9307 // out with UseBuildVector set.
9308 bool UseBuildVector = false;
9309 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
9310 unsigned LaneStart = l * NumLaneElems;
9311 for (unsigned i = 0; i != NumLaneElems; ++i) {
9312 // The mask element. This indexes into the input.
9313 int Idx = SVOp->getMaskElt(i+LaneStart);
9315 // the mask element does not index into any input vector.
9320 // The input vector this mask element indexes into.
9321 int Input = Idx / NumLaneElems;
9323 // Turn the index into an offset from the start of the input vector.
9324 Idx -= Input * NumLaneElems;
9326 // Find or create a shuffle vector operand to hold this input.
9328 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
9329 if (InputUsed[OpNo] == Input)
9330 // This input vector is already an operand.
9332 if (InputUsed[OpNo] < 0) {
9333 // Create a new operand for this input vector.
9334 InputUsed[OpNo] = Input;
9339 if (OpNo >= array_lengthof(InputUsed)) {
9340 // More than two input vectors used! Give up on trying to create a
9341 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
9342 UseBuildVector = true;
9346 // Add the mask index for the new shuffle vector.
9347 Mask.push_back(Idx + OpNo * NumLaneElems);
9350 if (UseBuildVector) {
9351 SmallVector<SDValue, 16> SVOps;
9352 for (unsigned i = 0; i != NumLaneElems; ++i) {
9353 // The mask element. This indexes into the input.
9354 int Idx = SVOp->getMaskElt(i+LaneStart);
9356 SVOps.push_back(DAG.getUNDEF(EltVT));
9360 // The input vector this mask element indexes into.
9361 int Input = Idx / NumElems;
9363 // Turn the index into an offset from the start of the input vector.
9364 Idx -= Input * NumElems;
9366 // Extract the vector element by hand.
9367 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
9368 SVOp->getOperand(Input),
9369 DAG.getIntPtrConstant(Idx)));
9372 // Construct the output using a BUILD_VECTOR.
9373 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
9374 } else if (InputUsed[0] < 0) {
9375 // No input vectors were used! The result is undefined.
9376 Output[l] = DAG.getUNDEF(NVT);
9378 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
9379 (InputUsed[0] % 2) * NumLaneElems,
9381 // If only one input was used, use an undefined vector for the other.
9382 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
9383 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
9384 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
9385 // At least one input vector was used. Create a new shuffle vector.
9386 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9392 // Concatenate the result back
9393 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
9396 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9397 /// 4 elements, and match them with several different shuffle types.
9399 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9400 SDValue V1 = SVOp->getOperand(0);
9401 SDValue V2 = SVOp->getOperand(1);
9403 MVT VT = SVOp->getSimpleValueType(0);
9405 assert(VT.is128BitVector() && "Unsupported vector size");
9407 std::pair<int, int> Locs[4];
9408 int Mask1[] = { -1, -1, -1, -1 };
9409 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9413 for (unsigned i = 0; i != 4; ++i) {
9414 int Idx = PermMask[i];
9416 Locs[i] = std::make_pair(-1, -1);
9418 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9420 Locs[i] = std::make_pair(0, NumLo);
9424 Locs[i] = std::make_pair(1, NumHi);
9426 Mask1[2+NumHi] = Idx;
9432 if (NumLo <= 2 && NumHi <= 2) {
9433 // If no more than two elements come from either vector. This can be
9434 // implemented with two shuffles. First shuffle gather the elements.
9435 // The second shuffle, which takes the first shuffle as both of its
9436 // vector operands, put the elements into the right order.
9437 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9439 int Mask2[] = { -1, -1, -1, -1 };
9441 for (unsigned i = 0; i != 4; ++i)
9442 if (Locs[i].first != -1) {
9443 unsigned Idx = (i < 2) ? 0 : 4;
9444 Idx += Locs[i].first * 2 + Locs[i].second;
9448 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9451 if (NumLo == 3 || NumHi == 3) {
9452 // Otherwise, we must have three elements from one vector, call it X, and
9453 // one element from the other, call it Y. First, use a shufps to build an
9454 // intermediate vector with the one element from Y and the element from X
9455 // that will be in the same half in the final destination (the indexes don't
9456 // matter). Then, use a shufps to build the final vector, taking the half
9457 // containing the element from Y from the intermediate, and the other half
9460 // Normalize it so the 3 elements come from V1.
9461 CommuteVectorShuffleMask(PermMask, 4);
9465 // Find the element from V2.
9467 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9468 int Val = PermMask[HiIndex];
9475 Mask1[0] = PermMask[HiIndex];
9477 Mask1[2] = PermMask[HiIndex^1];
9479 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9482 Mask1[0] = PermMask[0];
9483 Mask1[1] = PermMask[1];
9484 Mask1[2] = HiIndex & 1 ? 6 : 4;
9485 Mask1[3] = HiIndex & 1 ? 4 : 6;
9486 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9489 Mask1[0] = HiIndex & 1 ? 2 : 0;
9490 Mask1[1] = HiIndex & 1 ? 0 : 2;
9491 Mask1[2] = PermMask[2];
9492 Mask1[3] = PermMask[3];
9497 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9500 // Break it into (shuffle shuffle_hi, shuffle_lo).
9501 int LoMask[] = { -1, -1, -1, -1 };
9502 int HiMask[] = { -1, -1, -1, -1 };
9504 int *MaskPtr = LoMask;
9505 unsigned MaskIdx = 0;
9508 for (unsigned i = 0; i != 4; ++i) {
9515 int Idx = PermMask[i];
9517 Locs[i] = std::make_pair(-1, -1);
9518 } else if (Idx < 4) {
9519 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9520 MaskPtr[LoIdx] = Idx;
9523 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9524 MaskPtr[HiIdx] = Idx;
9529 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9530 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9531 int MaskOps[] = { -1, -1, -1, -1 };
9532 for (unsigned i = 0; i != 4; ++i)
9533 if (Locs[i].first != -1)
9534 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9535 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9538 static bool MayFoldVectorLoad(SDValue V) {
9539 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9540 V = V.getOperand(0);
9542 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9543 V = V.getOperand(0);
9544 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9545 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9546 // BUILD_VECTOR (load), undef
9547 V = V.getOperand(0);
9549 return MayFoldLoad(V);
9553 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9554 MVT VT = Op.getSimpleValueType();
9556 // Canonizalize to v2f64.
9557 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9558 return DAG.getNode(ISD::BITCAST, dl, VT,
9559 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9564 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9566 SDValue V1 = Op.getOperand(0);
9567 SDValue V2 = Op.getOperand(1);
9568 MVT VT = Op.getSimpleValueType();
9570 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9572 if (HasSSE2 && VT == MVT::v2f64)
9573 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9575 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9576 return DAG.getNode(ISD::BITCAST, dl, VT,
9577 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9578 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9579 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9583 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9584 SDValue V1 = Op.getOperand(0);
9585 SDValue V2 = Op.getOperand(1);
9586 MVT VT = Op.getSimpleValueType();
9588 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9589 "unsupported shuffle type");
9591 if (V2.getOpcode() == ISD::UNDEF)
9595 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9599 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9600 SDValue V1 = Op.getOperand(0);
9601 SDValue V2 = Op.getOperand(1);
9602 MVT VT = Op.getSimpleValueType();
9603 unsigned NumElems = VT.getVectorNumElements();
9605 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9606 // operand of these instructions is only memory, so check if there's a
9607 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9609 bool CanFoldLoad = false;
9611 // Trivial case, when V2 comes from a load.
9612 if (MayFoldVectorLoad(V2))
9615 // When V1 is a load, it can be folded later into a store in isel, example:
9616 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9618 // (MOVLPSmr addr:$src1, VR128:$src2)
9619 // So, recognize this potential and also use MOVLPS or MOVLPD
9620 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9623 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9625 if (HasSSE2 && NumElems == 2)
9626 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9629 // If we don't care about the second element, proceed to use movss.
9630 if (SVOp->getMaskElt(1) != -1)
9631 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9634 // movl and movlp will both match v2i64, but v2i64 is never matched by
9635 // movl earlier because we make it strict to avoid messing with the movlp load
9636 // folding logic (see the code above getMOVLP call). Match it here then,
9637 // this is horrible, but will stay like this until we move all shuffle
9638 // matching to x86 specific nodes. Note that for the 1st condition all
9639 // types are matched with movsd.
9641 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9642 // as to remove this logic from here, as much as possible
9643 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9644 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9645 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9648 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9650 // Invert the operand order and use SHUFPS to match it.
9651 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9652 getShuffleSHUFImmediate(SVOp), DAG);
9655 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9656 SelectionDAG &DAG) {
9658 MVT VT = Load->getSimpleValueType(0);
9659 MVT EVT = VT.getVectorElementType();
9660 SDValue Addr = Load->getOperand(1);
9661 SDValue NewAddr = DAG.getNode(
9662 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9663 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9666 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9667 DAG.getMachineFunction().getMachineMemOperand(
9668 Load->getMemOperand(), 0, EVT.getStoreSize()));
9672 // It is only safe to call this function if isINSERTPSMask is true for
9673 // this shufflevector mask.
9674 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9675 SelectionDAG &DAG) {
9676 // Generate an insertps instruction when inserting an f32 from memory onto a
9677 // v4f32 or when copying a member from one v4f32 to another.
9678 // We also use it for transferring i32 from one register to another,
9679 // since it simply copies the same bits.
9680 // If we're transferring an i32 from memory to a specific element in a
9681 // register, we output a generic DAG that will match the PINSRD
9683 MVT VT = SVOp->getSimpleValueType(0);
9684 MVT EVT = VT.getVectorElementType();
9685 SDValue V1 = SVOp->getOperand(0);
9686 SDValue V2 = SVOp->getOperand(1);
9687 auto Mask = SVOp->getMask();
9688 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9689 "unsupported vector type for insertps/pinsrd");
9691 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9692 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9693 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9701 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9704 // If we have 1 element from each vector, we have to check if we're
9705 // changing V1's element's place. If so, we're done. Otherwise, we
9706 // should assume we're changing V2's element's place and behave
9708 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9709 assert(DestIndex <= INT32_MAX && "truncated destination index");
9710 if (FromV1 == FromV2 &&
9711 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
9715 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9718 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9719 "More than one element from V1 and from V2, or no elements from one "
9720 "of the vectors. This case should not have returned true from "
9725 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9728 // Get an index into the source vector in the range [0,4) (the mask is
9729 // in the range [0,8) because it can address V1 and V2)
9730 unsigned SrcIndex = Mask[DestIndex] % 4;
9731 if (MayFoldLoad(From)) {
9732 // Trivial case, when From comes from a load and is only used by the
9733 // shuffle. Make it use insertps from the vector that we need from that
9736 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9737 if (!NewLoad.getNode())
9740 if (EVT == MVT::f32) {
9741 // Create this as a scalar to vector to match the instruction pattern.
9742 SDValue LoadScalarToVector =
9743 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9744 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9745 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9747 } else { // EVT == MVT::i32
9748 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9749 // instruction, to match the PINSRD instruction, which loads an i32 to a
9750 // certain vector element.
9751 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9752 DAG.getConstant(DestIndex, MVT::i32));
9756 // Vector-element-to-vector
9757 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9758 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9761 // Reduce a vector shuffle to zext.
9762 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9763 SelectionDAG &DAG) {
9764 // PMOVZX is only available from SSE41.
9765 if (!Subtarget->hasSSE41())
9768 MVT VT = Op.getSimpleValueType();
9770 // Only AVX2 support 256-bit vector integer extending.
9771 if (!Subtarget->hasInt256() && VT.is256BitVector())
9774 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9776 SDValue V1 = Op.getOperand(0);
9777 SDValue V2 = Op.getOperand(1);
9778 unsigned NumElems = VT.getVectorNumElements();
9780 // Extending is an unary operation and the element type of the source vector
9781 // won't be equal to or larger than i64.
9782 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9783 VT.getVectorElementType() == MVT::i64)
9786 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9787 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9788 while ((1U << Shift) < NumElems) {
9789 if (SVOp->getMaskElt(1U << Shift) == 1)
9792 // The maximal ratio is 8, i.e. from i8 to i64.
9797 // Check the shuffle mask.
9798 unsigned Mask = (1U << Shift) - 1;
9799 for (unsigned i = 0; i != NumElems; ++i) {
9800 int EltIdx = SVOp->getMaskElt(i);
9801 if ((i & Mask) != 0 && EltIdx != -1)
9803 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9807 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9808 MVT NeVT = MVT::getIntegerVT(NBits);
9809 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9811 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9814 // Simplify the operand as it's prepared to be fed into shuffle.
9815 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9816 if (V1.getOpcode() == ISD::BITCAST &&
9817 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9818 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9819 V1.getOperand(0).getOperand(0)
9820 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9821 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9822 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9823 ConstantSDNode *CIdx =
9824 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9825 // If it's foldable, i.e. normal load with single use, we will let code
9826 // selection to fold it. Otherwise, we will short the conversion sequence.
9827 if (CIdx && CIdx->getZExtValue() == 0 &&
9828 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9829 MVT FullVT = V.getSimpleValueType();
9830 MVT V1VT = V1.getSimpleValueType();
9831 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9832 // The "ext_vec_elt" node is wider than the result node.
9833 // In this case we should extract subvector from V.
9834 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9835 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9836 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9837 FullVT.getVectorNumElements()/Ratio);
9838 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9839 DAG.getIntPtrConstant(0));
9841 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9845 return DAG.getNode(ISD::BITCAST, DL, VT,
9846 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9849 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9850 SelectionDAG &DAG) {
9851 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9852 MVT VT = Op.getSimpleValueType();
9854 SDValue V1 = Op.getOperand(0);
9855 SDValue V2 = Op.getOperand(1);
9857 if (isZeroShuffle(SVOp))
9858 return getZeroVector(VT, Subtarget, DAG, dl);
9860 // Handle splat operations
9861 if (SVOp->isSplat()) {
9862 // Use vbroadcast whenever the splat comes from a foldable load
9863 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9864 if (Broadcast.getNode())
9868 // Check integer expanding shuffles.
9869 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9870 if (NewOp.getNode())
9873 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9875 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9877 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9878 if (NewOp.getNode())
9879 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9880 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9881 // FIXME: Figure out a cleaner way to do this.
9882 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9883 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9884 if (NewOp.getNode()) {
9885 MVT NewVT = NewOp.getSimpleValueType();
9886 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9887 NewVT, true, false))
9888 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9891 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9892 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9893 if (NewOp.getNode()) {
9894 MVT NewVT = NewOp.getSimpleValueType();
9895 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9896 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9905 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9906 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9907 SDValue V1 = Op.getOperand(0);
9908 SDValue V2 = Op.getOperand(1);
9909 MVT VT = Op.getSimpleValueType();
9911 unsigned NumElems = VT.getVectorNumElements();
9912 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9913 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9914 bool V1IsSplat = false;
9915 bool V2IsSplat = false;
9916 bool HasSSE2 = Subtarget->hasSSE2();
9917 bool HasFp256 = Subtarget->hasFp256();
9918 bool HasInt256 = Subtarget->hasInt256();
9919 MachineFunction &MF = DAG.getMachineFunction();
9920 bool OptForSize = MF.getFunction()->getAttributes().
9921 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9923 // Check if we should use the experimental vector shuffle lowering. If so,
9924 // delegate completely to that code path.
9925 if (ExperimentalVectorShuffleLowering)
9926 return lowerVectorShuffle(Op, Subtarget, DAG);
9928 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9930 if (V1IsUndef && V2IsUndef)
9931 return DAG.getUNDEF(VT);
9933 // When we create a shuffle node we put the UNDEF node to second operand,
9934 // but in some cases the first operand may be transformed to UNDEF.
9935 // In this case we should just commute the node.
9937 return DAG.getCommutedVectorShuffle(*SVOp);
9939 // Vector shuffle lowering takes 3 steps:
9941 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9942 // narrowing and commutation of operands should be handled.
9943 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9945 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9946 // so the shuffle can be broken into other shuffles and the legalizer can
9947 // try the lowering again.
9949 // The general idea is that no vector_shuffle operation should be left to
9950 // be matched during isel, all of them must be converted to a target specific
9953 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9954 // narrowing and commutation of operands should be handled. The actual code
9955 // doesn't include all of those, work in progress...
9956 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9957 if (NewOp.getNode())
9960 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9962 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9963 // unpckh_undef). Only use pshufd if speed is more important than size.
9964 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9965 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9966 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9967 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9969 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9970 V2IsUndef && MayFoldVectorLoad(V1))
9971 return getMOVDDup(Op, dl, V1, DAG);
9973 if (isMOVHLPS_v_undef_Mask(M, VT))
9974 return getMOVHighToLow(Op, dl, DAG);
9976 // Use to match splats
9977 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9978 (VT == MVT::v2f64 || VT == MVT::v2i64))
9979 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9981 if (isPSHUFDMask(M, VT)) {
9982 // The actual implementation will match the mask in the if above and then
9983 // during isel it can match several different instructions, not only pshufd
9984 // as its name says, sad but true, emulate the behavior for now...
9985 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9986 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9988 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9990 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9991 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9993 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9994 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9997 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
10001 if (isPALIGNRMask(M, VT, Subtarget))
10002 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
10003 getShufflePALIGNRImmediate(SVOp),
10006 if (isVALIGNMask(M, VT, Subtarget))
10007 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
10008 getShuffleVALIGNImmediate(SVOp),
10011 // Check if this can be converted into a logical shift.
10012 bool isLeft = false;
10013 unsigned ShAmt = 0;
10015 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
10016 if (isShift && ShVal.hasOneUse()) {
10017 // If the shifted value has multiple uses, it may be cheaper to use
10018 // v_set0 + movlhps or movhlps, etc.
10019 MVT EltVT = VT.getVectorElementType();
10020 ShAmt *= EltVT.getSizeInBits();
10021 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10024 if (isMOVLMask(M, VT)) {
10025 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10026 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
10027 if (!isMOVLPMask(M, VT)) {
10028 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
10029 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
10031 if (VT == MVT::v4i32 || VT == MVT::v4f32)
10032 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
10036 // FIXME: fold these into legal mask.
10037 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
10038 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
10040 if (isMOVHLPSMask(M, VT))
10041 return getMOVHighToLow(Op, dl, DAG);
10043 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
10044 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
10046 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
10047 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
10049 if (isMOVLPMask(M, VT))
10050 return getMOVLP(Op, dl, DAG, HasSSE2);
10052 if (ShouldXformToMOVHLPS(M, VT) ||
10053 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
10054 return DAG.getCommutedVectorShuffle(*SVOp);
10057 // No better options. Use a vshldq / vsrldq.
10058 MVT EltVT = VT.getVectorElementType();
10059 ShAmt *= EltVT.getSizeInBits();
10060 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
10063 bool Commuted = false;
10064 // FIXME: This should also accept a bitcast of a splat? Be careful, not
10065 // 1,1,1,1 -> v8i16 though.
10066 BitVector UndefElements;
10067 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
10068 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10070 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
10071 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
10074 // Canonicalize the splat or undef, if present, to be on the RHS.
10075 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
10076 CommuteVectorShuffleMask(M, NumElems);
10078 std::swap(V1IsSplat, V2IsSplat);
10082 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
10083 // Shuffling low element of v1 into undef, just return v1.
10086 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
10087 // the instruction selector will not match, so get a canonical MOVL with
10088 // swapped operands to undo the commute.
10089 return getMOVL(DAG, dl, VT, V2, V1);
10092 if (isUNPCKLMask(M, VT, HasInt256))
10093 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10095 if (isUNPCKHMask(M, VT, HasInt256))
10096 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10099 // Normalize mask so all entries that point to V2 points to its first
10100 // element then try to match unpck{h|l} again. If match, return a
10101 // new vector_shuffle with the corrected mask.p
10102 SmallVector<int, 8> NewMask(M.begin(), M.end());
10103 NormalizeMask(NewMask, NumElems);
10104 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
10105 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10106 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
10107 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10111 // Commute is back and try unpck* again.
10112 // FIXME: this seems wrong.
10113 CommuteVectorShuffleMask(M, NumElems);
10115 std::swap(V1IsSplat, V2IsSplat);
10117 if (isUNPCKLMask(M, VT, HasInt256))
10118 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
10120 if (isUNPCKHMask(M, VT, HasInt256))
10121 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
10124 // Normalize the node to match x86 shuffle ops if needed
10125 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
10126 return DAG.getCommutedVectorShuffle(*SVOp);
10128 // The checks below are all present in isShuffleMaskLegal, but they are
10129 // inlined here right now to enable us to directly emit target specific
10130 // nodes, and remove one by one until they don't return Op anymore.
10132 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
10133 SVOp->getSplatIndex() == 0 && V2IsUndef) {
10134 if (VT == MVT::v2f64 || VT == MVT::v2i64)
10135 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10138 if (isPSHUFHWMask(M, VT, HasInt256))
10139 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
10140 getShufflePSHUFHWImmediate(SVOp),
10143 if (isPSHUFLWMask(M, VT, HasInt256))
10144 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
10145 getShufflePSHUFLWImmediate(SVOp),
10148 unsigned MaskValue;
10149 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
10151 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
10153 if (isSHUFPMask(M, VT))
10154 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
10155 getShuffleSHUFImmediate(SVOp), DAG);
10157 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
10158 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
10159 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
10160 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
10162 //===--------------------------------------------------------------------===//
10163 // Generate target specific nodes for 128 or 256-bit shuffles only
10164 // supported in the AVX instruction set.
10167 // Handle VMOVDDUPY permutations
10168 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
10169 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
10171 // Handle VPERMILPS/D* permutations
10172 if (isVPERMILPMask(M, VT)) {
10173 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
10174 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
10175 getShuffleSHUFImmediate(SVOp), DAG);
10176 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
10177 getShuffleSHUFImmediate(SVOp), DAG);
10181 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
10182 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
10183 Idx*(NumElems/2), DAG, dl);
10185 // Handle VPERM2F128/VPERM2I128 permutations
10186 if (isVPERM2X128Mask(M, VT, HasFp256))
10187 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
10188 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
10190 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
10191 return getINSERTPS(SVOp, dl, DAG);
10194 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
10195 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
10197 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
10198 VT.is512BitVector()) {
10199 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
10200 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
10201 SmallVector<SDValue, 16> permclMask;
10202 for (unsigned i = 0; i != NumElems; ++i) {
10203 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
10206 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
10208 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
10209 return DAG.getNode(X86ISD::VPERMV, dl, VT,
10210 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
10211 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
10212 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
10215 //===--------------------------------------------------------------------===//
10216 // Since no target specific shuffle was selected for this generic one,
10217 // lower it into other known shuffles. FIXME: this isn't true yet, but
10218 // this is the plan.
10221 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
10222 if (VT == MVT::v8i16) {
10223 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
10224 if (NewOp.getNode())
10228 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
10229 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
10230 if (NewOp.getNode())
10234 if (VT == MVT::v16i8) {
10235 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
10236 if (NewOp.getNode())
10240 if (VT == MVT::v32i8) {
10241 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
10242 if (NewOp.getNode())
10246 // Handle all 128-bit wide vectors with 4 elements, and match them with
10247 // several different shuffle types.
10248 if (NumElems == 4 && VT.is128BitVector())
10249 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
10251 // Handle general 256-bit shuffles
10252 if (VT.is256BitVector())
10253 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
10258 // This function assumes its argument is a BUILD_VECTOR of constants or
10259 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10261 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10262 unsigned &MaskValue) {
10264 unsigned NumElems = BuildVector->getNumOperands();
10265 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10266 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10267 unsigned NumElemsInLane = NumElems / NumLanes;
10269 // Blend for v16i16 should be symetric for the both lanes.
10270 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10271 SDValue EltCond = BuildVector->getOperand(i);
10272 SDValue SndLaneEltCond =
10273 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10275 int Lane1Cond = -1, Lane2Cond = -1;
10276 if (isa<ConstantSDNode>(EltCond))
10277 Lane1Cond = !isZero(EltCond);
10278 if (isa<ConstantSDNode>(SndLaneEltCond))
10279 Lane2Cond = !isZero(SndLaneEltCond);
10281 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10282 // Lane1Cond != 0, means we want the first argument.
10283 // Lane1Cond == 0, means we want the second argument.
10284 // The encoding of this argument is 0 for the first argument, 1
10285 // for the second. Therefore, invert the condition.
10286 MaskValue |= !Lane1Cond << i;
10287 else if (Lane1Cond < 0)
10288 MaskValue |= !Lane2Cond << i;
10295 // Try to lower a vselect node into a simple blend instruction.
10296 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
10297 SelectionDAG &DAG) {
10298 SDValue Cond = Op.getOperand(0);
10299 SDValue LHS = Op.getOperand(1);
10300 SDValue RHS = Op.getOperand(2);
10302 MVT VT = Op.getSimpleValueType();
10303 MVT EltVT = VT.getVectorElementType();
10304 unsigned NumElems = VT.getVectorNumElements();
10306 // There is no blend with immediate in AVX-512.
10307 if (VT.is512BitVector())
10310 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
10312 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
10315 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10318 // Check the mask for BLEND and build the value.
10319 unsigned MaskValue = 0;
10320 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
10323 // Convert i32 vectors to floating point if it is not AVX2.
10324 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10326 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10327 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10329 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
10330 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
10333 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
10334 DAG.getConstant(MaskValue, MVT::i32));
10335 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10338 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10339 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
10340 if (BlendOp.getNode())
10343 // Some types for vselect were previously set to Expand, not Legal or
10344 // Custom. Return an empty SDValue so we fall-through to Expand, after
10345 // the Custom lowering phase.
10346 MVT VT = Op.getSimpleValueType();
10347 switch (VT.SimpleTy) {
10355 // We couldn't create a "Blend with immediate" node.
10356 // This node should still be legal, but we'll have to emit a blendv*
10361 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10362 MVT VT = Op.getSimpleValueType();
10365 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10368 if (VT.getSizeInBits() == 8) {
10369 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10370 Op.getOperand(0), Op.getOperand(1));
10371 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10372 DAG.getValueType(VT));
10373 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10376 if (VT.getSizeInBits() == 16) {
10377 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10378 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10380 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10381 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10382 DAG.getNode(ISD::BITCAST, dl,
10385 Op.getOperand(1)));
10386 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10387 Op.getOperand(0), Op.getOperand(1));
10388 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10389 DAG.getValueType(VT));
10390 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10393 if (VT == MVT::f32) {
10394 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10395 // the result back to FR32 register. It's only worth matching if the
10396 // result has a single use which is a store or a bitcast to i32. And in
10397 // the case of a store, it's not worth it if the index is a constant 0,
10398 // because a MOVSSmr can be used instead, which is smaller and faster.
10399 if (!Op.hasOneUse())
10401 SDNode *User = *Op.getNode()->use_begin();
10402 if ((User->getOpcode() != ISD::STORE ||
10403 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10404 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10405 (User->getOpcode() != ISD::BITCAST ||
10406 User->getValueType(0) != MVT::i32))
10408 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10409 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10412 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10415 if (VT == MVT::i32 || VT == MVT::i64) {
10416 // ExtractPS/pextrq works with constant index.
10417 if (isa<ConstantSDNode>(Op.getOperand(1)))
10423 /// Extract one bit from mask vector, like v16i1 or v8i1.
10424 /// AVX-512 feature.
10426 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10427 SDValue Vec = Op.getOperand(0);
10429 MVT VecVT = Vec.getSimpleValueType();
10430 SDValue Idx = Op.getOperand(1);
10431 MVT EltVT = Op.getSimpleValueType();
10433 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10435 // variable index can't be handled in mask registers,
10436 // extend vector to VR512
10437 if (!isa<ConstantSDNode>(Idx)) {
10438 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10439 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10440 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10441 ExtVT.getVectorElementType(), Ext, Idx);
10442 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10445 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10446 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10447 unsigned MaxSift = rc->getSize()*8 - 1;
10448 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10449 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10450 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10451 DAG.getConstant(MaxSift, MVT::i8));
10452 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10453 DAG.getIntPtrConstant(0));
10457 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10458 SelectionDAG &DAG) const {
10460 SDValue Vec = Op.getOperand(0);
10461 MVT VecVT = Vec.getSimpleValueType();
10462 SDValue Idx = Op.getOperand(1);
10464 if (Op.getSimpleValueType() == MVT::i1)
10465 return ExtractBitFromMaskVector(Op, DAG);
10467 if (!isa<ConstantSDNode>(Idx)) {
10468 if (VecVT.is512BitVector() ||
10469 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10470 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10473 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10474 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10475 MaskEltVT.getSizeInBits());
10477 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10478 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10479 getZeroVector(MaskVT, Subtarget, DAG, dl),
10480 Idx, DAG.getConstant(0, getPointerTy()));
10481 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10482 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10483 Perm, DAG.getConstant(0, getPointerTy()));
10488 // If this is a 256-bit vector result, first extract the 128-bit vector and
10489 // then extract the element from the 128-bit vector.
10490 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10492 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10493 // Get the 128-bit vector.
10494 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10495 MVT EltVT = VecVT.getVectorElementType();
10497 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10499 //if (IdxVal >= NumElems/2)
10500 // IdxVal -= NumElems/2;
10501 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10502 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10503 DAG.getConstant(IdxVal, MVT::i32));
10506 assert(VecVT.is128BitVector() && "Unexpected vector length");
10508 if (Subtarget->hasSSE41()) {
10509 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10514 MVT VT = Op.getSimpleValueType();
10515 // TODO: handle v16i8.
10516 if (VT.getSizeInBits() == 16) {
10517 SDValue Vec = Op.getOperand(0);
10518 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10520 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10521 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10522 DAG.getNode(ISD::BITCAST, dl,
10524 Op.getOperand(1)));
10525 // Transform it so it match pextrw which produces a 32-bit result.
10526 MVT EltVT = MVT::i32;
10527 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10528 Op.getOperand(0), Op.getOperand(1));
10529 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10530 DAG.getValueType(VT));
10531 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10534 if (VT.getSizeInBits() == 32) {
10535 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10539 // SHUFPS the element to the lowest double word, then movss.
10540 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10541 MVT VVT = Op.getOperand(0).getSimpleValueType();
10542 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10543 DAG.getUNDEF(VVT), Mask);
10544 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10545 DAG.getIntPtrConstant(0));
10548 if (VT.getSizeInBits() == 64) {
10549 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10550 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10551 // to match extract_elt for f64.
10552 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10556 // UNPCKHPD the element to the lowest double word, then movsd.
10557 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10558 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10559 int Mask[2] = { 1, -1 };
10560 MVT VVT = Op.getOperand(0).getSimpleValueType();
10561 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10562 DAG.getUNDEF(VVT), Mask);
10563 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10564 DAG.getIntPtrConstant(0));
10570 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10571 MVT VT = Op.getSimpleValueType();
10572 MVT EltVT = VT.getVectorElementType();
10575 SDValue N0 = Op.getOperand(0);
10576 SDValue N1 = Op.getOperand(1);
10577 SDValue N2 = Op.getOperand(2);
10579 if (!VT.is128BitVector())
10582 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
10583 isa<ConstantSDNode>(N2)) {
10585 if (VT == MVT::v8i16)
10586 Opc = X86ISD::PINSRW;
10587 else if (VT == MVT::v16i8)
10588 Opc = X86ISD::PINSRB;
10590 Opc = X86ISD::PINSRB;
10592 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10594 if (N1.getValueType() != MVT::i32)
10595 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10596 if (N2.getValueType() != MVT::i32)
10597 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10598 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10601 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
10602 // Bits [7:6] of the constant are the source select. This will always be
10603 // zero here. The DAG Combiner may combine an extract_elt index into these
10604 // bits. For example (insert (extract, 3), 2) could be matched by putting
10605 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10606 // Bits [5:4] of the constant are the destination select. This is the
10607 // value of the incoming immediate.
10608 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10609 // combine either bitwise AND or insert of float 0.0 to set these bits.
10610 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
10611 // Create this as a scalar to vector..
10612 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10613 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10616 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
10617 // PINSR* works with constant index.
10623 /// Insert one bit to mask vector, like v16i1 or v8i1.
10624 /// AVX-512 feature.
10626 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10628 SDValue Vec = Op.getOperand(0);
10629 SDValue Elt = Op.getOperand(1);
10630 SDValue Idx = Op.getOperand(2);
10631 MVT VecVT = Vec.getSimpleValueType();
10633 if (!isa<ConstantSDNode>(Idx)) {
10634 // Non constant index. Extend source and destination,
10635 // insert element and then truncate the result.
10636 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10637 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10638 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10639 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10640 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10641 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10644 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10645 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10646 if (Vec.getOpcode() == ISD::UNDEF)
10647 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10648 DAG.getConstant(IdxVal, MVT::i8));
10649 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10650 unsigned MaxSift = rc->getSize()*8 - 1;
10651 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10652 DAG.getConstant(MaxSift, MVT::i8));
10653 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10654 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10655 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10658 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
10659 MVT VT = Op.getSimpleValueType();
10660 MVT EltVT = VT.getVectorElementType();
10662 if (EltVT == MVT::i1)
10663 return InsertBitToMaskVector(Op, DAG);
10666 SDValue N0 = Op.getOperand(0);
10667 SDValue N1 = Op.getOperand(1);
10668 SDValue N2 = Op.getOperand(2);
10670 // If this is a 256-bit vector result, first extract the 128-bit vector,
10671 // insert the element into the extracted half and then place it back.
10672 if (VT.is256BitVector() || VT.is512BitVector()) {
10673 if (!isa<ConstantSDNode>(N2))
10676 // Get the desired 128-bit vector half.
10677 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10678 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10680 // Insert the element into the desired half.
10681 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10682 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10684 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10685 DAG.getConstant(IdxIn128, MVT::i32));
10687 // Insert the changed part back to the 256-bit vector
10688 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10691 if (Subtarget->hasSSE41())
10692 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10694 if (EltVT == MVT::i8)
10697 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10698 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10699 // as its second argument.
10700 if (N1.getValueType() != MVT::i32)
10701 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10702 if (N2.getValueType() != MVT::i32)
10703 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10704 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10709 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10711 MVT OpVT = Op.getSimpleValueType();
10713 // If this is a 256-bit vector result, first insert into a 128-bit
10714 // vector and then insert into the 256-bit vector.
10715 if (!OpVT.is128BitVector()) {
10716 // Insert into a 128-bit vector.
10717 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10718 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10719 OpVT.getVectorNumElements() / SizeFactor);
10721 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10723 // Insert the 128-bit vector.
10724 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10727 if (OpVT == MVT::v1i64 &&
10728 Op.getOperand(0).getValueType() == MVT::i64)
10729 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10731 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10732 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10733 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10734 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10737 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10738 // a simple subregister reference or explicit instructions to grab
10739 // upper bits of a vector.
10740 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10741 SelectionDAG &DAG) {
10743 SDValue In = Op.getOperand(0);
10744 SDValue Idx = Op.getOperand(1);
10745 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10746 MVT ResVT = Op.getSimpleValueType();
10747 MVT InVT = In.getSimpleValueType();
10749 if (Subtarget->hasFp256()) {
10750 if (ResVT.is128BitVector() &&
10751 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10752 isa<ConstantSDNode>(Idx)) {
10753 return Extract128BitVector(In, IdxVal, DAG, dl);
10755 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10756 isa<ConstantSDNode>(Idx)) {
10757 return Extract256BitVector(In, IdxVal, DAG, dl);
10763 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10764 // simple superregister reference or explicit instructions to insert
10765 // the upper bits of a vector.
10766 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10767 SelectionDAG &DAG) {
10768 if (Subtarget->hasFp256()) {
10769 SDLoc dl(Op.getNode());
10770 SDValue Vec = Op.getNode()->getOperand(0);
10771 SDValue SubVec = Op.getNode()->getOperand(1);
10772 SDValue Idx = Op.getNode()->getOperand(2);
10774 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10775 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10776 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10777 isa<ConstantSDNode>(Idx)) {
10778 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10779 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10782 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10783 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10784 isa<ConstantSDNode>(Idx)) {
10785 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10786 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10792 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10793 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10794 // one of the above mentioned nodes. It has to be wrapped because otherwise
10795 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10796 // be used to form addressing mode. These wrapped nodes will be selected
10799 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10800 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10802 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10803 // global base reg.
10804 unsigned char OpFlag = 0;
10805 unsigned WrapperKind = X86ISD::Wrapper;
10806 CodeModel::Model M = DAG.getTarget().getCodeModel();
10808 if (Subtarget->isPICStyleRIPRel() &&
10809 (M == CodeModel::Small || M == CodeModel::Kernel))
10810 WrapperKind = X86ISD::WrapperRIP;
10811 else if (Subtarget->isPICStyleGOT())
10812 OpFlag = X86II::MO_GOTOFF;
10813 else if (Subtarget->isPICStyleStubPIC())
10814 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10816 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10817 CP->getAlignment(),
10818 CP->getOffset(), OpFlag);
10820 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10821 // With PIC, the address is actually $g + Offset.
10823 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10824 DAG.getNode(X86ISD::GlobalBaseReg,
10825 SDLoc(), getPointerTy()),
10832 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10833 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10835 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10836 // global base reg.
10837 unsigned char OpFlag = 0;
10838 unsigned WrapperKind = X86ISD::Wrapper;
10839 CodeModel::Model M = DAG.getTarget().getCodeModel();
10841 if (Subtarget->isPICStyleRIPRel() &&
10842 (M == CodeModel::Small || M == CodeModel::Kernel))
10843 WrapperKind = X86ISD::WrapperRIP;
10844 else if (Subtarget->isPICStyleGOT())
10845 OpFlag = X86II::MO_GOTOFF;
10846 else if (Subtarget->isPICStyleStubPIC())
10847 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10849 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10852 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10854 // With PIC, the address is actually $g + Offset.
10856 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10857 DAG.getNode(X86ISD::GlobalBaseReg,
10858 SDLoc(), getPointerTy()),
10865 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10866 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10868 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10869 // global base reg.
10870 unsigned char OpFlag = 0;
10871 unsigned WrapperKind = X86ISD::Wrapper;
10872 CodeModel::Model M = DAG.getTarget().getCodeModel();
10874 if (Subtarget->isPICStyleRIPRel() &&
10875 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10876 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10877 OpFlag = X86II::MO_GOTPCREL;
10878 WrapperKind = X86ISD::WrapperRIP;
10879 } else if (Subtarget->isPICStyleGOT()) {
10880 OpFlag = X86II::MO_GOT;
10881 } else if (Subtarget->isPICStyleStubPIC()) {
10882 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10883 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10884 OpFlag = X86II::MO_DARWIN_NONLAZY;
10887 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10890 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10892 // With PIC, the address is actually $g + Offset.
10893 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10894 !Subtarget->is64Bit()) {
10895 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10896 DAG.getNode(X86ISD::GlobalBaseReg,
10897 SDLoc(), getPointerTy()),
10901 // For symbols that require a load from a stub to get the address, emit the
10903 if (isGlobalStubReference(OpFlag))
10904 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10905 MachinePointerInfo::getGOT(), false, false, false, 0);
10911 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10912 // Create the TargetBlockAddressAddress node.
10913 unsigned char OpFlags =
10914 Subtarget->ClassifyBlockAddressReference();
10915 CodeModel::Model M = DAG.getTarget().getCodeModel();
10916 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10917 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10919 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10922 if (Subtarget->isPICStyleRIPRel() &&
10923 (M == CodeModel::Small || M == CodeModel::Kernel))
10924 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10926 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10928 // With PIC, the address is actually $g + Offset.
10929 if (isGlobalRelativeToPICBase(OpFlags)) {
10930 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10931 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10939 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10940 int64_t Offset, SelectionDAG &DAG) const {
10941 // Create the TargetGlobalAddress node, folding in the constant
10942 // offset if it is legal.
10943 unsigned char OpFlags =
10944 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10945 CodeModel::Model M = DAG.getTarget().getCodeModel();
10947 if (OpFlags == X86II::MO_NO_FLAG &&
10948 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10949 // A direct static reference to a global.
10950 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10953 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10956 if (Subtarget->isPICStyleRIPRel() &&
10957 (M == CodeModel::Small || M == CodeModel::Kernel))
10958 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10960 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10962 // With PIC, the address is actually $g + Offset.
10963 if (isGlobalRelativeToPICBase(OpFlags)) {
10964 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10965 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10969 // For globals that require a load from a stub to get the address, emit the
10971 if (isGlobalStubReference(OpFlags))
10972 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10973 MachinePointerInfo::getGOT(), false, false, false, 0);
10975 // If there was a non-zero offset that we didn't fold, create an explicit
10976 // addition for it.
10978 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10979 DAG.getConstant(Offset, getPointerTy()));
10985 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10986 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10987 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10988 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10992 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10993 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10994 unsigned char OperandFlags, bool LocalDynamic = false) {
10995 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10996 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10998 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10999 GA->getValueType(0),
11003 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11007 SDValue Ops[] = { Chain, TGA, *InFlag };
11008 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11010 SDValue Ops[] = { Chain, TGA };
11011 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11014 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11015 MFI->setAdjustsStack(true);
11017 SDValue Flag = Chain.getValue(1);
11018 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11021 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11023 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11026 SDLoc dl(GA); // ? function entry point might be better
11027 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11028 DAG.getNode(X86ISD::GlobalBaseReg,
11029 SDLoc(), PtrVT), InFlag);
11030 InFlag = Chain.getValue(1);
11032 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11035 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11037 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11039 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11040 X86::RAX, X86II::MO_TLSGD);
11043 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11049 // Get the start address of the TLS block for this module.
11050 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11051 .getInfo<X86MachineFunctionInfo>();
11052 MFI->incNumLocalDynamicTLSAccesses();
11056 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11057 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11060 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11061 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11062 InFlag = Chain.getValue(1);
11063 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11064 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11067 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11071 unsigned char OperandFlags = X86II::MO_DTPOFF;
11072 unsigned WrapperKind = X86ISD::Wrapper;
11073 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11074 GA->getValueType(0),
11075 GA->getOffset(), OperandFlags);
11076 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11078 // Add x@dtpoff with the base.
11079 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11082 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11083 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11084 const EVT PtrVT, TLSModel::Model model,
11085 bool is64Bit, bool isPIC) {
11088 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11089 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11090 is64Bit ? 257 : 256));
11092 SDValue ThreadPointer =
11093 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11094 MachinePointerInfo(Ptr), false, false, false, 0);
11096 unsigned char OperandFlags = 0;
11097 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11099 unsigned WrapperKind = X86ISD::Wrapper;
11100 if (model == TLSModel::LocalExec) {
11101 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11102 } else if (model == TLSModel::InitialExec) {
11104 OperandFlags = X86II::MO_GOTTPOFF;
11105 WrapperKind = X86ISD::WrapperRIP;
11107 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11110 llvm_unreachable("Unexpected model");
11113 // emit "addl x@ntpoff,%eax" (local exec)
11114 // or "addl x@indntpoff,%eax" (initial exec)
11115 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11117 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11118 GA->getOffset(), OperandFlags);
11119 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11121 if (model == TLSModel::InitialExec) {
11122 if (isPIC && !is64Bit) {
11123 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11124 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11128 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11129 MachinePointerInfo::getGOT(), false, false, false, 0);
11132 // The address of the thread local variable is the add of the thread
11133 // pointer with the offset of the variable.
11134 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11138 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11140 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11141 const GlobalValue *GV = GA->getGlobal();
11143 if (Subtarget->isTargetELF()) {
11144 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11147 case TLSModel::GeneralDynamic:
11148 if (Subtarget->is64Bit())
11149 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11150 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11151 case TLSModel::LocalDynamic:
11152 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11153 Subtarget->is64Bit());
11154 case TLSModel::InitialExec:
11155 case TLSModel::LocalExec:
11156 return LowerToTLSExecModel(
11157 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11158 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11160 llvm_unreachable("Unknown TLS model.");
11163 if (Subtarget->isTargetDarwin()) {
11164 // Darwin only has one model of TLS. Lower to that.
11165 unsigned char OpFlag = 0;
11166 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11167 X86ISD::WrapperRIP : X86ISD::Wrapper;
11169 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11170 // global base reg.
11171 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11172 !Subtarget->is64Bit();
11174 OpFlag = X86II::MO_TLVP_PIC_BASE;
11176 OpFlag = X86II::MO_TLVP;
11178 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11179 GA->getValueType(0),
11180 GA->getOffset(), OpFlag);
11181 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11183 // With PIC32, the address is actually $g + Offset.
11185 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11186 DAG.getNode(X86ISD::GlobalBaseReg,
11187 SDLoc(), getPointerTy()),
11190 // Lowering the machine isd will make sure everything is in the right
11192 SDValue Chain = DAG.getEntryNode();
11193 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11194 SDValue Args[] = { Chain, Offset };
11195 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11197 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11198 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11199 MFI->setAdjustsStack(true);
11201 // And our return value (tls address) is in the standard call return value
11203 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11204 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11205 Chain.getValue(1));
11208 if (Subtarget->isTargetKnownWindowsMSVC() ||
11209 Subtarget->isTargetWindowsGNU()) {
11210 // Just use the implicit TLS architecture
11211 // Need to generate someting similar to:
11212 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11214 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11215 // mov rcx, qword [rdx+rcx*8]
11216 // mov eax, .tls$:tlsvar
11217 // [rax+rcx] contains the address
11218 // Windows 64bit: gs:0x58
11219 // Windows 32bit: fs:__tls_array
11222 SDValue Chain = DAG.getEntryNode();
11224 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11225 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11226 // use its literal value of 0x2C.
11227 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11228 ? Type::getInt8PtrTy(*DAG.getContext(),
11230 : Type::getInt32PtrTy(*DAG.getContext(),
11234 Subtarget->is64Bit()
11235 ? DAG.getIntPtrConstant(0x58)
11236 : (Subtarget->isTargetWindowsGNU()
11237 ? DAG.getIntPtrConstant(0x2C)
11238 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11240 SDValue ThreadPointer =
11241 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11242 MachinePointerInfo(Ptr), false, false, false, 0);
11244 // Load the _tls_index variable
11245 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11246 if (Subtarget->is64Bit())
11247 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11248 IDX, MachinePointerInfo(), MVT::i32,
11249 false, false, false, 0);
11251 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11252 false, false, false, 0);
11254 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11256 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11258 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11259 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11260 false, false, false, 0);
11262 // Get the offset of start of .tls section
11263 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11264 GA->getValueType(0),
11265 GA->getOffset(), X86II::MO_SECREL);
11266 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11268 // The address of the thread local variable is the add of the thread
11269 // pointer with the offset of the variable.
11270 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11273 llvm_unreachable("TLS not implemented for this target.");
11276 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11277 /// and take a 2 x i32 value to shift plus a shift amount.
11278 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11279 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11280 MVT VT = Op.getSimpleValueType();
11281 unsigned VTBits = VT.getSizeInBits();
11283 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11284 SDValue ShOpLo = Op.getOperand(0);
11285 SDValue ShOpHi = Op.getOperand(1);
11286 SDValue ShAmt = Op.getOperand(2);
11287 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11288 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11290 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11291 DAG.getConstant(VTBits - 1, MVT::i8));
11292 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11293 DAG.getConstant(VTBits - 1, MVT::i8))
11294 : DAG.getConstant(0, VT);
11296 SDValue Tmp2, Tmp3;
11297 if (Op.getOpcode() == ISD::SHL_PARTS) {
11298 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11299 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11301 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11302 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11305 // If the shift amount is larger or equal than the width of a part we can't
11306 // rely on the results of shld/shrd. Insert a test and select the appropriate
11307 // values for large shift amounts.
11308 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11309 DAG.getConstant(VTBits, MVT::i8));
11310 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11311 AndNode, DAG.getConstant(0, MVT::i8));
11314 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11315 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11316 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11318 if (Op.getOpcode() == ISD::SHL_PARTS) {
11319 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11320 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11322 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11323 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11326 SDValue Ops[2] = { Lo, Hi };
11327 return DAG.getMergeValues(Ops, dl);
11330 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11331 SelectionDAG &DAG) const {
11332 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11334 if (SrcVT.isVector())
11337 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11338 "Unknown SINT_TO_FP to lower!");
11340 // These are really Legal; return the operand so the caller accepts it as
11342 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11344 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11345 Subtarget->is64Bit()) {
11350 unsigned Size = SrcVT.getSizeInBits()/8;
11351 MachineFunction &MF = DAG.getMachineFunction();
11352 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11353 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11354 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11356 MachinePointerInfo::getFixedStack(SSFI),
11358 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11361 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11363 SelectionDAG &DAG) const {
11367 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11369 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11371 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11373 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11375 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11376 MachineMemOperand *MMO;
11378 int SSFI = FI->getIndex();
11380 DAG.getMachineFunction()
11381 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11382 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11384 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11385 StackSlot = StackSlot.getOperand(1);
11387 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11388 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11390 Tys, Ops, SrcVT, MMO);
11393 Chain = Result.getValue(1);
11394 SDValue InFlag = Result.getValue(2);
11396 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11397 // shouldn't be necessary except that RFP cannot be live across
11398 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11399 MachineFunction &MF = DAG.getMachineFunction();
11400 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11401 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11402 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11403 Tys = DAG.getVTList(MVT::Other);
11405 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11407 MachineMemOperand *MMO =
11408 DAG.getMachineFunction()
11409 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11410 MachineMemOperand::MOStore, SSFISize, SSFISize);
11412 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11413 Ops, Op.getValueType(), MMO);
11414 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11415 MachinePointerInfo::getFixedStack(SSFI),
11416 false, false, false, 0);
11422 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11423 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11424 SelectionDAG &DAG) const {
11425 // This algorithm is not obvious. Here it is what we're trying to output:
11428 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11429 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11431 haddpd %xmm0, %xmm0
11433 pshufd $0x4e, %xmm0, %xmm1
11439 LLVMContext *Context = DAG.getContext();
11441 // Build some magic constants.
11442 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11443 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11444 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11446 SmallVector<Constant*,2> CV1;
11448 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11449 APInt(64, 0x4330000000000000ULL))));
11451 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11452 APInt(64, 0x4530000000000000ULL))));
11453 Constant *C1 = ConstantVector::get(CV1);
11454 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11456 // Load the 64-bit value into an XMM register.
11457 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11459 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11460 MachinePointerInfo::getConstantPool(),
11461 false, false, false, 16);
11462 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11463 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11466 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11467 MachinePointerInfo::getConstantPool(),
11468 false, false, false, 16);
11469 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11470 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11473 if (Subtarget->hasSSE3()) {
11474 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11475 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11477 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11478 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11480 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11481 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11485 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11486 DAG.getIntPtrConstant(0));
11489 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11490 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11491 SelectionDAG &DAG) const {
11493 // FP constant to bias correct the final result.
11494 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11497 // Load the 32-bit value into an XMM register.
11498 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11501 // Zero out the upper parts of the register.
11502 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11504 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11505 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11506 DAG.getIntPtrConstant(0));
11508 // Or the load with the bias.
11509 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11510 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11511 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11512 MVT::v2f64, Load)),
11513 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11514 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11515 MVT::v2f64, Bias)));
11516 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11517 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11518 DAG.getIntPtrConstant(0));
11520 // Subtract the bias.
11521 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11523 // Handle final rounding.
11524 EVT DestVT = Op.getValueType();
11526 if (DestVT.bitsLT(MVT::f64))
11527 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11528 DAG.getIntPtrConstant(0));
11529 if (DestVT.bitsGT(MVT::f64))
11530 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11532 // Handle final rounding.
11536 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11537 SelectionDAG &DAG) const {
11538 SDValue N0 = Op.getOperand(0);
11539 MVT SVT = N0.getSimpleValueType();
11542 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11543 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11544 "Custom UINT_TO_FP is not supported!");
11546 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11547 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11548 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11551 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11552 SelectionDAG &DAG) const {
11553 SDValue N0 = Op.getOperand(0);
11556 if (Op.getValueType().isVector())
11557 return lowerUINT_TO_FP_vec(Op, DAG);
11559 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11560 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11561 // the optimization here.
11562 if (DAG.SignBitIsZero(N0))
11563 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11565 MVT SrcVT = N0.getSimpleValueType();
11566 MVT DstVT = Op.getSimpleValueType();
11567 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11568 return LowerUINT_TO_FP_i64(Op, DAG);
11569 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11570 return LowerUINT_TO_FP_i32(Op, DAG);
11571 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11574 // Make a 64-bit buffer, and use it to build an FILD.
11575 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11576 if (SrcVT == MVT::i32) {
11577 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11578 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11579 getPointerTy(), StackSlot, WordOff);
11580 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11581 StackSlot, MachinePointerInfo(),
11583 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11584 OffsetSlot, MachinePointerInfo(),
11586 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11590 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11591 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11592 StackSlot, MachinePointerInfo(),
11594 // For i64 source, we need to add the appropriate power of 2 if the input
11595 // was negative. This is the same as the optimization in
11596 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11597 // we must be careful to do the computation in x87 extended precision, not
11598 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11599 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11600 MachineMemOperand *MMO =
11601 DAG.getMachineFunction()
11602 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11603 MachineMemOperand::MOLoad, 8, 8);
11605 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11606 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11607 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11610 APInt FF(32, 0x5F800000ULL);
11612 // Check whether the sign bit is set.
11613 SDValue SignSet = DAG.getSetCC(dl,
11614 getSetCCResultType(*DAG.getContext(), MVT::i64),
11615 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11618 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11619 SDValue FudgePtr = DAG.getConstantPool(
11620 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11623 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11624 SDValue Zero = DAG.getIntPtrConstant(0);
11625 SDValue Four = DAG.getIntPtrConstant(4);
11626 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11628 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11630 // Load the value out, extending it from f32 to f80.
11631 // FIXME: Avoid the extend by constructing the right constant pool?
11632 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11633 FudgePtr, MachinePointerInfo::getConstantPool(),
11634 MVT::f32, false, false, false, 4);
11635 // Extend everything to 80 bits to force it to be done on x87.
11636 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11637 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11640 std::pair<SDValue,SDValue>
11641 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11642 bool IsSigned, bool IsReplace) const {
11645 EVT DstTy = Op.getValueType();
11647 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11648 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11652 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11653 DstTy.getSimpleVT() >= MVT::i16 &&
11654 "Unknown FP_TO_INT to lower!");
11656 // These are really Legal.
11657 if (DstTy == MVT::i32 &&
11658 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11659 return std::make_pair(SDValue(), SDValue());
11660 if (Subtarget->is64Bit() &&
11661 DstTy == MVT::i64 &&
11662 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11663 return std::make_pair(SDValue(), SDValue());
11665 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11666 // stack slot, or into the FTOL runtime function.
11667 MachineFunction &MF = DAG.getMachineFunction();
11668 unsigned MemSize = DstTy.getSizeInBits()/8;
11669 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11670 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11673 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11674 Opc = X86ISD::WIN_FTOL;
11676 switch (DstTy.getSimpleVT().SimpleTy) {
11677 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11678 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11679 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11680 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11683 SDValue Chain = DAG.getEntryNode();
11684 SDValue Value = Op.getOperand(0);
11685 EVT TheVT = Op.getOperand(0).getValueType();
11686 // FIXME This causes a redundant load/store if the SSE-class value is already
11687 // in memory, such as if it is on the callstack.
11688 if (isScalarFPTypeInSSEReg(TheVT)) {
11689 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11690 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11691 MachinePointerInfo::getFixedStack(SSFI),
11693 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11695 Chain, StackSlot, DAG.getValueType(TheVT)
11698 MachineMemOperand *MMO =
11699 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11700 MachineMemOperand::MOLoad, MemSize, MemSize);
11701 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11702 Chain = Value.getValue(1);
11703 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11704 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11707 MachineMemOperand *MMO =
11708 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11709 MachineMemOperand::MOStore, MemSize, MemSize);
11711 if (Opc != X86ISD::WIN_FTOL) {
11712 // Build the FP_TO_INT*_IN_MEM
11713 SDValue Ops[] = { Chain, Value, StackSlot };
11714 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11716 return std::make_pair(FIST, StackSlot);
11718 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11719 DAG.getVTList(MVT::Other, MVT::Glue),
11721 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11722 MVT::i32, ftol.getValue(1));
11723 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11724 MVT::i32, eax.getValue(2));
11725 SDValue Ops[] = { eax, edx };
11726 SDValue pair = IsReplace
11727 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11728 : DAG.getMergeValues(Ops, DL);
11729 return std::make_pair(pair, SDValue());
11733 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11734 const X86Subtarget *Subtarget) {
11735 MVT VT = Op->getSimpleValueType(0);
11736 SDValue In = Op->getOperand(0);
11737 MVT InVT = In.getSimpleValueType();
11740 // Optimize vectors in AVX mode:
11743 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11744 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11745 // Concat upper and lower parts.
11748 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11749 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11750 // Concat upper and lower parts.
11753 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11754 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11755 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11758 if (Subtarget->hasInt256())
11759 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11761 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11762 SDValue Undef = DAG.getUNDEF(InVT);
11763 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11764 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11765 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11767 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11768 VT.getVectorNumElements()/2);
11770 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11771 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11773 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11776 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11777 SelectionDAG &DAG) {
11778 MVT VT = Op->getSimpleValueType(0);
11779 SDValue In = Op->getOperand(0);
11780 MVT InVT = In.getSimpleValueType();
11782 unsigned int NumElts = VT.getVectorNumElements();
11783 if (NumElts != 8 && NumElts != 16)
11786 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11787 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11789 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11790 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11791 // Now we have only mask extension
11792 assert(InVT.getVectorElementType() == MVT::i1);
11793 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11794 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11795 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11796 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11797 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11798 MachinePointerInfo::getConstantPool(),
11799 false, false, false, Alignment);
11801 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11802 if (VT.is512BitVector())
11804 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11807 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11808 SelectionDAG &DAG) {
11809 if (Subtarget->hasFp256()) {
11810 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11818 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11819 SelectionDAG &DAG) {
11821 MVT VT = Op.getSimpleValueType();
11822 SDValue In = Op.getOperand(0);
11823 MVT SVT = In.getSimpleValueType();
11825 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11826 return LowerZERO_EXTEND_AVX512(Op, DAG);
11828 if (Subtarget->hasFp256()) {
11829 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11834 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11835 VT.getVectorNumElements() != SVT.getVectorNumElements());
11839 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11841 MVT VT = Op.getSimpleValueType();
11842 SDValue In = Op.getOperand(0);
11843 MVT InVT = In.getSimpleValueType();
11845 if (VT == MVT::i1) {
11846 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11847 "Invalid scalar TRUNCATE operation");
11848 if (InVT == MVT::i32)
11850 if (InVT.getSizeInBits() == 64)
11851 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11852 else if (InVT.getSizeInBits() < 32)
11853 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11854 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11856 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11857 "Invalid TRUNCATE operation");
11859 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11860 if (VT.getVectorElementType().getSizeInBits() >=8)
11861 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11863 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11864 unsigned NumElts = InVT.getVectorNumElements();
11865 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11866 if (InVT.getSizeInBits() < 512) {
11867 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11868 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11872 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11873 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11874 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11875 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11876 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11877 MachinePointerInfo::getConstantPool(),
11878 false, false, false, Alignment);
11879 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11880 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11881 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11884 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11885 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11886 if (Subtarget->hasInt256()) {
11887 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11888 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11889 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11891 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11892 DAG.getIntPtrConstant(0));
11895 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11896 DAG.getIntPtrConstant(0));
11897 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11898 DAG.getIntPtrConstant(2));
11899 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11900 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11901 static const int ShufMask[] = {0, 2, 4, 6};
11902 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11905 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11906 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11907 if (Subtarget->hasInt256()) {
11908 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11910 SmallVector<SDValue,32> pshufbMask;
11911 for (unsigned i = 0; i < 2; ++i) {
11912 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11913 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11914 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11915 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11916 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11917 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11918 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11919 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11920 for (unsigned j = 0; j < 8; ++j)
11921 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11923 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11924 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11925 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11927 static const int ShufMask[] = {0, 2, -1, -1};
11928 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11930 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11931 DAG.getIntPtrConstant(0));
11932 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11935 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11936 DAG.getIntPtrConstant(0));
11938 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11939 DAG.getIntPtrConstant(4));
11941 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11942 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11944 // The PSHUFB mask:
11945 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11946 -1, -1, -1, -1, -1, -1, -1, -1};
11948 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11949 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11950 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11952 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11953 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11955 // The MOVLHPS Mask:
11956 static const int ShufMask2[] = {0, 1, 4, 5};
11957 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11958 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11961 // Handle truncation of V256 to V128 using shuffles.
11962 if (!VT.is128BitVector() || !InVT.is256BitVector())
11965 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11967 unsigned NumElems = VT.getVectorNumElements();
11968 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11970 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11971 // Prepare truncation shuffle mask
11972 for (unsigned i = 0; i != NumElems; ++i)
11973 MaskVec[i] = i * 2;
11974 SDValue V = DAG.getVectorShuffle(NVT, DL,
11975 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11976 DAG.getUNDEF(NVT), &MaskVec[0]);
11977 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11978 DAG.getIntPtrConstant(0));
11981 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11982 SelectionDAG &DAG) const {
11983 assert(!Op.getSimpleValueType().isVector());
11985 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11986 /*IsSigned=*/ true, /*IsReplace=*/ false);
11987 SDValue FIST = Vals.first, StackSlot = Vals.second;
11988 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11989 if (!FIST.getNode()) return Op;
11991 if (StackSlot.getNode())
11992 // Load the result.
11993 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11994 FIST, StackSlot, MachinePointerInfo(),
11995 false, false, false, 0);
11997 // The node is the result.
12001 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12002 SelectionDAG &DAG) const {
12003 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12004 /*IsSigned=*/ false, /*IsReplace=*/ false);
12005 SDValue FIST = Vals.first, StackSlot = Vals.second;
12006 assert(FIST.getNode() && "Unexpected failure");
12008 if (StackSlot.getNode())
12009 // Load the result.
12010 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12011 FIST, StackSlot, MachinePointerInfo(),
12012 false, false, false, 0);
12014 // The node is the result.
12018 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12020 MVT VT = Op.getSimpleValueType();
12021 SDValue In = Op.getOperand(0);
12022 MVT SVT = In.getSimpleValueType();
12024 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12026 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12027 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12028 In, DAG.getUNDEF(SVT)));
12031 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
12032 LLVMContext *Context = DAG.getContext();
12034 MVT VT = Op.getSimpleValueType();
12036 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12037 if (VT.isVector()) {
12038 EltVT = VT.getVectorElementType();
12039 NumElts = VT.getVectorNumElements();
12042 if (EltVT == MVT::f64)
12043 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12044 APInt(64, ~(1ULL << 63))));
12046 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
12047 APInt(32, ~(1U << 31))));
12048 C = ConstantVector::getSplat(NumElts, C);
12049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12050 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12051 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12052 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12053 MachinePointerInfo::getConstantPool(),
12054 false, false, false, Alignment);
12055 if (VT.isVector()) {
12056 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12057 return DAG.getNode(ISD::BITCAST, dl, VT,
12058 DAG.getNode(ISD::AND, dl, ANDVT,
12059 DAG.getNode(ISD::BITCAST, dl, ANDVT,
12061 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
12063 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
12066 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
12067 LLVMContext *Context = DAG.getContext();
12069 MVT VT = Op.getSimpleValueType();
12071 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12072 if (VT.isVector()) {
12073 EltVT = VT.getVectorElementType();
12074 NumElts = VT.getVectorNumElements();
12077 if (EltVT == MVT::f64)
12078 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12079 APInt(64, 1ULL << 63)));
12081 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
12082 APInt(32, 1U << 31)));
12083 C = ConstantVector::getSplat(NumElts, C);
12084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12085 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12086 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12087 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12088 MachinePointerInfo::getConstantPool(),
12089 false, false, false, Alignment);
12090 if (VT.isVector()) {
12091 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
12092 return DAG.getNode(ISD::BITCAST, dl, VT,
12093 DAG.getNode(ISD::XOR, dl, XORVT,
12094 DAG.getNode(ISD::BITCAST, dl, XORVT,
12096 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
12099 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
12102 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12104 LLVMContext *Context = DAG.getContext();
12105 SDValue Op0 = Op.getOperand(0);
12106 SDValue Op1 = Op.getOperand(1);
12108 MVT VT = Op.getSimpleValueType();
12109 MVT SrcVT = Op1.getSimpleValueType();
12111 // If second operand is smaller, extend it first.
12112 if (SrcVT.bitsLT(VT)) {
12113 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12116 // And if it is bigger, shrink it first.
12117 if (SrcVT.bitsGT(VT)) {
12118 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12122 // At this point the operands and the result should have the same
12123 // type, and that won't be f80 since that is not custom lowered.
12125 // First get the sign bit of second operand.
12126 SmallVector<Constant*,4> CV;
12127 if (SrcVT == MVT::f64) {
12128 const fltSemantics &Sem = APFloat::IEEEdouble;
12129 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
12130 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12132 const fltSemantics &Sem = APFloat::IEEEsingle;
12133 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
12134 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12135 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12136 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12138 Constant *C = ConstantVector::get(CV);
12139 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12140 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12141 MachinePointerInfo::getConstantPool(),
12142 false, false, false, 16);
12143 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12145 // Shift sign bit right or left if the two operands have different types.
12146 if (SrcVT.bitsGT(VT)) {
12147 // Op0 is MVT::f32, Op1 is MVT::f64.
12148 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
12149 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
12150 DAG.getConstant(32, MVT::i32));
12151 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
12152 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
12153 DAG.getIntPtrConstant(0));
12156 // Clear first operand sign bit.
12158 if (VT == MVT::f64) {
12159 const fltSemantics &Sem = APFloat::IEEEdouble;
12160 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12161 APInt(64, ~(1ULL << 63)))));
12162 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
12164 const fltSemantics &Sem = APFloat::IEEEsingle;
12165 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
12166 APInt(32, ~(1U << 31)))));
12167 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12168 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12169 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
12171 C = ConstantVector::get(CV);
12172 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12173 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12174 MachinePointerInfo::getConstantPool(),
12175 false, false, false, 16);
12176 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
12178 // Or the value with the sign bit.
12179 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12182 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12183 SDValue N0 = Op.getOperand(0);
12185 MVT VT = Op.getSimpleValueType();
12187 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12188 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12189 DAG.getConstant(1, VT));
12190 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12193 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
12195 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12196 SelectionDAG &DAG) {
12197 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12199 if (!Subtarget->hasSSE41())
12202 if (!Op->hasOneUse())
12205 SDNode *N = Op.getNode();
12208 SmallVector<SDValue, 8> Opnds;
12209 DenseMap<SDValue, unsigned> VecInMap;
12210 SmallVector<SDValue, 8> VecIns;
12211 EVT VT = MVT::Other;
12213 // Recognize a special case where a vector is casted into wide integer to
12215 Opnds.push_back(N->getOperand(0));
12216 Opnds.push_back(N->getOperand(1));
12218 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12219 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12220 // BFS traverse all OR'd operands.
12221 if (I->getOpcode() == ISD::OR) {
12222 Opnds.push_back(I->getOperand(0));
12223 Opnds.push_back(I->getOperand(1));
12224 // Re-evaluate the number of nodes to be traversed.
12225 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12229 // Quit if a non-EXTRACT_VECTOR_ELT
12230 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12233 // Quit if without a constant index.
12234 SDValue Idx = I->getOperand(1);
12235 if (!isa<ConstantSDNode>(Idx))
12238 SDValue ExtractedFromVec = I->getOperand(0);
12239 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12240 if (M == VecInMap.end()) {
12241 VT = ExtractedFromVec.getValueType();
12242 // Quit if not 128/256-bit vector.
12243 if (!VT.is128BitVector() && !VT.is256BitVector())
12245 // Quit if not the same type.
12246 if (VecInMap.begin() != VecInMap.end() &&
12247 VT != VecInMap.begin()->first.getValueType())
12249 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12250 VecIns.push_back(ExtractedFromVec);
12252 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12255 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12256 "Not extracted from 128-/256-bit vector.");
12258 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12260 for (DenseMap<SDValue, unsigned>::const_iterator
12261 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12262 // Quit if not all elements are used.
12263 if (I->second != FullMask)
12267 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12269 // Cast all vectors into TestVT for PTEST.
12270 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12271 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12273 // If more than one full vectors are evaluated, OR them first before PTEST.
12274 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12275 // Each iteration will OR 2 nodes and append the result until there is only
12276 // 1 node left, i.e. the final OR'd value of all vectors.
12277 SDValue LHS = VecIns[Slot];
12278 SDValue RHS = VecIns[Slot + 1];
12279 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12282 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12283 VecIns.back(), VecIns.back());
12286 /// \brief return true if \c Op has a use that doesn't just read flags.
12287 static bool hasNonFlagsUse(SDValue Op) {
12288 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12290 SDNode *User = *UI;
12291 unsigned UOpNo = UI.getOperandNo();
12292 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12293 // Look pass truncate.
12294 UOpNo = User->use_begin().getOperandNo();
12295 User = *User->use_begin();
12298 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12299 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12305 /// Emit nodes that will be selected as "test Op0,Op0", or something
12307 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12308 SelectionDAG &DAG) const {
12309 if (Op.getValueType() == MVT::i1)
12310 // KORTEST instruction should be selected
12311 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12312 DAG.getConstant(0, Op.getValueType()));
12314 // CF and OF aren't always set the way we want. Determine which
12315 // of these we need.
12316 bool NeedCF = false;
12317 bool NeedOF = false;
12320 case X86::COND_A: case X86::COND_AE:
12321 case X86::COND_B: case X86::COND_BE:
12324 case X86::COND_G: case X86::COND_GE:
12325 case X86::COND_L: case X86::COND_LE:
12326 case X86::COND_O: case X86::COND_NO: {
12327 // Check if we really need to set the
12328 // Overflow flag. If NoSignedWrap is present
12329 // that is not actually needed.
12330 switch (Op->getOpcode()) {
12335 const BinaryWithFlagsSDNode *BinNode =
12336 cast<BinaryWithFlagsSDNode>(Op.getNode());
12337 if (BinNode->hasNoSignedWrap())
12347 // See if we can use the EFLAGS value from the operand instead of
12348 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12349 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12350 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12351 // Emit a CMP with 0, which is the TEST pattern.
12352 //if (Op.getValueType() == MVT::i1)
12353 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12354 // DAG.getConstant(0, MVT::i1));
12355 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12356 DAG.getConstant(0, Op.getValueType()));
12358 unsigned Opcode = 0;
12359 unsigned NumOperands = 0;
12361 // Truncate operations may prevent the merge of the SETCC instruction
12362 // and the arithmetic instruction before it. Attempt to truncate the operands
12363 // of the arithmetic instruction and use a reduced bit-width instruction.
12364 bool NeedTruncation = false;
12365 SDValue ArithOp = Op;
12366 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12367 SDValue Arith = Op->getOperand(0);
12368 // Both the trunc and the arithmetic op need to have one user each.
12369 if (Arith->hasOneUse())
12370 switch (Arith.getOpcode()) {
12377 NeedTruncation = true;
12383 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12384 // which may be the result of a CAST. We use the variable 'Op', which is the
12385 // non-casted variable when we check for possible users.
12386 switch (ArithOp.getOpcode()) {
12388 // Due to an isel shortcoming, be conservative if this add is likely to be
12389 // selected as part of a load-modify-store instruction. When the root node
12390 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12391 // uses of other nodes in the match, such as the ADD in this case. This
12392 // leads to the ADD being left around and reselected, with the result being
12393 // two adds in the output. Alas, even if none our users are stores, that
12394 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12395 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12396 // climbing the DAG back to the root, and it doesn't seem to be worth the
12398 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12399 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12400 if (UI->getOpcode() != ISD::CopyToReg &&
12401 UI->getOpcode() != ISD::SETCC &&
12402 UI->getOpcode() != ISD::STORE)
12405 if (ConstantSDNode *C =
12406 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12407 // An add of one will be selected as an INC.
12408 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12409 Opcode = X86ISD::INC;
12414 // An add of negative one (subtract of one) will be selected as a DEC.
12415 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12416 Opcode = X86ISD::DEC;
12422 // Otherwise use a regular EFLAGS-setting add.
12423 Opcode = X86ISD::ADD;
12428 // If we have a constant logical shift that's only used in a comparison
12429 // against zero turn it into an equivalent AND. This allows turning it into
12430 // a TEST instruction later.
12431 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12432 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12433 EVT VT = Op.getValueType();
12434 unsigned BitWidth = VT.getSizeInBits();
12435 unsigned ShAmt = Op->getConstantOperandVal(1);
12436 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12438 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12439 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12440 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12441 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12443 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12444 DAG.getConstant(Mask, VT));
12445 DAG.ReplaceAllUsesWith(Op, New);
12451 // If the primary and result isn't used, don't bother using X86ISD::AND,
12452 // because a TEST instruction will be better.
12453 if (!hasNonFlagsUse(Op))
12459 // Due to the ISEL shortcoming noted above, be conservative if this op is
12460 // likely to be selected as part of a load-modify-store instruction.
12461 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12462 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12463 if (UI->getOpcode() == ISD::STORE)
12466 // Otherwise use a regular EFLAGS-setting instruction.
12467 switch (ArithOp.getOpcode()) {
12468 default: llvm_unreachable("unexpected operator!");
12469 case ISD::SUB: Opcode = X86ISD::SUB; break;
12470 case ISD::XOR: Opcode = X86ISD::XOR; break;
12471 case ISD::AND: Opcode = X86ISD::AND; break;
12473 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12474 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12475 if (EFLAGS.getNode())
12478 Opcode = X86ISD::OR;
12492 return SDValue(Op.getNode(), 1);
12498 // If we found that truncation is beneficial, perform the truncation and
12500 if (NeedTruncation) {
12501 EVT VT = Op.getValueType();
12502 SDValue WideVal = Op->getOperand(0);
12503 EVT WideVT = WideVal.getValueType();
12504 unsigned ConvertedOp = 0;
12505 // Use a target machine opcode to prevent further DAGCombine
12506 // optimizations that may separate the arithmetic operations
12507 // from the setcc node.
12508 switch (WideVal.getOpcode()) {
12510 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12511 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12512 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12513 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12514 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12519 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12520 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12521 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12522 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12528 // Emit a CMP with 0, which is the TEST pattern.
12529 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12530 DAG.getConstant(0, Op.getValueType()));
12532 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12533 SmallVector<SDValue, 4> Ops;
12534 for (unsigned i = 0; i != NumOperands; ++i)
12535 Ops.push_back(Op.getOperand(i));
12537 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12538 DAG.ReplaceAllUsesWith(Op, New);
12539 return SDValue(New.getNode(), 1);
12542 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12544 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12545 SDLoc dl, SelectionDAG &DAG) const {
12546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12547 if (C->getAPIntValue() == 0)
12548 return EmitTest(Op0, X86CC, dl, DAG);
12550 if (Op0.getValueType() == MVT::i1)
12551 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12554 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12555 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12556 // Do the comparison at i32 if it's smaller, besides the Atom case.
12557 // This avoids subregister aliasing issues. Keep the smaller reference
12558 // if we're optimizing for size, however, as that'll allow better folding
12559 // of memory operations.
12560 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12561 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12562 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12563 !Subtarget->isAtom()) {
12564 unsigned ExtendOp =
12565 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12566 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12567 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12569 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12570 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12571 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12573 return SDValue(Sub.getNode(), 1);
12575 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12578 /// Convert a comparison if required by the subtarget.
12579 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12580 SelectionDAG &DAG) const {
12581 // If the subtarget does not support the FUCOMI instruction, floating-point
12582 // comparisons have to be converted.
12583 if (Subtarget->hasCMov() ||
12584 Cmp.getOpcode() != X86ISD::CMP ||
12585 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12586 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12589 // The instruction selector will select an FUCOM instruction instead of
12590 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12591 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12592 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12594 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12595 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12596 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12597 DAG.getConstant(8, MVT::i8));
12598 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12599 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12602 static bool isAllOnes(SDValue V) {
12603 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12604 return C && C->isAllOnesValue();
12607 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12608 /// if it's possible.
12609 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12610 SDLoc dl, SelectionDAG &DAG) const {
12611 SDValue Op0 = And.getOperand(0);
12612 SDValue Op1 = And.getOperand(1);
12613 if (Op0.getOpcode() == ISD::TRUNCATE)
12614 Op0 = Op0.getOperand(0);
12615 if (Op1.getOpcode() == ISD::TRUNCATE)
12616 Op1 = Op1.getOperand(0);
12619 if (Op1.getOpcode() == ISD::SHL)
12620 std::swap(Op0, Op1);
12621 if (Op0.getOpcode() == ISD::SHL) {
12622 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12623 if (And00C->getZExtValue() == 1) {
12624 // If we looked past a truncate, check that it's only truncating away
12626 unsigned BitWidth = Op0.getValueSizeInBits();
12627 unsigned AndBitWidth = And.getValueSizeInBits();
12628 if (BitWidth > AndBitWidth) {
12630 DAG.computeKnownBits(Op0, Zeros, Ones);
12631 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12635 RHS = Op0.getOperand(1);
12637 } else if (Op1.getOpcode() == ISD::Constant) {
12638 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12639 uint64_t AndRHSVal = AndRHS->getZExtValue();
12640 SDValue AndLHS = Op0;
12642 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12643 LHS = AndLHS.getOperand(0);
12644 RHS = AndLHS.getOperand(1);
12647 // Use BT if the immediate can't be encoded in a TEST instruction.
12648 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12650 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12654 if (LHS.getNode()) {
12655 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12656 // instruction. Since the shift amount is in-range-or-undefined, we know
12657 // that doing a bittest on the i32 value is ok. We extend to i32 because
12658 // the encoding for the i16 version is larger than the i32 version.
12659 // Also promote i16 to i32 for performance / code size reason.
12660 if (LHS.getValueType() == MVT::i8 ||
12661 LHS.getValueType() == MVT::i16)
12662 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12664 // If the operand types disagree, extend the shift amount to match. Since
12665 // BT ignores high bits (like shifts) we can use anyextend.
12666 if (LHS.getValueType() != RHS.getValueType())
12667 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12669 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12670 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12671 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12672 DAG.getConstant(Cond, MVT::i8), BT);
12678 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12680 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12685 // SSE Condition code mapping:
12694 switch (SetCCOpcode) {
12695 default: llvm_unreachable("Unexpected SETCC condition");
12697 case ISD::SETEQ: SSECC = 0; break;
12699 case ISD::SETGT: Swap = true; // Fallthrough
12701 case ISD::SETOLT: SSECC = 1; break;
12703 case ISD::SETGE: Swap = true; // Fallthrough
12705 case ISD::SETOLE: SSECC = 2; break;
12706 case ISD::SETUO: SSECC = 3; break;
12708 case ISD::SETNE: SSECC = 4; break;
12709 case ISD::SETULE: Swap = true; // Fallthrough
12710 case ISD::SETUGE: SSECC = 5; break;
12711 case ISD::SETULT: Swap = true; // Fallthrough
12712 case ISD::SETUGT: SSECC = 6; break;
12713 case ISD::SETO: SSECC = 7; break;
12715 case ISD::SETONE: SSECC = 8; break;
12718 std::swap(Op0, Op1);
12723 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12724 // ones, and then concatenate the result back.
12725 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12726 MVT VT = Op.getSimpleValueType();
12728 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12729 "Unsupported value type for operation");
12731 unsigned NumElems = VT.getVectorNumElements();
12733 SDValue CC = Op.getOperand(2);
12735 // Extract the LHS vectors
12736 SDValue LHS = Op.getOperand(0);
12737 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12738 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12740 // Extract the RHS vectors
12741 SDValue RHS = Op.getOperand(1);
12742 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12743 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12745 // Issue the operation on the smaller types and concatenate the result back
12746 MVT EltVT = VT.getVectorElementType();
12747 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12748 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12749 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12750 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12753 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12754 const X86Subtarget *Subtarget) {
12755 SDValue Op0 = Op.getOperand(0);
12756 SDValue Op1 = Op.getOperand(1);
12757 SDValue CC = Op.getOperand(2);
12758 MVT VT = Op.getSimpleValueType();
12761 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12762 Op.getValueType().getScalarType() == MVT::i1 &&
12763 "Cannot set masked compare for this operation");
12765 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12767 bool Unsigned = false;
12770 switch (SetCCOpcode) {
12771 default: llvm_unreachable("Unexpected SETCC condition");
12772 case ISD::SETNE: SSECC = 4; break;
12773 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12774 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12775 case ISD::SETLT: Swap = true; //fall-through
12776 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12777 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12778 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12779 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12780 case ISD::SETULE: Unsigned = true; //fall-through
12781 case ISD::SETLE: SSECC = 2; break;
12785 std::swap(Op0, Op1);
12787 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12788 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12789 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12790 DAG.getConstant(SSECC, MVT::i8));
12793 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12794 /// operand \p Op1. If non-trivial (for example because it's not constant)
12795 /// return an empty value.
12796 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12798 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12802 MVT VT = Op1.getSimpleValueType();
12803 MVT EVT = VT.getVectorElementType();
12804 unsigned n = VT.getVectorNumElements();
12805 SmallVector<SDValue, 8> ULTOp1;
12807 for (unsigned i = 0; i < n; ++i) {
12808 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12809 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12812 // Avoid underflow.
12813 APInt Val = Elt->getAPIntValue();
12817 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12820 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12823 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12824 SelectionDAG &DAG) {
12825 SDValue Op0 = Op.getOperand(0);
12826 SDValue Op1 = Op.getOperand(1);
12827 SDValue CC = Op.getOperand(2);
12828 MVT VT = Op.getSimpleValueType();
12829 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12830 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12835 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12836 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12839 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12840 unsigned Opc = X86ISD::CMPP;
12841 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12842 assert(VT.getVectorNumElements() <= 16);
12843 Opc = X86ISD::CMPM;
12845 // In the two special cases we can't handle, emit two comparisons.
12848 unsigned CombineOpc;
12849 if (SetCCOpcode == ISD::SETUEQ) {
12850 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12852 assert(SetCCOpcode == ISD::SETONE);
12853 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12856 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12857 DAG.getConstant(CC0, MVT::i8));
12858 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12859 DAG.getConstant(CC1, MVT::i8));
12860 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12862 // Handle all other FP comparisons here.
12863 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12864 DAG.getConstant(SSECC, MVT::i8));
12867 // Break 256-bit integer vector compare into smaller ones.
12868 if (VT.is256BitVector() && !Subtarget->hasInt256())
12869 return Lower256IntVSETCC(Op, DAG);
12871 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12872 EVT OpVT = Op1.getValueType();
12873 if (Subtarget->hasAVX512()) {
12874 if (Op1.getValueType().is512BitVector() ||
12875 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12876 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12878 // In AVX-512 architecture setcc returns mask with i1 elements,
12879 // But there is no compare instruction for i8 and i16 elements.
12880 // We are not talking about 512-bit operands in this case, these
12881 // types are illegal.
12883 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12884 OpVT.getVectorElementType().getSizeInBits() >= 8))
12885 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12886 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12889 // We are handling one of the integer comparisons here. Since SSE only has
12890 // GT and EQ comparisons for integer, swapping operands and multiple
12891 // operations may be required for some comparisons.
12893 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12894 bool Subus = false;
12896 switch (SetCCOpcode) {
12897 default: llvm_unreachable("Unexpected SETCC condition");
12898 case ISD::SETNE: Invert = true;
12899 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12900 case ISD::SETLT: Swap = true;
12901 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12902 case ISD::SETGE: Swap = true;
12903 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12904 Invert = true; break;
12905 case ISD::SETULT: Swap = true;
12906 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12907 FlipSigns = true; break;
12908 case ISD::SETUGE: Swap = true;
12909 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12910 FlipSigns = true; Invert = true; break;
12913 // Special case: Use min/max operations for SETULE/SETUGE
12914 MVT VET = VT.getVectorElementType();
12916 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12917 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12920 switch (SetCCOpcode) {
12922 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12923 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12926 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12929 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12930 if (!MinMax && hasSubus) {
12931 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12933 // t = psubus Op0, Op1
12934 // pcmpeq t, <0..0>
12935 switch (SetCCOpcode) {
12937 case ISD::SETULT: {
12938 // If the comparison is against a constant we can turn this into a
12939 // setule. With psubus, setule does not require a swap. This is
12940 // beneficial because the constant in the register is no longer
12941 // destructed as the destination so it can be hoisted out of a loop.
12942 // Only do this pre-AVX since vpcmp* is no longer destructive.
12943 if (Subtarget->hasAVX())
12945 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12946 if (ULEOp1.getNode()) {
12948 Subus = true; Invert = false; Swap = false;
12952 // Psubus is better than flip-sign because it requires no inversion.
12953 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12954 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12958 Opc = X86ISD::SUBUS;
12964 std::swap(Op0, Op1);
12966 // Check that the operation in question is available (most are plain SSE2,
12967 // but PCMPGTQ and PCMPEQQ have different requirements).
12968 if (VT == MVT::v2i64) {
12969 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12970 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12972 // First cast everything to the right type.
12973 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12974 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12976 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12977 // bits of the inputs before performing those operations. The lower
12978 // compare is always unsigned.
12981 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12983 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12984 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12985 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12986 Sign, Zero, Sign, Zero);
12988 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12989 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12991 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12992 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12993 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12995 // Create masks for only the low parts/high parts of the 64 bit integers.
12996 static const int MaskHi[] = { 1, 1, 3, 3 };
12997 static const int MaskLo[] = { 0, 0, 2, 2 };
12998 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12999 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13000 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13002 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13003 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13006 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13008 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13011 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13012 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13013 // pcmpeqd + pshufd + pand.
13014 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13016 // First cast everything to the right type.
13017 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13018 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13021 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13023 // Make sure the lower and upper halves are both all-ones.
13024 static const int Mask[] = { 1, 0, 3, 2 };
13025 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13026 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13029 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13031 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13035 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13036 // bits of the inputs before performing those operations.
13038 EVT EltVT = VT.getVectorElementType();
13039 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13040 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13041 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13044 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13046 // If the logical-not of the result is required, perform that now.
13048 Result = DAG.getNOT(dl, Result, VT);
13051 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13054 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13055 getZeroVector(VT, Subtarget, DAG, dl));
13060 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13062 MVT VT = Op.getSimpleValueType();
13064 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13066 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13067 && "SetCC type must be 8-bit or 1-bit integer");
13068 SDValue Op0 = Op.getOperand(0);
13069 SDValue Op1 = Op.getOperand(1);
13071 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13073 // Optimize to BT if possible.
13074 // Lower (X & (1 << N)) == 0 to BT(X, N).
13075 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13076 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13077 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13078 Op1.getOpcode() == ISD::Constant &&
13079 cast<ConstantSDNode>(Op1)->isNullValue() &&
13080 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13081 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13082 if (NewSetCC.getNode())
13086 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13088 if (Op1.getOpcode() == ISD::Constant &&
13089 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13090 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13091 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13093 // If the input is a setcc, then reuse the input setcc or use a new one with
13094 // the inverted condition.
13095 if (Op0.getOpcode() == X86ISD::SETCC) {
13096 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13097 bool Invert = (CC == ISD::SETNE) ^
13098 cast<ConstantSDNode>(Op1)->isNullValue();
13102 CCode = X86::GetOppositeBranchCondition(CCode);
13103 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13104 DAG.getConstant(CCode, MVT::i8),
13105 Op0.getOperand(1));
13107 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13111 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13112 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13113 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13115 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13116 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13119 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13120 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13121 if (X86CC == X86::COND_INVALID)
13124 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13125 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13126 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13127 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13129 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13133 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13134 static bool isX86LogicalCmp(SDValue Op) {
13135 unsigned Opc = Op.getNode()->getOpcode();
13136 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13137 Opc == X86ISD::SAHF)
13139 if (Op.getResNo() == 1 &&
13140 (Opc == X86ISD::ADD ||
13141 Opc == X86ISD::SUB ||
13142 Opc == X86ISD::ADC ||
13143 Opc == X86ISD::SBB ||
13144 Opc == X86ISD::SMUL ||
13145 Opc == X86ISD::UMUL ||
13146 Opc == X86ISD::INC ||
13147 Opc == X86ISD::DEC ||
13148 Opc == X86ISD::OR ||
13149 Opc == X86ISD::XOR ||
13150 Opc == X86ISD::AND))
13153 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13159 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13160 if (V.getOpcode() != ISD::TRUNCATE)
13163 SDValue VOp0 = V.getOperand(0);
13164 unsigned InBits = VOp0.getValueSizeInBits();
13165 unsigned Bits = V.getValueSizeInBits();
13166 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13169 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13170 bool addTest = true;
13171 SDValue Cond = Op.getOperand(0);
13172 SDValue Op1 = Op.getOperand(1);
13173 SDValue Op2 = Op.getOperand(2);
13175 EVT VT = Op1.getValueType();
13178 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13179 // are available. Otherwise fp cmovs get lowered into a less efficient branch
13180 // sequence later on.
13181 if (Cond.getOpcode() == ISD::SETCC &&
13182 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13183 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13184 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13185 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13186 int SSECC = translateX86FSETCC(
13187 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13190 if (Subtarget->hasAVX512()) {
13191 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13192 DAG.getConstant(SSECC, MVT::i8));
13193 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13195 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13196 DAG.getConstant(SSECC, MVT::i8));
13197 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13198 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13199 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13203 if (Cond.getOpcode() == ISD::SETCC) {
13204 SDValue NewCond = LowerSETCC(Cond, DAG);
13205 if (NewCond.getNode())
13209 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13210 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13211 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13212 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13213 if (Cond.getOpcode() == X86ISD::SETCC &&
13214 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13215 isZero(Cond.getOperand(1).getOperand(1))) {
13216 SDValue Cmp = Cond.getOperand(1);
13218 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13220 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13221 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13222 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13224 SDValue CmpOp0 = Cmp.getOperand(0);
13225 // Apply further optimizations for special cases
13226 // (select (x != 0), -1, 0) -> neg & sbb
13227 // (select (x == 0), 0, -1) -> neg & sbb
13228 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13229 if (YC->isNullValue() &&
13230 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13231 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13232 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13233 DAG.getConstant(0, CmpOp0.getValueType()),
13235 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13236 DAG.getConstant(X86::COND_B, MVT::i8),
13237 SDValue(Neg.getNode(), 1));
13241 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13242 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13243 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13245 SDValue Res = // Res = 0 or -1.
13246 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13247 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13249 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13250 Res = DAG.getNOT(DL, Res, Res.getValueType());
13252 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13253 if (!N2C || !N2C->isNullValue())
13254 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13259 // Look past (and (setcc_carry (cmp ...)), 1).
13260 if (Cond.getOpcode() == ISD::AND &&
13261 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13262 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13263 if (C && C->getAPIntValue() == 1)
13264 Cond = Cond.getOperand(0);
13267 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13268 // setting operand in place of the X86ISD::SETCC.
13269 unsigned CondOpcode = Cond.getOpcode();
13270 if (CondOpcode == X86ISD::SETCC ||
13271 CondOpcode == X86ISD::SETCC_CARRY) {
13272 CC = Cond.getOperand(0);
13274 SDValue Cmp = Cond.getOperand(1);
13275 unsigned Opc = Cmp.getOpcode();
13276 MVT VT = Op.getSimpleValueType();
13278 bool IllegalFPCMov = false;
13279 if (VT.isFloatingPoint() && !VT.isVector() &&
13280 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13281 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13283 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13284 Opc == X86ISD::BT) { // FIXME
13288 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13289 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13290 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13291 Cond.getOperand(0).getValueType() != MVT::i8)) {
13292 SDValue LHS = Cond.getOperand(0);
13293 SDValue RHS = Cond.getOperand(1);
13294 unsigned X86Opcode;
13297 switch (CondOpcode) {
13298 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13299 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13300 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13301 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13302 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13303 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13304 default: llvm_unreachable("unexpected overflowing operator");
13306 if (CondOpcode == ISD::UMULO)
13307 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13310 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13312 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13314 if (CondOpcode == ISD::UMULO)
13315 Cond = X86Op.getValue(2);
13317 Cond = X86Op.getValue(1);
13319 CC = DAG.getConstant(X86Cond, MVT::i8);
13324 // Look pass the truncate if the high bits are known zero.
13325 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13326 Cond = Cond.getOperand(0);
13328 // We know the result of AND is compared against zero. Try to match
13330 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13331 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13332 if (NewSetCC.getNode()) {
13333 CC = NewSetCC.getOperand(0);
13334 Cond = NewSetCC.getOperand(1);
13341 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13342 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13345 // a < b ? -1 : 0 -> RES = ~setcc_carry
13346 // a < b ? 0 : -1 -> RES = setcc_carry
13347 // a >= b ? -1 : 0 -> RES = setcc_carry
13348 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13349 if (Cond.getOpcode() == X86ISD::SUB) {
13350 Cond = ConvertCmpIfNecessary(Cond, DAG);
13351 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13353 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13354 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13355 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13356 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13357 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13358 return DAG.getNOT(DL, Res, Res.getValueType());
13363 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13364 // widen the cmov and push the truncate through. This avoids introducing a new
13365 // branch during isel and doesn't add any extensions.
13366 if (Op.getValueType() == MVT::i8 &&
13367 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13368 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13369 if (T1.getValueType() == T2.getValueType() &&
13370 // Blacklist CopyFromReg to avoid partial register stalls.
13371 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13372 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13373 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13374 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13378 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13379 // condition is true.
13380 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13381 SDValue Ops[] = { Op2, Op1, CC, Cond };
13382 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13385 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
13386 MVT VT = Op->getSimpleValueType(0);
13387 SDValue In = Op->getOperand(0);
13388 MVT InVT = In.getSimpleValueType();
13391 unsigned int NumElts = VT.getVectorNumElements();
13392 if (NumElts != 8 && NumElts != 16)
13395 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13396 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13398 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13399 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13401 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13402 Constant *C = ConstantInt::get(*DAG.getContext(),
13403 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13405 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13406 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13407 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13408 MachinePointerInfo::getConstantPool(),
13409 false, false, false, Alignment);
13410 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13411 if (VT.is512BitVector())
13413 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13416 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13417 SelectionDAG &DAG) {
13418 MVT VT = Op->getSimpleValueType(0);
13419 SDValue In = Op->getOperand(0);
13420 MVT InVT = In.getSimpleValueType();
13423 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13424 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13426 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13427 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13428 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13431 if (Subtarget->hasInt256())
13432 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13434 // Optimize vectors in AVX mode
13435 // Sign extend v8i16 to v8i32 and
13438 // Divide input vector into two parts
13439 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13440 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13441 // concat the vectors to original VT
13443 unsigned NumElems = InVT.getVectorNumElements();
13444 SDValue Undef = DAG.getUNDEF(InVT);
13446 SmallVector<int,8> ShufMask1(NumElems, -1);
13447 for (unsigned i = 0; i != NumElems/2; ++i)
13450 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13452 SmallVector<int,8> ShufMask2(NumElems, -1);
13453 for (unsigned i = 0; i != NumElems/2; ++i)
13454 ShufMask2[i] = i + NumElems/2;
13456 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13458 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13459 VT.getVectorNumElements()/2);
13461 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13462 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13464 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13467 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13468 // may emit an illegal shuffle but the expansion is still better than scalar
13469 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13470 // we'll emit a shuffle and a arithmetic shift.
13471 // TODO: It is possible to support ZExt by zeroing the undef values during
13472 // the shuffle phase or after the shuffle.
13473 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13474 SelectionDAG &DAG) {
13475 MVT RegVT = Op.getSimpleValueType();
13476 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13477 assert(RegVT.isInteger() &&
13478 "We only custom lower integer vector sext loads.");
13480 // Nothing useful we can do without SSE2 shuffles.
13481 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13483 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13485 EVT MemVT = Ld->getMemoryVT();
13486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13487 unsigned RegSz = RegVT.getSizeInBits();
13489 ISD::LoadExtType Ext = Ld->getExtensionType();
13491 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13492 && "Only anyext and sext are currently implemented.");
13493 assert(MemVT != RegVT && "Cannot extend to the same type");
13494 assert(MemVT.isVector() && "Must load a vector from memory");
13496 unsigned NumElems = RegVT.getVectorNumElements();
13497 unsigned MemSz = MemVT.getSizeInBits();
13498 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13500 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13501 // The only way in which we have a legal 256-bit vector result but not the
13502 // integer 256-bit operations needed to directly lower a sextload is if we
13503 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13504 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13505 // correctly legalized. We do this late to allow the canonical form of
13506 // sextload to persist throughout the rest of the DAG combiner -- it wants
13507 // to fold together any extensions it can, and so will fuse a sign_extend
13508 // of an sextload into a sextload targeting a wider value.
13510 if (MemSz == 128) {
13511 // Just switch this to a normal load.
13512 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13513 "it must be a legal 128-bit vector "
13515 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13516 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13517 Ld->isInvariant(), Ld->getAlignment());
13519 assert(MemSz < 128 &&
13520 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13521 // Do an sext load to a 128-bit vector type. We want to use the same
13522 // number of elements, but elements half as wide. This will end up being
13523 // recursively lowered by this routine, but will succeed as we definitely
13524 // have all the necessary features if we're using AVX1.
13526 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13527 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13529 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13530 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13531 Ld->isNonTemporal(), Ld->isInvariant(),
13532 Ld->getAlignment());
13535 // Replace chain users with the new chain.
13536 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13537 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13539 // Finally, do a normal sign-extend to the desired register.
13540 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13543 // All sizes must be a power of two.
13544 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13545 "Non-power-of-two elements are not custom lowered!");
13547 // Attempt to load the original value using scalar loads.
13548 // Find the largest scalar type that divides the total loaded size.
13549 MVT SclrLoadTy = MVT::i8;
13550 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13551 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13552 MVT Tp = (MVT::SimpleValueType)tp;
13553 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13558 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13559 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13561 SclrLoadTy = MVT::f64;
13563 // Calculate the number of scalar loads that we need to perform
13564 // in order to load our vector from memory.
13565 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13567 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13568 "Can only lower sext loads with a single scalar load!");
13570 unsigned loadRegZize = RegSz;
13571 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13574 // Represent our vector as a sequence of elements which are the
13575 // largest scalar that we can load.
13576 EVT LoadUnitVecVT = EVT::getVectorVT(
13577 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13579 // Represent the data using the same element type that is stored in
13580 // memory. In practice, we ''widen'' MemVT.
13582 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13583 loadRegZize / MemVT.getScalarType().getSizeInBits());
13585 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13586 "Invalid vector type");
13588 // We can't shuffle using an illegal type.
13589 assert(TLI.isTypeLegal(WideVecVT) &&
13590 "We only lower types that form legal widened vector types");
13592 SmallVector<SDValue, 8> Chains;
13593 SDValue Ptr = Ld->getBasePtr();
13594 SDValue Increment =
13595 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13596 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13598 for (unsigned i = 0; i < NumLoads; ++i) {
13599 // Perform a single load.
13600 SDValue ScalarLoad =
13601 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13602 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13603 Ld->getAlignment());
13604 Chains.push_back(ScalarLoad.getValue(1));
13605 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13606 // another round of DAGCombining.
13608 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13610 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13611 ScalarLoad, DAG.getIntPtrConstant(i));
13613 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13616 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13618 // Bitcast the loaded value to a vector of the original element type, in
13619 // the size of the target vector type.
13620 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13621 unsigned SizeRatio = RegSz / MemSz;
13623 if (Ext == ISD::SEXTLOAD) {
13624 // If we have SSE4.1, we can directly emit a VSEXT node.
13625 if (Subtarget->hasSSE41()) {
13626 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13627 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13631 // Otherwise we'll shuffle the small elements in the high bits of the
13632 // larger type and perform an arithmetic shift. If the shift is not legal
13633 // it's better to scalarize.
13634 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13635 "We can't implement a sext load without an arithmetic right shift!");
13637 // Redistribute the loaded elements into the different locations.
13638 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13639 for (unsigned i = 0; i != NumElems; ++i)
13640 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13642 SDValue Shuff = DAG.getVectorShuffle(
13643 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13645 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13647 // Build the arithmetic shift.
13648 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13649 MemVT.getVectorElementType().getSizeInBits();
13651 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13653 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13657 // Redistribute the loaded elements into the different locations.
13658 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13659 for (unsigned i = 0; i != NumElems; ++i)
13660 ShuffleVec[i * SizeRatio] = i;
13662 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13663 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13665 // Bitcast to the requested type.
13666 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13667 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13671 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13672 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13673 // from the AND / OR.
13674 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13675 Opc = Op.getOpcode();
13676 if (Opc != ISD::OR && Opc != ISD::AND)
13678 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13679 Op.getOperand(0).hasOneUse() &&
13680 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13681 Op.getOperand(1).hasOneUse());
13684 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13685 // 1 and that the SETCC node has a single use.
13686 static bool isXor1OfSetCC(SDValue Op) {
13687 if (Op.getOpcode() != ISD::XOR)
13689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13690 if (N1C && N1C->getAPIntValue() == 1) {
13691 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13692 Op.getOperand(0).hasOneUse();
13697 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13698 bool addTest = true;
13699 SDValue Chain = Op.getOperand(0);
13700 SDValue Cond = Op.getOperand(1);
13701 SDValue Dest = Op.getOperand(2);
13704 bool Inverted = false;
13706 if (Cond.getOpcode() == ISD::SETCC) {
13707 // Check for setcc([su]{add,sub,mul}o == 0).
13708 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13709 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13710 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13711 Cond.getOperand(0).getResNo() == 1 &&
13712 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13713 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13714 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13715 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13716 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13717 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13719 Cond = Cond.getOperand(0);
13721 SDValue NewCond = LowerSETCC(Cond, DAG);
13722 if (NewCond.getNode())
13727 // FIXME: LowerXALUO doesn't handle these!!
13728 else if (Cond.getOpcode() == X86ISD::ADD ||
13729 Cond.getOpcode() == X86ISD::SUB ||
13730 Cond.getOpcode() == X86ISD::SMUL ||
13731 Cond.getOpcode() == X86ISD::UMUL)
13732 Cond = LowerXALUO(Cond, DAG);
13735 // Look pass (and (setcc_carry (cmp ...)), 1).
13736 if (Cond.getOpcode() == ISD::AND &&
13737 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13738 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13739 if (C && C->getAPIntValue() == 1)
13740 Cond = Cond.getOperand(0);
13743 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13744 // setting operand in place of the X86ISD::SETCC.
13745 unsigned CondOpcode = Cond.getOpcode();
13746 if (CondOpcode == X86ISD::SETCC ||
13747 CondOpcode == X86ISD::SETCC_CARRY) {
13748 CC = Cond.getOperand(0);
13750 SDValue Cmp = Cond.getOperand(1);
13751 unsigned Opc = Cmp.getOpcode();
13752 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13753 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13757 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13761 // These can only come from an arithmetic instruction with overflow,
13762 // e.g. SADDO, UADDO.
13763 Cond = Cond.getNode()->getOperand(1);
13769 CondOpcode = Cond.getOpcode();
13770 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13771 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13772 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13773 Cond.getOperand(0).getValueType() != MVT::i8)) {
13774 SDValue LHS = Cond.getOperand(0);
13775 SDValue RHS = Cond.getOperand(1);
13776 unsigned X86Opcode;
13779 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13780 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13782 switch (CondOpcode) {
13783 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13785 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13787 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13790 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13791 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13793 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13795 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13798 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13799 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13800 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13801 default: llvm_unreachable("unexpected overflowing operator");
13804 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13805 if (CondOpcode == ISD::UMULO)
13806 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13809 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13811 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13813 if (CondOpcode == ISD::UMULO)
13814 Cond = X86Op.getValue(2);
13816 Cond = X86Op.getValue(1);
13818 CC = DAG.getConstant(X86Cond, MVT::i8);
13822 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13823 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13824 if (CondOpc == ISD::OR) {
13825 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13826 // two branches instead of an explicit OR instruction with a
13828 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13829 isX86LogicalCmp(Cmp)) {
13830 CC = Cond.getOperand(0).getOperand(0);
13831 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13832 Chain, Dest, CC, Cmp);
13833 CC = Cond.getOperand(1).getOperand(0);
13837 } else { // ISD::AND
13838 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13839 // two branches instead of an explicit AND instruction with a
13840 // separate test. However, we only do this if this block doesn't
13841 // have a fall-through edge, because this requires an explicit
13842 // jmp when the condition is false.
13843 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13844 isX86LogicalCmp(Cmp) &&
13845 Op.getNode()->hasOneUse()) {
13846 X86::CondCode CCode =
13847 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13848 CCode = X86::GetOppositeBranchCondition(CCode);
13849 CC = DAG.getConstant(CCode, MVT::i8);
13850 SDNode *User = *Op.getNode()->use_begin();
13851 // Look for an unconditional branch following this conditional branch.
13852 // We need this because we need to reverse the successors in order
13853 // to implement FCMP_OEQ.
13854 if (User->getOpcode() == ISD::BR) {
13855 SDValue FalseBB = User->getOperand(1);
13857 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13858 assert(NewBR == User);
13862 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13863 Chain, Dest, CC, Cmp);
13864 X86::CondCode CCode =
13865 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13866 CCode = X86::GetOppositeBranchCondition(CCode);
13867 CC = DAG.getConstant(CCode, MVT::i8);
13873 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13874 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13875 // It should be transformed during dag combiner except when the condition
13876 // is set by a arithmetics with overflow node.
13877 X86::CondCode CCode =
13878 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13879 CCode = X86::GetOppositeBranchCondition(CCode);
13880 CC = DAG.getConstant(CCode, MVT::i8);
13881 Cond = Cond.getOperand(0).getOperand(1);
13883 } else if (Cond.getOpcode() == ISD::SETCC &&
13884 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13885 // For FCMP_OEQ, we can emit
13886 // two branches instead of an explicit AND instruction with a
13887 // separate test. However, we only do this if this block doesn't
13888 // have a fall-through edge, because this requires an explicit
13889 // jmp when the condition is false.
13890 if (Op.getNode()->hasOneUse()) {
13891 SDNode *User = *Op.getNode()->use_begin();
13892 // Look for an unconditional branch following this conditional branch.
13893 // We need this because we need to reverse the successors in order
13894 // to implement FCMP_OEQ.
13895 if (User->getOpcode() == ISD::BR) {
13896 SDValue FalseBB = User->getOperand(1);
13898 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13899 assert(NewBR == User);
13903 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13904 Cond.getOperand(0), Cond.getOperand(1));
13905 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13906 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13907 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13908 Chain, Dest, CC, Cmp);
13909 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13914 } else if (Cond.getOpcode() == ISD::SETCC &&
13915 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13916 // For FCMP_UNE, we can emit
13917 // two branches instead of an explicit AND instruction with a
13918 // separate test. However, we only do this if this block doesn't
13919 // have a fall-through edge, because this requires an explicit
13920 // jmp when the condition is false.
13921 if (Op.getNode()->hasOneUse()) {
13922 SDNode *User = *Op.getNode()->use_begin();
13923 // Look for an unconditional branch following this conditional branch.
13924 // We need this because we need to reverse the successors in order
13925 // to implement FCMP_UNE.
13926 if (User->getOpcode() == ISD::BR) {
13927 SDValue FalseBB = User->getOperand(1);
13929 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13930 assert(NewBR == User);
13933 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13934 Cond.getOperand(0), Cond.getOperand(1));
13935 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13936 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13937 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13938 Chain, Dest, CC, Cmp);
13939 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13949 // Look pass the truncate if the high bits are known zero.
13950 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13951 Cond = Cond.getOperand(0);
13953 // We know the result of AND is compared against zero. Try to match
13955 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13956 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13957 if (NewSetCC.getNode()) {
13958 CC = NewSetCC.getOperand(0);
13959 Cond = NewSetCC.getOperand(1);
13966 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13967 CC = DAG.getConstant(X86Cond, MVT::i8);
13968 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13970 Cond = ConvertCmpIfNecessary(Cond, DAG);
13971 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13972 Chain, Dest, CC, Cond);
13975 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13976 // Calls to _alloca are needed to probe the stack when allocating more than 4k
13977 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13978 // that the guard pages used by the OS virtual memory manager are allocated in
13979 // correct sequence.
13981 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13982 SelectionDAG &DAG) const {
13983 MachineFunction &MF = DAG.getMachineFunction();
13984 bool SplitStack = MF.shouldSplitStack();
13985 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13990 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13991 SDNode* Node = Op.getNode();
13993 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13994 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13995 " not tell us which reg is the stack pointer!");
13996 EVT VT = Node->getValueType(0);
13997 SDValue Tmp1 = SDValue(Node, 0);
13998 SDValue Tmp2 = SDValue(Node, 1);
13999 SDValue Tmp3 = Node->getOperand(2);
14000 SDValue Chain = Tmp1.getOperand(0);
14002 // Chain the dynamic stack allocation so that it doesn't modify the stack
14003 // pointer when other instructions are using the stack.
14004 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14007 SDValue Size = Tmp2.getOperand(1);
14008 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14009 Chain = SP.getValue(1);
14010 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14011 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
14012 unsigned StackAlign = TFI.getStackAlignment();
14013 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14014 if (Align > StackAlign)
14015 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14016 DAG.getConstant(-(uint64_t)Align, VT));
14017 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14019 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14020 DAG.getIntPtrConstant(0, true), SDValue(),
14023 SDValue Ops[2] = { Tmp1, Tmp2 };
14024 return DAG.getMergeValues(Ops, dl);
14028 SDValue Chain = Op.getOperand(0);
14029 SDValue Size = Op.getOperand(1);
14030 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14031 EVT VT = Op.getNode()->getValueType(0);
14033 bool Is64Bit = Subtarget->is64Bit();
14034 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
14037 MachineRegisterInfo &MRI = MF.getRegInfo();
14040 // The 64 bit implementation of segmented stacks needs to clobber both r10
14041 // r11. This makes it impossible to use it along with nested parameters.
14042 const Function *F = MF.getFunction();
14044 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14046 if (I->hasNestAttr())
14047 report_fatal_error("Cannot use segmented stacks with functions that "
14048 "have nested arguments.");
14051 const TargetRegisterClass *AddrRegClass =
14052 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
14053 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14054 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14055 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14056 DAG.getRegister(Vreg, SPTy));
14057 SDValue Ops1[2] = { Value, Chain };
14058 return DAG.getMergeValues(Ops1, dl);
14061 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
14063 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14064 Flag = Chain.getValue(1);
14065 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14067 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14069 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
14070 DAG.getSubtarget().getRegisterInfo());
14071 unsigned SPReg = RegInfo->getStackRegister();
14072 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14073 Chain = SP.getValue(1);
14076 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14077 DAG.getConstant(-(uint64_t)Align, VT));
14078 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14081 SDValue Ops1[2] = { SP, Chain };
14082 return DAG.getMergeValues(Ops1, dl);
14086 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14087 MachineFunction &MF = DAG.getMachineFunction();
14088 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14090 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14093 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14094 // vastart just stores the address of the VarArgsFrameIndex slot into the
14095 // memory location argument.
14096 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14098 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14099 MachinePointerInfo(SV), false, false, 0);
14103 // gp_offset (0 - 6 * 8)
14104 // fp_offset (48 - 48 + 8 * 16)
14105 // overflow_arg_area (point to parameters coming in memory).
14107 SmallVector<SDValue, 8> MemOps;
14108 SDValue FIN = Op.getOperand(1);
14110 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14111 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14113 FIN, MachinePointerInfo(SV), false, false, 0);
14114 MemOps.push_back(Store);
14117 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14118 FIN, DAG.getIntPtrConstant(4));
14119 Store = DAG.getStore(Op.getOperand(0), DL,
14120 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14122 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14123 MemOps.push_back(Store);
14125 // Store ptr to overflow_arg_area
14126 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14127 FIN, DAG.getIntPtrConstant(4));
14128 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14130 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14131 MachinePointerInfo(SV, 8),
14133 MemOps.push_back(Store);
14135 // Store ptr to reg_save_area.
14136 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14137 FIN, DAG.getIntPtrConstant(8));
14138 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14140 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14141 MachinePointerInfo(SV, 16), false, false, 0);
14142 MemOps.push_back(Store);
14143 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14146 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14147 assert(Subtarget->is64Bit() &&
14148 "LowerVAARG only handles 64-bit va_arg!");
14149 assert((Subtarget->isTargetLinux() ||
14150 Subtarget->isTargetDarwin()) &&
14151 "Unhandled target in LowerVAARG");
14152 assert(Op.getNode()->getNumOperands() == 4);
14153 SDValue Chain = Op.getOperand(0);
14154 SDValue SrcPtr = Op.getOperand(1);
14155 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14156 unsigned Align = Op.getConstantOperandVal(3);
14159 EVT ArgVT = Op.getNode()->getValueType(0);
14160 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14161 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14164 // Decide which area this value should be read from.
14165 // TODO: Implement the AMD64 ABI in its entirety. This simple
14166 // selection mechanism works only for the basic types.
14167 if (ArgVT == MVT::f80) {
14168 llvm_unreachable("va_arg for f80 not yet implemented");
14169 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14170 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14171 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14172 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14174 llvm_unreachable("Unhandled argument type in LowerVAARG");
14177 if (ArgMode == 2) {
14178 // Sanity Check: Make sure using fp_offset makes sense.
14179 assert(!DAG.getTarget().Options.UseSoftFloat &&
14180 !(DAG.getMachineFunction()
14181 .getFunction()->getAttributes()
14182 .hasAttribute(AttributeSet::FunctionIndex,
14183 Attribute::NoImplicitFloat)) &&
14184 Subtarget->hasSSE1());
14187 // Insert VAARG_64 node into the DAG
14188 // VAARG_64 returns two values: Variable Argument Address, Chain
14189 SmallVector<SDValue, 11> InstOps;
14190 InstOps.push_back(Chain);
14191 InstOps.push_back(SrcPtr);
14192 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
14193 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
14194 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
14195 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14196 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14197 VTs, InstOps, MVT::i64,
14198 MachinePointerInfo(SV),
14200 /*Volatile=*/false,
14202 /*WriteMem=*/true);
14203 Chain = VAARG.getValue(1);
14205 // Load the next argument and return it
14206 return DAG.getLoad(ArgVT, dl,
14209 MachinePointerInfo(),
14210 false, false, false, 0);
14213 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14214 SelectionDAG &DAG) {
14215 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14216 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14217 SDValue Chain = Op.getOperand(0);
14218 SDValue DstPtr = Op.getOperand(1);
14219 SDValue SrcPtr = Op.getOperand(2);
14220 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14221 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14224 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14225 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14227 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14230 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14231 // amount is a constant. Takes immediate version of shift as input.
14232 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14233 SDValue SrcOp, uint64_t ShiftAmt,
14234 SelectionDAG &DAG) {
14235 MVT ElementType = VT.getVectorElementType();
14237 // Fold this packed shift into its first operand if ShiftAmt is 0.
14241 // Check for ShiftAmt >= element width
14242 if (ShiftAmt >= ElementType.getSizeInBits()) {
14243 if (Opc == X86ISD::VSRAI)
14244 ShiftAmt = ElementType.getSizeInBits() - 1;
14246 return DAG.getConstant(0, VT);
14249 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14250 && "Unknown target vector shift-by-constant node");
14252 // Fold this packed vector shift into a build vector if SrcOp is a
14253 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14254 if (VT == SrcOp.getSimpleValueType() &&
14255 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14256 SmallVector<SDValue, 8> Elts;
14257 unsigned NumElts = SrcOp->getNumOperands();
14258 ConstantSDNode *ND;
14261 default: llvm_unreachable(nullptr);
14262 case X86ISD::VSHLI:
14263 for (unsigned i=0; i!=NumElts; ++i) {
14264 SDValue CurrentOp = SrcOp->getOperand(i);
14265 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14266 Elts.push_back(CurrentOp);
14269 ND = cast<ConstantSDNode>(CurrentOp);
14270 const APInt &C = ND->getAPIntValue();
14271 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14274 case X86ISD::VSRLI:
14275 for (unsigned i=0; i!=NumElts; ++i) {
14276 SDValue CurrentOp = SrcOp->getOperand(i);
14277 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14278 Elts.push_back(CurrentOp);
14281 ND = cast<ConstantSDNode>(CurrentOp);
14282 const APInt &C = ND->getAPIntValue();
14283 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14286 case X86ISD::VSRAI:
14287 for (unsigned i=0; i!=NumElts; ++i) {
14288 SDValue CurrentOp = SrcOp->getOperand(i);
14289 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14290 Elts.push_back(CurrentOp);
14293 ND = cast<ConstantSDNode>(CurrentOp);
14294 const APInt &C = ND->getAPIntValue();
14295 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14300 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14303 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14306 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14307 // may or may not be a constant. Takes immediate version of shift as input.
14308 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14309 SDValue SrcOp, SDValue ShAmt,
14310 SelectionDAG &DAG) {
14311 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
14313 // Catch shift-by-constant.
14314 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14315 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14316 CShAmt->getZExtValue(), DAG);
14318 // Change opcode to non-immediate version
14320 default: llvm_unreachable("Unknown target vector shift node");
14321 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14322 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14323 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14326 // Need to build a vector containing shift amount
14327 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
14330 ShOps[1] = DAG.getConstant(0, MVT::i32);
14331 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
14332 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
14334 // The return type has to be a 128-bit type with the same element
14335 // type as the input type.
14336 MVT EltVT = VT.getVectorElementType();
14337 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14339 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14340 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14343 /// \brief Return (vselect \p Mask, \p Op, \p PreservedSrc) along with the
14344 /// necessary casting for \p Mask when lowering masking intrinsics.
14345 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14346 SDValue PreservedSrc, SelectionDAG &DAG) {
14347 EVT VT = Op.getValueType();
14348 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14349 MVT::i1, VT.getVectorNumElements());
14352 assert(MaskVT.isSimple() && "invalid mask type");
14353 return DAG.getNode(ISD::VSELECT, dl, VT,
14354 DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask),
14358 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
14360 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14361 case Intrinsic::x86_fma_vfmadd_ps:
14362 case Intrinsic::x86_fma_vfmadd_pd:
14363 case Intrinsic::x86_fma_vfmadd_ps_256:
14364 case Intrinsic::x86_fma_vfmadd_pd_256:
14365 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
14366 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
14367 return X86ISD::FMADD;
14368 case Intrinsic::x86_fma_vfmsub_ps:
14369 case Intrinsic::x86_fma_vfmsub_pd:
14370 case Intrinsic::x86_fma_vfmsub_ps_256:
14371 case Intrinsic::x86_fma_vfmsub_pd_256:
14372 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
14373 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
14374 return X86ISD::FMSUB;
14375 case Intrinsic::x86_fma_vfnmadd_ps:
14376 case Intrinsic::x86_fma_vfnmadd_pd:
14377 case Intrinsic::x86_fma_vfnmadd_ps_256:
14378 case Intrinsic::x86_fma_vfnmadd_pd_256:
14379 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
14380 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
14381 return X86ISD::FNMADD;
14382 case Intrinsic::x86_fma_vfnmsub_ps:
14383 case Intrinsic::x86_fma_vfnmsub_pd:
14384 case Intrinsic::x86_fma_vfnmsub_ps_256:
14385 case Intrinsic::x86_fma_vfnmsub_pd_256:
14386 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
14387 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
14388 return X86ISD::FNMSUB;
14389 case Intrinsic::x86_fma_vfmaddsub_ps:
14390 case Intrinsic::x86_fma_vfmaddsub_pd:
14391 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14392 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14393 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
14394 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
14395 return X86ISD::FMADDSUB;
14396 case Intrinsic::x86_fma_vfmsubadd_ps:
14397 case Intrinsic::x86_fma_vfmsubadd_pd:
14398 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14399 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14400 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
14401 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
14402 return X86ISD::FMSUBADD;
14406 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
14408 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14410 default: return SDValue(); // Don't custom lower most intrinsics.
14411 // Comparison intrinsics.
14412 case Intrinsic::x86_sse_comieq_ss:
14413 case Intrinsic::x86_sse_comilt_ss:
14414 case Intrinsic::x86_sse_comile_ss:
14415 case Intrinsic::x86_sse_comigt_ss:
14416 case Intrinsic::x86_sse_comige_ss:
14417 case Intrinsic::x86_sse_comineq_ss:
14418 case Intrinsic::x86_sse_ucomieq_ss:
14419 case Intrinsic::x86_sse_ucomilt_ss:
14420 case Intrinsic::x86_sse_ucomile_ss:
14421 case Intrinsic::x86_sse_ucomigt_ss:
14422 case Intrinsic::x86_sse_ucomige_ss:
14423 case Intrinsic::x86_sse_ucomineq_ss:
14424 case Intrinsic::x86_sse2_comieq_sd:
14425 case Intrinsic::x86_sse2_comilt_sd:
14426 case Intrinsic::x86_sse2_comile_sd:
14427 case Intrinsic::x86_sse2_comigt_sd:
14428 case Intrinsic::x86_sse2_comige_sd:
14429 case Intrinsic::x86_sse2_comineq_sd:
14430 case Intrinsic::x86_sse2_ucomieq_sd:
14431 case Intrinsic::x86_sse2_ucomilt_sd:
14432 case Intrinsic::x86_sse2_ucomile_sd:
14433 case Intrinsic::x86_sse2_ucomigt_sd:
14434 case Intrinsic::x86_sse2_ucomige_sd:
14435 case Intrinsic::x86_sse2_ucomineq_sd: {
14439 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14440 case Intrinsic::x86_sse_comieq_ss:
14441 case Intrinsic::x86_sse2_comieq_sd:
14442 Opc = X86ISD::COMI;
14445 case Intrinsic::x86_sse_comilt_ss:
14446 case Intrinsic::x86_sse2_comilt_sd:
14447 Opc = X86ISD::COMI;
14450 case Intrinsic::x86_sse_comile_ss:
14451 case Intrinsic::x86_sse2_comile_sd:
14452 Opc = X86ISD::COMI;
14455 case Intrinsic::x86_sse_comigt_ss:
14456 case Intrinsic::x86_sse2_comigt_sd:
14457 Opc = X86ISD::COMI;
14460 case Intrinsic::x86_sse_comige_ss:
14461 case Intrinsic::x86_sse2_comige_sd:
14462 Opc = X86ISD::COMI;
14465 case Intrinsic::x86_sse_comineq_ss:
14466 case Intrinsic::x86_sse2_comineq_sd:
14467 Opc = X86ISD::COMI;
14470 case Intrinsic::x86_sse_ucomieq_ss:
14471 case Intrinsic::x86_sse2_ucomieq_sd:
14472 Opc = X86ISD::UCOMI;
14475 case Intrinsic::x86_sse_ucomilt_ss:
14476 case Intrinsic::x86_sse2_ucomilt_sd:
14477 Opc = X86ISD::UCOMI;
14480 case Intrinsic::x86_sse_ucomile_ss:
14481 case Intrinsic::x86_sse2_ucomile_sd:
14482 Opc = X86ISD::UCOMI;
14485 case Intrinsic::x86_sse_ucomigt_ss:
14486 case Intrinsic::x86_sse2_ucomigt_sd:
14487 Opc = X86ISD::UCOMI;
14490 case Intrinsic::x86_sse_ucomige_ss:
14491 case Intrinsic::x86_sse2_ucomige_sd:
14492 Opc = X86ISD::UCOMI;
14495 case Intrinsic::x86_sse_ucomineq_ss:
14496 case Intrinsic::x86_sse2_ucomineq_sd:
14497 Opc = X86ISD::UCOMI;
14502 SDValue LHS = Op.getOperand(1);
14503 SDValue RHS = Op.getOperand(2);
14504 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14505 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14506 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
14507 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14508 DAG.getConstant(X86CC, MVT::i8), Cond);
14509 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14512 // Arithmetic intrinsics.
14513 case Intrinsic::x86_sse2_pmulu_dq:
14514 case Intrinsic::x86_avx2_pmulu_dq:
14515 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14516 Op.getOperand(1), Op.getOperand(2));
14518 case Intrinsic::x86_sse41_pmuldq:
14519 case Intrinsic::x86_avx2_pmul_dq:
14520 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14521 Op.getOperand(1), Op.getOperand(2));
14523 case Intrinsic::x86_sse2_pmulhu_w:
14524 case Intrinsic::x86_avx2_pmulhu_w:
14525 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14526 Op.getOperand(1), Op.getOperand(2));
14528 case Intrinsic::x86_sse2_pmulh_w:
14529 case Intrinsic::x86_avx2_pmulh_w:
14530 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14531 Op.getOperand(1), Op.getOperand(2));
14533 // SSE2/AVX2 sub with unsigned saturation intrinsics
14534 case Intrinsic::x86_sse2_psubus_b:
14535 case Intrinsic::x86_sse2_psubus_w:
14536 case Intrinsic::x86_avx2_psubus_b:
14537 case Intrinsic::x86_avx2_psubus_w:
14538 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
14539 Op.getOperand(1), Op.getOperand(2));
14541 // SSE3/AVX horizontal add/sub intrinsics
14542 case Intrinsic::x86_sse3_hadd_ps:
14543 case Intrinsic::x86_sse3_hadd_pd:
14544 case Intrinsic::x86_avx_hadd_ps_256:
14545 case Intrinsic::x86_avx_hadd_pd_256:
14546 case Intrinsic::x86_sse3_hsub_ps:
14547 case Intrinsic::x86_sse3_hsub_pd:
14548 case Intrinsic::x86_avx_hsub_ps_256:
14549 case Intrinsic::x86_avx_hsub_pd_256:
14550 case Intrinsic::x86_ssse3_phadd_w_128:
14551 case Intrinsic::x86_ssse3_phadd_d_128:
14552 case Intrinsic::x86_avx2_phadd_w:
14553 case Intrinsic::x86_avx2_phadd_d:
14554 case Intrinsic::x86_ssse3_phsub_w_128:
14555 case Intrinsic::x86_ssse3_phsub_d_128:
14556 case Intrinsic::x86_avx2_phsub_w:
14557 case Intrinsic::x86_avx2_phsub_d: {
14560 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14561 case Intrinsic::x86_sse3_hadd_ps:
14562 case Intrinsic::x86_sse3_hadd_pd:
14563 case Intrinsic::x86_avx_hadd_ps_256:
14564 case Intrinsic::x86_avx_hadd_pd_256:
14565 Opcode = X86ISD::FHADD;
14567 case Intrinsic::x86_sse3_hsub_ps:
14568 case Intrinsic::x86_sse3_hsub_pd:
14569 case Intrinsic::x86_avx_hsub_ps_256:
14570 case Intrinsic::x86_avx_hsub_pd_256:
14571 Opcode = X86ISD::FHSUB;
14573 case Intrinsic::x86_ssse3_phadd_w_128:
14574 case Intrinsic::x86_ssse3_phadd_d_128:
14575 case Intrinsic::x86_avx2_phadd_w:
14576 case Intrinsic::x86_avx2_phadd_d:
14577 Opcode = X86ISD::HADD;
14579 case Intrinsic::x86_ssse3_phsub_w_128:
14580 case Intrinsic::x86_ssse3_phsub_d_128:
14581 case Intrinsic::x86_avx2_phsub_w:
14582 case Intrinsic::x86_avx2_phsub_d:
14583 Opcode = X86ISD::HSUB;
14586 return DAG.getNode(Opcode, dl, Op.getValueType(),
14587 Op.getOperand(1), Op.getOperand(2));
14590 // SSE2/SSE41/AVX2 integer max/min intrinsics.
14591 case Intrinsic::x86_sse2_pmaxu_b:
14592 case Intrinsic::x86_sse41_pmaxuw:
14593 case Intrinsic::x86_sse41_pmaxud:
14594 case Intrinsic::x86_avx2_pmaxu_b:
14595 case Intrinsic::x86_avx2_pmaxu_w:
14596 case Intrinsic::x86_avx2_pmaxu_d:
14597 case Intrinsic::x86_sse2_pminu_b:
14598 case Intrinsic::x86_sse41_pminuw:
14599 case Intrinsic::x86_sse41_pminud:
14600 case Intrinsic::x86_avx2_pminu_b:
14601 case Intrinsic::x86_avx2_pminu_w:
14602 case Intrinsic::x86_avx2_pminu_d:
14603 case Intrinsic::x86_sse41_pmaxsb:
14604 case Intrinsic::x86_sse2_pmaxs_w:
14605 case Intrinsic::x86_sse41_pmaxsd:
14606 case Intrinsic::x86_avx2_pmaxs_b:
14607 case Intrinsic::x86_avx2_pmaxs_w:
14608 case Intrinsic::x86_avx2_pmaxs_d:
14609 case Intrinsic::x86_sse41_pminsb:
14610 case Intrinsic::x86_sse2_pmins_w:
14611 case Intrinsic::x86_sse41_pminsd:
14612 case Intrinsic::x86_avx2_pmins_b:
14613 case Intrinsic::x86_avx2_pmins_w:
14614 case Intrinsic::x86_avx2_pmins_d: {
14617 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14618 case Intrinsic::x86_sse2_pmaxu_b:
14619 case Intrinsic::x86_sse41_pmaxuw:
14620 case Intrinsic::x86_sse41_pmaxud:
14621 case Intrinsic::x86_avx2_pmaxu_b:
14622 case Intrinsic::x86_avx2_pmaxu_w:
14623 case Intrinsic::x86_avx2_pmaxu_d:
14624 Opcode = X86ISD::UMAX;
14626 case Intrinsic::x86_sse2_pminu_b:
14627 case Intrinsic::x86_sse41_pminuw:
14628 case Intrinsic::x86_sse41_pminud:
14629 case Intrinsic::x86_avx2_pminu_b:
14630 case Intrinsic::x86_avx2_pminu_w:
14631 case Intrinsic::x86_avx2_pminu_d:
14632 Opcode = X86ISD::UMIN;
14634 case Intrinsic::x86_sse41_pmaxsb:
14635 case Intrinsic::x86_sse2_pmaxs_w:
14636 case Intrinsic::x86_sse41_pmaxsd:
14637 case Intrinsic::x86_avx2_pmaxs_b:
14638 case Intrinsic::x86_avx2_pmaxs_w:
14639 case Intrinsic::x86_avx2_pmaxs_d:
14640 Opcode = X86ISD::SMAX;
14642 case Intrinsic::x86_sse41_pminsb:
14643 case Intrinsic::x86_sse2_pmins_w:
14644 case Intrinsic::x86_sse41_pminsd:
14645 case Intrinsic::x86_avx2_pmins_b:
14646 case Intrinsic::x86_avx2_pmins_w:
14647 case Intrinsic::x86_avx2_pmins_d:
14648 Opcode = X86ISD::SMIN;
14651 return DAG.getNode(Opcode, dl, Op.getValueType(),
14652 Op.getOperand(1), Op.getOperand(2));
14655 // SSE/SSE2/AVX floating point max/min intrinsics.
14656 case Intrinsic::x86_sse_max_ps:
14657 case Intrinsic::x86_sse2_max_pd:
14658 case Intrinsic::x86_avx_max_ps_256:
14659 case Intrinsic::x86_avx_max_pd_256:
14660 case Intrinsic::x86_sse_min_ps:
14661 case Intrinsic::x86_sse2_min_pd:
14662 case Intrinsic::x86_avx_min_ps_256:
14663 case Intrinsic::x86_avx_min_pd_256: {
14666 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14667 case Intrinsic::x86_sse_max_ps:
14668 case Intrinsic::x86_sse2_max_pd:
14669 case Intrinsic::x86_avx_max_ps_256:
14670 case Intrinsic::x86_avx_max_pd_256:
14671 Opcode = X86ISD::FMAX;
14673 case Intrinsic::x86_sse_min_ps:
14674 case Intrinsic::x86_sse2_min_pd:
14675 case Intrinsic::x86_avx_min_ps_256:
14676 case Intrinsic::x86_avx_min_pd_256:
14677 Opcode = X86ISD::FMIN;
14680 return DAG.getNode(Opcode, dl, Op.getValueType(),
14681 Op.getOperand(1), Op.getOperand(2));
14684 // AVX2 variable shift intrinsics
14685 case Intrinsic::x86_avx2_psllv_d:
14686 case Intrinsic::x86_avx2_psllv_q:
14687 case Intrinsic::x86_avx2_psllv_d_256:
14688 case Intrinsic::x86_avx2_psllv_q_256:
14689 case Intrinsic::x86_avx2_psrlv_d:
14690 case Intrinsic::x86_avx2_psrlv_q:
14691 case Intrinsic::x86_avx2_psrlv_d_256:
14692 case Intrinsic::x86_avx2_psrlv_q_256:
14693 case Intrinsic::x86_avx2_psrav_d:
14694 case Intrinsic::x86_avx2_psrav_d_256: {
14697 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14698 case Intrinsic::x86_avx2_psllv_d:
14699 case Intrinsic::x86_avx2_psllv_q:
14700 case Intrinsic::x86_avx2_psllv_d_256:
14701 case Intrinsic::x86_avx2_psllv_q_256:
14704 case Intrinsic::x86_avx2_psrlv_d:
14705 case Intrinsic::x86_avx2_psrlv_q:
14706 case Intrinsic::x86_avx2_psrlv_d_256:
14707 case Intrinsic::x86_avx2_psrlv_q_256:
14710 case Intrinsic::x86_avx2_psrav_d:
14711 case Intrinsic::x86_avx2_psrav_d_256:
14715 return DAG.getNode(Opcode, dl, Op.getValueType(),
14716 Op.getOperand(1), Op.getOperand(2));
14719 case Intrinsic::x86_sse2_packssdw_128:
14720 case Intrinsic::x86_sse2_packsswb_128:
14721 case Intrinsic::x86_avx2_packssdw:
14722 case Intrinsic::x86_avx2_packsswb:
14723 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14724 Op.getOperand(1), Op.getOperand(2));
14726 case Intrinsic::x86_sse2_packuswb_128:
14727 case Intrinsic::x86_sse41_packusdw:
14728 case Intrinsic::x86_avx2_packuswb:
14729 case Intrinsic::x86_avx2_packusdw:
14730 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14731 Op.getOperand(1), Op.getOperand(2));
14733 case Intrinsic::x86_ssse3_pshuf_b_128:
14734 case Intrinsic::x86_avx2_pshuf_b:
14735 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14736 Op.getOperand(1), Op.getOperand(2));
14738 case Intrinsic::x86_sse2_pshuf_d:
14739 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14740 Op.getOperand(1), Op.getOperand(2));
14742 case Intrinsic::x86_sse2_pshufl_w:
14743 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14744 Op.getOperand(1), Op.getOperand(2));
14746 case Intrinsic::x86_sse2_pshufh_w:
14747 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14748 Op.getOperand(1), Op.getOperand(2));
14750 case Intrinsic::x86_ssse3_psign_b_128:
14751 case Intrinsic::x86_ssse3_psign_w_128:
14752 case Intrinsic::x86_ssse3_psign_d_128:
14753 case Intrinsic::x86_avx2_psign_b:
14754 case Intrinsic::x86_avx2_psign_w:
14755 case Intrinsic::x86_avx2_psign_d:
14756 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14757 Op.getOperand(1), Op.getOperand(2));
14759 case Intrinsic::x86_sse41_insertps:
14760 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
14761 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14763 case Intrinsic::x86_avx_vperm2f128_ps_256:
14764 case Intrinsic::x86_avx_vperm2f128_pd_256:
14765 case Intrinsic::x86_avx_vperm2f128_si_256:
14766 case Intrinsic::x86_avx2_vperm2i128:
14767 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
14768 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14770 case Intrinsic::x86_avx2_permd:
14771 case Intrinsic::x86_avx2_permps:
14772 // Operands intentionally swapped. Mask is last operand to intrinsic,
14773 // but second operand for node/instruction.
14774 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14775 Op.getOperand(2), Op.getOperand(1));
14777 case Intrinsic::x86_sse_sqrt_ps:
14778 case Intrinsic::x86_sse2_sqrt_pd:
14779 case Intrinsic::x86_avx_sqrt_ps_256:
14780 case Intrinsic::x86_avx_sqrt_pd_256:
14781 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
14783 case Intrinsic::x86_avx512_mask_valign_q_512:
14784 case Intrinsic::x86_avx512_mask_valign_d_512:
14785 // Vector source operands are swapped.
14786 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14787 Op.getValueType(), Op.getOperand(2),
14790 Op.getOperand(5), Op.getOperand(4), DAG);
14792 // ptest and testp intrinsics. The intrinsic these come from are designed to
14793 // return an integer value, not just an instruction so lower it to the ptest
14794 // or testp pattern and a setcc for the result.
14795 case Intrinsic::x86_sse41_ptestz:
14796 case Intrinsic::x86_sse41_ptestc:
14797 case Intrinsic::x86_sse41_ptestnzc:
14798 case Intrinsic::x86_avx_ptestz_256:
14799 case Intrinsic::x86_avx_ptestc_256:
14800 case Intrinsic::x86_avx_ptestnzc_256:
14801 case Intrinsic::x86_avx_vtestz_ps:
14802 case Intrinsic::x86_avx_vtestc_ps:
14803 case Intrinsic::x86_avx_vtestnzc_ps:
14804 case Intrinsic::x86_avx_vtestz_pd:
14805 case Intrinsic::x86_avx_vtestc_pd:
14806 case Intrinsic::x86_avx_vtestnzc_pd:
14807 case Intrinsic::x86_avx_vtestz_ps_256:
14808 case Intrinsic::x86_avx_vtestc_ps_256:
14809 case Intrinsic::x86_avx_vtestnzc_ps_256:
14810 case Intrinsic::x86_avx_vtestz_pd_256:
14811 case Intrinsic::x86_avx_vtestc_pd_256:
14812 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14813 bool IsTestPacked = false;
14816 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14817 case Intrinsic::x86_avx_vtestz_ps:
14818 case Intrinsic::x86_avx_vtestz_pd:
14819 case Intrinsic::x86_avx_vtestz_ps_256:
14820 case Intrinsic::x86_avx_vtestz_pd_256:
14821 IsTestPacked = true; // Fallthrough
14822 case Intrinsic::x86_sse41_ptestz:
14823 case Intrinsic::x86_avx_ptestz_256:
14825 X86CC = X86::COND_E;
14827 case Intrinsic::x86_avx_vtestc_ps:
14828 case Intrinsic::x86_avx_vtestc_pd:
14829 case Intrinsic::x86_avx_vtestc_ps_256:
14830 case Intrinsic::x86_avx_vtestc_pd_256:
14831 IsTestPacked = true; // Fallthrough
14832 case Intrinsic::x86_sse41_ptestc:
14833 case Intrinsic::x86_avx_ptestc_256:
14835 X86CC = X86::COND_B;
14837 case Intrinsic::x86_avx_vtestnzc_ps:
14838 case Intrinsic::x86_avx_vtestnzc_pd:
14839 case Intrinsic::x86_avx_vtestnzc_ps_256:
14840 case Intrinsic::x86_avx_vtestnzc_pd_256:
14841 IsTestPacked = true; // Fallthrough
14842 case Intrinsic::x86_sse41_ptestnzc:
14843 case Intrinsic::x86_avx_ptestnzc_256:
14845 X86CC = X86::COND_A;
14849 SDValue LHS = Op.getOperand(1);
14850 SDValue RHS = Op.getOperand(2);
14851 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14852 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14853 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14854 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14855 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14857 case Intrinsic::x86_avx512_kortestz_w:
14858 case Intrinsic::x86_avx512_kortestc_w: {
14859 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14860 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14861 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14862 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14863 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14864 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14865 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14868 // SSE/AVX shift intrinsics
14869 case Intrinsic::x86_sse2_psll_w:
14870 case Intrinsic::x86_sse2_psll_d:
14871 case Intrinsic::x86_sse2_psll_q:
14872 case Intrinsic::x86_avx2_psll_w:
14873 case Intrinsic::x86_avx2_psll_d:
14874 case Intrinsic::x86_avx2_psll_q:
14875 case Intrinsic::x86_sse2_psrl_w:
14876 case Intrinsic::x86_sse2_psrl_d:
14877 case Intrinsic::x86_sse2_psrl_q:
14878 case Intrinsic::x86_avx2_psrl_w:
14879 case Intrinsic::x86_avx2_psrl_d:
14880 case Intrinsic::x86_avx2_psrl_q:
14881 case Intrinsic::x86_sse2_psra_w:
14882 case Intrinsic::x86_sse2_psra_d:
14883 case Intrinsic::x86_avx2_psra_w:
14884 case Intrinsic::x86_avx2_psra_d: {
14887 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14888 case Intrinsic::x86_sse2_psll_w:
14889 case Intrinsic::x86_sse2_psll_d:
14890 case Intrinsic::x86_sse2_psll_q:
14891 case Intrinsic::x86_avx2_psll_w:
14892 case Intrinsic::x86_avx2_psll_d:
14893 case Intrinsic::x86_avx2_psll_q:
14894 Opcode = X86ISD::VSHL;
14896 case Intrinsic::x86_sse2_psrl_w:
14897 case Intrinsic::x86_sse2_psrl_d:
14898 case Intrinsic::x86_sse2_psrl_q:
14899 case Intrinsic::x86_avx2_psrl_w:
14900 case Intrinsic::x86_avx2_psrl_d:
14901 case Intrinsic::x86_avx2_psrl_q:
14902 Opcode = X86ISD::VSRL;
14904 case Intrinsic::x86_sse2_psra_w:
14905 case Intrinsic::x86_sse2_psra_d:
14906 case Intrinsic::x86_avx2_psra_w:
14907 case Intrinsic::x86_avx2_psra_d:
14908 Opcode = X86ISD::VSRA;
14911 return DAG.getNode(Opcode, dl, Op.getValueType(),
14912 Op.getOperand(1), Op.getOperand(2));
14915 // SSE/AVX immediate shift intrinsics
14916 case Intrinsic::x86_sse2_pslli_w:
14917 case Intrinsic::x86_sse2_pslli_d:
14918 case Intrinsic::x86_sse2_pslli_q:
14919 case Intrinsic::x86_avx2_pslli_w:
14920 case Intrinsic::x86_avx2_pslli_d:
14921 case Intrinsic::x86_avx2_pslli_q:
14922 case Intrinsic::x86_sse2_psrli_w:
14923 case Intrinsic::x86_sse2_psrli_d:
14924 case Intrinsic::x86_sse2_psrli_q:
14925 case Intrinsic::x86_avx2_psrli_w:
14926 case Intrinsic::x86_avx2_psrli_d:
14927 case Intrinsic::x86_avx2_psrli_q:
14928 case Intrinsic::x86_sse2_psrai_w:
14929 case Intrinsic::x86_sse2_psrai_d:
14930 case Intrinsic::x86_avx2_psrai_w:
14931 case Intrinsic::x86_avx2_psrai_d: {
14934 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14935 case Intrinsic::x86_sse2_pslli_w:
14936 case Intrinsic::x86_sse2_pslli_d:
14937 case Intrinsic::x86_sse2_pslli_q:
14938 case Intrinsic::x86_avx2_pslli_w:
14939 case Intrinsic::x86_avx2_pslli_d:
14940 case Intrinsic::x86_avx2_pslli_q:
14941 Opcode = X86ISD::VSHLI;
14943 case Intrinsic::x86_sse2_psrli_w:
14944 case Intrinsic::x86_sse2_psrli_d:
14945 case Intrinsic::x86_sse2_psrli_q:
14946 case Intrinsic::x86_avx2_psrli_w:
14947 case Intrinsic::x86_avx2_psrli_d:
14948 case Intrinsic::x86_avx2_psrli_q:
14949 Opcode = X86ISD::VSRLI;
14951 case Intrinsic::x86_sse2_psrai_w:
14952 case Intrinsic::x86_sse2_psrai_d:
14953 case Intrinsic::x86_avx2_psrai_w:
14954 case Intrinsic::x86_avx2_psrai_d:
14955 Opcode = X86ISD::VSRAI;
14958 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
14959 Op.getOperand(1), Op.getOperand(2), DAG);
14962 case Intrinsic::x86_sse42_pcmpistria128:
14963 case Intrinsic::x86_sse42_pcmpestria128:
14964 case Intrinsic::x86_sse42_pcmpistric128:
14965 case Intrinsic::x86_sse42_pcmpestric128:
14966 case Intrinsic::x86_sse42_pcmpistrio128:
14967 case Intrinsic::x86_sse42_pcmpestrio128:
14968 case Intrinsic::x86_sse42_pcmpistris128:
14969 case Intrinsic::x86_sse42_pcmpestris128:
14970 case Intrinsic::x86_sse42_pcmpistriz128:
14971 case Intrinsic::x86_sse42_pcmpestriz128: {
14975 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14976 case Intrinsic::x86_sse42_pcmpistria128:
14977 Opcode = X86ISD::PCMPISTRI;
14978 X86CC = X86::COND_A;
14980 case Intrinsic::x86_sse42_pcmpestria128:
14981 Opcode = X86ISD::PCMPESTRI;
14982 X86CC = X86::COND_A;
14984 case Intrinsic::x86_sse42_pcmpistric128:
14985 Opcode = X86ISD::PCMPISTRI;
14986 X86CC = X86::COND_B;
14988 case Intrinsic::x86_sse42_pcmpestric128:
14989 Opcode = X86ISD::PCMPESTRI;
14990 X86CC = X86::COND_B;
14992 case Intrinsic::x86_sse42_pcmpistrio128:
14993 Opcode = X86ISD::PCMPISTRI;
14994 X86CC = X86::COND_O;
14996 case Intrinsic::x86_sse42_pcmpestrio128:
14997 Opcode = X86ISD::PCMPESTRI;
14998 X86CC = X86::COND_O;
15000 case Intrinsic::x86_sse42_pcmpistris128:
15001 Opcode = X86ISD::PCMPISTRI;
15002 X86CC = X86::COND_S;
15004 case Intrinsic::x86_sse42_pcmpestris128:
15005 Opcode = X86ISD::PCMPESTRI;
15006 X86CC = X86::COND_S;
15008 case Intrinsic::x86_sse42_pcmpistriz128:
15009 Opcode = X86ISD::PCMPISTRI;
15010 X86CC = X86::COND_E;
15012 case Intrinsic::x86_sse42_pcmpestriz128:
15013 Opcode = X86ISD::PCMPESTRI;
15014 X86CC = X86::COND_E;
15017 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15018 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15019 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15020 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15021 DAG.getConstant(X86CC, MVT::i8),
15022 SDValue(PCMP.getNode(), 1));
15023 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15026 case Intrinsic::x86_sse42_pcmpistri128:
15027 case Intrinsic::x86_sse42_pcmpestri128: {
15029 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15030 Opcode = X86ISD::PCMPISTRI;
15032 Opcode = X86ISD::PCMPESTRI;
15034 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15035 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15036 return DAG.getNode(Opcode, dl, VTs, NewOps);
15039 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
15040 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
15041 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
15042 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
15043 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
15044 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
15045 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
15046 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
15047 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
15048 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
15049 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
15050 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
15051 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
15052 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
15053 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
15054 dl, Op.getValueType(),
15058 Op.getOperand(4), Op.getOperand(1), DAG);
15063 case Intrinsic::x86_fma_vfmadd_ps:
15064 case Intrinsic::x86_fma_vfmadd_pd:
15065 case Intrinsic::x86_fma_vfmsub_ps:
15066 case Intrinsic::x86_fma_vfmsub_pd:
15067 case Intrinsic::x86_fma_vfnmadd_ps:
15068 case Intrinsic::x86_fma_vfnmadd_pd:
15069 case Intrinsic::x86_fma_vfnmsub_ps:
15070 case Intrinsic::x86_fma_vfnmsub_pd:
15071 case Intrinsic::x86_fma_vfmaddsub_ps:
15072 case Intrinsic::x86_fma_vfmaddsub_pd:
15073 case Intrinsic::x86_fma_vfmsubadd_ps:
15074 case Intrinsic::x86_fma_vfmsubadd_pd:
15075 case Intrinsic::x86_fma_vfmadd_ps_256:
15076 case Intrinsic::x86_fma_vfmadd_pd_256:
15077 case Intrinsic::x86_fma_vfmsub_ps_256:
15078 case Intrinsic::x86_fma_vfmsub_pd_256:
15079 case Intrinsic::x86_fma_vfnmadd_ps_256:
15080 case Intrinsic::x86_fma_vfnmadd_pd_256:
15081 case Intrinsic::x86_fma_vfnmsub_ps_256:
15082 case Intrinsic::x86_fma_vfnmsub_pd_256:
15083 case Intrinsic::x86_fma_vfmaddsub_ps_256:
15084 case Intrinsic::x86_fma_vfmaddsub_pd_256:
15085 case Intrinsic::x86_fma_vfmsubadd_ps_256:
15086 case Intrinsic::x86_fma_vfmsubadd_pd_256:
15087 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
15088 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
15092 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15093 SDValue Src, SDValue Mask, SDValue Base,
15094 SDValue Index, SDValue ScaleOp, SDValue Chain,
15095 const X86Subtarget * Subtarget) {
15097 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15098 assert(C && "Invalid scale type");
15099 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15100 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15101 Index.getSimpleValueType().getVectorNumElements());
15103 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15105 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15107 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15108 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15109 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15110 SDValue Segment = DAG.getRegister(0, MVT::i32);
15111 if (Src.getOpcode() == ISD::UNDEF)
15112 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15113 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15114 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15115 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15116 return DAG.getMergeValues(RetOps, dl);
15119 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15120 SDValue Src, SDValue Mask, SDValue Base,
15121 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15123 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15124 assert(C && "Invalid scale type");
15125 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15126 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15127 SDValue Segment = DAG.getRegister(0, MVT::i32);
15128 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15129 Index.getSimpleValueType().getVectorNumElements());
15131 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15133 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15135 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15136 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15137 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15138 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15139 return SDValue(Res, 1);
15142 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15143 SDValue Mask, SDValue Base, SDValue Index,
15144 SDValue ScaleOp, SDValue Chain) {
15146 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15147 assert(C && "Invalid scale type");
15148 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15149 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15150 SDValue Segment = DAG.getRegister(0, MVT::i32);
15152 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15154 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15156 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15158 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15159 //SDVTList VTs = DAG.getVTList(MVT::Other);
15160 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15161 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15162 return SDValue(Res, 0);
15165 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15166 // read performance monitor counters (x86_rdpmc).
15167 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15168 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15169 SmallVectorImpl<SDValue> &Results) {
15170 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15171 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15174 // The ECX register is used to select the index of the performance counter
15176 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15178 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15180 // Reads the content of a 64-bit performance counter and returns it in the
15181 // registers EDX:EAX.
15182 if (Subtarget->is64Bit()) {
15183 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15184 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15187 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15188 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15191 Chain = HI.getValue(1);
15193 if (Subtarget->is64Bit()) {
15194 // The EAX register is loaded with the low-order 32 bits. The EDX register
15195 // is loaded with the supported high-order bits of the counter.
15196 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15197 DAG.getConstant(32, MVT::i8));
15198 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15199 Results.push_back(Chain);
15203 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15204 SDValue Ops[] = { LO, HI };
15205 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15206 Results.push_back(Pair);
15207 Results.push_back(Chain);
15210 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15211 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15212 // also used to custom lower READCYCLECOUNTER nodes.
15213 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15214 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15215 SmallVectorImpl<SDValue> &Results) {
15216 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15217 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15220 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15221 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15222 // and the EAX register is loaded with the low-order 32 bits.
15223 if (Subtarget->is64Bit()) {
15224 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15225 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15228 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15229 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15232 SDValue Chain = HI.getValue(1);
15234 if (Opcode == X86ISD::RDTSCP_DAG) {
15235 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15237 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15238 // the ECX register. Add 'ecx' explicitly to the chain.
15239 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15241 // Explicitly store the content of ECX at the location passed in input
15242 // to the 'rdtscp' intrinsic.
15243 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15244 MachinePointerInfo(), false, false, 0);
15247 if (Subtarget->is64Bit()) {
15248 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15249 // the EAX register is loaded with the low-order 32 bits.
15250 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15251 DAG.getConstant(32, MVT::i8));
15252 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15253 Results.push_back(Chain);
15257 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15258 SDValue Ops[] = { LO, HI };
15259 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15260 Results.push_back(Pair);
15261 Results.push_back(Chain);
15264 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15265 SelectionDAG &DAG) {
15266 SmallVector<SDValue, 2> Results;
15268 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15270 return DAG.getMergeValues(Results, DL);
15273 enum IntrinsicType {
15274 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
15277 struct IntrinsicData {
15278 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
15279 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
15280 IntrinsicType Type;
15285 std::map < unsigned, IntrinsicData> IntrMap;
15286 static void InitIntinsicsMap() {
15287 static bool Initialized = false;
15290 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
15291 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
15292 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
15293 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
15294 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
15295 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
15296 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
15297 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
15298 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
15299 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
15300 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
15301 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
15302 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
15303 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
15304 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
15305 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
15306 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
15307 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
15309 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
15310 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
15311 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
15312 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
15313 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
15314 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
15315 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
15316 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
15317 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
15318 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
15319 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
15320 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
15321 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
15322 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
15323 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
15324 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
15326 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
15327 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
15328 X86::VGATHERPF1QPSm)));
15329 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
15330 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
15331 X86::VGATHERPF1QPDm)));
15332 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
15333 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
15334 X86::VGATHERPF1DPDm)));
15335 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
15336 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
15337 X86::VGATHERPF1DPSm)));
15338 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
15339 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
15340 X86::VSCATTERPF1QPSm)));
15341 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
15342 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
15343 X86::VSCATTERPF1QPDm)));
15344 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
15345 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
15346 X86::VSCATTERPF1DPDm)));
15347 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
15348 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
15349 X86::VSCATTERPF1DPSm)));
15350 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
15351 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15352 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
15353 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15354 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
15355 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
15356 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
15357 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15358 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
15359 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15360 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
15361 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
15362 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
15363 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
15364 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
15365 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
15366 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
15367 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
15368 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
15369 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
15370 Initialized = true;
15373 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15374 SelectionDAG &DAG) {
15375 InitIntinsicsMap();
15376 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15377 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
15378 if (itr == IntrMap.end())
15382 IntrinsicData Intr = itr->second;
15383 switch(Intr.Type) {
15386 // Emit the node with the right value type.
15387 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15388 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
15390 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15391 // Otherwise return the value from Rand, which is always 0, casted to i32.
15392 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15393 DAG.getConstant(1, Op->getValueType(1)),
15394 DAG.getConstant(X86::COND_B, MVT::i32),
15395 SDValue(Result.getNode(), 1) };
15396 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15397 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15400 // Return { result, isValid, chain }.
15401 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15402 SDValue(Result.getNode(), 2));
15405 //gather(v1, mask, index, base, scale);
15406 SDValue Chain = Op.getOperand(0);
15407 SDValue Src = Op.getOperand(2);
15408 SDValue Base = Op.getOperand(3);
15409 SDValue Index = Op.getOperand(4);
15410 SDValue Mask = Op.getOperand(5);
15411 SDValue Scale = Op.getOperand(6);
15412 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15416 //scatter(base, mask, index, v1, scale);
15417 SDValue Chain = Op.getOperand(0);
15418 SDValue Base = Op.getOperand(2);
15419 SDValue Mask = Op.getOperand(3);
15420 SDValue Index = Op.getOperand(4);
15421 SDValue Src = Op.getOperand(5);
15422 SDValue Scale = Op.getOperand(6);
15423 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15426 SDValue Hint = Op.getOperand(6);
15428 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15429 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15430 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15431 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
15432 SDValue Chain = Op.getOperand(0);
15433 SDValue Mask = Op.getOperand(2);
15434 SDValue Index = Op.getOperand(3);
15435 SDValue Base = Op.getOperand(4);
15436 SDValue Scale = Op.getOperand(5);
15437 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15439 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15441 SmallVector<SDValue, 2> Results;
15442 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
15443 return DAG.getMergeValues(Results, dl);
15445 // Read Performance Monitoring Counters.
15447 SmallVector<SDValue, 2> Results;
15448 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15449 return DAG.getMergeValues(Results, dl);
15451 // XTEST intrinsics.
15453 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15454 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
15455 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15456 DAG.getConstant(X86::COND_NE, MVT::i8),
15458 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15459 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15460 Ret, SDValue(InTrans.getNode(), 1));
15463 llvm_unreachable("Unknown Intrinsic Type");
15466 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15467 SelectionDAG &DAG) const {
15468 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15469 MFI->setReturnAddressIsTaken(true);
15471 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15474 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15476 EVT PtrVT = getPointerTy();
15479 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15480 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15481 DAG.getSubtarget().getRegisterInfo());
15482 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15483 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15484 DAG.getNode(ISD::ADD, dl, PtrVT,
15485 FrameAddr, Offset),
15486 MachinePointerInfo(), false, false, false, 0);
15489 // Just load the return address.
15490 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15491 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15492 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15495 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15496 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15497 MFI->setFrameAddressIsTaken(true);
15499 EVT VT = Op.getValueType();
15500 SDLoc dl(Op); // FIXME probably not meaningful
15501 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15502 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15503 DAG.getSubtarget().getRegisterInfo());
15504 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15505 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15506 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15507 "Invalid Frame Register!");
15508 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15510 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15511 MachinePointerInfo(),
15512 false, false, false, 0);
15516 // FIXME? Maybe this could be a TableGen attribute on some registers and
15517 // this table could be generated automatically from RegInfo.
15518 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15520 unsigned Reg = StringSwitch<unsigned>(RegName)
15521 .Case("esp", X86::ESP)
15522 .Case("rsp", X86::RSP)
15526 report_fatal_error("Invalid register name global variable");
15529 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15530 SelectionDAG &DAG) const {
15531 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15532 DAG.getSubtarget().getRegisterInfo());
15533 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15536 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15537 SDValue Chain = Op.getOperand(0);
15538 SDValue Offset = Op.getOperand(1);
15539 SDValue Handler = Op.getOperand(2);
15542 EVT PtrVT = getPointerTy();
15543 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15544 DAG.getSubtarget().getRegisterInfo());
15545 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15546 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15547 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15548 "Invalid Frame Register!");
15549 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15550 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15552 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15553 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15554 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15555 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15557 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15559 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15560 DAG.getRegister(StoreAddrReg, PtrVT));
15563 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15564 SelectionDAG &DAG) const {
15566 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15567 DAG.getVTList(MVT::i32, MVT::Other),
15568 Op.getOperand(0), Op.getOperand(1));
15571 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15572 SelectionDAG &DAG) const {
15574 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15575 Op.getOperand(0), Op.getOperand(1));
15578 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15579 return Op.getOperand(0);
15582 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15583 SelectionDAG &DAG) const {
15584 SDValue Root = Op.getOperand(0);
15585 SDValue Trmp = Op.getOperand(1); // trampoline
15586 SDValue FPtr = Op.getOperand(2); // nested function
15587 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15590 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15591 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15593 if (Subtarget->is64Bit()) {
15594 SDValue OutChains[6];
15596 // Large code-model.
15597 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15598 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15600 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15601 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15603 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15605 // Load the pointer to the nested function into R11.
15606 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15607 SDValue Addr = Trmp;
15608 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15609 Addr, MachinePointerInfo(TrmpAddr),
15612 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15613 DAG.getConstant(2, MVT::i64));
15614 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15615 MachinePointerInfo(TrmpAddr, 2),
15618 // Load the 'nest' parameter value into R10.
15619 // R10 is specified in X86CallingConv.td
15620 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15621 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15622 DAG.getConstant(10, MVT::i64));
15623 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15624 Addr, MachinePointerInfo(TrmpAddr, 10),
15627 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15628 DAG.getConstant(12, MVT::i64));
15629 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15630 MachinePointerInfo(TrmpAddr, 12),
15633 // Jump to the nested function.
15634 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15635 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15636 DAG.getConstant(20, MVT::i64));
15637 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15638 Addr, MachinePointerInfo(TrmpAddr, 20),
15641 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15642 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15643 DAG.getConstant(22, MVT::i64));
15644 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15645 MachinePointerInfo(TrmpAddr, 22),
15648 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15650 const Function *Func =
15651 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15652 CallingConv::ID CC = Func->getCallingConv();
15657 llvm_unreachable("Unsupported calling convention");
15658 case CallingConv::C:
15659 case CallingConv::X86_StdCall: {
15660 // Pass 'nest' parameter in ECX.
15661 // Must be kept in sync with X86CallingConv.td
15662 NestReg = X86::ECX;
15664 // Check that ECX wasn't needed by an 'inreg' parameter.
15665 FunctionType *FTy = Func->getFunctionType();
15666 const AttributeSet &Attrs = Func->getAttributes();
15668 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15669 unsigned InRegCount = 0;
15672 for (FunctionType::param_iterator I = FTy->param_begin(),
15673 E = FTy->param_end(); I != E; ++I, ++Idx)
15674 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15675 // FIXME: should only count parameters that are lowered to integers.
15676 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15678 if (InRegCount > 2) {
15679 report_fatal_error("Nest register in use - reduce number of inreg"
15685 case CallingConv::X86_FastCall:
15686 case CallingConv::X86_ThisCall:
15687 case CallingConv::Fast:
15688 // Pass 'nest' parameter in EAX.
15689 // Must be kept in sync with X86CallingConv.td
15690 NestReg = X86::EAX;
15694 SDValue OutChains[4];
15695 SDValue Addr, Disp;
15697 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15698 DAG.getConstant(10, MVT::i32));
15699 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15701 // This is storing the opcode for MOV32ri.
15702 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15703 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15704 OutChains[0] = DAG.getStore(Root, dl,
15705 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15706 Trmp, MachinePointerInfo(TrmpAddr),
15709 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15710 DAG.getConstant(1, MVT::i32));
15711 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15712 MachinePointerInfo(TrmpAddr, 1),
15715 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15716 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15717 DAG.getConstant(5, MVT::i32));
15718 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15719 MachinePointerInfo(TrmpAddr, 5),
15722 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15723 DAG.getConstant(6, MVT::i32));
15724 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15725 MachinePointerInfo(TrmpAddr, 6),
15728 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15732 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15733 SelectionDAG &DAG) const {
15735 The rounding mode is in bits 11:10 of FPSR, and has the following
15737 00 Round to nearest
15742 FLT_ROUNDS, on the other hand, expects the following:
15749 To perform the conversion, we do:
15750 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15753 MachineFunction &MF = DAG.getMachineFunction();
15754 const TargetMachine &TM = MF.getTarget();
15755 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15756 unsigned StackAlignment = TFI.getStackAlignment();
15757 MVT VT = Op.getSimpleValueType();
15760 // Save FP Control Word to stack slot
15761 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15762 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15764 MachineMemOperand *MMO =
15765 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15766 MachineMemOperand::MOStore, 2, 2);
15768 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15769 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15770 DAG.getVTList(MVT::Other),
15771 Ops, MVT::i16, MMO);
15773 // Load FP Control Word from stack slot
15774 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15775 MachinePointerInfo(), false, false, false, 0);
15777 // Transform as necessary
15779 DAG.getNode(ISD::SRL, DL, MVT::i16,
15780 DAG.getNode(ISD::AND, DL, MVT::i16,
15781 CWD, DAG.getConstant(0x800, MVT::i16)),
15782 DAG.getConstant(11, MVT::i8));
15784 DAG.getNode(ISD::SRL, DL, MVT::i16,
15785 DAG.getNode(ISD::AND, DL, MVT::i16,
15786 CWD, DAG.getConstant(0x400, MVT::i16)),
15787 DAG.getConstant(9, MVT::i8));
15790 DAG.getNode(ISD::AND, DL, MVT::i16,
15791 DAG.getNode(ISD::ADD, DL, MVT::i16,
15792 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15793 DAG.getConstant(1, MVT::i16)),
15794 DAG.getConstant(3, MVT::i16));
15796 return DAG.getNode((VT.getSizeInBits() < 16 ?
15797 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15800 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15801 MVT VT = Op.getSimpleValueType();
15803 unsigned NumBits = VT.getSizeInBits();
15806 Op = Op.getOperand(0);
15807 if (VT == MVT::i8) {
15808 // Zero extend to i32 since there is not an i8 bsr.
15810 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15813 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15814 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15815 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15817 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15820 DAG.getConstant(NumBits+NumBits-1, OpVT),
15821 DAG.getConstant(X86::COND_E, MVT::i8),
15824 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15826 // Finally xor with NumBits-1.
15827 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15830 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15834 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15835 MVT VT = Op.getSimpleValueType();
15837 unsigned NumBits = VT.getSizeInBits();
15840 Op = Op.getOperand(0);
15841 if (VT == MVT::i8) {
15842 // Zero extend to i32 since there is not an i8 bsr.
15844 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15847 // Issue a bsr (scan bits in reverse).
15848 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15849 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15851 // And xor with NumBits-1.
15852 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15855 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15859 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15860 MVT VT = Op.getSimpleValueType();
15861 unsigned NumBits = VT.getSizeInBits();
15863 Op = Op.getOperand(0);
15865 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15866 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15867 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15869 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15872 DAG.getConstant(NumBits, VT),
15873 DAG.getConstant(X86::COND_E, MVT::i8),
15876 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15879 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15880 // ones, and then concatenate the result back.
15881 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15882 MVT VT = Op.getSimpleValueType();
15884 assert(VT.is256BitVector() && VT.isInteger() &&
15885 "Unsupported value type for operation");
15887 unsigned NumElems = VT.getVectorNumElements();
15890 // Extract the LHS vectors
15891 SDValue LHS = Op.getOperand(0);
15892 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15893 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15895 // Extract the RHS vectors
15896 SDValue RHS = Op.getOperand(1);
15897 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15898 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15900 MVT EltVT = VT.getVectorElementType();
15901 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15903 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15904 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15905 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15908 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15909 assert(Op.getSimpleValueType().is256BitVector() &&
15910 Op.getSimpleValueType().isInteger() &&
15911 "Only handle AVX 256-bit vector integer operation");
15912 return Lower256IntArith(Op, DAG);
15915 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15916 assert(Op.getSimpleValueType().is256BitVector() &&
15917 Op.getSimpleValueType().isInteger() &&
15918 "Only handle AVX 256-bit vector integer operation");
15919 return Lower256IntArith(Op, DAG);
15922 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15923 SelectionDAG &DAG) {
15925 MVT VT = Op.getSimpleValueType();
15927 // Decompose 256-bit ops into smaller 128-bit ops.
15928 if (VT.is256BitVector() && !Subtarget->hasInt256())
15929 return Lower256IntArith(Op, DAG);
15931 SDValue A = Op.getOperand(0);
15932 SDValue B = Op.getOperand(1);
15934 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15935 if (VT == MVT::v4i32) {
15936 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15937 "Should not custom lower when pmuldq is available!");
15939 // Extract the odd parts.
15940 static const int UnpackMask[] = { 1, -1, 3, -1 };
15941 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15942 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15944 // Multiply the even parts.
15945 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15946 // Now multiply odd parts.
15947 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15949 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15950 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15952 // Merge the two vectors back together with a shuffle. This expands into 2
15954 static const int ShufMask[] = { 0, 4, 2, 6 };
15955 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15958 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15959 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15961 // Ahi = psrlqi(a, 32);
15962 // Bhi = psrlqi(b, 32);
15964 // AloBlo = pmuludq(a, b);
15965 // AloBhi = pmuludq(a, Bhi);
15966 // AhiBlo = pmuludq(Ahi, b);
15968 // AloBhi = psllqi(AloBhi, 32);
15969 // AhiBlo = psllqi(AhiBlo, 32);
15970 // return AloBlo + AloBhi + AhiBlo;
15972 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15973 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15975 // Bit cast to 32-bit vectors for MULUDQ
15976 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15977 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15978 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15979 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15980 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15981 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15983 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15984 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15985 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15987 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15988 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15990 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15991 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15994 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15995 assert(Subtarget->isTargetWin64() && "Unexpected target");
15996 EVT VT = Op.getValueType();
15997 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15998 "Unexpected return type for lowering");
16002 switch (Op->getOpcode()) {
16003 default: llvm_unreachable("Unexpected request for libcall!");
16004 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16005 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16006 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16007 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16008 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16009 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16013 SDValue InChain = DAG.getEntryNode();
16015 TargetLowering::ArgListTy Args;
16016 TargetLowering::ArgListEntry Entry;
16017 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16018 EVT ArgVT = Op->getOperand(i).getValueType();
16019 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16020 "Unexpected argument type for lowering");
16021 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16022 Entry.Node = StackPtr;
16023 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16025 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16026 Entry.Ty = PointerType::get(ArgTy,0);
16027 Entry.isSExt = false;
16028 Entry.isZExt = false;
16029 Args.push_back(Entry);
16032 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16035 TargetLowering::CallLoweringInfo CLI(DAG);
16036 CLI.setDebugLoc(dl).setChain(InChain)
16037 .setCallee(getLibcallCallingConv(LC),
16038 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16039 Callee, std::move(Args), 0)
16040 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16042 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16043 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16046 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16047 SelectionDAG &DAG) {
16048 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16049 EVT VT = Op0.getValueType();
16052 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16053 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16055 // PMULxD operations multiply each even value (starting at 0) of LHS with
16056 // the related value of RHS and produce a widen result.
16057 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16058 // => <2 x i64> <ae|cg>
16060 // In other word, to have all the results, we need to perform two PMULxD:
16061 // 1. one with the even values.
16062 // 2. one with the odd values.
16063 // To achieve #2, with need to place the odd values at an even position.
16065 // Place the odd value at an even position (basically, shift all values 1
16066 // step to the left):
16067 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16068 // <a|b|c|d> => <b|undef|d|undef>
16069 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16070 // <e|f|g|h> => <f|undef|h|undef>
16071 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16073 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16075 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16076 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16078 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16079 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16080 // => <2 x i64> <ae|cg>
16081 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16082 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16083 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16084 // => <2 x i64> <bf|dh>
16085 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16086 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16088 // Shuffle it back into the right order.
16089 SDValue Highs, Lows;
16090 if (VT == MVT::v8i32) {
16091 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16092 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16093 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16094 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16096 const int HighMask[] = {1, 5, 3, 7};
16097 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16098 const int LowMask[] = {0, 4, 2, 6};
16099 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16102 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16103 // unsigned multiply.
16104 if (IsSigned && !Subtarget->hasSSE41()) {
16106 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16107 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16108 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16109 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16110 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16112 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16113 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16116 // The first result of MUL_LOHI is actually the low value, followed by the
16118 SDValue Ops[] = {Lows, Highs};
16119 return DAG.getMergeValues(Ops, dl);
16122 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16123 const X86Subtarget *Subtarget) {
16124 MVT VT = Op.getSimpleValueType();
16126 SDValue R = Op.getOperand(0);
16127 SDValue Amt = Op.getOperand(1);
16129 // Optimize shl/srl/sra with constant shift amount.
16130 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16131 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16132 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16134 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16135 (Subtarget->hasInt256() &&
16136 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16137 (Subtarget->hasAVX512() &&
16138 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16139 if (Op.getOpcode() == ISD::SHL)
16140 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16142 if (Op.getOpcode() == ISD::SRL)
16143 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16145 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16146 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16150 if (VT == MVT::v16i8) {
16151 if (Op.getOpcode() == ISD::SHL) {
16152 // Make a large shift.
16153 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16154 MVT::v8i16, R, ShiftAmt,
16156 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16157 // Zero out the rightmost bits.
16158 SmallVector<SDValue, 16> V(16,
16159 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16161 return DAG.getNode(ISD::AND, dl, VT, SHL,
16162 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16164 if (Op.getOpcode() == ISD::SRL) {
16165 // Make a large shift.
16166 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16167 MVT::v8i16, R, ShiftAmt,
16169 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16170 // Zero out the leftmost bits.
16171 SmallVector<SDValue, 16> V(16,
16172 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16174 return DAG.getNode(ISD::AND, dl, VT, SRL,
16175 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16177 if (Op.getOpcode() == ISD::SRA) {
16178 if (ShiftAmt == 7) {
16179 // R s>> 7 === R s< 0
16180 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16181 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16184 // R s>> a === ((R u>> a) ^ m) - m
16185 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16186 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
16188 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16189 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16190 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16193 llvm_unreachable("Unknown shift opcode.");
16196 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
16197 if (Op.getOpcode() == ISD::SHL) {
16198 // Make a large shift.
16199 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
16200 MVT::v16i16, R, ShiftAmt,
16202 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16203 // Zero out the rightmost bits.
16204 SmallVector<SDValue, 32> V(32,
16205 DAG.getConstant(uint8_t(-1U << ShiftAmt),
16207 return DAG.getNode(ISD::AND, dl, VT, SHL,
16208 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16210 if (Op.getOpcode() == ISD::SRL) {
16211 // Make a large shift.
16212 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
16213 MVT::v16i16, R, ShiftAmt,
16215 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16216 // Zero out the leftmost bits.
16217 SmallVector<SDValue, 32> V(32,
16218 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
16220 return DAG.getNode(ISD::AND, dl, VT, SRL,
16221 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16223 if (Op.getOpcode() == ISD::SRA) {
16224 if (ShiftAmt == 7) {
16225 // R s>> 7 === R s< 0
16226 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16227 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16230 // R s>> a === ((R u>> a) ^ m) - m
16231 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16232 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
16234 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16235 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16236 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16239 llvm_unreachable("Unknown shift opcode.");
16244 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16245 if (!Subtarget->is64Bit() &&
16246 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16247 Amt.getOpcode() == ISD::BITCAST &&
16248 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16249 Amt = Amt.getOperand(0);
16250 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16251 VT.getVectorNumElements();
16252 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16253 uint64_t ShiftAmt = 0;
16254 for (unsigned i = 0; i != Ratio; ++i) {
16255 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16259 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16261 // Check remaining shift amounts.
16262 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16263 uint64_t ShAmt = 0;
16264 for (unsigned j = 0; j != Ratio; ++j) {
16265 ConstantSDNode *C =
16266 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16270 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16272 if (ShAmt != ShiftAmt)
16275 switch (Op.getOpcode()) {
16277 llvm_unreachable("Unknown shift opcode!");
16279 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16282 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16285 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16293 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16294 const X86Subtarget* Subtarget) {
16295 MVT VT = Op.getSimpleValueType();
16297 SDValue R = Op.getOperand(0);
16298 SDValue Amt = Op.getOperand(1);
16300 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16301 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16302 (Subtarget->hasInt256() &&
16303 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16304 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16305 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16307 EVT EltVT = VT.getVectorElementType();
16309 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16310 unsigned NumElts = VT.getVectorNumElements();
16312 for (i = 0; i != NumElts; ++i) {
16313 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
16317 for (j = i; j != NumElts; ++j) {
16318 SDValue Arg = Amt.getOperand(j);
16319 if (Arg.getOpcode() == ISD::UNDEF) continue;
16320 if (Arg != Amt.getOperand(i))
16323 if (i != NumElts && j == NumElts)
16324 BaseShAmt = Amt.getOperand(i);
16326 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16327 Amt = Amt.getOperand(0);
16328 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
16329 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
16330 SDValue InVec = Amt.getOperand(0);
16331 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16332 unsigned NumElts = InVec.getValueType().getVectorNumElements();
16334 for (; i != NumElts; ++i) {
16335 SDValue Arg = InVec.getOperand(i);
16336 if (Arg.getOpcode() == ISD::UNDEF) continue;
16340 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16341 if (ConstantSDNode *C =
16342 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16343 unsigned SplatIdx =
16344 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
16345 if (C->getZExtValue() == SplatIdx)
16346 BaseShAmt = InVec.getOperand(1);
16349 if (!BaseShAmt.getNode())
16350 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
16351 DAG.getIntPtrConstant(0));
16355 if (BaseShAmt.getNode()) {
16356 if (EltVT.bitsGT(MVT::i32))
16357 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
16358 else if (EltVT.bitsLT(MVT::i32))
16359 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16361 switch (Op.getOpcode()) {
16363 llvm_unreachable("Unknown shift opcode!");
16365 switch (VT.SimpleTy) {
16366 default: return SDValue();
16375 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16378 switch (VT.SimpleTy) {
16379 default: return SDValue();
16386 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16389 switch (VT.SimpleTy) {
16390 default: return SDValue();
16399 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16405 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16406 if (!Subtarget->is64Bit() &&
16407 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16408 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16409 Amt.getOpcode() == ISD::BITCAST &&
16410 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16411 Amt = Amt.getOperand(0);
16412 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16413 VT.getVectorNumElements();
16414 std::vector<SDValue> Vals(Ratio);
16415 for (unsigned i = 0; i != Ratio; ++i)
16416 Vals[i] = Amt.getOperand(i);
16417 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16418 for (unsigned j = 0; j != Ratio; ++j)
16419 if (Vals[j] != Amt.getOperand(i + j))
16422 switch (Op.getOpcode()) {
16424 llvm_unreachable("Unknown shift opcode!");
16426 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16428 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16430 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16437 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16438 SelectionDAG &DAG) {
16439 MVT VT = Op.getSimpleValueType();
16441 SDValue R = Op.getOperand(0);
16442 SDValue Amt = Op.getOperand(1);
16445 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16446 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16448 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16452 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16456 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16458 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16459 if (Subtarget->hasInt256()) {
16460 if (Op.getOpcode() == ISD::SRL &&
16461 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16462 VT == MVT::v4i64 || VT == MVT::v8i32))
16464 if (Op.getOpcode() == ISD::SHL &&
16465 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16466 VT == MVT::v4i64 || VT == MVT::v8i32))
16468 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16472 // If possible, lower this packed shift into a vector multiply instead of
16473 // expanding it into a sequence of scalar shifts.
16474 // Do this only if the vector shift count is a constant build_vector.
16475 if (Op.getOpcode() == ISD::SHL &&
16476 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16477 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16478 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16479 SmallVector<SDValue, 8> Elts;
16480 EVT SVT = VT.getScalarType();
16481 unsigned SVTBits = SVT.getSizeInBits();
16482 const APInt &One = APInt(SVTBits, 1);
16483 unsigned NumElems = VT.getVectorNumElements();
16485 for (unsigned i=0; i !=NumElems; ++i) {
16486 SDValue Op = Amt->getOperand(i);
16487 if (Op->getOpcode() == ISD::UNDEF) {
16488 Elts.push_back(Op);
16492 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16493 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16494 uint64_t ShAmt = C.getZExtValue();
16495 if (ShAmt >= SVTBits) {
16496 Elts.push_back(DAG.getUNDEF(SVT));
16499 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16501 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16502 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16505 // Lower SHL with variable shift amount.
16506 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16507 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16509 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16510 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16511 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16512 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16515 // If possible, lower this shift as a sequence of two shifts by
16516 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16518 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16520 // Could be rewritten as:
16521 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16523 // The advantage is that the two shifts from the example would be
16524 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16525 // the vector shift into four scalar shifts plus four pairs of vector
16527 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16528 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16529 unsigned TargetOpcode = X86ISD::MOVSS;
16530 bool CanBeSimplified;
16531 // The splat value for the first packed shift (the 'X' from the example).
16532 SDValue Amt1 = Amt->getOperand(0);
16533 // The splat value for the second packed shift (the 'Y' from the example).
16534 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16535 Amt->getOperand(2);
16537 // See if it is possible to replace this node with a sequence of
16538 // two shifts followed by a MOVSS/MOVSD
16539 if (VT == MVT::v4i32) {
16540 // Check if it is legal to use a MOVSS.
16541 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16542 Amt2 == Amt->getOperand(3);
16543 if (!CanBeSimplified) {
16544 // Otherwise, check if we can still simplify this node using a MOVSD.
16545 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16546 Amt->getOperand(2) == Amt->getOperand(3);
16547 TargetOpcode = X86ISD::MOVSD;
16548 Amt2 = Amt->getOperand(2);
16551 // Do similar checks for the case where the machine value type
16553 CanBeSimplified = Amt1 == Amt->getOperand(1);
16554 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16555 CanBeSimplified = Amt2 == Amt->getOperand(i);
16557 if (!CanBeSimplified) {
16558 TargetOpcode = X86ISD::MOVSD;
16559 CanBeSimplified = true;
16560 Amt2 = Amt->getOperand(4);
16561 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16562 CanBeSimplified = Amt1 == Amt->getOperand(i);
16563 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16564 CanBeSimplified = Amt2 == Amt->getOperand(j);
16568 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16569 isa<ConstantSDNode>(Amt2)) {
16570 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16571 EVT CastVT = MVT::v4i32;
16573 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16574 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16576 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16577 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16578 if (TargetOpcode == X86ISD::MOVSD)
16579 CastVT = MVT::v2i64;
16580 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16581 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16582 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16584 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16588 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16589 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16592 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16593 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16595 // Turn 'a' into a mask suitable for VSELECT
16596 SDValue VSelM = DAG.getConstant(0x80, VT);
16597 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16598 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16600 SDValue CM1 = DAG.getConstant(0x0f, VT);
16601 SDValue CM2 = DAG.getConstant(0x3f, VT);
16603 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16604 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16605 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16606 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16607 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16610 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16611 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16612 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16614 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16615 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16616 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16617 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16618 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16621 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16622 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16623 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16625 // return VSELECT(r, r+r, a);
16626 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16627 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16631 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16632 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16633 // solution better.
16634 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16635 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16637 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16638 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16639 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16640 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16641 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16644 // Decompose 256-bit shifts into smaller 128-bit shifts.
16645 if (VT.is256BitVector()) {
16646 unsigned NumElems = VT.getVectorNumElements();
16647 MVT EltVT = VT.getVectorElementType();
16648 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16650 // Extract the two vectors
16651 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16652 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16654 // Recreate the shift amount vectors
16655 SDValue Amt1, Amt2;
16656 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16657 // Constant shift amount
16658 SmallVector<SDValue, 4> Amt1Csts;
16659 SmallVector<SDValue, 4> Amt2Csts;
16660 for (unsigned i = 0; i != NumElems/2; ++i)
16661 Amt1Csts.push_back(Amt->getOperand(i));
16662 for (unsigned i = NumElems/2; i != NumElems; ++i)
16663 Amt2Csts.push_back(Amt->getOperand(i));
16665 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16666 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16668 // Variable shift amount
16669 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16670 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16673 // Issue new vector shifts for the smaller types
16674 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16675 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16677 // Concatenate the result back
16678 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16684 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16685 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16686 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16687 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16688 // has only one use.
16689 SDNode *N = Op.getNode();
16690 SDValue LHS = N->getOperand(0);
16691 SDValue RHS = N->getOperand(1);
16692 unsigned BaseOp = 0;
16695 switch (Op.getOpcode()) {
16696 default: llvm_unreachable("Unknown ovf instruction!");
16698 // A subtract of one will be selected as a INC. Note that INC doesn't
16699 // set CF, so we can't do this for UADDO.
16700 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16702 BaseOp = X86ISD::INC;
16703 Cond = X86::COND_O;
16706 BaseOp = X86ISD::ADD;
16707 Cond = X86::COND_O;
16710 BaseOp = X86ISD::ADD;
16711 Cond = X86::COND_B;
16714 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16715 // set CF, so we can't do this for USUBO.
16716 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16718 BaseOp = X86ISD::DEC;
16719 Cond = X86::COND_O;
16722 BaseOp = X86ISD::SUB;
16723 Cond = X86::COND_O;
16726 BaseOp = X86ISD::SUB;
16727 Cond = X86::COND_B;
16730 BaseOp = X86ISD::SMUL;
16731 Cond = X86::COND_O;
16733 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16734 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16736 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16739 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16740 DAG.getConstant(X86::COND_O, MVT::i32),
16741 SDValue(Sum.getNode(), 2));
16743 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16747 // Also sets EFLAGS.
16748 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16749 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16752 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16753 DAG.getConstant(Cond, MVT::i32),
16754 SDValue(Sum.getNode(), 1));
16756 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16759 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16760 SelectionDAG &DAG) const {
16762 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16763 MVT VT = Op.getSimpleValueType();
16765 if (!Subtarget->hasSSE2() || !VT.isVector())
16768 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16769 ExtraVT.getScalarType().getSizeInBits();
16771 switch (VT.SimpleTy) {
16772 default: return SDValue();
16775 if (!Subtarget->hasFp256())
16777 if (!Subtarget->hasInt256()) {
16778 // needs to be split
16779 unsigned NumElems = VT.getVectorNumElements();
16781 // Extract the LHS vectors
16782 SDValue LHS = Op.getOperand(0);
16783 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16784 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16786 MVT EltVT = VT.getVectorElementType();
16787 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16789 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16790 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16791 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16793 SDValue Extra = DAG.getValueType(ExtraVT);
16795 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16796 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16798 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16803 SDValue Op0 = Op.getOperand(0);
16804 SDValue Op00 = Op0.getOperand(0);
16806 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
16807 if (Op0.getOpcode() == ISD::BITCAST &&
16808 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
16809 // (sext (vzext x)) -> (vsext x)
16810 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
16811 if (Tmp1.getNode()) {
16812 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16813 // This folding is only valid when the in-reg type is a vector of i8,
16815 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
16816 ExtraEltVT == MVT::i32) {
16817 SDValue Tmp1Op0 = Tmp1.getOperand(0);
16818 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
16819 "This optimization is invalid without a VZEXT.");
16820 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
16826 // If the above didn't work, then just use Shift-Left + Shift-Right.
16827 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
16829 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
16835 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16836 SelectionDAG &DAG) {
16838 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16839 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16840 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16841 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16843 // The only fence that needs an instruction is a sequentially-consistent
16844 // cross-thread fence.
16845 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16846 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16847 // no-sse2). There isn't any reason to disable it if the target processor
16849 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16850 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16852 SDValue Chain = Op.getOperand(0);
16853 SDValue Zero = DAG.getConstant(0, MVT::i32);
16855 DAG.getRegister(X86::ESP, MVT::i32), // Base
16856 DAG.getTargetConstant(1, MVT::i8), // Scale
16857 DAG.getRegister(0, MVT::i32), // Index
16858 DAG.getTargetConstant(0, MVT::i32), // Disp
16859 DAG.getRegister(0, MVT::i32), // Segment.
16863 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16864 return SDValue(Res, 0);
16867 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16868 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16871 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16872 SelectionDAG &DAG) {
16873 MVT T = Op.getSimpleValueType();
16877 switch(T.SimpleTy) {
16878 default: llvm_unreachable("Invalid value type!");
16879 case MVT::i8: Reg = X86::AL; size = 1; break;
16880 case MVT::i16: Reg = X86::AX; size = 2; break;
16881 case MVT::i32: Reg = X86::EAX; size = 4; break;
16883 assert(Subtarget->is64Bit() && "Node not type legal!");
16884 Reg = X86::RAX; size = 8;
16887 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16888 Op.getOperand(2), SDValue());
16889 SDValue Ops[] = { cpIn.getValue(0),
16892 DAG.getTargetConstant(size, MVT::i8),
16893 cpIn.getValue(1) };
16894 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16895 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16896 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16900 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16901 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16902 MVT::i32, cpOut.getValue(2));
16903 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16904 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16906 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16907 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16908 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16912 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16913 SelectionDAG &DAG) {
16914 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16915 MVT DstVT = Op.getSimpleValueType();
16917 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16918 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16919 if (DstVT != MVT::f64)
16920 // This conversion needs to be expanded.
16923 SDValue InVec = Op->getOperand(0);
16925 unsigned NumElts = SrcVT.getVectorNumElements();
16926 EVT SVT = SrcVT.getVectorElementType();
16928 // Widen the vector in input in the case of MVT::v2i32.
16929 // Example: from MVT::v2i32 to MVT::v4i32.
16930 SmallVector<SDValue, 16> Elts;
16931 for (unsigned i = 0, e = NumElts; i != e; ++i)
16932 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16933 DAG.getIntPtrConstant(i)));
16935 // Explicitly mark the extra elements as Undef.
16936 SDValue Undef = DAG.getUNDEF(SVT);
16937 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16938 Elts.push_back(Undef);
16940 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16941 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16942 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16943 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16944 DAG.getIntPtrConstant(0));
16947 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16948 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16949 assert((DstVT == MVT::i64 ||
16950 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16951 "Unexpected custom BITCAST");
16952 // i64 <=> MMX conversions are Legal.
16953 if (SrcVT==MVT::i64 && DstVT.isVector())
16955 if (DstVT==MVT::i64 && SrcVT.isVector())
16957 // MMX <=> MMX conversions are Legal.
16958 if (SrcVT.isVector() && DstVT.isVector())
16960 // All other conversions need to be expanded.
16964 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16965 SDNode *Node = Op.getNode();
16967 EVT T = Node->getValueType(0);
16968 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16969 DAG.getConstant(0, T), Node->getOperand(2));
16970 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16971 cast<AtomicSDNode>(Node)->getMemoryVT(),
16972 Node->getOperand(0),
16973 Node->getOperand(1), negOp,
16974 cast<AtomicSDNode>(Node)->getMemOperand(),
16975 cast<AtomicSDNode>(Node)->getOrdering(),
16976 cast<AtomicSDNode>(Node)->getSynchScope());
16979 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16980 SDNode *Node = Op.getNode();
16982 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16984 // Convert seq_cst store -> xchg
16985 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16986 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16987 // (The only way to get a 16-byte store is cmpxchg16b)
16988 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16989 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16990 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16991 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16992 cast<AtomicSDNode>(Node)->getMemoryVT(),
16993 Node->getOperand(0),
16994 Node->getOperand(1), Node->getOperand(2),
16995 cast<AtomicSDNode>(Node)->getMemOperand(),
16996 cast<AtomicSDNode>(Node)->getOrdering(),
16997 cast<AtomicSDNode>(Node)->getSynchScope());
16998 return Swap.getValue(1);
17000 // Other atomic stores have a simple pattern.
17004 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17005 EVT VT = Op.getNode()->getSimpleValueType(0);
17007 // Let legalize expand this if it isn't a legal type yet.
17008 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17011 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17014 bool ExtraOp = false;
17015 switch (Op.getOpcode()) {
17016 default: llvm_unreachable("Invalid code");
17017 case ISD::ADDC: Opc = X86ISD::ADD; break;
17018 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17019 case ISD::SUBC: Opc = X86ISD::SUB; break;
17020 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17024 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17026 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17027 Op.getOperand(1), Op.getOperand(2));
17030 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17031 SelectionDAG &DAG) {
17032 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17034 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17035 // which returns the values as { float, float } (in XMM0) or
17036 // { double, double } (which is returned in XMM0, XMM1).
17038 SDValue Arg = Op.getOperand(0);
17039 EVT ArgVT = Arg.getValueType();
17040 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17042 TargetLowering::ArgListTy Args;
17043 TargetLowering::ArgListEntry Entry;
17047 Entry.isSExt = false;
17048 Entry.isZExt = false;
17049 Args.push_back(Entry);
17051 bool isF64 = ArgVT == MVT::f64;
17052 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17053 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17054 // the results are returned via SRet in memory.
17055 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17056 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17057 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17059 Type *RetTy = isF64
17060 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
17061 : (Type*)VectorType::get(ArgTy, 4);
17063 TargetLowering::CallLoweringInfo CLI(DAG);
17064 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17065 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17067 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17070 // Returned in xmm0 and xmm1.
17071 return CallResult.first;
17073 // Returned in bits 0:31 and 32:64 xmm0.
17074 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17075 CallResult.first, DAG.getIntPtrConstant(0));
17076 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17077 CallResult.first, DAG.getIntPtrConstant(1));
17078 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17079 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17082 /// LowerOperation - Provide custom lowering hooks for some operations.
17084 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17085 switch (Op.getOpcode()) {
17086 default: llvm_unreachable("Should not custom lower this!");
17087 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
17088 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17089 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17090 return LowerCMP_SWAP(Op, Subtarget, DAG);
17091 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17092 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17093 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17094 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
17095 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
17096 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17097 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17098 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17099 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17100 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17101 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17102 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17103 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17104 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17105 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17106 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17107 case ISD::SHL_PARTS:
17108 case ISD::SRA_PARTS:
17109 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17110 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17111 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17112 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17113 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17114 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17115 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17116 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17117 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17118 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17119 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17120 case ISD::FABS: return LowerFABS(Op, DAG);
17121 case ISD::FNEG: return LowerFNEG(Op, DAG);
17122 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17123 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17124 case ISD::SETCC: return LowerSETCC(Op, DAG);
17125 case ISD::SELECT: return LowerSELECT(Op, DAG);
17126 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17127 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17128 case ISD::VASTART: return LowerVASTART(Op, DAG);
17129 case ISD::VAARG: return LowerVAARG(Op, DAG);
17130 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17131 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
17132 case ISD::INTRINSIC_VOID:
17133 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17134 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17135 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17136 case ISD::FRAME_TO_ARGS_OFFSET:
17137 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17138 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17139 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17140 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17141 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17142 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17143 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17144 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17145 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17146 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17147 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17148 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17149 case ISD::UMUL_LOHI:
17150 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17153 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17159 case ISD::UMULO: return LowerXALUO(Op, DAG);
17160 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17161 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17165 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17166 case ISD::ADD: return LowerADD(Op, DAG);
17167 case ISD::SUB: return LowerSUB(Op, DAG);
17168 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17172 static void ReplaceATOMIC_LOAD(SDNode *Node,
17173 SmallVectorImpl<SDValue> &Results,
17174 SelectionDAG &DAG) {
17176 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17178 // Convert wide load -> cmpxchg8b/cmpxchg16b
17179 // FIXME: On 32-bit, load -> fild or movq would be more efficient
17180 // (The only way to get a 16-byte load is cmpxchg16b)
17181 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
17182 SDValue Zero = DAG.getConstant(0, VT);
17183 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
17185 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
17186 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
17187 cast<AtomicSDNode>(Node)->getMemOperand(),
17188 cast<AtomicSDNode>(Node)->getOrdering(),
17189 cast<AtomicSDNode>(Node)->getOrdering(),
17190 cast<AtomicSDNode>(Node)->getSynchScope());
17191 Results.push_back(Swap.getValue(0));
17192 Results.push_back(Swap.getValue(2));
17195 /// ReplaceNodeResults - Replace a node with an illegal result type
17196 /// with a new node built out of custom code.
17197 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17198 SmallVectorImpl<SDValue>&Results,
17199 SelectionDAG &DAG) const {
17201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17202 switch (N->getOpcode()) {
17204 llvm_unreachable("Do not know how to custom type legalize this operation!");
17205 case ISD::SIGN_EXTEND_INREG:
17210 // We don't want to expand or promote these.
17217 case ISD::UDIVREM: {
17218 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17219 Results.push_back(V);
17222 case ISD::FP_TO_SINT:
17223 case ISD::FP_TO_UINT: {
17224 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17226 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17229 std::pair<SDValue,SDValue> Vals =
17230 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17231 SDValue FIST = Vals.first, StackSlot = Vals.second;
17232 if (FIST.getNode()) {
17233 EVT VT = N->getValueType(0);
17234 // Return a load from the stack slot.
17235 if (StackSlot.getNode())
17236 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17237 MachinePointerInfo(),
17238 false, false, false, 0));
17240 Results.push_back(FIST);
17244 case ISD::UINT_TO_FP: {
17245 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17246 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17247 N->getValueType(0) != MVT::v2f32)
17249 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17251 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17253 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17254 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17255 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17256 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17257 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17258 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17261 case ISD::FP_ROUND: {
17262 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17264 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17265 Results.push_back(V);
17268 case ISD::INTRINSIC_W_CHAIN: {
17269 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17271 default : llvm_unreachable("Do not know how to custom type "
17272 "legalize this intrinsic operation!");
17273 case Intrinsic::x86_rdtsc:
17274 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17276 case Intrinsic::x86_rdtscp:
17277 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17279 case Intrinsic::x86_rdpmc:
17280 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17283 case ISD::READCYCLECOUNTER: {
17284 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17287 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17288 EVT T = N->getValueType(0);
17289 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17290 bool Regs64bit = T == MVT::i128;
17291 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17292 SDValue cpInL, cpInH;
17293 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17294 DAG.getConstant(0, HalfT));
17295 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17296 DAG.getConstant(1, HalfT));
17297 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17298 Regs64bit ? X86::RAX : X86::EAX,
17300 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17301 Regs64bit ? X86::RDX : X86::EDX,
17302 cpInH, cpInL.getValue(1));
17303 SDValue swapInL, swapInH;
17304 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17305 DAG.getConstant(0, HalfT));
17306 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17307 DAG.getConstant(1, HalfT));
17308 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17309 Regs64bit ? X86::RBX : X86::EBX,
17310 swapInL, cpInH.getValue(1));
17311 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17312 Regs64bit ? X86::RCX : X86::ECX,
17313 swapInH, swapInL.getValue(1));
17314 SDValue Ops[] = { swapInH.getValue(0),
17316 swapInH.getValue(1) };
17317 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17318 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17319 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17320 X86ISD::LCMPXCHG8_DAG;
17321 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17322 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17323 Regs64bit ? X86::RAX : X86::EAX,
17324 HalfT, Result.getValue(1));
17325 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17326 Regs64bit ? X86::RDX : X86::EDX,
17327 HalfT, cpOutL.getValue(2));
17328 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17330 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17331 MVT::i32, cpOutH.getValue(2));
17333 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17334 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17335 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17337 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17338 Results.push_back(Success);
17339 Results.push_back(EFLAGS.getValue(1));
17342 case ISD::ATOMIC_SWAP:
17343 case ISD::ATOMIC_LOAD_ADD:
17344 case ISD::ATOMIC_LOAD_SUB:
17345 case ISD::ATOMIC_LOAD_AND:
17346 case ISD::ATOMIC_LOAD_OR:
17347 case ISD::ATOMIC_LOAD_XOR:
17348 case ISD::ATOMIC_LOAD_NAND:
17349 case ISD::ATOMIC_LOAD_MIN:
17350 case ISD::ATOMIC_LOAD_MAX:
17351 case ISD::ATOMIC_LOAD_UMIN:
17352 case ISD::ATOMIC_LOAD_UMAX:
17353 // Delegate to generic TypeLegalization. Situations we can really handle
17354 // should have already been dealt with by X86AtomicExpandPass.cpp.
17356 case ISD::ATOMIC_LOAD: {
17357 ReplaceATOMIC_LOAD(N, Results, DAG);
17360 case ISD::BITCAST: {
17361 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17362 EVT DstVT = N->getValueType(0);
17363 EVT SrcVT = N->getOperand(0)->getValueType(0);
17365 if (SrcVT != MVT::f64 ||
17366 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17369 unsigned NumElts = DstVT.getVectorNumElements();
17370 EVT SVT = DstVT.getVectorElementType();
17371 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17372 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17373 MVT::v2f64, N->getOperand(0));
17374 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17376 if (ExperimentalVectorWideningLegalization) {
17377 // If we are legalizing vectors by widening, we already have the desired
17378 // legal vector type, just return it.
17379 Results.push_back(ToVecInt);
17383 SmallVector<SDValue, 8> Elts;
17384 for (unsigned i = 0, e = NumElts; i != e; ++i)
17385 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17386 ToVecInt, DAG.getIntPtrConstant(i)));
17388 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17393 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17395 default: return nullptr;
17396 case X86ISD::BSF: return "X86ISD::BSF";
17397 case X86ISD::BSR: return "X86ISD::BSR";
17398 case X86ISD::SHLD: return "X86ISD::SHLD";
17399 case X86ISD::SHRD: return "X86ISD::SHRD";
17400 case X86ISD::FAND: return "X86ISD::FAND";
17401 case X86ISD::FANDN: return "X86ISD::FANDN";
17402 case X86ISD::FOR: return "X86ISD::FOR";
17403 case X86ISD::FXOR: return "X86ISD::FXOR";
17404 case X86ISD::FSRL: return "X86ISD::FSRL";
17405 case X86ISD::FILD: return "X86ISD::FILD";
17406 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17407 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17408 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17409 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17410 case X86ISD::FLD: return "X86ISD::FLD";
17411 case X86ISD::FST: return "X86ISD::FST";
17412 case X86ISD::CALL: return "X86ISD::CALL";
17413 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17414 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17415 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17416 case X86ISD::BT: return "X86ISD::BT";
17417 case X86ISD::CMP: return "X86ISD::CMP";
17418 case X86ISD::COMI: return "X86ISD::COMI";
17419 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17420 case X86ISD::CMPM: return "X86ISD::CMPM";
17421 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17422 case X86ISD::SETCC: return "X86ISD::SETCC";
17423 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17424 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17425 case X86ISD::CMOV: return "X86ISD::CMOV";
17426 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17427 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17428 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17429 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17430 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17431 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17432 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17433 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17434 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17435 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17436 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17437 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17438 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17439 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17440 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17441 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17442 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17443 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17444 case X86ISD::HADD: return "X86ISD::HADD";
17445 case X86ISD::HSUB: return "X86ISD::HSUB";
17446 case X86ISD::FHADD: return "X86ISD::FHADD";
17447 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17448 case X86ISD::UMAX: return "X86ISD::UMAX";
17449 case X86ISD::UMIN: return "X86ISD::UMIN";
17450 case X86ISD::SMAX: return "X86ISD::SMAX";
17451 case X86ISD::SMIN: return "X86ISD::SMIN";
17452 case X86ISD::FMAX: return "X86ISD::FMAX";
17453 case X86ISD::FMIN: return "X86ISD::FMIN";
17454 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17455 case X86ISD::FMINC: return "X86ISD::FMINC";
17456 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17457 case X86ISD::FRCP: return "X86ISD::FRCP";
17458 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17459 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17460 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17461 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17462 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17463 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17464 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17465 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17466 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17467 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17468 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17469 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17470 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17471 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17472 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17473 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17474 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17475 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17476 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17477 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17478 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17479 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17480 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17481 case X86ISD::VSHL: return "X86ISD::VSHL";
17482 case X86ISD::VSRL: return "X86ISD::VSRL";
17483 case X86ISD::VSRA: return "X86ISD::VSRA";
17484 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17485 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17486 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17487 case X86ISD::CMPP: return "X86ISD::CMPP";
17488 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17489 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17490 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17491 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17492 case X86ISD::ADD: return "X86ISD::ADD";
17493 case X86ISD::SUB: return "X86ISD::SUB";
17494 case X86ISD::ADC: return "X86ISD::ADC";
17495 case X86ISD::SBB: return "X86ISD::SBB";
17496 case X86ISD::SMUL: return "X86ISD::SMUL";
17497 case X86ISD::UMUL: return "X86ISD::UMUL";
17498 case X86ISD::INC: return "X86ISD::INC";
17499 case X86ISD::DEC: return "X86ISD::DEC";
17500 case X86ISD::OR: return "X86ISD::OR";
17501 case X86ISD::XOR: return "X86ISD::XOR";
17502 case X86ISD::AND: return "X86ISD::AND";
17503 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17504 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17505 case X86ISD::PTEST: return "X86ISD::PTEST";
17506 case X86ISD::TESTP: return "X86ISD::TESTP";
17507 case X86ISD::TESTM: return "X86ISD::TESTM";
17508 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17509 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17510 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17511 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17512 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17513 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17514 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17515 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17516 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17517 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17518 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17519 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17520 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17521 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17522 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17523 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17524 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17525 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17526 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17527 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17528 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17529 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17530 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17531 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17532 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17533 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17534 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17535 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17536 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17537 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17538 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17539 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17540 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17541 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17542 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17543 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17544 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17545 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17546 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17547 case X86ISD::SAHF: return "X86ISD::SAHF";
17548 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17549 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17550 case X86ISD::FMADD: return "X86ISD::FMADD";
17551 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17552 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17553 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17554 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17555 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17556 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17557 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17558 case X86ISD::XTEST: return "X86ISD::XTEST";
17562 // isLegalAddressingMode - Return true if the addressing mode represented
17563 // by AM is legal for this target, for a load/store of the specified type.
17564 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17566 // X86 supports extremely general addressing modes.
17567 CodeModel::Model M = getTargetMachine().getCodeModel();
17568 Reloc::Model R = getTargetMachine().getRelocationModel();
17570 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17571 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17576 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17578 // If a reference to this global requires an extra load, we can't fold it.
17579 if (isGlobalStubReference(GVFlags))
17582 // If BaseGV requires a register for the PIC base, we cannot also have a
17583 // BaseReg specified.
17584 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17587 // If lower 4G is not available, then we must use rip-relative addressing.
17588 if ((M != CodeModel::Small || R != Reloc::Static) &&
17589 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17593 switch (AM.Scale) {
17599 // These scales always work.
17604 // These scales are formed with basereg+scalereg. Only accept if there is
17609 default: // Other stuff never works.
17616 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17617 unsigned Bits = Ty->getScalarSizeInBits();
17619 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17620 // particularly cheaper than those without.
17624 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17625 // variable shifts just as cheap as scalar ones.
17626 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17629 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17630 // fully general vector.
17634 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17635 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17637 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17638 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17639 return NumBits1 > NumBits2;
17642 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17643 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17646 if (!isTypeLegal(EVT::getEVT(Ty1)))
17649 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17651 // Assuming the caller doesn't have a zeroext or signext return parameter,
17652 // truncation all the way down to i1 is valid.
17656 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17657 return isInt<32>(Imm);
17660 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17661 // Can also use sub to handle negated immediates.
17662 return isInt<32>(Imm);
17665 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17666 if (!VT1.isInteger() || !VT2.isInteger())
17668 unsigned NumBits1 = VT1.getSizeInBits();
17669 unsigned NumBits2 = VT2.getSizeInBits();
17670 return NumBits1 > NumBits2;
17673 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17674 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17675 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17678 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17679 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17680 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17683 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17684 EVT VT1 = Val.getValueType();
17685 if (isZExtFree(VT1, VT2))
17688 if (Val.getOpcode() != ISD::LOAD)
17691 if (!VT1.isSimple() || !VT1.isInteger() ||
17692 !VT2.isSimple() || !VT2.isInteger())
17695 switch (VT1.getSimpleVT().SimpleTy) {
17700 // X86 has 8, 16, and 32-bit zero-extending loads.
17708 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17709 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17712 VT = VT.getScalarType();
17714 if (!VT.isSimple())
17717 switch (VT.getSimpleVT().SimpleTy) {
17728 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17729 // i16 instructions are longer (0x66 prefix) and potentially slower.
17730 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17733 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17734 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17735 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17736 /// are assumed to be legal.
17738 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17740 if (!VT.isSimple())
17743 MVT SVT = VT.getSimpleVT();
17745 // Very little shuffling can be done for 64-bit vectors right now.
17746 if (VT.getSizeInBits() == 64)
17749 // If this is a single-input shuffle with no 128 bit lane crossings we can
17750 // lower it into pshufb.
17751 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17752 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17753 bool isLegal = true;
17754 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17755 if (M[I] >= (int)SVT.getVectorNumElements() ||
17756 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17765 // FIXME: blends, shifts.
17766 return (SVT.getVectorNumElements() == 2 ||
17767 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17768 isMOVLMask(M, SVT) ||
17769 isMOVHLPSMask(M, SVT) ||
17770 isSHUFPMask(M, SVT) ||
17771 isPSHUFDMask(M, SVT) ||
17772 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17773 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17774 isPALIGNRMask(M, SVT, Subtarget) ||
17775 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17776 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17777 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17778 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17779 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17783 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17785 if (!VT.isSimple())
17788 MVT SVT = VT.getSimpleVT();
17789 unsigned NumElts = SVT.getVectorNumElements();
17790 // FIXME: This collection of masks seems suspect.
17793 if (NumElts == 4 && SVT.is128BitVector()) {
17794 return (isMOVLMask(Mask, SVT) ||
17795 isCommutedMOVLMask(Mask, SVT, true) ||
17796 isSHUFPMask(Mask, SVT) ||
17797 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17802 //===----------------------------------------------------------------------===//
17803 // X86 Scheduler Hooks
17804 //===----------------------------------------------------------------------===//
17806 /// Utility function to emit xbegin specifying the start of an RTM region.
17807 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17808 const TargetInstrInfo *TII) {
17809 DebugLoc DL = MI->getDebugLoc();
17811 const BasicBlock *BB = MBB->getBasicBlock();
17812 MachineFunction::iterator I = MBB;
17815 // For the v = xbegin(), we generate
17826 MachineBasicBlock *thisMBB = MBB;
17827 MachineFunction *MF = MBB->getParent();
17828 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17829 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17830 MF->insert(I, mainMBB);
17831 MF->insert(I, sinkMBB);
17833 // Transfer the remainder of BB and its successor edges to sinkMBB.
17834 sinkMBB->splice(sinkMBB->begin(), MBB,
17835 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17836 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17840 // # fallthrough to mainMBB
17841 // # abortion to sinkMBB
17842 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17843 thisMBB->addSuccessor(mainMBB);
17844 thisMBB->addSuccessor(sinkMBB);
17848 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17849 mainMBB->addSuccessor(sinkMBB);
17852 // EAX is live into the sinkMBB
17853 sinkMBB->addLiveIn(X86::EAX);
17854 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17855 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17858 MI->eraseFromParent();
17862 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17863 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17864 // in the .td file.
17865 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17866 const TargetInstrInfo *TII) {
17868 switch (MI->getOpcode()) {
17869 default: llvm_unreachable("illegal opcode!");
17870 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17871 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17872 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17873 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17874 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17875 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17876 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17877 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17880 DebugLoc dl = MI->getDebugLoc();
17881 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17883 unsigned NumArgs = MI->getNumOperands();
17884 for (unsigned i = 1; i < NumArgs; ++i) {
17885 MachineOperand &Op = MI->getOperand(i);
17886 if (!(Op.isReg() && Op.isImplicit()))
17887 MIB.addOperand(Op);
17889 if (MI->hasOneMemOperand())
17890 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17892 BuildMI(*BB, MI, dl,
17893 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17894 .addReg(X86::XMM0);
17896 MI->eraseFromParent();
17900 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17901 // defs in an instruction pattern
17902 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17903 const TargetInstrInfo *TII) {
17905 switch (MI->getOpcode()) {
17906 default: llvm_unreachable("illegal opcode!");
17907 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17908 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17909 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17910 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17911 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17912 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17913 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17914 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17917 DebugLoc dl = MI->getDebugLoc();
17918 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17920 unsigned NumArgs = MI->getNumOperands(); // remove the results
17921 for (unsigned i = 1; i < NumArgs; ++i) {
17922 MachineOperand &Op = MI->getOperand(i);
17923 if (!(Op.isReg() && Op.isImplicit()))
17924 MIB.addOperand(Op);
17926 if (MI->hasOneMemOperand())
17927 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17929 BuildMI(*BB, MI, dl,
17930 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17933 MI->eraseFromParent();
17937 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17938 const TargetInstrInfo *TII,
17939 const X86Subtarget* Subtarget) {
17940 DebugLoc dl = MI->getDebugLoc();
17942 // Address into RAX/EAX, other two args into ECX, EDX.
17943 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17944 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17945 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17946 for (int i = 0; i < X86::AddrNumOperands; ++i)
17947 MIB.addOperand(MI->getOperand(i));
17949 unsigned ValOps = X86::AddrNumOperands;
17950 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17951 .addReg(MI->getOperand(ValOps).getReg());
17952 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17953 .addReg(MI->getOperand(ValOps+1).getReg());
17955 // The instruction doesn't actually take any operands though.
17956 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17958 MI->eraseFromParent(); // The pseudo is gone now.
17962 MachineBasicBlock *
17963 X86TargetLowering::EmitVAARG64WithCustomInserter(
17965 MachineBasicBlock *MBB) const {
17966 // Emit va_arg instruction on X86-64.
17968 // Operands to this pseudo-instruction:
17969 // 0 ) Output : destination address (reg)
17970 // 1-5) Input : va_list address (addr, i64mem)
17971 // 6 ) ArgSize : Size (in bytes) of vararg type
17972 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17973 // 8 ) Align : Alignment of type
17974 // 9 ) EFLAGS (implicit-def)
17976 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17977 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17979 unsigned DestReg = MI->getOperand(0).getReg();
17980 MachineOperand &Base = MI->getOperand(1);
17981 MachineOperand &Scale = MI->getOperand(2);
17982 MachineOperand &Index = MI->getOperand(3);
17983 MachineOperand &Disp = MI->getOperand(4);
17984 MachineOperand &Segment = MI->getOperand(5);
17985 unsigned ArgSize = MI->getOperand(6).getImm();
17986 unsigned ArgMode = MI->getOperand(7).getImm();
17987 unsigned Align = MI->getOperand(8).getImm();
17989 // Memory Reference
17990 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17991 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17992 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17994 // Machine Information
17995 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17996 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17997 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17998 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17999 DebugLoc DL = MI->getDebugLoc();
18001 // struct va_list {
18004 // i64 overflow_area (address)
18005 // i64 reg_save_area (address)
18007 // sizeof(va_list) = 24
18008 // alignment(va_list) = 8
18010 unsigned TotalNumIntRegs = 6;
18011 unsigned TotalNumXMMRegs = 8;
18012 bool UseGPOffset = (ArgMode == 1);
18013 bool UseFPOffset = (ArgMode == 2);
18014 unsigned MaxOffset = TotalNumIntRegs * 8 +
18015 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18017 /* Align ArgSize to a multiple of 8 */
18018 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18019 bool NeedsAlign = (Align > 8);
18021 MachineBasicBlock *thisMBB = MBB;
18022 MachineBasicBlock *overflowMBB;
18023 MachineBasicBlock *offsetMBB;
18024 MachineBasicBlock *endMBB;
18026 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18027 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18028 unsigned OffsetReg = 0;
18030 if (!UseGPOffset && !UseFPOffset) {
18031 // If we only pull from the overflow region, we don't create a branch.
18032 // We don't need to alter control flow.
18033 OffsetDestReg = 0; // unused
18034 OverflowDestReg = DestReg;
18036 offsetMBB = nullptr;
18037 overflowMBB = thisMBB;
18040 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18041 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18042 // If not, pull from overflow_area. (branch to overflowMBB)
18047 // offsetMBB overflowMBB
18052 // Registers for the PHI in endMBB
18053 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18054 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18056 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18057 MachineFunction *MF = MBB->getParent();
18058 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18059 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18060 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18062 MachineFunction::iterator MBBIter = MBB;
18065 // Insert the new basic blocks
18066 MF->insert(MBBIter, offsetMBB);
18067 MF->insert(MBBIter, overflowMBB);
18068 MF->insert(MBBIter, endMBB);
18070 // Transfer the remainder of MBB and its successor edges to endMBB.
18071 endMBB->splice(endMBB->begin(), thisMBB,
18072 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18073 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18075 // Make offsetMBB and overflowMBB successors of thisMBB
18076 thisMBB->addSuccessor(offsetMBB);
18077 thisMBB->addSuccessor(overflowMBB);
18079 // endMBB is a successor of both offsetMBB and overflowMBB
18080 offsetMBB->addSuccessor(endMBB);
18081 overflowMBB->addSuccessor(endMBB);
18083 // Load the offset value into a register
18084 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18085 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18089 .addDisp(Disp, UseFPOffset ? 4 : 0)
18090 .addOperand(Segment)
18091 .setMemRefs(MMOBegin, MMOEnd);
18093 // Check if there is enough room left to pull this argument.
18094 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18096 .addImm(MaxOffset + 8 - ArgSizeA8);
18098 // Branch to "overflowMBB" if offset >= max
18099 // Fall through to "offsetMBB" otherwise
18100 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18101 .addMBB(overflowMBB);
18104 // In offsetMBB, emit code to use the reg_save_area.
18106 assert(OffsetReg != 0);
18108 // Read the reg_save_area address.
18109 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18110 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18115 .addOperand(Segment)
18116 .setMemRefs(MMOBegin, MMOEnd);
18118 // Zero-extend the offset
18119 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18120 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18123 .addImm(X86::sub_32bit);
18125 // Add the offset to the reg_save_area to get the final address.
18126 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18127 .addReg(OffsetReg64)
18128 .addReg(RegSaveReg);
18130 // Compute the offset for the next argument
18131 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18132 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18134 .addImm(UseFPOffset ? 16 : 8);
18136 // Store it back into the va_list.
18137 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18141 .addDisp(Disp, UseFPOffset ? 4 : 0)
18142 .addOperand(Segment)
18143 .addReg(NextOffsetReg)
18144 .setMemRefs(MMOBegin, MMOEnd);
18147 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
18152 // Emit code to use overflow area
18155 // Load the overflow_area address into a register.
18156 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18157 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18162 .addOperand(Segment)
18163 .setMemRefs(MMOBegin, MMOEnd);
18165 // If we need to align it, do so. Otherwise, just copy the address
18166 // to OverflowDestReg.
18168 // Align the overflow address
18169 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18170 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18172 // aligned_addr = (addr + (align-1)) & ~(align-1)
18173 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18174 .addReg(OverflowAddrReg)
18177 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18179 .addImm(~(uint64_t)(Align-1));
18181 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18182 .addReg(OverflowAddrReg);
18185 // Compute the next overflow address after this argument.
18186 // (the overflow address should be kept 8-byte aligned)
18187 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18188 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18189 .addReg(OverflowDestReg)
18190 .addImm(ArgSizeA8);
18192 // Store the new overflow address.
18193 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18198 .addOperand(Segment)
18199 .addReg(NextAddrReg)
18200 .setMemRefs(MMOBegin, MMOEnd);
18202 // If we branched, emit the PHI to the front of endMBB.
18204 BuildMI(*endMBB, endMBB->begin(), DL,
18205 TII->get(X86::PHI), DestReg)
18206 .addReg(OffsetDestReg).addMBB(offsetMBB)
18207 .addReg(OverflowDestReg).addMBB(overflowMBB);
18210 // Erase the pseudo instruction
18211 MI->eraseFromParent();
18216 MachineBasicBlock *
18217 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18219 MachineBasicBlock *MBB) const {
18220 // Emit code to save XMM registers to the stack. The ABI says that the
18221 // number of registers to save is given in %al, so it's theoretically
18222 // possible to do an indirect jump trick to avoid saving all of them,
18223 // however this code takes a simpler approach and just executes all
18224 // of the stores if %al is non-zero. It's less code, and it's probably
18225 // easier on the hardware branch predictor, and stores aren't all that
18226 // expensive anyway.
18228 // Create the new basic blocks. One block contains all the XMM stores,
18229 // and one block is the final destination regardless of whether any
18230 // stores were performed.
18231 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18232 MachineFunction *F = MBB->getParent();
18233 MachineFunction::iterator MBBIter = MBB;
18235 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18236 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18237 F->insert(MBBIter, XMMSaveMBB);
18238 F->insert(MBBIter, EndMBB);
18240 // Transfer the remainder of MBB and its successor edges to EndMBB.
18241 EndMBB->splice(EndMBB->begin(), MBB,
18242 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18243 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18245 // The original block will now fall through to the XMM save block.
18246 MBB->addSuccessor(XMMSaveMBB);
18247 // The XMMSaveMBB will fall through to the end block.
18248 XMMSaveMBB->addSuccessor(EndMBB);
18250 // Now add the instructions.
18251 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
18252 DebugLoc DL = MI->getDebugLoc();
18254 unsigned CountReg = MI->getOperand(0).getReg();
18255 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18256 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18258 if (!Subtarget->isTargetWin64()) {
18259 // If %al is 0, branch around the XMM save block.
18260 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18261 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
18262 MBB->addSuccessor(EndMBB);
18265 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18266 // that was just emitted, but clearly shouldn't be "saved".
18267 assert((MI->getNumOperands() <= 3 ||
18268 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18269 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18270 && "Expected last argument to be EFLAGS");
18271 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18272 // In the XMM save block, save all the XMM argument registers.
18273 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18274 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18275 MachineMemOperand *MMO =
18276 F->getMachineMemOperand(
18277 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18278 MachineMemOperand::MOStore,
18279 /*Size=*/16, /*Align=*/16);
18280 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18281 .addFrameIndex(RegSaveFrameIndex)
18282 .addImm(/*Scale=*/1)
18283 .addReg(/*IndexReg=*/0)
18284 .addImm(/*Disp=*/Offset)
18285 .addReg(/*Segment=*/0)
18286 .addReg(MI->getOperand(i).getReg())
18287 .addMemOperand(MMO);
18290 MI->eraseFromParent(); // The pseudo instruction is gone now.
18295 // The EFLAGS operand of SelectItr might be missing a kill marker
18296 // because there were multiple uses of EFLAGS, and ISel didn't know
18297 // which to mark. Figure out whether SelectItr should have had a
18298 // kill marker, and set it if it should. Returns the correct kill
18300 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18301 MachineBasicBlock* BB,
18302 const TargetRegisterInfo* TRI) {
18303 // Scan forward through BB for a use/def of EFLAGS.
18304 MachineBasicBlock::iterator miI(std::next(SelectItr));
18305 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18306 const MachineInstr& mi = *miI;
18307 if (mi.readsRegister(X86::EFLAGS))
18309 if (mi.definesRegister(X86::EFLAGS))
18310 break; // Should have kill-flag - update below.
18313 // If we hit the end of the block, check whether EFLAGS is live into a
18315 if (miI == BB->end()) {
18316 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18317 sEnd = BB->succ_end();
18318 sItr != sEnd; ++sItr) {
18319 MachineBasicBlock* succ = *sItr;
18320 if (succ->isLiveIn(X86::EFLAGS))
18325 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18326 // out. SelectMI should have a kill flag on EFLAGS.
18327 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18331 MachineBasicBlock *
18332 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18333 MachineBasicBlock *BB) const {
18334 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18335 DebugLoc DL = MI->getDebugLoc();
18337 // To "insert" a SELECT_CC instruction, we actually have to insert the
18338 // diamond control-flow pattern. The incoming instruction knows the
18339 // destination vreg to set, the condition code register to branch on, the
18340 // true/false values to select between, and a branch opcode to use.
18341 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18342 MachineFunction::iterator It = BB;
18348 // cmpTY ccX, r1, r2
18350 // fallthrough --> copy0MBB
18351 MachineBasicBlock *thisMBB = BB;
18352 MachineFunction *F = BB->getParent();
18353 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18354 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18355 F->insert(It, copy0MBB);
18356 F->insert(It, sinkMBB);
18358 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18359 // live into the sink and copy blocks.
18360 const TargetRegisterInfo *TRI =
18361 BB->getParent()->getSubtarget().getRegisterInfo();
18362 if (!MI->killsRegister(X86::EFLAGS) &&
18363 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
18364 copy0MBB->addLiveIn(X86::EFLAGS);
18365 sinkMBB->addLiveIn(X86::EFLAGS);
18368 // Transfer the remainder of BB and its successor edges to sinkMBB.
18369 sinkMBB->splice(sinkMBB->begin(), BB,
18370 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18371 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18373 // Add the true and fallthrough blocks as its successors.
18374 BB->addSuccessor(copy0MBB);
18375 BB->addSuccessor(sinkMBB);
18377 // Create the conditional branch instruction.
18379 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18380 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18383 // %FalseValue = ...
18384 // # fallthrough to sinkMBB
18385 copy0MBB->addSuccessor(sinkMBB);
18388 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18390 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18391 TII->get(X86::PHI), MI->getOperand(0).getReg())
18392 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18393 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18395 MI->eraseFromParent(); // The pseudo instruction is gone now.
18399 MachineBasicBlock *
18400 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18401 bool Is64Bit) const {
18402 MachineFunction *MF = BB->getParent();
18403 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18404 DebugLoc DL = MI->getDebugLoc();
18405 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18407 assert(MF->shouldSplitStack());
18409 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18410 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18413 // ... [Till the alloca]
18414 // If stacklet is not large enough, jump to mallocMBB
18417 // Allocate by subtracting from RSP
18418 // Jump to continueMBB
18421 // Allocate by call to runtime
18425 // [rest of original BB]
18428 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18429 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18430 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18432 MachineRegisterInfo &MRI = MF->getRegInfo();
18433 const TargetRegisterClass *AddrRegClass =
18434 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18436 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18437 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18438 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18439 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18440 sizeVReg = MI->getOperand(1).getReg(),
18441 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18443 MachineFunction::iterator MBBIter = BB;
18446 MF->insert(MBBIter, bumpMBB);
18447 MF->insert(MBBIter, mallocMBB);
18448 MF->insert(MBBIter, continueMBB);
18450 continueMBB->splice(continueMBB->begin(), BB,
18451 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18452 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18454 // Add code to the main basic block to check if the stack limit has been hit,
18455 // and if so, jump to mallocMBB otherwise to bumpMBB.
18456 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18457 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18458 .addReg(tmpSPVReg).addReg(sizeVReg);
18459 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18460 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18461 .addReg(SPLimitVReg);
18462 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18464 // bumpMBB simply decreases the stack pointer, since we know the current
18465 // stacklet has enough space.
18466 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18467 .addReg(SPLimitVReg);
18468 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18469 .addReg(SPLimitVReg);
18470 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18472 // Calls into a routine in libgcc to allocate more space from the heap.
18473 const uint32_t *RegMask = MF->getTarget()
18474 .getSubtargetImpl()
18475 ->getRegisterInfo()
18476 ->getCallPreservedMask(CallingConv::C);
18478 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18480 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18481 .addExternalSymbol("__morestack_allocate_stack_space")
18482 .addRegMask(RegMask)
18483 .addReg(X86::RDI, RegState::Implicit)
18484 .addReg(X86::RAX, RegState::ImplicitDefine);
18486 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18488 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18489 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18490 .addExternalSymbol("__morestack_allocate_stack_space")
18491 .addRegMask(RegMask)
18492 .addReg(X86::EAX, RegState::ImplicitDefine);
18496 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18499 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18500 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18501 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18503 // Set up the CFG correctly.
18504 BB->addSuccessor(bumpMBB);
18505 BB->addSuccessor(mallocMBB);
18506 mallocMBB->addSuccessor(continueMBB);
18507 bumpMBB->addSuccessor(continueMBB);
18509 // Take care of the PHI nodes.
18510 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18511 MI->getOperand(0).getReg())
18512 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18513 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18515 // Delete the original pseudo instruction.
18516 MI->eraseFromParent();
18519 return continueMBB;
18522 MachineBasicBlock *
18523 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18524 MachineBasicBlock *BB) const {
18525 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18526 DebugLoc DL = MI->getDebugLoc();
18528 assert(!Subtarget->isTargetMacho());
18530 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18531 // non-trivial part is impdef of ESP.
18533 if (Subtarget->isTargetWin64()) {
18534 if (Subtarget->isTargetCygMing()) {
18535 // ___chkstk(Mingw64):
18536 // Clobbers R10, R11, RAX and EFLAGS.
18538 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18539 .addExternalSymbol("___chkstk")
18540 .addReg(X86::RAX, RegState::Implicit)
18541 .addReg(X86::RSP, RegState::Implicit)
18542 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18543 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18544 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18546 // __chkstk(MSVCRT): does not update stack pointer.
18547 // Clobbers R10, R11 and EFLAGS.
18548 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18549 .addExternalSymbol("__chkstk")
18550 .addReg(X86::RAX, RegState::Implicit)
18551 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18552 // RAX has the offset to be subtracted from RSP.
18553 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18558 const char *StackProbeSymbol =
18559 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18561 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18562 .addExternalSymbol(StackProbeSymbol)
18563 .addReg(X86::EAX, RegState::Implicit)
18564 .addReg(X86::ESP, RegState::Implicit)
18565 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18566 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18567 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18570 MI->eraseFromParent(); // The pseudo instruction is gone now.
18574 MachineBasicBlock *
18575 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18576 MachineBasicBlock *BB) const {
18577 // This is pretty easy. We're taking the value that we received from
18578 // our load from the relocation, sticking it in either RDI (x86-64)
18579 // or EAX and doing an indirect call. The return value will then
18580 // be in the normal return register.
18581 MachineFunction *F = BB->getParent();
18582 const X86InstrInfo *TII =
18583 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18584 DebugLoc DL = MI->getDebugLoc();
18586 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18587 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18589 // Get a register mask for the lowered call.
18590 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18591 // proper register mask.
18592 const uint32_t *RegMask = F->getTarget()
18593 .getSubtargetImpl()
18594 ->getRegisterInfo()
18595 ->getCallPreservedMask(CallingConv::C);
18596 if (Subtarget->is64Bit()) {
18597 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18598 TII->get(X86::MOV64rm), X86::RDI)
18600 .addImm(0).addReg(0)
18601 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18602 MI->getOperand(3).getTargetFlags())
18604 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18605 addDirectMem(MIB, X86::RDI);
18606 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18607 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18608 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18609 TII->get(X86::MOV32rm), X86::EAX)
18611 .addImm(0).addReg(0)
18612 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18613 MI->getOperand(3).getTargetFlags())
18615 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18616 addDirectMem(MIB, X86::EAX);
18617 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18619 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18620 TII->get(X86::MOV32rm), X86::EAX)
18621 .addReg(TII->getGlobalBaseReg(F))
18622 .addImm(0).addReg(0)
18623 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18624 MI->getOperand(3).getTargetFlags())
18626 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18627 addDirectMem(MIB, X86::EAX);
18628 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18631 MI->eraseFromParent(); // The pseudo instruction is gone now.
18635 MachineBasicBlock *
18636 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18637 MachineBasicBlock *MBB) const {
18638 DebugLoc DL = MI->getDebugLoc();
18639 MachineFunction *MF = MBB->getParent();
18640 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18641 MachineRegisterInfo &MRI = MF->getRegInfo();
18643 const BasicBlock *BB = MBB->getBasicBlock();
18644 MachineFunction::iterator I = MBB;
18647 // Memory Reference
18648 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18649 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18652 unsigned MemOpndSlot = 0;
18654 unsigned CurOp = 0;
18656 DstReg = MI->getOperand(CurOp++).getReg();
18657 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18658 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18659 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18660 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18662 MemOpndSlot = CurOp;
18664 MVT PVT = getPointerTy();
18665 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18666 "Invalid Pointer Size!");
18668 // For v = setjmp(buf), we generate
18671 // buf[LabelOffset] = restoreMBB
18672 // SjLjSetup restoreMBB
18678 // v = phi(main, restore)
18683 MachineBasicBlock *thisMBB = MBB;
18684 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18685 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18686 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18687 MF->insert(I, mainMBB);
18688 MF->insert(I, sinkMBB);
18689 MF->push_back(restoreMBB);
18691 MachineInstrBuilder MIB;
18693 // Transfer the remainder of BB and its successor edges to sinkMBB.
18694 sinkMBB->splice(sinkMBB->begin(), MBB,
18695 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18696 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18699 unsigned PtrStoreOpc = 0;
18700 unsigned LabelReg = 0;
18701 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18702 Reloc::Model RM = MF->getTarget().getRelocationModel();
18703 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18704 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18706 // Prepare IP either in reg or imm.
18707 if (!UseImmLabel) {
18708 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18709 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18710 LabelReg = MRI.createVirtualRegister(PtrRC);
18711 if (Subtarget->is64Bit()) {
18712 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18716 .addMBB(restoreMBB)
18719 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18720 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18721 .addReg(XII->getGlobalBaseReg(MF))
18724 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18728 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18730 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18731 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18732 if (i == X86::AddrDisp)
18733 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18735 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18738 MIB.addReg(LabelReg);
18740 MIB.addMBB(restoreMBB);
18741 MIB.setMemRefs(MMOBegin, MMOEnd);
18743 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18744 .addMBB(restoreMBB);
18746 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18747 MF->getSubtarget().getRegisterInfo());
18748 MIB.addRegMask(RegInfo->getNoPreservedMask());
18749 thisMBB->addSuccessor(mainMBB);
18750 thisMBB->addSuccessor(restoreMBB);
18754 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18755 mainMBB->addSuccessor(sinkMBB);
18758 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18759 TII->get(X86::PHI), DstReg)
18760 .addReg(mainDstReg).addMBB(mainMBB)
18761 .addReg(restoreDstReg).addMBB(restoreMBB);
18764 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18765 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18766 restoreMBB->addSuccessor(sinkMBB);
18768 MI->eraseFromParent();
18772 MachineBasicBlock *
18773 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18774 MachineBasicBlock *MBB) const {
18775 DebugLoc DL = MI->getDebugLoc();
18776 MachineFunction *MF = MBB->getParent();
18777 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18778 MachineRegisterInfo &MRI = MF->getRegInfo();
18780 // Memory Reference
18781 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18782 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18784 MVT PVT = getPointerTy();
18785 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18786 "Invalid Pointer Size!");
18788 const TargetRegisterClass *RC =
18789 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18790 unsigned Tmp = MRI.createVirtualRegister(RC);
18791 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18792 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18793 MF->getSubtarget().getRegisterInfo());
18794 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18795 unsigned SP = RegInfo->getStackRegister();
18797 MachineInstrBuilder MIB;
18799 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18800 const int64_t SPOffset = 2 * PVT.getStoreSize();
18802 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18803 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18806 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18807 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18808 MIB.addOperand(MI->getOperand(i));
18809 MIB.setMemRefs(MMOBegin, MMOEnd);
18811 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18812 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18813 if (i == X86::AddrDisp)
18814 MIB.addDisp(MI->getOperand(i), LabelOffset);
18816 MIB.addOperand(MI->getOperand(i));
18818 MIB.setMemRefs(MMOBegin, MMOEnd);
18820 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18821 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18822 if (i == X86::AddrDisp)
18823 MIB.addDisp(MI->getOperand(i), SPOffset);
18825 MIB.addOperand(MI->getOperand(i));
18827 MIB.setMemRefs(MMOBegin, MMOEnd);
18829 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18831 MI->eraseFromParent();
18835 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18836 // accumulator loops. Writing back to the accumulator allows the coalescer
18837 // to remove extra copies in the loop.
18838 MachineBasicBlock *
18839 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18840 MachineBasicBlock *MBB) const {
18841 MachineOperand &AddendOp = MI->getOperand(3);
18843 // Bail out early if the addend isn't a register - we can't switch these.
18844 if (!AddendOp.isReg())
18847 MachineFunction &MF = *MBB->getParent();
18848 MachineRegisterInfo &MRI = MF.getRegInfo();
18850 // Check whether the addend is defined by a PHI:
18851 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18852 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18853 if (!AddendDef.isPHI())
18856 // Look for the following pattern:
18858 // %addend = phi [%entry, 0], [%loop, %result]
18860 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18864 // %addend = phi [%entry, 0], [%loop, %result]
18866 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18868 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18869 assert(AddendDef.getOperand(i).isReg());
18870 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18871 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18872 if (&PHISrcInst == MI) {
18873 // Found a matching instruction.
18874 unsigned NewFMAOpc = 0;
18875 switch (MI->getOpcode()) {
18876 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18877 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18878 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18879 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18880 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18881 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18882 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18883 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18884 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18885 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18886 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18887 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18888 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18889 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18890 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18891 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18892 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18893 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18894 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18895 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18896 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18897 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18898 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18899 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18900 default: llvm_unreachable("Unrecognized FMA variant.");
18903 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18904 MachineInstrBuilder MIB =
18905 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18906 .addOperand(MI->getOperand(0))
18907 .addOperand(MI->getOperand(3))
18908 .addOperand(MI->getOperand(2))
18909 .addOperand(MI->getOperand(1));
18910 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18911 MI->eraseFromParent();
18918 MachineBasicBlock *
18919 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18920 MachineBasicBlock *BB) const {
18921 switch (MI->getOpcode()) {
18922 default: llvm_unreachable("Unexpected instr type to insert");
18923 case X86::TAILJMPd64:
18924 case X86::TAILJMPr64:
18925 case X86::TAILJMPm64:
18926 llvm_unreachable("TAILJMP64 would not be touched here.");
18927 case X86::TCRETURNdi64:
18928 case X86::TCRETURNri64:
18929 case X86::TCRETURNmi64:
18931 case X86::WIN_ALLOCA:
18932 return EmitLoweredWinAlloca(MI, BB);
18933 case X86::SEG_ALLOCA_32:
18934 return EmitLoweredSegAlloca(MI, BB, false);
18935 case X86::SEG_ALLOCA_64:
18936 return EmitLoweredSegAlloca(MI, BB, true);
18937 case X86::TLSCall_32:
18938 case X86::TLSCall_64:
18939 return EmitLoweredTLSCall(MI, BB);
18940 case X86::CMOV_GR8:
18941 case X86::CMOV_FR32:
18942 case X86::CMOV_FR64:
18943 case X86::CMOV_V4F32:
18944 case X86::CMOV_V2F64:
18945 case X86::CMOV_V2I64:
18946 case X86::CMOV_V8F32:
18947 case X86::CMOV_V4F64:
18948 case X86::CMOV_V4I64:
18949 case X86::CMOV_V16F32:
18950 case X86::CMOV_V8F64:
18951 case X86::CMOV_V8I64:
18952 case X86::CMOV_GR16:
18953 case X86::CMOV_GR32:
18954 case X86::CMOV_RFP32:
18955 case X86::CMOV_RFP64:
18956 case X86::CMOV_RFP80:
18957 return EmitLoweredSelect(MI, BB);
18959 case X86::FP32_TO_INT16_IN_MEM:
18960 case X86::FP32_TO_INT32_IN_MEM:
18961 case X86::FP32_TO_INT64_IN_MEM:
18962 case X86::FP64_TO_INT16_IN_MEM:
18963 case X86::FP64_TO_INT32_IN_MEM:
18964 case X86::FP64_TO_INT64_IN_MEM:
18965 case X86::FP80_TO_INT16_IN_MEM:
18966 case X86::FP80_TO_INT32_IN_MEM:
18967 case X86::FP80_TO_INT64_IN_MEM: {
18968 MachineFunction *F = BB->getParent();
18969 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
18970 DebugLoc DL = MI->getDebugLoc();
18972 // Change the floating point control register to use "round towards zero"
18973 // mode when truncating to an integer value.
18974 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18975 addFrameReference(BuildMI(*BB, MI, DL,
18976 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18978 // Load the old value of the high byte of the control word...
18980 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18981 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18984 // Set the high part to be round to zero...
18985 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18988 // Reload the modified control word now...
18989 addFrameReference(BuildMI(*BB, MI, DL,
18990 TII->get(X86::FLDCW16m)), CWFrameIdx);
18992 // Restore the memory image of control word to original value
18993 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18996 // Get the X86 opcode to use.
18998 switch (MI->getOpcode()) {
18999 default: llvm_unreachable("illegal opcode!");
19000 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19001 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19002 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19003 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19004 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19005 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19006 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19007 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19008 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19012 MachineOperand &Op = MI->getOperand(0);
19014 AM.BaseType = X86AddressMode::RegBase;
19015 AM.Base.Reg = Op.getReg();
19017 AM.BaseType = X86AddressMode::FrameIndexBase;
19018 AM.Base.FrameIndex = Op.getIndex();
19020 Op = MI->getOperand(1);
19022 AM.Scale = Op.getImm();
19023 Op = MI->getOperand(2);
19025 AM.IndexReg = Op.getImm();
19026 Op = MI->getOperand(3);
19027 if (Op.isGlobal()) {
19028 AM.GV = Op.getGlobal();
19030 AM.Disp = Op.getImm();
19032 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19033 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19035 // Reload the original control word now.
19036 addFrameReference(BuildMI(*BB, MI, DL,
19037 TII->get(X86::FLDCW16m)), CWFrameIdx);
19039 MI->eraseFromParent(); // The pseudo instruction is gone now.
19042 // String/text processing lowering.
19043 case X86::PCMPISTRM128REG:
19044 case X86::VPCMPISTRM128REG:
19045 case X86::PCMPISTRM128MEM:
19046 case X86::VPCMPISTRM128MEM:
19047 case X86::PCMPESTRM128REG:
19048 case X86::VPCMPESTRM128REG:
19049 case X86::PCMPESTRM128MEM:
19050 case X86::VPCMPESTRM128MEM:
19051 assert(Subtarget->hasSSE42() &&
19052 "Target must have SSE4.2 or AVX features enabled");
19053 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19055 // String/text processing lowering.
19056 case X86::PCMPISTRIREG:
19057 case X86::VPCMPISTRIREG:
19058 case X86::PCMPISTRIMEM:
19059 case X86::VPCMPISTRIMEM:
19060 case X86::PCMPESTRIREG:
19061 case X86::VPCMPESTRIREG:
19062 case X86::PCMPESTRIMEM:
19063 case X86::VPCMPESTRIMEM:
19064 assert(Subtarget->hasSSE42() &&
19065 "Target must have SSE4.2 or AVX features enabled");
19066 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19068 // Thread synchronization.
19070 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
19075 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
19077 case X86::VASTART_SAVE_XMM_REGS:
19078 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19080 case X86::VAARG_64:
19081 return EmitVAARG64WithCustomInserter(MI, BB);
19083 case X86::EH_SjLj_SetJmp32:
19084 case X86::EH_SjLj_SetJmp64:
19085 return emitEHSjLjSetJmp(MI, BB);
19087 case X86::EH_SjLj_LongJmp32:
19088 case X86::EH_SjLj_LongJmp64:
19089 return emitEHSjLjLongJmp(MI, BB);
19091 case TargetOpcode::STACKMAP:
19092 case TargetOpcode::PATCHPOINT:
19093 return emitPatchPoint(MI, BB);
19095 case X86::VFMADDPDr213r:
19096 case X86::VFMADDPSr213r:
19097 case X86::VFMADDSDr213r:
19098 case X86::VFMADDSSr213r:
19099 case X86::VFMSUBPDr213r:
19100 case X86::VFMSUBPSr213r:
19101 case X86::VFMSUBSDr213r:
19102 case X86::VFMSUBSSr213r:
19103 case X86::VFNMADDPDr213r:
19104 case X86::VFNMADDPSr213r:
19105 case X86::VFNMADDSDr213r:
19106 case X86::VFNMADDSSr213r:
19107 case X86::VFNMSUBPDr213r:
19108 case X86::VFNMSUBPSr213r:
19109 case X86::VFNMSUBSDr213r:
19110 case X86::VFNMSUBSSr213r:
19111 case X86::VFMADDPDr213rY:
19112 case X86::VFMADDPSr213rY:
19113 case X86::VFMSUBPDr213rY:
19114 case X86::VFMSUBPSr213rY:
19115 case X86::VFNMADDPDr213rY:
19116 case X86::VFNMADDPSr213rY:
19117 case X86::VFNMSUBPDr213rY:
19118 case X86::VFNMSUBPSr213rY:
19119 return emitFMA3Instr(MI, BB);
19123 //===----------------------------------------------------------------------===//
19124 // X86 Optimization Hooks
19125 //===----------------------------------------------------------------------===//
19127 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19130 const SelectionDAG &DAG,
19131 unsigned Depth) const {
19132 unsigned BitWidth = KnownZero.getBitWidth();
19133 unsigned Opc = Op.getOpcode();
19134 assert((Opc >= ISD::BUILTIN_OP_END ||
19135 Opc == ISD::INTRINSIC_WO_CHAIN ||
19136 Opc == ISD::INTRINSIC_W_CHAIN ||
19137 Opc == ISD::INTRINSIC_VOID) &&
19138 "Should use MaskedValueIsZero if you don't know whether Op"
19139 " is a target node!");
19141 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19155 // These nodes' second result is a boolean.
19156 if (Op.getResNo() == 0)
19159 case X86ISD::SETCC:
19160 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19162 case ISD::INTRINSIC_WO_CHAIN: {
19163 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19164 unsigned NumLoBits = 0;
19167 case Intrinsic::x86_sse_movmsk_ps:
19168 case Intrinsic::x86_avx_movmsk_ps_256:
19169 case Intrinsic::x86_sse2_movmsk_pd:
19170 case Intrinsic::x86_avx_movmsk_pd_256:
19171 case Intrinsic::x86_mmx_pmovmskb:
19172 case Intrinsic::x86_sse2_pmovmskb_128:
19173 case Intrinsic::x86_avx2_pmovmskb: {
19174 // High bits of movmskp{s|d}, pmovmskb are known zero.
19176 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19177 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19178 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19179 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19180 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19181 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19182 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19183 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19185 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19194 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19196 const SelectionDAG &,
19197 unsigned Depth) const {
19198 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19199 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19200 return Op.getValueType().getScalarType().getSizeInBits();
19206 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19207 /// node is a GlobalAddress + offset.
19208 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19209 const GlobalValue* &GA,
19210 int64_t &Offset) const {
19211 if (N->getOpcode() == X86ISD::Wrapper) {
19212 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19213 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19214 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19218 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19221 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19222 /// same as extracting the high 128-bit part of 256-bit vector and then
19223 /// inserting the result into the low part of a new 256-bit vector
19224 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19225 EVT VT = SVOp->getValueType(0);
19226 unsigned NumElems = VT.getVectorNumElements();
19228 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19229 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19230 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19231 SVOp->getMaskElt(j) >= 0)
19237 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19238 /// same as extracting the low 128-bit part of 256-bit vector and then
19239 /// inserting the result into the high part of a new 256-bit vector
19240 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19241 EVT VT = SVOp->getValueType(0);
19242 unsigned NumElems = VT.getVectorNumElements();
19244 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19245 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19246 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19247 SVOp->getMaskElt(j) >= 0)
19253 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19254 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19255 TargetLowering::DAGCombinerInfo &DCI,
19256 const X86Subtarget* Subtarget) {
19258 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19259 SDValue V1 = SVOp->getOperand(0);
19260 SDValue V2 = SVOp->getOperand(1);
19261 EVT VT = SVOp->getValueType(0);
19262 unsigned NumElems = VT.getVectorNumElements();
19264 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19265 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19269 // V UNDEF BUILD_VECTOR UNDEF
19271 // CONCAT_VECTOR CONCAT_VECTOR
19274 // RESULT: V + zero extended
19276 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19277 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19278 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19281 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19284 // To match the shuffle mask, the first half of the mask should
19285 // be exactly the first vector, and all the rest a splat with the
19286 // first element of the second one.
19287 for (unsigned i = 0; i != NumElems/2; ++i)
19288 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19289 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19292 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19293 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19294 if (Ld->hasNUsesOfValue(1, 0)) {
19295 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19296 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19298 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19300 Ld->getPointerInfo(),
19301 Ld->getAlignment(),
19302 false/*isVolatile*/, true/*ReadMem*/,
19303 false/*WriteMem*/);
19305 // Make sure the newly-created LOAD is in the same position as Ld in
19306 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19307 // and update uses of Ld's output chain to use the TokenFactor.
19308 if (Ld->hasAnyUseOfValue(1)) {
19309 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19310 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19311 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19312 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19313 SDValue(ResNode.getNode(), 1));
19316 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19320 // Emit a zeroed vector and insert the desired subvector on its
19322 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19323 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19324 return DCI.CombineTo(N, InsV);
19327 //===--------------------------------------------------------------------===//
19328 // Combine some shuffles into subvector extracts and inserts:
19331 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19332 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19333 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19334 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19335 return DCI.CombineTo(N, InsV);
19338 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19339 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19340 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19341 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19342 return DCI.CombineTo(N, InsV);
19348 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19351 /// This is the leaf of the recursive combinine below. When we have found some
19352 /// chain of single-use x86 shuffle instructions and accumulated the combined
19353 /// shuffle mask represented by them, this will try to pattern match that mask
19354 /// into either a single instruction if there is a special purpose instruction
19355 /// for this operation, or into a PSHUFB instruction which is a fully general
19356 /// instruction but should only be used to replace chains over a certain depth.
19357 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19358 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19359 TargetLowering::DAGCombinerInfo &DCI,
19360 const X86Subtarget *Subtarget) {
19361 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19363 // Find the operand that enters the chain. Note that multiple uses are OK
19364 // here, we're not going to remove the operand we find.
19365 SDValue Input = Op.getOperand(0);
19366 while (Input.getOpcode() == ISD::BITCAST)
19367 Input = Input.getOperand(0);
19369 MVT VT = Input.getSimpleValueType();
19370 MVT RootVT = Root.getSimpleValueType();
19373 // Just remove no-op shuffle masks.
19374 if (Mask.size() == 1) {
19375 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19380 // Use the float domain if the operand type is a floating point type.
19381 bool FloatDomain = VT.isFloatingPoint();
19383 // If we don't have access to VEX encodings, the generic PSHUF instructions
19384 // are preferable to some of the specialized forms despite requiring one more
19385 // byte to encode because they can implicitly copy.
19387 // IF we *do* have VEX encodings, than we can use shorter, more specific
19388 // shuffle instructions freely as they can copy due to the extra register
19390 if (Subtarget->hasAVX()) {
19391 // We have both floating point and integer variants of shuffles that dup
19392 // either the low or high half of the vector.
19393 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19394 bool Lo = Mask.equals(0, 0);
19395 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
19396 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
19397 if (Depth == 1 && Root->getOpcode() == Shuffle)
19398 return false; // Nothing to do!
19399 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
19400 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19401 DCI.AddToWorklist(Op.getNode());
19402 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19403 DCI.AddToWorklist(Op.getNode());
19404 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19409 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
19411 // For the integer domain we have specialized instructions for duplicating
19412 // any element size from the low or high half.
19413 if (!FloatDomain &&
19414 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
19415 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19416 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19417 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19418 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19420 bool Lo = Mask[0] == 0;
19421 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19422 if (Depth == 1 && Root->getOpcode() == Shuffle)
19423 return false; // Nothing to do!
19425 switch (Mask.size()) {
19426 case 4: ShuffleVT = MVT::v4i32; break;
19427 case 8: ShuffleVT = MVT::v8i16; break;
19428 case 16: ShuffleVT = MVT::v16i8; break;
19430 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19431 DCI.AddToWorklist(Op.getNode());
19432 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19433 DCI.AddToWorklist(Op.getNode());
19434 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19440 // Don't try to re-form single instruction chains under any circumstances now
19441 // that we've done encoding canonicalization for them.
19445 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19446 // can replace them with a single PSHUFB instruction profitably. Intel's
19447 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19448 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19449 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19450 SmallVector<SDValue, 16> PSHUFBMask;
19451 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19452 int Ratio = 16 / Mask.size();
19453 for (unsigned i = 0; i < 16; ++i) {
19454 int M = Mask[i / Ratio] != SM_SentinelZero
19455 ? Ratio * Mask[i / Ratio] + i % Ratio
19457 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19459 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19460 DCI.AddToWorklist(Op.getNode());
19461 SDValue PSHUFBMaskOp =
19462 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19463 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19464 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19465 DCI.AddToWorklist(Op.getNode());
19466 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19471 // Failed to find any combines.
19475 /// \brief Fully generic combining of x86 shuffle instructions.
19477 /// This should be the last combine run over the x86 shuffle instructions. Once
19478 /// they have been fully optimized, this will recursively consider all chains
19479 /// of single-use shuffle instructions, build a generic model of the cumulative
19480 /// shuffle operation, and check for simpler instructions which implement this
19481 /// operation. We use this primarily for two purposes:
19483 /// 1) Collapse generic shuffles to specialized single instructions when
19484 /// equivalent. In most cases, this is just an encoding size win, but
19485 /// sometimes we will collapse multiple generic shuffles into a single
19486 /// special-purpose shuffle.
19487 /// 2) Look for sequences of shuffle instructions with 3 or more total
19488 /// instructions, and replace them with the slightly more expensive SSSE3
19489 /// PSHUFB instruction if available. We do this as the last combining step
19490 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19491 /// a suitable short sequence of other instructions. The PHUFB will either
19492 /// use a register or have to read from memory and so is slightly (but only
19493 /// slightly) more expensive than the other shuffle instructions.
19495 /// Because this is inherently a quadratic operation (for each shuffle in
19496 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19497 /// This should never be an issue in practice as the shuffle lowering doesn't
19498 /// produce sequences of more than 8 instructions.
19500 /// FIXME: We will currently miss some cases where the redundant shuffling
19501 /// would simplify under the threshold for PSHUFB formation because of
19502 /// combine-ordering. To fix this, we should do the redundant instruction
19503 /// combining in this recursive walk.
19504 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19505 ArrayRef<int> RootMask,
19506 int Depth, bool HasPSHUFB,
19508 TargetLowering::DAGCombinerInfo &DCI,
19509 const X86Subtarget *Subtarget) {
19510 // Bound the depth of our recursive combine because this is ultimately
19511 // quadratic in nature.
19515 // Directly rip through bitcasts to find the underlying operand.
19516 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19517 Op = Op.getOperand(0);
19519 MVT VT = Op.getSimpleValueType();
19520 if (!VT.isVector())
19521 return false; // Bail if we hit a non-vector.
19522 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19523 // version should be added.
19524 if (VT.getSizeInBits() != 128)
19527 assert(Root.getSimpleValueType().isVector() &&
19528 "Shuffles operate on vector types!");
19529 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19530 "Can only combine shuffles of the same vector register size.");
19532 if (!isTargetShuffle(Op.getOpcode()))
19534 SmallVector<int, 16> OpMask;
19536 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19537 // We only can combine unary shuffles which we can decode the mask for.
19538 if (!HaveMask || !IsUnary)
19541 assert(VT.getVectorNumElements() == OpMask.size() &&
19542 "Different mask size from vector size!");
19543 assert(((RootMask.size() > OpMask.size() &&
19544 RootMask.size() % OpMask.size() == 0) ||
19545 (OpMask.size() > RootMask.size() &&
19546 OpMask.size() % RootMask.size() == 0) ||
19547 OpMask.size() == RootMask.size()) &&
19548 "The smaller number of elements must divide the larger.");
19549 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19550 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19551 assert(((RootRatio == 1 && OpRatio == 1) ||
19552 (RootRatio == 1) != (OpRatio == 1)) &&
19553 "Must not have a ratio for both incoming and op masks!");
19555 SmallVector<int, 16> Mask;
19556 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19558 // Merge this shuffle operation's mask into our accumulated mask. Note that
19559 // this shuffle's mask will be the first applied to the input, followed by the
19560 // root mask to get us all the way to the root value arrangement. The reason
19561 // for this order is that we are recursing up the operation chain.
19562 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19563 int RootIdx = i / RootRatio;
19564 if (RootMask[RootIdx] == SM_SentinelZero) {
19565 // This is a zero-ed lane, we're done.
19566 Mask.push_back(SM_SentinelZero);
19570 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19571 int OpIdx = RootMaskedIdx / OpRatio;
19572 if (OpMask[OpIdx] == SM_SentinelZero) {
19573 // The incoming lanes are zero, it doesn't matter which ones we are using.
19574 Mask.push_back(SM_SentinelZero);
19578 // Ok, we have non-zero lanes, map them through.
19579 Mask.push_back(OpMask[OpIdx] * OpRatio +
19580 RootMaskedIdx % OpRatio);
19583 // See if we can recurse into the operand to combine more things.
19584 switch (Op.getOpcode()) {
19585 case X86ISD::PSHUFB:
19587 case X86ISD::PSHUFD:
19588 case X86ISD::PSHUFHW:
19589 case X86ISD::PSHUFLW:
19590 if (Op.getOperand(0).hasOneUse() &&
19591 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19592 HasPSHUFB, DAG, DCI, Subtarget))
19596 case X86ISD::UNPCKL:
19597 case X86ISD::UNPCKH:
19598 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19599 // We can't check for single use, we have to check that this shuffle is the only user.
19600 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19601 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19602 HasPSHUFB, DAG, DCI, Subtarget))
19607 // Minor canonicalization of the accumulated shuffle mask to make it easier
19608 // to match below. All this does is detect masks with squential pairs of
19609 // elements, and shrink them to the half-width mask. It does this in a loop
19610 // so it will reduce the size of the mask to the minimal width mask which
19611 // performs an equivalent shuffle.
19612 while (Mask.size() > 1 && canWidenShuffleElements(Mask)) {
19613 for (int i = 0, e = Mask.size() / 2; i < e; ++i)
19614 Mask[i] = Mask[2 * i] / 2;
19615 Mask.resize(Mask.size() / 2);
19618 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19622 /// \brief Get the PSHUF-style mask from PSHUF node.
19624 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19625 /// PSHUF-style masks that can be reused with such instructions.
19626 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19627 SmallVector<int, 4> Mask;
19629 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19633 switch (N.getOpcode()) {
19634 case X86ISD::PSHUFD:
19636 case X86ISD::PSHUFLW:
19639 case X86ISD::PSHUFHW:
19640 Mask.erase(Mask.begin(), Mask.begin() + 4);
19641 for (int &M : Mask)
19645 llvm_unreachable("No valid shuffle instruction found!");
19649 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19651 /// We walk up the chain and look for a combinable shuffle, skipping over
19652 /// shuffles that we could hoist this shuffle's transformation past without
19653 /// altering anything.
19654 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19656 TargetLowering::DAGCombinerInfo &DCI) {
19657 assert(N.getOpcode() == X86ISD::PSHUFD &&
19658 "Called with something other than an x86 128-bit half shuffle!");
19661 // Walk up a single-use chain looking for a combinable shuffle.
19662 SDValue V = N.getOperand(0);
19663 for (; V.hasOneUse(); V = V.getOperand(0)) {
19664 switch (V.getOpcode()) {
19666 return false; // Nothing combined!
19669 // Skip bitcasts as we always know the type for the target specific
19673 case X86ISD::PSHUFD:
19674 // Found another dword shuffle.
19677 case X86ISD::PSHUFLW:
19678 // Check that the low words (being shuffled) are the identity in the
19679 // dword shuffle, and the high words are self-contained.
19680 if (Mask[0] != 0 || Mask[1] != 1 ||
19681 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19686 case X86ISD::PSHUFHW:
19687 // Check that the high words (being shuffled) are the identity in the
19688 // dword shuffle, and the low words are self-contained.
19689 if (Mask[2] != 2 || Mask[3] != 3 ||
19690 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19695 case X86ISD::UNPCKL:
19696 case X86ISD::UNPCKH:
19697 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19698 // shuffle into a preceding word shuffle.
19699 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19702 // Search for a half-shuffle which we can combine with.
19703 unsigned CombineOp =
19704 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19705 if (V.getOperand(0) != V.getOperand(1) ||
19706 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19708 V = V.getOperand(0);
19710 switch (V.getOpcode()) {
19712 return false; // Nothing to combine.
19714 case X86ISD::PSHUFLW:
19715 case X86ISD::PSHUFHW:
19716 if (V.getOpcode() == CombineOp)
19721 V = V.getOperand(0);
19725 } while (V.hasOneUse());
19728 // Break out of the loop if we break out of the switch.
19732 if (!V.hasOneUse())
19733 // We fell out of the loop without finding a viable combining instruction.
19736 // Record the old value to use in RAUW-ing.
19739 // Merge this node's mask and our incoming mask.
19740 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19741 for (int &M : Mask)
19743 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19744 getV4X86ShuffleImm8ForMask(Mask, DAG));
19746 // It is possible that one of the combinable shuffles was completely absorbed
19747 // by the other, just replace it and revisit all users in that case.
19748 if (Old.getNode() == V.getNode()) {
19749 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
19753 // Replace N with its operand as we're going to combine that shuffle away.
19754 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
19756 // Replace the combinable shuffle with the combined one, updating all users
19757 // so that we re-evaluate the chain here.
19758 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19762 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19764 /// We walk up the chain, skipping shuffles of the other half and looking
19765 /// through shuffles which switch halves trying to find a shuffle of the same
19766 /// pair of dwords.
19767 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19769 TargetLowering::DAGCombinerInfo &DCI) {
19771 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19772 "Called with something other than an x86 128-bit half shuffle!");
19774 unsigned CombineOpcode = N.getOpcode();
19776 // Walk up a single-use chain looking for a combinable shuffle.
19777 SDValue V = N.getOperand(0);
19778 for (; V.hasOneUse(); V = V.getOperand(0)) {
19779 switch (V.getOpcode()) {
19781 return false; // Nothing combined!
19784 // Skip bitcasts as we always know the type for the target specific
19788 case X86ISD::PSHUFLW:
19789 case X86ISD::PSHUFHW:
19790 if (V.getOpcode() == CombineOpcode)
19793 // Other-half shuffles are no-ops.
19796 // Break out of the loop if we break out of the switch.
19800 if (!V.hasOneUse())
19801 // We fell out of the loop without finding a viable combining instruction.
19804 // Combine away the bottom node as its shuffle will be accumulated into
19805 // a preceding shuffle.
19806 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19808 // Record the old value.
19811 // Merge this node's mask and our incoming mask (adjusted to account for all
19812 // the pshufd instructions encountered).
19813 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19814 for (int &M : Mask)
19816 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19817 getV4X86ShuffleImm8ForMask(Mask, DAG));
19819 // Check that the shuffles didn't cancel each other out. If not, we need to
19820 // combine to the new one.
19822 // Replace the combinable shuffle with the combined one, updating all users
19823 // so that we re-evaluate the chain here.
19824 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19829 /// \brief Try to combine x86 target specific shuffles.
19830 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19831 TargetLowering::DAGCombinerInfo &DCI,
19832 const X86Subtarget *Subtarget) {
19834 MVT VT = N.getSimpleValueType();
19835 SmallVector<int, 4> Mask;
19837 switch (N.getOpcode()) {
19838 case X86ISD::PSHUFD:
19839 case X86ISD::PSHUFLW:
19840 case X86ISD::PSHUFHW:
19841 Mask = getPSHUFShuffleMask(N);
19842 assert(Mask.size() == 4);
19848 // Nuke no-op shuffles that show up after combining.
19849 if (isNoopShuffleMask(Mask))
19850 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19852 // Look for simplifications involving one or two shuffle instructions.
19853 SDValue V = N.getOperand(0);
19854 switch (N.getOpcode()) {
19857 case X86ISD::PSHUFLW:
19858 case X86ISD::PSHUFHW:
19859 assert(VT == MVT::v8i16);
19862 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19863 return SDValue(); // We combined away this shuffle, so we're done.
19865 // See if this reduces to a PSHUFD which is no more expensive and can
19866 // combine with more operations.
19867 if (canWidenShuffleElements(Mask)) {
19868 int DMask[] = {-1, -1, -1, -1};
19869 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19870 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19871 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19872 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19873 DCI.AddToWorklist(V.getNode());
19874 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19875 getV4X86ShuffleImm8ForMask(DMask, DAG));
19876 DCI.AddToWorklist(V.getNode());
19877 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19880 // Look for shuffle patterns which can be implemented as a single unpack.
19881 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19882 // only works when we have a PSHUFD followed by two half-shuffles.
19883 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19884 (V.getOpcode() == X86ISD::PSHUFLW ||
19885 V.getOpcode() == X86ISD::PSHUFHW) &&
19886 V.getOpcode() != N.getOpcode() &&
19888 SDValue D = V.getOperand(0);
19889 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19890 D = D.getOperand(0);
19891 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19892 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19893 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19894 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19895 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19897 for (int i = 0; i < 4; ++i) {
19898 WordMask[i + NOffset] = Mask[i] + NOffset;
19899 WordMask[i + VOffset] = VMask[i] + VOffset;
19901 // Map the word mask through the DWord mask.
19903 for (int i = 0; i < 8; ++i)
19904 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19905 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19906 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19907 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19908 std::begin(UnpackLoMask)) ||
19909 std::equal(std::begin(MappedMask), std::end(MappedMask),
19910 std::begin(UnpackHiMask))) {
19911 // We can replace all three shuffles with an unpack.
19912 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19913 DCI.AddToWorklist(V.getNode());
19914 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19916 DL, MVT::v8i16, V, V);
19923 case X86ISD::PSHUFD:
19924 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19925 return SDValue(); // We combined away this shuffle.
19933 /// PerformShuffleCombine - Performs several different shuffle combines.
19934 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19935 TargetLowering::DAGCombinerInfo &DCI,
19936 const X86Subtarget *Subtarget) {
19938 SDValue N0 = N->getOperand(0);
19939 SDValue N1 = N->getOperand(1);
19940 EVT VT = N->getValueType(0);
19942 // Don't create instructions with illegal types after legalize types has run.
19943 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19944 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19947 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19948 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19949 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19950 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19952 // During Type Legalization, when promoting illegal vector types,
19953 // the backend might introduce new shuffle dag nodes and bitcasts.
19955 // This code performs the following transformation:
19956 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19957 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19959 // We do this only if both the bitcast and the BINOP dag nodes have
19960 // one use. Also, perform this transformation only if the new binary
19961 // operation is legal. This is to avoid introducing dag nodes that
19962 // potentially need to be further expanded (or custom lowered) into a
19963 // less optimal sequence of dag nodes.
19964 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19965 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19966 N0.getOpcode() == ISD::BITCAST) {
19967 SDValue BC0 = N0.getOperand(0);
19968 EVT SVT = BC0.getValueType();
19969 unsigned Opcode = BC0.getOpcode();
19970 unsigned NumElts = VT.getVectorNumElements();
19972 if (BC0.hasOneUse() && SVT.isVector() &&
19973 SVT.getVectorNumElements() * 2 == NumElts &&
19974 TLI.isOperationLegal(Opcode, VT)) {
19975 bool CanFold = false;
19987 unsigned SVTNumElts = SVT.getVectorNumElements();
19988 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19989 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19990 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19991 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19992 CanFold = SVOp->getMaskElt(i) < 0;
19995 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19996 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19997 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19998 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20003 // Only handle 128 wide vector from here on.
20004 if (!VT.is128BitVector())
20007 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20008 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20009 // consecutive, non-overlapping, and in the right order.
20010 SmallVector<SDValue, 16> Elts;
20011 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20012 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20014 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20018 if (isTargetShuffle(N->getOpcode())) {
20020 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20021 if (Shuffle.getNode())
20024 // Try recursively combining arbitrary sequences of x86 shuffle
20025 // instructions into higher-order shuffles. We do this after combining
20026 // specific PSHUF instruction sequences into their minimal form so that we
20027 // can evaluate how many specialized shuffle instructions are involved in
20028 // a particular chain.
20029 SmallVector<int, 1> NonceMask; // Just a placeholder.
20030 NonceMask.push_back(0);
20031 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20032 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20034 return SDValue(); // This routine will use CombineTo to replace N.
20040 /// PerformTruncateCombine - Converts truncate operation to
20041 /// a sequence of vector shuffle operations.
20042 /// It is possible when we truncate 256-bit vector to 128-bit vector
20043 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20044 TargetLowering::DAGCombinerInfo &DCI,
20045 const X86Subtarget *Subtarget) {
20049 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20050 /// specific shuffle of a load can be folded into a single element load.
20051 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20052 /// shuffles have been customed lowered so we need to handle those here.
20053 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20054 TargetLowering::DAGCombinerInfo &DCI) {
20055 if (DCI.isBeforeLegalizeOps())
20058 SDValue InVec = N->getOperand(0);
20059 SDValue EltNo = N->getOperand(1);
20061 if (!isa<ConstantSDNode>(EltNo))
20064 EVT VT = InVec.getValueType();
20066 bool HasShuffleIntoBitcast = false;
20067 if (InVec.getOpcode() == ISD::BITCAST) {
20068 // Don't duplicate a load with other uses.
20069 if (!InVec.hasOneUse())
20071 EVT BCVT = InVec.getOperand(0).getValueType();
20072 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
20074 InVec = InVec.getOperand(0);
20075 HasShuffleIntoBitcast = true;
20078 if (!isTargetShuffle(InVec.getOpcode()))
20081 // Don't duplicate a load with other uses.
20082 if (!InVec.hasOneUse())
20085 SmallVector<int, 16> ShuffleMask;
20087 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
20091 // Select the input vector, guarding against out of range extract vector.
20092 unsigned NumElems = VT.getVectorNumElements();
20093 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20094 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20095 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20096 : InVec.getOperand(1);
20098 // If inputs to shuffle are the same for both ops, then allow 2 uses
20099 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20101 if (LdNode.getOpcode() == ISD::BITCAST) {
20102 // Don't duplicate a load with other uses.
20103 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20106 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20107 LdNode = LdNode.getOperand(0);
20110 if (!ISD::isNormalLoad(LdNode.getNode()))
20113 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20115 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20118 if (HasShuffleIntoBitcast) {
20119 // If there's a bitcast before the shuffle, check if the load type and
20120 // alignment is valid.
20121 unsigned Align = LN0->getAlignment();
20122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20123 unsigned NewAlign = TLI.getDataLayout()->
20124 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
20126 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
20130 // All checks match so transform back to vector_shuffle so that DAG combiner
20131 // can finish the job
20134 // Create shuffle node taking into account the case that its a unary shuffle
20135 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
20136 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
20137 InVec.getOperand(0), Shuffle,
20139 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
20140 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20144 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20145 /// generation and convert it from being a bunch of shuffles and extracts
20146 /// to a simple store and scalar loads to extract the elements.
20147 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20148 TargetLowering::DAGCombinerInfo &DCI) {
20149 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20150 if (NewOp.getNode())
20153 SDValue InputVector = N->getOperand(0);
20155 // Detect whether we are trying to convert from mmx to i32 and the bitcast
20156 // from mmx to v2i32 has a single usage.
20157 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
20158 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
20159 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
20160 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20161 N->getValueType(0),
20162 InputVector.getNode()->getOperand(0));
20164 // Only operate on vectors of 4 elements, where the alternative shuffling
20165 // gets to be more expensive.
20166 if (InputVector.getValueType() != MVT::v4i32)
20169 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20170 // single use which is a sign-extend or zero-extend, and all elements are
20172 SmallVector<SDNode *, 4> Uses;
20173 unsigned ExtractedElements = 0;
20174 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20175 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20176 if (UI.getUse().getResNo() != InputVector.getResNo())
20179 SDNode *Extract = *UI;
20180 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20183 if (Extract->getValueType(0) != MVT::i32)
20185 if (!Extract->hasOneUse())
20187 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20188 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20190 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20193 // Record which element was extracted.
20194 ExtractedElements |=
20195 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20197 Uses.push_back(Extract);
20200 // If not all the elements were used, this may not be worthwhile.
20201 if (ExtractedElements != 15)
20204 // Ok, we've now decided to do the transformation.
20205 SDLoc dl(InputVector);
20207 // Store the value to a temporary stack slot.
20208 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20209 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20210 MachinePointerInfo(), false, false, 0);
20212 // Replace each use (extract) with a load of the appropriate element.
20213 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20214 UE = Uses.end(); UI != UE; ++UI) {
20215 SDNode *Extract = *UI;
20217 // cOMpute the element's address.
20218 SDValue Idx = Extract->getOperand(1);
20220 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
20221 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
20222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20223 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20225 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20226 StackPtr, OffsetVal);
20228 // Load the scalar.
20229 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
20230 ScalarAddr, MachinePointerInfo(),
20231 false, false, false, 0);
20233 // Replace the exact with the load.
20234 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
20237 // The replacement was made in place; don't return anything.
20241 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20242 static std::pair<unsigned, bool>
20243 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20244 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20245 if (!VT.isVector())
20246 return std::make_pair(0, false);
20248 bool NeedSplit = false;
20249 switch (VT.getSimpleVT().SimpleTy) {
20250 default: return std::make_pair(0, false);
20254 if (!Subtarget->hasAVX2())
20256 if (!Subtarget->hasAVX())
20257 return std::make_pair(0, false);
20262 if (!Subtarget->hasSSE2())
20263 return std::make_pair(0, false);
20266 // SSE2 has only a small subset of the operations.
20267 bool hasUnsigned = Subtarget->hasSSE41() ||
20268 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20269 bool hasSigned = Subtarget->hasSSE41() ||
20270 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20272 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20275 // Check for x CC y ? x : y.
20276 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20277 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20282 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20285 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20288 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20291 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20293 // Check for x CC y ? y : x -- a min/max with reversed arms.
20294 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20295 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20300 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20303 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20306 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20309 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20313 return std::make_pair(Opc, NeedSplit);
20317 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20318 const X86Subtarget *Subtarget) {
20320 SDValue Cond = N->getOperand(0);
20321 SDValue LHS = N->getOperand(1);
20322 SDValue RHS = N->getOperand(2);
20324 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20325 SDValue CondSrc = Cond->getOperand(0);
20326 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20327 Cond = CondSrc->getOperand(0);
20330 MVT VT = N->getSimpleValueType(0);
20331 MVT EltVT = VT.getVectorElementType();
20332 unsigned NumElems = VT.getVectorNumElements();
20333 // There is no blend with immediate in AVX-512.
20334 if (VT.is512BitVector())
20337 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
20339 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
20342 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20345 unsigned MaskValue = 0;
20346 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20349 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20350 for (unsigned i = 0; i < NumElems; ++i) {
20351 // Be sure we emit undef where we can.
20352 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20353 ShuffleMask[i] = -1;
20355 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20358 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20361 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20363 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20364 TargetLowering::DAGCombinerInfo &DCI,
20365 const X86Subtarget *Subtarget) {
20367 SDValue Cond = N->getOperand(0);
20368 // Get the LHS/RHS of the select.
20369 SDValue LHS = N->getOperand(1);
20370 SDValue RHS = N->getOperand(2);
20371 EVT VT = LHS.getValueType();
20372 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20374 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20375 // instructions match the semantics of the common C idiom x<y?x:y but not
20376 // x<=y?x:y, because of how they handle negative zero (which can be
20377 // ignored in unsafe-math mode).
20378 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20379 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20380 (Subtarget->hasSSE2() ||
20381 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20382 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20384 unsigned Opcode = 0;
20385 // Check for x CC y ? x : y.
20386 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20387 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20391 // Converting this to a min would handle NaNs incorrectly, and swapping
20392 // the operands would cause it to handle comparisons between positive
20393 // and negative zero incorrectly.
20394 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20395 if (!DAG.getTarget().Options.UnsafeFPMath &&
20396 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20398 std::swap(LHS, RHS);
20400 Opcode = X86ISD::FMIN;
20403 // Converting this to a min would handle comparisons between positive
20404 // and negative zero incorrectly.
20405 if (!DAG.getTarget().Options.UnsafeFPMath &&
20406 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20408 Opcode = X86ISD::FMIN;
20411 // Converting this to a min would handle both negative zeros and NaNs
20412 // incorrectly, but we can swap the operands to fix both.
20413 std::swap(LHS, RHS);
20417 Opcode = X86ISD::FMIN;
20421 // Converting this to a max would handle comparisons between positive
20422 // and negative zero incorrectly.
20423 if (!DAG.getTarget().Options.UnsafeFPMath &&
20424 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20426 Opcode = X86ISD::FMAX;
20429 // Converting this to a max would handle NaNs incorrectly, and swapping
20430 // the operands would cause it to handle comparisons between positive
20431 // and negative zero incorrectly.
20432 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20433 if (!DAG.getTarget().Options.UnsafeFPMath &&
20434 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20436 std::swap(LHS, RHS);
20438 Opcode = X86ISD::FMAX;
20441 // Converting this to a max would handle both negative zeros and NaNs
20442 // incorrectly, but we can swap the operands to fix both.
20443 std::swap(LHS, RHS);
20447 Opcode = X86ISD::FMAX;
20450 // Check for x CC y ? y : x -- a min/max with reversed arms.
20451 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20452 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20456 // Converting this to a min would handle comparisons between positive
20457 // and negative zero incorrectly, and swapping the operands would
20458 // cause it to handle NaNs incorrectly.
20459 if (!DAG.getTarget().Options.UnsafeFPMath &&
20460 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20461 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20463 std::swap(LHS, RHS);
20465 Opcode = X86ISD::FMIN;
20468 // Converting this to a min would handle NaNs incorrectly.
20469 if (!DAG.getTarget().Options.UnsafeFPMath &&
20470 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20472 Opcode = X86ISD::FMIN;
20475 // Converting this to a min would handle both negative zeros and NaNs
20476 // incorrectly, but we can swap the operands to fix both.
20477 std::swap(LHS, RHS);
20481 Opcode = X86ISD::FMIN;
20485 // Converting this to a max would handle NaNs incorrectly.
20486 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20488 Opcode = X86ISD::FMAX;
20491 // Converting this to a max would handle comparisons between positive
20492 // and negative zero incorrectly, and swapping the operands would
20493 // cause it to handle NaNs incorrectly.
20494 if (!DAG.getTarget().Options.UnsafeFPMath &&
20495 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20496 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20498 std::swap(LHS, RHS);
20500 Opcode = X86ISD::FMAX;
20503 // Converting this to a max would handle both negative zeros and NaNs
20504 // incorrectly, but we can swap the operands to fix both.
20505 std::swap(LHS, RHS);
20509 Opcode = X86ISD::FMAX;
20515 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20518 EVT CondVT = Cond.getValueType();
20519 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20520 CondVT.getVectorElementType() == MVT::i1) {
20521 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20522 // lowering on AVX-512. In this case we convert it to
20523 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20524 // The same situation for all 128 and 256-bit vectors of i8 and i16
20525 EVT OpVT = LHS.getValueType();
20526 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20527 (OpVT.getVectorElementType() == MVT::i8 ||
20528 OpVT.getVectorElementType() == MVT::i16)) {
20529 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20530 DCI.AddToWorklist(Cond.getNode());
20531 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20534 // If this is a select between two integer constants, try to do some
20536 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20537 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20538 // Don't do this for crazy integer types.
20539 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20540 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20541 // so that TrueC (the true value) is larger than FalseC.
20542 bool NeedsCondInvert = false;
20544 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20545 // Efficiently invertible.
20546 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20547 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20548 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20549 NeedsCondInvert = true;
20550 std::swap(TrueC, FalseC);
20553 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20554 if (FalseC->getAPIntValue() == 0 &&
20555 TrueC->getAPIntValue().isPowerOf2()) {
20556 if (NeedsCondInvert) // Invert the condition if needed.
20557 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20558 DAG.getConstant(1, Cond.getValueType()));
20560 // Zero extend the condition if needed.
20561 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20563 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20564 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20565 DAG.getConstant(ShAmt, MVT::i8));
20568 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20569 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20570 if (NeedsCondInvert) // Invert the condition if needed.
20571 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20572 DAG.getConstant(1, Cond.getValueType()));
20574 // Zero extend the condition if needed.
20575 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20576 FalseC->getValueType(0), Cond);
20577 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20578 SDValue(FalseC, 0));
20581 // Optimize cases that will turn into an LEA instruction. This requires
20582 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20583 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20584 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20585 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20587 bool isFastMultiplier = false;
20589 switch ((unsigned char)Diff) {
20591 case 1: // result = add base, cond
20592 case 2: // result = lea base( , cond*2)
20593 case 3: // result = lea base(cond, cond*2)
20594 case 4: // result = lea base( , cond*4)
20595 case 5: // result = lea base(cond, cond*4)
20596 case 8: // result = lea base( , cond*8)
20597 case 9: // result = lea base(cond, cond*8)
20598 isFastMultiplier = true;
20603 if (isFastMultiplier) {
20604 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20605 if (NeedsCondInvert) // Invert the condition if needed.
20606 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20607 DAG.getConstant(1, Cond.getValueType()));
20609 // Zero extend the condition if needed.
20610 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20612 // Scale the condition by the difference.
20614 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20615 DAG.getConstant(Diff, Cond.getValueType()));
20617 // Add the base if non-zero.
20618 if (FalseC->getAPIntValue() != 0)
20619 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20620 SDValue(FalseC, 0));
20627 // Canonicalize max and min:
20628 // (x > y) ? x : y -> (x >= y) ? x : y
20629 // (x < y) ? x : y -> (x <= y) ? x : y
20630 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20631 // the need for an extra compare
20632 // against zero. e.g.
20633 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20635 // testl %edi, %edi
20637 // cmovgl %edi, %eax
20641 // cmovsl %eax, %edi
20642 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20643 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20644 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20645 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20650 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20651 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20652 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20653 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20658 // Early exit check
20659 if (!TLI.isTypeLegal(VT))
20662 // Match VSELECTs into subs with unsigned saturation.
20663 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20664 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20665 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20666 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20667 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20669 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20670 // left side invert the predicate to simplify logic below.
20672 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20674 CC = ISD::getSetCCInverse(CC, true);
20675 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20679 if (Other.getNode() && Other->getNumOperands() == 2 &&
20680 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20681 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20682 SDValue CondRHS = Cond->getOperand(1);
20684 // Look for a general sub with unsigned saturation first.
20685 // x >= y ? x-y : 0 --> subus x, y
20686 // x > y ? x-y : 0 --> subus x, y
20687 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20688 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20689 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20691 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20692 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20693 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20694 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20695 // If the RHS is a constant we have to reverse the const
20696 // canonicalization.
20697 // x > C-1 ? x+-C : 0 --> subus x, C
20698 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20699 CondRHSConst->getAPIntValue() ==
20700 (-OpRHSConst->getAPIntValue() - 1))
20701 return DAG.getNode(
20702 X86ISD::SUBUS, DL, VT, OpLHS,
20703 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20705 // Another special case: If C was a sign bit, the sub has been
20706 // canonicalized into a xor.
20707 // FIXME: Would it be better to use computeKnownBits to determine
20708 // whether it's safe to decanonicalize the xor?
20709 // x s< 0 ? x^C : 0 --> subus x, C
20710 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20711 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20712 OpRHSConst->getAPIntValue().isSignBit())
20713 // Note that we have to rebuild the RHS constant here to ensure we
20714 // don't rely on particular values of undef lanes.
20715 return DAG.getNode(
20716 X86ISD::SUBUS, DL, VT, OpLHS,
20717 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20722 // Try to match a min/max vector operation.
20723 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20724 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20725 unsigned Opc = ret.first;
20726 bool NeedSplit = ret.second;
20728 if (Opc && NeedSplit) {
20729 unsigned NumElems = VT.getVectorNumElements();
20730 // Extract the LHS vectors
20731 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20732 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20734 // Extract the RHS vectors
20735 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20736 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20738 // Create min/max for each subvector
20739 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20740 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20742 // Merge the result
20743 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20745 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20748 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20749 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20750 // Check if SETCC has already been promoted
20751 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20752 // Check that condition value type matches vselect operand type
20755 assert(Cond.getValueType().isVector() &&
20756 "vector select expects a vector selector!");
20758 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20759 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20761 if (!TValIsAllOnes && !FValIsAllZeros) {
20762 // Try invert the condition if true value is not all 1s and false value
20764 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20765 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20767 if (TValIsAllZeros || FValIsAllOnes) {
20768 SDValue CC = Cond.getOperand(2);
20769 ISD::CondCode NewCC =
20770 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20771 Cond.getOperand(0).getValueType().isInteger());
20772 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20773 std::swap(LHS, RHS);
20774 TValIsAllOnes = FValIsAllOnes;
20775 FValIsAllZeros = TValIsAllZeros;
20779 if (TValIsAllOnes || FValIsAllZeros) {
20782 if (TValIsAllOnes && FValIsAllZeros)
20784 else if (TValIsAllOnes)
20785 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20786 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20787 else if (FValIsAllZeros)
20788 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20789 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20791 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20795 // Try to fold this VSELECT into a MOVSS/MOVSD
20796 if (N->getOpcode() == ISD::VSELECT &&
20797 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20798 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20799 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20800 bool CanFold = false;
20801 unsigned NumElems = Cond.getNumOperands();
20805 if (isZero(Cond.getOperand(0))) {
20808 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20809 // fold (vselect <0,-1> -> (movsd A, B)
20810 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20811 CanFold = isAllOnes(Cond.getOperand(i));
20812 } else if (isAllOnes(Cond.getOperand(0))) {
20816 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20817 // fold (vselect <-1,0> -> (movsd B, A)
20818 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20819 CanFold = isZero(Cond.getOperand(i));
20823 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20824 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20825 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20828 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20829 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20830 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20831 // (v2i64 (bitcast B)))))
20833 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20834 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20835 // (v2f64 (bitcast B)))))
20837 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20838 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20839 // (v2i64 (bitcast A)))))
20841 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20842 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20843 // (v2f64 (bitcast A)))))
20845 CanFold = (isZero(Cond.getOperand(0)) &&
20846 isZero(Cond.getOperand(1)) &&
20847 isAllOnes(Cond.getOperand(2)) &&
20848 isAllOnes(Cond.getOperand(3)));
20850 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20851 isAllOnes(Cond.getOperand(1)) &&
20852 isZero(Cond.getOperand(2)) &&
20853 isZero(Cond.getOperand(3))) {
20855 std::swap(LHS, RHS);
20859 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20860 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20861 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20862 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20864 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20870 // If we know that this node is legal then we know that it is going to be
20871 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20872 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20873 // to simplify previous instructions.
20874 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20875 !DCI.isBeforeLegalize() &&
20876 // We explicitly check against v8i16 and v16i16 because, although
20877 // they're marked as Custom, they might only be legal when Cond is a
20878 // build_vector of constants. This will be taken care in a later
20880 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20881 VT != MVT::v8i16)) {
20882 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20884 // Don't optimize vector selects that map to mask-registers.
20888 // Check all uses of that condition operand to check whether it will be
20889 // consumed by non-BLEND instructions, which may depend on all bits are set
20891 for (SDNode::use_iterator I = Cond->use_begin(),
20892 E = Cond->use_end(); I != E; ++I)
20893 if (I->getOpcode() != ISD::VSELECT)
20894 // TODO: Add other opcodes eventually lowered into BLEND.
20897 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20898 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20900 APInt KnownZero, KnownOne;
20901 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20902 DCI.isBeforeLegalizeOps());
20903 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20904 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20905 DCI.CommitTargetLoweringOpt(TLO);
20908 // We should generate an X86ISD::BLENDI from a vselect if its argument
20909 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20910 // constants. This specific pattern gets generated when we split a
20911 // selector for a 512 bit vector in a machine without AVX512 (but with
20912 // 256-bit vectors), during legalization:
20914 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20916 // Iff we find this pattern and the build_vectors are built from
20917 // constants, we translate the vselect into a shuffle_vector that we
20918 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20919 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20920 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20921 if (Shuffle.getNode())
20928 // Check whether a boolean test is testing a boolean value generated by
20929 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20932 // Simplify the following patterns:
20933 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20934 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20935 // to (Op EFLAGS Cond)
20937 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20938 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20939 // to (Op EFLAGS !Cond)
20941 // where Op could be BRCOND or CMOV.
20943 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20944 // Quit if not CMP and SUB with its value result used.
20945 if (Cmp.getOpcode() != X86ISD::CMP &&
20946 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20949 // Quit if not used as a boolean value.
20950 if (CC != X86::COND_E && CC != X86::COND_NE)
20953 // Check CMP operands. One of them should be 0 or 1 and the other should be
20954 // an SetCC or extended from it.
20955 SDValue Op1 = Cmp.getOperand(0);
20956 SDValue Op2 = Cmp.getOperand(1);
20959 const ConstantSDNode* C = nullptr;
20960 bool needOppositeCond = (CC == X86::COND_E);
20961 bool checkAgainstTrue = false; // Is it a comparison against 1?
20963 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20965 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20967 else // Quit if all operands are not constants.
20970 if (C->getZExtValue() == 1) {
20971 needOppositeCond = !needOppositeCond;
20972 checkAgainstTrue = true;
20973 } else if (C->getZExtValue() != 0)
20974 // Quit if the constant is neither 0 or 1.
20977 bool truncatedToBoolWithAnd = false;
20978 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20979 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20980 SetCC.getOpcode() == ISD::TRUNCATE ||
20981 SetCC.getOpcode() == ISD::AND) {
20982 if (SetCC.getOpcode() == ISD::AND) {
20984 ConstantSDNode *CS;
20985 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20986 CS->getZExtValue() == 1)
20988 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20989 CS->getZExtValue() == 1)
20993 SetCC = SetCC.getOperand(OpIdx);
20994 truncatedToBoolWithAnd = true;
20996 SetCC = SetCC.getOperand(0);
20999 switch (SetCC.getOpcode()) {
21000 case X86ISD::SETCC_CARRY:
21001 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21002 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21003 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21004 // truncated to i1 using 'and'.
21005 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21007 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21008 "Invalid use of SETCC_CARRY!");
21010 case X86ISD::SETCC:
21011 // Set the condition code or opposite one if necessary.
21012 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21013 if (needOppositeCond)
21014 CC = X86::GetOppositeBranchCondition(CC);
21015 return SetCC.getOperand(1);
21016 case X86ISD::CMOV: {
21017 // Check whether false/true value has canonical one, i.e. 0 or 1.
21018 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21019 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21020 // Quit if true value is not a constant.
21023 // Quit if false value is not a constant.
21025 SDValue Op = SetCC.getOperand(0);
21026 // Skip 'zext' or 'trunc' node.
21027 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21028 Op.getOpcode() == ISD::TRUNCATE)
21029 Op = Op.getOperand(0);
21030 // A special case for rdrand/rdseed, where 0 is set if false cond is
21032 if ((Op.getOpcode() != X86ISD::RDRAND &&
21033 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21036 // Quit if false value is not the constant 0 or 1.
21037 bool FValIsFalse = true;
21038 if (FVal && FVal->getZExtValue() != 0) {
21039 if (FVal->getZExtValue() != 1)
21041 // If FVal is 1, opposite cond is needed.
21042 needOppositeCond = !needOppositeCond;
21043 FValIsFalse = false;
21045 // Quit if TVal is not the constant opposite of FVal.
21046 if (FValIsFalse && TVal->getZExtValue() != 1)
21048 if (!FValIsFalse && TVal->getZExtValue() != 0)
21050 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21051 if (needOppositeCond)
21052 CC = X86::GetOppositeBranchCondition(CC);
21053 return SetCC.getOperand(3);
21060 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21061 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21062 TargetLowering::DAGCombinerInfo &DCI,
21063 const X86Subtarget *Subtarget) {
21066 // If the flag operand isn't dead, don't touch this CMOV.
21067 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21070 SDValue FalseOp = N->getOperand(0);
21071 SDValue TrueOp = N->getOperand(1);
21072 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21073 SDValue Cond = N->getOperand(3);
21075 if (CC == X86::COND_E || CC == X86::COND_NE) {
21076 switch (Cond.getOpcode()) {
21080 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21081 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21082 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21088 Flags = checkBoolTestSetCCCombine(Cond, CC);
21089 if (Flags.getNode() &&
21090 // Extra check as FCMOV only supports a subset of X86 cond.
21091 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21092 SDValue Ops[] = { FalseOp, TrueOp,
21093 DAG.getConstant(CC, MVT::i8), Flags };
21094 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21097 // If this is a select between two integer constants, try to do some
21098 // optimizations. Note that the operands are ordered the opposite of SELECT
21100 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21101 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21102 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21103 // larger than FalseC (the false value).
21104 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21105 CC = X86::GetOppositeBranchCondition(CC);
21106 std::swap(TrueC, FalseC);
21107 std::swap(TrueOp, FalseOp);
21110 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21111 // This is efficient for any integer data type (including i8/i16) and
21113 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21114 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21115 DAG.getConstant(CC, MVT::i8), Cond);
21117 // Zero extend the condition if needed.
21118 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21120 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21121 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21122 DAG.getConstant(ShAmt, MVT::i8));
21123 if (N->getNumValues() == 2) // Dead flag value?
21124 return DCI.CombineTo(N, Cond, SDValue());
21128 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21129 // for any integer data type, including i8/i16.
21130 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21131 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21132 DAG.getConstant(CC, MVT::i8), Cond);
21134 // Zero extend the condition if needed.
21135 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21136 FalseC->getValueType(0), Cond);
21137 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21138 SDValue(FalseC, 0));
21140 if (N->getNumValues() == 2) // Dead flag value?
21141 return DCI.CombineTo(N, Cond, SDValue());
21145 // Optimize cases that will turn into an LEA instruction. This requires
21146 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21147 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21148 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21149 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21151 bool isFastMultiplier = false;
21153 switch ((unsigned char)Diff) {
21155 case 1: // result = add base, cond
21156 case 2: // result = lea base( , cond*2)
21157 case 3: // result = lea base(cond, cond*2)
21158 case 4: // result = lea base( , cond*4)
21159 case 5: // result = lea base(cond, cond*4)
21160 case 8: // result = lea base( , cond*8)
21161 case 9: // result = lea base(cond, cond*8)
21162 isFastMultiplier = true;
21167 if (isFastMultiplier) {
21168 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21169 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21170 DAG.getConstant(CC, MVT::i8), Cond);
21171 // Zero extend the condition if needed.
21172 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21174 // Scale the condition by the difference.
21176 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21177 DAG.getConstant(Diff, Cond.getValueType()));
21179 // Add the base if non-zero.
21180 if (FalseC->getAPIntValue() != 0)
21181 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21182 SDValue(FalseC, 0));
21183 if (N->getNumValues() == 2) // Dead flag value?
21184 return DCI.CombineTo(N, Cond, SDValue());
21191 // Handle these cases:
21192 // (select (x != c), e, c) -> select (x != c), e, x),
21193 // (select (x == c), c, e) -> select (x == c), x, e)
21194 // where the c is an integer constant, and the "select" is the combination
21195 // of CMOV and CMP.
21197 // The rationale for this change is that the conditional-move from a constant
21198 // needs two instructions, however, conditional-move from a register needs
21199 // only one instruction.
21201 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21202 // some instruction-combining opportunities. This opt needs to be
21203 // postponed as late as possible.
21205 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21206 // the DCI.xxxx conditions are provided to postpone the optimization as
21207 // late as possible.
21209 ConstantSDNode *CmpAgainst = nullptr;
21210 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21211 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21212 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21214 if (CC == X86::COND_NE &&
21215 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21216 CC = X86::GetOppositeBranchCondition(CC);
21217 std::swap(TrueOp, FalseOp);
21220 if (CC == X86::COND_E &&
21221 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21222 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21223 DAG.getConstant(CC, MVT::i8), Cond };
21224 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21232 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21233 const X86Subtarget *Subtarget) {
21234 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21236 default: return SDValue();
21237 // SSE/AVX/AVX2 blend intrinsics.
21238 case Intrinsic::x86_avx2_pblendvb:
21239 case Intrinsic::x86_avx2_pblendw:
21240 case Intrinsic::x86_avx2_pblendd_128:
21241 case Intrinsic::x86_avx2_pblendd_256:
21242 // Don't try to simplify this intrinsic if we don't have AVX2.
21243 if (!Subtarget->hasAVX2())
21246 case Intrinsic::x86_avx_blend_pd_256:
21247 case Intrinsic::x86_avx_blend_ps_256:
21248 case Intrinsic::x86_avx_blendv_pd_256:
21249 case Intrinsic::x86_avx_blendv_ps_256:
21250 // Don't try to simplify this intrinsic if we don't have AVX.
21251 if (!Subtarget->hasAVX())
21254 case Intrinsic::x86_sse41_pblendw:
21255 case Intrinsic::x86_sse41_blendpd:
21256 case Intrinsic::x86_sse41_blendps:
21257 case Intrinsic::x86_sse41_blendvps:
21258 case Intrinsic::x86_sse41_blendvpd:
21259 case Intrinsic::x86_sse41_pblendvb: {
21260 SDValue Op0 = N->getOperand(1);
21261 SDValue Op1 = N->getOperand(2);
21262 SDValue Mask = N->getOperand(3);
21264 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21265 if (!Subtarget->hasSSE41())
21268 // fold (blend A, A, Mask) -> A
21271 // fold (blend A, B, allZeros) -> A
21272 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21274 // fold (blend A, B, allOnes) -> B
21275 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21278 // Simplify the case where the mask is a constant i32 value.
21279 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21280 if (C->isNullValue())
21282 if (C->isAllOnesValue())
21289 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21290 case Intrinsic::x86_sse2_psrai_w:
21291 case Intrinsic::x86_sse2_psrai_d:
21292 case Intrinsic::x86_avx2_psrai_w:
21293 case Intrinsic::x86_avx2_psrai_d:
21294 case Intrinsic::x86_sse2_psra_w:
21295 case Intrinsic::x86_sse2_psra_d:
21296 case Intrinsic::x86_avx2_psra_w:
21297 case Intrinsic::x86_avx2_psra_d: {
21298 SDValue Op0 = N->getOperand(1);
21299 SDValue Op1 = N->getOperand(2);
21300 EVT VT = Op0.getValueType();
21301 assert(VT.isVector() && "Expected a vector type!");
21303 if (isa<BuildVectorSDNode>(Op1))
21304 Op1 = Op1.getOperand(0);
21306 if (!isa<ConstantSDNode>(Op1))
21309 EVT SVT = VT.getVectorElementType();
21310 unsigned SVTBits = SVT.getSizeInBits();
21312 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21313 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21314 uint64_t ShAmt = C.getZExtValue();
21316 // Don't try to convert this shift into a ISD::SRA if the shift
21317 // count is bigger than or equal to the element size.
21318 if (ShAmt >= SVTBits)
21321 // Trivial case: if the shift count is zero, then fold this
21322 // into the first operand.
21326 // Replace this packed shift intrinsic with a target independent
21328 SDValue Splat = DAG.getConstant(C, VT);
21329 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21334 /// PerformMulCombine - Optimize a single multiply with constant into two
21335 /// in order to implement it with two cheaper instructions, e.g.
21336 /// LEA + SHL, LEA + LEA.
21337 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21338 TargetLowering::DAGCombinerInfo &DCI) {
21339 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21342 EVT VT = N->getValueType(0);
21343 if (VT != MVT::i64)
21346 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21349 uint64_t MulAmt = C->getZExtValue();
21350 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21353 uint64_t MulAmt1 = 0;
21354 uint64_t MulAmt2 = 0;
21355 if ((MulAmt % 9) == 0) {
21357 MulAmt2 = MulAmt / 9;
21358 } else if ((MulAmt % 5) == 0) {
21360 MulAmt2 = MulAmt / 5;
21361 } else if ((MulAmt % 3) == 0) {
21363 MulAmt2 = MulAmt / 3;
21366 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21369 if (isPowerOf2_64(MulAmt2) &&
21370 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21371 // If second multiplifer is pow2, issue it first. We want the multiply by
21372 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21374 std::swap(MulAmt1, MulAmt2);
21377 if (isPowerOf2_64(MulAmt1))
21378 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21379 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21381 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21382 DAG.getConstant(MulAmt1, VT));
21384 if (isPowerOf2_64(MulAmt2))
21385 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21386 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21388 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21389 DAG.getConstant(MulAmt2, VT));
21391 // Do not add new nodes to DAG combiner worklist.
21392 DCI.CombineTo(N, NewMul, false);
21397 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21398 SDValue N0 = N->getOperand(0);
21399 SDValue N1 = N->getOperand(1);
21400 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21401 EVT VT = N0.getValueType();
21403 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21404 // since the result of setcc_c is all zero's or all ones.
21405 if (VT.isInteger() && !VT.isVector() &&
21406 N1C && N0.getOpcode() == ISD::AND &&
21407 N0.getOperand(1).getOpcode() == ISD::Constant) {
21408 SDValue N00 = N0.getOperand(0);
21409 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21410 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21411 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21412 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21413 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21414 APInt ShAmt = N1C->getAPIntValue();
21415 Mask = Mask.shl(ShAmt);
21417 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21418 N00, DAG.getConstant(Mask, VT));
21422 // Hardware support for vector shifts is sparse which makes us scalarize the
21423 // vector operations in many cases. Also, on sandybridge ADD is faster than
21425 // (shl V, 1) -> add V,V
21426 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21427 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21428 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21429 // We shift all of the values by one. In many cases we do not have
21430 // hardware support for this operation. This is better expressed as an ADD
21432 if (N1SplatC->getZExtValue() == 1)
21433 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21439 /// \brief Returns a vector of 0s if the node in input is a vector logical
21440 /// shift by a constant amount which is known to be bigger than or equal
21441 /// to the vector element size in bits.
21442 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21443 const X86Subtarget *Subtarget) {
21444 EVT VT = N->getValueType(0);
21446 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21447 (!Subtarget->hasInt256() ||
21448 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21451 SDValue Amt = N->getOperand(1);
21453 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21454 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21455 APInt ShiftAmt = AmtSplat->getAPIntValue();
21456 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21458 // SSE2/AVX2 logical shifts always return a vector of 0s
21459 // if the shift amount is bigger than or equal to
21460 // the element size. The constant shift amount will be
21461 // encoded as a 8-bit immediate.
21462 if (ShiftAmt.trunc(8).uge(MaxAmount))
21463 return getZeroVector(VT, Subtarget, DAG, DL);
21469 /// PerformShiftCombine - Combine shifts.
21470 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21471 TargetLowering::DAGCombinerInfo &DCI,
21472 const X86Subtarget *Subtarget) {
21473 if (N->getOpcode() == ISD::SHL) {
21474 SDValue V = PerformSHLCombine(N, DAG);
21475 if (V.getNode()) return V;
21478 if (N->getOpcode() != ISD::SRA) {
21479 // Try to fold this logical shift into a zero vector.
21480 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21481 if (V.getNode()) return V;
21487 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21488 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21489 // and friends. Likewise for OR -> CMPNEQSS.
21490 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21491 TargetLowering::DAGCombinerInfo &DCI,
21492 const X86Subtarget *Subtarget) {
21495 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21496 // we're requiring SSE2 for both.
21497 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21498 SDValue N0 = N->getOperand(0);
21499 SDValue N1 = N->getOperand(1);
21500 SDValue CMP0 = N0->getOperand(1);
21501 SDValue CMP1 = N1->getOperand(1);
21504 // The SETCCs should both refer to the same CMP.
21505 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21508 SDValue CMP00 = CMP0->getOperand(0);
21509 SDValue CMP01 = CMP0->getOperand(1);
21510 EVT VT = CMP00.getValueType();
21512 if (VT == MVT::f32 || VT == MVT::f64) {
21513 bool ExpectingFlags = false;
21514 // Check for any users that want flags:
21515 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21516 !ExpectingFlags && UI != UE; ++UI)
21517 switch (UI->getOpcode()) {
21522 ExpectingFlags = true;
21524 case ISD::CopyToReg:
21525 case ISD::SIGN_EXTEND:
21526 case ISD::ZERO_EXTEND:
21527 case ISD::ANY_EXTEND:
21531 if (!ExpectingFlags) {
21532 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21533 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21535 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21536 X86::CondCode tmp = cc0;
21541 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21542 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21543 // FIXME: need symbolic constants for these magic numbers.
21544 // See X86ATTInstPrinter.cpp:printSSECC().
21545 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21546 if (Subtarget->hasAVX512()) {
21547 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21548 CMP01, DAG.getConstant(x86cc, MVT::i8));
21549 if (N->getValueType(0) != MVT::i1)
21550 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21554 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21555 CMP00.getValueType(), CMP00, CMP01,
21556 DAG.getConstant(x86cc, MVT::i8));
21558 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21559 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21561 if (is64BitFP && !Subtarget->is64Bit()) {
21562 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21563 // 64-bit integer, since that's not a legal type. Since
21564 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21565 // bits, but can do this little dance to extract the lowest 32 bits
21566 // and work with those going forward.
21567 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21569 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21571 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21572 Vector32, DAG.getIntPtrConstant(0));
21576 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21577 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21578 DAG.getConstant(1, IntVT));
21579 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21580 return OneBitOfTruth;
21588 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21589 /// so it can be folded inside ANDNP.
21590 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21591 EVT VT = N->getValueType(0);
21593 // Match direct AllOnes for 128 and 256-bit vectors
21594 if (ISD::isBuildVectorAllOnes(N))
21597 // Look through a bit convert.
21598 if (N->getOpcode() == ISD::BITCAST)
21599 N = N->getOperand(0).getNode();
21601 // Sometimes the operand may come from a insert_subvector building a 256-bit
21603 if (VT.is256BitVector() &&
21604 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21605 SDValue V1 = N->getOperand(0);
21606 SDValue V2 = N->getOperand(1);
21608 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21609 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21610 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21611 ISD::isBuildVectorAllOnes(V2.getNode()))
21618 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21619 // register. In most cases we actually compare or select YMM-sized registers
21620 // and mixing the two types creates horrible code. This method optimizes
21621 // some of the transition sequences.
21622 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21623 TargetLowering::DAGCombinerInfo &DCI,
21624 const X86Subtarget *Subtarget) {
21625 EVT VT = N->getValueType(0);
21626 if (!VT.is256BitVector())
21629 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21630 N->getOpcode() == ISD::ZERO_EXTEND ||
21631 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21633 SDValue Narrow = N->getOperand(0);
21634 EVT NarrowVT = Narrow->getValueType(0);
21635 if (!NarrowVT.is128BitVector())
21638 if (Narrow->getOpcode() != ISD::XOR &&
21639 Narrow->getOpcode() != ISD::AND &&
21640 Narrow->getOpcode() != ISD::OR)
21643 SDValue N0 = Narrow->getOperand(0);
21644 SDValue N1 = Narrow->getOperand(1);
21647 // The Left side has to be a trunc.
21648 if (N0.getOpcode() != ISD::TRUNCATE)
21651 // The type of the truncated inputs.
21652 EVT WideVT = N0->getOperand(0)->getValueType(0);
21656 // The right side has to be a 'trunc' or a constant vector.
21657 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21658 ConstantSDNode *RHSConstSplat = nullptr;
21659 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21660 RHSConstSplat = RHSBV->getConstantSplatNode();
21661 if (!RHSTrunc && !RHSConstSplat)
21664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21666 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21669 // Set N0 and N1 to hold the inputs to the new wide operation.
21670 N0 = N0->getOperand(0);
21671 if (RHSConstSplat) {
21672 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21673 SDValue(RHSConstSplat, 0));
21674 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21675 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21676 } else if (RHSTrunc) {
21677 N1 = N1->getOperand(0);
21680 // Generate the wide operation.
21681 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21682 unsigned Opcode = N->getOpcode();
21684 case ISD::ANY_EXTEND:
21686 case ISD::ZERO_EXTEND: {
21687 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21688 APInt Mask = APInt::getAllOnesValue(InBits);
21689 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21690 return DAG.getNode(ISD::AND, DL, VT,
21691 Op, DAG.getConstant(Mask, VT));
21693 case ISD::SIGN_EXTEND:
21694 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21695 Op, DAG.getValueType(NarrowVT));
21697 llvm_unreachable("Unexpected opcode");
21701 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21702 TargetLowering::DAGCombinerInfo &DCI,
21703 const X86Subtarget *Subtarget) {
21704 EVT VT = N->getValueType(0);
21705 if (DCI.isBeforeLegalizeOps())
21708 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21712 // Create BEXTR instructions
21713 // BEXTR is ((X >> imm) & (2**size-1))
21714 if (VT == MVT::i32 || VT == MVT::i64) {
21715 SDValue N0 = N->getOperand(0);
21716 SDValue N1 = N->getOperand(1);
21719 // Check for BEXTR.
21720 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21721 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21722 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21723 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21724 if (MaskNode && ShiftNode) {
21725 uint64_t Mask = MaskNode->getZExtValue();
21726 uint64_t Shift = ShiftNode->getZExtValue();
21727 if (isMask_64(Mask)) {
21728 uint64_t MaskSize = CountPopulation_64(Mask);
21729 if (Shift + MaskSize <= VT.getSizeInBits())
21730 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21731 DAG.getConstant(Shift | (MaskSize << 8), VT));
21739 // Want to form ANDNP nodes:
21740 // 1) In the hopes of then easily combining them with OR and AND nodes
21741 // to form PBLEND/PSIGN.
21742 // 2) To match ANDN packed intrinsics
21743 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21746 SDValue N0 = N->getOperand(0);
21747 SDValue N1 = N->getOperand(1);
21750 // Check LHS for vnot
21751 if (N0.getOpcode() == ISD::XOR &&
21752 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21753 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21754 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21756 // Check RHS for vnot
21757 if (N1.getOpcode() == ISD::XOR &&
21758 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21759 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21760 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21765 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21766 TargetLowering::DAGCombinerInfo &DCI,
21767 const X86Subtarget *Subtarget) {
21768 if (DCI.isBeforeLegalizeOps())
21771 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21775 SDValue N0 = N->getOperand(0);
21776 SDValue N1 = N->getOperand(1);
21777 EVT VT = N->getValueType(0);
21779 // look for psign/blend
21780 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21781 if (!Subtarget->hasSSSE3() ||
21782 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21785 // Canonicalize pandn to RHS
21786 if (N0.getOpcode() == X86ISD::ANDNP)
21788 // or (and (m, y), (pandn m, x))
21789 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21790 SDValue Mask = N1.getOperand(0);
21791 SDValue X = N1.getOperand(1);
21793 if (N0.getOperand(0) == Mask)
21794 Y = N0.getOperand(1);
21795 if (N0.getOperand(1) == Mask)
21796 Y = N0.getOperand(0);
21798 // Check to see if the mask appeared in both the AND and ANDNP and
21802 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21803 // Look through mask bitcast.
21804 if (Mask.getOpcode() == ISD::BITCAST)
21805 Mask = Mask.getOperand(0);
21806 if (X.getOpcode() == ISD::BITCAST)
21807 X = X.getOperand(0);
21808 if (Y.getOpcode() == ISD::BITCAST)
21809 Y = Y.getOperand(0);
21811 EVT MaskVT = Mask.getValueType();
21813 // Validate that the Mask operand is a vector sra node.
21814 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21815 // there is no psrai.b
21816 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21817 unsigned SraAmt = ~0;
21818 if (Mask.getOpcode() == ISD::SRA) {
21819 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21820 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21821 SraAmt = AmtConst->getZExtValue();
21822 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21823 SDValue SraC = Mask.getOperand(1);
21824 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21826 if ((SraAmt + 1) != EltBits)
21831 // Now we know we at least have a plendvb with the mask val. See if
21832 // we can form a psignb/w/d.
21833 // psign = x.type == y.type == mask.type && y = sub(0, x);
21834 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21835 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21836 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21837 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21838 "Unsupported VT for PSIGN");
21839 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21840 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21842 // PBLENDVB only available on SSE 4.1
21843 if (!Subtarget->hasSSE41())
21846 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21848 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21849 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21850 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21851 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21852 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21856 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21859 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21860 MachineFunction &MF = DAG.getMachineFunction();
21861 bool OptForSize = MF.getFunction()->getAttributes().
21862 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21864 // SHLD/SHRD instructions have lower register pressure, but on some
21865 // platforms they have higher latency than the equivalent
21866 // series of shifts/or that would otherwise be generated.
21867 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21868 // have higher latencies and we are not optimizing for size.
21869 if (!OptForSize && Subtarget->isSHLDSlow())
21872 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21874 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21876 if (!N0.hasOneUse() || !N1.hasOneUse())
21879 SDValue ShAmt0 = N0.getOperand(1);
21880 if (ShAmt0.getValueType() != MVT::i8)
21882 SDValue ShAmt1 = N1.getOperand(1);
21883 if (ShAmt1.getValueType() != MVT::i8)
21885 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21886 ShAmt0 = ShAmt0.getOperand(0);
21887 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21888 ShAmt1 = ShAmt1.getOperand(0);
21891 unsigned Opc = X86ISD::SHLD;
21892 SDValue Op0 = N0.getOperand(0);
21893 SDValue Op1 = N1.getOperand(0);
21894 if (ShAmt0.getOpcode() == ISD::SUB) {
21895 Opc = X86ISD::SHRD;
21896 std::swap(Op0, Op1);
21897 std::swap(ShAmt0, ShAmt1);
21900 unsigned Bits = VT.getSizeInBits();
21901 if (ShAmt1.getOpcode() == ISD::SUB) {
21902 SDValue Sum = ShAmt1.getOperand(0);
21903 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21904 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21905 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21906 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21907 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21908 return DAG.getNode(Opc, DL, VT,
21910 DAG.getNode(ISD::TRUNCATE, DL,
21913 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21914 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21916 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21917 return DAG.getNode(Opc, DL, VT,
21918 N0.getOperand(0), N1.getOperand(0),
21919 DAG.getNode(ISD::TRUNCATE, DL,
21926 // Generate NEG and CMOV for integer abs.
21927 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21928 EVT VT = N->getValueType(0);
21930 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21931 // 8-bit integer abs to NEG and CMOV.
21932 if (VT.isInteger() && VT.getSizeInBits() == 8)
21935 SDValue N0 = N->getOperand(0);
21936 SDValue N1 = N->getOperand(1);
21939 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21940 // and change it to SUB and CMOV.
21941 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21942 N0.getOpcode() == ISD::ADD &&
21943 N0.getOperand(1) == N1 &&
21944 N1.getOpcode() == ISD::SRA &&
21945 N1.getOperand(0) == N0.getOperand(0))
21946 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21947 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21948 // Generate SUB & CMOV.
21949 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21950 DAG.getConstant(0, VT), N0.getOperand(0));
21952 SDValue Ops[] = { N0.getOperand(0), Neg,
21953 DAG.getConstant(X86::COND_GE, MVT::i8),
21954 SDValue(Neg.getNode(), 1) };
21955 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21960 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
21961 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
21962 TargetLowering::DAGCombinerInfo &DCI,
21963 const X86Subtarget *Subtarget) {
21964 if (DCI.isBeforeLegalizeOps())
21967 if (Subtarget->hasCMov()) {
21968 SDValue RV = performIntegerAbsCombine(N, DAG);
21976 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
21977 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
21978 TargetLowering::DAGCombinerInfo &DCI,
21979 const X86Subtarget *Subtarget) {
21980 LoadSDNode *Ld = cast<LoadSDNode>(N);
21981 EVT RegVT = Ld->getValueType(0);
21982 EVT MemVT = Ld->getMemoryVT();
21984 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21986 // On Sandybridge unaligned 256bit loads are inefficient.
21987 ISD::LoadExtType Ext = Ld->getExtensionType();
21988 unsigned Alignment = Ld->getAlignment();
21989 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
21990 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
21991 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
21992 unsigned NumElems = RegVT.getVectorNumElements();
21996 SDValue Ptr = Ld->getBasePtr();
21997 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
21999 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22001 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22002 Ld->getPointerInfo(), Ld->isVolatile(),
22003 Ld->isNonTemporal(), Ld->isInvariant(),
22005 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22006 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22007 Ld->getPointerInfo(), Ld->isVolatile(),
22008 Ld->isNonTemporal(), Ld->isInvariant(),
22009 std::min(16U, Alignment));
22010 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22012 Load2.getValue(1));
22014 SDValue NewVec = DAG.getUNDEF(RegVT);
22015 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22016 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22017 return DCI.CombineTo(N, NewVec, TF, true);
22023 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22024 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22025 const X86Subtarget *Subtarget) {
22026 StoreSDNode *St = cast<StoreSDNode>(N);
22027 EVT VT = St->getValue().getValueType();
22028 EVT StVT = St->getMemoryVT();
22030 SDValue StoredVal = St->getOperand(1);
22031 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22033 // If we are saving a concatenation of two XMM registers, perform two stores.
22034 // On Sandy Bridge, 256-bit memory operations are executed by two
22035 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
22036 // memory operation.
22037 unsigned Alignment = St->getAlignment();
22038 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22039 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
22040 StVT == VT && !IsAligned) {
22041 unsigned NumElems = VT.getVectorNumElements();
22045 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22046 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22048 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22049 SDValue Ptr0 = St->getBasePtr();
22050 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22052 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22053 St->getPointerInfo(), St->isVolatile(),
22054 St->isNonTemporal(), Alignment);
22055 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22056 St->getPointerInfo(), St->isVolatile(),
22057 St->isNonTemporal(),
22058 std::min(16U, Alignment));
22059 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22062 // Optimize trunc store (of multiple scalars) to shuffle and store.
22063 // First, pack all of the elements in one place. Next, store to memory
22064 // in fewer chunks.
22065 if (St->isTruncatingStore() && VT.isVector()) {
22066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22067 unsigned NumElems = VT.getVectorNumElements();
22068 assert(StVT != VT && "Cannot truncate to the same type");
22069 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22070 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22072 // From, To sizes and ElemCount must be pow of two
22073 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22074 // We are going to use the original vector elt for storing.
22075 // Accumulated smaller vector elements must be a multiple of the store size.
22076 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22078 unsigned SizeRatio = FromSz / ToSz;
22080 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22082 // Create a type on which we perform the shuffle
22083 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22084 StVT.getScalarType(), NumElems*SizeRatio);
22086 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22088 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22089 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22090 for (unsigned i = 0; i != NumElems; ++i)
22091 ShuffleVec[i] = i * SizeRatio;
22093 // Can't shuffle using an illegal type.
22094 if (!TLI.isTypeLegal(WideVecVT))
22097 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22098 DAG.getUNDEF(WideVecVT),
22100 // At this point all of the data is stored at the bottom of the
22101 // register. We now need to save it to mem.
22103 // Find the largest store unit
22104 MVT StoreType = MVT::i8;
22105 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
22106 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
22107 MVT Tp = (MVT::SimpleValueType)tp;
22108 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22112 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22113 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22114 (64 <= NumElems * ToSz))
22115 StoreType = MVT::f64;
22117 // Bitcast the original vector into a vector of store-size units
22118 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22119 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22120 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22121 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22122 SmallVector<SDValue, 8> Chains;
22123 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22124 TLI.getPointerTy());
22125 SDValue Ptr = St->getBasePtr();
22127 // Perform one or more big stores into memory.
22128 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22129 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22130 StoreType, ShuffWide,
22131 DAG.getIntPtrConstant(i));
22132 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22133 St->getPointerInfo(), St->isVolatile(),
22134 St->isNonTemporal(), St->getAlignment());
22135 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22136 Chains.push_back(Ch);
22139 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22142 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22143 // the FP state in cases where an emms may be missing.
22144 // A preferable solution to the general problem is to figure out the right
22145 // places to insert EMMS. This qualifies as a quick hack.
22147 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22148 if (VT.getSizeInBits() != 64)
22151 const Function *F = DAG.getMachineFunction().getFunction();
22152 bool NoImplicitFloatOps = F->getAttributes().
22153 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
22154 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22155 && Subtarget->hasSSE2();
22156 if ((VT.isVector() ||
22157 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22158 isa<LoadSDNode>(St->getValue()) &&
22159 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22160 St->getChain().hasOneUse() && !St->isVolatile()) {
22161 SDNode* LdVal = St->getValue().getNode();
22162 LoadSDNode *Ld = nullptr;
22163 int TokenFactorIndex = -1;
22164 SmallVector<SDValue, 8> Ops;
22165 SDNode* ChainVal = St->getChain().getNode();
22166 // Must be a store of a load. We currently handle two cases: the load
22167 // is a direct child, and it's under an intervening TokenFactor. It is
22168 // possible to dig deeper under nested TokenFactors.
22169 if (ChainVal == LdVal)
22170 Ld = cast<LoadSDNode>(St->getChain());
22171 else if (St->getValue().hasOneUse() &&
22172 ChainVal->getOpcode() == ISD::TokenFactor) {
22173 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22174 if (ChainVal->getOperand(i).getNode() == LdVal) {
22175 TokenFactorIndex = i;
22176 Ld = cast<LoadSDNode>(St->getValue());
22178 Ops.push_back(ChainVal->getOperand(i));
22182 if (!Ld || !ISD::isNormalLoad(Ld))
22185 // If this is not the MMX case, i.e. we are just turning i64 load/store
22186 // into f64 load/store, avoid the transformation if there are multiple
22187 // uses of the loaded value.
22188 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22193 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22194 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22196 if (Subtarget->is64Bit() || F64IsLegal) {
22197 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22198 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22199 Ld->getPointerInfo(), Ld->isVolatile(),
22200 Ld->isNonTemporal(), Ld->isInvariant(),
22201 Ld->getAlignment());
22202 SDValue NewChain = NewLd.getValue(1);
22203 if (TokenFactorIndex != -1) {
22204 Ops.push_back(NewChain);
22205 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22207 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22208 St->getPointerInfo(),
22209 St->isVolatile(), St->isNonTemporal(),
22210 St->getAlignment());
22213 // Otherwise, lower to two pairs of 32-bit loads / stores.
22214 SDValue LoAddr = Ld->getBasePtr();
22215 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22216 DAG.getConstant(4, MVT::i32));
22218 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22219 Ld->getPointerInfo(),
22220 Ld->isVolatile(), Ld->isNonTemporal(),
22221 Ld->isInvariant(), Ld->getAlignment());
22222 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22223 Ld->getPointerInfo().getWithOffset(4),
22224 Ld->isVolatile(), Ld->isNonTemporal(),
22226 MinAlign(Ld->getAlignment(), 4));
22228 SDValue NewChain = LoLd.getValue(1);
22229 if (TokenFactorIndex != -1) {
22230 Ops.push_back(LoLd);
22231 Ops.push_back(HiLd);
22232 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22235 LoAddr = St->getBasePtr();
22236 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22237 DAG.getConstant(4, MVT::i32));
22239 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22240 St->getPointerInfo(),
22241 St->isVolatile(), St->isNonTemporal(),
22242 St->getAlignment());
22243 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22244 St->getPointerInfo().getWithOffset(4),
22246 St->isNonTemporal(),
22247 MinAlign(St->getAlignment(), 4));
22248 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22253 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
22254 /// and return the operands for the horizontal operation in LHS and RHS. A
22255 /// horizontal operation performs the binary operation on successive elements
22256 /// of its first operand, then on successive elements of its second operand,
22257 /// returning the resulting values in a vector. For example, if
22258 /// A = < float a0, float a1, float a2, float a3 >
22260 /// B = < float b0, float b1, float b2, float b3 >
22261 /// then the result of doing a horizontal operation on A and B is
22262 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22263 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22264 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22265 /// set to A, RHS to B, and the routine returns 'true'.
22266 /// Note that the binary operation should have the property that if one of the
22267 /// operands is UNDEF then the result is UNDEF.
22268 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22269 // Look for the following pattern: if
22270 // A = < float a0, float a1, float a2, float a3 >
22271 // B = < float b0, float b1, float b2, float b3 >
22273 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22274 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22275 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22276 // which is A horizontal-op B.
22278 // At least one of the operands should be a vector shuffle.
22279 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22280 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22283 MVT VT = LHS.getSimpleValueType();
22285 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22286 "Unsupported vector type for horizontal add/sub");
22288 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22289 // operate independently on 128-bit lanes.
22290 unsigned NumElts = VT.getVectorNumElements();
22291 unsigned NumLanes = VT.getSizeInBits()/128;
22292 unsigned NumLaneElts = NumElts / NumLanes;
22293 assert((NumLaneElts % 2 == 0) &&
22294 "Vector type should have an even number of elements in each lane");
22295 unsigned HalfLaneElts = NumLaneElts/2;
22297 // View LHS in the form
22298 // LHS = VECTOR_SHUFFLE A, B, LMask
22299 // If LHS is not a shuffle then pretend it is the shuffle
22300 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22301 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22304 SmallVector<int, 16> LMask(NumElts);
22305 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22306 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22307 A = LHS.getOperand(0);
22308 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22309 B = LHS.getOperand(1);
22310 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22311 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22313 if (LHS.getOpcode() != ISD::UNDEF)
22315 for (unsigned i = 0; i != NumElts; ++i)
22319 // Likewise, view RHS in the form
22320 // RHS = VECTOR_SHUFFLE C, D, RMask
22322 SmallVector<int, 16> RMask(NumElts);
22323 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22324 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22325 C = RHS.getOperand(0);
22326 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22327 D = RHS.getOperand(1);
22328 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
22329 std::copy(Mask.begin(), Mask.end(), RMask.begin());
22331 if (RHS.getOpcode() != ISD::UNDEF)
22333 for (unsigned i = 0; i != NumElts; ++i)
22337 // Check that the shuffles are both shuffling the same vectors.
22338 if (!(A == C && B == D) && !(A == D && B == C))
22341 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
22342 if (!A.getNode() && !B.getNode())
22345 // If A and B occur in reverse order in RHS, then "swap" them (which means
22346 // rewriting the mask).
22348 CommuteVectorShuffleMask(RMask, NumElts);
22350 // At this point LHS and RHS are equivalent to
22351 // LHS = VECTOR_SHUFFLE A, B, LMask
22352 // RHS = VECTOR_SHUFFLE A, B, RMask
22353 // Check that the masks correspond to performing a horizontal operation.
22354 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
22355 for (unsigned i = 0; i != NumLaneElts; ++i) {
22356 int LIdx = LMask[i+l], RIdx = RMask[i+l];
22358 // Ignore any UNDEF components.
22359 if (LIdx < 0 || RIdx < 0 ||
22360 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
22361 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
22364 // Check that successive elements are being operated on. If not, this is
22365 // not a horizontal operation.
22366 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
22367 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
22368 if (!(LIdx == Index && RIdx == Index + 1) &&
22369 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
22374 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
22375 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
22379 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22380 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22381 const X86Subtarget *Subtarget) {
22382 EVT VT = N->getValueType(0);
22383 SDValue LHS = N->getOperand(0);
22384 SDValue RHS = N->getOperand(1);
22386 // Try to synthesize horizontal adds from adds of shuffles.
22387 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22388 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22389 isHorizontalBinOp(LHS, RHS, true))
22390 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22394 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22395 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22396 const X86Subtarget *Subtarget) {
22397 EVT VT = N->getValueType(0);
22398 SDValue LHS = N->getOperand(0);
22399 SDValue RHS = N->getOperand(1);
22401 // Try to synthesize horizontal subs from subs of shuffles.
22402 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22403 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22404 isHorizontalBinOp(LHS, RHS, false))
22405 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22409 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22410 /// X86ISD::FXOR nodes.
22411 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22412 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22413 // F[X]OR(0.0, x) -> x
22414 // F[X]OR(x, 0.0) -> x
22415 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22416 if (C->getValueAPF().isPosZero())
22417 return N->getOperand(1);
22418 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22419 if (C->getValueAPF().isPosZero())
22420 return N->getOperand(0);
22424 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22425 /// X86ISD::FMAX nodes.
22426 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22427 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22429 // Only perform optimizations if UnsafeMath is used.
22430 if (!DAG.getTarget().Options.UnsafeFPMath)
22433 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22434 // into FMINC and FMAXC, which are Commutative operations.
22435 unsigned NewOp = 0;
22436 switch (N->getOpcode()) {
22437 default: llvm_unreachable("unknown opcode");
22438 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22439 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22442 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22443 N->getOperand(0), N->getOperand(1));
22446 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22447 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22448 // FAND(0.0, x) -> 0.0
22449 // FAND(x, 0.0) -> 0.0
22450 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22451 if (C->getValueAPF().isPosZero())
22452 return N->getOperand(0);
22453 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22454 if (C->getValueAPF().isPosZero())
22455 return N->getOperand(1);
22459 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22460 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22461 // FANDN(x, 0.0) -> 0.0
22462 // FANDN(0.0, x) -> x
22463 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22464 if (C->getValueAPF().isPosZero())
22465 return N->getOperand(1);
22466 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22467 if (C->getValueAPF().isPosZero())
22468 return N->getOperand(1);
22472 static SDValue PerformBTCombine(SDNode *N,
22474 TargetLowering::DAGCombinerInfo &DCI) {
22475 // BT ignores high bits in the bit index operand.
22476 SDValue Op1 = N->getOperand(1);
22477 if (Op1.hasOneUse()) {
22478 unsigned BitWidth = Op1.getValueSizeInBits();
22479 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22480 APInt KnownZero, KnownOne;
22481 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22482 !DCI.isBeforeLegalizeOps());
22483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22484 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22485 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22486 DCI.CommitTargetLoweringOpt(TLO);
22491 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22492 SDValue Op = N->getOperand(0);
22493 if (Op.getOpcode() == ISD::BITCAST)
22494 Op = Op.getOperand(0);
22495 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22496 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22497 VT.getVectorElementType().getSizeInBits() ==
22498 OpVT.getVectorElementType().getSizeInBits()) {
22499 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22504 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22505 const X86Subtarget *Subtarget) {
22506 EVT VT = N->getValueType(0);
22507 if (!VT.isVector())
22510 SDValue N0 = N->getOperand(0);
22511 SDValue N1 = N->getOperand(1);
22512 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22515 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22516 // both SSE and AVX2 since there is no sign-extended shift right
22517 // operation on a vector with 64-bit elements.
22518 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22519 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22520 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22521 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22522 SDValue N00 = N0.getOperand(0);
22524 // EXTLOAD has a better solution on AVX2,
22525 // it may be replaced with X86ISD::VSEXT node.
22526 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22527 if (!ISD::isNormalLoad(N00.getNode()))
22530 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22531 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22533 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22539 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22540 TargetLowering::DAGCombinerInfo &DCI,
22541 const X86Subtarget *Subtarget) {
22542 if (!DCI.isBeforeLegalizeOps())
22545 if (!Subtarget->hasFp256())
22548 EVT VT = N->getValueType(0);
22549 if (VT.isVector() && VT.getSizeInBits() == 256) {
22550 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22558 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22559 const X86Subtarget* Subtarget) {
22561 EVT VT = N->getValueType(0);
22563 // Let legalize expand this if it isn't a legal type yet.
22564 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22567 EVT ScalarVT = VT.getScalarType();
22568 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22569 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22572 SDValue A = N->getOperand(0);
22573 SDValue B = N->getOperand(1);
22574 SDValue C = N->getOperand(2);
22576 bool NegA = (A.getOpcode() == ISD::FNEG);
22577 bool NegB = (B.getOpcode() == ISD::FNEG);
22578 bool NegC = (C.getOpcode() == ISD::FNEG);
22580 // Negative multiplication when NegA xor NegB
22581 bool NegMul = (NegA != NegB);
22583 A = A.getOperand(0);
22585 B = B.getOperand(0);
22587 C = C.getOperand(0);
22591 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22593 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22595 return DAG.getNode(Opcode, dl, VT, A, B, C);
22598 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22599 TargetLowering::DAGCombinerInfo &DCI,
22600 const X86Subtarget *Subtarget) {
22601 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22602 // (and (i32 x86isd::setcc_carry), 1)
22603 // This eliminates the zext. This transformation is necessary because
22604 // ISD::SETCC is always legalized to i8.
22606 SDValue N0 = N->getOperand(0);
22607 EVT VT = N->getValueType(0);
22609 if (N0.getOpcode() == ISD::AND &&
22611 N0.getOperand(0).hasOneUse()) {
22612 SDValue N00 = N0.getOperand(0);
22613 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22614 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22615 if (!C || C->getZExtValue() != 1)
22617 return DAG.getNode(ISD::AND, dl, VT,
22618 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22619 N00.getOperand(0), N00.getOperand(1)),
22620 DAG.getConstant(1, VT));
22624 if (N0.getOpcode() == ISD::TRUNCATE &&
22626 N0.getOperand(0).hasOneUse()) {
22627 SDValue N00 = N0.getOperand(0);
22628 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22629 return DAG.getNode(ISD::AND, dl, VT,
22630 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22631 N00.getOperand(0), N00.getOperand(1)),
22632 DAG.getConstant(1, VT));
22635 if (VT.is256BitVector()) {
22636 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22644 // Optimize x == -y --> x+y == 0
22645 // x != -y --> x+y != 0
22646 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22647 const X86Subtarget* Subtarget) {
22648 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22649 SDValue LHS = N->getOperand(0);
22650 SDValue RHS = N->getOperand(1);
22651 EVT VT = N->getValueType(0);
22654 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22655 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22656 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22657 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22658 LHS.getValueType(), RHS, LHS.getOperand(1));
22659 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22660 addV, DAG.getConstant(0, addV.getValueType()), CC);
22662 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22664 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22665 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22666 RHS.getValueType(), LHS, RHS.getOperand(1));
22667 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22668 addV, DAG.getConstant(0, addV.getValueType()), CC);
22671 if (VT.getScalarType() == MVT::i1) {
22672 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22673 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22674 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22675 if (!IsSEXT0 && !IsVZero0)
22677 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22678 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22679 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22681 if (!IsSEXT1 && !IsVZero1)
22684 if (IsSEXT0 && IsVZero1) {
22685 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22686 if (CC == ISD::SETEQ)
22687 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22688 return LHS.getOperand(0);
22690 if (IsSEXT1 && IsVZero0) {
22691 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22692 if (CC == ISD::SETEQ)
22693 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22694 return RHS.getOperand(0);
22701 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22702 const X86Subtarget *Subtarget) {
22704 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22705 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22706 "X86insertps is only defined for v4x32");
22708 SDValue Ld = N->getOperand(1);
22709 if (MayFoldLoad(Ld)) {
22710 // Extract the countS bits from the immediate so we can get the proper
22711 // address when narrowing the vector load to a specific element.
22712 // When the second source op is a memory address, interps doesn't use
22713 // countS and just gets an f32 from that address.
22714 unsigned DestIndex =
22715 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22716 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22720 // Create this as a scalar to vector to match the instruction pattern.
22721 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22722 // countS bits are ignored when loading from memory on insertps, which
22723 // means we don't need to explicitly set them to 0.
22724 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22725 LoadScalarToVector, N->getOperand(2));
22728 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22729 // as "sbb reg,reg", since it can be extended without zext and produces
22730 // an all-ones bit which is more useful than 0/1 in some cases.
22731 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22734 return DAG.getNode(ISD::AND, DL, VT,
22735 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22736 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22737 DAG.getConstant(1, VT));
22738 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22739 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22740 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22741 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22744 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22745 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22746 TargetLowering::DAGCombinerInfo &DCI,
22747 const X86Subtarget *Subtarget) {
22749 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22750 SDValue EFLAGS = N->getOperand(1);
22752 if (CC == X86::COND_A) {
22753 // Try to convert COND_A into COND_B in an attempt to facilitate
22754 // materializing "setb reg".
22756 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22757 // cannot take an immediate as its first operand.
22759 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22760 EFLAGS.getValueType().isInteger() &&
22761 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22762 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22763 EFLAGS.getNode()->getVTList(),
22764 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22765 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22766 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22770 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22771 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22773 if (CC == X86::COND_B)
22774 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22778 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22779 if (Flags.getNode()) {
22780 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22781 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22787 // Optimize branch condition evaluation.
22789 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22790 TargetLowering::DAGCombinerInfo &DCI,
22791 const X86Subtarget *Subtarget) {
22793 SDValue Chain = N->getOperand(0);
22794 SDValue Dest = N->getOperand(1);
22795 SDValue EFLAGS = N->getOperand(3);
22796 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22800 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22801 if (Flags.getNode()) {
22802 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22803 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22810 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22811 SelectionDAG &DAG) {
22812 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22813 // optimize away operation when it's from a constant.
22815 // The general transformation is:
22816 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22817 // AND(VECTOR_CMP(x,y), constant2)
22818 // constant2 = UNARYOP(constant)
22820 // Early exit if this isn't a vector operation, the operand of the
22821 // unary operation isn't a bitwise AND, or if the sizes of the operations
22822 // aren't the same.
22823 EVT VT = N->getValueType(0);
22824 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22825 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22826 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22829 // Now check that the other operand of the AND is a constant. We could
22830 // make the transformation for non-constant splats as well, but it's unclear
22831 // that would be a benefit as it would not eliminate any operations, just
22832 // perform one more step in scalar code before moving to the vector unit.
22833 if (BuildVectorSDNode *BV =
22834 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22835 // Bail out if the vector isn't a constant.
22836 if (!BV->isConstant())
22839 // Everything checks out. Build up the new and improved node.
22841 EVT IntVT = BV->getValueType(0);
22842 // Create a new constant of the appropriate type for the transformed
22844 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22845 // The AND node needs bitcasts to/from an integer vector type around it.
22846 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22847 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22848 N->getOperand(0)->getOperand(0), MaskConst);
22849 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22856 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22857 const X86TargetLowering *XTLI) {
22858 // First try to optimize away the conversion entirely when it's
22859 // conditionally from a constant. Vectors only.
22860 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22861 if (Res != SDValue())
22864 // Now move on to more general possibilities.
22865 SDValue Op0 = N->getOperand(0);
22866 EVT InVT = Op0->getValueType(0);
22868 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22869 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22871 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22872 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22873 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22876 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22877 // a 32-bit target where SSE doesn't support i64->FP operations.
22878 if (Op0.getOpcode() == ISD::LOAD) {
22879 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22880 EVT VT = Ld->getValueType(0);
22881 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22882 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22883 !XTLI->getSubtarget()->is64Bit() &&
22885 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22886 Ld->getChain(), Op0, DAG);
22887 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22894 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22895 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22896 X86TargetLowering::DAGCombinerInfo &DCI) {
22897 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22898 // the result is either zero or one (depending on the input carry bit).
22899 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22900 if (X86::isZeroNode(N->getOperand(0)) &&
22901 X86::isZeroNode(N->getOperand(1)) &&
22902 // We don't have a good way to replace an EFLAGS use, so only do this when
22904 SDValue(N, 1).use_empty()) {
22906 EVT VT = N->getValueType(0);
22907 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22908 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22909 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22910 DAG.getConstant(X86::COND_B,MVT::i8),
22912 DAG.getConstant(1, VT));
22913 return DCI.CombineTo(N, Res1, CarryOut);
22919 // fold (add Y, (sete X, 0)) -> adc 0, Y
22920 // (add Y, (setne X, 0)) -> sbb -1, Y
22921 // (sub (sete X, 0), Y) -> sbb 0, Y
22922 // (sub (setne X, 0), Y) -> adc -1, Y
22923 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
22926 // Look through ZExts.
22927 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
22928 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
22931 SDValue SetCC = Ext.getOperand(0);
22932 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
22935 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
22936 if (CC != X86::COND_E && CC != X86::COND_NE)
22939 SDValue Cmp = SetCC.getOperand(1);
22940 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
22941 !X86::isZeroNode(Cmp.getOperand(1)) ||
22942 !Cmp.getOperand(0).getValueType().isInteger())
22945 SDValue CmpOp0 = Cmp.getOperand(0);
22946 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
22947 DAG.getConstant(1, CmpOp0.getValueType()));
22949 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
22950 if (CC == X86::COND_NE)
22951 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
22952 DL, OtherVal.getValueType(), OtherVal,
22953 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
22954 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
22955 DL, OtherVal.getValueType(), OtherVal,
22956 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
22959 /// PerformADDCombine - Do target-specific dag combines on integer adds.
22960 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
22961 const X86Subtarget *Subtarget) {
22962 EVT VT = N->getValueType(0);
22963 SDValue Op0 = N->getOperand(0);
22964 SDValue Op1 = N->getOperand(1);
22966 // Try to synthesize horizontal adds from adds of shuffles.
22967 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22968 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22969 isHorizontalBinOp(Op0, Op1, true))
22970 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
22972 return OptimizeConditionalInDecrement(N, DAG);
22975 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
22976 const X86Subtarget *Subtarget) {
22977 SDValue Op0 = N->getOperand(0);
22978 SDValue Op1 = N->getOperand(1);
22980 // X86 can't encode an immediate LHS of a sub. See if we can push the
22981 // negation into a preceding instruction.
22982 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
22983 // If the RHS of the sub is a XOR with one use and a constant, invert the
22984 // immediate. Then add one to the LHS of the sub so we can turn
22985 // X-Y -> X+~Y+1, saving one register.
22986 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
22987 isa<ConstantSDNode>(Op1.getOperand(1))) {
22988 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
22989 EVT VT = Op0.getValueType();
22990 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
22992 DAG.getConstant(~XorC, VT));
22993 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
22994 DAG.getConstant(C->getAPIntValue()+1, VT));
22998 // Try to synthesize horizontal adds from adds of shuffles.
22999 EVT VT = N->getValueType(0);
23000 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23001 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23002 isHorizontalBinOp(Op0, Op1, true))
23003 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23005 return OptimizeConditionalInDecrement(N, DAG);
23008 /// performVZEXTCombine - Performs build vector combines
23009 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23010 TargetLowering::DAGCombinerInfo &DCI,
23011 const X86Subtarget *Subtarget) {
23012 // (vzext (bitcast (vzext (x)) -> (vzext x)
23013 SDValue In = N->getOperand(0);
23014 while (In.getOpcode() == ISD::BITCAST)
23015 In = In.getOperand(0);
23017 if (In.getOpcode() != X86ISD::VZEXT)
23020 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
23024 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23025 DAGCombinerInfo &DCI) const {
23026 SelectionDAG &DAG = DCI.DAG;
23027 switch (N->getOpcode()) {
23029 case ISD::EXTRACT_VECTOR_ELT:
23030 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23032 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23033 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23034 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23035 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23036 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23037 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23040 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23041 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23042 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23043 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23044 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23045 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23046 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
23047 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23048 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23050 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23052 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23053 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23054 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23055 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23056 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23057 case ISD::ANY_EXTEND:
23058 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23059 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23060 case ISD::SIGN_EXTEND_INREG:
23061 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23062 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23063 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23064 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23065 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23066 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23067 case X86ISD::SHUFP: // Handle all target specific shuffles
23068 case X86ISD::PALIGNR:
23069 case X86ISD::UNPCKH:
23070 case X86ISD::UNPCKL:
23071 case X86ISD::MOVHLPS:
23072 case X86ISD::MOVLHPS:
23073 case X86ISD::PSHUFB:
23074 case X86ISD::PSHUFD:
23075 case X86ISD::PSHUFHW:
23076 case X86ISD::PSHUFLW:
23077 case X86ISD::MOVSS:
23078 case X86ISD::MOVSD:
23079 case X86ISD::VPERMILP:
23080 case X86ISD::VPERM2X128:
23081 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23082 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23083 case ISD::INTRINSIC_WO_CHAIN:
23084 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23085 case X86ISD::INSERTPS:
23086 return PerformINSERTPSCombine(N, DAG, Subtarget);
23087 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23093 /// isTypeDesirableForOp - Return true if the target has native support for
23094 /// the specified value type and it is 'desirable' to use the type for the
23095 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23096 /// instruction encodings are longer and some i16 instructions are slow.
23097 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23098 if (!isTypeLegal(VT))
23100 if (VT != MVT::i16)
23107 case ISD::SIGN_EXTEND:
23108 case ISD::ZERO_EXTEND:
23109 case ISD::ANY_EXTEND:
23122 /// IsDesirableToPromoteOp - This method query the target whether it is
23123 /// beneficial for dag combiner to promote the specified node. If true, it
23124 /// should return the desired promotion type by reference.
23125 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23126 EVT VT = Op.getValueType();
23127 if (VT != MVT::i16)
23130 bool Promote = false;
23131 bool Commute = false;
23132 switch (Op.getOpcode()) {
23135 LoadSDNode *LD = cast<LoadSDNode>(Op);
23136 // If the non-extending load has a single use and it's not live out, then it
23137 // might be folded.
23138 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23139 Op.hasOneUse()*/) {
23140 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23141 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23142 // The only case where we'd want to promote LOAD (rather then it being
23143 // promoted as an operand is when it's only use is liveout.
23144 if (UI->getOpcode() != ISD::CopyToReg)
23151 case ISD::SIGN_EXTEND:
23152 case ISD::ZERO_EXTEND:
23153 case ISD::ANY_EXTEND:
23158 SDValue N0 = Op.getOperand(0);
23159 // Look out for (store (shl (load), x)).
23160 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23173 SDValue N0 = Op.getOperand(0);
23174 SDValue N1 = Op.getOperand(1);
23175 if (!Commute && MayFoldLoad(N1))
23177 // Avoid disabling potential load folding opportunities.
23178 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23180 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
23190 //===----------------------------------------------------------------------===//
23191 // X86 Inline Assembly Support
23192 //===----------------------------------------------------------------------===//
23195 // Helper to match a string separated by whitespace.
23196 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
23197 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
23199 for (unsigned i = 0, e = args.size(); i != e; ++i) {
23200 StringRef piece(*args[i]);
23201 if (!s.startswith(piece)) // Check if the piece matches.
23204 s = s.substr(piece.size());
23205 StringRef::size_type pos = s.find_first_not_of(" \t");
23206 if (pos == 0) // We matched a prefix.
23214 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
23217 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
23219 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
23220 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
23221 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
23222 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
23224 if (AsmPieces.size() == 3)
23226 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
23233 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
23234 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
23236 std::string AsmStr = IA->getAsmString();
23238 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
23239 if (!Ty || Ty->getBitWidth() % 16 != 0)
23242 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
23243 SmallVector<StringRef, 4> AsmPieces;
23244 SplitString(AsmStr, AsmPieces, ";\n");
23246 switch (AsmPieces.size()) {
23247 default: return false;
23249 // FIXME: this should verify that we are targeting a 486 or better. If not,
23250 // we will turn this bswap into something that will be lowered to logical
23251 // ops instead of emitting the bswap asm. For now, we don't support 486 or
23252 // lower so don't worry about this.
23254 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
23255 matchAsm(AsmPieces[0], "bswapl", "$0") ||
23256 matchAsm(AsmPieces[0], "bswapq", "$0") ||
23257 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
23258 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
23259 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
23260 // No need to check constraints, nothing other than the equivalent of
23261 // "=r,0" would be valid here.
23262 return IntrinsicLowering::LowerToByteSwap(CI);
23265 // rorw $$8, ${0:w} --> llvm.bswap.i16
23266 if (CI->getType()->isIntegerTy(16) &&
23267 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23268 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
23269 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
23271 const std::string &ConstraintsStr = IA->getConstraintString();
23272 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23273 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23274 if (clobbersFlagRegisters(AsmPieces))
23275 return IntrinsicLowering::LowerToByteSwap(CI);
23279 if (CI->getType()->isIntegerTy(32) &&
23280 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
23281 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
23282 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
23283 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
23285 const std::string &ConstraintsStr = IA->getConstraintString();
23286 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
23287 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
23288 if (clobbersFlagRegisters(AsmPieces))
23289 return IntrinsicLowering::LowerToByteSwap(CI);
23292 if (CI->getType()->isIntegerTy(64)) {
23293 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
23294 if (Constraints.size() >= 2 &&
23295 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
23296 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
23297 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
23298 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
23299 matchAsm(AsmPieces[1], "bswap", "%edx") &&
23300 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
23301 return IntrinsicLowering::LowerToByteSwap(CI);
23309 /// getConstraintType - Given a constraint letter, return the type of
23310 /// constraint it is for this target.
23311 X86TargetLowering::ConstraintType
23312 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
23313 if (Constraint.size() == 1) {
23314 switch (Constraint[0]) {
23325 return C_RegisterClass;
23349 return TargetLowering::getConstraintType(Constraint);
23352 /// Examine constraint type and operand type and determine a weight value.
23353 /// This object must already have been set up with the operand type
23354 /// and the current alternative constraint selected.
23355 TargetLowering::ConstraintWeight
23356 X86TargetLowering::getSingleConstraintMatchWeight(
23357 AsmOperandInfo &info, const char *constraint) const {
23358 ConstraintWeight weight = CW_Invalid;
23359 Value *CallOperandVal = info.CallOperandVal;
23360 // If we don't have a value, we can't do a match,
23361 // but allow it at the lowest weight.
23362 if (!CallOperandVal)
23364 Type *type = CallOperandVal->getType();
23365 // Look at the constraint type.
23366 switch (*constraint) {
23368 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
23379 if (CallOperandVal->getType()->isIntegerTy())
23380 weight = CW_SpecificReg;
23385 if (type->isFloatingPointTy())
23386 weight = CW_SpecificReg;
23389 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23390 weight = CW_SpecificReg;
23394 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23395 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23396 weight = CW_Register;
23399 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23400 if (C->getZExtValue() <= 31)
23401 weight = CW_Constant;
23405 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23406 if (C->getZExtValue() <= 63)
23407 weight = CW_Constant;
23411 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23412 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23413 weight = CW_Constant;
23417 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23418 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23419 weight = CW_Constant;
23423 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23424 if (C->getZExtValue() <= 3)
23425 weight = CW_Constant;
23429 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23430 if (C->getZExtValue() <= 0xff)
23431 weight = CW_Constant;
23436 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23437 weight = CW_Constant;
23441 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23442 if ((C->getSExtValue() >= -0x80000000LL) &&
23443 (C->getSExtValue() <= 0x7fffffffLL))
23444 weight = CW_Constant;
23448 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23449 if (C->getZExtValue() <= 0xffffffff)
23450 weight = CW_Constant;
23457 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23458 /// with another that has more specific requirements based on the type of the
23459 /// corresponding operand.
23460 const char *X86TargetLowering::
23461 LowerXConstraint(EVT ConstraintVT) const {
23462 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23463 // 'f' like normal targets.
23464 if (ConstraintVT.isFloatingPoint()) {
23465 if (Subtarget->hasSSE2())
23467 if (Subtarget->hasSSE1())
23471 return TargetLowering::LowerXConstraint(ConstraintVT);
23474 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23475 /// vector. If it is invalid, don't add anything to Ops.
23476 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23477 std::string &Constraint,
23478 std::vector<SDValue>&Ops,
23479 SelectionDAG &DAG) const {
23482 // Only support length 1 constraints for now.
23483 if (Constraint.length() > 1) return;
23485 char ConstraintLetter = Constraint[0];
23486 switch (ConstraintLetter) {
23489 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23490 if (C->getZExtValue() <= 31) {
23491 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23497 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23498 if (C->getZExtValue() <= 63) {
23499 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23506 if (isInt<8>(C->getSExtValue())) {
23507 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23513 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23514 if (C->getZExtValue() <= 255) {
23515 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23521 // 32-bit signed value
23522 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23523 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23524 C->getSExtValue())) {
23525 // Widen to 64 bits here to get it sign extended.
23526 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23529 // FIXME gcc accepts some relocatable values here too, but only in certain
23530 // memory models; it's complicated.
23535 // 32-bit unsigned value
23536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23537 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23538 C->getZExtValue())) {
23539 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23543 // FIXME gcc accepts some relocatable values here too, but only in certain
23544 // memory models; it's complicated.
23548 // Literal immediates are always ok.
23549 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23550 // Widen to 64 bits here to get it sign extended.
23551 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23555 // In any sort of PIC mode addresses need to be computed at runtime by
23556 // adding in a register or some sort of table lookup. These can't
23557 // be used as immediates.
23558 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23561 // If we are in non-pic codegen mode, we allow the address of a global (with
23562 // an optional displacement) to be used with 'i'.
23563 GlobalAddressSDNode *GA = nullptr;
23564 int64_t Offset = 0;
23566 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23568 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23569 Offset += GA->getOffset();
23571 } else if (Op.getOpcode() == ISD::ADD) {
23572 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23573 Offset += C->getZExtValue();
23574 Op = Op.getOperand(0);
23577 } else if (Op.getOpcode() == ISD::SUB) {
23578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23579 Offset += -C->getZExtValue();
23580 Op = Op.getOperand(0);
23585 // Otherwise, this isn't something we can handle, reject it.
23589 const GlobalValue *GV = GA->getGlobal();
23590 // If we require an extra load to get this address, as in PIC mode, we
23591 // can't accept it.
23592 if (isGlobalStubReference(
23593 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23596 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23597 GA->getValueType(0), Offset);
23602 if (Result.getNode()) {
23603 Ops.push_back(Result);
23606 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23609 std::pair<unsigned, const TargetRegisterClass*>
23610 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23612 // First, see if this is a constraint that directly corresponds to an LLVM
23614 if (Constraint.size() == 1) {
23615 // GCC Constraint Letters
23616 switch (Constraint[0]) {
23618 // TODO: Slight differences here in allocation order and leaving
23619 // RIP in the class. Do they matter any more here than they do
23620 // in the normal allocation?
23621 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23622 if (Subtarget->is64Bit()) {
23623 if (VT == MVT::i32 || VT == MVT::f32)
23624 return std::make_pair(0U, &X86::GR32RegClass);
23625 if (VT == MVT::i16)
23626 return std::make_pair(0U, &X86::GR16RegClass);
23627 if (VT == MVT::i8 || VT == MVT::i1)
23628 return std::make_pair(0U, &X86::GR8RegClass);
23629 if (VT == MVT::i64 || VT == MVT::f64)
23630 return std::make_pair(0U, &X86::GR64RegClass);
23633 // 32-bit fallthrough
23634 case 'Q': // Q_REGS
23635 if (VT == MVT::i32 || VT == MVT::f32)
23636 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23637 if (VT == MVT::i16)
23638 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23639 if (VT == MVT::i8 || VT == MVT::i1)
23640 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23641 if (VT == MVT::i64)
23642 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23644 case 'r': // GENERAL_REGS
23645 case 'l': // INDEX_REGS
23646 if (VT == MVT::i8 || VT == MVT::i1)
23647 return std::make_pair(0U, &X86::GR8RegClass);
23648 if (VT == MVT::i16)
23649 return std::make_pair(0U, &X86::GR16RegClass);
23650 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23651 return std::make_pair(0U, &X86::GR32RegClass);
23652 return std::make_pair(0U, &X86::GR64RegClass);
23653 case 'R': // LEGACY_REGS
23654 if (VT == MVT::i8 || VT == MVT::i1)
23655 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23656 if (VT == MVT::i16)
23657 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23658 if (VT == MVT::i32 || !Subtarget->is64Bit())
23659 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23660 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23661 case 'f': // FP Stack registers.
23662 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23663 // value to the correct fpstack register class.
23664 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23665 return std::make_pair(0U, &X86::RFP32RegClass);
23666 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23667 return std::make_pair(0U, &X86::RFP64RegClass);
23668 return std::make_pair(0U, &X86::RFP80RegClass);
23669 case 'y': // MMX_REGS if MMX allowed.
23670 if (!Subtarget->hasMMX()) break;
23671 return std::make_pair(0U, &X86::VR64RegClass);
23672 case 'Y': // SSE_REGS if SSE2 allowed
23673 if (!Subtarget->hasSSE2()) break;
23675 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23676 if (!Subtarget->hasSSE1()) break;
23678 switch (VT.SimpleTy) {
23680 // Scalar SSE types.
23683 return std::make_pair(0U, &X86::FR32RegClass);
23686 return std::make_pair(0U, &X86::FR64RegClass);
23694 return std::make_pair(0U, &X86::VR128RegClass);
23702 return std::make_pair(0U, &X86::VR256RegClass);
23707 return std::make_pair(0U, &X86::VR512RegClass);
23713 // Use the default implementation in TargetLowering to convert the register
23714 // constraint into a member of a register class.
23715 std::pair<unsigned, const TargetRegisterClass*> Res;
23716 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23718 // Not found as a standard register?
23720 // Map st(0) -> st(7) -> ST0
23721 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23722 tolower(Constraint[1]) == 's' &&
23723 tolower(Constraint[2]) == 't' &&
23724 Constraint[3] == '(' &&
23725 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23726 Constraint[5] == ')' &&
23727 Constraint[6] == '}') {
23729 Res.first = X86::FP0+Constraint[4]-'0';
23730 Res.second = &X86::RFP80RegClass;
23734 // GCC allows "st(0)" to be called just plain "st".
23735 if (StringRef("{st}").equals_lower(Constraint)) {
23736 Res.first = X86::FP0;
23737 Res.second = &X86::RFP80RegClass;
23742 if (StringRef("{flags}").equals_lower(Constraint)) {
23743 Res.first = X86::EFLAGS;
23744 Res.second = &X86::CCRRegClass;
23748 // 'A' means EAX + EDX.
23749 if (Constraint == "A") {
23750 Res.first = X86::EAX;
23751 Res.second = &X86::GR32_ADRegClass;
23757 // Otherwise, check to see if this is a register class of the wrong value
23758 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23759 // turn into {ax},{dx}.
23760 if (Res.second->hasType(VT))
23761 return Res; // Correct type already, nothing to do.
23763 // All of the single-register GCC register classes map their values onto
23764 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23765 // really want an 8-bit or 32-bit register, map to the appropriate register
23766 // class and return the appropriate register.
23767 if (Res.second == &X86::GR16RegClass) {
23768 if (VT == MVT::i8 || VT == MVT::i1) {
23769 unsigned DestReg = 0;
23770 switch (Res.first) {
23772 case X86::AX: DestReg = X86::AL; break;
23773 case X86::DX: DestReg = X86::DL; break;
23774 case X86::CX: DestReg = X86::CL; break;
23775 case X86::BX: DestReg = X86::BL; break;
23778 Res.first = DestReg;
23779 Res.second = &X86::GR8RegClass;
23781 } else if (VT == MVT::i32 || VT == MVT::f32) {
23782 unsigned DestReg = 0;
23783 switch (Res.first) {
23785 case X86::AX: DestReg = X86::EAX; break;
23786 case X86::DX: DestReg = X86::EDX; break;
23787 case X86::CX: DestReg = X86::ECX; break;
23788 case X86::BX: DestReg = X86::EBX; break;
23789 case X86::SI: DestReg = X86::ESI; break;
23790 case X86::DI: DestReg = X86::EDI; break;
23791 case X86::BP: DestReg = X86::EBP; break;
23792 case X86::SP: DestReg = X86::ESP; break;
23795 Res.first = DestReg;
23796 Res.second = &X86::GR32RegClass;
23798 } else if (VT == MVT::i64 || VT == MVT::f64) {
23799 unsigned DestReg = 0;
23800 switch (Res.first) {
23802 case X86::AX: DestReg = X86::RAX; break;
23803 case X86::DX: DestReg = X86::RDX; break;
23804 case X86::CX: DestReg = X86::RCX; break;
23805 case X86::BX: DestReg = X86::RBX; break;
23806 case X86::SI: DestReg = X86::RSI; break;
23807 case X86::DI: DestReg = X86::RDI; break;
23808 case X86::BP: DestReg = X86::RBP; break;
23809 case X86::SP: DestReg = X86::RSP; break;
23812 Res.first = DestReg;
23813 Res.second = &X86::GR64RegClass;
23816 } else if (Res.second == &X86::FR32RegClass ||
23817 Res.second == &X86::FR64RegClass ||
23818 Res.second == &X86::VR128RegClass ||
23819 Res.second == &X86::VR256RegClass ||
23820 Res.second == &X86::FR32XRegClass ||
23821 Res.second == &X86::FR64XRegClass ||
23822 Res.second == &X86::VR128XRegClass ||
23823 Res.second == &X86::VR256XRegClass ||
23824 Res.second == &X86::VR512RegClass) {
23825 // Handle references to XMM physical registers that got mapped into the
23826 // wrong class. This can happen with constraints like {xmm0} where the
23827 // target independent register mapper will just pick the first match it can
23828 // find, ignoring the required type.
23830 if (VT == MVT::f32 || VT == MVT::i32)
23831 Res.second = &X86::FR32RegClass;
23832 else if (VT == MVT::f64 || VT == MVT::i64)
23833 Res.second = &X86::FR64RegClass;
23834 else if (X86::VR128RegClass.hasType(VT))
23835 Res.second = &X86::VR128RegClass;
23836 else if (X86::VR256RegClass.hasType(VT))
23837 Res.second = &X86::VR256RegClass;
23838 else if (X86::VR512RegClass.hasType(VT))
23839 Res.second = &X86::VR512RegClass;
23845 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23847 // Scaling factors are not free at all.
23848 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23849 // will take 2 allocations in the out of order engine instead of 1
23850 // for plain addressing mode, i.e. inst (reg1).
23852 // vaddps (%rsi,%drx), %ymm0, %ymm1
23853 // Requires two allocations (one for the load, one for the computation)
23855 // vaddps (%rsi), %ymm0, %ymm1
23856 // Requires just 1 allocation, i.e., freeing allocations for other operations
23857 // and having less micro operations to execute.
23859 // For some X86 architectures, this is even worse because for instance for
23860 // stores, the complex addressing mode forces the instruction to use the
23861 // "load" ports instead of the dedicated "store" port.
23862 // E.g., on Haswell:
23863 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23864 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23865 if (isLegalAddressingMode(AM, Ty))
23866 // Scale represents reg2 * scale, thus account for 1
23867 // as soon as we use a second register.
23868 return AM.Scale != 0;
23872 bool X86TargetLowering::isTargetFTOL() const {
23873 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();