1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
118 // The _ftol2 runtime function has an unusual calling conv, which
119 // is modeled by a special pseudo-instruction.
120 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
121 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
122 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
123 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
126 if (Subtarget->isTargetDarwin()) {
127 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
128 setUseUnderscoreSetJmp(false);
129 setUseUnderscoreLongJmp(false);
130 } else if (Subtarget->isTargetWindowsGNU()) {
131 // MS runtime is weird: it exports _setjmp, but longjmp!
132 setUseUnderscoreSetJmp(true);
133 setUseUnderscoreLongJmp(false);
135 setUseUnderscoreSetJmp(true);
136 setUseUnderscoreLongJmp(true);
139 // Set up the register classes.
140 addRegisterClass(MVT::i8, &X86::GR8RegClass);
141 addRegisterClass(MVT::i16, &X86::GR16RegClass);
142 addRegisterClass(MVT::i32, &X86::GR32RegClass);
143 if (Subtarget->is64Bit())
144 addRegisterClass(MVT::i64, &X86::GR64RegClass);
146 for (MVT VT : MVT::integer_valuetypes())
147 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
149 // We don't accept any truncstore of integer registers.
150 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
151 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
152 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
153 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
154 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
155 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
157 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
159 // SETOEQ and SETUNE require checking two conditions.
160 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
161 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
162 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
163 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
164 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
165 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
167 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
169 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
170 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
173 if (Subtarget->is64Bit()) {
174 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
176 } else if (!Subtarget->useSoftFloat()) {
177 // We have an algorithm for SSE2->double, and we turn this into a
178 // 64-bit FILD followed by conditional FADD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 // We have an algorithm for SSE2, and we turn this into a 64-bit
181 // FILD for other targets.
182 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
185 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
187 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
188 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
190 if (!Subtarget->useSoftFloat()) {
191 // SSE has no i16 to fp conversion, only i32
192 if (X86ScalarSSEf32) {
193 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
194 // f32 and f64 cases are Legal, f80 case is not
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
205 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
206 // are Legal, f80 is custom lowered.
207 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
210 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
212 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
213 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
215 if (X86ScalarSSEf32) {
216 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
217 // f32 and f64 cases are Legal, f80 case is not
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
221 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 // Handle FP_TO_UINT by promoting the destination to a larger signed
226 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
227 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
228 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
230 if (Subtarget->is64Bit()) {
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
233 } else if (!Subtarget->useSoftFloat()) {
234 // Since AVX is a superset of SSE3, only check for SSE here.
235 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
236 // Expand FP_TO_UINT into a select.
237 // FIXME: We would like to use a Custom expander here eventually to do
238 // the optimal thing for SSE vs. the default expansion in the legalizer.
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
241 // With SSE3 we can use fisttpll to convert to a signed i64; without
242 // SSE, we're stuck with a fistpll.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
246 if (isTargetFTOL()) {
247 // Use the _ftol2 runtime function, which has a pseudo-instruction
248 // to handle its weird calling convention.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
311 setOperationAction(ISD::FREM , MVT::f32 , Expand);
312 setOperationAction(ISD::FREM , MVT::f64 , Expand);
313 setOperationAction(ISD::FREM , MVT::f80 , Expand);
314 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
316 // Promote the i8 variants and force them on up to i32 which has a shorter
318 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
319 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
320 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
321 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
322 if (Subtarget->hasBMI()) {
323 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
325 if (Subtarget->is64Bit())
326 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
328 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
329 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
330 if (Subtarget->is64Bit())
331 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
334 if (Subtarget->hasLZCNT()) {
335 // When promoting the i8 variants, force them to i32 for a shorter
337 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
338 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
339 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
340 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
341 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
342 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
343 if (Subtarget->is64Bit())
344 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
346 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
347 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
348 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
350 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
352 if (Subtarget->is64Bit()) {
353 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
358 // Special handling for half-precision floating point conversions.
359 // If we don't have F16C support, then lower half float conversions
360 // into library calls.
361 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
362 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
363 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
366 // There's never any support for operations beyond MVT::f32.
367 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
368 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
369 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
370 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
372 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
373 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
374 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
375 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
376 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
377 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
379 if (Subtarget->hasPOPCNT()) {
380 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
382 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
383 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
384 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
385 if (Subtarget->is64Bit())
386 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
389 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
391 if (!Subtarget->hasMOVBE())
392 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
394 // These should be promoted to a larger select which is supported.
395 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
396 // X86 wants to expand cmov itself.
397 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
398 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
399 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
400 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
401 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
402 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
403 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
404 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
405 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
406 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
407 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
408 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
409 if (Subtarget->is64Bit()) {
410 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
413 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
414 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
415 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
416 // support continuation, user-level threading, and etc.. As a result, no
417 // other SjLj exception interfaces are implemented and please don't build
418 // your own exception handling based on them.
419 // LLVM/Clang supports zero-cost DWARF exception handling.
420 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
421 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasSSE1())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
454 // Expand certain atomics
455 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
457 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
458 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
459 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
462 if (Subtarget->hasCmpxchg16b()) {
463 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
466 // FIXME - use subtarget debug flags
467 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
468 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
469 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
472 if (Subtarget->isTarget64BitLP64()) {
473 setExceptionPointerRegister(X86::RAX);
474 setExceptionSelectorRegister(X86::RDX);
476 setExceptionPointerRegister(X86::EAX);
477 setExceptionSelectorRegister(X86::EDX);
479 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
480 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
482 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
483 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
485 setOperationAction(ISD::TRAP, MVT::Other, Legal);
486 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
488 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
489 setOperationAction(ISD::VASTART , MVT::Other, Custom);
490 setOperationAction(ISD::VAEND , MVT::Other, Expand);
491 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
492 // TargetInfo::X86_64ABIBuiltinVaList
493 setOperationAction(ISD::VAARG , MVT::Other, Custom);
494 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
496 // TargetInfo::CharPtrBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Expand);
498 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
501 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
502 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
504 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
506 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
507 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
508 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
510 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
511 // f32 and f64 use SSE.
512 // Set up the FP register classes.
513 addRegisterClass(MVT::f32, &X86::FR32RegClass);
514 addRegisterClass(MVT::f64, &X86::FR64RegClass);
516 // Use ANDPD to simulate FABS.
517 setOperationAction(ISD::FABS , MVT::f64, Custom);
518 setOperationAction(ISD::FABS , MVT::f32, Custom);
520 // Use XORP to simulate FNEG.
521 setOperationAction(ISD::FNEG , MVT::f64, Custom);
522 setOperationAction(ISD::FNEG , MVT::f32, Custom);
524 // Use ANDPD and ORPD to simulate FCOPYSIGN.
525 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
526 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
528 // Lower this to FGETSIGNx86 plus an AND.
529 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
530 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
532 // We don't support sin/cos/fmod
533 setOperationAction(ISD::FSIN , MVT::f64, Expand);
534 setOperationAction(ISD::FCOS , MVT::f64, Expand);
535 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
536 setOperationAction(ISD::FSIN , MVT::f32, Expand);
537 setOperationAction(ISD::FCOS , MVT::f32, Expand);
538 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
540 // Expand FP immediates into loads from the stack, except for the special
542 addLegalFPImmediate(APFloat(+0.0)); // xorpd
543 addLegalFPImmediate(APFloat(+0.0f)); // xorps
544 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
545 // Use SSE for f32, x87 for f64.
546 // Set up the FP register classes.
547 addRegisterClass(MVT::f32, &X86::FR32RegClass);
548 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
550 // Use ANDPS to simulate FABS.
551 setOperationAction(ISD::FABS , MVT::f32, Custom);
553 // Use XORP to simulate FNEG.
554 setOperationAction(ISD::FNEG , MVT::f32, Custom);
556 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
558 // Use ANDPS and ORPS to simulate FCOPYSIGN.
559 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
560 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
562 // We don't support sin/cos/fmod
563 setOperationAction(ISD::FSIN , MVT::f32, Expand);
564 setOperationAction(ISD::FCOS , MVT::f32, Expand);
565 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
567 // Special cases we handle for FP constants.
568 addLegalFPImmediate(APFloat(+0.0f)); // xorps
569 addLegalFPImmediate(APFloat(+0.0)); // FLD0
570 addLegalFPImmediate(APFloat(+1.0)); // FLD1
571 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
572 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
574 if (!TM.Options.UnsafeFPMath) {
575 setOperationAction(ISD::FSIN , MVT::f64, Expand);
576 setOperationAction(ISD::FCOS , MVT::f64, Expand);
577 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
579 } else if (!Subtarget->useSoftFloat()) {
580 // f32 and f64 in x87.
581 // Set up the FP register classes.
582 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
583 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
585 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
586 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
587 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
588 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
590 if (!TM.Options.UnsafeFPMath) {
591 setOperationAction(ISD::FSIN , MVT::f64, Expand);
592 setOperationAction(ISD::FSIN , MVT::f32, Expand);
593 setOperationAction(ISD::FCOS , MVT::f64, Expand);
594 setOperationAction(ISD::FCOS , MVT::f32, Expand);
595 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
596 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
598 addLegalFPImmediate(APFloat(+0.0)); // FLD0
599 addLegalFPImmediate(APFloat(+1.0)); // FLD1
600 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
601 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
602 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
608 // We don't support FMA.
609 setOperationAction(ISD::FMA, MVT::f64, Expand);
610 setOperationAction(ISD::FMA, MVT::f32, Expand);
612 // Long double always uses X87.
613 if (!Subtarget->useSoftFloat()) {
614 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
615 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
616 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
618 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
619 addLegalFPImmediate(TmpFlt); // FLD0
621 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
624 APFloat TmpFlt2(+1.0);
625 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
627 addLegalFPImmediate(TmpFlt2); // FLD1
628 TmpFlt2.changeSign();
629 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
632 if (!TM.Options.UnsafeFPMath) {
633 setOperationAction(ISD::FSIN , MVT::f80, Expand);
634 setOperationAction(ISD::FCOS , MVT::f80, Expand);
635 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
638 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
639 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
640 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
641 setOperationAction(ISD::FRINT, MVT::f80, Expand);
642 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
643 setOperationAction(ISD::FMA, MVT::f80, Expand);
646 // Always use a library call for pow.
647 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
648 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
649 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
651 setOperationAction(ISD::FLOG, MVT::f80, Expand);
652 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
653 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
654 setOperationAction(ISD::FEXP, MVT::f80, Expand);
655 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
656 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
657 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
659 // First set operation action for all vector types to either promote
660 // (for widening) or expand (for scalarization). Then we will selectively
661 // turn on ones that can be effectively codegen'd.
662 for (MVT VT : MVT::vector_valuetypes()) {
663 setOperationAction(ISD::ADD , VT, Expand);
664 setOperationAction(ISD::SUB , VT, Expand);
665 setOperationAction(ISD::FADD, VT, Expand);
666 setOperationAction(ISD::FNEG, VT, Expand);
667 setOperationAction(ISD::FSUB, VT, Expand);
668 setOperationAction(ISD::MUL , VT, Expand);
669 setOperationAction(ISD::FMUL, VT, Expand);
670 setOperationAction(ISD::SDIV, VT, Expand);
671 setOperationAction(ISD::UDIV, VT, Expand);
672 setOperationAction(ISD::FDIV, VT, Expand);
673 setOperationAction(ISD::SREM, VT, Expand);
674 setOperationAction(ISD::UREM, VT, Expand);
675 setOperationAction(ISD::LOAD, VT, Expand);
676 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
677 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
678 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
679 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
680 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
681 setOperationAction(ISD::FABS, VT, Expand);
682 setOperationAction(ISD::FSIN, VT, Expand);
683 setOperationAction(ISD::FSINCOS, VT, Expand);
684 setOperationAction(ISD::FCOS, VT, Expand);
685 setOperationAction(ISD::FSINCOS, VT, Expand);
686 setOperationAction(ISD::FREM, VT, Expand);
687 setOperationAction(ISD::FMA, VT, Expand);
688 setOperationAction(ISD::FPOWI, VT, Expand);
689 setOperationAction(ISD::FSQRT, VT, Expand);
690 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
691 setOperationAction(ISD::FFLOOR, VT, Expand);
692 setOperationAction(ISD::FCEIL, VT, Expand);
693 setOperationAction(ISD::FTRUNC, VT, Expand);
694 setOperationAction(ISD::FRINT, VT, Expand);
695 setOperationAction(ISD::FNEARBYINT, VT, Expand);
696 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
697 setOperationAction(ISD::MULHS, VT, Expand);
698 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
699 setOperationAction(ISD::MULHU, VT, Expand);
700 setOperationAction(ISD::SDIVREM, VT, Expand);
701 setOperationAction(ISD::UDIVREM, VT, Expand);
702 setOperationAction(ISD::FPOW, VT, Expand);
703 setOperationAction(ISD::CTPOP, VT, Expand);
704 setOperationAction(ISD::CTTZ, VT, Expand);
705 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
706 setOperationAction(ISD::CTLZ, VT, Expand);
707 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
708 setOperationAction(ISD::SHL, VT, Expand);
709 setOperationAction(ISD::SRA, VT, Expand);
710 setOperationAction(ISD::SRL, VT, Expand);
711 setOperationAction(ISD::ROTL, VT, Expand);
712 setOperationAction(ISD::ROTR, VT, Expand);
713 setOperationAction(ISD::BSWAP, VT, Expand);
714 setOperationAction(ISD::SETCC, VT, Expand);
715 setOperationAction(ISD::FLOG, VT, Expand);
716 setOperationAction(ISD::FLOG2, VT, Expand);
717 setOperationAction(ISD::FLOG10, VT, Expand);
718 setOperationAction(ISD::FEXP, VT, Expand);
719 setOperationAction(ISD::FEXP2, VT, Expand);
720 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
721 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
722 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
723 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
724 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
725 setOperationAction(ISD::TRUNCATE, VT, Expand);
726 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
727 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
728 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
729 setOperationAction(ISD::VSELECT, VT, Expand);
730 setOperationAction(ISD::SELECT_CC, VT, Expand);
731 for (MVT InnerVT : MVT::vector_valuetypes()) {
732 setTruncStoreAction(InnerVT, VT, Expand);
734 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
735 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
737 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
738 // types, we have to deal with them whether we ask for Expansion or not.
739 // Setting Expand causes its own optimisation problems though, so leave
741 if (VT.getVectorElementType() == MVT::i1)
742 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
744 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
745 // split/scalarized right now.
746 if (VT.getVectorElementType() == MVT::f16)
747 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
751 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
752 // with -msoft-float, disable use of MMX as well.
753 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
754 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
755 // No operations on x86mmx supported, everything uses intrinsics.
758 // MMX-sized vectors (other than x86mmx) are expected to be expanded
759 // into smaller operations.
760 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
761 setOperationAction(ISD::MULHS, MMXTy, Expand);
762 setOperationAction(ISD::AND, MMXTy, Expand);
763 setOperationAction(ISD::OR, MMXTy, Expand);
764 setOperationAction(ISD::XOR, MMXTy, Expand);
765 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
766 setOperationAction(ISD::SELECT, MMXTy, Expand);
767 setOperationAction(ISD::BITCAST, MMXTy, Expand);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
771 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
772 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
774 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
775 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
776 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
777 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
778 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
779 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
780 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
781 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
782 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
783 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
784 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
785 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
786 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
787 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
790 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
791 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
793 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
794 // registers cannot be used even for integer operations.
795 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
796 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
797 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
798 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
800 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
801 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
802 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
803 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
804 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
805 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
806 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
807 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
808 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
809 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
810 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
811 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
812 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
813 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
814 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
815 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
816 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
817 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
818 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
819 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
820 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
821 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
822 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
824 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
825 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
826 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
827 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
829 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
830 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
831 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
832 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
834 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
835 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
838 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
841 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
842 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
843 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
845 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
846 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
847 MVT VT = (MVT::SimpleValueType)i;
848 // Do not attempt to custom lower non-power-of-2 vectors
849 if (!isPowerOf2_32(VT.getVectorNumElements()))
851 // Do not attempt to custom lower non-128-bit vectors
852 if (!VT.is128BitVector())
854 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
855 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
856 setOperationAction(ISD::VSELECT, VT, Custom);
857 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
860 // We support custom legalizing of sext and anyext loads for specific
861 // memory vector types which we can load as a scalar (or sequence of
862 // scalars) and extend in-register to a legal 128-bit vector type. For sext
863 // loads these must work with a single scalar load.
864 for (MVT VT : MVT::integer_vector_valuetypes()) {
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
866 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
867 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
877 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
879 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
880 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
881 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
882 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
883 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
885 if (Subtarget->is64Bit()) {
886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
887 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
890 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
891 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
892 MVT VT = (MVT::SimpleValueType)i;
894 // Do not attempt to promote non-128-bit vectors
895 if (!VT.is128BitVector())
898 setOperationAction(ISD::AND, VT, Promote);
899 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
900 setOperationAction(ISD::OR, VT, Promote);
901 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
902 setOperationAction(ISD::XOR, VT, Promote);
903 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
904 setOperationAction(ISD::LOAD, VT, Promote);
905 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
906 setOperationAction(ISD::SELECT, VT, Promote);
907 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
910 // Custom lower v2i64 and v2f64 selects.
911 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
912 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
913 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
914 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
916 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
917 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
919 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
921 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
922 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
923 // As there is no 64-bit GPR available, we need build a special custom
924 // sequence to convert from v2i32 to v2f32.
925 if (!Subtarget->is64Bit())
926 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
928 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
929 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
931 for (MVT VT : MVT::fp_vector_valuetypes())
932 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
934 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
935 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
936 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
939 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
940 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
941 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
942 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
943 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
944 setOperationAction(ISD::FRINT, RoundedTy, Legal);
945 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
948 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
949 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
950 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
951 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
952 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
953 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
954 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
955 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
957 // FIXME: Do we need to handle scalar-to-vector here?
958 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
960 // We directly match byte blends in the backend as they match the VSELECT
962 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
964 // SSE41 brings specific instructions for doing vector sign extend even in
965 // cases where we don't have SRA.
966 for (MVT VT : MVT::integer_vector_valuetypes()) {
967 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
968 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
969 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
972 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
973 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
974 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
975 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
976 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
980 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
981 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
982 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
983 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
987 // i8 and i16 vectors are custom because the source register and source
988 // source memory operand types are not the same width. f32 vectors are
989 // custom since the immediate controlling the insert encodes additional
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
994 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
996 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
997 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
998 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
999 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1001 // FIXME: these should be Legal, but that's only for the case where
1002 // the index is constant. For now custom expand to deal with that.
1003 if (Subtarget->is64Bit()) {
1004 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1009 if (Subtarget->hasSSE2()) {
1010 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1011 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1012 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1014 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1015 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1017 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1018 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1020 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1023 // In the customized shift lowering, the legal cases in AVX2 will be
1025 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1026 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1028 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1031 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1035 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1036 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1037 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1038 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1039 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1040 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1041 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1043 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1044 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1045 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1047 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1048 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1049 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1050 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1051 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1052 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1053 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1054 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1056 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1057 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1058 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1060 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1061 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1062 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1063 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1064 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1066 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1067 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1070 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1071 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1073 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1074 // even though v8i16 is a legal type.
1075 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1076 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1077 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1079 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1080 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1081 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1083 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1084 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1086 for (MVT VT : MVT::fp_vector_valuetypes())
1087 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1089 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1090 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1092 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1093 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1095 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1096 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1098 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1099 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1100 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1101 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1103 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1104 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1105 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1107 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1108 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1109 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1110 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1111 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1112 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1113 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1114 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1115 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1116 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1117 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1118 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1120 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1121 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1122 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1123 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1125 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1126 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1127 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1128 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1129 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1130 setOperationAction(ISD::FMA, MVT::f32, Legal);
1131 setOperationAction(ISD::FMA, MVT::f64, Legal);
1134 if (Subtarget->hasInt256()) {
1135 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1136 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1137 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1138 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1140 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1141 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1142 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1143 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1145 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1146 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1147 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1148 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1150 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1151 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1152 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1153 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1155 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1156 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1157 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1158 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1159 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1160 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1161 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1162 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1163 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1164 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1165 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1166 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1168 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1169 // when we have a 256bit-wide blend with immediate.
1170 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1172 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1173 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1174 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1175 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1176 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1177 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1178 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1180 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1181 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1182 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1183 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1184 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1185 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1187 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1188 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1189 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1190 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1192 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1194 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1195 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1197 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1198 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1199 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1200 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1202 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1203 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1204 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1205 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1206 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1207 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1208 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1209 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1210 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1211 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1212 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1213 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1216 // In the customized shift lowering, the legal cases in AVX2 will be
1218 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1224 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1225 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1227 // Custom lower several nodes for 256-bit types.
1228 for (MVT VT : MVT::vector_valuetypes()) {
1229 if (VT.getScalarSizeInBits() >= 32) {
1230 setOperationAction(ISD::MLOAD, VT, Legal);
1231 setOperationAction(ISD::MSTORE, VT, Legal);
1233 // Extract subvector is special because the value type
1234 // (result) is 128-bit but the source is 256-bit wide.
1235 if (VT.is128BitVector()) {
1236 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1238 // Do not attempt to custom lower other non-256-bit vectors
1239 if (!VT.is256BitVector())
1242 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1243 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1244 setOperationAction(ISD::VSELECT, VT, Custom);
1245 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1246 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1247 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1248 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1249 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1252 if (Subtarget->hasInt256())
1253 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1256 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1257 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1258 MVT VT = (MVT::SimpleValueType)i;
1260 // Do not attempt to promote non-256-bit vectors
1261 if (!VT.is256BitVector())
1264 setOperationAction(ISD::AND, VT, Promote);
1265 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1266 setOperationAction(ISD::OR, VT, Promote);
1267 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1268 setOperationAction(ISD::XOR, VT, Promote);
1269 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1270 setOperationAction(ISD::LOAD, VT, Promote);
1271 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1272 setOperationAction(ISD::SELECT, VT, Promote);
1273 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1277 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1278 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1279 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1280 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1281 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1283 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1284 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1285 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1287 for (MVT VT : MVT::fp_vector_valuetypes())
1288 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1290 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1291 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1292 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1293 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1294 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1295 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1296 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1297 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1298 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1299 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1300 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1301 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1303 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1304 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1305 setOperationAction(ISD::XOR, MVT::i1, Legal);
1306 setOperationAction(ISD::OR, MVT::i1, Legal);
1307 setOperationAction(ISD::AND, MVT::i1, Legal);
1308 setOperationAction(ISD::SUB, MVT::i1, Custom);
1309 setOperationAction(ISD::ADD, MVT::i1, Custom);
1310 setOperationAction(ISD::MUL, MVT::i1, Custom);
1311 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1315 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1317 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1322 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1324 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1329 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1330 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1331 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1333 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1334 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1335 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1336 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1337 if (Subtarget->is64Bit()) {
1338 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1339 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1340 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1341 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1343 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1344 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1345 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1346 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1347 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1348 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1349 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1350 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1351 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1352 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1353 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1354 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1355 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1356 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1357 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1358 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1360 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1361 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1362 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1363 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1364 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1365 if (Subtarget->hasVLX()){
1366 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1367 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1368 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1369 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1370 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1372 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1373 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1374 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1375 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1376 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1378 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1379 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1380 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1381 if (Subtarget->hasDQI()) {
1382 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1383 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1385 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1386 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1387 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1388 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1389 if (Subtarget->hasVLX()) {
1390 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1391 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1392 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1393 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1394 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1395 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1396 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1397 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1400 if (Subtarget->hasVLX()) {
1401 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1402 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1410 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1411 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1412 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1413 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1414 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1415 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1416 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1417 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1418 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1419 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1420 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1421 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1422 if (Subtarget->hasDQI()) {
1423 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1424 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1426 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1427 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1428 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1429 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1430 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1431 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1432 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1433 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1434 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1435 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1443 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1444 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1446 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1448 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1450 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1452 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1454 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1460 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1461 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1462 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1463 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1465 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1466 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1467 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1469 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1470 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1472 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1473 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1475 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1477 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1478 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1480 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1481 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1483 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1484 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1486 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1487 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1488 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1489 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1490 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1491 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1493 if (Subtarget->hasCDI()) {
1494 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1495 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1497 if (Subtarget->hasDQI()) {
1498 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1499 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1500 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1502 // Custom lower several nodes.
1503 for (MVT VT : MVT::vector_valuetypes()) {
1504 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1506 setOperationAction(ISD::AND, VT, Legal);
1507 setOperationAction(ISD::OR, VT, Legal);
1508 setOperationAction(ISD::XOR, VT, Legal);
1510 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1511 setOperationAction(ISD::MGATHER, VT, Custom);
1512 setOperationAction(ISD::MSCATTER, VT, Custom);
1514 // Extract subvector is special because the value type
1515 // (result) is 256/128-bit but the source is 512-bit wide.
1516 if (VT.is128BitVector() || VT.is256BitVector()) {
1517 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1519 if (VT.getVectorElementType() == MVT::i1)
1520 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1522 // Do not attempt to custom lower other non-512-bit vectors
1523 if (!VT.is512BitVector())
1526 if (EltSize >= 32) {
1527 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1528 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1529 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1530 setOperationAction(ISD::VSELECT, VT, Legal);
1531 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1532 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1533 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1534 setOperationAction(ISD::MLOAD, VT, Legal);
1535 setOperationAction(ISD::MSTORE, VT, Legal);
1538 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1539 MVT VT = (MVT::SimpleValueType)i;
1541 // Do not attempt to promote non-512-bit vectors.
1542 if (!VT.is512BitVector())
1545 setOperationAction(ISD::SELECT, VT, Promote);
1546 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1550 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1551 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1552 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1554 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1555 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1557 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1558 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1559 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1560 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1561 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1562 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1563 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1564 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1565 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1566 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1567 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1568 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1569 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1570 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1572 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1573 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1574 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1575 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1576 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1577 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1578 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1579 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1580 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1581 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1582 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1583 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1584 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1585 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1586 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1588 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1589 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1590 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1591 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1592 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1593 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1594 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1595 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1597 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1598 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1599 if (Subtarget->hasVLX())
1600 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1602 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1603 const MVT VT = (MVT::SimpleValueType)i;
1605 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1607 // Do not attempt to promote non-512-bit vectors.
1608 if (!VT.is512BitVector())
1612 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1613 setOperationAction(ISD::VSELECT, VT, Legal);
1618 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1619 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1620 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1622 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1623 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1624 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1625 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1626 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1627 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1628 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1629 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1630 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1631 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1633 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1634 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1635 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1636 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1637 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1638 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1639 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1640 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1642 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1643 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1644 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1645 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1646 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1647 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1648 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1649 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1652 // We want to custom lower some of our intrinsics.
1653 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1654 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1655 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1656 if (!Subtarget->is64Bit())
1657 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1659 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1660 // handle type legalization for these operations here.
1662 // FIXME: We really should do custom legalization for addition and
1663 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1664 // than generic legalization for 64-bit multiplication-with-overflow, though.
1665 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1666 // Add/Sub/Mul with overflow operations are custom lowered.
1668 setOperationAction(ISD::SADDO, VT, Custom);
1669 setOperationAction(ISD::UADDO, VT, Custom);
1670 setOperationAction(ISD::SSUBO, VT, Custom);
1671 setOperationAction(ISD::USUBO, VT, Custom);
1672 setOperationAction(ISD::SMULO, VT, Custom);
1673 setOperationAction(ISD::UMULO, VT, Custom);
1677 if (!Subtarget->is64Bit()) {
1678 // These libcalls are not available in 32-bit.
1679 setLibcallName(RTLIB::SHL_I128, nullptr);
1680 setLibcallName(RTLIB::SRL_I128, nullptr);
1681 setLibcallName(RTLIB::SRA_I128, nullptr);
1684 // Combine sin / cos into one node or libcall if possible.
1685 if (Subtarget->hasSinCos()) {
1686 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1687 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1688 if (Subtarget->isTargetDarwin()) {
1689 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1690 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1691 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1692 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1696 if (Subtarget->isTargetWin64()) {
1697 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1698 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1699 setOperationAction(ISD::SREM, MVT::i128, Custom);
1700 setOperationAction(ISD::UREM, MVT::i128, Custom);
1701 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1702 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1705 // We have target-specific dag combine patterns for the following nodes:
1706 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1707 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1708 setTargetDAGCombine(ISD::BITCAST);
1709 setTargetDAGCombine(ISD::VSELECT);
1710 setTargetDAGCombine(ISD::SELECT);
1711 setTargetDAGCombine(ISD::SHL);
1712 setTargetDAGCombine(ISD::SRA);
1713 setTargetDAGCombine(ISD::SRL);
1714 setTargetDAGCombine(ISD::OR);
1715 setTargetDAGCombine(ISD::AND);
1716 setTargetDAGCombine(ISD::ADD);
1717 setTargetDAGCombine(ISD::FADD);
1718 setTargetDAGCombine(ISD::FSUB);
1719 setTargetDAGCombine(ISD::FMA);
1720 setTargetDAGCombine(ISD::SUB);
1721 setTargetDAGCombine(ISD::LOAD);
1722 setTargetDAGCombine(ISD::MLOAD);
1723 setTargetDAGCombine(ISD::STORE);
1724 setTargetDAGCombine(ISD::MSTORE);
1725 setTargetDAGCombine(ISD::ZERO_EXTEND);
1726 setTargetDAGCombine(ISD::ANY_EXTEND);
1727 setTargetDAGCombine(ISD::SIGN_EXTEND);
1728 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1729 setTargetDAGCombine(ISD::SINT_TO_FP);
1730 setTargetDAGCombine(ISD::UINT_TO_FP);
1731 setTargetDAGCombine(ISD::SETCC);
1732 setTargetDAGCombine(ISD::BUILD_VECTOR);
1733 setTargetDAGCombine(ISD::MUL);
1734 setTargetDAGCombine(ISD::XOR);
1736 computeRegisterProperties(Subtarget->getRegisterInfo());
1738 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1739 MaxStoresPerMemsetOptSize = 8;
1740 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1741 MaxStoresPerMemcpyOptSize = 4;
1742 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1743 MaxStoresPerMemmoveOptSize = 4;
1744 setPrefLoopAlignment(4); // 2^4 bytes.
1746 // Predictable cmov don't hurt on atom because it's in-order.
1747 PredictableSelectIsExpensive = !Subtarget->isAtom();
1748 EnableExtLdPromotion = true;
1749 setPrefFunctionAlignment(4); // 2^4 bytes.
1751 verifyIntrinsicTables();
1754 // This has so far only been implemented for 64-bit MachO.
1755 bool X86TargetLowering::useLoadStackGuardNode() const {
1756 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1759 TargetLoweringBase::LegalizeTypeAction
1760 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1761 if (ExperimentalVectorWideningLegalization &&
1762 VT.getVectorNumElements() != 1 &&
1763 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1764 return TypeWidenVector;
1766 return TargetLoweringBase::getPreferredVectorAction(VT);
1769 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1772 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1774 const unsigned NumElts = VT.getVectorNumElements();
1775 const EVT EltVT = VT.getVectorElementType();
1776 if (VT.is512BitVector()) {
1777 if (Subtarget->hasAVX512())
1778 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1779 EltVT == MVT::f32 || EltVT == MVT::f64)
1781 case 8: return MVT::v8i1;
1782 case 16: return MVT::v16i1;
1784 if (Subtarget->hasBWI())
1785 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1787 case 32: return MVT::v32i1;
1788 case 64: return MVT::v64i1;
1792 if (VT.is256BitVector() || VT.is128BitVector()) {
1793 if (Subtarget->hasVLX())
1794 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1795 EltVT == MVT::f32 || EltVT == MVT::f64)
1797 case 2: return MVT::v2i1;
1798 case 4: return MVT::v4i1;
1799 case 8: return MVT::v8i1;
1801 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1802 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1804 case 8: return MVT::v8i1;
1805 case 16: return MVT::v16i1;
1806 case 32: return MVT::v32i1;
1810 return VT.changeVectorElementTypeToInteger();
1813 /// Helper for getByValTypeAlignment to determine
1814 /// the desired ByVal argument alignment.
1815 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1818 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1819 if (VTy->getBitWidth() == 128)
1821 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1822 unsigned EltAlign = 0;
1823 getMaxByValAlign(ATy->getElementType(), EltAlign);
1824 if (EltAlign > MaxAlign)
1825 MaxAlign = EltAlign;
1826 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1827 for (auto *EltTy : STy->elements()) {
1828 unsigned EltAlign = 0;
1829 getMaxByValAlign(EltTy, EltAlign);
1830 if (EltAlign > MaxAlign)
1831 MaxAlign = EltAlign;
1838 /// Return the desired alignment for ByVal aggregate
1839 /// function arguments in the caller parameter area. For X86, aggregates
1840 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1841 /// are at 4-byte boundaries.
1842 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1843 const DataLayout &DL) const {
1844 if (Subtarget->is64Bit()) {
1845 // Max of 8 and alignment of type.
1846 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1853 if (Subtarget->hasSSE1())
1854 getMaxByValAlign(Ty, Align);
1858 /// Returns the target specific optimal type for load
1859 /// and store operations as a result of memset, memcpy, and memmove
1860 /// lowering. If DstAlign is zero that means it's safe to destination
1861 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1862 /// means there isn't a need to check it against alignment requirement,
1863 /// probably because the source does not need to be loaded. If 'IsMemset' is
1864 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1865 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1866 /// source is constant so it does not need to be loaded.
1867 /// It returns EVT::Other if the type should be determined using generic
1868 /// target-independent logic.
1870 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1871 unsigned DstAlign, unsigned SrcAlign,
1872 bool IsMemset, bool ZeroMemset,
1874 MachineFunction &MF) const {
1875 const Function *F = MF.getFunction();
1876 if ((!IsMemset || ZeroMemset) &&
1877 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1879 (Subtarget->isUnalignedMemAccessFast() ||
1880 ((DstAlign == 0 || DstAlign >= 16) &&
1881 (SrcAlign == 0 || SrcAlign >= 16)))) {
1883 if (Subtarget->hasInt256())
1885 if (Subtarget->hasFp256())
1888 if (Subtarget->hasSSE2())
1890 if (Subtarget->hasSSE1())
1892 } else if (!MemcpyStrSrc && Size >= 8 &&
1893 !Subtarget->is64Bit() &&
1894 Subtarget->hasSSE2()) {
1895 // Do not use f64 to lower memcpy if source is string constant. It's
1896 // better to use i32 to avoid the loads.
1900 if (Subtarget->is64Bit() && Size >= 8)
1905 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1907 return X86ScalarSSEf32;
1908 else if (VT == MVT::f64)
1909 return X86ScalarSSEf64;
1914 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1919 // FIXME: We should be checking 128-bit accesses separately from smaller
1921 if (VT.getSizeInBits() == 256)
1922 *Fast = !Subtarget->isUnalignedMem32Slow();
1924 *Fast = Subtarget->isUnalignedMemAccessFast();
1929 /// Return the entry encoding for a jump table in the
1930 /// current function. The returned value is a member of the
1931 /// MachineJumpTableInfo::JTEntryKind enum.
1932 unsigned X86TargetLowering::getJumpTableEncoding() const {
1933 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1935 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1936 Subtarget->isPICStyleGOT())
1937 return MachineJumpTableInfo::EK_Custom32;
1939 // Otherwise, use the normal jump table encoding heuristics.
1940 return TargetLowering::getJumpTableEncoding();
1943 bool X86TargetLowering::useSoftFloat() const {
1944 return Subtarget->useSoftFloat();
1948 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1949 const MachineBasicBlock *MBB,
1950 unsigned uid,MCContext &Ctx) const{
1951 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1952 Subtarget->isPICStyleGOT());
1953 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1955 return MCSymbolRefExpr::create(MBB->getSymbol(),
1956 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1959 /// Returns relocation base for the given PIC jumptable.
1960 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1961 SelectionDAG &DAG) const {
1962 if (!Subtarget->is64Bit())
1963 // This doesn't have SDLoc associated with it, but is not really the
1964 // same as a Register.
1965 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
1966 getPointerTy(DAG.getDataLayout()));
1970 /// This returns the relocation base for the given PIC jumptable,
1971 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1972 const MCExpr *X86TargetLowering::
1973 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1974 MCContext &Ctx) const {
1975 // X86-64 uses RIP relative addressing based on the jump table label.
1976 if (Subtarget->isPICStyleRIPRel())
1977 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1979 // Otherwise, the reference is relative to the PIC base.
1980 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1983 std::pair<const TargetRegisterClass *, uint8_t>
1984 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1986 const TargetRegisterClass *RRC = nullptr;
1988 switch (VT.SimpleTy) {
1990 return TargetLowering::findRepresentativeClass(TRI, VT);
1991 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1992 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1995 RRC = &X86::VR64RegClass;
1997 case MVT::f32: case MVT::f64:
1998 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1999 case MVT::v4f32: case MVT::v2f64:
2000 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2002 RRC = &X86::VR128RegClass;
2005 return std::make_pair(RRC, Cost);
2008 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2009 unsigned &Offset) const {
2010 if (!Subtarget->isTargetLinux())
2013 if (Subtarget->is64Bit()) {
2014 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2016 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2028 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2029 unsigned DestAS) const {
2030 assert(SrcAS != DestAS && "Expected different address spaces!");
2032 return SrcAS < 256 && DestAS < 256;
2035 //===----------------------------------------------------------------------===//
2036 // Return Value Calling Convention Implementation
2037 //===----------------------------------------------------------------------===//
2039 #include "X86GenCallingConv.inc"
2042 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2043 MachineFunction &MF, bool isVarArg,
2044 const SmallVectorImpl<ISD::OutputArg> &Outs,
2045 LLVMContext &Context) const {
2046 SmallVector<CCValAssign, 16> RVLocs;
2047 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2048 return CCInfo.CheckReturn(Outs, RetCC_X86);
2051 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2052 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2057 X86TargetLowering::LowerReturn(SDValue Chain,
2058 CallingConv::ID CallConv, bool isVarArg,
2059 const SmallVectorImpl<ISD::OutputArg> &Outs,
2060 const SmallVectorImpl<SDValue> &OutVals,
2061 SDLoc dl, SelectionDAG &DAG) const {
2062 MachineFunction &MF = DAG.getMachineFunction();
2063 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2065 SmallVector<CCValAssign, 16> RVLocs;
2066 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2067 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2070 SmallVector<SDValue, 6> RetOps;
2071 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2072 // Operand #1 = Bytes To Pop
2073 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2076 // Copy the result values into the output registers.
2077 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2078 CCValAssign &VA = RVLocs[i];
2079 assert(VA.isRegLoc() && "Can only return in registers!");
2080 SDValue ValToCopy = OutVals[i];
2081 EVT ValVT = ValToCopy.getValueType();
2083 // Promote values to the appropriate types.
2084 if (VA.getLocInfo() == CCValAssign::SExt)
2085 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2086 else if (VA.getLocInfo() == CCValAssign::ZExt)
2087 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2088 else if (VA.getLocInfo() == CCValAssign::AExt) {
2089 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2090 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2092 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2094 else if (VA.getLocInfo() == CCValAssign::BCvt)
2095 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2097 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2098 "Unexpected FP-extend for return value.");
2100 // If this is x86-64, and we disabled SSE, we can't return FP values,
2101 // or SSE or MMX vectors.
2102 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2103 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2104 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2105 report_fatal_error("SSE register return with SSE disabled");
2107 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2108 // llvm-gcc has never done it right and no one has noticed, so this
2109 // should be OK for now.
2110 if (ValVT == MVT::f64 &&
2111 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2112 report_fatal_error("SSE2 register return with SSE2 disabled");
2114 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2115 // the RET instruction and handled by the FP Stackifier.
2116 if (VA.getLocReg() == X86::FP0 ||
2117 VA.getLocReg() == X86::FP1) {
2118 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2119 // change the value to the FP stack register class.
2120 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2121 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2122 RetOps.push_back(ValToCopy);
2123 // Don't emit a copytoreg.
2127 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2128 // which is returned in RAX / RDX.
2129 if (Subtarget->is64Bit()) {
2130 if (ValVT == MVT::x86mmx) {
2131 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2132 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2133 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2135 // If we don't have SSE2 available, convert to v4f32 so the generated
2136 // register is legal.
2137 if (!Subtarget->hasSSE2())
2138 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2143 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2144 Flag = Chain.getValue(1);
2145 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2148 // All x86 ABIs require that for returning structs by value we copy
2149 // the sret argument into %rax/%eax (depending on ABI) for the return.
2150 // We saved the argument into a virtual register in the entry block,
2151 // so now we copy the value out and into %rax/%eax.
2153 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2154 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2155 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2156 // either case FuncInfo->setSRetReturnReg() will have been called.
2157 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2158 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2159 getPointerTy(MF.getDataLayout()));
2162 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2163 X86::RAX : X86::EAX;
2164 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2165 Flag = Chain.getValue(1);
2167 // RAX/EAX now acts like a return value.
2169 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2172 RetOps[0] = Chain; // Update chain.
2174 // Add the flag if we have it.
2176 RetOps.push_back(Flag);
2178 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2181 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2182 if (N->getNumValues() != 1)
2184 if (!N->hasNUsesOfValue(1, 0))
2187 SDValue TCChain = Chain;
2188 SDNode *Copy = *N->use_begin();
2189 if (Copy->getOpcode() == ISD::CopyToReg) {
2190 // If the copy has a glue operand, we conservatively assume it isn't safe to
2191 // perform a tail call.
2192 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2194 TCChain = Copy->getOperand(0);
2195 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2198 bool HasRet = false;
2199 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2201 if (UI->getOpcode() != X86ISD::RET_FLAG)
2203 // If we are returning more than one value, we can definitely
2204 // not make a tail call see PR19530
2205 if (UI->getNumOperands() > 4)
2207 if (UI->getNumOperands() == 4 &&
2208 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2221 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2222 ISD::NodeType ExtendKind) const {
2224 // TODO: Is this also valid on 32-bit?
2225 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2226 ReturnMVT = MVT::i8;
2228 ReturnMVT = MVT::i32;
2230 EVT MinVT = getRegisterType(Context, ReturnMVT);
2231 return VT.bitsLT(MinVT) ? MinVT : VT;
2234 /// Lower the result values of a call into the
2235 /// appropriate copies out of appropriate physical registers.
2238 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2239 CallingConv::ID CallConv, bool isVarArg,
2240 const SmallVectorImpl<ISD::InputArg> &Ins,
2241 SDLoc dl, SelectionDAG &DAG,
2242 SmallVectorImpl<SDValue> &InVals) const {
2244 // Assign locations to each value returned by this call.
2245 SmallVector<CCValAssign, 16> RVLocs;
2246 bool Is64Bit = Subtarget->is64Bit();
2247 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2249 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2251 // Copy all of the result registers out of their specified physreg.
2252 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2253 CCValAssign &VA = RVLocs[i];
2254 EVT CopyVT = VA.getLocVT();
2256 // If this is x86-64, and we disabled SSE, we can't return FP values
2257 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2258 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2259 report_fatal_error("SSE register return with SSE disabled");
2262 // If we prefer to use the value in xmm registers, copy it out as f80 and
2263 // use a truncate to move it from fp stack reg to xmm reg.
2264 bool RoundAfterCopy = false;
2265 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2266 isScalarFPTypeInSSEReg(VA.getValVT())) {
2268 RoundAfterCopy = (CopyVT != VA.getLocVT());
2271 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2272 CopyVT, InFlag).getValue(1);
2273 SDValue Val = Chain.getValue(0);
2276 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2277 // This truncation won't change the value.
2278 DAG.getIntPtrConstant(1, dl));
2280 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2281 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2283 InFlag = Chain.getValue(2);
2284 InVals.push_back(Val);
2290 //===----------------------------------------------------------------------===//
2291 // C & StdCall & Fast Calling Convention implementation
2292 //===----------------------------------------------------------------------===//
2293 // StdCall calling convention seems to be standard for many Windows' API
2294 // routines and around. It differs from C calling convention just a little:
2295 // callee should clean up the stack, not caller. Symbols should be also
2296 // decorated in some fancy way :) It doesn't support any vector arguments.
2297 // For info on fast calling convention see Fast Calling Convention (tail call)
2298 // implementation LowerX86_32FastCCCallTo.
2300 /// CallIsStructReturn - Determines whether a call uses struct return
2302 enum StructReturnType {
2307 static StructReturnType
2308 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2310 return NotStructReturn;
2312 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2313 if (!Flags.isSRet())
2314 return NotStructReturn;
2315 if (Flags.isInReg())
2316 return RegStructReturn;
2317 return StackStructReturn;
2320 /// Determines whether a function uses struct return semantics.
2321 static StructReturnType
2322 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2324 return NotStructReturn;
2326 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2327 if (!Flags.isSRet())
2328 return NotStructReturn;
2329 if (Flags.isInReg())
2330 return RegStructReturn;
2331 return StackStructReturn;
2334 /// Make a copy of an aggregate at address specified by "Src" to address
2335 /// "Dst" with size and alignment information specified by the specific
2336 /// parameter attribute. The copy will be passed as a byval function parameter.
2338 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2339 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2341 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2343 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2344 /*isVolatile*/false, /*AlwaysInline=*/true,
2345 /*isTailCall*/false,
2346 MachinePointerInfo(), MachinePointerInfo());
2349 /// Return true if the calling convention is one that
2350 /// supports tail call optimization.
2351 static bool IsTailCallConvention(CallingConv::ID CC) {
2352 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2353 CC == CallingConv::HiPE);
2356 /// \brief Return true if the calling convention is a C calling convention.
2357 static bool IsCCallConvention(CallingConv::ID CC) {
2358 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2359 CC == CallingConv::X86_64_SysV);
2362 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2364 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2365 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2369 CallingConv::ID CalleeCC = CS.getCallingConv();
2370 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2376 /// Return true if the function is being made into
2377 /// a tailcall target by changing its ABI.
2378 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2379 bool GuaranteedTailCallOpt) {
2380 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2384 X86TargetLowering::LowerMemArgument(SDValue Chain,
2385 CallingConv::ID CallConv,
2386 const SmallVectorImpl<ISD::InputArg> &Ins,
2387 SDLoc dl, SelectionDAG &DAG,
2388 const CCValAssign &VA,
2389 MachineFrameInfo *MFI,
2391 // Create the nodes corresponding to a load from this parameter slot.
2392 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2393 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2394 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2395 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2398 // If value is passed by pointer we have address passed instead of the value
2400 bool ExtendedInMem = VA.isExtInLoc() &&
2401 VA.getValVT().getScalarType() == MVT::i1;
2403 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2404 ValVT = VA.getLocVT();
2406 ValVT = VA.getValVT();
2408 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2409 // changed with more analysis.
2410 // In case of tail call optimization mark all arguments mutable. Since they
2411 // could be overwritten by lowering of arguments in case of a tail call.
2412 if (Flags.isByVal()) {
2413 unsigned Bytes = Flags.getByValSize();
2414 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2415 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2416 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2418 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2419 VA.getLocMemOffset(), isImmutable);
2420 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2421 SDValue Val = DAG.getLoad(
2422 ValVT, dl, Chain, FIN,
2423 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2425 return ExtendedInMem ?
2426 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2430 // FIXME: Get this from tablegen.
2431 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2432 const X86Subtarget *Subtarget) {
2433 assert(Subtarget->is64Bit());
2435 if (Subtarget->isCallingConvWin64(CallConv)) {
2436 static const MCPhysReg GPR64ArgRegsWin64[] = {
2437 X86::RCX, X86::RDX, X86::R8, X86::R9
2439 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2442 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2443 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2445 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2448 // FIXME: Get this from tablegen.
2449 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2450 CallingConv::ID CallConv,
2451 const X86Subtarget *Subtarget) {
2452 assert(Subtarget->is64Bit());
2453 if (Subtarget->isCallingConvWin64(CallConv)) {
2454 // The XMM registers which might contain var arg parameters are shadowed
2455 // in their paired GPR. So we only need to save the GPR to their home
2457 // TODO: __vectorcall will change this.
2461 const Function *Fn = MF.getFunction();
2462 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2463 bool isSoftFloat = Subtarget->useSoftFloat();
2464 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2465 "SSE register cannot be used when SSE is disabled!");
2466 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2467 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2471 static const MCPhysReg XMMArgRegs64Bit[] = {
2472 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2473 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2475 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2479 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2480 CallingConv::ID CallConv,
2482 const SmallVectorImpl<ISD::InputArg> &Ins,
2485 SmallVectorImpl<SDValue> &InVals)
2487 MachineFunction &MF = DAG.getMachineFunction();
2488 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2489 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2491 const Function* Fn = MF.getFunction();
2492 if (Fn->hasExternalLinkage() &&
2493 Subtarget->isTargetCygMing() &&
2494 Fn->getName() == "main")
2495 FuncInfo->setForceFramePointer(true);
2497 MachineFrameInfo *MFI = MF.getFrameInfo();
2498 bool Is64Bit = Subtarget->is64Bit();
2499 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2501 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2502 "Var args not supported with calling convention fastcc, ghc or hipe");
2504 // Assign locations to all of the incoming arguments.
2505 SmallVector<CCValAssign, 16> ArgLocs;
2506 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2508 // Allocate shadow area for Win64
2510 CCInfo.AllocateStack(32, 8);
2512 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2514 unsigned LastVal = ~0U;
2516 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2517 CCValAssign &VA = ArgLocs[i];
2518 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2520 assert(VA.getValNo() != LastVal &&
2521 "Don't support value assigned to multiple locs yet");
2523 LastVal = VA.getValNo();
2525 if (VA.isRegLoc()) {
2526 EVT RegVT = VA.getLocVT();
2527 const TargetRegisterClass *RC;
2528 if (RegVT == MVT::i32)
2529 RC = &X86::GR32RegClass;
2530 else if (Is64Bit && RegVT == MVT::i64)
2531 RC = &X86::GR64RegClass;
2532 else if (RegVT == MVT::f32)
2533 RC = &X86::FR32RegClass;
2534 else if (RegVT == MVT::f64)
2535 RC = &X86::FR64RegClass;
2536 else if (RegVT.is512BitVector())
2537 RC = &X86::VR512RegClass;
2538 else if (RegVT.is256BitVector())
2539 RC = &X86::VR256RegClass;
2540 else if (RegVT.is128BitVector())
2541 RC = &X86::VR128RegClass;
2542 else if (RegVT == MVT::x86mmx)
2543 RC = &X86::VR64RegClass;
2544 else if (RegVT == MVT::i1)
2545 RC = &X86::VK1RegClass;
2546 else if (RegVT == MVT::v8i1)
2547 RC = &X86::VK8RegClass;
2548 else if (RegVT == MVT::v16i1)
2549 RC = &X86::VK16RegClass;
2550 else if (RegVT == MVT::v32i1)
2551 RC = &X86::VK32RegClass;
2552 else if (RegVT == MVT::v64i1)
2553 RC = &X86::VK64RegClass;
2555 llvm_unreachable("Unknown argument type!");
2557 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2558 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2560 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2561 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2563 if (VA.getLocInfo() == CCValAssign::SExt)
2564 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2565 DAG.getValueType(VA.getValVT()));
2566 else if (VA.getLocInfo() == CCValAssign::ZExt)
2567 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2568 DAG.getValueType(VA.getValVT()));
2569 else if (VA.getLocInfo() == CCValAssign::BCvt)
2570 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2572 if (VA.isExtInLoc()) {
2573 // Handle MMX values passed in XMM regs.
2574 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2575 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2577 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2580 assert(VA.isMemLoc());
2581 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2584 // If value is passed via pointer - do a load.
2585 if (VA.getLocInfo() == CCValAssign::Indirect)
2586 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2587 MachinePointerInfo(), false, false, false, 0);
2589 InVals.push_back(ArgValue);
2592 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2593 // All x86 ABIs require that for returning structs by value we copy the
2594 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2595 // the argument into a virtual register so that we can access it from the
2597 if (Ins[i].Flags.isSRet()) {
2598 unsigned Reg = FuncInfo->getSRetReturnReg();
2600 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2601 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2602 FuncInfo->setSRetReturnReg(Reg);
2604 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2605 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2610 unsigned StackSize = CCInfo.getNextStackOffset();
2611 // Align stack specially for tail calls.
2612 if (FuncIsMadeTailCallSafe(CallConv,
2613 MF.getTarget().Options.GuaranteedTailCallOpt))
2614 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2616 // If the function takes variable number of arguments, make a frame index for
2617 // the start of the first vararg value... for expansion of llvm.va_start. We
2618 // can skip this if there are no va_start calls.
2619 if (MFI->hasVAStart() &&
2620 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2621 CallConv != CallingConv::X86_ThisCall))) {
2622 FuncInfo->setVarArgsFrameIndex(
2623 MFI->CreateFixedObject(1, StackSize, true));
2626 MachineModuleInfo &MMI = MF.getMMI();
2627 const Function *WinEHParent = nullptr;
2628 if (MMI.hasWinEHFuncInfo(Fn))
2629 WinEHParent = MMI.getWinEHParent(Fn);
2630 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2631 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2633 // Figure out if XMM registers are in use.
2634 assert(!(Subtarget->useSoftFloat() &&
2635 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2636 "SSE register cannot be used when SSE is disabled!");
2638 // 64-bit calling conventions support varargs and register parameters, so we
2639 // have to do extra work to spill them in the prologue.
2640 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2641 // Find the first unallocated argument registers.
2642 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2643 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2644 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2645 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2646 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2647 "SSE register cannot be used when SSE is disabled!");
2649 // Gather all the live in physical registers.
2650 SmallVector<SDValue, 6> LiveGPRs;
2651 SmallVector<SDValue, 8> LiveXMMRegs;
2653 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2654 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2656 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2658 if (!ArgXMMs.empty()) {
2659 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2660 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2661 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2662 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2663 LiveXMMRegs.push_back(
2664 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2669 // Get to the caller-allocated home save location. Add 8 to account
2670 // for the return address.
2671 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2672 FuncInfo->setRegSaveFrameIndex(
2673 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2674 // Fixup to set vararg frame on shadow area (4 x i64).
2676 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2678 // For X86-64, if there are vararg parameters that are passed via
2679 // registers, then we must store them to their spots on the stack so
2680 // they may be loaded by deferencing the result of va_next.
2681 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2682 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2683 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2684 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2687 // Store the integer parameter registers.
2688 SmallVector<SDValue, 8> MemOps;
2689 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2690 getPointerTy(DAG.getDataLayout()));
2691 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2692 for (SDValue Val : LiveGPRs) {
2693 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2694 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2696 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2697 MachinePointerInfo::getFixedStack(
2698 DAG.getMachineFunction(),
2699 FuncInfo->getRegSaveFrameIndex(), Offset),
2701 MemOps.push_back(Store);
2705 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2706 // Now store the XMM (fp + vector) parameter registers.
2707 SmallVector<SDValue, 12> SaveXMMOps;
2708 SaveXMMOps.push_back(Chain);
2709 SaveXMMOps.push_back(ALVal);
2710 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2711 FuncInfo->getRegSaveFrameIndex(), dl));
2712 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2713 FuncInfo->getVarArgsFPOffset(), dl));
2714 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2716 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2717 MVT::Other, SaveXMMOps));
2720 if (!MemOps.empty())
2721 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2722 } else if (IsWin64 && IsWinEHOutlined) {
2723 // Get to the caller-allocated home save location. Add 8 to account
2724 // for the return address.
2725 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2726 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2727 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2729 MMI.getWinEHFuncInfo(Fn)
2730 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2731 FuncInfo->getRegSaveFrameIndex();
2733 // Store the second integer parameter (rdx) into rsp+16 relative to the
2734 // stack pointer at the entry of the function.
2735 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2736 getPointerTy(DAG.getDataLayout()));
2737 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2738 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2739 Chain = DAG.getStore(
2740 Val.getValue(1), dl, Val, RSFIN,
2741 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(),
2742 FuncInfo->getRegSaveFrameIndex()),
2743 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2746 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2747 // Find the largest legal vector type.
2748 MVT VecVT = MVT::Other;
2749 // FIXME: Only some x86_32 calling conventions support AVX512.
2750 if (Subtarget->hasAVX512() &&
2751 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2752 CallConv == CallingConv::Intel_OCL_BI)))
2753 VecVT = MVT::v16f32;
2754 else if (Subtarget->hasAVX())
2756 else if (Subtarget->hasSSE2())
2759 // We forward some GPRs and some vector types.
2760 SmallVector<MVT, 2> RegParmTypes;
2761 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2762 RegParmTypes.push_back(IntVT);
2763 if (VecVT != MVT::Other)
2764 RegParmTypes.push_back(VecVT);
2766 // Compute the set of forwarded registers. The rest are scratch.
2767 SmallVectorImpl<ForwardedRegister> &Forwards =
2768 FuncInfo->getForwardedMustTailRegParms();
2769 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2771 // Conservatively forward AL on x86_64, since it might be used for varargs.
2772 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2773 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2774 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2777 // Copy all forwards from physical to virtual registers.
2778 for (ForwardedRegister &F : Forwards) {
2779 // FIXME: Can we use a less constrained schedule?
2780 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2781 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2782 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2786 // Some CCs need callee pop.
2787 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2788 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2789 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2791 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2792 // If this is an sret function, the return should pop the hidden pointer.
2793 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2794 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2795 argsAreStructReturn(Ins) == StackStructReturn)
2796 FuncInfo->setBytesToPopOnReturn(4);
2800 // RegSaveFrameIndex is X86-64 only.
2801 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2802 if (CallConv == CallingConv::X86_FastCall ||
2803 CallConv == CallingConv::X86_ThisCall)
2804 // fastcc functions can't have varargs.
2805 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2808 FuncInfo->setArgumentStackSize(StackSize);
2810 if (IsWinEHParent) {
2812 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2813 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2814 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2815 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2816 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2817 MachinePointerInfo::getFixedStack(
2818 DAG.getMachineFunction(), UnwindHelpFI),
2819 /*isVolatile=*/true,
2820 /*isNonTemporal=*/false, /*Alignment=*/0);
2822 // Functions using Win32 EH are considered to have opaque SP adjustments
2823 // to force local variables to be addressed from the frame or base
2825 MFI->setHasOpaqueSPAdjustment(true);
2833 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2834 SDValue StackPtr, SDValue Arg,
2835 SDLoc dl, SelectionDAG &DAG,
2836 const CCValAssign &VA,
2837 ISD::ArgFlagsTy Flags) const {
2838 unsigned LocMemOffset = VA.getLocMemOffset();
2839 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2840 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2842 if (Flags.isByVal())
2843 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2845 return DAG.getStore(
2846 Chain, dl, Arg, PtrOff,
2847 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2851 /// Emit a load of return address if tail call
2852 /// optimization is performed and it is required.
2854 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2855 SDValue &OutRetAddr, SDValue Chain,
2856 bool IsTailCall, bool Is64Bit,
2857 int FPDiff, SDLoc dl) const {
2858 // Adjust the Return address stack slot.
2859 EVT VT = getPointerTy(DAG.getDataLayout());
2860 OutRetAddr = getReturnAddressFrameIndex(DAG);
2862 // Load the "old" Return address.
2863 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2864 false, false, false, 0);
2865 return SDValue(OutRetAddr.getNode(), 1);
2868 /// Emit a store of the return address if tail call
2869 /// optimization is performed and it is required (FPDiff!=0).
2870 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2871 SDValue Chain, SDValue RetAddrFrIdx,
2872 EVT PtrVT, unsigned SlotSize,
2873 int FPDiff, SDLoc dl) {
2874 // Store the return address to the appropriate stack slot.
2875 if (!FPDiff) return Chain;
2876 // Calculate the new stack slot for the return address.
2877 int NewReturnAddrFI =
2878 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2880 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2881 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2882 MachinePointerInfo::getFixedStack(
2883 DAG.getMachineFunction(), NewReturnAddrFI),
2888 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2889 /// operation of specified width.
2890 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2892 unsigned NumElems = VT.getVectorNumElements();
2893 SmallVector<int, 8> Mask;
2894 Mask.push_back(NumElems);
2895 for (unsigned i = 1; i != NumElems; ++i)
2897 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2901 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2902 SmallVectorImpl<SDValue> &InVals) const {
2903 SelectionDAG &DAG = CLI.DAG;
2905 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2906 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2907 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2908 SDValue Chain = CLI.Chain;
2909 SDValue Callee = CLI.Callee;
2910 CallingConv::ID CallConv = CLI.CallConv;
2911 bool &isTailCall = CLI.IsTailCall;
2912 bool isVarArg = CLI.IsVarArg;
2914 MachineFunction &MF = DAG.getMachineFunction();
2915 bool Is64Bit = Subtarget->is64Bit();
2916 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2917 StructReturnType SR = callIsStructReturn(Outs);
2918 bool IsSibcall = false;
2919 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2920 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2922 if (Attr.getValueAsString() == "true")
2925 if (Subtarget->isPICStyleGOT() &&
2926 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2927 // If we are using a GOT, disable tail calls to external symbols with
2928 // default visibility. Tail calling such a symbol requires using a GOT
2929 // relocation, which forces early binding of the symbol. This breaks code
2930 // that require lazy function symbol resolution. Using musttail or
2931 // GuaranteedTailCallOpt will override this.
2932 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2933 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2934 G->getGlobal()->hasDefaultVisibility()))
2938 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2940 // Force this to be a tail call. The verifier rules are enough to ensure
2941 // that we can lower this successfully without moving the return address
2944 } else if (isTailCall) {
2945 // Check if it's really possible to do a tail call.
2946 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2947 isVarArg, SR != NotStructReturn,
2948 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2949 Outs, OutVals, Ins, DAG);
2951 // Sibcalls are automatically detected tailcalls which do not require
2953 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2960 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2961 "Var args not supported with calling convention fastcc, ghc or hipe");
2963 // Analyze operands of the call, assigning locations to each operand.
2964 SmallVector<CCValAssign, 16> ArgLocs;
2965 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2967 // Allocate shadow area for Win64
2969 CCInfo.AllocateStack(32, 8);
2971 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2973 // Get a count of how many bytes are to be pushed on the stack.
2974 unsigned NumBytes = CCInfo.getNextStackOffset();
2976 // This is a sibcall. The memory operands are available in caller's
2977 // own caller's stack.
2979 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2980 IsTailCallConvention(CallConv))
2981 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2984 if (isTailCall && !IsSibcall && !IsMustTail) {
2985 // Lower arguments at fp - stackoffset + fpdiff.
2986 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2988 FPDiff = NumBytesCallerPushed - NumBytes;
2990 // Set the delta of movement of the returnaddr stackslot.
2991 // But only set if delta is greater than previous delta.
2992 if (FPDiff < X86Info->getTCReturnAddrDelta())
2993 X86Info->setTCReturnAddrDelta(FPDiff);
2996 unsigned NumBytesToPush = NumBytes;
2997 unsigned NumBytesToPop = NumBytes;
2999 // If we have an inalloca argument, all stack space has already been allocated
3000 // for us and be right at the top of the stack. We don't support multiple
3001 // arguments passed in memory when using inalloca.
3002 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3004 if (!ArgLocs.back().isMemLoc())
3005 report_fatal_error("cannot use inalloca attribute on a register "
3007 if (ArgLocs.back().getLocMemOffset() != 0)
3008 report_fatal_error("any parameter with the inalloca attribute must be "
3009 "the only memory argument");
3013 Chain = DAG.getCALLSEQ_START(
3014 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3016 SDValue RetAddrFrIdx;
3017 // Load return address for tail calls.
3018 if (isTailCall && FPDiff)
3019 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3020 Is64Bit, FPDiff, dl);
3022 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3023 SmallVector<SDValue, 8> MemOpChains;
3026 // Walk the register/memloc assignments, inserting copies/loads. In the case
3027 // of tail call optimization arguments are handle later.
3028 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3029 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3030 // Skip inalloca arguments, they have already been written.
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 if (Flags.isInAlloca())
3035 CCValAssign &VA = ArgLocs[i];
3036 EVT RegVT = VA.getLocVT();
3037 SDValue Arg = OutVals[i];
3038 bool isByVal = Flags.isByVal();
3040 // Promote the value if needed.
3041 switch (VA.getLocInfo()) {
3042 default: llvm_unreachable("Unknown loc info!");
3043 case CCValAssign::Full: break;
3044 case CCValAssign::SExt:
3045 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3047 case CCValAssign::ZExt:
3048 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3050 case CCValAssign::AExt:
3051 if (Arg.getValueType().isVector() &&
3052 Arg.getValueType().getScalarType() == MVT::i1)
3053 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3054 else if (RegVT.is128BitVector()) {
3055 // Special case: passing MMX values in XMM registers.
3056 Arg = DAG.getBitcast(MVT::i64, Arg);
3057 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3058 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3060 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3062 case CCValAssign::BCvt:
3063 Arg = DAG.getBitcast(RegVT, Arg);
3065 case CCValAssign::Indirect: {
3066 // Store the argument.
3067 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3068 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3069 Chain = DAG.getStore(
3070 Chain, dl, Arg, SpillSlot,
3071 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3078 if (VA.isRegLoc()) {
3079 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3080 if (isVarArg && IsWin64) {
3081 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3082 // shadow reg if callee is a varargs function.
3083 unsigned ShadowReg = 0;
3084 switch (VA.getLocReg()) {
3085 case X86::XMM0: ShadowReg = X86::RCX; break;
3086 case X86::XMM1: ShadowReg = X86::RDX; break;
3087 case X86::XMM2: ShadowReg = X86::R8; break;
3088 case X86::XMM3: ShadowReg = X86::R9; break;
3091 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3093 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3094 assert(VA.isMemLoc());
3095 if (!StackPtr.getNode())
3096 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3097 getPointerTy(DAG.getDataLayout()));
3098 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3099 dl, DAG, VA, Flags));
3103 if (!MemOpChains.empty())
3104 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3106 if (Subtarget->isPICStyleGOT()) {
3107 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3110 RegsToPass.push_back(std::make_pair(
3111 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3112 getPointerTy(DAG.getDataLayout()))));
3114 // If we are tail calling and generating PIC/GOT style code load the
3115 // address of the callee into ECX. The value in ecx is used as target of
3116 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3117 // for tail calls on PIC/GOT architectures. Normally we would just put the
3118 // address of GOT into ebx and then call target@PLT. But for tail calls
3119 // ebx would be restored (since ebx is callee saved) before jumping to the
3122 // Note: The actual moving to ECX is done further down.
3123 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3124 if (G && !G->getGlobal()->hasLocalLinkage() &&
3125 G->getGlobal()->hasDefaultVisibility())
3126 Callee = LowerGlobalAddress(Callee, DAG);
3127 else if (isa<ExternalSymbolSDNode>(Callee))
3128 Callee = LowerExternalSymbol(Callee, DAG);
3132 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3133 // From AMD64 ABI document:
3134 // For calls that may call functions that use varargs or stdargs
3135 // (prototype-less calls or calls to functions containing ellipsis (...) in
3136 // the declaration) %al is used as hidden argument to specify the number
3137 // of SSE registers used. The contents of %al do not need to match exactly
3138 // the number of registers, but must be an ubound on the number of SSE
3139 // registers used and is in the range 0 - 8 inclusive.
3141 // Count the number of XMM registers allocated.
3142 static const MCPhysReg XMMArgRegs[] = {
3143 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3144 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3146 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3147 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3148 && "SSE registers cannot be used when SSE is disabled");
3150 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3151 DAG.getConstant(NumXMMRegs, dl,
3155 if (isVarArg && IsMustTail) {
3156 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3157 for (const auto &F : Forwards) {
3158 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3159 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3163 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3164 // don't need this because the eligibility check rejects calls that require
3165 // shuffling arguments passed in memory.
3166 if (!IsSibcall && isTailCall) {
3167 // Force all the incoming stack arguments to be loaded from the stack
3168 // before any new outgoing arguments are stored to the stack, because the
3169 // outgoing stack slots may alias the incoming argument stack slots, and
3170 // the alias isn't otherwise explicit. This is slightly more conservative
3171 // than necessary, because it means that each store effectively depends
3172 // on every argument instead of just those arguments it would clobber.
3173 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3175 SmallVector<SDValue, 8> MemOpChains2;
3178 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3179 CCValAssign &VA = ArgLocs[i];
3182 assert(VA.isMemLoc());
3183 SDValue Arg = OutVals[i];
3184 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3185 // Skip inalloca arguments. They don't require any work.
3186 if (Flags.isInAlloca())
3188 // Create frame index.
3189 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3190 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3191 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3192 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3194 if (Flags.isByVal()) {
3195 // Copy relative to framepointer.
3196 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3197 if (!StackPtr.getNode())
3198 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3199 getPointerTy(DAG.getDataLayout()));
3200 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3203 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3207 // Store relative to framepointer.
3208 MemOpChains2.push_back(DAG.getStore(
3209 ArgChain, dl, Arg, FIN,
3210 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3215 if (!MemOpChains2.empty())
3216 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3218 // Store the return address to the appropriate stack slot.
3219 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3220 getPointerTy(DAG.getDataLayout()),
3221 RegInfo->getSlotSize(), FPDiff, dl);
3224 // Build a sequence of copy-to-reg nodes chained together with token chain
3225 // and flag operands which copy the outgoing args into registers.
3227 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3228 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3229 RegsToPass[i].second, InFlag);
3230 InFlag = Chain.getValue(1);
3233 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3234 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3235 // In the 64-bit large code model, we have to make all calls
3236 // through a register, since the call instruction's 32-bit
3237 // pc-relative offset may not be large enough to hold the whole
3239 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3240 // If the callee is a GlobalAddress node (quite common, every direct call
3241 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3243 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3245 // We should use extra load for direct calls to dllimported functions in
3247 const GlobalValue *GV = G->getGlobal();
3248 if (!GV->hasDLLImportStorageClass()) {
3249 unsigned char OpFlags = 0;
3250 bool ExtraLoad = false;
3251 unsigned WrapperKind = ISD::DELETED_NODE;
3253 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3254 // external symbols most go through the PLT in PIC mode. If the symbol
3255 // has hidden or protected visibility, or if it is static or local, then
3256 // we don't need to use the PLT - we can directly call it.
3257 if (Subtarget->isTargetELF() &&
3258 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3259 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3260 OpFlags = X86II::MO_PLT;
3261 } else if (Subtarget->isPICStyleStubAny() &&
3262 !GV->isStrongDefinitionForLinker() &&
3263 (!Subtarget->getTargetTriple().isMacOSX() ||
3264 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3265 // PC-relative references to external symbols should go through $stub,
3266 // unless we're building with the leopard linker or later, which
3267 // automatically synthesizes these stubs.
3268 OpFlags = X86II::MO_DARWIN_STUB;
3269 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3270 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3271 // If the function is marked as non-lazy, generate an indirect call
3272 // which loads from the GOT directly. This avoids runtime overhead
3273 // at the cost of eager binding (and one extra byte of encoding).
3274 OpFlags = X86II::MO_GOTPCREL;
3275 WrapperKind = X86ISD::WrapperRIP;
3279 Callee = DAG.getTargetGlobalAddress(
3280 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3282 // Add a wrapper if needed.
3283 if (WrapperKind != ISD::DELETED_NODE)
3284 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3285 getPointerTy(DAG.getDataLayout()), Callee);
3286 // Add extra indirection if needed.
3288 Callee = DAG.getLoad(
3289 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3290 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3293 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3294 unsigned char OpFlags = 0;
3296 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3297 // external symbols should go through the PLT.
3298 if (Subtarget->isTargetELF() &&
3299 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3300 OpFlags = X86II::MO_PLT;
3301 } else if (Subtarget->isPICStyleStubAny() &&
3302 (!Subtarget->getTargetTriple().isMacOSX() ||
3303 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3304 // PC-relative references to external symbols should go through $stub,
3305 // unless we're building with the leopard linker or later, which
3306 // automatically synthesizes these stubs.
3307 OpFlags = X86II::MO_DARWIN_STUB;
3310 Callee = DAG.getTargetExternalSymbol(
3311 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3312 } else if (Subtarget->isTarget64BitILP32() &&
3313 Callee->getValueType(0) == MVT::i32) {
3314 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3315 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3318 // Returns a chain & a flag for retval copy to use.
3319 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3320 SmallVector<SDValue, 8> Ops;
3322 if (!IsSibcall && isTailCall) {
3323 Chain = DAG.getCALLSEQ_END(Chain,
3324 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3325 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3326 InFlag = Chain.getValue(1);
3329 Ops.push_back(Chain);
3330 Ops.push_back(Callee);
3333 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3335 // Add argument registers to the end of the list so that they are known live
3337 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3338 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3339 RegsToPass[i].second.getValueType()));
3341 // Add a register mask operand representing the call-preserved registers.
3342 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3343 assert(Mask && "Missing call preserved mask for calling convention");
3345 // If this is an invoke in a 32-bit function using an MSVC personality, assume
3346 // the function clobbers all registers. If an exception is thrown, the runtime
3347 // will not restore CSRs.
3348 // FIXME: Model this more precisely so that we can register allocate across
3349 // the normal edge and spill and fill across the exceptional edge.
3350 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3351 const Function *CallerFn = MF.getFunction();
3352 EHPersonality Pers =
3353 CallerFn->hasPersonalityFn()
3354 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3355 : EHPersonality::Unknown;
3356 if (isMSVCEHPersonality(Pers))
3357 Mask = RegInfo->getNoPreservedMask();
3360 Ops.push_back(DAG.getRegisterMask(Mask));
3362 if (InFlag.getNode())
3363 Ops.push_back(InFlag);
3367 //// If this is the first return lowered for this function, add the regs
3368 //// to the liveout set for the function.
3369 // This isn't right, although it's probably harmless on x86; liveouts
3370 // should be computed from returns not tail calls. Consider a void
3371 // function making a tail call to a function returning int.
3372 MF.getFrameInfo()->setHasTailCall();
3373 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3376 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3377 InFlag = Chain.getValue(1);
3379 // Create the CALLSEQ_END node.
3380 unsigned NumBytesForCalleeToPop;
3381 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3382 DAG.getTarget().Options.GuaranteedTailCallOpt))
3383 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3384 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3385 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3386 SR == StackStructReturn)
3387 // If this is a call to a struct-return function, the callee
3388 // pops the hidden struct pointer, so we have to push it back.
3389 // This is common for Darwin/X86, Linux & Mingw32 targets.
3390 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3391 NumBytesForCalleeToPop = 4;
3393 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3395 // Returns a flag for retval copy to use.
3397 Chain = DAG.getCALLSEQ_END(Chain,
3398 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3399 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3402 InFlag = Chain.getValue(1);
3405 // Handle result values, copying them out of physregs into vregs that we
3407 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3408 Ins, dl, DAG, InVals);
3411 //===----------------------------------------------------------------------===//
3412 // Fast Calling Convention (tail call) implementation
3413 //===----------------------------------------------------------------------===//
3415 // Like std call, callee cleans arguments, convention except that ECX is
3416 // reserved for storing the tail called function address. Only 2 registers are
3417 // free for argument passing (inreg). Tail call optimization is performed
3419 // * tailcallopt is enabled
3420 // * caller/callee are fastcc
3421 // On X86_64 architecture with GOT-style position independent code only local
3422 // (within module) calls are supported at the moment.
3423 // To keep the stack aligned according to platform abi the function
3424 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3425 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3426 // If a tail called function callee has more arguments than the caller the
3427 // caller needs to make sure that there is room to move the RETADDR to. This is
3428 // achieved by reserving an area the size of the argument delta right after the
3429 // original RETADDR, but before the saved framepointer or the spilled registers
3430 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3442 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3445 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3446 SelectionDAG& DAG) const {
3447 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3448 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3449 unsigned StackAlignment = TFI.getStackAlignment();
3450 uint64_t AlignMask = StackAlignment - 1;
3451 int64_t Offset = StackSize;
3452 unsigned SlotSize = RegInfo->getSlotSize();
3453 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3454 // Number smaller than 12 so just add the difference.
3455 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3457 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3458 Offset = ((~AlignMask) & Offset) + StackAlignment +
3459 (StackAlignment-SlotSize);
3464 /// Return true if the given stack call argument is already available in the
3465 /// same position (relatively) of the caller's incoming argument stack.
3467 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3468 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3469 const X86InstrInfo *TII) {
3470 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3472 if (Arg.getOpcode() == ISD::CopyFromReg) {
3473 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3474 if (!TargetRegisterInfo::isVirtualRegister(VR))
3476 MachineInstr *Def = MRI->getVRegDef(VR);
3479 if (!Flags.isByVal()) {
3480 if (!TII->isLoadFromStackSlot(Def, FI))
3483 unsigned Opcode = Def->getOpcode();
3484 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3485 Opcode == X86::LEA64_32r) &&
3486 Def->getOperand(1).isFI()) {
3487 FI = Def->getOperand(1).getIndex();
3488 Bytes = Flags.getByValSize();
3492 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3493 if (Flags.isByVal())
3494 // ByVal argument is passed in as a pointer but it's now being
3495 // dereferenced. e.g.
3496 // define @foo(%struct.X* %A) {
3497 // tail call @bar(%struct.X* byval %A)
3500 SDValue Ptr = Ld->getBasePtr();
3501 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3504 FI = FINode->getIndex();
3505 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3506 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3507 FI = FINode->getIndex();
3508 Bytes = Flags.getByValSize();
3512 assert(FI != INT_MAX);
3513 if (!MFI->isFixedObjectIndex(FI))
3515 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3518 /// Check whether the call is eligible for tail call optimization. Targets
3519 /// that want to do tail call optimization should implement this function.
3521 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3522 CallingConv::ID CalleeCC,
3524 bool isCalleeStructRet,
3525 bool isCallerStructRet,
3527 const SmallVectorImpl<ISD::OutputArg> &Outs,
3528 const SmallVectorImpl<SDValue> &OutVals,
3529 const SmallVectorImpl<ISD::InputArg> &Ins,
3530 SelectionDAG &DAG) const {
3531 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3534 // If -tailcallopt is specified, make fastcc functions tail-callable.
3535 const MachineFunction &MF = DAG.getMachineFunction();
3536 const Function *CallerF = MF.getFunction();
3538 // If the function return type is x86_fp80 and the callee return type is not,
3539 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3540 // perform a tailcall optimization here.
3541 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3544 CallingConv::ID CallerCC = CallerF->getCallingConv();
3545 bool CCMatch = CallerCC == CalleeCC;
3546 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3547 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3549 // Win64 functions have extra shadow space for argument homing. Don't do the
3550 // sibcall if the caller and callee have mismatched expectations for this
3552 if (IsCalleeWin64 != IsCallerWin64)
3555 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3556 if (IsTailCallConvention(CalleeCC) && CCMatch)
3561 // Look for obvious safe cases to perform tail call optimization that do not
3562 // require ABI changes. This is what gcc calls sibcall.
3564 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3565 // emit a special epilogue.
3566 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3567 if (RegInfo->needsStackRealignment(MF))
3570 // Also avoid sibcall optimization if either caller or callee uses struct
3571 // return semantics.
3572 if (isCalleeStructRet || isCallerStructRet)
3575 // An stdcall/thiscall caller is expected to clean up its arguments; the
3576 // callee isn't going to do that.
3577 // FIXME: this is more restrictive than needed. We could produce a tailcall
3578 // when the stack adjustment matches. For example, with a thiscall that takes
3579 // only one argument.
3580 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3581 CallerCC == CallingConv::X86_ThisCall))
3584 // Do not sibcall optimize vararg calls unless all arguments are passed via
3586 if (isVarArg && !Outs.empty()) {
3588 // Optimizing for varargs on Win64 is unlikely to be safe without
3589 // additional testing.
3590 if (IsCalleeWin64 || IsCallerWin64)
3593 SmallVector<CCValAssign, 16> ArgLocs;
3594 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3597 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3598 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3599 if (!ArgLocs[i].isRegLoc())
3603 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3604 // stack. Therefore, if it's not used by the call it is not safe to optimize
3605 // this into a sibcall.
3606 bool Unused = false;
3607 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3614 SmallVector<CCValAssign, 16> RVLocs;
3615 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3617 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3618 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3619 CCValAssign &VA = RVLocs[i];
3620 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3625 // If the calling conventions do not match, then we'd better make sure the
3626 // results are returned in the same way as what the caller expects.
3628 SmallVector<CCValAssign, 16> RVLocs1;
3629 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3631 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3633 SmallVector<CCValAssign, 16> RVLocs2;
3634 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3636 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3638 if (RVLocs1.size() != RVLocs2.size())
3640 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3641 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3643 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3645 if (RVLocs1[i].isRegLoc()) {
3646 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3649 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3655 // If the callee takes no arguments then go on to check the results of the
3657 if (!Outs.empty()) {
3658 // Check if stack adjustment is needed. For now, do not do this if any
3659 // argument is passed on the stack.
3660 SmallVector<CCValAssign, 16> ArgLocs;
3661 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3664 // Allocate shadow area for Win64
3666 CCInfo.AllocateStack(32, 8);
3668 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3669 if (CCInfo.getNextStackOffset()) {
3670 MachineFunction &MF = DAG.getMachineFunction();
3671 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3674 // Check if the arguments are already laid out in the right way as
3675 // the caller's fixed stack objects.
3676 MachineFrameInfo *MFI = MF.getFrameInfo();
3677 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3678 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3679 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3680 CCValAssign &VA = ArgLocs[i];
3681 SDValue Arg = OutVals[i];
3682 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3683 if (VA.getLocInfo() == CCValAssign::Indirect)
3685 if (!VA.isRegLoc()) {
3686 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3693 // If the tailcall address may be in a register, then make sure it's
3694 // possible to register allocate for it. In 32-bit, the call address can
3695 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3696 // callee-saved registers are restored. These happen to be the same
3697 // registers used to pass 'inreg' arguments so watch out for those.
3698 if (!Subtarget->is64Bit() &&
3699 ((!isa<GlobalAddressSDNode>(Callee) &&
3700 !isa<ExternalSymbolSDNode>(Callee)) ||
3701 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3702 unsigned NumInRegs = 0;
3703 // In PIC we need an extra register to formulate the address computation
3705 unsigned MaxInRegs =
3706 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3708 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3709 CCValAssign &VA = ArgLocs[i];
3712 unsigned Reg = VA.getLocReg();
3715 case X86::EAX: case X86::EDX: case X86::ECX:
3716 if (++NumInRegs == MaxInRegs)
3728 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3729 const TargetLibraryInfo *libInfo) const {
3730 return X86::createFastISel(funcInfo, libInfo);
3733 //===----------------------------------------------------------------------===//
3734 // Other Lowering Hooks
3735 //===----------------------------------------------------------------------===//
3737 static bool MayFoldLoad(SDValue Op) {
3738 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3741 static bool MayFoldIntoStore(SDValue Op) {
3742 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3745 static bool isTargetShuffle(unsigned Opcode) {
3747 default: return false;
3748 case X86ISD::BLENDI:
3749 case X86ISD::PSHUFB:
3750 case X86ISD::PSHUFD:
3751 case X86ISD::PSHUFHW:
3752 case X86ISD::PSHUFLW:
3754 case X86ISD::PALIGNR:
3755 case X86ISD::MOVLHPS:
3756 case X86ISD::MOVLHPD:
3757 case X86ISD::MOVHLPS:
3758 case X86ISD::MOVLPS:
3759 case X86ISD::MOVLPD:
3760 case X86ISD::MOVSHDUP:
3761 case X86ISD::MOVSLDUP:
3762 case X86ISD::MOVDDUP:
3765 case X86ISD::UNPCKL:
3766 case X86ISD::UNPCKH:
3767 case X86ISD::VPERMILPI:
3768 case X86ISD::VPERM2X128:
3769 case X86ISD::VPERMI:
3774 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3775 SDValue V1, unsigned TargetMask,
3776 SelectionDAG &DAG) {
3778 default: llvm_unreachable("Unknown x86 shuffle node");
3779 case X86ISD::PSHUFD:
3780 case X86ISD::PSHUFHW:
3781 case X86ISD::PSHUFLW:
3782 case X86ISD::VPERMILPI:
3783 case X86ISD::VPERMI:
3784 return DAG.getNode(Opc, dl, VT, V1,
3785 DAG.getConstant(TargetMask, dl, MVT::i8));
3789 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3790 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3792 default: llvm_unreachable("Unknown x86 shuffle node");
3793 case X86ISD::MOVLHPS:
3794 case X86ISD::MOVLHPD:
3795 case X86ISD::MOVHLPS:
3796 case X86ISD::MOVLPS:
3797 case X86ISD::MOVLPD:
3800 case X86ISD::UNPCKL:
3801 case X86ISD::UNPCKH:
3802 return DAG.getNode(Opc, dl, VT, V1, V2);
3806 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3807 MachineFunction &MF = DAG.getMachineFunction();
3808 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3809 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3810 int ReturnAddrIndex = FuncInfo->getRAIndex();
3812 if (ReturnAddrIndex == 0) {
3813 // Set up a frame object for the return address.
3814 unsigned SlotSize = RegInfo->getSlotSize();
3815 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3818 FuncInfo->setRAIndex(ReturnAddrIndex);
3821 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3824 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3825 bool hasSymbolicDisplacement) {
3826 // Offset should fit into 32 bit immediate field.
3827 if (!isInt<32>(Offset))
3830 // If we don't have a symbolic displacement - we don't have any extra
3832 if (!hasSymbolicDisplacement)
3835 // FIXME: Some tweaks might be needed for medium code model.
3836 if (M != CodeModel::Small && M != CodeModel::Kernel)
3839 // For small code model we assume that latest object is 16MB before end of 31
3840 // bits boundary. We may also accept pretty large negative constants knowing
3841 // that all objects are in the positive half of address space.
3842 if (M == CodeModel::Small && Offset < 16*1024*1024)
3845 // For kernel code model we know that all object resist in the negative half
3846 // of 32bits address space. We may not accept negative offsets, since they may
3847 // be just off and we may accept pretty large positive ones.
3848 if (M == CodeModel::Kernel && Offset >= 0)
3854 /// Determines whether the callee is required to pop its own arguments.
3855 /// Callee pop is necessary to support tail calls.
3856 bool X86::isCalleePop(CallingConv::ID CallingConv,
3857 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3858 switch (CallingConv) {
3861 case CallingConv::X86_StdCall:
3862 case CallingConv::X86_FastCall:
3863 case CallingConv::X86_ThisCall:
3865 case CallingConv::Fast:
3866 case CallingConv::GHC:
3867 case CallingConv::HiPE:
3874 /// \brief Return true if the condition is an unsigned comparison operation.
3875 static bool isX86CCUnsigned(unsigned X86CC) {
3877 default: llvm_unreachable("Invalid integer condition!");
3878 case X86::COND_E: return true;
3879 case X86::COND_G: return false;
3880 case X86::COND_GE: return false;
3881 case X86::COND_L: return false;
3882 case X86::COND_LE: return false;
3883 case X86::COND_NE: return true;
3884 case X86::COND_B: return true;
3885 case X86::COND_A: return true;
3886 case X86::COND_BE: return true;
3887 case X86::COND_AE: return true;
3889 llvm_unreachable("covered switch fell through?!");
3892 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3893 /// condition code, returning the condition code and the LHS/RHS of the
3894 /// comparison to make.
3895 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3896 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3898 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3899 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3900 // X > -1 -> X == 0, jump !sign.
3901 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3902 return X86::COND_NS;
3904 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3905 // X < 0 -> X == 0, jump on sign.
3908 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3910 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3911 return X86::COND_LE;
3915 switch (SetCCOpcode) {
3916 default: llvm_unreachable("Invalid integer condition!");
3917 case ISD::SETEQ: return X86::COND_E;
3918 case ISD::SETGT: return X86::COND_G;
3919 case ISD::SETGE: return X86::COND_GE;
3920 case ISD::SETLT: return X86::COND_L;
3921 case ISD::SETLE: return X86::COND_LE;
3922 case ISD::SETNE: return X86::COND_NE;
3923 case ISD::SETULT: return X86::COND_B;
3924 case ISD::SETUGT: return X86::COND_A;
3925 case ISD::SETULE: return X86::COND_BE;
3926 case ISD::SETUGE: return X86::COND_AE;
3930 // First determine if it is required or is profitable to flip the operands.
3932 // If LHS is a foldable load, but RHS is not, flip the condition.
3933 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3934 !ISD::isNON_EXTLoad(RHS.getNode())) {
3935 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3936 std::swap(LHS, RHS);
3939 switch (SetCCOpcode) {
3945 std::swap(LHS, RHS);
3949 // On a floating point condition, the flags are set as follows:
3951 // 0 | 0 | 0 | X > Y
3952 // 0 | 0 | 1 | X < Y
3953 // 1 | 0 | 0 | X == Y
3954 // 1 | 1 | 1 | unordered
3955 switch (SetCCOpcode) {
3956 default: llvm_unreachable("Condcode should be pre-legalized away");
3958 case ISD::SETEQ: return X86::COND_E;
3959 case ISD::SETOLT: // flipped
3961 case ISD::SETGT: return X86::COND_A;
3962 case ISD::SETOLE: // flipped
3964 case ISD::SETGE: return X86::COND_AE;
3965 case ISD::SETUGT: // flipped
3967 case ISD::SETLT: return X86::COND_B;
3968 case ISD::SETUGE: // flipped
3970 case ISD::SETLE: return X86::COND_BE;
3972 case ISD::SETNE: return X86::COND_NE;
3973 case ISD::SETUO: return X86::COND_P;
3974 case ISD::SETO: return X86::COND_NP;
3976 case ISD::SETUNE: return X86::COND_INVALID;
3980 /// Is there a floating point cmov for the specific X86 condition code?
3981 /// Current x86 isa includes the following FP cmov instructions:
3982 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3983 static bool hasFPCMov(unsigned X86CC) {
3999 /// Returns true if the target can instruction select the
4000 /// specified FP immediate natively. If false, the legalizer will
4001 /// materialize the FP immediate as a load from a constant pool.
4002 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4003 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4004 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4010 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4011 ISD::LoadExtType ExtTy,
4013 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4014 // relocation target a movq or addq instruction: don't let the load shrink.
4015 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4016 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4017 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4018 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4022 /// \brief Returns true if it is beneficial to convert a load of a constant
4023 /// to just the constant itself.
4024 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4026 assert(Ty->isIntegerTy());
4028 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4029 if (BitSize == 0 || BitSize > 64)
4034 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4035 unsigned Index) const {
4036 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4039 return (Index == 0 || Index == ResVT.getVectorNumElements());
4042 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4043 // Speculate cttz only if we can directly use TZCNT.
4044 return Subtarget->hasBMI();
4047 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4048 // Speculate ctlz only if we can directly use LZCNT.
4049 return Subtarget->hasLZCNT();
4052 /// Return true if every element in Mask, beginning
4053 /// from position Pos and ending in Pos+Size is undef.
4054 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4055 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4061 /// Return true if Val is undef or if its value falls within the
4062 /// specified range (L, H].
4063 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4064 return (Val < 0) || (Val >= Low && Val < Hi);
4067 /// Val is either less than zero (undef) or equal to the specified value.
4068 static bool isUndefOrEqual(int Val, int CmpVal) {
4069 return (Val < 0 || Val == CmpVal);
4072 /// Return true if every element in Mask, beginning
4073 /// from position Pos and ending in Pos+Size, falls within the specified
4074 /// sequential range (Low, Low+Size]. or is undef.
4075 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4076 unsigned Pos, unsigned Size, int Low) {
4077 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4078 if (!isUndefOrEqual(Mask[i], Low))
4083 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4084 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4085 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4086 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4087 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4090 // The index should be aligned on a vecWidth-bit boundary.
4092 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4094 MVT VT = N->getSimpleValueType(0);
4095 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4096 bool Result = (Index * ElSize) % vecWidth == 0;
4101 /// Return true if the specified INSERT_SUBVECTOR
4102 /// operand specifies a subvector insert that is suitable for input to
4103 /// insertion of 128 or 256-bit subvectors
4104 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4105 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4106 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4108 // The index should be aligned on a vecWidth-bit boundary.
4110 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4112 MVT VT = N->getSimpleValueType(0);
4113 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4114 bool Result = (Index * ElSize) % vecWidth == 0;
4119 bool X86::isVINSERT128Index(SDNode *N) {
4120 return isVINSERTIndex(N, 128);
4123 bool X86::isVINSERT256Index(SDNode *N) {
4124 return isVINSERTIndex(N, 256);
4127 bool X86::isVEXTRACT128Index(SDNode *N) {
4128 return isVEXTRACTIndex(N, 128);
4131 bool X86::isVEXTRACT256Index(SDNode *N) {
4132 return isVEXTRACTIndex(N, 256);
4135 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4136 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4137 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4138 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4141 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4143 MVT VecVT = N->getOperand(0).getSimpleValueType();
4144 MVT ElVT = VecVT.getVectorElementType();
4146 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4147 return Index / NumElemsPerChunk;
4150 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4151 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4152 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4153 llvm_unreachable("Illegal insert subvector for VINSERT");
4156 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4158 MVT VecVT = N->getSimpleValueType(0);
4159 MVT ElVT = VecVT.getVectorElementType();
4161 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4162 return Index / NumElemsPerChunk;
4165 /// Return the appropriate immediate to extract the specified
4166 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4167 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4168 return getExtractVEXTRACTImmediate(N, 128);
4171 /// Return the appropriate immediate to extract the specified
4172 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4173 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4174 return getExtractVEXTRACTImmediate(N, 256);
4177 /// Return the appropriate immediate to insert at the specified
4178 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4179 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4180 return getInsertVINSERTImmediate(N, 128);
4183 /// Return the appropriate immediate to insert at the specified
4184 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4185 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4186 return getInsertVINSERTImmediate(N, 256);
4189 /// Returns true if Elt is a constant integer zero
4190 static bool isZero(SDValue V) {
4191 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4192 return C && C->isNullValue();
4195 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4196 bool X86::isZeroNode(SDValue Elt) {
4199 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4200 return CFP->getValueAPF().isPosZero();
4204 /// Returns a vector of specified type with all zero elements.
4205 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4206 SelectionDAG &DAG, SDLoc dl) {
4207 assert(VT.isVector() && "Expected a vector type");
4209 // Always build SSE zero vectors as <4 x i32> bitcasted
4210 // to their dest type. This ensures they get CSE'd.
4212 if (VT.is128BitVector()) { // SSE
4213 if (Subtarget->hasSSE2()) { // SSE2
4214 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4215 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4217 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4218 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4220 } else if (VT.is256BitVector()) { // AVX
4221 if (Subtarget->hasInt256()) { // AVX2
4222 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4223 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4224 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4226 // 256-bit logic and arithmetic instructions in AVX are all
4227 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4228 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4229 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4230 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4232 } else if (VT.is512BitVector()) { // AVX-512
4233 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4234 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4235 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4236 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4237 } else if (VT.getScalarType() == MVT::i1) {
4239 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4240 && "Unexpected vector type");
4241 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4242 && "Unexpected vector type");
4243 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4244 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4245 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4247 llvm_unreachable("Unexpected vector type");
4249 return DAG.getBitcast(VT, Vec);
4252 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4253 SelectionDAG &DAG, SDLoc dl,
4254 unsigned vectorWidth) {
4255 assert((vectorWidth == 128 || vectorWidth == 256) &&
4256 "Unsupported vector width");
4257 EVT VT = Vec.getValueType();
4258 EVT ElVT = VT.getVectorElementType();
4259 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4260 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4261 VT.getVectorNumElements()/Factor);
4263 // Extract from UNDEF is UNDEF.
4264 if (Vec.getOpcode() == ISD::UNDEF)
4265 return DAG.getUNDEF(ResultVT);
4267 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4268 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4270 // This is the index of the first element of the vectorWidth-bit chunk
4272 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4275 // If the input is a buildvector just emit a smaller one.
4276 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4277 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4278 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4281 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4285 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4286 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4287 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4288 /// instructions or a simple subregister reference. Idx is an index in the
4289 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4290 /// lowering EXTRACT_VECTOR_ELT operations easier.
4291 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4292 SelectionDAG &DAG, SDLoc dl) {
4293 assert((Vec.getValueType().is256BitVector() ||
4294 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4295 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4298 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4299 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4300 SelectionDAG &DAG, SDLoc dl) {
4301 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4302 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4305 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4306 unsigned IdxVal, SelectionDAG &DAG,
4307 SDLoc dl, unsigned vectorWidth) {
4308 assert((vectorWidth == 128 || vectorWidth == 256) &&
4309 "Unsupported vector width");
4310 // Inserting UNDEF is Result
4311 if (Vec.getOpcode() == ISD::UNDEF)
4313 EVT VT = Vec.getValueType();
4314 EVT ElVT = VT.getVectorElementType();
4315 EVT ResultVT = Result.getValueType();
4317 // Insert the relevant vectorWidth bits.
4318 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4320 // This is the index of the first element of the vectorWidth-bit chunk
4322 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4325 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4326 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4329 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4330 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4331 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4332 /// simple superregister reference. Idx is an index in the 128 bits
4333 /// we want. It need not be aligned to a 128-bit boundary. That makes
4334 /// lowering INSERT_VECTOR_ELT operations easier.
4335 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4336 SelectionDAG &DAG, SDLoc dl) {
4337 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4339 // For insertion into the zero index (low half) of a 256-bit vector, it is
4340 // more efficient to generate a blend with immediate instead of an insert*128.
4341 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4342 // extend the subvector to the size of the result vector. Make sure that
4343 // we are not recursing on that node by checking for undef here.
4344 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4345 Result.getOpcode() != ISD::UNDEF) {
4346 EVT ResultVT = Result.getValueType();
4347 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4348 SDValue Undef = DAG.getUNDEF(ResultVT);
4349 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4352 // The blend instruction, and therefore its mask, depend on the data type.
4353 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4354 if (ScalarType.isFloatingPoint()) {
4355 // Choose either vblendps (float) or vblendpd (double).
4356 unsigned ScalarSize = ScalarType.getSizeInBits();
4357 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4358 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4359 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4360 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4363 const X86Subtarget &Subtarget =
4364 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4366 // AVX2 is needed for 256-bit integer blend support.
4367 // Integers must be cast to 32-bit because there is only vpblendd;
4368 // vpblendw can't be used for this because it has a handicapped mask.
4370 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4371 // is still more efficient than using the wrong domain vinsertf128 that
4372 // will be created by InsertSubVector().
4373 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4375 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4376 Vec256 = DAG.getBitcast(CastVT, Vec256);
4377 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4378 return DAG.getBitcast(ResultVT, Vec256);
4381 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4384 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4385 SelectionDAG &DAG, SDLoc dl) {
4386 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4387 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4390 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4391 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4392 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4393 /// large BUILD_VECTORS.
4394 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4395 unsigned NumElems, SelectionDAG &DAG,
4397 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4398 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4401 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4402 unsigned NumElems, SelectionDAG &DAG,
4404 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4405 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4408 /// Returns a vector of specified type with all bits set.
4409 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4410 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4411 /// Then bitcast to their original type, ensuring they get CSE'd.
4412 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4414 assert(VT.isVector() && "Expected a vector type");
4416 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4418 if (VT.is256BitVector()) {
4419 if (HasInt256) { // AVX2
4420 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4421 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4423 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4424 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4426 } else if (VT.is128BitVector()) {
4427 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4429 llvm_unreachable("Unexpected vector type");
4431 return DAG.getBitcast(VT, Vec);
4434 /// Returns a vector_shuffle node for an unpackl operation.
4435 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4437 unsigned NumElems = VT.getVectorNumElements();
4438 SmallVector<int, 8> Mask;
4439 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4441 Mask.push_back(i + NumElems);
4443 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4446 /// Returns a vector_shuffle node for an unpackh operation.
4447 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4449 unsigned NumElems = VT.getVectorNumElements();
4450 SmallVector<int, 8> Mask;
4451 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4452 Mask.push_back(i + Half);
4453 Mask.push_back(i + NumElems + Half);
4455 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4458 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4459 /// This produces a shuffle where the low element of V2 is swizzled into the
4460 /// zero/undef vector, landing at element Idx.
4461 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4462 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4464 const X86Subtarget *Subtarget,
4465 SelectionDAG &DAG) {
4466 MVT VT = V2.getSimpleValueType();
4468 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4469 unsigned NumElems = VT.getVectorNumElements();
4470 SmallVector<int, 16> MaskVec;
4471 for (unsigned i = 0; i != NumElems; ++i)
4472 // If this is the insertion idx, put the low elt of V2 here.
4473 MaskVec.push_back(i == Idx ? NumElems : i);
4474 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4477 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4478 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4479 /// uses one source. Note that this will set IsUnary for shuffles which use a
4480 /// single input multiple times, and in those cases it will
4481 /// adjust the mask to only have indices within that single input.
4482 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4483 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4484 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4485 unsigned NumElems = VT.getVectorNumElements();
4489 bool IsFakeUnary = false;
4490 switch(N->getOpcode()) {
4491 case X86ISD::BLENDI:
4492 ImmN = N->getOperand(N->getNumOperands()-1);
4493 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4496 ImmN = N->getOperand(N->getNumOperands()-1);
4497 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4498 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4500 case X86ISD::UNPCKH:
4501 DecodeUNPCKHMask(VT, Mask);
4502 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4504 case X86ISD::UNPCKL:
4505 DecodeUNPCKLMask(VT, Mask);
4506 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4508 case X86ISD::MOVHLPS:
4509 DecodeMOVHLPSMask(NumElems, Mask);
4510 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4512 case X86ISD::MOVLHPS:
4513 DecodeMOVLHPSMask(NumElems, Mask);
4514 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4516 case X86ISD::PALIGNR:
4517 ImmN = N->getOperand(N->getNumOperands()-1);
4518 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4520 case X86ISD::PSHUFD:
4521 case X86ISD::VPERMILPI:
4522 ImmN = N->getOperand(N->getNumOperands()-1);
4523 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4526 case X86ISD::PSHUFHW:
4527 ImmN = N->getOperand(N->getNumOperands()-1);
4528 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4531 case X86ISD::PSHUFLW:
4532 ImmN = N->getOperand(N->getNumOperands()-1);
4533 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4536 case X86ISD::PSHUFB: {
4538 SDValue MaskNode = N->getOperand(1);
4539 while (MaskNode->getOpcode() == ISD::BITCAST)
4540 MaskNode = MaskNode->getOperand(0);
4542 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4543 // If we have a build-vector, then things are easy.
4544 EVT VT = MaskNode.getValueType();
4545 assert(VT.isVector() &&
4546 "Can't produce a non-vector with a build_vector!");
4547 if (!VT.isInteger())
4550 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4552 SmallVector<uint64_t, 32> RawMask;
4553 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4554 SDValue Op = MaskNode->getOperand(i);
4555 if (Op->getOpcode() == ISD::UNDEF) {
4556 RawMask.push_back((uint64_t)SM_SentinelUndef);
4559 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4562 APInt MaskElement = CN->getAPIntValue();
4564 // We now have to decode the element which could be any integer size and
4565 // extract each byte of it.
4566 for (int j = 0; j < NumBytesPerElement; ++j) {
4567 // Note that this is x86 and so always little endian: the low byte is
4568 // the first byte of the mask.
4569 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4570 MaskElement = MaskElement.lshr(8);
4573 DecodePSHUFBMask(RawMask, Mask);
4577 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4581 SDValue Ptr = MaskLoad->getBasePtr();
4582 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4583 Ptr->getOpcode() == X86ISD::WrapperRIP)
4584 Ptr = Ptr->getOperand(0);
4586 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4587 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4590 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4591 DecodePSHUFBMask(C, Mask);
4599 case X86ISD::VPERMI:
4600 ImmN = N->getOperand(N->getNumOperands()-1);
4601 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4606 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4608 case X86ISD::VPERM2X128:
4609 ImmN = N->getOperand(N->getNumOperands()-1);
4610 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4611 if (Mask.empty()) return false;
4612 // Mask only contains negative index if an element is zero.
4613 if (std::any_of(Mask.begin(), Mask.end(),
4614 [](int M){ return M == SM_SentinelZero; }))
4617 case X86ISD::MOVSLDUP:
4618 DecodeMOVSLDUPMask(VT, Mask);
4621 case X86ISD::MOVSHDUP:
4622 DecodeMOVSHDUPMask(VT, Mask);
4625 case X86ISD::MOVDDUP:
4626 DecodeMOVDDUPMask(VT, Mask);
4629 case X86ISD::MOVLHPD:
4630 case X86ISD::MOVLPD:
4631 case X86ISD::MOVLPS:
4632 // Not yet implemented
4634 default: llvm_unreachable("unknown target shuffle node");
4637 // If we have a fake unary shuffle, the shuffle mask is spread across two
4638 // inputs that are actually the same node. Re-map the mask to always point
4639 // into the first input.
4642 if (M >= (int)Mask.size())
4648 /// Returns the scalar element that will make up the ith
4649 /// element of the result of the vector shuffle.
4650 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4653 return SDValue(); // Limit search depth.
4655 SDValue V = SDValue(N, 0);
4656 EVT VT = V.getValueType();
4657 unsigned Opcode = V.getOpcode();
4659 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4660 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4661 int Elt = SV->getMaskElt(Index);
4664 return DAG.getUNDEF(VT.getVectorElementType());
4666 unsigned NumElems = VT.getVectorNumElements();
4667 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4668 : SV->getOperand(1);
4669 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4672 // Recurse into target specific vector shuffles to find scalars.
4673 if (isTargetShuffle(Opcode)) {
4674 MVT ShufVT = V.getSimpleValueType();
4675 unsigned NumElems = ShufVT.getVectorNumElements();
4676 SmallVector<int, 16> ShuffleMask;
4679 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4682 int Elt = ShuffleMask[Index];
4684 return DAG.getUNDEF(ShufVT.getVectorElementType());
4686 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4688 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4692 // Actual nodes that may contain scalar elements
4693 if (Opcode == ISD::BITCAST) {
4694 V = V.getOperand(0);
4695 EVT SrcVT = V.getValueType();
4696 unsigned NumElems = VT.getVectorNumElements();
4698 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4702 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4703 return (Index == 0) ? V.getOperand(0)
4704 : DAG.getUNDEF(VT.getVectorElementType());
4706 if (V.getOpcode() == ISD::BUILD_VECTOR)
4707 return V.getOperand(Index);
4712 /// Custom lower build_vector of v16i8.
4713 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4714 unsigned NumNonZero, unsigned NumZero,
4716 const X86Subtarget* Subtarget,
4717 const TargetLowering &TLI) {
4725 // SSE4.1 - use PINSRB to insert each byte directly.
4726 if (Subtarget->hasSSE41()) {
4727 for (unsigned i = 0; i < 16; ++i) {
4728 bool isNonZero = (NonZeros & (1 << i)) != 0;
4732 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4734 V = DAG.getUNDEF(MVT::v16i8);
4737 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4738 MVT::v16i8, V, Op.getOperand(i),
4739 DAG.getIntPtrConstant(i, dl));
4746 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4747 for (unsigned i = 0; i < 16; ++i) {
4748 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4749 if (ThisIsNonZero && First) {
4751 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4753 V = DAG.getUNDEF(MVT::v8i16);
4758 SDValue ThisElt, LastElt;
4759 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4760 if (LastIsNonZero) {
4761 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4762 MVT::i16, Op.getOperand(i-1));
4764 if (ThisIsNonZero) {
4765 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4766 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4767 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4769 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4773 if (ThisElt.getNode())
4774 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4775 DAG.getIntPtrConstant(i/2, dl));
4779 return DAG.getBitcast(MVT::v16i8, V);
4782 /// Custom lower build_vector of v8i16.
4783 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4784 unsigned NumNonZero, unsigned NumZero,
4786 const X86Subtarget* Subtarget,
4787 const TargetLowering &TLI) {
4794 for (unsigned i = 0; i < 8; ++i) {
4795 bool isNonZero = (NonZeros & (1 << i)) != 0;
4799 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4801 V = DAG.getUNDEF(MVT::v8i16);
4804 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4805 MVT::v8i16, V, Op.getOperand(i),
4806 DAG.getIntPtrConstant(i, dl));
4813 /// Custom lower build_vector of v4i32 or v4f32.
4814 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4815 const X86Subtarget *Subtarget,
4816 const TargetLowering &TLI) {
4817 // Find all zeroable elements.
4818 std::bitset<4> Zeroable;
4819 for (int i=0; i < 4; ++i) {
4820 SDValue Elt = Op->getOperand(i);
4821 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4823 assert(Zeroable.size() - Zeroable.count() > 1 &&
4824 "We expect at least two non-zero elements!");
4826 // We only know how to deal with build_vector nodes where elements are either
4827 // zeroable or extract_vector_elt with constant index.
4828 SDValue FirstNonZero;
4829 unsigned FirstNonZeroIdx;
4830 for (unsigned i=0; i < 4; ++i) {
4833 SDValue Elt = Op->getOperand(i);
4834 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4835 !isa<ConstantSDNode>(Elt.getOperand(1)))
4837 // Make sure that this node is extracting from a 128-bit vector.
4838 MVT VT = Elt.getOperand(0).getSimpleValueType();
4839 if (!VT.is128BitVector())
4841 if (!FirstNonZero.getNode()) {
4843 FirstNonZeroIdx = i;
4847 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4848 SDValue V1 = FirstNonZero.getOperand(0);
4849 MVT VT = V1.getSimpleValueType();
4851 // See if this build_vector can be lowered as a blend with zero.
4853 unsigned EltMaskIdx, EltIdx;
4855 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4856 if (Zeroable[EltIdx]) {
4857 // The zero vector will be on the right hand side.
4858 Mask[EltIdx] = EltIdx+4;
4862 Elt = Op->getOperand(EltIdx);
4863 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4864 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4865 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4867 Mask[EltIdx] = EltIdx;
4871 // Let the shuffle legalizer deal with blend operations.
4872 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4873 if (V1.getSimpleValueType() != VT)
4874 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4875 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4878 // See if we can lower this build_vector to a INSERTPS.
4879 if (!Subtarget->hasSSE41())
4882 SDValue V2 = Elt.getOperand(0);
4883 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4886 bool CanFold = true;
4887 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4891 SDValue Current = Op->getOperand(i);
4892 SDValue SrcVector = Current->getOperand(0);
4895 CanFold = SrcVector == V1 &&
4896 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4902 assert(V1.getNode() && "Expected at least two non-zero elements!");
4903 if (V1.getSimpleValueType() != MVT::v4f32)
4904 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4905 if (V2.getSimpleValueType() != MVT::v4f32)
4906 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4908 // Ok, we can emit an INSERTPS instruction.
4909 unsigned ZMask = Zeroable.to_ulong();
4911 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4912 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4914 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4915 DAG.getIntPtrConstant(InsertPSMask, DL));
4916 return DAG.getBitcast(VT, Result);
4919 /// Return a vector logical shift node.
4920 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4921 unsigned NumBits, SelectionDAG &DAG,
4922 const TargetLowering &TLI, SDLoc dl) {
4923 assert(VT.is128BitVector() && "Unknown type for VShift");
4924 MVT ShVT = MVT::v2i64;
4925 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4926 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4927 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
4928 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4929 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4930 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4934 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4936 // Check if the scalar load can be widened into a vector load. And if
4937 // the address is "base + cst" see if the cst can be "absorbed" into
4938 // the shuffle mask.
4939 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4940 SDValue Ptr = LD->getBasePtr();
4941 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4943 EVT PVT = LD->getValueType(0);
4944 if (PVT != MVT::i32 && PVT != MVT::f32)
4949 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4950 FI = FINode->getIndex();
4952 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4953 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4954 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4955 Offset = Ptr.getConstantOperandVal(1);
4956 Ptr = Ptr.getOperand(0);
4961 // FIXME: 256-bit vector instructions don't require a strict alignment,
4962 // improve this code to support it better.
4963 unsigned RequiredAlign = VT.getSizeInBits()/8;
4964 SDValue Chain = LD->getChain();
4965 // Make sure the stack object alignment is at least 16 or 32.
4966 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4967 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4968 if (MFI->isFixedObjectIndex(FI)) {
4969 // Can't change the alignment. FIXME: It's possible to compute
4970 // the exact stack offset and reference FI + adjust offset instead.
4971 // If someone *really* cares about this. That's the way to implement it.
4974 MFI->setObjectAlignment(FI, RequiredAlign);
4978 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4979 // Ptr + (Offset & ~15).
4982 if ((Offset % RequiredAlign) & 3)
4984 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
4987 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4988 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4991 int EltNo = (Offset - StartOffset) >> 2;
4992 unsigned NumElems = VT.getVectorNumElements();
4994 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4995 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4996 LD->getPointerInfo().getWithOffset(StartOffset),
4997 false, false, false, 0);
4999 SmallVector<int, 8> Mask(NumElems, EltNo);
5001 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5007 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5008 /// elements can be replaced by a single large load which has the same value as
5009 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5011 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5013 /// FIXME: we'd also like to handle the case where the last elements are zero
5014 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5015 /// There's even a handy isZeroNode for that purpose.
5016 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5017 SDLoc &DL, SelectionDAG &DAG,
5018 bool isAfterLegalize) {
5019 unsigned NumElems = Elts.size();
5021 LoadSDNode *LDBase = nullptr;
5022 unsigned LastLoadedElt = -1U;
5024 // For each element in the initializer, see if we've found a load or an undef.
5025 // If we don't find an initial load element, or later load elements are
5026 // non-consecutive, bail out.
5027 for (unsigned i = 0; i < NumElems; ++i) {
5028 SDValue Elt = Elts[i];
5029 // Look through a bitcast.
5030 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5031 Elt = Elt.getOperand(0);
5032 if (!Elt.getNode() ||
5033 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5036 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5038 LDBase = cast<LoadSDNode>(Elt.getNode());
5042 if (Elt.getOpcode() == ISD::UNDEF)
5045 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5046 EVT LdVT = Elt.getValueType();
5047 // Each loaded element must be the correct fractional portion of the
5048 // requested vector load.
5049 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5051 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5056 // If we have found an entire vector of loads and undefs, then return a large
5057 // load of the entire vector width starting at the base pointer. If we found
5058 // consecutive loads for the low half, generate a vzext_load node.
5059 if (LastLoadedElt == NumElems - 1) {
5060 assert(LDBase && "Did not find base load for merging consecutive loads");
5061 EVT EltVT = LDBase->getValueType(0);
5062 // Ensure that the input vector size for the merged loads matches the
5063 // cumulative size of the input elements.
5064 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5067 if (isAfterLegalize &&
5068 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5071 SDValue NewLd = SDValue();
5073 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5074 LDBase->getPointerInfo(), LDBase->isVolatile(),
5075 LDBase->isNonTemporal(), LDBase->isInvariant(),
5076 LDBase->getAlignment());
5078 if (LDBase->hasAnyUseOfValue(1)) {
5079 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5081 SDValue(NewLd.getNode(), 1));
5082 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5083 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5084 SDValue(NewLd.getNode(), 1));
5090 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5091 //of a v4i32 / v4f32. It's probably worth generalizing.
5092 EVT EltVT = VT.getVectorElementType();
5093 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5094 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5095 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5096 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5098 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5099 LDBase->getPointerInfo(),
5100 LDBase->getAlignment(),
5101 false/*isVolatile*/, true/*ReadMem*/,
5104 // Make sure the newly-created LOAD is in the same position as LDBase in
5105 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5106 // update uses of LDBase's output chain to use the TokenFactor.
5107 if (LDBase->hasAnyUseOfValue(1)) {
5108 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5109 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5110 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5111 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5112 SDValue(ResNode.getNode(), 1));
5115 return DAG.getBitcast(VT, ResNode);
5120 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5121 /// to generate a splat value for the following cases:
5122 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5123 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5124 /// a scalar load, or a constant.
5125 /// The VBROADCAST node is returned when a pattern is found,
5126 /// or SDValue() otherwise.
5127 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5128 SelectionDAG &DAG) {
5129 // VBROADCAST requires AVX.
5130 // TODO: Splats could be generated for non-AVX CPUs using SSE
5131 // instructions, but there's less potential gain for only 128-bit vectors.
5132 if (!Subtarget->hasAVX())
5135 MVT VT = Op.getSimpleValueType();
5138 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5139 "Unsupported vector type for broadcast.");
5144 switch (Op.getOpcode()) {
5146 // Unknown pattern found.
5149 case ISD::BUILD_VECTOR: {
5150 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5151 BitVector UndefElements;
5152 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5154 // We need a splat of a single value to use broadcast, and it doesn't
5155 // make any sense if the value is only in one element of the vector.
5156 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5160 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5161 Ld.getOpcode() == ISD::ConstantFP);
5163 // Make sure that all of the users of a non-constant load are from the
5164 // BUILD_VECTOR node.
5165 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5170 case ISD::VECTOR_SHUFFLE: {
5171 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5173 // Shuffles must have a splat mask where the first element is
5175 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5178 SDValue Sc = Op.getOperand(0);
5179 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5180 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5182 if (!Subtarget->hasInt256())
5185 // Use the register form of the broadcast instruction available on AVX2.
5186 if (VT.getSizeInBits() >= 256)
5187 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5188 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5191 Ld = Sc.getOperand(0);
5192 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5193 Ld.getOpcode() == ISD::ConstantFP);
5195 // The scalar_to_vector node and the suspected
5196 // load node must have exactly one user.
5197 // Constants may have multiple users.
5199 // AVX-512 has register version of the broadcast
5200 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5201 Ld.getValueType().getSizeInBits() >= 32;
5202 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5209 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5210 bool IsGE256 = (VT.getSizeInBits() >= 256);
5212 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5213 // instruction to save 8 or more bytes of constant pool data.
5214 // TODO: If multiple splats are generated to load the same constant,
5215 // it may be detrimental to overall size. There needs to be a way to detect
5216 // that condition to know if this is truly a size win.
5217 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5219 // Handle broadcasting a single constant scalar from the constant pool
5221 // On Sandybridge (no AVX2), it is still better to load a constant vector
5222 // from the constant pool and not to broadcast it from a scalar.
5223 // But override that restriction when optimizing for size.
5224 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5225 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5226 EVT CVT = Ld.getValueType();
5227 assert(!CVT.isVector() && "Must not broadcast a vector type");
5229 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5230 // For size optimization, also splat v2f64 and v2i64, and for size opt
5231 // with AVX2, also splat i8 and i16.
5232 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5233 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5234 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5235 const Constant *C = nullptr;
5236 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5237 C = CI->getConstantIntValue();
5238 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5239 C = CF->getConstantFPValue();
5241 assert(C && "Invalid constant type");
5243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5245 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5246 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5248 CVT, dl, DAG.getEntryNode(), CP,
5249 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5250 false, false, Alignment);
5252 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5256 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5258 // Handle AVX2 in-register broadcasts.
5259 if (!IsLoad && Subtarget->hasInt256() &&
5260 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5261 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5263 // The scalar source must be a normal load.
5267 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5268 (Subtarget->hasVLX() && ScalarSize == 64))
5269 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5271 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5272 // double since there is no vbroadcastsd xmm
5273 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5274 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5275 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5278 // Unsupported broadcast.
5282 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5283 /// underlying vector and index.
5285 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5287 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5289 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5290 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5293 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5295 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5297 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5298 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5301 // In this case the vector is the extract_subvector expression and the index
5302 // is 2, as specified by the shuffle.
5303 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5304 SDValue ShuffleVec = SVOp->getOperand(0);
5305 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5306 assert(ShuffleVecVT.getVectorElementType() ==
5307 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5309 int ShuffleIdx = SVOp->getMaskElt(Idx);
5310 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5311 ExtractedFromVec = ShuffleVec;
5317 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5318 MVT VT = Op.getSimpleValueType();
5320 // Skip if insert_vec_elt is not supported.
5321 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5322 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5326 unsigned NumElems = Op.getNumOperands();
5330 SmallVector<unsigned, 4> InsertIndices;
5331 SmallVector<int, 8> Mask(NumElems, -1);
5333 for (unsigned i = 0; i != NumElems; ++i) {
5334 unsigned Opc = Op.getOperand(i).getOpcode();
5336 if (Opc == ISD::UNDEF)
5339 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5340 // Quit if more than 1 elements need inserting.
5341 if (InsertIndices.size() > 1)
5344 InsertIndices.push_back(i);
5348 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5349 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5350 // Quit if non-constant index.
5351 if (!isa<ConstantSDNode>(ExtIdx))
5353 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5355 // Quit if extracted from vector of different type.
5356 if (ExtractedFromVec.getValueType() != VT)
5359 if (!VecIn1.getNode())
5360 VecIn1 = ExtractedFromVec;
5361 else if (VecIn1 != ExtractedFromVec) {
5362 if (!VecIn2.getNode())
5363 VecIn2 = ExtractedFromVec;
5364 else if (VecIn2 != ExtractedFromVec)
5365 // Quit if more than 2 vectors to shuffle
5369 if (ExtractedFromVec == VecIn1)
5371 else if (ExtractedFromVec == VecIn2)
5372 Mask[i] = Idx + NumElems;
5375 if (!VecIn1.getNode())
5378 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5379 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5380 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5381 unsigned Idx = InsertIndices[i];
5382 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5383 DAG.getIntPtrConstant(Idx, DL));
5389 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5390 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5391 Op.getScalarValueSizeInBits() == 1 &&
5392 "Can not convert non-constant vector");
5393 uint64_t Immediate = 0;
5394 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5395 SDValue In = Op.getOperand(idx);
5396 if (In.getOpcode() != ISD::UNDEF)
5397 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5401 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5402 return DAG.getConstant(Immediate, dl, VT);
5404 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5406 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5408 MVT VT = Op.getSimpleValueType();
5409 assert((VT.getVectorElementType() == MVT::i1) &&
5410 "Unexpected type in LowerBUILD_VECTORvXi1!");
5413 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5414 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5415 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5416 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5419 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5420 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5421 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5422 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5425 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5426 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5427 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5428 return DAG.getBitcast(VT, Imm);
5429 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5430 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5431 DAG.getIntPtrConstant(0, dl));
5434 // Vector has one or more non-const elements
5435 uint64_t Immediate = 0;
5436 SmallVector<unsigned, 16> NonConstIdx;
5437 bool IsSplat = true;
5438 bool HasConstElts = false;
5440 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5441 SDValue In = Op.getOperand(idx);
5442 if (In.getOpcode() == ISD::UNDEF)
5444 if (!isa<ConstantSDNode>(In))
5445 NonConstIdx.push_back(idx);
5447 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5448 HasConstElts = true;
5452 else if (In != Op.getOperand(SplatIdx))
5456 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5458 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5459 DAG.getConstant(1, dl, VT),
5460 DAG.getConstant(0, dl, VT));
5462 // insert elements one by one
5466 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5467 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5469 else if (HasConstElts)
5470 Imm = DAG.getConstant(0, dl, VT);
5472 Imm = DAG.getUNDEF(VT);
5473 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5474 DstVec = DAG.getBitcast(VT, Imm);
5476 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5477 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5478 DAG.getIntPtrConstant(0, dl));
5481 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5482 unsigned InsertIdx = NonConstIdx[i];
5483 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5484 Op.getOperand(InsertIdx),
5485 DAG.getIntPtrConstant(InsertIdx, dl));
5490 /// \brief Return true if \p N implements a horizontal binop and return the
5491 /// operands for the horizontal binop into V0 and V1.
5493 /// This is a helper function of LowerToHorizontalOp().
5494 /// This function checks that the build_vector \p N in input implements a
5495 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5496 /// operation to match.
5497 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5498 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5499 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5502 /// This function only analyzes elements of \p N whose indices are
5503 /// in range [BaseIdx, LastIdx).
5504 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5506 unsigned BaseIdx, unsigned LastIdx,
5507 SDValue &V0, SDValue &V1) {
5508 EVT VT = N->getValueType(0);
5510 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5511 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5512 "Invalid Vector in input!");
5514 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5515 bool CanFold = true;
5516 unsigned ExpectedVExtractIdx = BaseIdx;
5517 unsigned NumElts = LastIdx - BaseIdx;
5518 V0 = DAG.getUNDEF(VT);
5519 V1 = DAG.getUNDEF(VT);
5521 // Check if N implements a horizontal binop.
5522 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5523 SDValue Op = N->getOperand(i + BaseIdx);
5526 if (Op->getOpcode() == ISD::UNDEF) {
5527 // Update the expected vector extract index.
5528 if (i * 2 == NumElts)
5529 ExpectedVExtractIdx = BaseIdx;
5530 ExpectedVExtractIdx += 2;
5534 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5539 SDValue Op0 = Op.getOperand(0);
5540 SDValue Op1 = Op.getOperand(1);
5542 // Try to match the following pattern:
5543 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5544 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5545 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5546 Op0.getOperand(0) == Op1.getOperand(0) &&
5547 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5548 isa<ConstantSDNode>(Op1.getOperand(1)));
5552 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5553 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5555 if (i * 2 < NumElts) {
5556 if (V0.getOpcode() == ISD::UNDEF) {
5557 V0 = Op0.getOperand(0);
5558 if (V0.getValueType() != VT)
5562 if (V1.getOpcode() == ISD::UNDEF) {
5563 V1 = Op0.getOperand(0);
5564 if (V1.getValueType() != VT)
5567 if (i * 2 == NumElts)
5568 ExpectedVExtractIdx = BaseIdx;
5571 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5572 if (I0 == ExpectedVExtractIdx)
5573 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5574 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5575 // Try to match the following dag sequence:
5576 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5577 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5581 ExpectedVExtractIdx += 2;
5587 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5588 /// a concat_vector.
5590 /// This is a helper function of LowerToHorizontalOp().
5591 /// This function expects two 256-bit vectors called V0 and V1.
5592 /// At first, each vector is split into two separate 128-bit vectors.
5593 /// Then, the resulting 128-bit vectors are used to implement two
5594 /// horizontal binary operations.
5596 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5598 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5599 /// the two new horizontal binop.
5600 /// When Mode is set, the first horizontal binop dag node would take as input
5601 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5602 /// horizontal binop dag node would take as input the lower 128-bit of V1
5603 /// and the upper 128-bit of V1.
5605 /// HADD V0_LO, V0_HI
5606 /// HADD V1_LO, V1_HI
5608 /// Otherwise, the first horizontal binop dag node takes as input the lower
5609 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5610 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5612 /// HADD V0_LO, V1_LO
5613 /// HADD V0_HI, V1_HI
5615 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5616 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5617 /// the upper 128-bits of the result.
5618 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5619 SDLoc DL, SelectionDAG &DAG,
5620 unsigned X86Opcode, bool Mode,
5621 bool isUndefLO, bool isUndefHI) {
5622 EVT VT = V0.getValueType();
5623 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5624 "Invalid nodes in input!");
5626 unsigned NumElts = VT.getVectorNumElements();
5627 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5628 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5629 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5630 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5631 EVT NewVT = V0_LO.getValueType();
5633 SDValue LO = DAG.getUNDEF(NewVT);
5634 SDValue HI = DAG.getUNDEF(NewVT);
5637 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5638 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5639 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5640 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5641 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5643 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5644 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5645 V1_LO->getOpcode() != ISD::UNDEF))
5646 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5648 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5649 V1_HI->getOpcode() != ISD::UNDEF))
5650 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5653 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5656 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5658 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5659 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5660 EVT VT = BV->getValueType(0);
5661 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5662 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5666 unsigned NumElts = VT.getVectorNumElements();
5667 SDValue InVec0 = DAG.getUNDEF(VT);
5668 SDValue InVec1 = DAG.getUNDEF(VT);
5670 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5671 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5673 // Odd-numbered elements in the input build vector are obtained from
5674 // adding two integer/float elements.
5675 // Even-numbered elements in the input build vector are obtained from
5676 // subtracting two integer/float elements.
5677 unsigned ExpectedOpcode = ISD::FSUB;
5678 unsigned NextExpectedOpcode = ISD::FADD;
5679 bool AddFound = false;
5680 bool SubFound = false;
5682 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5683 SDValue Op = BV->getOperand(i);
5685 // Skip 'undef' values.
5686 unsigned Opcode = Op.getOpcode();
5687 if (Opcode == ISD::UNDEF) {
5688 std::swap(ExpectedOpcode, NextExpectedOpcode);
5692 // Early exit if we found an unexpected opcode.
5693 if (Opcode != ExpectedOpcode)
5696 SDValue Op0 = Op.getOperand(0);
5697 SDValue Op1 = Op.getOperand(1);
5699 // Try to match the following pattern:
5700 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5701 // Early exit if we cannot match that sequence.
5702 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5703 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5704 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5705 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5706 Op0.getOperand(1) != Op1.getOperand(1))
5709 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5713 // We found a valid add/sub node. Update the information accordingly.
5719 // Update InVec0 and InVec1.
5720 if (InVec0.getOpcode() == ISD::UNDEF) {
5721 InVec0 = Op0.getOperand(0);
5722 if (InVec0.getValueType() != VT)
5725 if (InVec1.getOpcode() == ISD::UNDEF) {
5726 InVec1 = Op1.getOperand(0);
5727 if (InVec1.getValueType() != VT)
5731 // Make sure that operands in input to each add/sub node always
5732 // come from a same pair of vectors.
5733 if (InVec0 != Op0.getOperand(0)) {
5734 if (ExpectedOpcode == ISD::FSUB)
5737 // FADD is commutable. Try to commute the operands
5738 // and then test again.
5739 std::swap(Op0, Op1);
5740 if (InVec0 != Op0.getOperand(0))
5744 if (InVec1 != Op1.getOperand(0))
5747 // Update the pair of expected opcodes.
5748 std::swap(ExpectedOpcode, NextExpectedOpcode);
5751 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5752 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5753 InVec1.getOpcode() != ISD::UNDEF)
5754 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5759 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5760 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5761 const X86Subtarget *Subtarget,
5762 SelectionDAG &DAG) {
5763 EVT VT = BV->getValueType(0);
5764 unsigned NumElts = VT.getVectorNumElements();
5765 unsigned NumUndefsLO = 0;
5766 unsigned NumUndefsHI = 0;
5767 unsigned Half = NumElts/2;
5769 // Count the number of UNDEF operands in the build_vector in input.
5770 for (unsigned i = 0, e = Half; i != e; ++i)
5771 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5774 for (unsigned i = Half, e = NumElts; i != e; ++i)
5775 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5778 // Early exit if this is either a build_vector of all UNDEFs or all the
5779 // operands but one are UNDEF.
5780 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5784 SDValue InVec0, InVec1;
5785 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5786 // Try to match an SSE3 float HADD/HSUB.
5787 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5788 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5790 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5791 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5792 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5793 // Try to match an SSSE3 integer HADD/HSUB.
5794 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5795 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5797 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5798 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5801 if (!Subtarget->hasAVX())
5804 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5805 // Try to match an AVX horizontal add/sub of packed single/double
5806 // precision floating point values from 256-bit vectors.
5807 SDValue InVec2, InVec3;
5808 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5809 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5810 ((InVec0.getOpcode() == ISD::UNDEF ||
5811 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5812 ((InVec1.getOpcode() == ISD::UNDEF ||
5813 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5814 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5816 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5817 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5818 ((InVec0.getOpcode() == ISD::UNDEF ||
5819 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5820 ((InVec1.getOpcode() == ISD::UNDEF ||
5821 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5822 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5823 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5824 // Try to match an AVX2 horizontal add/sub of signed integers.
5825 SDValue InVec2, InVec3;
5827 bool CanFold = true;
5829 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5830 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5831 ((InVec0.getOpcode() == ISD::UNDEF ||
5832 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5833 ((InVec1.getOpcode() == ISD::UNDEF ||
5834 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5835 X86Opcode = X86ISD::HADD;
5836 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5837 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5838 ((InVec0.getOpcode() == ISD::UNDEF ||
5839 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5840 ((InVec1.getOpcode() == ISD::UNDEF ||
5841 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5842 X86Opcode = X86ISD::HSUB;
5847 // Fold this build_vector into a single horizontal add/sub.
5848 // Do this only if the target has AVX2.
5849 if (Subtarget->hasAVX2())
5850 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5852 // Do not try to expand this build_vector into a pair of horizontal
5853 // add/sub if we can emit a pair of scalar add/sub.
5854 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5857 // Convert this build_vector into a pair of horizontal binop followed by
5859 bool isUndefLO = NumUndefsLO == Half;
5860 bool isUndefHI = NumUndefsHI == Half;
5861 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5862 isUndefLO, isUndefHI);
5866 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5867 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5869 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5870 X86Opcode = X86ISD::HADD;
5871 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5872 X86Opcode = X86ISD::HSUB;
5873 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5874 X86Opcode = X86ISD::FHADD;
5875 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5876 X86Opcode = X86ISD::FHSUB;
5880 // Don't try to expand this build_vector into a pair of horizontal add/sub
5881 // if we can simply emit a pair of scalar add/sub.
5882 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5885 // Convert this build_vector into two horizontal add/sub followed by
5887 bool isUndefLO = NumUndefsLO == Half;
5888 bool isUndefHI = NumUndefsHI == Half;
5889 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5890 isUndefLO, isUndefHI);
5897 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5900 MVT VT = Op.getSimpleValueType();
5901 MVT ExtVT = VT.getVectorElementType();
5902 unsigned NumElems = Op.getNumOperands();
5904 // Generate vectors for predicate vectors.
5905 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5906 return LowerBUILD_VECTORvXi1(Op, DAG);
5908 // Vectors containing all zeros can be matched by pxor and xorps later
5909 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5910 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5911 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5912 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5915 return getZeroVector(VT, Subtarget, DAG, dl);
5918 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5919 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5920 // vpcmpeqd on 256-bit vectors.
5921 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5922 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5925 if (!VT.is512BitVector())
5926 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5929 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5930 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5932 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5933 return HorizontalOp;
5934 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5937 unsigned EVTBits = ExtVT.getSizeInBits();
5939 unsigned NumZero = 0;
5940 unsigned NumNonZero = 0;
5941 unsigned NonZeros = 0;
5942 bool IsAllConstants = true;
5943 SmallSet<SDValue, 8> Values;
5944 for (unsigned i = 0; i < NumElems; ++i) {
5945 SDValue Elt = Op.getOperand(i);
5946 if (Elt.getOpcode() == ISD::UNDEF)
5949 if (Elt.getOpcode() != ISD::Constant &&
5950 Elt.getOpcode() != ISD::ConstantFP)
5951 IsAllConstants = false;
5952 if (X86::isZeroNode(Elt))
5955 NonZeros |= (1 << i);
5960 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5961 if (NumNonZero == 0)
5962 return DAG.getUNDEF(VT);
5964 // Special case for single non-zero, non-undef, element.
5965 if (NumNonZero == 1) {
5966 unsigned Idx = countTrailingZeros(NonZeros);
5967 SDValue Item = Op.getOperand(Idx);
5969 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5970 // the value are obviously zero, truncate the value to i32 and do the
5971 // insertion that way. Only do this if the value is non-constant or if the
5972 // value is a constant being inserted into element 0. It is cheaper to do
5973 // a constant pool load than it is to do a movd + shuffle.
5974 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5975 (!IsAllConstants || Idx == 0)) {
5976 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5978 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5979 EVT VecVT = MVT::v4i32;
5981 // Truncate the value (which may itself be a constant) to i32, and
5982 // convert it to a vector with movd (S2V+shuffle to zero extend).
5983 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5984 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5985 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5986 Item, Idx * 2, true, Subtarget, DAG));
5990 // If we have a constant or non-constant insertion into the low element of
5991 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5992 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5993 // depending on what the source datatype is.
5996 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5998 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5999 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6000 if (VT.is512BitVector()) {
6001 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6002 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6003 Item, DAG.getIntPtrConstant(0, dl));
6005 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6006 "Expected an SSE value type!");
6007 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6008 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6009 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6012 // We can't directly insert an i8 or i16 into a vector, so zero extend
6014 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6015 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6016 if (VT.is256BitVector()) {
6017 if (Subtarget->hasAVX()) {
6018 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6019 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6021 // Without AVX, we need to extend to a 128-bit vector and then
6022 // insert into the 256-bit vector.
6023 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6024 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6025 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6028 assert(VT.is128BitVector() && "Expected an SSE value type!");
6029 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6030 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6032 return DAG.getBitcast(VT, Item);
6036 // Is it a vector logical left shift?
6037 if (NumElems == 2 && Idx == 1 &&
6038 X86::isZeroNode(Op.getOperand(0)) &&
6039 !X86::isZeroNode(Op.getOperand(1))) {
6040 unsigned NumBits = VT.getSizeInBits();
6041 return getVShift(true, VT,
6042 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6043 VT, Op.getOperand(1)),
6044 NumBits/2, DAG, *this, dl);
6047 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6050 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6051 // is a non-constant being inserted into an element other than the low one,
6052 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6053 // movd/movss) to move this into the low element, then shuffle it into
6055 if (EVTBits == 32) {
6056 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6057 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6061 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6062 if (Values.size() == 1) {
6063 if (EVTBits == 32) {
6064 // Instead of a shuffle like this:
6065 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6066 // Check if it's possible to issue this instead.
6067 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6068 unsigned Idx = countTrailingZeros(NonZeros);
6069 SDValue Item = Op.getOperand(Idx);
6070 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6071 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6076 // A vector full of immediates; various special cases are already
6077 // handled, so this is best done with a single constant-pool load.
6081 // For AVX-length vectors, see if we can use a vector load to get all of the
6082 // elements, otherwise build the individual 128-bit pieces and use
6083 // shuffles to put them in place.
6084 if (VT.is256BitVector() || VT.is512BitVector()) {
6085 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6087 // Check for a build vector of consecutive loads.
6088 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6091 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6093 // Build both the lower and upper subvector.
6094 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6095 makeArrayRef(&V[0], NumElems/2));
6096 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6097 makeArrayRef(&V[NumElems / 2], NumElems/2));
6099 // Recreate the wider vector with the lower and upper part.
6100 if (VT.is256BitVector())
6101 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6102 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6105 // Let legalizer expand 2-wide build_vectors.
6106 if (EVTBits == 64) {
6107 if (NumNonZero == 1) {
6108 // One half is zero or undef.
6109 unsigned Idx = countTrailingZeros(NonZeros);
6110 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6111 Op.getOperand(Idx));
6112 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6117 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6118 if (EVTBits == 8 && NumElems == 16)
6119 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6123 if (EVTBits == 16 && NumElems == 8)
6124 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6128 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6129 if (EVTBits == 32 && NumElems == 4)
6130 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6133 // If element VT is == 32 bits, turn it into a number of shuffles.
6134 SmallVector<SDValue, 8> V(NumElems);
6135 if (NumElems == 4 && NumZero > 0) {
6136 for (unsigned i = 0; i < 4; ++i) {
6137 bool isZero = !(NonZeros & (1 << i));
6139 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6141 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6144 for (unsigned i = 0; i < 2; ++i) {
6145 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6148 V[i] = V[i*2]; // Must be a zero vector.
6151 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6154 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6157 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6162 bool Reverse1 = (NonZeros & 0x3) == 2;
6163 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6167 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6168 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6170 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6173 if (Values.size() > 1 && VT.is128BitVector()) {
6174 // Check for a build vector of consecutive loads.
6175 for (unsigned i = 0; i < NumElems; ++i)
6176 V[i] = Op.getOperand(i);
6178 // Check for elements which are consecutive loads.
6179 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6182 // Check for a build vector from mostly shuffle plus few inserting.
6183 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6186 // For SSE 4.1, use insertps to put the high elements into the low element.
6187 if (Subtarget->hasSSE41()) {
6189 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6190 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6192 Result = DAG.getUNDEF(VT);
6194 for (unsigned i = 1; i < NumElems; ++i) {
6195 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6196 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6197 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6202 // Otherwise, expand into a number of unpckl*, start by extending each of
6203 // our (non-undef) elements to the full vector width with the element in the
6204 // bottom slot of the vector (which generates no code for SSE).
6205 for (unsigned i = 0; i < NumElems; ++i) {
6206 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6207 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6209 V[i] = DAG.getUNDEF(VT);
6212 // Next, we iteratively mix elements, e.g. for v4f32:
6213 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6214 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6215 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6216 unsigned EltStride = NumElems >> 1;
6217 while (EltStride != 0) {
6218 for (unsigned i = 0; i < EltStride; ++i) {
6219 // If V[i+EltStride] is undef and this is the first round of mixing,
6220 // then it is safe to just drop this shuffle: V[i] is already in the
6221 // right place, the one element (since it's the first round) being
6222 // inserted as undef can be dropped. This isn't safe for successive
6223 // rounds because they will permute elements within both vectors.
6224 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6225 EltStride == NumElems/2)
6228 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6237 // 256-bit AVX can use the vinsertf128 instruction
6238 // to create 256-bit vectors from two other 128-bit ones.
6239 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6241 MVT ResVT = Op.getSimpleValueType();
6243 assert((ResVT.is256BitVector() ||
6244 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6246 SDValue V1 = Op.getOperand(0);
6247 SDValue V2 = Op.getOperand(1);
6248 unsigned NumElems = ResVT.getVectorNumElements();
6249 if (ResVT.is256BitVector())
6250 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6252 if (Op.getNumOperands() == 4) {
6253 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6254 ResVT.getVectorNumElements()/2);
6255 SDValue V3 = Op.getOperand(2);
6256 SDValue V4 = Op.getOperand(3);
6257 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6258 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6260 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6263 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6264 const X86Subtarget *Subtarget,
6265 SelectionDAG & DAG) {
6267 MVT ResVT = Op.getSimpleValueType();
6268 unsigned NumOfOperands = Op.getNumOperands();
6270 assert(isPowerOf2_32(NumOfOperands) &&
6271 "Unexpected number of operands in CONCAT_VECTORS");
6273 if (NumOfOperands > 2) {
6274 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6275 ResVT.getVectorNumElements()/2);
6276 SmallVector<SDValue, 2> Ops;
6277 for (unsigned i = 0; i < NumOfOperands/2; i++)
6278 Ops.push_back(Op.getOperand(i));
6279 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6281 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6282 Ops.push_back(Op.getOperand(i));
6283 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6284 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6287 SDValue V1 = Op.getOperand(0);
6288 SDValue V2 = Op.getOperand(1);
6289 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6290 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6292 if (IsZeroV1 && IsZeroV2)
6293 return getZeroVector(ResVT, Subtarget, DAG, dl);
6295 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6296 SDValue Undef = DAG.getUNDEF(ResVT);
6297 unsigned NumElems = ResVT.getVectorNumElements();
6298 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6300 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6301 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6305 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6306 // Zero the upper bits of V1
6307 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6308 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6311 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6314 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6315 const X86Subtarget *Subtarget,
6316 SelectionDAG &DAG) {
6317 MVT VT = Op.getSimpleValueType();
6318 if (VT.getVectorElementType() == MVT::i1)
6319 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6321 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6322 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6323 Op.getNumOperands() == 4)));
6325 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6326 // from two other 128-bit ones.
6328 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6329 return LowerAVXCONCAT_VECTORS(Op, DAG);
6333 //===----------------------------------------------------------------------===//
6334 // Vector shuffle lowering
6336 // This is an experimental code path for lowering vector shuffles on x86. It is
6337 // designed to handle arbitrary vector shuffles and blends, gracefully
6338 // degrading performance as necessary. It works hard to recognize idiomatic
6339 // shuffles and lower them to optimal instruction patterns without leaving
6340 // a framework that allows reasonably efficient handling of all vector shuffle
6342 //===----------------------------------------------------------------------===//
6344 /// \brief Tiny helper function to identify a no-op mask.
6346 /// This is a somewhat boring predicate function. It checks whether the mask
6347 /// array input, which is assumed to be a single-input shuffle mask of the kind
6348 /// used by the X86 shuffle instructions (not a fully general
6349 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6350 /// in-place shuffle are 'no-op's.
6351 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6352 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6353 if (Mask[i] != -1 && Mask[i] != i)
6358 /// \brief Helper function to classify a mask as a single-input mask.
6360 /// This isn't a generic single-input test because in the vector shuffle
6361 /// lowering we canonicalize single inputs to be the first input operand. This
6362 /// means we can more quickly test for a single input by only checking whether
6363 /// an input from the second operand exists. We also assume that the size of
6364 /// mask corresponds to the size of the input vectors which isn't true in the
6365 /// fully general case.
6366 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6368 if (M >= (int)Mask.size())
6373 /// \brief Test whether there are elements crossing 128-bit lanes in this
6376 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6377 /// and we routinely test for these.
6378 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6379 int LaneSize = 128 / VT.getScalarSizeInBits();
6380 int Size = Mask.size();
6381 for (int i = 0; i < Size; ++i)
6382 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6387 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6389 /// This checks a shuffle mask to see if it is performing the same
6390 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6391 /// that it is also not lane-crossing. It may however involve a blend from the
6392 /// same lane of a second vector.
6394 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6395 /// non-trivial to compute in the face of undef lanes. The representation is
6396 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6397 /// entries from both V1 and V2 inputs to the wider mask.
6399 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6400 SmallVectorImpl<int> &RepeatedMask) {
6401 int LaneSize = 128 / VT.getScalarSizeInBits();
6402 RepeatedMask.resize(LaneSize, -1);
6403 int Size = Mask.size();
6404 for (int i = 0; i < Size; ++i) {
6407 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6408 // This entry crosses lanes, so there is no way to model this shuffle.
6411 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6412 if (RepeatedMask[i % LaneSize] == -1)
6413 // This is the first non-undef entry in this slot of a 128-bit lane.
6414 RepeatedMask[i % LaneSize] =
6415 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6416 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6417 // Found a mismatch with the repeated mask.
6423 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6426 /// This is a fast way to test a shuffle mask against a fixed pattern:
6428 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6430 /// It returns true if the mask is exactly as wide as the argument list, and
6431 /// each element of the mask is either -1 (signifying undef) or the value given
6432 /// in the argument.
6433 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6434 ArrayRef<int> ExpectedMask) {
6435 if (Mask.size() != ExpectedMask.size())
6438 int Size = Mask.size();
6440 // If the values are build vectors, we can look through them to find
6441 // equivalent inputs that make the shuffles equivalent.
6442 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6443 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6445 for (int i = 0; i < Size; ++i)
6446 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6447 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6448 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6449 if (!MaskBV || !ExpectedBV ||
6450 MaskBV->getOperand(Mask[i] % Size) !=
6451 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6458 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6460 /// This helper function produces an 8-bit shuffle immediate corresponding to
6461 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6462 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6465 /// NB: We rely heavily on "undef" masks preserving the input lane.
6466 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6467 SelectionDAG &DAG) {
6468 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6469 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6470 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6471 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6472 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6475 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6476 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6477 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6478 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6479 return DAG.getConstant(Imm, DL, MVT::i8);
6482 /// \brief Compute whether each element of a shuffle is zeroable.
6484 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6485 /// Either it is an undef element in the shuffle mask, the element of the input
6486 /// referenced is undef, or the element of the input referenced is known to be
6487 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6488 /// as many lanes with this technique as possible to simplify the remaining
6490 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6491 SDValue V1, SDValue V2) {
6492 SmallBitVector Zeroable(Mask.size(), false);
6494 while (V1.getOpcode() == ISD::BITCAST)
6495 V1 = V1->getOperand(0);
6496 while (V2.getOpcode() == ISD::BITCAST)
6497 V2 = V2->getOperand(0);
6499 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6500 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6502 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6504 // Handle the easy cases.
6505 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6510 // If this is an index into a build_vector node (which has the same number
6511 // of elements), dig out the input value and use it.
6512 SDValue V = M < Size ? V1 : V2;
6513 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6516 SDValue Input = V.getOperand(M % Size);
6517 // The UNDEF opcode check really should be dead code here, but not quite
6518 // worth asserting on (it isn't invalid, just unexpected).
6519 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6526 /// \brief Try to emit a bitmask instruction for a shuffle.
6528 /// This handles cases where we can model a blend exactly as a bitmask due to
6529 /// one of the inputs being zeroable.
6530 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6531 SDValue V2, ArrayRef<int> Mask,
6532 SelectionDAG &DAG) {
6533 MVT EltVT = VT.getScalarType();
6534 int NumEltBits = EltVT.getSizeInBits();
6535 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6536 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6537 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6539 if (EltVT.isFloatingPoint()) {
6540 Zero = DAG.getBitcast(EltVT, Zero);
6541 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6543 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6544 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6546 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6549 if (Mask[i] % Size != i)
6550 return SDValue(); // Not a blend.
6552 V = Mask[i] < Size ? V1 : V2;
6553 else if (V != (Mask[i] < Size ? V1 : V2))
6554 return SDValue(); // Can only let one input through the mask.
6556 VMaskOps[i] = AllOnes;
6559 return SDValue(); // No non-zeroable elements!
6561 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6562 V = DAG.getNode(VT.isFloatingPoint()
6563 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6568 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6570 /// This is used as a fallback approach when first class blend instructions are
6571 /// unavailable. Currently it is only suitable for integer vectors, but could
6572 /// be generalized for floating point vectors if desirable.
6573 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6574 SDValue V2, ArrayRef<int> Mask,
6575 SelectionDAG &DAG) {
6576 assert(VT.isInteger() && "Only supports integer vector types!");
6577 MVT EltVT = VT.getScalarType();
6578 int NumEltBits = EltVT.getSizeInBits();
6579 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6580 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6582 SmallVector<SDValue, 16> MaskOps;
6583 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6584 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6585 return SDValue(); // Shuffled input!
6586 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6589 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6590 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6591 // We have to cast V2 around.
6592 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6593 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6594 DAG.getBitcast(MaskVT, V1Mask),
6595 DAG.getBitcast(MaskVT, V2)));
6596 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6599 /// \brief Try to emit a blend instruction for a shuffle.
6601 /// This doesn't do any checks for the availability of instructions for blending
6602 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6603 /// be matched in the backend with the type given. What it does check for is
6604 /// that the shuffle mask is in fact a blend.
6605 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6606 SDValue V2, ArrayRef<int> Mask,
6607 const X86Subtarget *Subtarget,
6608 SelectionDAG &DAG) {
6609 unsigned BlendMask = 0;
6610 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6611 if (Mask[i] >= Size) {
6612 if (Mask[i] != i + Size)
6613 return SDValue(); // Shuffled V2 input!
6614 BlendMask |= 1u << i;
6617 if (Mask[i] >= 0 && Mask[i] != i)
6618 return SDValue(); // Shuffled V1 input!
6620 switch (VT.SimpleTy) {
6625 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6626 DAG.getConstant(BlendMask, DL, MVT::i8));
6630 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6634 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6635 // that instruction.
6636 if (Subtarget->hasAVX2()) {
6637 // Scale the blend by the number of 32-bit dwords per element.
6638 int Scale = VT.getScalarSizeInBits() / 32;
6640 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6641 if (Mask[i] >= Size)
6642 for (int j = 0; j < Scale; ++j)
6643 BlendMask |= 1u << (i * Scale + j);
6645 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6646 V1 = DAG.getBitcast(BlendVT, V1);
6647 V2 = DAG.getBitcast(BlendVT, V2);
6648 return DAG.getBitcast(
6649 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6650 DAG.getConstant(BlendMask, DL, MVT::i8)));
6654 // For integer shuffles we need to expand the mask and cast the inputs to
6655 // v8i16s prior to blending.
6656 int Scale = 8 / VT.getVectorNumElements();
6658 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6659 if (Mask[i] >= Size)
6660 for (int j = 0; j < Scale; ++j)
6661 BlendMask |= 1u << (i * Scale + j);
6663 V1 = DAG.getBitcast(MVT::v8i16, V1);
6664 V2 = DAG.getBitcast(MVT::v8i16, V2);
6665 return DAG.getBitcast(VT,
6666 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6667 DAG.getConstant(BlendMask, DL, MVT::i8)));
6671 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6672 SmallVector<int, 8> RepeatedMask;
6673 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6674 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6675 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6677 for (int i = 0; i < 8; ++i)
6678 if (RepeatedMask[i] >= 16)
6679 BlendMask |= 1u << i;
6680 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6681 DAG.getConstant(BlendMask, DL, MVT::i8));
6687 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6688 "256-bit byte-blends require AVX2 support!");
6690 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6691 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6694 // Scale the blend by the number of bytes per element.
6695 int Scale = VT.getScalarSizeInBits() / 8;
6697 // This form of blend is always done on bytes. Compute the byte vector
6699 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6701 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6702 // mix of LLVM's code generator and the x86 backend. We tell the code
6703 // generator that boolean values in the elements of an x86 vector register
6704 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6705 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6706 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6707 // of the element (the remaining are ignored) and 0 in that high bit would
6708 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6709 // the LLVM model for boolean values in vector elements gets the relevant
6710 // bit set, it is set backwards and over constrained relative to x86's
6712 SmallVector<SDValue, 32> VSELECTMask;
6713 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6714 for (int j = 0; j < Scale; ++j)
6715 VSELECTMask.push_back(
6716 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6717 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6720 V1 = DAG.getBitcast(BlendVT, V1);
6721 V2 = DAG.getBitcast(BlendVT, V2);
6722 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6723 DAG.getNode(ISD::BUILD_VECTOR, DL,
6724 BlendVT, VSELECTMask),
6729 llvm_unreachable("Not a supported integer vector type!");
6733 /// \brief Try to lower as a blend of elements from two inputs followed by
6734 /// a single-input permutation.
6736 /// This matches the pattern where we can blend elements from two inputs and
6737 /// then reduce the shuffle to a single-input permutation.
6738 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6741 SelectionDAG &DAG) {
6742 // We build up the blend mask while checking whether a blend is a viable way
6743 // to reduce the shuffle.
6744 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6745 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6747 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6751 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6753 if (BlendMask[Mask[i] % Size] == -1)
6754 BlendMask[Mask[i] % Size] = Mask[i];
6755 else if (BlendMask[Mask[i] % Size] != Mask[i])
6756 return SDValue(); // Can't blend in the needed input!
6758 PermuteMask[i] = Mask[i] % Size;
6761 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6762 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6765 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6766 /// blends and permutes.
6768 /// This matches the extremely common pattern for handling combined
6769 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6770 /// operations. It will try to pick the best arrangement of shuffles and
6772 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6776 SelectionDAG &DAG) {
6777 // Shuffle the input elements into the desired positions in V1 and V2 and
6778 // blend them together.
6779 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6780 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6781 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6782 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6783 if (Mask[i] >= 0 && Mask[i] < Size) {
6784 V1Mask[i] = Mask[i];
6786 } else if (Mask[i] >= Size) {
6787 V2Mask[i] = Mask[i] - Size;
6788 BlendMask[i] = i + Size;
6791 // Try to lower with the simpler initial blend strategy unless one of the
6792 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6793 // shuffle may be able to fold with a load or other benefit. However, when
6794 // we'll have to do 2x as many shuffles in order to achieve this, blending
6795 // first is a better strategy.
6796 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6797 if (SDValue BlendPerm =
6798 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6801 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6802 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6803 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6806 /// \brief Try to lower a vector shuffle as a byte rotation.
6808 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6809 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6810 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6811 /// try to generically lower a vector shuffle through such an pattern. It
6812 /// does not check for the profitability of lowering either as PALIGNR or
6813 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6814 /// This matches shuffle vectors that look like:
6816 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6818 /// Essentially it concatenates V1 and V2, shifts right by some number of
6819 /// elements, and takes the low elements as the result. Note that while this is
6820 /// specified as a *right shift* because x86 is little-endian, it is a *left
6821 /// rotate* of the vector lanes.
6822 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6825 const X86Subtarget *Subtarget,
6826 SelectionDAG &DAG) {
6827 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6829 int NumElts = Mask.size();
6830 int NumLanes = VT.getSizeInBits() / 128;
6831 int NumLaneElts = NumElts / NumLanes;
6833 // We need to detect various ways of spelling a rotation:
6834 // [11, 12, 13, 14, 15, 0, 1, 2]
6835 // [-1, 12, 13, 14, -1, -1, 1, -1]
6836 // [-1, -1, -1, -1, -1, -1, 1, 2]
6837 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6838 // [-1, 4, 5, 6, -1, -1, 9, -1]
6839 // [-1, 4, 5, 6, -1, -1, -1, -1]
6842 for (int l = 0; l < NumElts; l += NumLaneElts) {
6843 for (int i = 0; i < NumLaneElts; ++i) {
6844 if (Mask[l + i] == -1)
6846 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6848 // Get the mod-Size index and lane correct it.
6849 int LaneIdx = (Mask[l + i] % NumElts) - l;
6850 // Make sure it was in this lane.
6851 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6854 // Determine where a rotated vector would have started.
6855 int StartIdx = i - LaneIdx;
6857 // The identity rotation isn't interesting, stop.
6860 // If we found the tail of a vector the rotation must be the missing
6861 // front. If we found the head of a vector, it must be how much of the
6863 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6866 Rotation = CandidateRotation;
6867 else if (Rotation != CandidateRotation)
6868 // The rotations don't match, so we can't match this mask.
6871 // Compute which value this mask is pointing at.
6872 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6874 // Compute which of the two target values this index should be assigned
6875 // to. This reflects whether the high elements are remaining or the low
6876 // elements are remaining.
6877 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6879 // Either set up this value if we've not encountered it before, or check
6880 // that it remains consistent.
6883 else if (TargetV != MaskV)
6884 // This may be a rotation, but it pulls from the inputs in some
6885 // unsupported interleaving.
6890 // Check that we successfully analyzed the mask, and normalize the results.
6891 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6892 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6898 // The actual rotate instruction rotates bytes, so we need to scale the
6899 // rotation based on how many bytes are in the vector lane.
6900 int Scale = 16 / NumLaneElts;
6902 // SSSE3 targets can use the palignr instruction.
6903 if (Subtarget->hasSSSE3()) {
6904 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6905 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6906 Lo = DAG.getBitcast(AlignVT, Lo);
6907 Hi = DAG.getBitcast(AlignVT, Hi);
6909 return DAG.getBitcast(
6910 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6911 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6914 assert(VT.getSizeInBits() == 128 &&
6915 "Rotate-based lowering only supports 128-bit lowering!");
6916 assert(Mask.size() <= 16 &&
6917 "Can shuffle at most 16 bytes in a 128-bit vector!");
6919 // Default SSE2 implementation
6920 int LoByteShift = 16 - Rotation * Scale;
6921 int HiByteShift = Rotation * Scale;
6923 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6924 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6925 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6927 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6928 DAG.getConstant(LoByteShift, DL, MVT::i8));
6929 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6930 DAG.getConstant(HiByteShift, DL, MVT::i8));
6931 return DAG.getBitcast(VT,
6932 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6935 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6937 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6938 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6939 /// matches elements from one of the input vectors shuffled to the left or
6940 /// right with zeroable elements 'shifted in'. It handles both the strictly
6941 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6944 /// PSHL : (little-endian) left bit shift.
6945 /// [ zz, 0, zz, 2 ]
6946 /// [ -1, 4, zz, -1 ]
6947 /// PSRL : (little-endian) right bit shift.
6949 /// [ -1, -1, 7, zz]
6950 /// PSLLDQ : (little-endian) left byte shift
6951 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6952 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6953 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6954 /// PSRLDQ : (little-endian) right byte shift
6955 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6956 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6957 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6958 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6959 SDValue V2, ArrayRef<int> Mask,
6960 SelectionDAG &DAG) {
6961 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6963 int Size = Mask.size();
6964 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6966 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6967 for (int i = 0; i < Size; i += Scale)
6968 for (int j = 0; j < Shift; ++j)
6969 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6975 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6976 for (int i = 0; i != Size; i += Scale) {
6977 unsigned Pos = Left ? i + Shift : i;
6978 unsigned Low = Left ? i : i + Shift;
6979 unsigned Len = Scale - Shift;
6980 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6981 Low + (V == V1 ? 0 : Size)))
6985 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6986 bool ByteShift = ShiftEltBits > 64;
6987 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6988 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6989 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6991 // Normalize the scale for byte shifts to still produce an i64 element
6993 Scale = ByteShift ? Scale / 2 : Scale;
6995 // We need to round trip through the appropriate type for the shift.
6996 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6997 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6998 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6999 "Illegal integer vector type");
7000 V = DAG.getBitcast(ShiftVT, V);
7002 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7003 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7004 return DAG.getBitcast(VT, V);
7007 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7008 // keep doubling the size of the integer elements up to that. We can
7009 // then shift the elements of the integer vector by whole multiples of
7010 // their width within the elements of the larger integer vector. Test each
7011 // multiple to see if we can find a match with the moved element indices
7012 // and that the shifted in elements are all zeroable.
7013 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7014 for (int Shift = 1; Shift != Scale; ++Shift)
7015 for (bool Left : {true, false})
7016 if (CheckZeros(Shift, Scale, Left))
7017 for (SDValue V : {V1, V2})
7018 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7025 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7026 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7027 SDValue V2, ArrayRef<int> Mask,
7028 SelectionDAG &DAG) {
7029 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7030 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7032 int Size = Mask.size();
7033 int HalfSize = Size / 2;
7034 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7036 // Upper half must be undefined.
7037 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7040 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7041 // Remainder of lower half result is zero and upper half is all undef.
7042 auto LowerAsEXTRQ = [&]() {
7043 // Determine the extraction length from the part of the
7044 // lower half that isn't zeroable.
7046 for (; Len >= 0; --Len)
7047 if (!Zeroable[Len - 1])
7049 assert(Len > 0 && "Zeroable shuffle mask");
7051 // Attempt to match first Len sequential elements from the lower half.
7054 for (int i = 0; i != Len; ++i) {
7058 SDValue &V = (M < Size ? V1 : V2);
7061 // All mask elements must be in the lower half.
7065 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7076 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7077 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7078 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7079 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7080 DAG.getConstant(BitLen, DL, MVT::i8),
7081 DAG.getConstant(BitIdx, DL, MVT::i8));
7084 if (SDValue ExtrQ = LowerAsEXTRQ())
7087 // INSERTQ: Extract lowest Len elements from lower half of second source and
7088 // insert over first source, starting at Idx.
7089 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7090 auto LowerAsInsertQ = [&]() {
7091 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7094 // Attempt to match first source from mask before insertion point.
7095 if (isUndefInRange(Mask, 0, Idx)) {
7097 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7099 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7105 // Extend the extraction length looking to match both the insertion of
7106 // the second source and the remaining elements of the first.
7107 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7112 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7114 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7120 // Match the remaining elements of the lower half.
7121 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7123 } else if ((!Base || (Base == V1)) &&
7124 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7126 } else if ((!Base || (Base == V2)) &&
7127 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7134 // We may not have a base (first source) - this can safely be undefined.
7136 Base = DAG.getUNDEF(VT);
7138 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7139 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7140 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7141 DAG.getConstant(BitLen, DL, MVT::i8),
7142 DAG.getConstant(BitIdx, DL, MVT::i8));
7149 if (SDValue InsertQ = LowerAsInsertQ())
7155 /// \brief Lower a vector shuffle as a zero or any extension.
7157 /// Given a specific number of elements, element bit width, and extension
7158 /// stride, produce either a zero or any extension based on the available
7159 /// features of the subtarget.
7160 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7161 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
7162 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7163 assert(Scale > 1 && "Need a scale to extend.");
7164 int NumElements = VT.getVectorNumElements();
7165 int EltBits = VT.getScalarSizeInBits();
7166 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7167 "Only 8, 16, and 32 bit elements can be extended.");
7168 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7170 // Found a valid zext mask! Try various lowering strategies based on the
7171 // input type and available ISA extensions.
7172 if (Subtarget->hasSSE41()) {
7173 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7174 NumElements / Scale);
7175 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7178 // For any extends we can cheat for larger element sizes and use shuffle
7179 // instructions that can fold with a load and/or copy.
7180 if (AnyExt && EltBits == 32) {
7181 int PSHUFDMask[4] = {0, -1, 1, -1};
7182 return DAG.getBitcast(
7183 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7184 DAG.getBitcast(MVT::v4i32, InputV),
7185 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7187 if (AnyExt && EltBits == 16 && Scale > 2) {
7188 int PSHUFDMask[4] = {0, -1, 0, -1};
7189 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7190 DAG.getBitcast(MVT::v4i32, InputV),
7191 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7192 int PSHUFHWMask[4] = {1, -1, -1, -1};
7193 return DAG.getBitcast(
7194 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7195 DAG.getBitcast(MVT::v8i16, InputV),
7196 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
7199 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7201 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7202 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7203 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7205 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7206 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7207 DAG.getConstant(EltBits, DL, MVT::i8),
7208 DAG.getConstant(0, DL, MVT::i8)));
7209 if (isUndefInRange(Mask, NumElements/2, NumElements/2))
7210 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7213 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7214 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7215 DAG.getConstant(EltBits, DL, MVT::i8),
7216 DAG.getConstant(EltBits, DL, MVT::i8)));
7217 return DAG.getNode(ISD::BITCAST, DL, VT,
7218 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7221 // If this would require more than 2 unpack instructions to expand, use
7222 // pshufb when available. We can only use more than 2 unpack instructions
7223 // when zero extending i8 elements which also makes it easier to use pshufb.
7224 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7225 assert(NumElements == 16 && "Unexpected byte vector width!");
7226 SDValue PSHUFBMask[16];
7227 for (int i = 0; i < 16; ++i)
7229 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
7230 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7231 return DAG.getBitcast(VT,
7232 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7233 DAG.getNode(ISD::BUILD_VECTOR, DL,
7234 MVT::v16i8, PSHUFBMask)));
7237 // Otherwise emit a sequence of unpacks.
7239 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7240 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7241 : getZeroVector(InputVT, Subtarget, DAG, DL);
7242 InputV = DAG.getBitcast(InputVT, InputV);
7243 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7247 } while (Scale > 1);
7248 return DAG.getBitcast(VT, InputV);
7251 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7253 /// This routine will try to do everything in its power to cleverly lower
7254 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7255 /// check for the profitability of this lowering, it tries to aggressively
7256 /// match this pattern. It will use all of the micro-architectural details it
7257 /// can to emit an efficient lowering. It handles both blends with all-zero
7258 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7259 /// masking out later).
7261 /// The reason we have dedicated lowering for zext-style shuffles is that they
7262 /// are both incredibly common and often quite performance sensitive.
7263 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7264 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7265 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7266 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7268 int Bits = VT.getSizeInBits();
7269 int NumElements = VT.getVectorNumElements();
7270 assert(VT.getScalarSizeInBits() <= 32 &&
7271 "Exceeds 32-bit integer zero extension limit");
7272 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7274 // Define a helper function to check a particular ext-scale and lower to it if
7276 auto Lower = [&](int Scale) -> SDValue {
7279 for (int i = 0; i < NumElements; ++i) {
7281 continue; // Valid anywhere but doesn't tell us anything.
7282 if (i % Scale != 0) {
7283 // Each of the extended elements need to be zeroable.
7287 // We no longer are in the anyext case.
7292 // Each of the base elements needs to be consecutive indices into the
7293 // same input vector.
7294 SDValue V = Mask[i] < NumElements ? V1 : V2;
7297 else if (InputV != V)
7298 return SDValue(); // Flip-flopping inputs.
7300 if (Mask[i] % NumElements != i / Scale)
7301 return SDValue(); // Non-consecutive strided elements.
7304 // If we fail to find an input, we have a zero-shuffle which should always
7305 // have already been handled.
7306 // FIXME: Maybe handle this here in case during blending we end up with one?
7310 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7311 DL, VT, Scale, AnyExt, InputV, Mask, Subtarget, DAG);
7314 // The widest scale possible for extending is to a 64-bit integer.
7315 assert(Bits % 64 == 0 &&
7316 "The number of bits in a vector must be divisible by 64 on x86!");
7317 int NumExtElements = Bits / 64;
7319 // Each iteration, try extending the elements half as much, but into twice as
7321 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7322 assert(NumElements % NumExtElements == 0 &&
7323 "The input vector size must be divisible by the extended size.");
7324 if (SDValue V = Lower(NumElements / NumExtElements))
7328 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7332 // Returns one of the source operands if the shuffle can be reduced to a
7333 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7334 auto CanZExtLowHalf = [&]() {
7335 for (int i = NumElements / 2; i != NumElements; ++i)
7338 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7340 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7345 if (SDValue V = CanZExtLowHalf()) {
7346 V = DAG.getBitcast(MVT::v2i64, V);
7347 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7348 return DAG.getBitcast(VT, V);
7351 // No viable ext lowering found.
7355 /// \brief Try to get a scalar value for a specific element of a vector.
7357 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7358 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7359 SelectionDAG &DAG) {
7360 MVT VT = V.getSimpleValueType();
7361 MVT EltVT = VT.getVectorElementType();
7362 while (V.getOpcode() == ISD::BITCAST)
7363 V = V.getOperand(0);
7364 // If the bitcasts shift the element size, we can't extract an equivalent
7366 MVT NewVT = V.getSimpleValueType();
7367 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7370 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7371 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7372 // Ensure the scalar operand is the same size as the destination.
7373 // FIXME: Add support for scalar truncation where possible.
7374 SDValue S = V.getOperand(Idx);
7375 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7376 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7382 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7384 /// This is particularly important because the set of instructions varies
7385 /// significantly based on whether the operand is a load or not.
7386 static bool isShuffleFoldableLoad(SDValue V) {
7387 while (V.getOpcode() == ISD::BITCAST)
7388 V = V.getOperand(0);
7390 return ISD::isNON_EXTLoad(V.getNode());
7393 /// \brief Try to lower insertion of a single element into a zero vector.
7395 /// This is a common pattern that we have especially efficient patterns to lower
7396 /// across all subtarget feature sets.
7397 static SDValue lowerVectorShuffleAsElementInsertion(
7398 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7399 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7400 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7402 MVT EltVT = VT.getVectorElementType();
7404 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7405 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7407 bool IsV1Zeroable = true;
7408 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7409 if (i != V2Index && !Zeroable[i]) {
7410 IsV1Zeroable = false;
7414 // Check for a single input from a SCALAR_TO_VECTOR node.
7415 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7416 // all the smarts here sunk into that routine. However, the current
7417 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7418 // vector shuffle lowering is dead.
7419 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7421 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7422 // We need to zext the scalar if it is smaller than an i32.
7423 V2S = DAG.getBitcast(EltVT, V2S);
7424 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7425 // Using zext to expand a narrow element won't work for non-zero
7430 // Zero-extend directly to i32.
7432 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7434 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7435 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7436 EltVT == MVT::i16) {
7437 // Either not inserting from the low element of the input or the input
7438 // element size is too small to use VZEXT_MOVL to clear the high bits.
7442 if (!IsV1Zeroable) {
7443 // If V1 can't be treated as a zero vector we have fewer options to lower
7444 // this. We can't support integer vectors or non-zero targets cheaply, and
7445 // the V1 elements can't be permuted in any way.
7446 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7447 if (!VT.isFloatingPoint() || V2Index != 0)
7449 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7450 V1Mask[V2Index] = -1;
7451 if (!isNoopShuffleMask(V1Mask))
7453 // This is essentially a special case blend operation, but if we have
7454 // general purpose blend operations, they are always faster. Bail and let
7455 // the rest of the lowering handle these as blends.
7456 if (Subtarget->hasSSE41())
7459 // Otherwise, use MOVSD or MOVSS.
7460 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7461 "Only two types of floating point element types to handle!");
7462 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7466 // This lowering only works for the low element with floating point vectors.
7467 if (VT.isFloatingPoint() && V2Index != 0)
7470 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7472 V2 = DAG.getBitcast(VT, V2);
7475 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7476 // the desired position. Otherwise it is more efficient to do a vector
7477 // shift left. We know that we can do a vector shift left because all
7478 // the inputs are zero.
7479 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7480 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7481 V2Shuffle[V2Index] = 0;
7482 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7484 V2 = DAG.getBitcast(MVT::v2i64, V2);
7486 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7487 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7488 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7489 DAG.getDataLayout(), VT)));
7490 V2 = DAG.getBitcast(VT, V2);
7496 /// \brief Try to lower broadcast of a single element.
7498 /// For convenience, this code also bundles all of the subtarget feature set
7499 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7500 /// a convenient way to factor it out.
7501 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7503 const X86Subtarget *Subtarget,
7504 SelectionDAG &DAG) {
7505 if (!Subtarget->hasAVX())
7507 if (VT.isInteger() && !Subtarget->hasAVX2())
7510 // Check that the mask is a broadcast.
7511 int BroadcastIdx = -1;
7513 if (M >= 0 && BroadcastIdx == -1)
7515 else if (M >= 0 && M != BroadcastIdx)
7518 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7519 "a sorted mask where the broadcast "
7522 // Go up the chain of (vector) values to find a scalar load that we can
7523 // combine with the broadcast.
7525 switch (V.getOpcode()) {
7526 case ISD::CONCAT_VECTORS: {
7527 int OperandSize = Mask.size() / V.getNumOperands();
7528 V = V.getOperand(BroadcastIdx / OperandSize);
7529 BroadcastIdx %= OperandSize;
7533 case ISD::INSERT_SUBVECTOR: {
7534 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7535 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7539 int BeginIdx = (int)ConstantIdx->getZExtValue();
7541 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7542 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7543 BroadcastIdx -= BeginIdx;
7554 // Check if this is a broadcast of a scalar. We special case lowering
7555 // for scalars so that we can more effectively fold with loads.
7556 // First, look through bitcast: if the original value has a larger element
7557 // type than the shuffle, the broadcast element is in essence truncated.
7558 // Make that explicit to ease folding.
7559 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7560 EVT EltVT = VT.getVectorElementType();
7561 SDValue V0 = V.getOperand(0);
7562 EVT V0VT = V0.getValueType();
7564 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7565 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7566 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7567 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7572 // Also check the simpler case, where we can directly reuse the scalar.
7573 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7574 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7575 V = V.getOperand(BroadcastIdx);
7577 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7578 // Only AVX2 has register broadcasts.
7579 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7581 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7582 // We can't broadcast from a vector register without AVX2, and we can only
7583 // broadcast from the zero-element of a vector register.
7587 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7590 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7591 // INSERTPS when the V1 elements are already in the correct locations
7592 // because otherwise we can just always use two SHUFPS instructions which
7593 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7594 // perform INSERTPS if a single V1 element is out of place and all V2
7595 // elements are zeroable.
7596 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7598 SelectionDAG &DAG) {
7599 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7600 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7601 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7602 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7604 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7607 int V1DstIndex = -1;
7608 int V2DstIndex = -1;
7609 bool V1UsedInPlace = false;
7611 for (int i = 0; i < 4; ++i) {
7612 // Synthesize a zero mask from the zeroable elements (includes undefs).
7618 // Flag if we use any V1 inputs in place.
7620 V1UsedInPlace = true;
7624 // We can only insert a single non-zeroable element.
7625 if (V1DstIndex != -1 || V2DstIndex != -1)
7629 // V1 input out of place for insertion.
7632 // V2 input for insertion.
7637 // Don't bother if we have no (non-zeroable) element for insertion.
7638 if (V1DstIndex == -1 && V2DstIndex == -1)
7641 // Determine element insertion src/dst indices. The src index is from the
7642 // start of the inserted vector, not the start of the concatenated vector.
7643 unsigned V2SrcIndex = 0;
7644 if (V1DstIndex != -1) {
7645 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7646 // and don't use the original V2 at all.
7647 V2SrcIndex = Mask[V1DstIndex];
7648 V2DstIndex = V1DstIndex;
7651 V2SrcIndex = Mask[V2DstIndex] - 4;
7654 // If no V1 inputs are used in place, then the result is created only from
7655 // the zero mask and the V2 insertion - so remove V1 dependency.
7657 V1 = DAG.getUNDEF(MVT::v4f32);
7659 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7660 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7662 // Insert the V2 element into the desired position.
7664 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7665 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7668 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7669 /// UNPCK instruction.
7671 /// This specifically targets cases where we end up with alternating between
7672 /// the two inputs, and so can permute them into something that feeds a single
7673 /// UNPCK instruction. Note that this routine only targets integer vectors
7674 /// because for floating point vectors we have a generalized SHUFPS lowering
7675 /// strategy that handles everything that doesn't *exactly* match an unpack,
7676 /// making this clever lowering unnecessary.
7677 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7678 SDValue V2, ArrayRef<int> Mask,
7679 SelectionDAG &DAG) {
7680 assert(!VT.isFloatingPoint() &&
7681 "This routine only supports integer vectors.");
7682 assert(!isSingleInputShuffleMask(Mask) &&
7683 "This routine should only be used when blending two inputs.");
7684 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7686 int Size = Mask.size();
7688 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7689 return M >= 0 && M % Size < Size / 2;
7691 int NumHiInputs = std::count_if(
7692 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7694 bool UnpackLo = NumLoInputs >= NumHiInputs;
7696 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7697 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7698 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7700 for (int i = 0; i < Size; ++i) {
7704 // Each element of the unpack contains Scale elements from this mask.
7705 int UnpackIdx = i / Scale;
7707 // We only handle the case where V1 feeds the first slots of the unpack.
7708 // We rely on canonicalization to ensure this is the case.
7709 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7712 // Setup the mask for this input. The indexing is tricky as we have to
7713 // handle the unpack stride.
7714 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7715 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7719 // If we will have to shuffle both inputs to use the unpack, check whether
7720 // we can just unpack first and shuffle the result. If so, skip this unpack.
7721 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7722 !isNoopShuffleMask(V2Mask))
7725 // Shuffle the inputs into place.
7726 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7727 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7729 // Cast the inputs to the type we will use to unpack them.
7730 V1 = DAG.getBitcast(UnpackVT, V1);
7731 V2 = DAG.getBitcast(UnpackVT, V2);
7733 // Unpack the inputs and cast the result back to the desired type.
7734 return DAG.getBitcast(
7735 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7739 // We try each unpack from the largest to the smallest to try and find one
7740 // that fits this mask.
7741 int OrigNumElements = VT.getVectorNumElements();
7742 int OrigScalarSize = VT.getScalarSizeInBits();
7743 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7744 int Scale = ScalarSize / OrigScalarSize;
7745 int NumElements = OrigNumElements / Scale;
7746 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7747 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7751 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7753 if (NumLoInputs == 0 || NumHiInputs == 0) {
7754 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7755 "We have to have *some* inputs!");
7756 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7758 // FIXME: We could consider the total complexity of the permute of each
7759 // possible unpacking. Or at the least we should consider how many
7760 // half-crossings are created.
7761 // FIXME: We could consider commuting the unpacks.
7763 SmallVector<int, 32> PermMask;
7764 PermMask.assign(Size, -1);
7765 for (int i = 0; i < Size; ++i) {
7769 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7772 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7774 return DAG.getVectorShuffle(
7775 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7777 DAG.getUNDEF(VT), PermMask);
7783 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7785 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7786 /// support for floating point shuffles but not integer shuffles. These
7787 /// instructions will incur a domain crossing penalty on some chips though so
7788 /// it is better to avoid lowering through this for integer vectors where
7790 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7791 const X86Subtarget *Subtarget,
7792 SelectionDAG &DAG) {
7794 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7795 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7796 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7797 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7798 ArrayRef<int> Mask = SVOp->getMask();
7799 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7801 if (isSingleInputShuffleMask(Mask)) {
7802 // Use low duplicate instructions for masks that match their pattern.
7803 if (Subtarget->hasSSE3())
7804 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7805 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7807 // Straight shuffle of a single input vector. Simulate this by using the
7808 // single input as both of the "inputs" to this instruction..
7809 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7811 if (Subtarget->hasAVX()) {
7812 // If we have AVX, we can use VPERMILPS which will allow folding a load
7813 // into the shuffle.
7814 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7815 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7818 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7819 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7821 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7822 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7824 // If we have a single input, insert that into V1 if we can do so cheaply.
7825 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7826 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7827 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7829 // Try inverting the insertion since for v2 masks it is easy to do and we
7830 // can't reliably sort the mask one way or the other.
7831 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7832 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7833 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7834 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7838 // Try to use one of the special instruction patterns to handle two common
7839 // blend patterns if a zero-blend above didn't work.
7840 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7841 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7842 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7843 // We can either use a special instruction to load over the low double or
7844 // to move just the low double.
7846 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7848 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7850 if (Subtarget->hasSSE41())
7851 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7855 // Use dedicated unpack instructions for masks that match their pattern.
7856 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7857 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7858 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7859 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7861 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7862 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7863 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7866 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7868 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7869 /// the integer unit to minimize domain crossing penalties. However, for blends
7870 /// it falls back to the floating point shuffle operation with appropriate bit
7872 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7873 const X86Subtarget *Subtarget,
7874 SelectionDAG &DAG) {
7876 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7877 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7878 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7879 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7880 ArrayRef<int> Mask = SVOp->getMask();
7881 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7883 if (isSingleInputShuffleMask(Mask)) {
7884 // Check for being able to broadcast a single element.
7885 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7886 Mask, Subtarget, DAG))
7889 // Straight shuffle of a single input vector. For everything from SSE2
7890 // onward this has a single fast instruction with no scary immediates.
7891 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7892 V1 = DAG.getBitcast(MVT::v4i32, V1);
7893 int WidenedMask[4] = {
7894 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7895 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7896 return DAG.getBitcast(
7898 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7899 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7901 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7902 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7903 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7904 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7906 // If we have a blend of two PACKUS operations an the blend aligns with the
7907 // low and half halves, we can just merge the PACKUS operations. This is
7908 // particularly important as it lets us merge shuffles that this routine itself
7910 auto GetPackNode = [](SDValue V) {
7911 while (V.getOpcode() == ISD::BITCAST)
7912 V = V.getOperand(0);
7914 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7916 if (SDValue V1Pack = GetPackNode(V1))
7917 if (SDValue V2Pack = GetPackNode(V2))
7918 return DAG.getBitcast(MVT::v2i64,
7919 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7920 Mask[0] == 0 ? V1Pack.getOperand(0)
7921 : V1Pack.getOperand(1),
7922 Mask[1] == 2 ? V2Pack.getOperand(0)
7923 : V2Pack.getOperand(1)));
7925 // Try to use shift instructions.
7927 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7930 // When loading a scalar and then shuffling it into a vector we can often do
7931 // the insertion cheaply.
7932 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7933 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7935 // Try inverting the insertion since for v2 masks it is easy to do and we
7936 // can't reliably sort the mask one way or the other.
7937 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7938 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7939 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7942 // We have different paths for blend lowering, but they all must use the
7943 // *exact* same predicate.
7944 bool IsBlendSupported = Subtarget->hasSSE41();
7945 if (IsBlendSupported)
7946 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7950 // Use dedicated unpack instructions for masks that match their pattern.
7951 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7952 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7953 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7954 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7956 // Try to use byte rotation instructions.
7957 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7958 if (Subtarget->hasSSSE3())
7959 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7960 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7963 // If we have direct support for blends, we should lower by decomposing into
7964 // a permute. That will be faster than the domain cross.
7965 if (IsBlendSupported)
7966 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7969 // We implement this with SHUFPD which is pretty lame because it will likely
7970 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7971 // However, all the alternatives are still more cycles and newer chips don't
7972 // have this problem. It would be really nice if x86 had better shuffles here.
7973 V1 = DAG.getBitcast(MVT::v2f64, V1);
7974 V2 = DAG.getBitcast(MVT::v2f64, V2);
7975 return DAG.getBitcast(MVT::v2i64,
7976 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7979 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7981 /// This is used to disable more specialized lowerings when the shufps lowering
7982 /// will happen to be efficient.
7983 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7984 // This routine only handles 128-bit shufps.
7985 assert(Mask.size() == 4 && "Unsupported mask size!");
7987 // To lower with a single SHUFPS we need to have the low half and high half
7988 // each requiring a single input.
7989 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7991 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7997 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7999 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8000 /// It makes no assumptions about whether this is the *best* lowering, it simply
8002 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8003 ArrayRef<int> Mask, SDValue V1,
8004 SDValue V2, SelectionDAG &DAG) {
8005 SDValue LowV = V1, HighV = V2;
8006 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8009 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8011 if (NumV2Elements == 1) {
8013 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8016 // Compute the index adjacent to V2Index and in the same half by toggling
8018 int V2AdjIndex = V2Index ^ 1;
8020 if (Mask[V2AdjIndex] == -1) {
8021 // Handles all the cases where we have a single V2 element and an undef.
8022 // This will only ever happen in the high lanes because we commute the
8023 // vector otherwise.
8025 std::swap(LowV, HighV);
8026 NewMask[V2Index] -= 4;
8028 // Handle the case where the V2 element ends up adjacent to a V1 element.
8029 // To make this work, blend them together as the first step.
8030 int V1Index = V2AdjIndex;
8031 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8032 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8033 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8035 // Now proceed to reconstruct the final blend as we have the necessary
8036 // high or low half formed.
8043 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8044 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8046 } else if (NumV2Elements == 2) {
8047 if (Mask[0] < 4 && Mask[1] < 4) {
8048 // Handle the easy case where we have V1 in the low lanes and V2 in the
8052 } else if (Mask[2] < 4 && Mask[3] < 4) {
8053 // We also handle the reversed case because this utility may get called
8054 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8055 // arrange things in the right direction.
8061 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8062 // trying to place elements directly, just blend them and set up the final
8063 // shuffle to place them.
8065 // The first two blend mask elements are for V1, the second two are for
8067 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8068 Mask[2] < 4 ? Mask[2] : Mask[3],
8069 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8070 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8071 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8072 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8074 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8077 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8078 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8079 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8080 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8083 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8084 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8087 /// \brief Lower 4-lane 32-bit floating point shuffles.
8089 /// Uses instructions exclusively from the floating point unit to minimize
8090 /// domain crossing penalties, as these are sufficient to implement all v4f32
8092 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8093 const X86Subtarget *Subtarget,
8094 SelectionDAG &DAG) {
8096 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8097 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8098 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8099 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8100 ArrayRef<int> Mask = SVOp->getMask();
8101 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8104 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8106 if (NumV2Elements == 0) {
8107 // Check for being able to broadcast a single element.
8108 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8109 Mask, Subtarget, DAG))
8112 // Use even/odd duplicate instructions for masks that match their pattern.
8113 if (Subtarget->hasSSE3()) {
8114 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8115 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8116 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8117 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8120 if (Subtarget->hasAVX()) {
8121 // If we have AVX, we can use VPERMILPS which will allow folding a load
8122 // into the shuffle.
8123 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8124 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8127 // Otherwise, use a straight shuffle of a single input vector. We pass the
8128 // input vector to both operands to simulate this with a SHUFPS.
8129 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8130 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8133 // There are special ways we can lower some single-element blends. However, we
8134 // have custom ways we can lower more complex single-element blends below that
8135 // we defer to if both this and BLENDPS fail to match, so restrict this to
8136 // when the V2 input is targeting element 0 of the mask -- that is the fast
8138 if (NumV2Elements == 1 && Mask[0] >= 4)
8139 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8140 Mask, Subtarget, DAG))
8143 if (Subtarget->hasSSE41()) {
8144 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8148 // Use INSERTPS if we can complete the shuffle efficiently.
8149 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8152 if (!isSingleSHUFPSMask(Mask))
8153 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8154 DL, MVT::v4f32, V1, V2, Mask, DAG))
8158 // Use dedicated unpack instructions for masks that match their pattern.
8159 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8160 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8161 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8162 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8163 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8164 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8165 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8166 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8168 // Otherwise fall back to a SHUFPS lowering strategy.
8169 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8172 /// \brief Lower 4-lane i32 vector shuffles.
8174 /// We try to handle these with integer-domain shuffles where we can, but for
8175 /// blends we use the floating point domain blend instructions.
8176 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8177 const X86Subtarget *Subtarget,
8178 SelectionDAG &DAG) {
8180 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8181 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8182 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8184 ArrayRef<int> Mask = SVOp->getMask();
8185 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8187 // Whenever we can lower this as a zext, that instruction is strictly faster
8188 // than any alternative. It also allows us to fold memory operands into the
8189 // shuffle in many cases.
8190 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8191 Mask, Subtarget, DAG))
8195 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8197 if (NumV2Elements == 0) {
8198 // Check for being able to broadcast a single element.
8199 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8200 Mask, Subtarget, DAG))
8203 // Straight shuffle of a single input vector. For everything from SSE2
8204 // onward this has a single fast instruction with no scary immediates.
8205 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8206 // but we aren't actually going to use the UNPCK instruction because doing
8207 // so prevents folding a load into this instruction or making a copy.
8208 const int UnpackLoMask[] = {0, 0, 1, 1};
8209 const int UnpackHiMask[] = {2, 2, 3, 3};
8210 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8211 Mask = UnpackLoMask;
8212 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8213 Mask = UnpackHiMask;
8215 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8216 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8219 // Try to use shift instructions.
8221 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8224 // There are special ways we can lower some single-element blends.
8225 if (NumV2Elements == 1)
8226 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8227 Mask, Subtarget, DAG))
8230 // We have different paths for blend lowering, but they all must use the
8231 // *exact* same predicate.
8232 bool IsBlendSupported = Subtarget->hasSSE41();
8233 if (IsBlendSupported)
8234 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8238 if (SDValue Masked =
8239 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8242 // Use dedicated unpack instructions for masks that match their pattern.
8243 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8244 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8245 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8246 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8247 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8248 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8249 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8250 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8252 // Try to use byte rotation instructions.
8253 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8254 if (Subtarget->hasSSSE3())
8255 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8256 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8259 // If we have direct support for blends, we should lower by decomposing into
8260 // a permute. That will be faster than the domain cross.
8261 if (IsBlendSupported)
8262 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8265 // Try to lower by permuting the inputs into an unpack instruction.
8266 if (SDValue Unpack =
8267 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
8270 // We implement this with SHUFPS because it can blend from two vectors.
8271 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8272 // up the inputs, bypassing domain shift penalties that we would encur if we
8273 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8275 return DAG.getBitcast(
8277 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8278 DAG.getBitcast(MVT::v4f32, V2), Mask));
8281 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8282 /// shuffle lowering, and the most complex part.
8284 /// The lowering strategy is to try to form pairs of input lanes which are
8285 /// targeted at the same half of the final vector, and then use a dword shuffle
8286 /// to place them onto the right half, and finally unpack the paired lanes into
8287 /// their final position.
8289 /// The exact breakdown of how to form these dword pairs and align them on the
8290 /// correct sides is really tricky. See the comments within the function for
8291 /// more of the details.
8293 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8294 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8295 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8296 /// vector, form the analogous 128-bit 8-element Mask.
8297 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8298 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8299 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8300 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8301 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8303 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8304 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8305 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8307 SmallVector<int, 4> LoInputs;
8308 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8309 [](int M) { return M >= 0; });
8310 std::sort(LoInputs.begin(), LoInputs.end());
8311 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8312 SmallVector<int, 4> HiInputs;
8313 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8314 [](int M) { return M >= 0; });
8315 std::sort(HiInputs.begin(), HiInputs.end());
8316 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8318 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8319 int NumHToL = LoInputs.size() - NumLToL;
8321 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8322 int NumHToH = HiInputs.size() - NumLToH;
8323 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8324 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8325 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8326 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8328 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8329 // such inputs we can swap two of the dwords across the half mark and end up
8330 // with <=2 inputs to each half in each half. Once there, we can fall through
8331 // to the generic code below. For example:
8333 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8334 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8336 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8337 // and an existing 2-into-2 on the other half. In this case we may have to
8338 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8339 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8340 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8341 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8342 // half than the one we target for fixing) will be fixed when we re-enter this
8343 // path. We will also combine away any sequence of PSHUFD instructions that
8344 // result into a single instruction. Here is an example of the tricky case:
8346 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8347 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8349 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8351 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8352 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8354 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8355 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8357 // The result is fine to be handled by the generic logic.
8358 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8359 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8360 int AOffset, int BOffset) {
8361 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8362 "Must call this with A having 3 or 1 inputs from the A half.");
8363 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8364 "Must call this with B having 1 or 3 inputs from the B half.");
8365 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8366 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8368 bool ThreeAInputs = AToAInputs.size() == 3;
8370 // Compute the index of dword with only one word among the three inputs in
8371 // a half by taking the sum of the half with three inputs and subtracting
8372 // the sum of the actual three inputs. The difference is the remaining
8375 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8376 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8377 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8378 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8379 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8380 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8381 int TripleNonInputIdx =
8382 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8383 TripleDWord = TripleNonInputIdx / 2;
8385 // We use xor with one to compute the adjacent DWord to whichever one the
8387 OneInputDWord = (OneInput / 2) ^ 1;
8389 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8390 // and BToA inputs. If there is also such a problem with the BToB and AToB
8391 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8392 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8393 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8394 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8395 // Compute how many inputs will be flipped by swapping these DWords. We
8397 // to balance this to ensure we don't form a 3-1 shuffle in the other
8399 int NumFlippedAToBInputs =
8400 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8401 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8402 int NumFlippedBToBInputs =
8403 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8404 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8405 if ((NumFlippedAToBInputs == 1 &&
8406 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8407 (NumFlippedBToBInputs == 1 &&
8408 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8409 // We choose whether to fix the A half or B half based on whether that
8410 // half has zero flipped inputs. At zero, we may not be able to fix it
8411 // with that half. We also bias towards fixing the B half because that
8412 // will more commonly be the high half, and we have to bias one way.
8413 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8414 ArrayRef<int> Inputs) {
8415 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8416 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8417 PinnedIdx ^ 1) != Inputs.end();
8418 // Determine whether the free index is in the flipped dword or the
8419 // unflipped dword based on where the pinned index is. We use this bit
8420 // in an xor to conditionally select the adjacent dword.
8421 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8422 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8423 FixFreeIdx) != Inputs.end();
8424 if (IsFixIdxInput == IsFixFreeIdxInput)
8426 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8427 FixFreeIdx) != Inputs.end();
8428 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8429 "We need to be changing the number of flipped inputs!");
8430 int PSHUFHalfMask[] = {0, 1, 2, 3};
8431 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8432 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8434 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8437 if (M != -1 && M == FixIdx)
8439 else if (M != -1 && M == FixFreeIdx)
8442 if (NumFlippedBToBInputs != 0) {
8444 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8445 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8447 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8448 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8449 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8454 int PSHUFDMask[] = {0, 1, 2, 3};
8455 PSHUFDMask[ADWord] = BDWord;
8456 PSHUFDMask[BDWord] = ADWord;
8459 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8460 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8462 // Adjust the mask to match the new locations of A and B.
8464 if (M != -1 && M/2 == ADWord)
8465 M = 2 * BDWord + M % 2;
8466 else if (M != -1 && M/2 == BDWord)
8467 M = 2 * ADWord + M % 2;
8469 // Recurse back into this routine to re-compute state now that this isn't
8470 // a 3 and 1 problem.
8471 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8474 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8475 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8476 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8477 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8479 // At this point there are at most two inputs to the low and high halves from
8480 // each half. That means the inputs can always be grouped into dwords and
8481 // those dwords can then be moved to the correct half with a dword shuffle.
8482 // We use at most one low and one high word shuffle to collect these paired
8483 // inputs into dwords, and finally a dword shuffle to place them.
8484 int PSHUFLMask[4] = {-1, -1, -1, -1};
8485 int PSHUFHMask[4] = {-1, -1, -1, -1};
8486 int PSHUFDMask[4] = {-1, -1, -1, -1};
8488 // First fix the masks for all the inputs that are staying in their
8489 // original halves. This will then dictate the targets of the cross-half
8491 auto fixInPlaceInputs =
8492 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8493 MutableArrayRef<int> SourceHalfMask,
8494 MutableArrayRef<int> HalfMask, int HalfOffset) {
8495 if (InPlaceInputs.empty())
8497 if (InPlaceInputs.size() == 1) {
8498 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8499 InPlaceInputs[0] - HalfOffset;
8500 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8503 if (IncomingInputs.empty()) {
8504 // Just fix all of the in place inputs.
8505 for (int Input : InPlaceInputs) {
8506 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8507 PSHUFDMask[Input / 2] = Input / 2;
8512 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8513 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8514 InPlaceInputs[0] - HalfOffset;
8515 // Put the second input next to the first so that they are packed into
8516 // a dword. We find the adjacent index by toggling the low bit.
8517 int AdjIndex = InPlaceInputs[0] ^ 1;
8518 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8519 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8520 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8522 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8523 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8525 // Now gather the cross-half inputs and place them into a free dword of
8526 // their target half.
8527 // FIXME: This operation could almost certainly be simplified dramatically to
8528 // look more like the 3-1 fixing operation.
8529 auto moveInputsToRightHalf = [&PSHUFDMask](
8530 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8531 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8532 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8534 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8535 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8537 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8539 int LowWord = Word & ~1;
8540 int HighWord = Word | 1;
8541 return isWordClobbered(SourceHalfMask, LowWord) ||
8542 isWordClobbered(SourceHalfMask, HighWord);
8545 if (IncomingInputs.empty())
8548 if (ExistingInputs.empty()) {
8549 // Map any dwords with inputs from them into the right half.
8550 for (int Input : IncomingInputs) {
8551 // If the source half mask maps over the inputs, turn those into
8552 // swaps and use the swapped lane.
8553 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8554 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8555 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8556 Input - SourceOffset;
8557 // We have to swap the uses in our half mask in one sweep.
8558 for (int &M : HalfMask)
8559 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8561 else if (M == Input)
8562 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8564 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8565 Input - SourceOffset &&
8566 "Previous placement doesn't match!");
8568 // Note that this correctly re-maps both when we do a swap and when
8569 // we observe the other side of the swap above. We rely on that to
8570 // avoid swapping the members of the input list directly.
8571 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8574 // Map the input's dword into the correct half.
8575 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8576 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8578 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8580 "Previous placement doesn't match!");
8583 // And just directly shift any other-half mask elements to be same-half
8584 // as we will have mirrored the dword containing the element into the
8585 // same position within that half.
8586 for (int &M : HalfMask)
8587 if (M >= SourceOffset && M < SourceOffset + 4) {
8588 M = M - SourceOffset + DestOffset;
8589 assert(M >= 0 && "This should never wrap below zero!");
8594 // Ensure we have the input in a viable dword of its current half. This
8595 // is particularly tricky because the original position may be clobbered
8596 // by inputs being moved and *staying* in that half.
8597 if (IncomingInputs.size() == 1) {
8598 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8599 int InputFixed = std::find(std::begin(SourceHalfMask),
8600 std::end(SourceHalfMask), -1) -
8601 std::begin(SourceHalfMask) + SourceOffset;
8602 SourceHalfMask[InputFixed - SourceOffset] =
8603 IncomingInputs[0] - SourceOffset;
8604 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8606 IncomingInputs[0] = InputFixed;
8608 } else if (IncomingInputs.size() == 2) {
8609 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8610 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8611 // We have two non-adjacent or clobbered inputs we need to extract from
8612 // the source half. To do this, we need to map them into some adjacent
8613 // dword slot in the source mask.
8614 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8615 IncomingInputs[1] - SourceOffset};
8617 // If there is a free slot in the source half mask adjacent to one of
8618 // the inputs, place the other input in it. We use (Index XOR 1) to
8619 // compute an adjacent index.
8620 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8621 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8622 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8623 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8624 InputsFixed[1] = InputsFixed[0] ^ 1;
8625 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8626 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8627 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8628 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8629 InputsFixed[0] = InputsFixed[1] ^ 1;
8630 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8631 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8632 // The two inputs are in the same DWord but it is clobbered and the
8633 // adjacent DWord isn't used at all. Move both inputs to the free
8635 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8636 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8637 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8638 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8640 // The only way we hit this point is if there is no clobbering
8641 // (because there are no off-half inputs to this half) and there is no
8642 // free slot adjacent to one of the inputs. In this case, we have to
8643 // swap an input with a non-input.
8644 for (int i = 0; i < 4; ++i)
8645 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8646 "We can't handle any clobbers here!");
8647 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8648 "Cannot have adjacent inputs here!");
8650 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8651 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8653 // We also have to update the final source mask in this case because
8654 // it may need to undo the above swap.
8655 for (int &M : FinalSourceHalfMask)
8656 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8657 M = InputsFixed[1] + SourceOffset;
8658 else if (M == InputsFixed[1] + SourceOffset)
8659 M = (InputsFixed[0] ^ 1) + SourceOffset;
8661 InputsFixed[1] = InputsFixed[0] ^ 1;
8664 // Point everything at the fixed inputs.
8665 for (int &M : HalfMask)
8666 if (M == IncomingInputs[0])
8667 M = InputsFixed[0] + SourceOffset;
8668 else if (M == IncomingInputs[1])
8669 M = InputsFixed[1] + SourceOffset;
8671 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8672 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8675 llvm_unreachable("Unhandled input size!");
8678 // Now hoist the DWord down to the right half.
8679 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8680 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8681 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8682 for (int &M : HalfMask)
8683 for (int Input : IncomingInputs)
8685 M = FreeDWord * 2 + Input % 2;
8687 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8688 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8689 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8690 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8692 // Now enact all the shuffles we've computed to move the inputs into their
8694 if (!isNoopShuffleMask(PSHUFLMask))
8695 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8696 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8697 if (!isNoopShuffleMask(PSHUFHMask))
8698 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8699 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8700 if (!isNoopShuffleMask(PSHUFDMask))
8703 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8704 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8706 // At this point, each half should contain all its inputs, and we can then
8707 // just shuffle them into their final position.
8708 assert(std::count_if(LoMask.begin(), LoMask.end(),
8709 [](int M) { return M >= 4; }) == 0 &&
8710 "Failed to lift all the high half inputs to the low mask!");
8711 assert(std::count_if(HiMask.begin(), HiMask.end(),
8712 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8713 "Failed to lift all the low half inputs to the high mask!");
8715 // Do a half shuffle for the low mask.
8716 if (!isNoopShuffleMask(LoMask))
8717 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8718 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8720 // Do a half shuffle with the high mask after shifting its values down.
8721 for (int &M : HiMask)
8724 if (!isNoopShuffleMask(HiMask))
8725 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8726 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8731 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8732 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8733 SDValue V2, ArrayRef<int> Mask,
8734 SelectionDAG &DAG, bool &V1InUse,
8736 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8742 int Size = Mask.size();
8743 int Scale = 16 / Size;
8744 for (int i = 0; i < 16; ++i) {
8745 if (Mask[i / Scale] == -1) {
8746 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8748 const int ZeroMask = 0x80;
8749 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8751 int V2Idx = Mask[i / Scale] < Size
8753 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8754 if (Zeroable[i / Scale])
8755 V1Idx = V2Idx = ZeroMask;
8756 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8757 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8758 V1InUse |= (ZeroMask != V1Idx);
8759 V2InUse |= (ZeroMask != V2Idx);
8764 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8765 DAG.getBitcast(MVT::v16i8, V1),
8766 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8768 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8769 DAG.getBitcast(MVT::v16i8, V2),
8770 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8772 // If we need shuffled inputs from both, blend the two.
8774 if (V1InUse && V2InUse)
8775 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8777 V = V1InUse ? V1 : V2;
8779 // Cast the result back to the correct type.
8780 return DAG.getBitcast(VT, V);
8783 /// \brief Generic lowering of 8-lane i16 shuffles.
8785 /// This handles both single-input shuffles and combined shuffle/blends with
8786 /// two inputs. The single input shuffles are immediately delegated to
8787 /// a dedicated lowering routine.
8789 /// The blends are lowered in one of three fundamental ways. If there are few
8790 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8791 /// of the input is significantly cheaper when lowered as an interleaving of
8792 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8793 /// halves of the inputs separately (making them have relatively few inputs)
8794 /// and then concatenate them.
8795 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8796 const X86Subtarget *Subtarget,
8797 SelectionDAG &DAG) {
8799 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8800 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8801 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8802 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8803 ArrayRef<int> OrigMask = SVOp->getMask();
8804 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8805 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8806 MutableArrayRef<int> Mask(MaskStorage);
8808 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8810 // Whenever we can lower this as a zext, that instruction is strictly faster
8811 // than any alternative.
8812 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8813 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8816 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8818 auto isV2 = [](int M) { return M >= 8; };
8820 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8822 if (NumV2Inputs == 0) {
8823 // Check for being able to broadcast a single element.
8824 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8825 Mask, Subtarget, DAG))
8828 // Try to use shift instructions.
8830 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8833 // Use dedicated unpack instructions for masks that match their pattern.
8834 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8835 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8836 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8837 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8839 // Try to use byte rotation instructions.
8840 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8841 Mask, Subtarget, DAG))
8844 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8848 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8849 "All single-input shuffles should be canonicalized to be V1-input "
8852 // Try to use shift instructions.
8854 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8857 // See if we can use SSE4A Extraction / Insertion.
8858 if (Subtarget->hasSSE4A())
8859 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
8862 // There are special ways we can lower some single-element blends.
8863 if (NumV2Inputs == 1)
8864 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8865 Mask, Subtarget, DAG))
8868 // We have different paths for blend lowering, but they all must use the
8869 // *exact* same predicate.
8870 bool IsBlendSupported = Subtarget->hasSSE41();
8871 if (IsBlendSupported)
8872 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8876 if (SDValue Masked =
8877 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8880 // Use dedicated unpack instructions for masks that match their pattern.
8881 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8882 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8883 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8884 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8886 // Try to use byte rotation instructions.
8887 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8888 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8891 if (SDValue BitBlend =
8892 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8895 if (SDValue Unpack =
8896 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8899 // If we can't directly blend but can use PSHUFB, that will be better as it
8900 // can both shuffle and set up the inefficient blend.
8901 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8902 bool V1InUse, V2InUse;
8903 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8907 // We can always bit-blend if we have to so the fallback strategy is to
8908 // decompose into single-input permutes and blends.
8909 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8913 /// \brief Check whether a compaction lowering can be done by dropping even
8914 /// elements and compute how many times even elements must be dropped.
8916 /// This handles shuffles which take every Nth element where N is a power of
8917 /// two. Example shuffle masks:
8919 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8920 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8921 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8922 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8923 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8924 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8926 /// Any of these lanes can of course be undef.
8928 /// This routine only supports N <= 3.
8929 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8932 /// \returns N above, or the number of times even elements must be dropped if
8933 /// there is such a number. Otherwise returns zero.
8934 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8935 // Figure out whether we're looping over two inputs or just one.
8936 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8938 // The modulus for the shuffle vector entries is based on whether this is
8939 // a single input or not.
8940 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8941 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8942 "We should only be called with masks with a power-of-2 size!");
8944 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8946 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8947 // and 2^3 simultaneously. This is because we may have ambiguity with
8948 // partially undef inputs.
8949 bool ViableForN[3] = {true, true, true};
8951 for (int i = 0, e = Mask.size(); i < e; ++i) {
8952 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8957 bool IsAnyViable = false;
8958 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8959 if (ViableForN[j]) {
8962 // The shuffle mask must be equal to (i * 2^N) % M.
8963 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8966 ViableForN[j] = false;
8968 // Early exit if we exhaust the possible powers of two.
8973 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8977 // Return 0 as there is no viable power of two.
8981 /// \brief Generic lowering of v16i8 shuffles.
8983 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8984 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8985 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8986 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8988 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8989 const X86Subtarget *Subtarget,
8990 SelectionDAG &DAG) {
8992 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8993 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8994 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8995 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8996 ArrayRef<int> Mask = SVOp->getMask();
8997 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8999 // Try to use shift instructions.
9001 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9004 // Try to use byte rotation instructions.
9005 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9006 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9009 // Try to use a zext lowering.
9010 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9011 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9014 // See if we can use SSE4A Extraction / Insertion.
9015 if (Subtarget->hasSSE4A())
9016 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9020 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9022 // For single-input shuffles, there are some nicer lowering tricks we can use.
9023 if (NumV2Elements == 0) {
9024 // Check for being able to broadcast a single element.
9025 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9026 Mask, Subtarget, DAG))
9029 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9030 // Notably, this handles splat and partial-splat shuffles more efficiently.
9031 // However, it only makes sense if the pre-duplication shuffle simplifies
9032 // things significantly. Currently, this means we need to be able to
9033 // express the pre-duplication shuffle as an i16 shuffle.
9035 // FIXME: We should check for other patterns which can be widened into an
9036 // i16 shuffle as well.
9037 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9038 for (int i = 0; i < 16; i += 2)
9039 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9044 auto tryToWidenViaDuplication = [&]() -> SDValue {
9045 if (!canWidenViaDuplication(Mask))
9047 SmallVector<int, 4> LoInputs;
9048 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9049 [](int M) { return M >= 0 && M < 8; });
9050 std::sort(LoInputs.begin(), LoInputs.end());
9051 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9053 SmallVector<int, 4> HiInputs;
9054 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9055 [](int M) { return M >= 8; });
9056 std::sort(HiInputs.begin(), HiInputs.end());
9057 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9060 bool TargetLo = LoInputs.size() >= HiInputs.size();
9061 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9062 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9064 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9065 SmallDenseMap<int, int, 8> LaneMap;
9066 for (int I : InPlaceInputs) {
9067 PreDupI16Shuffle[I/2] = I/2;
9070 int j = TargetLo ? 0 : 4, je = j + 4;
9071 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9072 // Check if j is already a shuffle of this input. This happens when
9073 // there are two adjacent bytes after we move the low one.
9074 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9075 // If we haven't yet mapped the input, search for a slot into which
9077 while (j < je && PreDupI16Shuffle[j] != -1)
9081 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9084 // Map this input with the i16 shuffle.
9085 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9088 // Update the lane map based on the mapping we ended up with.
9089 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9091 V1 = DAG.getBitcast(
9093 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9094 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9096 // Unpack the bytes to form the i16s that will be shuffled into place.
9097 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9098 MVT::v16i8, V1, V1);
9100 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9101 for (int i = 0; i < 16; ++i)
9102 if (Mask[i] != -1) {
9103 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9104 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9105 if (PostDupI16Shuffle[i / 2] == -1)
9106 PostDupI16Shuffle[i / 2] = MappedMask;
9108 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9109 "Conflicting entrties in the original shuffle!");
9111 return DAG.getBitcast(
9113 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9114 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9116 if (SDValue V = tryToWidenViaDuplication())
9120 if (SDValue Masked =
9121 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9124 // Use dedicated unpack instructions for masks that match their pattern.
9125 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9126 0, 16, 1, 17, 2, 18, 3, 19,
9128 4, 20, 5, 21, 6, 22, 7, 23}))
9129 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9130 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9131 8, 24, 9, 25, 10, 26, 11, 27,
9133 12, 28, 13, 29, 14, 30, 15, 31}))
9134 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9136 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9137 // with PSHUFB. It is important to do this before we attempt to generate any
9138 // blends but after all of the single-input lowerings. If the single input
9139 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9140 // want to preserve that and we can DAG combine any longer sequences into
9141 // a PSHUFB in the end. But once we start blending from multiple inputs,
9142 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9143 // and there are *very* few patterns that would actually be faster than the
9144 // PSHUFB approach because of its ability to zero lanes.
9146 // FIXME: The only exceptions to the above are blends which are exact
9147 // interleavings with direct instructions supporting them. We currently don't
9148 // handle those well here.
9149 if (Subtarget->hasSSSE3()) {
9150 bool V1InUse = false;
9151 bool V2InUse = false;
9153 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9154 DAG, V1InUse, V2InUse);
9156 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9157 // do so. This avoids using them to handle blends-with-zero which is
9158 // important as a single pshufb is significantly faster for that.
9159 if (V1InUse && V2InUse) {
9160 if (Subtarget->hasSSE41())
9161 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9162 Mask, Subtarget, DAG))
9165 // We can use an unpack to do the blending rather than an or in some
9166 // cases. Even though the or may be (very minorly) more efficient, we
9167 // preference this lowering because there are common cases where part of
9168 // the complexity of the shuffles goes away when we do the final blend as
9170 // FIXME: It might be worth trying to detect if the unpack-feeding
9171 // shuffles will both be pshufb, in which case we shouldn't bother with
9173 if (SDValue Unpack =
9174 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
9181 // There are special ways we can lower some single-element blends.
9182 if (NumV2Elements == 1)
9183 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9184 Mask, Subtarget, DAG))
9187 if (SDValue BitBlend =
9188 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9191 // Check whether a compaction lowering can be done. This handles shuffles
9192 // which take every Nth element for some even N. See the helper function for
9195 // We special case these as they can be particularly efficiently handled with
9196 // the PACKUSB instruction on x86 and they show up in common patterns of
9197 // rearranging bytes to truncate wide elements.
9198 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9199 // NumEvenDrops is the power of two stride of the elements. Another way of
9200 // thinking about it is that we need to drop the even elements this many
9201 // times to get the original input.
9202 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9204 // First we need to zero all the dropped bytes.
9205 assert(NumEvenDrops <= 3 &&
9206 "No support for dropping even elements more than 3 times.");
9207 // We use the mask type to pick which bytes are preserved based on how many
9208 // elements are dropped.
9209 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9210 SDValue ByteClearMask = DAG.getBitcast(
9211 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9212 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9214 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9216 // Now pack things back together.
9217 V1 = DAG.getBitcast(MVT::v8i16, V1);
9218 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9219 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9220 for (int i = 1; i < NumEvenDrops; ++i) {
9221 Result = DAG.getBitcast(MVT::v8i16, Result);
9222 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9228 // Handle multi-input cases by blending single-input shuffles.
9229 if (NumV2Elements > 0)
9230 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9233 // The fallback path for single-input shuffles widens this into two v8i16
9234 // vectors with unpacks, shuffles those, and then pulls them back together
9238 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9239 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9240 for (int i = 0; i < 16; ++i)
9242 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9244 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9246 SDValue VLoHalf, VHiHalf;
9247 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9248 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9250 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9251 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9252 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9253 [](int M) { return M >= 0 && M % 2 == 1; })) {
9254 // Use a mask to drop the high bytes.
9255 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9256 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9257 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9259 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9260 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9262 // Squash the masks to point directly into VLoHalf.
9263 for (int &M : LoBlendMask)
9266 for (int &M : HiBlendMask)
9270 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9271 // VHiHalf so that we can blend them as i16s.
9272 VLoHalf = DAG.getBitcast(
9273 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9274 VHiHalf = DAG.getBitcast(
9275 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9278 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9279 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9281 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9284 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9286 /// This routine breaks down the specific type of 128-bit shuffle and
9287 /// dispatches to the lowering routines accordingly.
9288 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9289 MVT VT, const X86Subtarget *Subtarget,
9290 SelectionDAG &DAG) {
9291 switch (VT.SimpleTy) {
9293 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9295 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9297 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9299 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9301 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9303 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9306 llvm_unreachable("Unimplemented!");
9310 /// \brief Helper function to test whether a shuffle mask could be
9311 /// simplified by widening the elements being shuffled.
9313 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9314 /// leaves it in an unspecified state.
9316 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9317 /// shuffle masks. The latter have the special property of a '-2' representing
9318 /// a zero-ed lane of a vector.
9319 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9320 SmallVectorImpl<int> &WidenedMask) {
9321 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9322 // If both elements are undef, its trivial.
9323 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9324 WidenedMask.push_back(SM_SentinelUndef);
9328 // Check for an undef mask and a mask value properly aligned to fit with
9329 // a pair of values. If we find such a case, use the non-undef mask's value.
9330 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9331 WidenedMask.push_back(Mask[i + 1] / 2);
9334 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9335 WidenedMask.push_back(Mask[i] / 2);
9339 // When zeroing, we need to spread the zeroing across both lanes to widen.
9340 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9341 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9342 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9343 WidenedMask.push_back(SM_SentinelZero);
9349 // Finally check if the two mask values are adjacent and aligned with
9351 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9352 WidenedMask.push_back(Mask[i] / 2);
9356 // Otherwise we can't safely widen the elements used in this shuffle.
9359 assert(WidenedMask.size() == Mask.size() / 2 &&
9360 "Incorrect size of mask after widening the elements!");
9365 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9367 /// This routine just extracts two subvectors, shuffles them independently, and
9368 /// then concatenates them back together. This should work effectively with all
9369 /// AVX vector shuffle types.
9370 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9371 SDValue V2, ArrayRef<int> Mask,
9372 SelectionDAG &DAG) {
9373 assert(VT.getSizeInBits() >= 256 &&
9374 "Only for 256-bit or wider vector shuffles!");
9375 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9376 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9378 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9379 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9381 int NumElements = VT.getVectorNumElements();
9382 int SplitNumElements = NumElements / 2;
9383 MVT ScalarVT = VT.getScalarType();
9384 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9386 // Rather than splitting build-vectors, just build two narrower build
9387 // vectors. This helps shuffling with splats and zeros.
9388 auto SplitVector = [&](SDValue V) {
9389 while (V.getOpcode() == ISD::BITCAST)
9390 V = V->getOperand(0);
9392 MVT OrigVT = V.getSimpleValueType();
9393 int OrigNumElements = OrigVT.getVectorNumElements();
9394 int OrigSplitNumElements = OrigNumElements / 2;
9395 MVT OrigScalarVT = OrigVT.getScalarType();
9396 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9400 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9402 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9403 DAG.getIntPtrConstant(0, DL));
9404 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9405 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9408 SmallVector<SDValue, 16> LoOps, HiOps;
9409 for (int i = 0; i < OrigSplitNumElements; ++i) {
9410 LoOps.push_back(BV->getOperand(i));
9411 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9413 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9414 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9416 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9417 DAG.getBitcast(SplitVT, HiV));
9420 SDValue LoV1, HiV1, LoV2, HiV2;
9421 std::tie(LoV1, HiV1) = SplitVector(V1);
9422 std::tie(LoV2, HiV2) = SplitVector(V2);
9424 // Now create two 4-way blends of these half-width vectors.
9425 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9426 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9427 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9428 for (int i = 0; i < SplitNumElements; ++i) {
9429 int M = HalfMask[i];
9430 if (M >= NumElements) {
9431 if (M >= NumElements + SplitNumElements)
9435 V2BlendMask.push_back(M - NumElements);
9436 V1BlendMask.push_back(-1);
9437 BlendMask.push_back(SplitNumElements + i);
9438 } else if (M >= 0) {
9439 if (M >= SplitNumElements)
9443 V2BlendMask.push_back(-1);
9444 V1BlendMask.push_back(M);
9445 BlendMask.push_back(i);
9447 V2BlendMask.push_back(-1);
9448 V1BlendMask.push_back(-1);
9449 BlendMask.push_back(-1);
9453 // Because the lowering happens after all combining takes place, we need to
9454 // manually combine these blend masks as much as possible so that we create
9455 // a minimal number of high-level vector shuffle nodes.
9457 // First try just blending the halves of V1 or V2.
9458 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9459 return DAG.getUNDEF(SplitVT);
9460 if (!UseLoV2 && !UseHiV2)
9461 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9462 if (!UseLoV1 && !UseHiV1)
9463 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9465 SDValue V1Blend, V2Blend;
9466 if (UseLoV1 && UseHiV1) {
9468 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9470 // We only use half of V1 so map the usage down into the final blend mask.
9471 V1Blend = UseLoV1 ? LoV1 : HiV1;
9472 for (int i = 0; i < SplitNumElements; ++i)
9473 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9474 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9476 if (UseLoV2 && UseHiV2) {
9478 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9480 // We only use half of V2 so map the usage down into the final blend mask.
9481 V2Blend = UseLoV2 ? LoV2 : HiV2;
9482 for (int i = 0; i < SplitNumElements; ++i)
9483 if (BlendMask[i] >= SplitNumElements)
9484 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9486 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9488 SDValue Lo = HalfBlend(LoMask);
9489 SDValue Hi = HalfBlend(HiMask);
9490 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9493 /// \brief Either split a vector in halves or decompose the shuffles and the
9496 /// This is provided as a good fallback for many lowerings of non-single-input
9497 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9498 /// between splitting the shuffle into 128-bit components and stitching those
9499 /// back together vs. extracting the single-input shuffles and blending those
9501 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9502 SDValue V2, ArrayRef<int> Mask,
9503 SelectionDAG &DAG) {
9504 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9505 "lower single-input shuffles as it "
9506 "could then recurse on itself.");
9507 int Size = Mask.size();
9509 // If this can be modeled as a broadcast of two elements followed by a blend,
9510 // prefer that lowering. This is especially important because broadcasts can
9511 // often fold with memory operands.
9512 auto DoBothBroadcast = [&] {
9513 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9516 if (V2BroadcastIdx == -1)
9517 V2BroadcastIdx = M - Size;
9518 else if (M - Size != V2BroadcastIdx)
9520 } else if (M >= 0) {
9521 if (V1BroadcastIdx == -1)
9523 else if (M != V1BroadcastIdx)
9528 if (DoBothBroadcast())
9529 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9532 // If the inputs all stem from a single 128-bit lane of each input, then we
9533 // split them rather than blending because the split will decompose to
9534 // unusually few instructions.
9535 int LaneCount = VT.getSizeInBits() / 128;
9536 int LaneSize = Size / LaneCount;
9537 SmallBitVector LaneInputs[2];
9538 LaneInputs[0].resize(LaneCount, false);
9539 LaneInputs[1].resize(LaneCount, false);
9540 for (int i = 0; i < Size; ++i)
9542 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9543 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9544 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9546 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9547 // that the decomposed single-input shuffles don't end up here.
9548 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9551 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9552 /// a permutation and blend of those lanes.
9554 /// This essentially blends the out-of-lane inputs to each lane into the lane
9555 /// from a permuted copy of the vector. This lowering strategy results in four
9556 /// instructions in the worst case for a single-input cross lane shuffle which
9557 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9558 /// of. Special cases for each particular shuffle pattern should be handled
9559 /// prior to trying this lowering.
9560 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9561 SDValue V1, SDValue V2,
9563 SelectionDAG &DAG) {
9564 // FIXME: This should probably be generalized for 512-bit vectors as well.
9565 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9566 int LaneSize = Mask.size() / 2;
9568 // If there are only inputs from one 128-bit lane, splitting will in fact be
9569 // less expensive. The flags track whether the given lane contains an element
9570 // that crosses to another lane.
9571 bool LaneCrossing[2] = {false, false};
9572 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9573 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9574 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9575 if (!LaneCrossing[0] || !LaneCrossing[1])
9576 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9578 if (isSingleInputShuffleMask(Mask)) {
9579 SmallVector<int, 32> FlippedBlendMask;
9580 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9581 FlippedBlendMask.push_back(
9582 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9584 : Mask[i] % LaneSize +
9585 (i / LaneSize) * LaneSize + Size));
9587 // Flip the vector, and blend the results which should now be in-lane. The
9588 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9589 // 5 for the high source. The value 3 selects the high half of source 2 and
9590 // the value 2 selects the low half of source 2. We only use source 2 to
9591 // allow folding it into a memory operand.
9592 unsigned PERMMask = 3 | 2 << 4;
9593 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9594 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9595 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9598 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9599 // will be handled by the above logic and a blend of the results, much like
9600 // other patterns in AVX.
9601 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9604 /// \brief Handle lowering 2-lane 128-bit shuffles.
9605 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9606 SDValue V2, ArrayRef<int> Mask,
9607 const X86Subtarget *Subtarget,
9608 SelectionDAG &DAG) {
9609 // TODO: If minimizing size and one of the inputs is a zero vector and the
9610 // the zero vector has only one use, we could use a VPERM2X128 to save the
9611 // instruction bytes needed to explicitly generate the zero vector.
9613 // Blends are faster and handle all the non-lane-crossing cases.
9614 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9618 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9619 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9621 // If either input operand is a zero vector, use VPERM2X128 because its mask
9622 // allows us to replace the zero input with an implicit zero.
9623 if (!IsV1Zero && !IsV2Zero) {
9624 // Check for patterns which can be matched with a single insert of a 128-bit
9626 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9627 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9628 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9629 VT.getVectorNumElements() / 2);
9630 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9631 DAG.getIntPtrConstant(0, DL));
9632 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9633 OnlyUsesV1 ? V1 : V2,
9634 DAG.getIntPtrConstant(0, DL));
9635 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9639 // Otherwise form a 128-bit permutation. After accounting for undefs,
9640 // convert the 64-bit shuffle mask selection values into 128-bit
9641 // selection bits by dividing the indexes by 2 and shifting into positions
9642 // defined by a vperm2*128 instruction's immediate control byte.
9644 // The immediate permute control byte looks like this:
9645 // [1:0] - select 128 bits from sources for low half of destination
9647 // [3] - zero low half of destination
9648 // [5:4] - select 128 bits from sources for high half of destination
9650 // [7] - zero high half of destination
9652 int MaskLO = Mask[0];
9653 if (MaskLO == SM_SentinelUndef)
9654 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9656 int MaskHI = Mask[2];
9657 if (MaskHI == SM_SentinelUndef)
9658 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9660 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9662 // If either input is a zero vector, replace it with an undef input.
9663 // Shuffle mask values < 4 are selecting elements of V1.
9664 // Shuffle mask values >= 4 are selecting elements of V2.
9665 // Adjust each half of the permute mask by clearing the half that was
9666 // selecting the zero vector and setting the zero mask bit.
9668 V1 = DAG.getUNDEF(VT);
9670 PermMask = (PermMask & 0xf0) | 0x08;
9672 PermMask = (PermMask & 0x0f) | 0x80;
9675 V2 = DAG.getUNDEF(VT);
9677 PermMask = (PermMask & 0xf0) | 0x08;
9679 PermMask = (PermMask & 0x0f) | 0x80;
9682 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9683 DAG.getConstant(PermMask, DL, MVT::i8));
9686 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9687 /// shuffling each lane.
9689 /// This will only succeed when the result of fixing the 128-bit lanes results
9690 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9691 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9692 /// the lane crosses early and then use simpler shuffles within each lane.
9694 /// FIXME: It might be worthwhile at some point to support this without
9695 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9696 /// in x86 only floating point has interesting non-repeating shuffles, and even
9697 /// those are still *marginally* more expensive.
9698 static SDValue lowerVectorShuffleByMerging128BitLanes(
9699 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9700 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9701 assert(!isSingleInputShuffleMask(Mask) &&
9702 "This is only useful with multiple inputs.");
9704 int Size = Mask.size();
9705 int LaneSize = 128 / VT.getScalarSizeInBits();
9706 int NumLanes = Size / LaneSize;
9707 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9709 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9710 // check whether the in-128-bit lane shuffles share a repeating pattern.
9711 SmallVector<int, 4> Lanes;
9712 Lanes.resize(NumLanes, -1);
9713 SmallVector<int, 4> InLaneMask;
9714 InLaneMask.resize(LaneSize, -1);
9715 for (int i = 0; i < Size; ++i) {
9719 int j = i / LaneSize;
9722 // First entry we've seen for this lane.
9723 Lanes[j] = Mask[i] / LaneSize;
9724 } else if (Lanes[j] != Mask[i] / LaneSize) {
9725 // This doesn't match the lane selected previously!
9729 // Check that within each lane we have a consistent shuffle mask.
9730 int k = i % LaneSize;
9731 if (InLaneMask[k] < 0) {
9732 InLaneMask[k] = Mask[i] % LaneSize;
9733 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9734 // This doesn't fit a repeating in-lane mask.
9739 // First shuffle the lanes into place.
9740 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9741 VT.getSizeInBits() / 64);
9742 SmallVector<int, 8> LaneMask;
9743 LaneMask.resize(NumLanes * 2, -1);
9744 for (int i = 0; i < NumLanes; ++i)
9745 if (Lanes[i] >= 0) {
9746 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9747 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9750 V1 = DAG.getBitcast(LaneVT, V1);
9751 V2 = DAG.getBitcast(LaneVT, V2);
9752 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9754 // Cast it back to the type we actually want.
9755 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9757 // Now do a simple shuffle that isn't lane crossing.
9758 SmallVector<int, 8> NewMask;
9759 NewMask.resize(Size, -1);
9760 for (int i = 0; i < Size; ++i)
9762 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9763 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9764 "Must not introduce lane crosses at this point!");
9766 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9769 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9772 /// This returns true if the elements from a particular input are already in the
9773 /// slot required by the given mask and require no permutation.
9774 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9775 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9776 int Size = Mask.size();
9777 for (int i = 0; i < Size; ++i)
9778 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9784 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9785 ArrayRef<int> Mask, SDValue V1,
9786 SDValue V2, SelectionDAG &DAG) {
9788 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9789 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9790 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9791 int NumElts = VT.getVectorNumElements();
9792 bool ShufpdMask = true;
9793 bool CommutableMask = true;
9794 unsigned Immediate = 0;
9795 for (int i = 0; i < NumElts; ++i) {
9798 int Val = (i & 6) + NumElts * (i & 1);
9799 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9800 if (Mask[i] < Val || Mask[i] > Val + 1)
9802 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9803 CommutableMask = false;
9804 Immediate |= (Mask[i] % 2) << i;
9807 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9808 DAG.getConstant(Immediate, DL, MVT::i8));
9810 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9811 DAG.getConstant(Immediate, DL, MVT::i8));
9815 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9817 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9818 /// isn't available.
9819 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9820 const X86Subtarget *Subtarget,
9821 SelectionDAG &DAG) {
9823 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9824 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9825 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9826 ArrayRef<int> Mask = SVOp->getMask();
9827 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9829 SmallVector<int, 4> WidenedMask;
9830 if (canWidenShuffleElements(Mask, WidenedMask))
9831 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9834 if (isSingleInputShuffleMask(Mask)) {
9835 // Check for being able to broadcast a single element.
9836 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9837 Mask, Subtarget, DAG))
9840 // Use low duplicate instructions for masks that match their pattern.
9841 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9842 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9844 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9845 // Non-half-crossing single input shuffles can be lowerid with an
9846 // interleaved permutation.
9847 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9848 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9849 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9850 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9853 // With AVX2 we have direct support for this permutation.
9854 if (Subtarget->hasAVX2())
9855 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9856 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9858 // Otherwise, fall back.
9859 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9863 // X86 has dedicated unpack instructions that can handle specific blend
9864 // operations: UNPCKH and UNPCKL.
9865 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9866 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9867 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9868 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9869 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9870 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9871 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9872 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9874 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9878 // Check if the blend happens to exactly fit that of SHUFPD.
9880 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9883 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9884 // shuffle. However, if we have AVX2 and either inputs are already in place,
9885 // we will be able to shuffle even across lanes the other input in a single
9886 // instruction so skip this pattern.
9887 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9888 isShuffleMaskInputInPlace(1, Mask))))
9889 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9890 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9893 // If we have AVX2 then we always want to lower with a blend because an v4 we
9894 // can fully permute the elements.
9895 if (Subtarget->hasAVX2())
9896 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9899 // Otherwise fall back on generic lowering.
9900 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9903 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9905 /// This routine is only called when we have AVX2 and thus a reasonable
9906 /// instruction set for v4i64 shuffling..
9907 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9908 const X86Subtarget *Subtarget,
9909 SelectionDAG &DAG) {
9911 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9912 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9913 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9914 ArrayRef<int> Mask = SVOp->getMask();
9915 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9916 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9918 SmallVector<int, 4> WidenedMask;
9919 if (canWidenShuffleElements(Mask, WidenedMask))
9920 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9923 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9927 // Check for being able to broadcast a single element.
9928 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9929 Mask, Subtarget, DAG))
9932 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9933 // use lower latency instructions that will operate on both 128-bit lanes.
9934 SmallVector<int, 2> RepeatedMask;
9935 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9936 if (isSingleInputShuffleMask(Mask)) {
9937 int PSHUFDMask[] = {-1, -1, -1, -1};
9938 for (int i = 0; i < 2; ++i)
9939 if (RepeatedMask[i] >= 0) {
9940 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9941 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9943 return DAG.getBitcast(
9945 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9946 DAG.getBitcast(MVT::v8i32, V1),
9947 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9951 // AVX2 provides a direct instruction for permuting a single input across
9953 if (isSingleInputShuffleMask(Mask))
9954 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9955 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9957 // Try to use shift instructions.
9959 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9962 // Use dedicated unpack instructions for masks that match their pattern.
9963 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9964 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9965 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9966 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9967 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9968 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9969 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9970 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9972 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9973 // shuffle. However, if we have AVX2 and either inputs are already in place,
9974 // we will be able to shuffle even across lanes the other input in a single
9975 // instruction so skip this pattern.
9976 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9977 isShuffleMaskInputInPlace(1, Mask))))
9978 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9979 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9982 // Otherwise fall back on generic blend lowering.
9983 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9987 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9989 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9990 /// isn't available.
9991 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9992 const X86Subtarget *Subtarget,
9993 SelectionDAG &DAG) {
9995 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9996 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9998 ArrayRef<int> Mask = SVOp->getMask();
9999 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10001 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10005 // Check for being able to broadcast a single element.
10006 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10007 Mask, Subtarget, DAG))
10010 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10011 // options to efficiently lower the shuffle.
10012 SmallVector<int, 4> RepeatedMask;
10013 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10014 assert(RepeatedMask.size() == 4 &&
10015 "Repeated masks must be half the mask width!");
10017 // Use even/odd duplicate instructions for masks that match their pattern.
10018 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10019 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10020 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10021 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10023 if (isSingleInputShuffleMask(Mask))
10024 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10025 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10027 // Use dedicated unpack instructions for masks that match their pattern.
10028 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10029 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10030 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10031 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10032 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10033 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10034 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10035 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10037 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10038 // have already handled any direct blends. We also need to squash the
10039 // repeated mask into a simulated v4f32 mask.
10040 for (int i = 0; i < 4; ++i)
10041 if (RepeatedMask[i] >= 8)
10042 RepeatedMask[i] -= 4;
10043 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10046 // If we have a single input shuffle with different shuffle patterns in the
10047 // two 128-bit lanes use the variable mask to VPERMILPS.
10048 if (isSingleInputShuffleMask(Mask)) {
10049 SDValue VPermMask[8];
10050 for (int i = 0; i < 8; ++i)
10051 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10052 : DAG.getConstant(Mask[i], DL, MVT::i32);
10053 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10054 return DAG.getNode(
10055 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10056 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10058 if (Subtarget->hasAVX2())
10059 return DAG.getNode(
10060 X86ISD::VPERMV, DL, MVT::v8f32,
10061 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10062 MVT::v8i32, VPermMask)),
10065 // Otherwise, fall back.
10066 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10070 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10072 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10073 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10076 // If we have AVX2 then we always want to lower with a blend because at v8 we
10077 // can fully permute the elements.
10078 if (Subtarget->hasAVX2())
10079 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10082 // Otherwise fall back on generic lowering.
10083 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10086 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10088 /// This routine is only called when we have AVX2 and thus a reasonable
10089 /// instruction set for v8i32 shuffling..
10090 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10091 const X86Subtarget *Subtarget,
10092 SelectionDAG &DAG) {
10094 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10095 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10097 ArrayRef<int> Mask = SVOp->getMask();
10098 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10099 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10101 // Whenever we can lower this as a zext, that instruction is strictly faster
10102 // than any alternative. It also allows us to fold memory operands into the
10103 // shuffle in many cases.
10104 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10105 Mask, Subtarget, DAG))
10108 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10112 // Check for being able to broadcast a single element.
10113 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10114 Mask, Subtarget, DAG))
10117 // If the shuffle mask is repeated in each 128-bit lane we can use more
10118 // efficient instructions that mirror the shuffles across the two 128-bit
10120 SmallVector<int, 4> RepeatedMask;
10121 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10122 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10123 if (isSingleInputShuffleMask(Mask))
10124 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10125 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10127 // Use dedicated unpack instructions for masks that match their pattern.
10128 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10129 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10130 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10131 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10132 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10133 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10134 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10135 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10138 // Try to use shift instructions.
10139 if (SDValue Shift =
10140 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10143 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10144 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10147 // If the shuffle patterns aren't repeated but it is a single input, directly
10148 // generate a cross-lane VPERMD instruction.
10149 if (isSingleInputShuffleMask(Mask)) {
10150 SDValue VPermMask[8];
10151 for (int i = 0; i < 8; ++i)
10152 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10153 : DAG.getConstant(Mask[i], DL, MVT::i32);
10154 return DAG.getNode(
10155 X86ISD::VPERMV, DL, MVT::v8i32,
10156 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10159 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10161 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10162 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10165 // Otherwise fall back on generic blend lowering.
10166 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10170 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10172 /// This routine is only called when we have AVX2 and thus a reasonable
10173 /// instruction set for v16i16 shuffling..
10174 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10175 const X86Subtarget *Subtarget,
10176 SelectionDAG &DAG) {
10178 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10179 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10181 ArrayRef<int> Mask = SVOp->getMask();
10182 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10183 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10185 // Whenever we can lower this as a zext, that instruction is strictly faster
10186 // than any alternative. It also allows us to fold memory operands into the
10187 // shuffle in many cases.
10188 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10189 Mask, Subtarget, DAG))
10192 // Check for being able to broadcast a single element.
10193 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10194 Mask, Subtarget, DAG))
10197 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10201 // Use dedicated unpack instructions for masks that match their pattern.
10202 if (isShuffleEquivalent(V1, V2, Mask,
10203 {// First 128-bit lane:
10204 0, 16, 1, 17, 2, 18, 3, 19,
10205 // Second 128-bit lane:
10206 8, 24, 9, 25, 10, 26, 11, 27}))
10207 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10208 if (isShuffleEquivalent(V1, V2, Mask,
10209 {// First 128-bit lane:
10210 4, 20, 5, 21, 6, 22, 7, 23,
10211 // Second 128-bit lane:
10212 12, 28, 13, 29, 14, 30, 15, 31}))
10213 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10215 // Try to use shift instructions.
10216 if (SDValue Shift =
10217 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10220 // Try to use byte rotation instructions.
10221 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10222 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10225 if (isSingleInputShuffleMask(Mask)) {
10226 // There are no generalized cross-lane shuffle operations available on i16
10228 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10229 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10232 SmallVector<int, 8> RepeatedMask;
10233 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10234 // As this is a single-input shuffle, the repeated mask should be
10235 // a strictly valid v8i16 mask that we can pass through to the v8i16
10236 // lowering to handle even the v16 case.
10237 return lowerV8I16GeneralSingleInputVectorShuffle(
10238 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10241 SDValue PSHUFBMask[32];
10242 for (int i = 0; i < 16; ++i) {
10243 if (Mask[i] == -1) {
10244 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10248 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10249 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10250 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10251 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10253 return DAG.getBitcast(MVT::v16i16,
10254 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10255 DAG.getBitcast(MVT::v32i8, V1),
10256 DAG.getNode(ISD::BUILD_VECTOR, DL,
10257 MVT::v32i8, PSHUFBMask)));
10260 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10262 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10263 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10266 // Otherwise fall back on generic lowering.
10267 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10270 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10272 /// This routine is only called when we have AVX2 and thus a reasonable
10273 /// instruction set for v32i8 shuffling..
10274 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10275 const X86Subtarget *Subtarget,
10276 SelectionDAG &DAG) {
10278 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10279 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10280 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10281 ArrayRef<int> Mask = SVOp->getMask();
10282 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10283 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10285 // Whenever we can lower this as a zext, that instruction is strictly faster
10286 // than any alternative. It also allows us to fold memory operands into the
10287 // shuffle in many cases.
10288 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10289 Mask, Subtarget, DAG))
10292 // Check for being able to broadcast a single element.
10293 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10294 Mask, Subtarget, DAG))
10297 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10301 // Use dedicated unpack instructions for masks that match their pattern.
10302 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10304 if (isShuffleEquivalent(
10306 {// First 128-bit lane:
10307 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10308 // Second 128-bit lane:
10309 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10310 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10311 if (isShuffleEquivalent(
10313 {// First 128-bit lane:
10314 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10315 // Second 128-bit lane:
10316 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10317 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10319 // Try to use shift instructions.
10320 if (SDValue Shift =
10321 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10324 // Try to use byte rotation instructions.
10325 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10326 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10329 if (isSingleInputShuffleMask(Mask)) {
10330 // There are no generalized cross-lane shuffle operations available on i8
10332 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10333 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10336 SDValue PSHUFBMask[32];
10337 for (int i = 0; i < 32; ++i)
10340 ? DAG.getUNDEF(MVT::i8)
10341 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10344 return DAG.getNode(
10345 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10346 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10349 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10351 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10352 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10355 // Otherwise fall back on generic lowering.
10356 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10359 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10361 /// This routine either breaks down the specific type of a 256-bit x86 vector
10362 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10363 /// together based on the available instructions.
10364 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10365 MVT VT, const X86Subtarget *Subtarget,
10366 SelectionDAG &DAG) {
10368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10369 ArrayRef<int> Mask = SVOp->getMask();
10371 // If we have a single input to the zero element, insert that into V1 if we
10372 // can do so cheaply.
10373 int NumElts = VT.getVectorNumElements();
10374 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10375 return M >= NumElts;
10378 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10379 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10380 DL, VT, V1, V2, Mask, Subtarget, DAG))
10383 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10384 // check for those subtargets here and avoid much of the subtarget querying in
10385 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10386 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10387 // floating point types there eventually, just immediately cast everything to
10388 // a float and operate entirely in that domain.
10389 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10390 int ElementBits = VT.getScalarSizeInBits();
10391 if (ElementBits < 32)
10392 // No floating point type available, decompose into 128-bit vectors.
10393 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10395 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10396 VT.getVectorNumElements());
10397 V1 = DAG.getBitcast(FpVT, V1);
10398 V2 = DAG.getBitcast(FpVT, V2);
10399 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10402 switch (VT.SimpleTy) {
10404 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10406 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10408 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10410 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10412 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10414 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10417 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10421 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10422 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10423 const X86Subtarget *Subtarget,
10424 SelectionDAG &DAG) {
10426 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10427 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10429 ArrayRef<int> Mask = SVOp->getMask();
10430 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10432 // X86 has dedicated unpack instructions that can handle specific blend
10433 // operations: UNPCKH and UNPCKL.
10434 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10435 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10436 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10437 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10439 // FIXME: Implement direct support for this type!
10440 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10443 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10444 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10445 const X86Subtarget *Subtarget,
10446 SelectionDAG &DAG) {
10448 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10449 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10450 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10451 ArrayRef<int> Mask = SVOp->getMask();
10452 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10454 // Use dedicated unpack instructions for masks that match their pattern.
10455 if (isShuffleEquivalent(V1, V2, Mask,
10456 {// First 128-bit lane.
10457 0, 16, 1, 17, 4, 20, 5, 21,
10458 // Second 128-bit lane.
10459 8, 24, 9, 25, 12, 28, 13, 29}))
10460 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10461 if (isShuffleEquivalent(V1, V2, Mask,
10462 {// First 128-bit lane.
10463 2, 18, 3, 19, 6, 22, 7, 23,
10464 // Second 128-bit lane.
10465 10, 26, 11, 27, 14, 30, 15, 31}))
10466 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10468 // FIXME: Implement direct support for this type!
10469 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10472 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10473 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10474 const X86Subtarget *Subtarget,
10475 SelectionDAG &DAG) {
10477 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10478 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10479 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10480 ArrayRef<int> Mask = SVOp->getMask();
10481 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10483 // X86 has dedicated unpack instructions that can handle specific blend
10484 // operations: UNPCKH and UNPCKL.
10485 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10486 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10487 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10488 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10490 // FIXME: Implement direct support for this type!
10491 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10494 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10495 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10496 const X86Subtarget *Subtarget,
10497 SelectionDAG &DAG) {
10499 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10500 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10502 ArrayRef<int> Mask = SVOp->getMask();
10503 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10505 // Use dedicated unpack instructions for masks that match their pattern.
10506 if (isShuffleEquivalent(V1, V2, Mask,
10507 {// First 128-bit lane.
10508 0, 16, 1, 17, 4, 20, 5, 21,
10509 // Second 128-bit lane.
10510 8, 24, 9, 25, 12, 28, 13, 29}))
10511 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10512 if (isShuffleEquivalent(V1, V2, Mask,
10513 {// First 128-bit lane.
10514 2, 18, 3, 19, 6, 22, 7, 23,
10515 // Second 128-bit lane.
10516 10, 26, 11, 27, 14, 30, 15, 31}))
10517 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10519 // FIXME: Implement direct support for this type!
10520 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10523 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10524 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10525 const X86Subtarget *Subtarget,
10526 SelectionDAG &DAG) {
10528 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10529 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10530 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10531 ArrayRef<int> Mask = SVOp->getMask();
10532 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10533 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10535 // FIXME: Implement direct support for this type!
10536 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10539 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10540 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10541 const X86Subtarget *Subtarget,
10542 SelectionDAG &DAG) {
10544 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10545 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10546 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10547 ArrayRef<int> Mask = SVOp->getMask();
10548 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10549 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10551 // FIXME: Implement direct support for this type!
10552 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10555 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10557 /// This routine either breaks down the specific type of a 512-bit x86 vector
10558 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10559 /// together based on the available instructions.
10560 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10561 MVT VT, const X86Subtarget *Subtarget,
10562 SelectionDAG &DAG) {
10564 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10565 ArrayRef<int> Mask = SVOp->getMask();
10566 assert(Subtarget->hasAVX512() &&
10567 "Cannot lower 512-bit vectors w/ basic ISA!");
10569 // Check for being able to broadcast a single element.
10570 if (SDValue Broadcast =
10571 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10574 // Dispatch to each element type for lowering. If we don't have supprot for
10575 // specific element type shuffles at 512 bits, immediately split them and
10576 // lower them. Each lowering routine of a given type is allowed to assume that
10577 // the requisite ISA extensions for that element type are available.
10578 switch (VT.SimpleTy) {
10580 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10582 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10584 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10586 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10588 if (Subtarget->hasBWI())
10589 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10592 if (Subtarget->hasBWI())
10593 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10597 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10600 // Otherwise fall back on splitting.
10601 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10604 /// \brief Top-level lowering for x86 vector shuffles.
10606 /// This handles decomposition, canonicalization, and lowering of all x86
10607 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10608 /// above in helper routines. The canonicalization attempts to widen shuffles
10609 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10610 /// s.t. only one of the two inputs needs to be tested, etc.
10611 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10612 SelectionDAG &DAG) {
10613 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10614 ArrayRef<int> Mask = SVOp->getMask();
10615 SDValue V1 = Op.getOperand(0);
10616 SDValue V2 = Op.getOperand(1);
10617 MVT VT = Op.getSimpleValueType();
10618 int NumElements = VT.getVectorNumElements();
10621 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10623 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10624 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10625 if (V1IsUndef && V2IsUndef)
10626 return DAG.getUNDEF(VT);
10628 // When we create a shuffle node we put the UNDEF node to second operand,
10629 // but in some cases the first operand may be transformed to UNDEF.
10630 // In this case we should just commute the node.
10632 return DAG.getCommutedVectorShuffle(*SVOp);
10634 // Check for non-undef masks pointing at an undef vector and make the masks
10635 // undef as well. This makes it easier to match the shuffle based solely on
10639 if (M >= NumElements) {
10640 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10641 for (int &M : NewMask)
10642 if (M >= NumElements)
10644 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10647 // We actually see shuffles that are entirely re-arrangements of a set of
10648 // zero inputs. This mostly happens while decomposing complex shuffles into
10649 // simple ones. Directly lower these as a buildvector of zeros.
10650 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10651 if (Zeroable.all())
10652 return getZeroVector(VT, Subtarget, DAG, dl);
10654 // Try to collapse shuffles into using a vector type with fewer elements but
10655 // wider element types. We cap this to not form integers or floating point
10656 // elements wider than 64 bits, but it might be interesting to form i128
10657 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10658 SmallVector<int, 16> WidenedMask;
10659 if (VT.getScalarSizeInBits() < 64 &&
10660 canWidenShuffleElements(Mask, WidenedMask)) {
10661 MVT NewEltVT = VT.isFloatingPoint()
10662 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10663 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10664 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10665 // Make sure that the new vector type is legal. For example, v2f64 isn't
10667 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10668 V1 = DAG.getBitcast(NewVT, V1);
10669 V2 = DAG.getBitcast(NewVT, V2);
10670 return DAG.getBitcast(
10671 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10675 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10676 for (int M : SVOp->getMask())
10678 ++NumUndefElements;
10679 else if (M < NumElements)
10684 // Commute the shuffle as needed such that more elements come from V1 than
10685 // V2. This allows us to match the shuffle pattern strictly on how many
10686 // elements come from V1 without handling the symmetric cases.
10687 if (NumV2Elements > NumV1Elements)
10688 return DAG.getCommutedVectorShuffle(*SVOp);
10690 // When the number of V1 and V2 elements are the same, try to minimize the
10691 // number of uses of V2 in the low half of the vector. When that is tied,
10692 // ensure that the sum of indices for V1 is equal to or lower than the sum
10693 // indices for V2. When those are equal, try to ensure that the number of odd
10694 // indices for V1 is lower than the number of odd indices for V2.
10695 if (NumV1Elements == NumV2Elements) {
10696 int LowV1Elements = 0, LowV2Elements = 0;
10697 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10698 if (M >= NumElements)
10702 if (LowV2Elements > LowV1Elements) {
10703 return DAG.getCommutedVectorShuffle(*SVOp);
10704 } else if (LowV2Elements == LowV1Elements) {
10705 int SumV1Indices = 0, SumV2Indices = 0;
10706 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10707 if (SVOp->getMask()[i] >= NumElements)
10709 else if (SVOp->getMask()[i] >= 0)
10711 if (SumV2Indices < SumV1Indices) {
10712 return DAG.getCommutedVectorShuffle(*SVOp);
10713 } else if (SumV2Indices == SumV1Indices) {
10714 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10715 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10716 if (SVOp->getMask()[i] >= NumElements)
10717 NumV2OddIndices += i % 2;
10718 else if (SVOp->getMask()[i] >= 0)
10719 NumV1OddIndices += i % 2;
10720 if (NumV2OddIndices < NumV1OddIndices)
10721 return DAG.getCommutedVectorShuffle(*SVOp);
10726 // For each vector width, delegate to a specialized lowering routine.
10727 if (VT.getSizeInBits() == 128)
10728 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10730 if (VT.getSizeInBits() == 256)
10731 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10733 // Force AVX-512 vectors to be scalarized for now.
10734 // FIXME: Implement AVX-512 support!
10735 if (VT.getSizeInBits() == 512)
10736 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10738 llvm_unreachable("Unimplemented!");
10741 // This function assumes its argument is a BUILD_VECTOR of constants or
10742 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10744 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10745 unsigned &MaskValue) {
10747 unsigned NumElems = BuildVector->getNumOperands();
10748 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10749 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10750 unsigned NumElemsInLane = NumElems / NumLanes;
10752 // Blend for v16i16 should be symetric for the both lanes.
10753 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10754 SDValue EltCond = BuildVector->getOperand(i);
10755 SDValue SndLaneEltCond =
10756 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10758 int Lane1Cond = -1, Lane2Cond = -1;
10759 if (isa<ConstantSDNode>(EltCond))
10760 Lane1Cond = !isZero(EltCond);
10761 if (isa<ConstantSDNode>(SndLaneEltCond))
10762 Lane2Cond = !isZero(SndLaneEltCond);
10764 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10765 // Lane1Cond != 0, means we want the first argument.
10766 // Lane1Cond == 0, means we want the second argument.
10767 // The encoding of this argument is 0 for the first argument, 1
10768 // for the second. Therefore, invert the condition.
10769 MaskValue |= !Lane1Cond << i;
10770 else if (Lane1Cond < 0)
10771 MaskValue |= !Lane2Cond << i;
10778 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10779 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10780 const X86Subtarget *Subtarget,
10781 SelectionDAG &DAG) {
10782 SDValue Cond = Op.getOperand(0);
10783 SDValue LHS = Op.getOperand(1);
10784 SDValue RHS = Op.getOperand(2);
10786 MVT VT = Op.getSimpleValueType();
10788 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10790 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10792 // Only non-legal VSELECTs reach this lowering, convert those into generic
10793 // shuffles and re-use the shuffle lowering path for blends.
10794 SmallVector<int, 32> Mask;
10795 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10796 SDValue CondElt = CondBV->getOperand(i);
10798 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10800 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10803 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10804 // A vselect where all conditions and data are constants can be optimized into
10805 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10806 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10807 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10808 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10811 // Try to lower this to a blend-style vector shuffle. This can handle all
10812 // constant condition cases.
10813 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10816 // Variable blends are only legal from SSE4.1 onward.
10817 if (!Subtarget->hasSSE41())
10820 // Only some types will be legal on some subtargets. If we can emit a legal
10821 // VSELECT-matching blend, return Op, and but if we need to expand, return
10823 switch (Op.getSimpleValueType().SimpleTy) {
10825 // Most of the vector types have blends past SSE4.1.
10829 // The byte blends for AVX vectors were introduced only in AVX2.
10830 if (Subtarget->hasAVX2())
10837 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10838 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10841 // FIXME: We should custom lower this by fixing the condition and using i8
10847 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10848 MVT VT = Op.getSimpleValueType();
10851 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10854 if (VT.getSizeInBits() == 8) {
10855 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10856 Op.getOperand(0), Op.getOperand(1));
10857 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10858 DAG.getValueType(VT));
10859 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10862 if (VT.getSizeInBits() == 16) {
10863 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10864 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10866 return DAG.getNode(
10867 ISD::TRUNCATE, dl, MVT::i16,
10868 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10869 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10870 Op.getOperand(1)));
10871 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10872 Op.getOperand(0), Op.getOperand(1));
10873 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10874 DAG.getValueType(VT));
10875 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10878 if (VT == MVT::f32) {
10879 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10880 // the result back to FR32 register. It's only worth matching if the
10881 // result has a single use which is a store or a bitcast to i32. And in
10882 // the case of a store, it's not worth it if the index is a constant 0,
10883 // because a MOVSSmr can be used instead, which is smaller and faster.
10884 if (!Op.hasOneUse())
10886 SDNode *User = *Op.getNode()->use_begin();
10887 if ((User->getOpcode() != ISD::STORE ||
10888 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10889 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10890 (User->getOpcode() != ISD::BITCAST ||
10891 User->getValueType(0) != MVT::i32))
10893 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10894 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10896 return DAG.getBitcast(MVT::f32, Extract);
10899 if (VT == MVT::i32 || VT == MVT::i64) {
10900 // ExtractPS/pextrq works with constant index.
10901 if (isa<ConstantSDNode>(Op.getOperand(1)))
10907 /// Extract one bit from mask vector, like v16i1 or v8i1.
10908 /// AVX-512 feature.
10910 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10911 SDValue Vec = Op.getOperand(0);
10913 MVT VecVT = Vec.getSimpleValueType();
10914 SDValue Idx = Op.getOperand(1);
10915 MVT EltVT = Op.getSimpleValueType();
10917 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10918 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10919 "Unexpected vector type in ExtractBitFromMaskVector");
10921 // variable index can't be handled in mask registers,
10922 // extend vector to VR512
10923 if (!isa<ConstantSDNode>(Idx)) {
10924 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10925 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10926 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10927 ExtVT.getVectorElementType(), Ext, Idx);
10928 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10931 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10932 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10933 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10934 rc = getRegClassFor(MVT::v16i1);
10935 unsigned MaxSift = rc->getSize()*8 - 1;
10936 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10937 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10938 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10939 DAG.getConstant(MaxSift, dl, MVT::i8));
10940 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10941 DAG.getIntPtrConstant(0, dl));
10945 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10946 SelectionDAG &DAG) const {
10948 SDValue Vec = Op.getOperand(0);
10949 MVT VecVT = Vec.getSimpleValueType();
10950 SDValue Idx = Op.getOperand(1);
10952 if (Op.getSimpleValueType() == MVT::i1)
10953 return ExtractBitFromMaskVector(Op, DAG);
10955 if (!isa<ConstantSDNode>(Idx)) {
10956 if (VecVT.is512BitVector() ||
10957 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10958 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10961 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10962 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10963 MaskEltVT.getSizeInBits());
10965 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10966 auto PtrVT = getPointerTy(DAG.getDataLayout());
10967 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10968 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
10969 DAG.getConstant(0, dl, PtrVT));
10970 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10971 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
10972 DAG.getConstant(0, dl, PtrVT));
10977 // If this is a 256-bit vector result, first extract the 128-bit vector and
10978 // then extract the element from the 128-bit vector.
10979 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10981 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10982 // Get the 128-bit vector.
10983 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10984 MVT EltVT = VecVT.getVectorElementType();
10986 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10988 //if (IdxVal >= NumElems/2)
10989 // IdxVal -= NumElems/2;
10990 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10991 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10992 DAG.getConstant(IdxVal, dl, MVT::i32));
10995 assert(VecVT.is128BitVector() && "Unexpected vector length");
10997 if (Subtarget->hasSSE41())
10998 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11001 MVT VT = Op.getSimpleValueType();
11002 // TODO: handle v16i8.
11003 if (VT.getSizeInBits() == 16) {
11004 SDValue Vec = Op.getOperand(0);
11005 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11007 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11008 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11009 DAG.getBitcast(MVT::v4i32, Vec),
11010 Op.getOperand(1)));
11011 // Transform it so it match pextrw which produces a 32-bit result.
11012 MVT EltVT = MVT::i32;
11013 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11014 Op.getOperand(0), Op.getOperand(1));
11015 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11016 DAG.getValueType(VT));
11017 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11020 if (VT.getSizeInBits() == 32) {
11021 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11025 // SHUFPS the element to the lowest double word, then movss.
11026 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11027 MVT VVT = Op.getOperand(0).getSimpleValueType();
11028 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11029 DAG.getUNDEF(VVT), Mask);
11030 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11031 DAG.getIntPtrConstant(0, dl));
11034 if (VT.getSizeInBits() == 64) {
11035 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11036 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11037 // to match extract_elt for f64.
11038 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11042 // UNPCKHPD the element to the lowest double word, then movsd.
11043 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11044 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11045 int Mask[2] = { 1, -1 };
11046 MVT VVT = Op.getOperand(0).getSimpleValueType();
11047 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11048 DAG.getUNDEF(VVT), Mask);
11049 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11050 DAG.getIntPtrConstant(0, dl));
11056 /// Insert one bit to mask vector, like v16i1 or v8i1.
11057 /// AVX-512 feature.
11059 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11061 SDValue Vec = Op.getOperand(0);
11062 SDValue Elt = Op.getOperand(1);
11063 SDValue Idx = Op.getOperand(2);
11064 MVT VecVT = Vec.getSimpleValueType();
11066 if (!isa<ConstantSDNode>(Idx)) {
11067 // Non constant index. Extend source and destination,
11068 // insert element and then truncate the result.
11069 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11070 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11071 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11072 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11073 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11074 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11077 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11078 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11080 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11081 DAG.getConstant(IdxVal, dl, MVT::i8));
11082 if (Vec.getOpcode() == ISD::UNDEF)
11084 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11087 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11088 SelectionDAG &DAG) const {
11089 MVT VT = Op.getSimpleValueType();
11090 MVT EltVT = VT.getVectorElementType();
11092 if (EltVT == MVT::i1)
11093 return InsertBitToMaskVector(Op, DAG);
11096 SDValue N0 = Op.getOperand(0);
11097 SDValue N1 = Op.getOperand(1);
11098 SDValue N2 = Op.getOperand(2);
11099 if (!isa<ConstantSDNode>(N2))
11101 auto *N2C = cast<ConstantSDNode>(N2);
11102 unsigned IdxVal = N2C->getZExtValue();
11104 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11105 // into that, and then insert the subvector back into the result.
11106 if (VT.is256BitVector() || VT.is512BitVector()) {
11107 // With a 256-bit vector, we can insert into the zero element efficiently
11108 // using a blend if we have AVX or AVX2 and the right data type.
11109 if (VT.is256BitVector() && IdxVal == 0) {
11110 // TODO: It is worthwhile to cast integer to floating point and back
11111 // and incur a domain crossing penalty if that's what we'll end up
11112 // doing anyway after extracting to a 128-bit vector.
11113 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11114 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11115 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11116 N2 = DAG.getIntPtrConstant(1, dl);
11117 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11121 // Get the desired 128-bit vector chunk.
11122 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11124 // Insert the element into the desired chunk.
11125 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11126 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11128 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11129 DAG.getConstant(IdxIn128, dl, MVT::i32));
11131 // Insert the changed part back into the bigger vector
11132 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11134 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11136 if (Subtarget->hasSSE41()) {
11137 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11139 if (VT == MVT::v8i16) {
11140 Opc = X86ISD::PINSRW;
11142 assert(VT == MVT::v16i8);
11143 Opc = X86ISD::PINSRB;
11146 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11148 if (N1.getValueType() != MVT::i32)
11149 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11150 if (N2.getValueType() != MVT::i32)
11151 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11152 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11155 if (EltVT == MVT::f32) {
11156 // Bits [7:6] of the constant are the source select. This will always be
11157 // zero here. The DAG Combiner may combine an extract_elt index into
11158 // these bits. For example (insert (extract, 3), 2) could be matched by
11159 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11160 // Bits [5:4] of the constant are the destination select. This is the
11161 // value of the incoming immediate.
11162 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11163 // combine either bitwise AND or insert of float 0.0 to set these bits.
11165 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11166 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11167 // If this is an insertion of 32-bits into the low 32-bits of
11168 // a vector, we prefer to generate a blend with immediate rather
11169 // than an insertps. Blends are simpler operations in hardware and so
11170 // will always have equal or better performance than insertps.
11171 // But if optimizing for size and there's a load folding opportunity,
11172 // generate insertps because blendps does not have a 32-bit memory
11174 N2 = DAG.getIntPtrConstant(1, dl);
11175 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11176 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11178 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11179 // Create this as a scalar to vector..
11180 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11181 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11184 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11185 // PINSR* works with constant index.
11190 if (EltVT == MVT::i8)
11193 if (EltVT.getSizeInBits() == 16) {
11194 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11195 // as its second argument.
11196 if (N1.getValueType() != MVT::i32)
11197 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11198 if (N2.getValueType() != MVT::i32)
11199 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11200 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11205 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11207 MVT OpVT = Op.getSimpleValueType();
11209 // If this is a 256-bit vector result, first insert into a 128-bit
11210 // vector and then insert into the 256-bit vector.
11211 if (!OpVT.is128BitVector()) {
11212 // Insert into a 128-bit vector.
11213 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11214 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11215 OpVT.getVectorNumElements() / SizeFactor);
11217 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11219 // Insert the 128-bit vector.
11220 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11223 if (OpVT == MVT::v1i64 &&
11224 Op.getOperand(0).getValueType() == MVT::i64)
11225 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11227 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11228 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11229 return DAG.getBitcast(
11230 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11233 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11234 // a simple subregister reference or explicit instructions to grab
11235 // upper bits of a vector.
11236 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11237 SelectionDAG &DAG) {
11239 SDValue In = Op.getOperand(0);
11240 SDValue Idx = Op.getOperand(1);
11241 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11242 MVT ResVT = Op.getSimpleValueType();
11243 MVT InVT = In.getSimpleValueType();
11245 if (Subtarget->hasFp256()) {
11246 if (ResVT.is128BitVector() &&
11247 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11248 isa<ConstantSDNode>(Idx)) {
11249 return Extract128BitVector(In, IdxVal, DAG, dl);
11251 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11252 isa<ConstantSDNode>(Idx)) {
11253 return Extract256BitVector(In, IdxVal, DAG, dl);
11259 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11260 // simple superregister reference or explicit instructions to insert
11261 // the upper bits of a vector.
11262 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11263 SelectionDAG &DAG) {
11264 if (!Subtarget->hasAVX())
11268 SDValue Vec = Op.getOperand(0);
11269 SDValue SubVec = Op.getOperand(1);
11270 SDValue Idx = Op.getOperand(2);
11272 if (!isa<ConstantSDNode>(Idx))
11275 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11276 MVT OpVT = Op.getSimpleValueType();
11277 MVT SubVecVT = SubVec.getSimpleValueType();
11279 // Fold two 16-byte subvector loads into one 32-byte load:
11280 // (insert_subvector (insert_subvector undef, (load addr), 0),
11281 // (load addr + 16), Elts/2)
11283 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11284 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11285 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11286 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11287 if (Idx2 && Idx2->getZExtValue() == 0) {
11288 SDValue SubVec2 = Vec.getOperand(1);
11289 // If needed, look through a bitcast to get to the load.
11290 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11291 SubVec2 = SubVec2.getOperand(0);
11293 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11295 unsigned Alignment = FirstLd->getAlignment();
11296 unsigned AS = FirstLd->getAddressSpace();
11297 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11298 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11299 OpVT, AS, Alignment, &Fast) && Fast) {
11300 SDValue Ops[] = { SubVec2, SubVec };
11301 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11308 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11309 SubVecVT.is128BitVector())
11310 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11312 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11313 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11315 if (OpVT.getVectorElementType() == MVT::i1) {
11316 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11318 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11319 SDValue Undef = DAG.getUNDEF(OpVT);
11320 unsigned NumElems = OpVT.getVectorNumElements();
11321 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11323 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11324 // Zero upper bits of the Vec
11325 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11326 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11328 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11330 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11331 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11334 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11336 // Zero upper bits of the Vec2
11337 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11338 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11339 // Zero lower bits of the Vec
11340 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11341 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11342 // Merge them together
11343 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11349 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11350 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11351 // one of the above mentioned nodes. It has to be wrapped because otherwise
11352 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11353 // be used to form addressing mode. These wrapped nodes will be selected
11356 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11357 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11359 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11360 // global base reg.
11361 unsigned char OpFlag = 0;
11362 unsigned WrapperKind = X86ISD::Wrapper;
11363 CodeModel::Model M = DAG.getTarget().getCodeModel();
11365 if (Subtarget->isPICStyleRIPRel() &&
11366 (M == CodeModel::Small || M == CodeModel::Kernel))
11367 WrapperKind = X86ISD::WrapperRIP;
11368 else if (Subtarget->isPICStyleGOT())
11369 OpFlag = X86II::MO_GOTOFF;
11370 else if (Subtarget->isPICStyleStubPIC())
11371 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11373 auto PtrVT = getPointerTy(DAG.getDataLayout());
11374 SDValue Result = DAG.getTargetConstantPool(
11375 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11377 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11378 // With PIC, the address is actually $g + Offset.
11381 DAG.getNode(ISD::ADD, DL, PtrVT,
11382 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11388 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11389 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11391 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11392 // global base reg.
11393 unsigned char OpFlag = 0;
11394 unsigned WrapperKind = X86ISD::Wrapper;
11395 CodeModel::Model M = DAG.getTarget().getCodeModel();
11397 if (Subtarget->isPICStyleRIPRel() &&
11398 (M == CodeModel::Small || M == CodeModel::Kernel))
11399 WrapperKind = X86ISD::WrapperRIP;
11400 else if (Subtarget->isPICStyleGOT())
11401 OpFlag = X86II::MO_GOTOFF;
11402 else if (Subtarget->isPICStyleStubPIC())
11403 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11405 auto PtrVT = getPointerTy(DAG.getDataLayout());
11406 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11408 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11410 // With PIC, the address is actually $g + Offset.
11413 DAG.getNode(ISD::ADD, DL, PtrVT,
11414 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11420 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11421 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11423 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11424 // global base reg.
11425 unsigned char OpFlag = 0;
11426 unsigned WrapperKind = X86ISD::Wrapper;
11427 CodeModel::Model M = DAG.getTarget().getCodeModel();
11429 if (Subtarget->isPICStyleRIPRel() &&
11430 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11431 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11432 OpFlag = X86II::MO_GOTPCREL;
11433 WrapperKind = X86ISD::WrapperRIP;
11434 } else if (Subtarget->isPICStyleGOT()) {
11435 OpFlag = X86II::MO_GOT;
11436 } else if (Subtarget->isPICStyleStubPIC()) {
11437 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11438 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11439 OpFlag = X86II::MO_DARWIN_NONLAZY;
11442 auto PtrVT = getPointerTy(DAG.getDataLayout());
11443 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11446 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11448 // With PIC, the address is actually $g + Offset.
11449 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11450 !Subtarget->is64Bit()) {
11452 DAG.getNode(ISD::ADD, DL, PtrVT,
11453 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11456 // For symbols that require a load from a stub to get the address, emit the
11458 if (isGlobalStubReference(OpFlag))
11459 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11460 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11461 false, false, false, 0);
11467 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11468 // Create the TargetBlockAddressAddress node.
11469 unsigned char OpFlags =
11470 Subtarget->ClassifyBlockAddressReference();
11471 CodeModel::Model M = DAG.getTarget().getCodeModel();
11472 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11473 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11475 auto PtrVT = getPointerTy(DAG.getDataLayout());
11476 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11478 if (Subtarget->isPICStyleRIPRel() &&
11479 (M == CodeModel::Small || M == CodeModel::Kernel))
11480 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11482 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11484 // With PIC, the address is actually $g + Offset.
11485 if (isGlobalRelativeToPICBase(OpFlags)) {
11486 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11487 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11494 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11495 int64_t Offset, SelectionDAG &DAG) const {
11496 // Create the TargetGlobalAddress node, folding in the constant
11497 // offset if it is legal.
11498 unsigned char OpFlags =
11499 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11500 CodeModel::Model M = DAG.getTarget().getCodeModel();
11501 auto PtrVT = getPointerTy(DAG.getDataLayout());
11503 if (OpFlags == X86II::MO_NO_FLAG &&
11504 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11505 // A direct static reference to a global.
11506 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11509 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11512 if (Subtarget->isPICStyleRIPRel() &&
11513 (M == CodeModel::Small || M == CodeModel::Kernel))
11514 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11516 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11518 // With PIC, the address is actually $g + Offset.
11519 if (isGlobalRelativeToPICBase(OpFlags)) {
11520 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11521 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11524 // For globals that require a load from a stub to get the address, emit the
11526 if (isGlobalStubReference(OpFlags))
11527 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11528 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11529 false, false, false, 0);
11531 // If there was a non-zero offset that we didn't fold, create an explicit
11532 // addition for it.
11534 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11535 DAG.getConstant(Offset, dl, PtrVT));
11541 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11542 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11543 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11544 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11548 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11549 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11550 unsigned char OperandFlags, bool LocalDynamic = false) {
11551 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11552 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11554 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11555 GA->getValueType(0),
11559 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11563 SDValue Ops[] = { Chain, TGA, *InFlag };
11564 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11566 SDValue Ops[] = { Chain, TGA };
11567 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11570 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11571 MFI->setAdjustsStack(true);
11572 MFI->setHasCalls(true);
11574 SDValue Flag = Chain.getValue(1);
11575 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11578 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11580 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11583 SDLoc dl(GA); // ? function entry point might be better
11584 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11585 DAG.getNode(X86ISD::GlobalBaseReg,
11586 SDLoc(), PtrVT), InFlag);
11587 InFlag = Chain.getValue(1);
11589 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11592 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11594 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11596 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11597 X86::RAX, X86II::MO_TLSGD);
11600 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11606 // Get the start address of the TLS block for this module.
11607 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11608 .getInfo<X86MachineFunctionInfo>();
11609 MFI->incNumLocalDynamicTLSAccesses();
11613 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11614 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11617 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11618 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11619 InFlag = Chain.getValue(1);
11620 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11621 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11624 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11628 unsigned char OperandFlags = X86II::MO_DTPOFF;
11629 unsigned WrapperKind = X86ISD::Wrapper;
11630 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11631 GA->getValueType(0),
11632 GA->getOffset(), OperandFlags);
11633 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11635 // Add x@dtpoff with the base.
11636 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11639 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11640 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11641 const EVT PtrVT, TLSModel::Model model,
11642 bool is64Bit, bool isPIC) {
11645 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11646 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11647 is64Bit ? 257 : 256));
11649 SDValue ThreadPointer =
11650 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11651 MachinePointerInfo(Ptr), false, false, false, 0);
11653 unsigned char OperandFlags = 0;
11654 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11656 unsigned WrapperKind = X86ISD::Wrapper;
11657 if (model == TLSModel::LocalExec) {
11658 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11659 } else if (model == TLSModel::InitialExec) {
11661 OperandFlags = X86II::MO_GOTTPOFF;
11662 WrapperKind = X86ISD::WrapperRIP;
11664 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11667 llvm_unreachable("Unexpected model");
11670 // emit "addl x@ntpoff,%eax" (local exec)
11671 // or "addl x@indntpoff,%eax" (initial exec)
11672 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11674 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11675 GA->getOffset(), OperandFlags);
11676 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11678 if (model == TLSModel::InitialExec) {
11679 if (isPIC && !is64Bit) {
11680 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11681 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11685 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11686 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11687 false, false, false, 0);
11690 // The address of the thread local variable is the add of the thread
11691 // pointer with the offset of the variable.
11692 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11696 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11698 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11699 const GlobalValue *GV = GA->getGlobal();
11700 auto PtrVT = getPointerTy(DAG.getDataLayout());
11702 if (Subtarget->isTargetELF()) {
11703 if (DAG.getTarget().Options.EmulatedTLS)
11704 return LowerToTLSEmulatedModel(GA, DAG);
11705 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11707 case TLSModel::GeneralDynamic:
11708 if (Subtarget->is64Bit())
11709 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
11710 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
11711 case TLSModel::LocalDynamic:
11712 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
11713 Subtarget->is64Bit());
11714 case TLSModel::InitialExec:
11715 case TLSModel::LocalExec:
11716 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
11717 DAG.getTarget().getRelocationModel() ==
11720 llvm_unreachable("Unknown TLS model.");
11723 if (Subtarget->isTargetDarwin()) {
11724 // Darwin only has one model of TLS. Lower to that.
11725 unsigned char OpFlag = 0;
11726 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11727 X86ISD::WrapperRIP : X86ISD::Wrapper;
11729 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11730 // global base reg.
11731 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11732 !Subtarget->is64Bit();
11734 OpFlag = X86II::MO_TLVP_PIC_BASE;
11736 OpFlag = X86II::MO_TLVP;
11738 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11739 GA->getValueType(0),
11740 GA->getOffset(), OpFlag);
11741 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11743 // With PIC32, the address is actually $g + Offset.
11745 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
11746 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11749 // Lowering the machine isd will make sure everything is in the right
11751 SDValue Chain = DAG.getEntryNode();
11752 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11753 SDValue Args[] = { Chain, Offset };
11754 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11756 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11757 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11758 MFI->setAdjustsStack(true);
11760 // And our return value (tls address) is in the standard call return value
11762 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11763 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
11766 if (Subtarget->isTargetKnownWindowsMSVC() ||
11767 Subtarget->isTargetWindowsGNU()) {
11768 // Just use the implicit TLS architecture
11769 // Need to generate someting similar to:
11770 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11772 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11773 // mov rcx, qword [rdx+rcx*8]
11774 // mov eax, .tls$:tlsvar
11775 // [rax+rcx] contains the address
11776 // Windows 64bit: gs:0x58
11777 // Windows 32bit: fs:__tls_array
11780 SDValue Chain = DAG.getEntryNode();
11782 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11783 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11784 // use its literal value of 0x2C.
11785 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11786 ? Type::getInt8PtrTy(*DAG.getContext(),
11788 : Type::getInt32PtrTy(*DAG.getContext(),
11791 SDValue TlsArray = Subtarget->is64Bit()
11792 ? DAG.getIntPtrConstant(0x58, dl)
11793 : (Subtarget->isTargetWindowsGNU()
11794 ? DAG.getIntPtrConstant(0x2C, dl)
11795 : DAG.getExternalSymbol("_tls_array", PtrVT));
11797 SDValue ThreadPointer =
11798 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
11802 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11803 res = ThreadPointer;
11805 // Load the _tls_index variable
11806 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
11807 if (Subtarget->is64Bit())
11808 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
11809 MachinePointerInfo(), MVT::i32, false, false,
11812 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
11815 auto &DL = DAG.getDataLayout();
11817 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
11818 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
11820 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
11823 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
11826 // Get the offset of start of .tls section
11827 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11828 GA->getValueType(0),
11829 GA->getOffset(), X86II::MO_SECREL);
11830 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
11832 // The address of the thread local variable is the add of the thread
11833 // pointer with the offset of the variable.
11834 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
11837 llvm_unreachable("TLS not implemented for this target.");
11840 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11841 /// and take a 2 x i32 value to shift plus a shift amount.
11842 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11843 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11844 MVT VT = Op.getSimpleValueType();
11845 unsigned VTBits = VT.getSizeInBits();
11847 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11848 SDValue ShOpLo = Op.getOperand(0);
11849 SDValue ShOpHi = Op.getOperand(1);
11850 SDValue ShAmt = Op.getOperand(2);
11851 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11852 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11854 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11855 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11856 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11857 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11858 : DAG.getConstant(0, dl, VT);
11860 SDValue Tmp2, Tmp3;
11861 if (Op.getOpcode() == ISD::SHL_PARTS) {
11862 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11863 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11865 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11866 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11869 // If the shift amount is larger or equal than the width of a part we can't
11870 // rely on the results of shld/shrd. Insert a test and select the appropriate
11871 // values for large shift amounts.
11872 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11873 DAG.getConstant(VTBits, dl, MVT::i8));
11874 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11875 AndNode, DAG.getConstant(0, dl, MVT::i8));
11878 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11879 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11880 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11882 if (Op.getOpcode() == ISD::SHL_PARTS) {
11883 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11884 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11886 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11887 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11890 SDValue Ops[2] = { Lo, Hi };
11891 return DAG.getMergeValues(Ops, dl);
11894 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11895 SelectionDAG &DAG) const {
11896 SDValue Src = Op.getOperand(0);
11897 MVT SrcVT = Src.getSimpleValueType();
11898 MVT VT = Op.getSimpleValueType();
11901 if (SrcVT.isVector()) {
11902 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
11903 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
11904 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
11905 DAG.getUNDEF(SrcVT)));
11907 if (SrcVT.getVectorElementType() == MVT::i1) {
11908 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11909 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11910 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
11915 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11916 "Unknown SINT_TO_FP to lower!");
11918 // These are really Legal; return the operand so the caller accepts it as
11920 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11922 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11923 Subtarget->is64Bit()) {
11927 unsigned Size = SrcVT.getSizeInBits()/8;
11928 MachineFunction &MF = DAG.getMachineFunction();
11929 auto PtrVT = getPointerTy(MF.getDataLayout());
11930 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11931 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
11932 SDValue Chain = DAG.getStore(
11933 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
11934 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
11936 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11939 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11941 SelectionDAG &DAG) const {
11945 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11947 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11949 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11951 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11953 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11954 MachineMemOperand *MMO;
11956 int SSFI = FI->getIndex();
11957 MMO = DAG.getMachineFunction().getMachineMemOperand(
11958 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
11959 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11961 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11962 StackSlot = StackSlot.getOperand(1);
11964 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11965 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11967 Tys, Ops, SrcVT, MMO);
11970 Chain = Result.getValue(1);
11971 SDValue InFlag = Result.getValue(2);
11973 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11974 // shouldn't be necessary except that RFP cannot be live across
11975 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11976 MachineFunction &MF = DAG.getMachineFunction();
11977 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11978 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11979 auto PtrVT = getPointerTy(MF.getDataLayout());
11980 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
11981 Tys = DAG.getVTList(MVT::Other);
11983 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11985 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
11986 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
11987 MachineMemOperand::MOStore, SSFISize, SSFISize);
11989 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11990 Ops, Op.getValueType(), MMO);
11991 Result = DAG.getLoad(
11992 Op.getValueType(), DL, Chain, StackSlot,
11993 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
11994 false, false, false, 0);
12000 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12001 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12002 SelectionDAG &DAG) const {
12003 // This algorithm is not obvious. Here it is what we're trying to output:
12006 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12007 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12009 haddpd %xmm0, %xmm0
12011 pshufd $0x4e, %xmm0, %xmm1
12017 LLVMContext *Context = DAG.getContext();
12019 // Build some magic constants.
12020 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12021 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12022 auto PtrVT = getPointerTy(DAG.getDataLayout());
12023 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12025 SmallVector<Constant*,2> CV1;
12027 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12028 APInt(64, 0x4330000000000000ULL))));
12030 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12031 APInt(64, 0x4530000000000000ULL))));
12032 Constant *C1 = ConstantVector::get(CV1);
12033 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12035 // Load the 64-bit value into an XMM register.
12036 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12039 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12040 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12041 false, false, false, 16);
12043 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12046 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12047 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12048 false, false, false, 16);
12049 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12050 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12053 if (Subtarget->hasSSE3()) {
12054 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12055 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12057 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12058 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12060 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12061 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12064 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12065 DAG.getIntPtrConstant(0, dl));
12068 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12069 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12070 SelectionDAG &DAG) const {
12072 // FP constant to bias correct the final result.
12073 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12076 // Load the 32-bit value into an XMM register.
12077 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12080 // Zero out the upper parts of the register.
12081 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12083 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12084 DAG.getBitcast(MVT::v2f64, Load),
12085 DAG.getIntPtrConstant(0, dl));
12087 // Or the load with the bias.
12088 SDValue Or = DAG.getNode(
12089 ISD::OR, dl, MVT::v2i64,
12090 DAG.getBitcast(MVT::v2i64,
12091 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12092 DAG.getBitcast(MVT::v2i64,
12093 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12095 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12096 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12098 // Subtract the bias.
12099 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12101 // Handle final rounding.
12102 EVT DestVT = Op.getValueType();
12104 if (DestVT.bitsLT(MVT::f64))
12105 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12106 DAG.getIntPtrConstant(0, dl));
12107 if (DestVT.bitsGT(MVT::f64))
12108 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12110 // Handle final rounding.
12114 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12115 const X86Subtarget &Subtarget) {
12116 // The algorithm is the following:
12117 // #ifdef __SSE4_1__
12118 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12119 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12120 // (uint4) 0x53000000, 0xaa);
12122 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12123 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12125 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12126 // return (float4) lo + fhi;
12129 SDValue V = Op->getOperand(0);
12130 EVT VecIntVT = V.getValueType();
12131 bool Is128 = VecIntVT == MVT::v4i32;
12132 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12133 // If we convert to something else than the supported type, e.g., to v4f64,
12135 if (VecFloatVT != Op->getValueType(0))
12138 unsigned NumElts = VecIntVT.getVectorNumElements();
12139 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12140 "Unsupported custom type");
12141 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12143 // In the #idef/#else code, we have in common:
12144 // - The vector of constants:
12150 // Create the splat vector for 0x4b000000.
12151 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12152 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12153 CstLow, CstLow, CstLow, CstLow};
12154 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12155 makeArrayRef(&CstLowArray[0], NumElts));
12156 // Create the splat vector for 0x53000000.
12157 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12158 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12159 CstHigh, CstHigh, CstHigh, CstHigh};
12160 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12161 makeArrayRef(&CstHighArray[0], NumElts));
12163 // Create the right shift.
12164 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12165 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12166 CstShift, CstShift, CstShift, CstShift};
12167 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12168 makeArrayRef(&CstShiftArray[0], NumElts));
12169 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12172 if (Subtarget.hasSSE41()) {
12173 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12174 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12175 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12176 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12177 // Low will be bitcasted right away, so do not bother bitcasting back to its
12179 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12180 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12181 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12182 // (uint4) 0x53000000, 0xaa);
12183 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12184 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12185 // High will be bitcasted right away, so do not bother bitcasting back to
12186 // its original type.
12187 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12188 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12190 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12191 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12192 CstMask, CstMask, CstMask);
12193 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12194 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12195 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12197 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12198 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12201 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12202 SDValue CstFAdd = DAG.getConstantFP(
12203 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12204 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12205 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12206 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12207 makeArrayRef(&CstFAddArray[0], NumElts));
12209 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12210 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12212 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12213 // return (float4) lo + fhi;
12214 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12215 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12218 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12219 SelectionDAG &DAG) const {
12220 SDValue N0 = Op.getOperand(0);
12221 MVT SVT = N0.getSimpleValueType();
12224 switch (SVT.SimpleTy) {
12226 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12231 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12232 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12233 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12237 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12240 if (Subtarget->hasAVX512())
12241 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12242 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12244 llvm_unreachable(nullptr);
12247 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12248 SelectionDAG &DAG) const {
12249 SDValue N0 = Op.getOperand(0);
12251 auto PtrVT = getPointerTy(DAG.getDataLayout());
12253 if (Op.getValueType().isVector())
12254 return lowerUINT_TO_FP_vec(Op, DAG);
12256 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12257 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12258 // the optimization here.
12259 if (DAG.SignBitIsZero(N0))
12260 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12262 MVT SrcVT = N0.getSimpleValueType();
12263 MVT DstVT = Op.getSimpleValueType();
12264 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12265 return LowerUINT_TO_FP_i64(Op, DAG);
12266 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12267 return LowerUINT_TO_FP_i32(Op, DAG);
12268 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12271 // Make a 64-bit buffer, and use it to build an FILD.
12272 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12273 if (SrcVT == MVT::i32) {
12274 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12275 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12276 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12277 StackSlot, MachinePointerInfo(),
12279 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12280 OffsetSlot, MachinePointerInfo(),
12282 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12286 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12287 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12288 StackSlot, MachinePointerInfo(),
12290 // For i64 source, we need to add the appropriate power of 2 if the input
12291 // was negative. This is the same as the optimization in
12292 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12293 // we must be careful to do the computation in x87 extended precision, not
12294 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12295 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12296 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12297 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12298 MachineMemOperand::MOLoad, 8, 8);
12300 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12301 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12302 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12305 APInt FF(32, 0x5F800000ULL);
12307 // Check whether the sign bit is set.
12308 SDValue SignSet = DAG.getSetCC(
12309 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12310 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12312 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12313 SDValue FudgePtr = DAG.getConstantPool(
12314 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12316 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12317 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12318 SDValue Four = DAG.getIntPtrConstant(4, dl);
12319 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12321 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12323 // Load the value out, extending it from f32 to f80.
12324 // FIXME: Avoid the extend by constructing the right constant pool?
12325 SDValue Fudge = DAG.getExtLoad(
12326 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12327 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12328 false, false, false, 4);
12329 // Extend everything to 80 bits to force it to be done on x87.
12330 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12331 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12332 DAG.getIntPtrConstant(0, dl));
12335 std::pair<SDValue,SDValue>
12336 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12337 bool IsSigned, bool IsReplace) const {
12340 EVT DstTy = Op.getValueType();
12341 auto PtrVT = getPointerTy(DAG.getDataLayout());
12343 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12344 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12348 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12349 DstTy.getSimpleVT() >= MVT::i16 &&
12350 "Unknown FP_TO_INT to lower!");
12352 // These are really Legal.
12353 if (DstTy == MVT::i32 &&
12354 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12355 return std::make_pair(SDValue(), SDValue());
12356 if (Subtarget->is64Bit() &&
12357 DstTy == MVT::i64 &&
12358 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12359 return std::make_pair(SDValue(), SDValue());
12361 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12362 // stack slot, or into the FTOL runtime function.
12363 MachineFunction &MF = DAG.getMachineFunction();
12364 unsigned MemSize = DstTy.getSizeInBits()/8;
12365 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12366 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12369 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12370 Opc = X86ISD::WIN_FTOL;
12372 switch (DstTy.getSimpleVT().SimpleTy) {
12373 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12374 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12375 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12376 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12379 SDValue Chain = DAG.getEntryNode();
12380 SDValue Value = Op.getOperand(0);
12381 EVT TheVT = Op.getOperand(0).getValueType();
12382 // FIXME This causes a redundant load/store if the SSE-class value is already
12383 // in memory, such as if it is on the callstack.
12384 if (isScalarFPTypeInSSEReg(TheVT)) {
12385 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12386 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12387 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12389 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12391 Chain, StackSlot, DAG.getValueType(TheVT)
12394 MachineMemOperand *MMO =
12395 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12396 MachineMemOperand::MOLoad, MemSize, MemSize);
12397 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12398 Chain = Value.getValue(1);
12399 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12400 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12403 MachineMemOperand *MMO =
12404 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12405 MachineMemOperand::MOStore, MemSize, MemSize);
12407 if (Opc != X86ISD::WIN_FTOL) {
12408 // Build the FP_TO_INT*_IN_MEM
12409 SDValue Ops[] = { Chain, Value, StackSlot };
12410 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12412 return std::make_pair(FIST, StackSlot);
12414 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12415 DAG.getVTList(MVT::Other, MVT::Glue),
12417 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12418 MVT::i32, ftol.getValue(1));
12419 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12420 MVT::i32, eax.getValue(2));
12421 SDValue Ops[] = { eax, edx };
12422 SDValue pair = IsReplace
12423 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12424 : DAG.getMergeValues(Ops, DL);
12425 return std::make_pair(pair, SDValue());
12429 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12430 const X86Subtarget *Subtarget) {
12431 MVT VT = Op->getSimpleValueType(0);
12432 SDValue In = Op->getOperand(0);
12433 MVT InVT = In.getSimpleValueType();
12436 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12437 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12439 // Optimize vectors in AVX mode:
12442 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12443 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12444 // Concat upper and lower parts.
12447 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12448 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12449 // Concat upper and lower parts.
12452 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12453 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12454 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12457 if (Subtarget->hasInt256())
12458 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12460 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12461 SDValue Undef = DAG.getUNDEF(InVT);
12462 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12463 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12464 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12466 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12467 VT.getVectorNumElements()/2);
12469 OpLo = DAG.getBitcast(HVT, OpLo);
12470 OpHi = DAG.getBitcast(HVT, OpHi);
12472 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12475 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12476 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12477 MVT VT = Op->getSimpleValueType(0);
12478 SDValue In = Op->getOperand(0);
12479 MVT InVT = In.getSimpleValueType();
12481 unsigned int NumElts = VT.getVectorNumElements();
12482 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12485 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12486 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12488 assert(InVT.getVectorElementType() == MVT::i1);
12489 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12491 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12493 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12495 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12496 if (VT.is512BitVector())
12498 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12501 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12502 SelectionDAG &DAG) {
12503 if (Subtarget->hasFp256())
12504 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12510 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12511 SelectionDAG &DAG) {
12513 MVT VT = Op.getSimpleValueType();
12514 SDValue In = Op.getOperand(0);
12515 MVT SVT = In.getSimpleValueType();
12517 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12518 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12520 if (Subtarget->hasFp256())
12521 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12524 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12525 VT.getVectorNumElements() != SVT.getVectorNumElements());
12529 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12531 MVT VT = Op.getSimpleValueType();
12532 SDValue In = Op.getOperand(0);
12533 MVT InVT = In.getSimpleValueType();
12535 if (VT == MVT::i1) {
12536 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12537 "Invalid scalar TRUNCATE operation");
12538 if (InVT.getSizeInBits() >= 32)
12540 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12541 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12543 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12544 "Invalid TRUNCATE operation");
12546 // move vector to mask - truncate solution for SKX
12547 if (VT.getVectorElementType() == MVT::i1) {
12548 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12549 Subtarget->hasBWI())
12550 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12551 if ((InVT.is256BitVector() || InVT.is128BitVector())
12552 && InVT.getScalarSizeInBits() <= 16 &&
12553 Subtarget->hasBWI() && Subtarget->hasVLX())
12554 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12555 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12556 Subtarget->hasDQI())
12557 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12558 if ((InVT.is256BitVector() || InVT.is128BitVector())
12559 && InVT.getScalarSizeInBits() >= 32 &&
12560 Subtarget->hasDQI() && Subtarget->hasVLX())
12561 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12564 if (VT.getVectorElementType() == MVT::i1) {
12565 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12566 unsigned NumElts = InVT.getVectorNumElements();
12567 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12568 if (InVT.getSizeInBits() < 512) {
12569 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12570 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12575 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12576 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12577 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12580 // vpmovqb/w/d, vpmovdb/w, vpmovwb
12581 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
12582 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
12583 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12585 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12586 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12587 if (Subtarget->hasInt256()) {
12588 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12589 In = DAG.getBitcast(MVT::v8i32, In);
12590 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12592 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12593 DAG.getIntPtrConstant(0, DL));
12596 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12597 DAG.getIntPtrConstant(0, DL));
12598 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12599 DAG.getIntPtrConstant(2, DL));
12600 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12601 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12602 static const int ShufMask[] = {0, 2, 4, 6};
12603 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12606 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12607 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12608 if (Subtarget->hasInt256()) {
12609 In = DAG.getBitcast(MVT::v32i8, In);
12611 SmallVector<SDValue,32> pshufbMask;
12612 for (unsigned i = 0; i < 2; ++i) {
12613 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12614 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12615 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12616 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12617 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12618 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12619 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12620 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12621 for (unsigned j = 0; j < 8; ++j)
12622 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12624 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12625 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12626 In = DAG.getBitcast(MVT::v4i64, In);
12628 static const int ShufMask[] = {0, 2, -1, -1};
12629 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12631 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12632 DAG.getIntPtrConstant(0, DL));
12633 return DAG.getBitcast(VT, In);
12636 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12637 DAG.getIntPtrConstant(0, DL));
12639 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12640 DAG.getIntPtrConstant(4, DL));
12642 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12643 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12645 // The PSHUFB mask:
12646 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12647 -1, -1, -1, -1, -1, -1, -1, -1};
12649 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12650 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12651 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12653 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12654 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12656 // The MOVLHPS Mask:
12657 static const int ShufMask2[] = {0, 1, 4, 5};
12658 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12659 return DAG.getBitcast(MVT::v8i16, res);
12662 // Handle truncation of V256 to V128 using shuffles.
12663 if (!VT.is128BitVector() || !InVT.is256BitVector())
12666 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12668 unsigned NumElems = VT.getVectorNumElements();
12669 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12671 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12672 // Prepare truncation shuffle mask
12673 for (unsigned i = 0; i != NumElems; ++i)
12674 MaskVec[i] = i * 2;
12675 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12676 DAG.getUNDEF(NVT), &MaskVec[0]);
12677 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12678 DAG.getIntPtrConstant(0, DL));
12681 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12682 SelectionDAG &DAG) const {
12683 assert(!Op.getSimpleValueType().isVector());
12685 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12686 /*IsSigned=*/ true, /*IsReplace=*/ false);
12687 SDValue FIST = Vals.first, StackSlot = Vals.second;
12688 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12689 if (!FIST.getNode()) return Op;
12691 if (StackSlot.getNode())
12692 // Load the result.
12693 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12694 FIST, StackSlot, MachinePointerInfo(),
12695 false, false, false, 0);
12697 // The node is the result.
12701 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12702 SelectionDAG &DAG) const {
12703 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12704 /*IsSigned=*/ false, /*IsReplace=*/ false);
12705 SDValue FIST = Vals.first, StackSlot = Vals.second;
12706 assert(FIST.getNode() && "Unexpected failure");
12708 if (StackSlot.getNode())
12709 // Load the result.
12710 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12711 FIST, StackSlot, MachinePointerInfo(),
12712 false, false, false, 0);
12714 // The node is the result.
12718 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12720 MVT VT = Op.getSimpleValueType();
12721 SDValue In = Op.getOperand(0);
12722 MVT SVT = In.getSimpleValueType();
12724 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12726 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12727 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12728 In, DAG.getUNDEF(SVT)));
12731 /// The only differences between FABS and FNEG are the mask and the logic op.
12732 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12733 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12734 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12735 "Wrong opcode for lowering FABS or FNEG.");
12737 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12739 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12740 // into an FNABS. We'll lower the FABS after that if it is still in use.
12742 for (SDNode *User : Op->uses())
12743 if (User->getOpcode() == ISD::FNEG)
12747 MVT VT = Op.getSimpleValueType();
12749 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12750 // decide if we should generate a 16-byte constant mask when we only need 4 or
12751 // 8 bytes for the scalar case.
12757 if (VT.isVector()) {
12759 EltVT = VT.getVectorElementType();
12760 NumElts = VT.getVectorNumElements();
12762 // There are no scalar bitwise logical SSE/AVX instructions, so we
12763 // generate a 16-byte vector constant and logic op even for the scalar case.
12764 // Using a 16-byte mask allows folding the load of the mask with
12765 // the logic op, so it can save (~4 bytes) on code size.
12766 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
12768 NumElts = (VT == MVT::f64) ? 2 : 4;
12771 unsigned EltBits = EltVT.getSizeInBits();
12772 LLVMContext *Context = DAG.getContext();
12773 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12775 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12776 Constant *C = ConstantInt::get(*Context, MaskElt);
12777 C = ConstantVector::getSplat(NumElts, C);
12778 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12779 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
12780 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12782 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
12783 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12784 false, false, false, Alignment);
12786 SDValue Op0 = Op.getOperand(0);
12787 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12789 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12790 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12793 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
12795 // For the scalar case extend to a 128-bit vector, perform the logic op,
12796 // and extract the scalar result back out.
12797 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
12798 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
12799 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
12800 DAG.getIntPtrConstant(0, dl));
12803 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12804 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12805 LLVMContext *Context = DAG.getContext();
12806 SDValue Op0 = Op.getOperand(0);
12807 SDValue Op1 = Op.getOperand(1);
12809 MVT VT = Op.getSimpleValueType();
12810 MVT SrcVT = Op1.getSimpleValueType();
12812 // If second operand is smaller, extend it first.
12813 if (SrcVT.bitsLT(VT)) {
12814 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12817 // And if it is bigger, shrink it first.
12818 if (SrcVT.bitsGT(VT)) {
12819 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12823 // At this point the operands and the result should have the same
12824 // type, and that won't be f80 since that is not custom lowered.
12826 const fltSemantics &Sem =
12827 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12828 const unsigned SizeInBits = VT.getSizeInBits();
12830 SmallVector<Constant *, 4> CV(
12831 VT == MVT::f64 ? 2 : 4,
12832 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12834 // First, clear all bits but the sign bit from the second operand (sign).
12835 CV[0] = ConstantFP::get(*Context,
12836 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12837 Constant *C = ConstantVector::get(CV);
12838 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
12839 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
12841 // Perform all logic operations as 16-byte vectors because there are no
12842 // scalar FP logic instructions in SSE. This allows load folding of the
12843 // constants into the logic instructions.
12844 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
12846 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
12847 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12848 false, false, false, 16);
12849 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
12850 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
12852 // Next, clear the sign bit from the first operand (magnitude).
12853 // If it's a constant, we can clear it here.
12854 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12855 APFloat APF = Op0CN->getValueAPF();
12856 // If the magnitude is a positive zero, the sign bit alone is enough.
12857 if (APF.isPosZero())
12858 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
12859 DAG.getIntPtrConstant(0, dl));
12861 CV[0] = ConstantFP::get(*Context, APF);
12863 CV[0] = ConstantFP::get(
12865 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12867 C = ConstantVector::get(CV);
12868 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
12870 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
12871 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12872 false, false, false, 16);
12873 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12874 if (!isa<ConstantFPSDNode>(Op0)) {
12875 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
12876 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
12878 // OR the magnitude value with the sign bit.
12879 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
12880 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
12881 DAG.getIntPtrConstant(0, dl));
12884 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12885 SDValue N0 = Op.getOperand(0);
12887 MVT VT = Op.getSimpleValueType();
12889 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12890 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12891 DAG.getConstant(1, dl, VT));
12892 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12895 // Check whether an OR'd tree is PTEST-able.
12896 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12897 SelectionDAG &DAG) {
12898 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12900 if (!Subtarget->hasSSE41())
12903 if (!Op->hasOneUse())
12906 SDNode *N = Op.getNode();
12909 SmallVector<SDValue, 8> Opnds;
12910 DenseMap<SDValue, unsigned> VecInMap;
12911 SmallVector<SDValue, 8> VecIns;
12912 EVT VT = MVT::Other;
12914 // Recognize a special case where a vector is casted into wide integer to
12916 Opnds.push_back(N->getOperand(0));
12917 Opnds.push_back(N->getOperand(1));
12919 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12920 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12921 // BFS traverse all OR'd operands.
12922 if (I->getOpcode() == ISD::OR) {
12923 Opnds.push_back(I->getOperand(0));
12924 Opnds.push_back(I->getOperand(1));
12925 // Re-evaluate the number of nodes to be traversed.
12926 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12930 // Quit if a non-EXTRACT_VECTOR_ELT
12931 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12934 // Quit if without a constant index.
12935 SDValue Idx = I->getOperand(1);
12936 if (!isa<ConstantSDNode>(Idx))
12939 SDValue ExtractedFromVec = I->getOperand(0);
12940 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12941 if (M == VecInMap.end()) {
12942 VT = ExtractedFromVec.getValueType();
12943 // Quit if not 128/256-bit vector.
12944 if (!VT.is128BitVector() && !VT.is256BitVector())
12946 // Quit if not the same type.
12947 if (VecInMap.begin() != VecInMap.end() &&
12948 VT != VecInMap.begin()->first.getValueType())
12950 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12951 VecIns.push_back(ExtractedFromVec);
12953 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12956 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12957 "Not extracted from 128-/256-bit vector.");
12959 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12961 for (DenseMap<SDValue, unsigned>::const_iterator
12962 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12963 // Quit if not all elements are used.
12964 if (I->second != FullMask)
12968 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12970 // Cast all vectors into TestVT for PTEST.
12971 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12972 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12974 // If more than one full vectors are evaluated, OR them first before PTEST.
12975 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12976 // Each iteration will OR 2 nodes and append the result until there is only
12977 // 1 node left, i.e. the final OR'd value of all vectors.
12978 SDValue LHS = VecIns[Slot];
12979 SDValue RHS = VecIns[Slot + 1];
12980 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12983 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12984 VecIns.back(), VecIns.back());
12987 /// \brief return true if \c Op has a use that doesn't just read flags.
12988 static bool hasNonFlagsUse(SDValue Op) {
12989 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12991 SDNode *User = *UI;
12992 unsigned UOpNo = UI.getOperandNo();
12993 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12994 // Look pass truncate.
12995 UOpNo = User->use_begin().getOperandNo();
12996 User = *User->use_begin();
12999 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13000 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13006 /// Emit nodes that will be selected as "test Op0,Op0", or something
13008 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13009 SelectionDAG &DAG) const {
13010 if (Op.getValueType() == MVT::i1) {
13011 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13012 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13013 DAG.getConstant(0, dl, MVT::i8));
13015 // CF and OF aren't always set the way we want. Determine which
13016 // of these we need.
13017 bool NeedCF = false;
13018 bool NeedOF = false;
13021 case X86::COND_A: case X86::COND_AE:
13022 case X86::COND_B: case X86::COND_BE:
13025 case X86::COND_G: case X86::COND_GE:
13026 case X86::COND_L: case X86::COND_LE:
13027 case X86::COND_O: case X86::COND_NO: {
13028 // Check if we really need to set the
13029 // Overflow flag. If NoSignedWrap is present
13030 // that is not actually needed.
13031 switch (Op->getOpcode()) {
13036 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13037 if (BinNode->Flags.hasNoSignedWrap())
13047 // See if we can use the EFLAGS value from the operand instead of
13048 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13049 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13050 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13051 // Emit a CMP with 0, which is the TEST pattern.
13052 //if (Op.getValueType() == MVT::i1)
13053 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13054 // DAG.getConstant(0, MVT::i1));
13055 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13056 DAG.getConstant(0, dl, Op.getValueType()));
13058 unsigned Opcode = 0;
13059 unsigned NumOperands = 0;
13061 // Truncate operations may prevent the merge of the SETCC instruction
13062 // and the arithmetic instruction before it. Attempt to truncate the operands
13063 // of the arithmetic instruction and use a reduced bit-width instruction.
13064 bool NeedTruncation = false;
13065 SDValue ArithOp = Op;
13066 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13067 SDValue Arith = Op->getOperand(0);
13068 // Both the trunc and the arithmetic op need to have one user each.
13069 if (Arith->hasOneUse())
13070 switch (Arith.getOpcode()) {
13077 NeedTruncation = true;
13083 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13084 // which may be the result of a CAST. We use the variable 'Op', which is the
13085 // non-casted variable when we check for possible users.
13086 switch (ArithOp.getOpcode()) {
13088 // Due to an isel shortcoming, be conservative if this add is likely to be
13089 // selected as part of a load-modify-store instruction. When the root node
13090 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13091 // uses of other nodes in the match, such as the ADD in this case. This
13092 // leads to the ADD being left around and reselected, with the result being
13093 // two adds in the output. Alas, even if none our users are stores, that
13094 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13095 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13096 // climbing the DAG back to the root, and it doesn't seem to be worth the
13098 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13099 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13100 if (UI->getOpcode() != ISD::CopyToReg &&
13101 UI->getOpcode() != ISD::SETCC &&
13102 UI->getOpcode() != ISD::STORE)
13105 if (ConstantSDNode *C =
13106 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13107 // An add of one will be selected as an INC.
13108 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13109 Opcode = X86ISD::INC;
13114 // An add of negative one (subtract of one) will be selected as a DEC.
13115 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13116 Opcode = X86ISD::DEC;
13122 // Otherwise use a regular EFLAGS-setting add.
13123 Opcode = X86ISD::ADD;
13128 // If we have a constant logical shift that's only used in a comparison
13129 // against zero turn it into an equivalent AND. This allows turning it into
13130 // a TEST instruction later.
13131 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13132 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13133 EVT VT = Op.getValueType();
13134 unsigned BitWidth = VT.getSizeInBits();
13135 unsigned ShAmt = Op->getConstantOperandVal(1);
13136 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13138 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13139 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13140 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13141 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13143 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13144 DAG.getConstant(Mask, dl, VT));
13145 DAG.ReplaceAllUsesWith(Op, New);
13151 // If the primary and result isn't used, don't bother using X86ISD::AND,
13152 // because a TEST instruction will be better.
13153 if (!hasNonFlagsUse(Op))
13159 // Due to the ISEL shortcoming noted above, be conservative if this op is
13160 // likely to be selected as part of a load-modify-store instruction.
13161 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13162 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13163 if (UI->getOpcode() == ISD::STORE)
13166 // Otherwise use a regular EFLAGS-setting instruction.
13167 switch (ArithOp.getOpcode()) {
13168 default: llvm_unreachable("unexpected operator!");
13169 case ISD::SUB: Opcode = X86ISD::SUB; break;
13170 case ISD::XOR: Opcode = X86ISD::XOR; break;
13171 case ISD::AND: Opcode = X86ISD::AND; break;
13173 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13174 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13175 if (EFLAGS.getNode())
13178 Opcode = X86ISD::OR;
13192 return SDValue(Op.getNode(), 1);
13198 // If we found that truncation is beneficial, perform the truncation and
13200 if (NeedTruncation) {
13201 EVT VT = Op.getValueType();
13202 SDValue WideVal = Op->getOperand(0);
13203 EVT WideVT = WideVal.getValueType();
13204 unsigned ConvertedOp = 0;
13205 // Use a target machine opcode to prevent further DAGCombine
13206 // optimizations that may separate the arithmetic operations
13207 // from the setcc node.
13208 switch (WideVal.getOpcode()) {
13210 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13211 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13212 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13213 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13214 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13218 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13219 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13220 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13221 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13222 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13228 // Emit a CMP with 0, which is the TEST pattern.
13229 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13230 DAG.getConstant(0, dl, Op.getValueType()));
13232 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13233 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13235 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13236 DAG.ReplaceAllUsesWith(Op, New);
13237 return SDValue(New.getNode(), 1);
13240 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13242 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13243 SDLoc dl, SelectionDAG &DAG) const {
13244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13245 if (C->getAPIntValue() == 0)
13246 return EmitTest(Op0, X86CC, dl, DAG);
13248 if (Op0.getValueType() == MVT::i1)
13249 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13252 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13253 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13254 // Do the comparison at i32 if it's smaller, besides the Atom case.
13255 // This avoids subregister aliasing issues. Keep the smaller reference
13256 // if we're optimizing for size, however, as that'll allow better folding
13257 // of memory operations.
13258 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13259 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13260 !Subtarget->isAtom()) {
13261 unsigned ExtendOp =
13262 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13263 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13264 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13266 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13267 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13268 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13270 return SDValue(Sub.getNode(), 1);
13272 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13275 /// Convert a comparison if required by the subtarget.
13276 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13277 SelectionDAG &DAG) const {
13278 // If the subtarget does not support the FUCOMI instruction, floating-point
13279 // comparisons have to be converted.
13280 if (Subtarget->hasCMov() ||
13281 Cmp.getOpcode() != X86ISD::CMP ||
13282 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13283 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13286 // The instruction selector will select an FUCOM instruction instead of
13287 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13288 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13289 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13291 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13292 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13293 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13294 DAG.getConstant(8, dl, MVT::i8));
13295 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13296 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13299 /// The minimum architected relative accuracy is 2^-12. We need one
13300 /// Newton-Raphson step to have a good float result (24 bits of precision).
13301 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13302 DAGCombinerInfo &DCI,
13303 unsigned &RefinementSteps,
13304 bool &UseOneConstNR) const {
13305 EVT VT = Op.getValueType();
13306 const char *RecipOp;
13308 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13309 // TODO: Add support for AVX512 (v16f32).
13310 // It is likely not profitable to do this for f64 because a double-precision
13311 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13312 // instructions: convert to single, rsqrtss, convert back to double, refine
13313 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13314 // along with FMA, this could be a throughput win.
13315 if (VT == MVT::f32 && Subtarget->hasSSE1())
13317 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13318 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13319 RecipOp = "vec-sqrtf";
13323 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13324 if (!Recips.isEnabled(RecipOp))
13327 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13328 UseOneConstNR = false;
13329 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13332 /// The minimum architected relative accuracy is 2^-12. We need one
13333 /// Newton-Raphson step to have a good float result (24 bits of precision).
13334 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13335 DAGCombinerInfo &DCI,
13336 unsigned &RefinementSteps) const {
13337 EVT VT = Op.getValueType();
13338 const char *RecipOp;
13340 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13341 // TODO: Add support for AVX512 (v16f32).
13342 // It is likely not profitable to do this for f64 because a double-precision
13343 // reciprocal estimate with refinement on x86 prior to FMA requires
13344 // 15 instructions: convert to single, rcpss, convert back to double, refine
13345 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13346 // along with FMA, this could be a throughput win.
13347 if (VT == MVT::f32 && Subtarget->hasSSE1())
13349 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13350 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13351 RecipOp = "vec-divf";
13355 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13356 if (!Recips.isEnabled(RecipOp))
13359 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13360 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13363 /// If we have at least two divisions that use the same divisor, convert to
13364 /// multplication by a reciprocal. This may need to be adjusted for a given
13365 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13366 /// This is because we still need one division to calculate the reciprocal and
13367 /// then we need two multiplies by that reciprocal as replacements for the
13368 /// original divisions.
13369 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13373 static bool isAllOnes(SDValue V) {
13374 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13375 return C && C->isAllOnesValue();
13378 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13379 /// if it's possible.
13380 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13381 SDLoc dl, SelectionDAG &DAG) const {
13382 SDValue Op0 = And.getOperand(0);
13383 SDValue Op1 = And.getOperand(1);
13384 if (Op0.getOpcode() == ISD::TRUNCATE)
13385 Op0 = Op0.getOperand(0);
13386 if (Op1.getOpcode() == ISD::TRUNCATE)
13387 Op1 = Op1.getOperand(0);
13390 if (Op1.getOpcode() == ISD::SHL)
13391 std::swap(Op0, Op1);
13392 if (Op0.getOpcode() == ISD::SHL) {
13393 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13394 if (And00C->getZExtValue() == 1) {
13395 // If we looked past a truncate, check that it's only truncating away
13397 unsigned BitWidth = Op0.getValueSizeInBits();
13398 unsigned AndBitWidth = And.getValueSizeInBits();
13399 if (BitWidth > AndBitWidth) {
13401 DAG.computeKnownBits(Op0, Zeros, Ones);
13402 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13406 RHS = Op0.getOperand(1);
13408 } else if (Op1.getOpcode() == ISD::Constant) {
13409 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13410 uint64_t AndRHSVal = AndRHS->getZExtValue();
13411 SDValue AndLHS = Op0;
13413 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13414 LHS = AndLHS.getOperand(0);
13415 RHS = AndLHS.getOperand(1);
13418 // Use BT if the immediate can't be encoded in a TEST instruction.
13419 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13421 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13425 if (LHS.getNode()) {
13426 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13427 // instruction. Since the shift amount is in-range-or-undefined, we know
13428 // that doing a bittest on the i32 value is ok. We extend to i32 because
13429 // the encoding for the i16 version is larger than the i32 version.
13430 // Also promote i16 to i32 for performance / code size reason.
13431 if (LHS.getValueType() == MVT::i8 ||
13432 LHS.getValueType() == MVT::i16)
13433 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13435 // If the operand types disagree, extend the shift amount to match. Since
13436 // BT ignores high bits (like shifts) we can use anyextend.
13437 if (LHS.getValueType() != RHS.getValueType())
13438 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13440 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13441 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13442 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13443 DAG.getConstant(Cond, dl, MVT::i8), BT);
13449 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13451 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13456 // SSE Condition code mapping:
13465 switch (SetCCOpcode) {
13466 default: llvm_unreachable("Unexpected SETCC condition");
13468 case ISD::SETEQ: SSECC = 0; break;
13470 case ISD::SETGT: Swap = true; // Fallthrough
13472 case ISD::SETOLT: SSECC = 1; break;
13474 case ISD::SETGE: Swap = true; // Fallthrough
13476 case ISD::SETOLE: SSECC = 2; break;
13477 case ISD::SETUO: SSECC = 3; break;
13479 case ISD::SETNE: SSECC = 4; break;
13480 case ISD::SETULE: Swap = true; // Fallthrough
13481 case ISD::SETUGE: SSECC = 5; break;
13482 case ISD::SETULT: Swap = true; // Fallthrough
13483 case ISD::SETUGT: SSECC = 6; break;
13484 case ISD::SETO: SSECC = 7; break;
13486 case ISD::SETONE: SSECC = 8; break;
13489 std::swap(Op0, Op1);
13494 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13495 // ones, and then concatenate the result back.
13496 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13497 MVT VT = Op.getSimpleValueType();
13499 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13500 "Unsupported value type for operation");
13502 unsigned NumElems = VT.getVectorNumElements();
13504 SDValue CC = Op.getOperand(2);
13506 // Extract the LHS vectors
13507 SDValue LHS = Op.getOperand(0);
13508 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13509 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13511 // Extract the RHS vectors
13512 SDValue RHS = Op.getOperand(1);
13513 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13514 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13516 // Issue the operation on the smaller types and concatenate the result back
13517 MVT EltVT = VT.getVectorElementType();
13518 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13519 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13520 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13521 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13524 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13525 SDValue Op0 = Op.getOperand(0);
13526 SDValue Op1 = Op.getOperand(1);
13527 SDValue CC = Op.getOperand(2);
13528 MVT VT = Op.getSimpleValueType();
13531 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13532 "Unexpected type for boolean compare operation");
13533 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13534 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13535 DAG.getConstant(-1, dl, VT));
13536 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13537 DAG.getConstant(-1, dl, VT));
13538 switch (SetCCOpcode) {
13539 default: llvm_unreachable("Unexpected SETCC condition");
13541 // (x == y) -> ~(x ^ y)
13542 return DAG.getNode(ISD::XOR, dl, VT,
13543 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13544 DAG.getConstant(-1, dl, VT));
13546 // (x != y) -> (x ^ y)
13547 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13550 // (x > y) -> (x & ~y)
13551 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13554 // (x < y) -> (~x & y)
13555 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13558 // (x <= y) -> (~x | y)
13559 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13562 // (x >=y) -> (x | ~y)
13563 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13567 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13568 const X86Subtarget *Subtarget) {
13569 SDValue Op0 = Op.getOperand(0);
13570 SDValue Op1 = Op.getOperand(1);
13571 SDValue CC = Op.getOperand(2);
13572 MVT VT = Op.getSimpleValueType();
13575 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13576 Op.getValueType().getScalarType() == MVT::i1 &&
13577 "Cannot set masked compare for this operation");
13579 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13581 bool Unsigned = false;
13584 switch (SetCCOpcode) {
13585 default: llvm_unreachable("Unexpected SETCC condition");
13586 case ISD::SETNE: SSECC = 4; break;
13587 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13588 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13589 case ISD::SETLT: Swap = true; //fall-through
13590 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13591 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13592 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13593 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13594 case ISD::SETULE: Unsigned = true; //fall-through
13595 case ISD::SETLE: SSECC = 2; break;
13599 std::swap(Op0, Op1);
13601 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13602 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13603 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13604 DAG.getConstant(SSECC, dl, MVT::i8));
13607 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13608 /// operand \p Op1. If non-trivial (for example because it's not constant)
13609 /// return an empty value.
13610 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13612 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13616 MVT VT = Op1.getSimpleValueType();
13617 MVT EVT = VT.getVectorElementType();
13618 unsigned n = VT.getVectorNumElements();
13619 SmallVector<SDValue, 8> ULTOp1;
13621 for (unsigned i = 0; i < n; ++i) {
13622 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13623 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13626 // Avoid underflow.
13627 APInt Val = Elt->getAPIntValue();
13631 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13634 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13637 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13638 SelectionDAG &DAG) {
13639 SDValue Op0 = Op.getOperand(0);
13640 SDValue Op1 = Op.getOperand(1);
13641 SDValue CC = Op.getOperand(2);
13642 MVT VT = Op.getSimpleValueType();
13643 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13644 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13649 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13650 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13653 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13654 unsigned Opc = X86ISD::CMPP;
13655 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13656 assert(VT.getVectorNumElements() <= 16);
13657 Opc = X86ISD::CMPM;
13659 // In the two special cases we can't handle, emit two comparisons.
13662 unsigned CombineOpc;
13663 if (SetCCOpcode == ISD::SETUEQ) {
13664 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13666 assert(SetCCOpcode == ISD::SETONE);
13667 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13670 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13671 DAG.getConstant(CC0, dl, MVT::i8));
13672 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13673 DAG.getConstant(CC1, dl, MVT::i8));
13674 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13676 // Handle all other FP comparisons here.
13677 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13678 DAG.getConstant(SSECC, dl, MVT::i8));
13681 // Break 256-bit integer vector compare into smaller ones.
13682 if (VT.is256BitVector() && !Subtarget->hasInt256())
13683 return Lower256IntVSETCC(Op, DAG);
13685 EVT OpVT = Op1.getValueType();
13686 if (OpVT.getVectorElementType() == MVT::i1)
13687 return LowerBoolVSETCC_AVX512(Op, DAG);
13689 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13690 if (Subtarget->hasAVX512()) {
13691 if (Op1.getValueType().is512BitVector() ||
13692 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13693 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13694 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13696 // In AVX-512 architecture setcc returns mask with i1 elements,
13697 // But there is no compare instruction for i8 and i16 elements in KNL.
13698 // We are not talking about 512-bit operands in this case, these
13699 // types are illegal.
13701 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13702 OpVT.getVectorElementType().getSizeInBits() >= 8))
13703 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13704 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13707 // We are handling one of the integer comparisons here. Since SSE only has
13708 // GT and EQ comparisons for integer, swapping operands and multiple
13709 // operations may be required for some comparisons.
13711 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13712 bool Subus = false;
13714 switch (SetCCOpcode) {
13715 default: llvm_unreachable("Unexpected SETCC condition");
13716 case ISD::SETNE: Invert = true;
13717 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13718 case ISD::SETLT: Swap = true;
13719 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13720 case ISD::SETGE: Swap = true;
13721 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13722 Invert = true; break;
13723 case ISD::SETULT: Swap = true;
13724 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13725 FlipSigns = true; break;
13726 case ISD::SETUGE: Swap = true;
13727 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13728 FlipSigns = true; Invert = true; break;
13731 // Special case: Use min/max operations for SETULE/SETUGE
13732 MVT VET = VT.getVectorElementType();
13734 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13735 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13738 switch (SetCCOpcode) {
13740 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
13741 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
13744 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13747 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13748 if (!MinMax && hasSubus) {
13749 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13751 // t = psubus Op0, Op1
13752 // pcmpeq t, <0..0>
13753 switch (SetCCOpcode) {
13755 case ISD::SETULT: {
13756 // If the comparison is against a constant we can turn this into a
13757 // setule. With psubus, setule does not require a swap. This is
13758 // beneficial because the constant in the register is no longer
13759 // destructed as the destination so it can be hoisted out of a loop.
13760 // Only do this pre-AVX since vpcmp* is no longer destructive.
13761 if (Subtarget->hasAVX())
13763 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13764 if (ULEOp1.getNode()) {
13766 Subus = true; Invert = false; Swap = false;
13770 // Psubus is better than flip-sign because it requires no inversion.
13771 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13772 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13776 Opc = X86ISD::SUBUS;
13782 std::swap(Op0, Op1);
13784 // Check that the operation in question is available (most are plain SSE2,
13785 // but PCMPGTQ and PCMPEQQ have different requirements).
13786 if (VT == MVT::v2i64) {
13787 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13788 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13790 // First cast everything to the right type.
13791 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13792 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13794 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13795 // bits of the inputs before performing those operations. The lower
13796 // compare is always unsigned.
13799 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13801 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13802 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13803 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13804 Sign, Zero, Sign, Zero);
13806 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13807 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13809 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13810 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13811 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13813 // Create masks for only the low parts/high parts of the 64 bit integers.
13814 static const int MaskHi[] = { 1, 1, 3, 3 };
13815 static const int MaskLo[] = { 0, 0, 2, 2 };
13816 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13817 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13818 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13820 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13821 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13824 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13826 return DAG.getBitcast(VT, Result);
13829 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13830 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13831 // pcmpeqd + pshufd + pand.
13832 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13834 // First cast everything to the right type.
13835 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13836 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13839 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13841 // Make sure the lower and upper halves are both all-ones.
13842 static const int Mask[] = { 1, 0, 3, 2 };
13843 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13844 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13847 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13849 return DAG.getBitcast(VT, Result);
13853 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13854 // bits of the inputs before performing those operations.
13856 EVT EltVT = VT.getVectorElementType();
13857 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13859 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13860 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13863 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13865 // If the logical-not of the result is required, perform that now.
13867 Result = DAG.getNOT(dl, Result, VT);
13870 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13873 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13874 getZeroVector(VT, Subtarget, DAG, dl));
13879 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13881 MVT VT = Op.getSimpleValueType();
13883 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13885 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13886 && "SetCC type must be 8-bit or 1-bit integer");
13887 SDValue Op0 = Op.getOperand(0);
13888 SDValue Op1 = Op.getOperand(1);
13890 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13892 // Optimize to BT if possible.
13893 // Lower (X & (1 << N)) == 0 to BT(X, N).
13894 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13895 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13896 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13897 Op1.getOpcode() == ISD::Constant &&
13898 cast<ConstantSDNode>(Op1)->isNullValue() &&
13899 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13900 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13901 if (NewSetCC.getNode()) {
13903 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13908 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13910 if (Op1.getOpcode() == ISD::Constant &&
13911 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13912 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13913 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13915 // If the input is a setcc, then reuse the input setcc or use a new one with
13916 // the inverted condition.
13917 if (Op0.getOpcode() == X86ISD::SETCC) {
13918 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13919 bool Invert = (CC == ISD::SETNE) ^
13920 cast<ConstantSDNode>(Op1)->isNullValue();
13924 CCode = X86::GetOppositeBranchCondition(CCode);
13925 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13926 DAG.getConstant(CCode, dl, MVT::i8),
13927 Op0.getOperand(1));
13929 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13933 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13934 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13935 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13937 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13938 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13941 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13942 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13943 if (X86CC == X86::COND_INVALID)
13946 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13947 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13948 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13949 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13951 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13955 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13956 static bool isX86LogicalCmp(SDValue Op) {
13957 unsigned Opc = Op.getNode()->getOpcode();
13958 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13959 Opc == X86ISD::SAHF)
13961 if (Op.getResNo() == 1 &&
13962 (Opc == X86ISD::ADD ||
13963 Opc == X86ISD::SUB ||
13964 Opc == X86ISD::ADC ||
13965 Opc == X86ISD::SBB ||
13966 Opc == X86ISD::SMUL ||
13967 Opc == X86ISD::UMUL ||
13968 Opc == X86ISD::INC ||
13969 Opc == X86ISD::DEC ||
13970 Opc == X86ISD::OR ||
13971 Opc == X86ISD::XOR ||
13972 Opc == X86ISD::AND))
13975 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13981 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13982 if (V.getOpcode() != ISD::TRUNCATE)
13985 SDValue VOp0 = V.getOperand(0);
13986 unsigned InBits = VOp0.getValueSizeInBits();
13987 unsigned Bits = V.getValueSizeInBits();
13988 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13991 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13992 bool addTest = true;
13993 SDValue Cond = Op.getOperand(0);
13994 SDValue Op1 = Op.getOperand(1);
13995 SDValue Op2 = Op.getOperand(2);
13997 EVT VT = Op1.getValueType();
14000 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14001 // are available or VBLENDV if AVX is available.
14002 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14003 if (Cond.getOpcode() == ISD::SETCC &&
14004 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14005 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14006 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14007 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14008 int SSECC = translateX86FSETCC(
14009 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14012 if (Subtarget->hasAVX512()) {
14013 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14014 DAG.getConstant(SSECC, DL, MVT::i8));
14015 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14018 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14019 DAG.getConstant(SSECC, DL, MVT::i8));
14021 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14022 // of 3 logic instructions for size savings and potentially speed.
14023 // Unfortunately, there is no scalar form of VBLENDV.
14025 // If either operand is a constant, don't try this. We can expect to
14026 // optimize away at least one of the logic instructions later in that
14027 // case, so that sequence would be faster than a variable blend.
14029 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14030 // uses XMM0 as the selection register. That may need just as many
14031 // instructions as the AND/ANDN/OR sequence due to register moves, so
14034 if (Subtarget->hasAVX() &&
14035 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14037 // Convert to vectors, do a VSELECT, and convert back to scalar.
14038 // All of the conversions should be optimized away.
14040 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14041 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14042 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14043 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14045 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14046 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14048 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14050 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14051 VSel, DAG.getIntPtrConstant(0, DL));
14053 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14054 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14055 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14059 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14061 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14062 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14063 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14064 Op1Scalar = Op1.getOperand(0);
14066 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14067 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14068 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14069 Op2Scalar = Op2.getOperand(0);
14070 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14071 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14072 Op1Scalar.getValueType(),
14073 Cond, Op1Scalar, Op2Scalar);
14074 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14075 return DAG.getBitcast(VT, newSelect);
14076 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14077 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14078 DAG.getIntPtrConstant(0, DL));
14082 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14083 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14084 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14085 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14086 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14087 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14088 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14090 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14093 if (Cond.getOpcode() == ISD::SETCC) {
14094 SDValue NewCond = LowerSETCC(Cond, DAG);
14095 if (NewCond.getNode())
14099 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14100 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14101 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14102 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14103 if (Cond.getOpcode() == X86ISD::SETCC &&
14104 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14105 isZero(Cond.getOperand(1).getOperand(1))) {
14106 SDValue Cmp = Cond.getOperand(1);
14108 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14110 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14111 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14112 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14114 SDValue CmpOp0 = Cmp.getOperand(0);
14115 // Apply further optimizations for special cases
14116 // (select (x != 0), -1, 0) -> neg & sbb
14117 // (select (x == 0), 0, -1) -> neg & sbb
14118 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14119 if (YC->isNullValue() &&
14120 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14121 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14122 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14123 DAG.getConstant(0, DL,
14124 CmpOp0.getValueType()),
14126 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14127 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14128 SDValue(Neg.getNode(), 1));
14132 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14133 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14134 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14136 SDValue Res = // Res = 0 or -1.
14137 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14138 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14140 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14141 Res = DAG.getNOT(DL, Res, Res.getValueType());
14143 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14144 if (!N2C || !N2C->isNullValue())
14145 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14150 // Look past (and (setcc_carry (cmp ...)), 1).
14151 if (Cond.getOpcode() == ISD::AND &&
14152 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14153 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14154 if (C && C->getAPIntValue() == 1)
14155 Cond = Cond.getOperand(0);
14158 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14159 // setting operand in place of the X86ISD::SETCC.
14160 unsigned CondOpcode = Cond.getOpcode();
14161 if (CondOpcode == X86ISD::SETCC ||
14162 CondOpcode == X86ISD::SETCC_CARRY) {
14163 CC = Cond.getOperand(0);
14165 SDValue Cmp = Cond.getOperand(1);
14166 unsigned Opc = Cmp.getOpcode();
14167 MVT VT = Op.getSimpleValueType();
14169 bool IllegalFPCMov = false;
14170 if (VT.isFloatingPoint() && !VT.isVector() &&
14171 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14172 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14174 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14175 Opc == X86ISD::BT) { // FIXME
14179 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14180 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14181 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14182 Cond.getOperand(0).getValueType() != MVT::i8)) {
14183 SDValue LHS = Cond.getOperand(0);
14184 SDValue RHS = Cond.getOperand(1);
14185 unsigned X86Opcode;
14188 switch (CondOpcode) {
14189 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14190 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14191 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14192 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14193 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14194 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14195 default: llvm_unreachable("unexpected overflowing operator");
14197 if (CondOpcode == ISD::UMULO)
14198 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14201 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14203 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14205 if (CondOpcode == ISD::UMULO)
14206 Cond = X86Op.getValue(2);
14208 Cond = X86Op.getValue(1);
14210 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14215 // Look past the truncate if the high bits are known zero.
14216 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14217 Cond = Cond.getOperand(0);
14219 // We know the result of AND is compared against zero. Try to match
14221 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14222 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14223 if (NewSetCC.getNode()) {
14224 CC = NewSetCC.getOperand(0);
14225 Cond = NewSetCC.getOperand(1);
14232 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14233 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14236 // a < b ? -1 : 0 -> RES = ~setcc_carry
14237 // a < b ? 0 : -1 -> RES = setcc_carry
14238 // a >= b ? -1 : 0 -> RES = setcc_carry
14239 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14240 if (Cond.getOpcode() == X86ISD::SUB) {
14241 Cond = ConvertCmpIfNecessary(Cond, DAG);
14242 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14244 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14245 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14246 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14247 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14249 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14250 return DAG.getNOT(DL, Res, Res.getValueType());
14255 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14256 // widen the cmov and push the truncate through. This avoids introducing a new
14257 // branch during isel and doesn't add any extensions.
14258 if (Op.getValueType() == MVT::i8 &&
14259 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14260 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14261 if (T1.getValueType() == T2.getValueType() &&
14262 // Blacklist CopyFromReg to avoid partial register stalls.
14263 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14264 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14265 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14266 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14270 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14271 // condition is true.
14272 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14273 SDValue Ops[] = { Op2, Op1, CC, Cond };
14274 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14277 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14278 const X86Subtarget *Subtarget,
14279 SelectionDAG &DAG) {
14280 MVT VT = Op->getSimpleValueType(0);
14281 SDValue In = Op->getOperand(0);
14282 MVT InVT = In.getSimpleValueType();
14283 MVT VTElt = VT.getVectorElementType();
14284 MVT InVTElt = InVT.getVectorElementType();
14288 if ((InVTElt == MVT::i1) &&
14289 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14290 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14292 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14293 VTElt.getSizeInBits() <= 16)) ||
14295 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14296 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14298 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14299 VTElt.getSizeInBits() >= 32))))
14300 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14302 unsigned int NumElts = VT.getVectorNumElements();
14304 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14307 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14308 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14309 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14310 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14313 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14314 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14316 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14319 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14321 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14322 if (VT.is512BitVector())
14324 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14327 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14328 const X86Subtarget *Subtarget,
14329 SelectionDAG &DAG) {
14330 SDValue In = Op->getOperand(0);
14331 MVT VT = Op->getSimpleValueType(0);
14332 MVT InVT = In.getSimpleValueType();
14333 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14335 MVT InSVT = InVT.getScalarType();
14336 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14338 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14340 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14345 // SSE41 targets can use the pmovsx* instructions directly.
14346 if (Subtarget->hasSSE41())
14347 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14349 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14353 // As SRAI is only available on i16/i32 types, we expand only up to i32
14354 // and handle i64 separately.
14355 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14356 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14357 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14358 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14359 Curr = DAG.getBitcast(CurrVT, Curr);
14362 SDValue SignExt = Curr;
14363 if (CurrVT != InVT) {
14364 unsigned SignExtShift =
14365 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14366 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14367 DAG.getConstant(SignExtShift, dl, MVT::i8));
14373 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14374 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14375 DAG.getConstant(31, dl, MVT::i8));
14376 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14377 return DAG.getBitcast(VT, Ext);
14383 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14384 SelectionDAG &DAG) {
14385 MVT VT = Op->getSimpleValueType(0);
14386 SDValue In = Op->getOperand(0);
14387 MVT InVT = In.getSimpleValueType();
14390 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14391 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14393 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14394 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14395 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14398 if (Subtarget->hasInt256())
14399 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14401 // Optimize vectors in AVX mode
14402 // Sign extend v8i16 to v8i32 and
14405 // Divide input vector into two parts
14406 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14407 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14408 // concat the vectors to original VT
14410 unsigned NumElems = InVT.getVectorNumElements();
14411 SDValue Undef = DAG.getUNDEF(InVT);
14413 SmallVector<int,8> ShufMask1(NumElems, -1);
14414 for (unsigned i = 0; i != NumElems/2; ++i)
14417 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14419 SmallVector<int,8> ShufMask2(NumElems, -1);
14420 for (unsigned i = 0; i != NumElems/2; ++i)
14421 ShufMask2[i] = i + NumElems/2;
14423 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14425 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14426 VT.getVectorNumElements()/2);
14428 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14429 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14431 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14434 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14435 // may emit an illegal shuffle but the expansion is still better than scalar
14436 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14437 // we'll emit a shuffle and a arithmetic shift.
14438 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14439 // TODO: It is possible to support ZExt by zeroing the undef values during
14440 // the shuffle phase or after the shuffle.
14441 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14442 SelectionDAG &DAG) {
14443 MVT RegVT = Op.getSimpleValueType();
14444 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14445 assert(RegVT.isInteger() &&
14446 "We only custom lower integer vector sext loads.");
14448 // Nothing useful we can do without SSE2 shuffles.
14449 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14451 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14453 EVT MemVT = Ld->getMemoryVT();
14454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14455 unsigned RegSz = RegVT.getSizeInBits();
14457 ISD::LoadExtType Ext = Ld->getExtensionType();
14459 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14460 && "Only anyext and sext are currently implemented.");
14461 assert(MemVT != RegVT && "Cannot extend to the same type");
14462 assert(MemVT.isVector() && "Must load a vector from memory");
14464 unsigned NumElems = RegVT.getVectorNumElements();
14465 unsigned MemSz = MemVT.getSizeInBits();
14466 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14468 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14469 // The only way in which we have a legal 256-bit vector result but not the
14470 // integer 256-bit operations needed to directly lower a sextload is if we
14471 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14472 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14473 // correctly legalized. We do this late to allow the canonical form of
14474 // sextload to persist throughout the rest of the DAG combiner -- it wants
14475 // to fold together any extensions it can, and so will fuse a sign_extend
14476 // of an sextload into a sextload targeting a wider value.
14478 if (MemSz == 128) {
14479 // Just switch this to a normal load.
14480 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14481 "it must be a legal 128-bit vector "
14483 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14484 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14485 Ld->isInvariant(), Ld->getAlignment());
14487 assert(MemSz < 128 &&
14488 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14489 // Do an sext load to a 128-bit vector type. We want to use the same
14490 // number of elements, but elements half as wide. This will end up being
14491 // recursively lowered by this routine, but will succeed as we definitely
14492 // have all the necessary features if we're using AVX1.
14494 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14495 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14497 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14498 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14499 Ld->isNonTemporal(), Ld->isInvariant(),
14500 Ld->getAlignment());
14503 // Replace chain users with the new chain.
14504 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14505 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14507 // Finally, do a normal sign-extend to the desired register.
14508 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14511 // All sizes must be a power of two.
14512 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14513 "Non-power-of-two elements are not custom lowered!");
14515 // Attempt to load the original value using scalar loads.
14516 // Find the largest scalar type that divides the total loaded size.
14517 MVT SclrLoadTy = MVT::i8;
14518 for (MVT Tp : MVT::integer_valuetypes()) {
14519 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14524 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14525 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14527 SclrLoadTy = MVT::f64;
14529 // Calculate the number of scalar loads that we need to perform
14530 // in order to load our vector from memory.
14531 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14533 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14534 "Can only lower sext loads with a single scalar load!");
14536 unsigned loadRegZize = RegSz;
14537 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14540 // Represent our vector as a sequence of elements which are the
14541 // largest scalar that we can load.
14542 EVT LoadUnitVecVT = EVT::getVectorVT(
14543 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14545 // Represent the data using the same element type that is stored in
14546 // memory. In practice, we ''widen'' MemVT.
14548 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14549 loadRegZize / MemVT.getScalarType().getSizeInBits());
14551 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14552 "Invalid vector type");
14554 // We can't shuffle using an illegal type.
14555 assert(TLI.isTypeLegal(WideVecVT) &&
14556 "We only lower types that form legal widened vector types");
14558 SmallVector<SDValue, 8> Chains;
14559 SDValue Ptr = Ld->getBasePtr();
14560 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
14561 TLI.getPointerTy(DAG.getDataLayout()));
14562 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14564 for (unsigned i = 0; i < NumLoads; ++i) {
14565 // Perform a single load.
14566 SDValue ScalarLoad =
14567 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14568 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14569 Ld->getAlignment());
14570 Chains.push_back(ScalarLoad.getValue(1));
14571 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14572 // another round of DAGCombining.
14574 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14576 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14577 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14579 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14582 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14584 // Bitcast the loaded value to a vector of the original element type, in
14585 // the size of the target vector type.
14586 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14587 unsigned SizeRatio = RegSz / MemSz;
14589 if (Ext == ISD::SEXTLOAD) {
14590 // If we have SSE4.1, we can directly emit a VSEXT node.
14591 if (Subtarget->hasSSE41()) {
14592 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14593 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14597 // Otherwise we'll shuffle the small elements in the high bits of the
14598 // larger type and perform an arithmetic shift. If the shift is not legal
14599 // it's better to scalarize.
14600 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14601 "We can't implement a sext load without an arithmetic right shift!");
14603 // Redistribute the loaded elements into the different locations.
14604 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14605 for (unsigned i = 0; i != NumElems; ++i)
14606 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14608 SDValue Shuff = DAG.getVectorShuffle(
14609 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14611 Shuff = DAG.getBitcast(RegVT, Shuff);
14613 // Build the arithmetic shift.
14614 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14615 MemVT.getVectorElementType().getSizeInBits();
14617 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14618 DAG.getConstant(Amt, dl, RegVT));
14620 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14624 // Redistribute the loaded elements into the different locations.
14625 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14626 for (unsigned i = 0; i != NumElems; ++i)
14627 ShuffleVec[i * SizeRatio] = i;
14629 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14630 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14632 // Bitcast to the requested type.
14633 Shuff = DAG.getBitcast(RegVT, Shuff);
14634 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14638 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14639 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14640 // from the AND / OR.
14641 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14642 Opc = Op.getOpcode();
14643 if (Opc != ISD::OR && Opc != ISD::AND)
14645 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14646 Op.getOperand(0).hasOneUse() &&
14647 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14648 Op.getOperand(1).hasOneUse());
14651 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14652 // 1 and that the SETCC node has a single use.
14653 static bool isXor1OfSetCC(SDValue Op) {
14654 if (Op.getOpcode() != ISD::XOR)
14656 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14657 if (N1C && N1C->getAPIntValue() == 1) {
14658 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14659 Op.getOperand(0).hasOneUse();
14664 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14665 bool addTest = true;
14666 SDValue Chain = Op.getOperand(0);
14667 SDValue Cond = Op.getOperand(1);
14668 SDValue Dest = Op.getOperand(2);
14671 bool Inverted = false;
14673 if (Cond.getOpcode() == ISD::SETCC) {
14674 // Check for setcc([su]{add,sub,mul}o == 0).
14675 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14676 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14677 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14678 Cond.getOperand(0).getResNo() == 1 &&
14679 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14680 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14681 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14682 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14683 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14684 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14686 Cond = Cond.getOperand(0);
14688 SDValue NewCond = LowerSETCC(Cond, DAG);
14689 if (NewCond.getNode())
14694 // FIXME: LowerXALUO doesn't handle these!!
14695 else if (Cond.getOpcode() == X86ISD::ADD ||
14696 Cond.getOpcode() == X86ISD::SUB ||
14697 Cond.getOpcode() == X86ISD::SMUL ||
14698 Cond.getOpcode() == X86ISD::UMUL)
14699 Cond = LowerXALUO(Cond, DAG);
14702 // Look pass (and (setcc_carry (cmp ...)), 1).
14703 if (Cond.getOpcode() == ISD::AND &&
14704 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14705 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14706 if (C && C->getAPIntValue() == 1)
14707 Cond = Cond.getOperand(0);
14710 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14711 // setting operand in place of the X86ISD::SETCC.
14712 unsigned CondOpcode = Cond.getOpcode();
14713 if (CondOpcode == X86ISD::SETCC ||
14714 CondOpcode == X86ISD::SETCC_CARRY) {
14715 CC = Cond.getOperand(0);
14717 SDValue Cmp = Cond.getOperand(1);
14718 unsigned Opc = Cmp.getOpcode();
14719 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14720 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14724 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14728 // These can only come from an arithmetic instruction with overflow,
14729 // e.g. SADDO, UADDO.
14730 Cond = Cond.getNode()->getOperand(1);
14736 CondOpcode = Cond.getOpcode();
14737 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14738 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14739 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14740 Cond.getOperand(0).getValueType() != MVT::i8)) {
14741 SDValue LHS = Cond.getOperand(0);
14742 SDValue RHS = Cond.getOperand(1);
14743 unsigned X86Opcode;
14746 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14747 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14749 switch (CondOpcode) {
14750 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14752 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14754 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14757 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14758 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14760 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14762 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14765 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14766 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14767 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14768 default: llvm_unreachable("unexpected overflowing operator");
14771 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14772 if (CondOpcode == ISD::UMULO)
14773 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14776 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14778 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14780 if (CondOpcode == ISD::UMULO)
14781 Cond = X86Op.getValue(2);
14783 Cond = X86Op.getValue(1);
14785 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14789 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14790 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14791 if (CondOpc == ISD::OR) {
14792 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14793 // two branches instead of an explicit OR instruction with a
14795 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14796 isX86LogicalCmp(Cmp)) {
14797 CC = Cond.getOperand(0).getOperand(0);
14798 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14799 Chain, Dest, CC, Cmp);
14800 CC = Cond.getOperand(1).getOperand(0);
14804 } else { // ISD::AND
14805 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14806 // two branches instead of an explicit AND instruction with a
14807 // separate test. However, we only do this if this block doesn't
14808 // have a fall-through edge, because this requires an explicit
14809 // jmp when the condition is false.
14810 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14811 isX86LogicalCmp(Cmp) &&
14812 Op.getNode()->hasOneUse()) {
14813 X86::CondCode CCode =
14814 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14815 CCode = X86::GetOppositeBranchCondition(CCode);
14816 CC = DAG.getConstant(CCode, dl, MVT::i8);
14817 SDNode *User = *Op.getNode()->use_begin();
14818 // Look for an unconditional branch following this conditional branch.
14819 // We need this because we need to reverse the successors in order
14820 // to implement FCMP_OEQ.
14821 if (User->getOpcode() == ISD::BR) {
14822 SDValue FalseBB = User->getOperand(1);
14824 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14825 assert(NewBR == User);
14829 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14830 Chain, Dest, CC, Cmp);
14831 X86::CondCode CCode =
14832 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14833 CCode = X86::GetOppositeBranchCondition(CCode);
14834 CC = DAG.getConstant(CCode, dl, MVT::i8);
14840 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14841 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14842 // It should be transformed during dag combiner except when the condition
14843 // is set by a arithmetics with overflow node.
14844 X86::CondCode CCode =
14845 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14846 CCode = X86::GetOppositeBranchCondition(CCode);
14847 CC = DAG.getConstant(CCode, dl, MVT::i8);
14848 Cond = Cond.getOperand(0).getOperand(1);
14850 } else if (Cond.getOpcode() == ISD::SETCC &&
14851 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14852 // For FCMP_OEQ, we can emit
14853 // two branches instead of an explicit AND instruction with a
14854 // separate test. However, we only do this if this block doesn't
14855 // have a fall-through edge, because this requires an explicit
14856 // jmp when the condition is false.
14857 if (Op.getNode()->hasOneUse()) {
14858 SDNode *User = *Op.getNode()->use_begin();
14859 // Look for an unconditional branch following this conditional branch.
14860 // We need this because we need to reverse the successors in order
14861 // to implement FCMP_OEQ.
14862 if (User->getOpcode() == ISD::BR) {
14863 SDValue FalseBB = User->getOperand(1);
14865 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14866 assert(NewBR == User);
14870 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14871 Cond.getOperand(0), Cond.getOperand(1));
14872 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14873 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14874 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14875 Chain, Dest, CC, Cmp);
14876 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14881 } else if (Cond.getOpcode() == ISD::SETCC &&
14882 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14883 // For FCMP_UNE, we can emit
14884 // two branches instead of an explicit AND instruction with a
14885 // separate test. However, we only do this if this block doesn't
14886 // have a fall-through edge, because this requires an explicit
14887 // jmp when the condition is false.
14888 if (Op.getNode()->hasOneUse()) {
14889 SDNode *User = *Op.getNode()->use_begin();
14890 // Look for an unconditional branch following this conditional branch.
14891 // We need this because we need to reverse the successors in order
14892 // to implement FCMP_UNE.
14893 if (User->getOpcode() == ISD::BR) {
14894 SDValue FalseBB = User->getOperand(1);
14896 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14897 assert(NewBR == User);
14900 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14901 Cond.getOperand(0), Cond.getOperand(1));
14902 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14903 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14904 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14905 Chain, Dest, CC, Cmp);
14906 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14916 // Look pass the truncate if the high bits are known zero.
14917 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14918 Cond = Cond.getOperand(0);
14920 // We know the result of AND is compared against zero. Try to match
14922 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14923 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14924 if (NewSetCC.getNode()) {
14925 CC = NewSetCC.getOperand(0);
14926 Cond = NewSetCC.getOperand(1);
14933 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14934 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14935 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14937 Cond = ConvertCmpIfNecessary(Cond, DAG);
14938 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14939 Chain, Dest, CC, Cond);
14942 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14943 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14944 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14945 // that the guard pages used by the OS virtual memory manager are allocated in
14946 // correct sequence.
14948 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14949 SelectionDAG &DAG) const {
14950 MachineFunction &MF = DAG.getMachineFunction();
14951 bool SplitStack = MF.shouldSplitStack();
14952 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14957 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14958 SDNode* Node = Op.getNode();
14960 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14961 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14962 " not tell us which reg is the stack pointer!");
14963 EVT VT = Node->getValueType(0);
14964 SDValue Tmp1 = SDValue(Node, 0);
14965 SDValue Tmp2 = SDValue(Node, 1);
14966 SDValue Tmp3 = Node->getOperand(2);
14967 SDValue Chain = Tmp1.getOperand(0);
14969 // Chain the dynamic stack allocation so that it doesn't modify the stack
14970 // pointer when other instructions are using the stack.
14971 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14974 SDValue Size = Tmp2.getOperand(1);
14975 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14976 Chain = SP.getValue(1);
14977 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14978 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14979 unsigned StackAlign = TFI.getStackAlignment();
14980 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14981 if (Align > StackAlign)
14982 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14983 DAG.getConstant(-(uint64_t)Align, dl, VT));
14984 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14986 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14987 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14990 SDValue Ops[2] = { Tmp1, Tmp2 };
14991 return DAG.getMergeValues(Ops, dl);
14995 SDValue Chain = Op.getOperand(0);
14996 SDValue Size = Op.getOperand(1);
14997 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14998 EVT VT = Op.getNode()->getValueType(0);
15000 bool Is64Bit = Subtarget->is64Bit();
15001 MVT SPTy = getPointerTy(DAG.getDataLayout());
15004 MachineRegisterInfo &MRI = MF.getRegInfo();
15007 // The 64 bit implementation of segmented stacks needs to clobber both r10
15008 // r11. This makes it impossible to use it along with nested parameters.
15009 const Function *F = MF.getFunction();
15011 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15013 if (I->hasNestAttr())
15014 report_fatal_error("Cannot use segmented stacks with functions that "
15015 "have nested arguments.");
15018 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15019 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15020 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15021 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15022 DAG.getRegister(Vreg, SPTy));
15023 SDValue Ops1[2] = { Value, Chain };
15024 return DAG.getMergeValues(Ops1, dl);
15027 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15029 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15030 Flag = Chain.getValue(1);
15031 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15033 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15035 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15036 unsigned SPReg = RegInfo->getStackRegister();
15037 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15038 Chain = SP.getValue(1);
15041 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15042 DAG.getConstant(-(uint64_t)Align, dl, VT));
15043 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15046 SDValue Ops1[2] = { SP, Chain };
15047 return DAG.getMergeValues(Ops1, dl);
15051 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15052 MachineFunction &MF = DAG.getMachineFunction();
15053 auto PtrVT = getPointerTy(MF.getDataLayout());
15054 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15056 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15059 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15060 // vastart just stores the address of the VarArgsFrameIndex slot into the
15061 // memory location argument.
15062 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15063 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15064 MachinePointerInfo(SV), false, false, 0);
15068 // gp_offset (0 - 6 * 8)
15069 // fp_offset (48 - 48 + 8 * 16)
15070 // overflow_arg_area (point to parameters coming in memory).
15072 SmallVector<SDValue, 8> MemOps;
15073 SDValue FIN = Op.getOperand(1);
15075 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15076 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15078 FIN, MachinePointerInfo(SV), false, false, 0);
15079 MemOps.push_back(Store);
15082 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15083 Store = DAG.getStore(Op.getOperand(0), DL,
15084 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15086 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15087 MemOps.push_back(Store);
15089 // Store ptr to overflow_arg_area
15090 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15091 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15092 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15093 MachinePointerInfo(SV, 8),
15095 MemOps.push_back(Store);
15097 // Store ptr to reg_save_area.
15098 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(8, DL));
15099 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15100 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15101 MachinePointerInfo(SV, 16), false, false, 0);
15102 MemOps.push_back(Store);
15103 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15106 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15107 assert(Subtarget->is64Bit() &&
15108 "LowerVAARG only handles 64-bit va_arg!");
15109 assert((Subtarget->isTargetLinux() ||
15110 Subtarget->isTargetDarwin()) &&
15111 "Unhandled target in LowerVAARG");
15112 assert(Op.getNode()->getNumOperands() == 4);
15113 SDValue Chain = Op.getOperand(0);
15114 SDValue SrcPtr = Op.getOperand(1);
15115 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15116 unsigned Align = Op.getConstantOperandVal(3);
15119 EVT ArgVT = Op.getNode()->getValueType(0);
15120 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15121 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15124 // Decide which area this value should be read from.
15125 // TODO: Implement the AMD64 ABI in its entirety. This simple
15126 // selection mechanism works only for the basic types.
15127 if (ArgVT == MVT::f80) {
15128 llvm_unreachable("va_arg for f80 not yet implemented");
15129 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15130 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15131 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15132 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15134 llvm_unreachable("Unhandled argument type in LowerVAARG");
15137 if (ArgMode == 2) {
15138 // Sanity Check: Make sure using fp_offset makes sense.
15139 assert(!Subtarget->useSoftFloat() &&
15140 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
15141 Attribute::NoImplicitFloat)) &&
15142 Subtarget->hasSSE1());
15145 // Insert VAARG_64 node into the DAG
15146 // VAARG_64 returns two values: Variable Argument Address, Chain
15147 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15148 DAG.getConstant(ArgMode, dl, MVT::i8),
15149 DAG.getConstant(Align, dl, MVT::i32)};
15150 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15151 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15152 VTs, InstOps, MVT::i64,
15153 MachinePointerInfo(SV),
15155 /*Volatile=*/false,
15157 /*WriteMem=*/true);
15158 Chain = VAARG.getValue(1);
15160 // Load the next argument and return it
15161 return DAG.getLoad(ArgVT, dl,
15164 MachinePointerInfo(),
15165 false, false, false, 0);
15168 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15169 SelectionDAG &DAG) {
15170 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15171 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15172 SDValue Chain = Op.getOperand(0);
15173 SDValue DstPtr = Op.getOperand(1);
15174 SDValue SrcPtr = Op.getOperand(2);
15175 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15176 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15179 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15180 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15182 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15185 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15186 // amount is a constant. Takes immediate version of shift as input.
15187 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15188 SDValue SrcOp, uint64_t ShiftAmt,
15189 SelectionDAG &DAG) {
15190 MVT ElementType = VT.getVectorElementType();
15192 // Fold this packed shift into its first operand if ShiftAmt is 0.
15196 // Check for ShiftAmt >= element width
15197 if (ShiftAmt >= ElementType.getSizeInBits()) {
15198 if (Opc == X86ISD::VSRAI)
15199 ShiftAmt = ElementType.getSizeInBits() - 1;
15201 return DAG.getConstant(0, dl, VT);
15204 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15205 && "Unknown target vector shift-by-constant node");
15207 // Fold this packed vector shift into a build vector if SrcOp is a
15208 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15209 if (VT == SrcOp.getSimpleValueType() &&
15210 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15211 SmallVector<SDValue, 8> Elts;
15212 unsigned NumElts = SrcOp->getNumOperands();
15213 ConstantSDNode *ND;
15216 default: llvm_unreachable(nullptr);
15217 case X86ISD::VSHLI:
15218 for (unsigned i=0; i!=NumElts; ++i) {
15219 SDValue CurrentOp = SrcOp->getOperand(i);
15220 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15221 Elts.push_back(CurrentOp);
15224 ND = cast<ConstantSDNode>(CurrentOp);
15225 const APInt &C = ND->getAPIntValue();
15226 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15229 case X86ISD::VSRLI:
15230 for (unsigned i=0; i!=NumElts; ++i) {
15231 SDValue CurrentOp = SrcOp->getOperand(i);
15232 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15233 Elts.push_back(CurrentOp);
15236 ND = cast<ConstantSDNode>(CurrentOp);
15237 const APInt &C = ND->getAPIntValue();
15238 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15241 case X86ISD::VSRAI:
15242 for (unsigned i=0; i!=NumElts; ++i) {
15243 SDValue CurrentOp = SrcOp->getOperand(i);
15244 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15245 Elts.push_back(CurrentOp);
15248 ND = cast<ConstantSDNode>(CurrentOp);
15249 const APInt &C = ND->getAPIntValue();
15250 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15255 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15258 return DAG.getNode(Opc, dl, VT, SrcOp,
15259 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15262 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15263 // may or may not be a constant. Takes immediate version of shift as input.
15264 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15265 SDValue SrcOp, SDValue ShAmt,
15266 SelectionDAG &DAG) {
15267 MVT SVT = ShAmt.getSimpleValueType();
15268 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15270 // Catch shift-by-constant.
15271 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15272 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15273 CShAmt->getZExtValue(), DAG);
15275 // Change opcode to non-immediate version
15277 default: llvm_unreachable("Unknown target vector shift node");
15278 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15279 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15280 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15283 const X86Subtarget &Subtarget =
15284 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15285 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15286 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15287 // Let the shuffle legalizer expand this shift amount node.
15288 SDValue Op0 = ShAmt.getOperand(0);
15289 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15290 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15292 // Need to build a vector containing shift amount.
15293 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15294 SmallVector<SDValue, 4> ShOps;
15295 ShOps.push_back(ShAmt);
15296 if (SVT == MVT::i32) {
15297 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15298 ShOps.push_back(DAG.getUNDEF(SVT));
15300 ShOps.push_back(DAG.getUNDEF(SVT));
15302 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15303 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15306 // The return type has to be a 128-bit type with the same element
15307 // type as the input type.
15308 MVT EltVT = VT.getVectorElementType();
15309 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15311 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15312 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15315 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15316 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15317 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15318 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15319 SDValue PreservedSrc,
15320 const X86Subtarget *Subtarget,
15321 SelectionDAG &DAG) {
15322 EVT VT = Op.getValueType();
15323 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15324 MVT::i1, VT.getVectorNumElements());
15325 SDValue VMask = SDValue();
15326 unsigned OpcodeSelect = ISD::VSELECT;
15329 assert(MaskVT.isSimple() && "invalid mask type");
15331 if (isAllOnes(Mask))
15334 if (MaskVT.bitsGT(Mask.getValueType())) {
15335 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15336 MaskVT.getSizeInBits());
15337 VMask = DAG.getBitcast(MaskVT,
15338 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15340 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15341 Mask.getValueType().getSizeInBits());
15342 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15343 // are extracted by EXTRACT_SUBVECTOR.
15344 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15345 DAG.getBitcast(BitcastVT, Mask),
15346 DAG.getIntPtrConstant(0, dl));
15349 switch (Op.getOpcode()) {
15351 case X86ISD::PCMPEQM:
15352 case X86ISD::PCMPGTM:
15354 case X86ISD::CMPMU:
15355 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15356 case X86ISD::VTRUNC:
15357 case X86ISD::VTRUNCS:
15358 case X86ISD::VTRUNCUS:
15359 // We can't use ISD::VSELECT here because it is not always "Legal"
15360 // for the destination type. For example vpmovqb require only AVX512
15361 // and vselect that can operate on byte element type require BWI
15362 OpcodeSelect = X86ISD::SELECT;
15365 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15366 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15367 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15370 /// \brief Creates an SDNode for a predicated scalar operation.
15371 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15372 /// The mask is coming as MVT::i8 and it should be truncated
15373 /// to MVT::i1 while lowering masking intrinsics.
15374 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15375 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15376 /// for a scalar instruction.
15377 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15378 SDValue PreservedSrc,
15379 const X86Subtarget *Subtarget,
15380 SelectionDAG &DAG) {
15381 if (isAllOnes(Mask))
15384 EVT VT = Op.getValueType();
15386 // The mask should be of type MVT::i1
15387 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15389 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15390 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15391 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15394 static int getSEHRegistrationNodeSize(const Function *Fn) {
15395 if (!Fn->hasPersonalityFn())
15396 report_fatal_error(
15397 "querying registration node size for function without personality");
15398 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15399 // WinEHStatePass for the full struct definition.
15400 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15401 case EHPersonality::MSVC_X86SEH: return 24;
15402 case EHPersonality::MSVC_CXX: return 16;
15405 report_fatal_error("can only recover FP for MSVC EH personality functions");
15408 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15409 /// function or when returning to a parent frame after catching an exception, we
15410 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15411 /// Here's the math:
15412 /// RegNodeBase = EntryEBP - RegNodeSize
15413 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15414 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15415 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15416 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15417 SDValue EntryEBP) {
15418 MachineFunction &MF = DAG.getMachineFunction();
15421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15422 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15424 // It's possible that the parent function no longer has a personality function
15425 // if the exceptional code was optimized away, in which case we just return
15426 // the incoming EBP.
15427 if (!Fn->hasPersonalityFn())
15430 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15432 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15434 MCSymbol *OffsetSym =
15435 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15436 GlobalValue::getRealLinkageName(Fn->getName()));
15437 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15438 SDValue RegNodeFrameOffset =
15439 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15441 // RegNodeBase = EntryEBP - RegNodeSize
15442 // ParentFP = RegNodeBase - RegNodeFrameOffset
15443 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15444 DAG.getConstant(RegNodeSize, dl, PtrVT));
15445 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15448 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15449 SelectionDAG &DAG) {
15451 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15452 EVT VT = Op.getValueType();
15453 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15455 switch(IntrData->Type) {
15456 case INTR_TYPE_1OP:
15457 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15458 case INTR_TYPE_2OP:
15459 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15461 case INTR_TYPE_3OP:
15462 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15463 Op.getOperand(2), Op.getOperand(3));
15464 case INTR_TYPE_4OP:
15465 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15466 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15467 case INTR_TYPE_1OP_MASK_RM: {
15468 SDValue Src = Op.getOperand(1);
15469 SDValue PassThru = Op.getOperand(2);
15470 SDValue Mask = Op.getOperand(3);
15471 SDValue RoundingMode;
15472 // We allways add rounding mode to the Node.
15473 // If the rounding mode is not specified, we add the
15474 // "current direction" mode.
15475 if (Op.getNumOperands() == 4)
15477 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15479 RoundingMode = Op.getOperand(4);
15480 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15481 if (IntrWithRoundingModeOpcode != 0)
15482 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15483 X86::STATIC_ROUNDING::CUR_DIRECTION)
15484 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15485 dl, Op.getValueType(), Src, RoundingMode),
15486 Mask, PassThru, Subtarget, DAG);
15487 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15489 Mask, PassThru, Subtarget, DAG);
15491 case INTR_TYPE_1OP_MASK: {
15492 SDValue Src = Op.getOperand(1);
15493 SDValue PassThru = Op.getOperand(2);
15494 SDValue Mask = Op.getOperand(3);
15495 // We add rounding mode to the Node when
15496 // - RM Opcode is specified and
15497 // - RM is not "current direction".
15498 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15499 if (IntrWithRoundingModeOpcode != 0) {
15500 SDValue Rnd = Op.getOperand(4);
15501 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15502 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15503 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15504 dl, Op.getValueType(),
15506 Mask, PassThru, Subtarget, DAG);
15509 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15510 Mask, PassThru, Subtarget, DAG);
15512 case INTR_TYPE_SCALAR_MASK_RM: {
15513 SDValue Src1 = Op.getOperand(1);
15514 SDValue Src2 = Op.getOperand(2);
15515 SDValue Src0 = Op.getOperand(3);
15516 SDValue Mask = Op.getOperand(4);
15517 // There are 2 kinds of intrinsics in this group:
15518 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
15519 // (2) With rounding mode and sae - 7 operands.
15520 if (Op.getNumOperands() == 6) {
15521 SDValue Sae = Op.getOperand(5);
15522 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15523 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15525 Mask, Src0, Subtarget, DAG);
15527 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15528 SDValue RoundingMode = Op.getOperand(5);
15529 SDValue Sae = Op.getOperand(6);
15530 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15531 RoundingMode, Sae),
15532 Mask, Src0, Subtarget, DAG);
15534 case INTR_TYPE_2OP_MASK: {
15535 SDValue Src1 = Op.getOperand(1);
15536 SDValue Src2 = Op.getOperand(2);
15537 SDValue PassThru = Op.getOperand(3);
15538 SDValue Mask = Op.getOperand(4);
15539 // We specify 2 possible opcodes for intrinsics with rounding modes.
15540 // First, we check if the intrinsic may have non-default rounding mode,
15541 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15542 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15543 if (IntrWithRoundingModeOpcode != 0) {
15544 SDValue Rnd = Op.getOperand(5);
15545 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15546 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15547 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15548 dl, Op.getValueType(),
15550 Mask, PassThru, Subtarget, DAG);
15553 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15555 Mask, PassThru, Subtarget, DAG);
15557 case INTR_TYPE_2OP_MASK_RM: {
15558 SDValue Src1 = Op.getOperand(1);
15559 SDValue Src2 = Op.getOperand(2);
15560 SDValue PassThru = Op.getOperand(3);
15561 SDValue Mask = Op.getOperand(4);
15562 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15563 // First, we check if the intrinsic have rounding mode (6 operands),
15564 // if not, we set rounding mode to "current".
15566 if (Op.getNumOperands() == 6)
15567 Rnd = Op.getOperand(5);
15569 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15570 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15572 Mask, PassThru, Subtarget, DAG);
15574 case INTR_TYPE_3OP_MASK_RM: {
15575 SDValue Src1 = Op.getOperand(1);
15576 SDValue Src2 = Op.getOperand(2);
15577 SDValue Imm = Op.getOperand(3);
15578 SDValue PassThru = Op.getOperand(4);
15579 SDValue Mask = Op.getOperand(5);
15580 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15581 // First, we check if the intrinsic have rounding mode (7 operands),
15582 // if not, we set rounding mode to "current".
15584 if (Op.getNumOperands() == 7)
15585 Rnd = Op.getOperand(6);
15587 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15588 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15589 Src1, Src2, Imm, Rnd),
15590 Mask, PassThru, Subtarget, DAG);
15592 case INTR_TYPE_3OP_MASK: {
15593 SDValue Src1 = Op.getOperand(1);
15594 SDValue Src2 = Op.getOperand(2);
15595 SDValue Src3 = Op.getOperand(3);
15596 SDValue PassThru = Op.getOperand(4);
15597 SDValue Mask = Op.getOperand(5);
15598 // We specify 2 possible opcodes for intrinsics with rounding modes.
15599 // First, we check if the intrinsic may have non-default rounding mode,
15600 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15601 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15602 if (IntrWithRoundingModeOpcode != 0) {
15603 SDValue Rnd = Op.getOperand(6);
15604 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15605 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15606 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15607 dl, Op.getValueType(),
15608 Src1, Src2, Src3, Rnd),
15609 Mask, PassThru, Subtarget, DAG);
15612 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15614 Mask, PassThru, Subtarget, DAG);
15616 case VPERM_3OP_MASKZ:
15617 case VPERM_3OP_MASK:
15620 case FMA_OP_MASK: {
15621 SDValue Src1 = Op.getOperand(1);
15622 SDValue Src2 = Op.getOperand(2);
15623 SDValue Src3 = Op.getOperand(3);
15624 SDValue Mask = Op.getOperand(4);
15625 EVT VT = Op.getValueType();
15626 SDValue PassThru = SDValue();
15628 // set PassThru element
15629 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15630 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15631 else if (IntrData->Type == FMA_OP_MASK3)
15636 // We specify 2 possible opcodes for intrinsics with rounding modes.
15637 // First, we check if the intrinsic may have non-default rounding mode,
15638 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15639 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15640 if (IntrWithRoundingModeOpcode != 0) {
15641 SDValue Rnd = Op.getOperand(5);
15642 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15643 X86::STATIC_ROUNDING::CUR_DIRECTION)
15644 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15645 dl, Op.getValueType(),
15646 Src1, Src2, Src3, Rnd),
15647 Mask, PassThru, Subtarget, DAG);
15649 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15650 dl, Op.getValueType(),
15652 Mask, PassThru, Subtarget, DAG);
15655 case CMP_MASK_CC: {
15656 // Comparison intrinsics with masks.
15657 // Example of transformation:
15658 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15659 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15661 // (v8i1 (insert_subvector undef,
15662 // (v2i1 (and (PCMPEQM %a, %b),
15663 // (extract_subvector
15664 // (v8i1 (bitcast %mask)), 0))), 0))))
15665 EVT VT = Op.getOperand(1).getValueType();
15666 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15667 VT.getVectorNumElements());
15668 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15669 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15670 Mask.getValueType().getSizeInBits());
15672 if (IntrData->Type == CMP_MASK_CC) {
15673 SDValue CC = Op.getOperand(3);
15674 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15675 // We specify 2 possible opcodes for intrinsics with rounding modes.
15676 // First, we check if the intrinsic may have non-default rounding mode,
15677 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15678 if (IntrData->Opc1 != 0) {
15679 SDValue Rnd = Op.getOperand(5);
15680 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15681 X86::STATIC_ROUNDING::CUR_DIRECTION)
15682 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15683 Op.getOperand(2), CC, Rnd);
15685 //default rounding mode
15687 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15688 Op.getOperand(2), CC);
15691 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15692 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15695 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15696 DAG.getTargetConstant(0, dl,
15699 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15700 DAG.getUNDEF(BitcastVT), CmpMask,
15701 DAG.getIntPtrConstant(0, dl));
15702 return DAG.getBitcast(Op.getValueType(), Res);
15704 case COMI: { // Comparison intrinsics
15705 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15706 SDValue LHS = Op.getOperand(1);
15707 SDValue RHS = Op.getOperand(2);
15708 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15709 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15710 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15711 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15712 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15713 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15716 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15717 Op.getOperand(1), Op.getOperand(2), DAG);
15719 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15720 Op.getSimpleValueType(),
15722 Op.getOperand(2), DAG),
15723 Op.getOperand(4), Op.getOperand(3), Subtarget,
15725 case COMPRESS_EXPAND_IN_REG: {
15726 SDValue Mask = Op.getOperand(3);
15727 SDValue DataToCompress = Op.getOperand(1);
15728 SDValue PassThru = Op.getOperand(2);
15729 if (isAllOnes(Mask)) // return data as is
15730 return Op.getOperand(1);
15732 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15734 Mask, PassThru, Subtarget, DAG);
15737 SDValue Mask = Op.getOperand(3);
15738 EVT VT = Op.getValueType();
15739 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15740 VT.getVectorNumElements());
15741 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15742 Mask.getValueType().getSizeInBits());
15744 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15745 DAG.getBitcast(BitcastVT, Mask),
15746 DAG.getIntPtrConstant(0, dl));
15747 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15756 default: return SDValue(); // Don't custom lower most intrinsics.
15758 case Intrinsic::x86_avx2_permd:
15759 case Intrinsic::x86_avx2_permps:
15760 // Operands intentionally swapped. Mask is last operand to intrinsic,
15761 // but second operand for node/instruction.
15762 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15763 Op.getOperand(2), Op.getOperand(1));
15765 // ptest and testp intrinsics. The intrinsic these come from are designed to
15766 // return an integer value, not just an instruction so lower it to the ptest
15767 // or testp pattern and a setcc for the result.
15768 case Intrinsic::x86_sse41_ptestz:
15769 case Intrinsic::x86_sse41_ptestc:
15770 case Intrinsic::x86_sse41_ptestnzc:
15771 case Intrinsic::x86_avx_ptestz_256:
15772 case Intrinsic::x86_avx_ptestc_256:
15773 case Intrinsic::x86_avx_ptestnzc_256:
15774 case Intrinsic::x86_avx_vtestz_ps:
15775 case Intrinsic::x86_avx_vtestc_ps:
15776 case Intrinsic::x86_avx_vtestnzc_ps:
15777 case Intrinsic::x86_avx_vtestz_pd:
15778 case Intrinsic::x86_avx_vtestc_pd:
15779 case Intrinsic::x86_avx_vtestnzc_pd:
15780 case Intrinsic::x86_avx_vtestz_ps_256:
15781 case Intrinsic::x86_avx_vtestc_ps_256:
15782 case Intrinsic::x86_avx_vtestnzc_ps_256:
15783 case Intrinsic::x86_avx_vtestz_pd_256:
15784 case Intrinsic::x86_avx_vtestc_pd_256:
15785 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15786 bool IsTestPacked = false;
15789 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15790 case Intrinsic::x86_avx_vtestz_ps:
15791 case Intrinsic::x86_avx_vtestz_pd:
15792 case Intrinsic::x86_avx_vtestz_ps_256:
15793 case Intrinsic::x86_avx_vtestz_pd_256:
15794 IsTestPacked = true; // Fallthrough
15795 case Intrinsic::x86_sse41_ptestz:
15796 case Intrinsic::x86_avx_ptestz_256:
15798 X86CC = X86::COND_E;
15800 case Intrinsic::x86_avx_vtestc_ps:
15801 case Intrinsic::x86_avx_vtestc_pd:
15802 case Intrinsic::x86_avx_vtestc_ps_256:
15803 case Intrinsic::x86_avx_vtestc_pd_256:
15804 IsTestPacked = true; // Fallthrough
15805 case Intrinsic::x86_sse41_ptestc:
15806 case Intrinsic::x86_avx_ptestc_256:
15808 X86CC = X86::COND_B;
15810 case Intrinsic::x86_avx_vtestnzc_ps:
15811 case Intrinsic::x86_avx_vtestnzc_pd:
15812 case Intrinsic::x86_avx_vtestnzc_ps_256:
15813 case Intrinsic::x86_avx_vtestnzc_pd_256:
15814 IsTestPacked = true; // Fallthrough
15815 case Intrinsic::x86_sse41_ptestnzc:
15816 case Intrinsic::x86_avx_ptestnzc_256:
15818 X86CC = X86::COND_A;
15822 SDValue LHS = Op.getOperand(1);
15823 SDValue RHS = Op.getOperand(2);
15824 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15825 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15826 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15827 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15828 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15830 case Intrinsic::x86_avx512_kortestz_w:
15831 case Intrinsic::x86_avx512_kortestc_w: {
15832 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15833 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15834 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15835 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15836 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15837 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15838 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15841 case Intrinsic::x86_sse42_pcmpistria128:
15842 case Intrinsic::x86_sse42_pcmpestria128:
15843 case Intrinsic::x86_sse42_pcmpistric128:
15844 case Intrinsic::x86_sse42_pcmpestric128:
15845 case Intrinsic::x86_sse42_pcmpistrio128:
15846 case Intrinsic::x86_sse42_pcmpestrio128:
15847 case Intrinsic::x86_sse42_pcmpistris128:
15848 case Intrinsic::x86_sse42_pcmpestris128:
15849 case Intrinsic::x86_sse42_pcmpistriz128:
15850 case Intrinsic::x86_sse42_pcmpestriz128: {
15854 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15855 case Intrinsic::x86_sse42_pcmpistria128:
15856 Opcode = X86ISD::PCMPISTRI;
15857 X86CC = X86::COND_A;
15859 case Intrinsic::x86_sse42_pcmpestria128:
15860 Opcode = X86ISD::PCMPESTRI;
15861 X86CC = X86::COND_A;
15863 case Intrinsic::x86_sse42_pcmpistric128:
15864 Opcode = X86ISD::PCMPISTRI;
15865 X86CC = X86::COND_B;
15867 case Intrinsic::x86_sse42_pcmpestric128:
15868 Opcode = X86ISD::PCMPESTRI;
15869 X86CC = X86::COND_B;
15871 case Intrinsic::x86_sse42_pcmpistrio128:
15872 Opcode = X86ISD::PCMPISTRI;
15873 X86CC = X86::COND_O;
15875 case Intrinsic::x86_sse42_pcmpestrio128:
15876 Opcode = X86ISD::PCMPESTRI;
15877 X86CC = X86::COND_O;
15879 case Intrinsic::x86_sse42_pcmpistris128:
15880 Opcode = X86ISD::PCMPISTRI;
15881 X86CC = X86::COND_S;
15883 case Intrinsic::x86_sse42_pcmpestris128:
15884 Opcode = X86ISD::PCMPESTRI;
15885 X86CC = X86::COND_S;
15887 case Intrinsic::x86_sse42_pcmpistriz128:
15888 Opcode = X86ISD::PCMPISTRI;
15889 X86CC = X86::COND_E;
15891 case Intrinsic::x86_sse42_pcmpestriz128:
15892 Opcode = X86ISD::PCMPESTRI;
15893 X86CC = X86::COND_E;
15896 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15897 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15898 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15899 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15900 DAG.getConstant(X86CC, dl, MVT::i8),
15901 SDValue(PCMP.getNode(), 1));
15902 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15905 case Intrinsic::x86_sse42_pcmpistri128:
15906 case Intrinsic::x86_sse42_pcmpestri128: {
15908 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15909 Opcode = X86ISD::PCMPISTRI;
15911 Opcode = X86ISD::PCMPESTRI;
15913 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15914 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15915 return DAG.getNode(Opcode, dl, VTs, NewOps);
15918 case Intrinsic::x86_seh_lsda: {
15919 // Compute the symbol for the LSDA. We know it'll get emitted later.
15920 MachineFunction &MF = DAG.getMachineFunction();
15921 SDValue Op1 = Op.getOperand(1);
15922 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15923 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15924 GlobalValue::getRealLinkageName(Fn->getName()));
15926 // Generate a simple absolute symbol reference. This intrinsic is only
15927 // supported on 32-bit Windows, which isn't PIC.
15928 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
15929 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15932 case Intrinsic::x86_seh_recoverfp: {
15933 SDValue FnOp = Op.getOperand(1);
15934 SDValue IncomingFPOp = Op.getOperand(2);
15935 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
15936 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
15938 report_fatal_error(
15939 "llvm.x86.seh.recoverfp must take a function as the first argument");
15940 return recoverFramePointer(DAG, Fn, IncomingFPOp);
15943 case Intrinsic::localaddress: {
15944 // Returns one of the stack, base, or frame pointer registers, depending on
15945 // which is used to reference local variables.
15946 MachineFunction &MF = DAG.getMachineFunction();
15947 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15949 if (RegInfo->hasBasePointer(MF))
15950 Reg = RegInfo->getBaseRegister();
15951 else // This function handles the SP or FP case.
15952 Reg = RegInfo->getPtrSizedFrameRegister(MF);
15953 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
15958 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15959 SDValue Src, SDValue Mask, SDValue Base,
15960 SDValue Index, SDValue ScaleOp, SDValue Chain,
15961 const X86Subtarget * Subtarget) {
15963 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15965 llvm_unreachable("Invalid scale type");
15966 unsigned ScaleVal = C->getZExtValue();
15967 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15968 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15970 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15971 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15972 Index.getSimpleValueType().getVectorNumElements());
15974 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15976 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15978 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15979 Mask.getValueType().getSizeInBits());
15981 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15982 // are extracted by EXTRACT_SUBVECTOR.
15983 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15984 DAG.getBitcast(BitcastVT, Mask),
15985 DAG.getIntPtrConstant(0, dl));
15987 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15988 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15989 SDValue Segment = DAG.getRegister(0, MVT::i32);
15990 if (Src.getOpcode() == ISD::UNDEF)
15991 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15992 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15993 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15994 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15995 return DAG.getMergeValues(RetOps, dl);
15998 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15999 SDValue Src, SDValue Mask, SDValue Base,
16000 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16002 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16004 llvm_unreachable("Invalid scale type");
16005 unsigned ScaleVal = C->getZExtValue();
16006 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16007 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16009 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16010 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16011 SDValue Segment = DAG.getRegister(0, MVT::i32);
16012 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16013 Index.getSimpleValueType().getVectorNumElements());
16015 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16017 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16019 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16020 Mask.getValueType().getSizeInBits());
16022 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16023 // are extracted by EXTRACT_SUBVECTOR.
16024 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16025 DAG.getBitcast(BitcastVT, Mask),
16026 DAG.getIntPtrConstant(0, dl));
16028 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16029 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16030 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16031 return SDValue(Res, 1);
16034 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16035 SDValue Mask, SDValue Base, SDValue Index,
16036 SDValue ScaleOp, SDValue Chain) {
16038 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16039 assert(C && "Invalid scale type");
16040 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16041 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16042 SDValue Segment = DAG.getRegister(0, MVT::i32);
16044 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16046 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16048 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16050 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16051 //SDVTList VTs = DAG.getVTList(MVT::Other);
16052 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16053 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16054 return SDValue(Res, 0);
16057 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16058 // read performance monitor counters (x86_rdpmc).
16059 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16060 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16061 SmallVectorImpl<SDValue> &Results) {
16062 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16063 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16066 // The ECX register is used to select the index of the performance counter
16068 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16070 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16072 // Reads the content of a 64-bit performance counter and returns it in the
16073 // registers EDX:EAX.
16074 if (Subtarget->is64Bit()) {
16075 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16076 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16079 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16080 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16083 Chain = HI.getValue(1);
16085 if (Subtarget->is64Bit()) {
16086 // The EAX register is loaded with the low-order 32 bits. The EDX register
16087 // is loaded with the supported high-order bits of the counter.
16088 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16089 DAG.getConstant(32, DL, MVT::i8));
16090 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16091 Results.push_back(Chain);
16095 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16096 SDValue Ops[] = { LO, HI };
16097 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16098 Results.push_back(Pair);
16099 Results.push_back(Chain);
16102 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16103 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16104 // also used to custom lower READCYCLECOUNTER nodes.
16105 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16106 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16107 SmallVectorImpl<SDValue> &Results) {
16108 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16109 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16112 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16113 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16114 // and the EAX register is loaded with the low-order 32 bits.
16115 if (Subtarget->is64Bit()) {
16116 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16117 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16120 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16121 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16124 SDValue Chain = HI.getValue(1);
16126 if (Opcode == X86ISD::RDTSCP_DAG) {
16127 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16129 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16130 // the ECX register. Add 'ecx' explicitly to the chain.
16131 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16133 // Explicitly store the content of ECX at the location passed in input
16134 // to the 'rdtscp' intrinsic.
16135 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16136 MachinePointerInfo(), false, false, 0);
16139 if (Subtarget->is64Bit()) {
16140 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16141 // the EAX register is loaded with the low-order 32 bits.
16142 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16143 DAG.getConstant(32, DL, MVT::i8));
16144 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16145 Results.push_back(Chain);
16149 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16150 SDValue Ops[] = { LO, HI };
16151 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16152 Results.push_back(Pair);
16153 Results.push_back(Chain);
16156 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16157 SelectionDAG &DAG) {
16158 SmallVector<SDValue, 2> Results;
16160 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16162 return DAG.getMergeValues(Results, DL);
16165 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16166 SelectionDAG &DAG) {
16167 MachineFunction &MF = DAG.getMachineFunction();
16168 const Function *Fn = MF.getFunction();
16170 SDValue Chain = Op.getOperand(0);
16172 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16173 "using llvm.x86.seh.restoreframe requires a frame pointer");
16175 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16176 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16178 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16179 unsigned FrameReg =
16180 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16181 unsigned SPReg = RegInfo->getStackRegister();
16182 unsigned SlotSize = RegInfo->getSlotSize();
16184 // Get incoming EBP.
16185 SDValue IncomingEBP =
16186 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16188 // SP is saved in the first field of every registration node, so load
16189 // [EBP-RegNodeSize] into SP.
16190 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16191 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16192 DAG.getConstant(-RegNodeSize, dl, VT));
16194 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16195 false, VT.getScalarSizeInBits() / 8);
16196 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16198 if (!RegInfo->needsStackRealignment(MF)) {
16199 // Adjust EBP to point back to the original frame position.
16200 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16201 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16203 assert(RegInfo->hasBasePointer(MF) &&
16204 "functions with Win32 EH must use frame or base pointer register");
16206 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16207 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16208 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16210 // Reload the spilled EBP value, now that the stack and base pointers are
16212 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16213 X86FI->setHasSEHFramePtrSave(true);
16214 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16215 X86FI->setSEHFramePtrSaveIndex(FI);
16216 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16217 MachinePointerInfo(), false, false, false,
16218 VT.getScalarSizeInBits() / 8);
16219 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16225 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16226 /// return truncate Store/MaskedStore Node
16227 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16231 SDValue Mask = Op.getOperand(4);
16232 SDValue DataToTruncate = Op.getOperand(3);
16233 SDValue Addr = Op.getOperand(2);
16234 SDValue Chain = Op.getOperand(0);
16236 EVT VT = DataToTruncate.getValueType();
16237 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16238 ElementType, VT.getVectorNumElements());
16240 if (isAllOnes(Mask)) // return just a truncate store
16241 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16242 MachinePointerInfo(), SVT, false, false,
16243 SVT.getScalarSizeInBits()/8);
16245 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16246 MVT::i1, VT.getVectorNumElements());
16247 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16248 Mask.getValueType().getSizeInBits());
16249 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16250 // are extracted by EXTRACT_SUBVECTOR.
16251 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16252 DAG.getBitcast(BitcastVT, Mask),
16253 DAG.getIntPtrConstant(0, dl));
16255 MachineMemOperand *MMO = DAG.getMachineFunction().
16256 getMachineMemOperand(MachinePointerInfo(),
16257 MachineMemOperand::MOStore, SVT.getStoreSize(),
16258 SVT.getScalarSizeInBits()/8);
16260 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16261 VMask, SVT, MMO, true);
16264 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16265 SelectionDAG &DAG) {
16266 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16268 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16270 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16271 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16276 switch(IntrData->Type) {
16278 llvm_unreachable("Unknown Intrinsic Type");
16282 // Emit the node with the right value type.
16283 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16284 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16286 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16287 // Otherwise return the value from Rand, which is always 0, casted to i32.
16288 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16289 DAG.getConstant(1, dl, Op->getValueType(1)),
16290 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16291 SDValue(Result.getNode(), 1) };
16292 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16293 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16296 // Return { result, isValid, chain }.
16297 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16298 SDValue(Result.getNode(), 2));
16301 //gather(v1, mask, index, base, scale);
16302 SDValue Chain = Op.getOperand(0);
16303 SDValue Src = Op.getOperand(2);
16304 SDValue Base = Op.getOperand(3);
16305 SDValue Index = Op.getOperand(4);
16306 SDValue Mask = Op.getOperand(5);
16307 SDValue Scale = Op.getOperand(6);
16308 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16312 //scatter(base, mask, index, v1, scale);
16313 SDValue Chain = Op.getOperand(0);
16314 SDValue Base = Op.getOperand(2);
16315 SDValue Mask = Op.getOperand(3);
16316 SDValue Index = Op.getOperand(4);
16317 SDValue Src = Op.getOperand(5);
16318 SDValue Scale = Op.getOperand(6);
16319 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16323 SDValue Hint = Op.getOperand(6);
16324 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16325 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16326 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16327 SDValue Chain = Op.getOperand(0);
16328 SDValue Mask = Op.getOperand(2);
16329 SDValue Index = Op.getOperand(3);
16330 SDValue Base = Op.getOperand(4);
16331 SDValue Scale = Op.getOperand(5);
16332 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16334 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16336 SmallVector<SDValue, 2> Results;
16337 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16339 return DAG.getMergeValues(Results, dl);
16341 // Read Performance Monitoring Counters.
16343 SmallVector<SDValue, 2> Results;
16344 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16345 return DAG.getMergeValues(Results, dl);
16347 // XTEST intrinsics.
16349 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16350 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16351 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16352 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16354 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16355 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16356 Ret, SDValue(InTrans.getNode(), 1));
16360 SmallVector<SDValue, 2> Results;
16361 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16362 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16363 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16364 DAG.getConstant(-1, dl, MVT::i8));
16365 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16366 Op.getOperand(4), GenCF.getValue(1));
16367 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16368 Op.getOperand(5), MachinePointerInfo(),
16370 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16371 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16373 Results.push_back(SetCC);
16374 Results.push_back(Store);
16375 return DAG.getMergeValues(Results, dl);
16377 case COMPRESS_TO_MEM: {
16379 SDValue Mask = Op.getOperand(4);
16380 SDValue DataToCompress = Op.getOperand(3);
16381 SDValue Addr = Op.getOperand(2);
16382 SDValue Chain = Op.getOperand(0);
16384 EVT VT = DataToCompress.getValueType();
16385 if (isAllOnes(Mask)) // return just a store
16386 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16387 MachinePointerInfo(), false, false,
16388 VT.getScalarSizeInBits()/8);
16390 SDValue Compressed =
16391 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16392 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16393 return DAG.getStore(Chain, dl, Compressed, Addr,
16394 MachinePointerInfo(), false, false,
16395 VT.getScalarSizeInBits()/8);
16397 case TRUNCATE_TO_MEM_VI8:
16398 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16399 case TRUNCATE_TO_MEM_VI16:
16400 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16401 case TRUNCATE_TO_MEM_VI32:
16402 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16403 case EXPAND_FROM_MEM: {
16405 SDValue Mask = Op.getOperand(4);
16406 SDValue PassThru = Op.getOperand(3);
16407 SDValue Addr = Op.getOperand(2);
16408 SDValue Chain = Op.getOperand(0);
16409 EVT VT = Op.getValueType();
16411 if (isAllOnes(Mask)) // return just a load
16412 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16413 false, VT.getScalarSizeInBits()/8);
16415 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16416 false, false, false,
16417 VT.getScalarSizeInBits()/8);
16419 SDValue Results[] = {
16420 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16421 Mask, PassThru, Subtarget, DAG), Chain};
16422 return DAG.getMergeValues(Results, dl);
16427 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16428 SelectionDAG &DAG) const {
16429 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16430 MFI->setReturnAddressIsTaken(true);
16432 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16435 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16437 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16440 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16441 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16442 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16443 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16444 DAG.getNode(ISD::ADD, dl, PtrVT,
16445 FrameAddr, Offset),
16446 MachinePointerInfo(), false, false, false, 0);
16449 // Just load the return address.
16450 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16451 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16452 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16455 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16456 MachineFunction &MF = DAG.getMachineFunction();
16457 MachineFrameInfo *MFI = MF.getFrameInfo();
16458 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16459 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16460 EVT VT = Op.getValueType();
16462 MFI->setFrameAddressIsTaken(true);
16464 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
16465 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
16466 // is not possible to crawl up the stack without looking at the unwind codes
16468 int FrameAddrIndex = FuncInfo->getFAIndex();
16469 if (!FrameAddrIndex) {
16470 // Set up a frame object for the return address.
16471 unsigned SlotSize = RegInfo->getSlotSize();
16472 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
16473 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
16474 FuncInfo->setFAIndex(FrameAddrIndex);
16476 return DAG.getFrameIndex(FrameAddrIndex, VT);
16479 unsigned FrameReg =
16480 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16481 SDLoc dl(Op); // FIXME probably not meaningful
16482 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16483 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16484 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16485 "Invalid Frame Register!");
16486 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16488 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16489 MachinePointerInfo(),
16490 false, false, false, 0);
16494 // FIXME? Maybe this could be a TableGen attribute on some registers and
16495 // this table could be generated automatically from RegInfo.
16496 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
16497 SelectionDAG &DAG) const {
16498 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16499 const MachineFunction &MF = DAG.getMachineFunction();
16501 unsigned Reg = StringSwitch<unsigned>(RegName)
16502 .Case("esp", X86::ESP)
16503 .Case("rsp", X86::RSP)
16504 .Case("ebp", X86::EBP)
16505 .Case("rbp", X86::RBP)
16508 if (Reg == X86::EBP || Reg == X86::RBP) {
16509 if (!TFI.hasFP(MF))
16510 report_fatal_error("register " + StringRef(RegName) +
16511 " is allocatable: function has no frame pointer");
16514 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16515 unsigned FrameReg =
16516 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16517 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
16518 "Invalid Frame Register!");
16526 report_fatal_error("Invalid register name global variable");
16529 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16530 SelectionDAG &DAG) const {
16531 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16532 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16535 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16536 SDValue Chain = Op.getOperand(0);
16537 SDValue Offset = Op.getOperand(1);
16538 SDValue Handler = Op.getOperand(2);
16541 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16542 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16543 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16544 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16545 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16546 "Invalid Frame Register!");
16547 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16548 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16550 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16551 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16553 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16554 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16556 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16558 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16559 DAG.getRegister(StoreAddrReg, PtrVT));
16562 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16563 SelectionDAG &DAG) const {
16565 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16566 DAG.getVTList(MVT::i32, MVT::Other),
16567 Op.getOperand(0), Op.getOperand(1));
16570 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16571 SelectionDAG &DAG) const {
16573 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16574 Op.getOperand(0), Op.getOperand(1));
16577 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16578 return Op.getOperand(0);
16581 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16582 SelectionDAG &DAG) const {
16583 SDValue Root = Op.getOperand(0);
16584 SDValue Trmp = Op.getOperand(1); // trampoline
16585 SDValue FPtr = Op.getOperand(2); // nested function
16586 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16589 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16590 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16592 if (Subtarget->is64Bit()) {
16593 SDValue OutChains[6];
16595 // Large code-model.
16596 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16597 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16599 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16600 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16602 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16604 // Load the pointer to the nested function into R11.
16605 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16606 SDValue Addr = Trmp;
16607 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16608 Addr, MachinePointerInfo(TrmpAddr),
16611 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16612 DAG.getConstant(2, dl, MVT::i64));
16613 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16614 MachinePointerInfo(TrmpAddr, 2),
16617 // Load the 'nest' parameter value into R10.
16618 // R10 is specified in X86CallingConv.td
16619 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16620 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16621 DAG.getConstant(10, dl, MVT::i64));
16622 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16623 Addr, MachinePointerInfo(TrmpAddr, 10),
16626 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16627 DAG.getConstant(12, dl, MVT::i64));
16628 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16629 MachinePointerInfo(TrmpAddr, 12),
16632 // Jump to the nested function.
16633 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16634 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16635 DAG.getConstant(20, dl, MVT::i64));
16636 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16637 Addr, MachinePointerInfo(TrmpAddr, 20),
16640 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16641 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16642 DAG.getConstant(22, dl, MVT::i64));
16643 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16644 Addr, MachinePointerInfo(TrmpAddr, 22),
16647 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16649 const Function *Func =
16650 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16651 CallingConv::ID CC = Func->getCallingConv();
16656 llvm_unreachable("Unsupported calling convention");
16657 case CallingConv::C:
16658 case CallingConv::X86_StdCall: {
16659 // Pass 'nest' parameter in ECX.
16660 // Must be kept in sync with X86CallingConv.td
16661 NestReg = X86::ECX;
16663 // Check that ECX wasn't needed by an 'inreg' parameter.
16664 FunctionType *FTy = Func->getFunctionType();
16665 const AttributeSet &Attrs = Func->getAttributes();
16667 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16668 unsigned InRegCount = 0;
16671 for (FunctionType::param_iterator I = FTy->param_begin(),
16672 E = FTy->param_end(); I != E; ++I, ++Idx)
16673 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
16674 auto &DL = DAG.getDataLayout();
16675 // FIXME: should only count parameters that are lowered to integers.
16676 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
16679 if (InRegCount > 2) {
16680 report_fatal_error("Nest register in use - reduce number of inreg"
16686 case CallingConv::X86_FastCall:
16687 case CallingConv::X86_ThisCall:
16688 case CallingConv::Fast:
16689 // Pass 'nest' parameter in EAX.
16690 // Must be kept in sync with X86CallingConv.td
16691 NestReg = X86::EAX;
16695 SDValue OutChains[4];
16696 SDValue Addr, Disp;
16698 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16699 DAG.getConstant(10, dl, MVT::i32));
16700 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16702 // This is storing the opcode for MOV32ri.
16703 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16704 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16705 OutChains[0] = DAG.getStore(Root, dl,
16706 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16707 Trmp, MachinePointerInfo(TrmpAddr),
16710 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16711 DAG.getConstant(1, dl, MVT::i32));
16712 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16713 MachinePointerInfo(TrmpAddr, 1),
16716 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16717 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16718 DAG.getConstant(5, dl, MVT::i32));
16719 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16720 Addr, MachinePointerInfo(TrmpAddr, 5),
16723 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16724 DAG.getConstant(6, dl, MVT::i32));
16725 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16726 MachinePointerInfo(TrmpAddr, 6),
16729 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16733 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16734 SelectionDAG &DAG) const {
16736 The rounding mode is in bits 11:10 of FPSR, and has the following
16738 00 Round to nearest
16743 FLT_ROUNDS, on the other hand, expects the following:
16750 To perform the conversion, we do:
16751 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16754 MachineFunction &MF = DAG.getMachineFunction();
16755 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16756 unsigned StackAlignment = TFI.getStackAlignment();
16757 MVT VT = Op.getSimpleValueType();
16760 // Save FP Control Word to stack slot
16761 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16762 SDValue StackSlot =
16763 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
16765 MachineMemOperand *MMO =
16766 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
16767 MachineMemOperand::MOStore, 2, 2);
16769 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16770 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16771 DAG.getVTList(MVT::Other),
16772 Ops, MVT::i16, MMO);
16774 // Load FP Control Word from stack slot
16775 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16776 MachinePointerInfo(), false, false, false, 0);
16778 // Transform as necessary
16780 DAG.getNode(ISD::SRL, DL, MVT::i16,
16781 DAG.getNode(ISD::AND, DL, MVT::i16,
16782 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16783 DAG.getConstant(11, DL, MVT::i8));
16785 DAG.getNode(ISD::SRL, DL, MVT::i16,
16786 DAG.getNode(ISD::AND, DL, MVT::i16,
16787 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16788 DAG.getConstant(9, DL, MVT::i8));
16791 DAG.getNode(ISD::AND, DL, MVT::i16,
16792 DAG.getNode(ISD::ADD, DL, MVT::i16,
16793 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16794 DAG.getConstant(1, DL, MVT::i16)),
16795 DAG.getConstant(3, DL, MVT::i16));
16797 return DAG.getNode((VT.getSizeInBits() < 16 ?
16798 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16801 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16802 MVT VT = Op.getSimpleValueType();
16804 unsigned NumBits = VT.getSizeInBits();
16807 Op = Op.getOperand(0);
16808 if (VT == MVT::i8) {
16809 // Zero extend to i32 since there is not an i8 bsr.
16811 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16814 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16815 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16816 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16818 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16821 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16822 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16825 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16827 // Finally xor with NumBits-1.
16828 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16829 DAG.getConstant(NumBits - 1, dl, OpVT));
16832 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16836 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16837 MVT VT = Op.getSimpleValueType();
16839 unsigned NumBits = VT.getSizeInBits();
16842 Op = Op.getOperand(0);
16843 if (VT == MVT::i8) {
16844 // Zero extend to i32 since there is not an i8 bsr.
16846 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16849 // Issue a bsr (scan bits in reverse).
16850 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16851 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16853 // And xor with NumBits-1.
16854 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16855 DAG.getConstant(NumBits - 1, dl, OpVT));
16858 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16862 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16863 MVT VT = Op.getSimpleValueType();
16864 unsigned NumBits = VT.getSizeInBits();
16866 Op = Op.getOperand(0);
16868 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16869 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16870 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16872 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16875 DAG.getConstant(NumBits, dl, VT),
16876 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16879 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16882 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16883 // ones, and then concatenate the result back.
16884 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16885 MVT VT = Op.getSimpleValueType();
16887 assert(VT.is256BitVector() && VT.isInteger() &&
16888 "Unsupported value type for operation");
16890 unsigned NumElems = VT.getVectorNumElements();
16893 // Extract the LHS vectors
16894 SDValue LHS = Op.getOperand(0);
16895 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16896 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16898 // Extract the RHS vectors
16899 SDValue RHS = Op.getOperand(1);
16900 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16901 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16903 MVT EltVT = VT.getVectorElementType();
16904 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16906 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16907 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16908 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16911 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16912 if (Op.getValueType() == MVT::i1)
16913 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16914 Op.getOperand(0), Op.getOperand(1));
16915 assert(Op.getSimpleValueType().is256BitVector() &&
16916 Op.getSimpleValueType().isInteger() &&
16917 "Only handle AVX 256-bit vector integer operation");
16918 return Lower256IntArith(Op, DAG);
16921 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16922 if (Op.getValueType() == MVT::i1)
16923 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16924 Op.getOperand(0), Op.getOperand(1));
16925 assert(Op.getSimpleValueType().is256BitVector() &&
16926 Op.getSimpleValueType().isInteger() &&
16927 "Only handle AVX 256-bit vector integer operation");
16928 return Lower256IntArith(Op, DAG);
16931 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
16932 assert(Op.getSimpleValueType().is256BitVector() &&
16933 Op.getSimpleValueType().isInteger() &&
16934 "Only handle AVX 256-bit vector integer operation");
16935 return Lower256IntArith(Op, DAG);
16938 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16939 SelectionDAG &DAG) {
16941 MVT VT = Op.getSimpleValueType();
16944 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16946 // Decompose 256-bit ops into smaller 128-bit ops.
16947 if (VT.is256BitVector() && !Subtarget->hasInt256())
16948 return Lower256IntArith(Op, DAG);
16950 SDValue A = Op.getOperand(0);
16951 SDValue B = Op.getOperand(1);
16953 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16954 // pairs, multiply and truncate.
16955 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16956 if (Subtarget->hasInt256()) {
16957 if (VT == MVT::v32i8) {
16958 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16959 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16960 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16961 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16962 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16963 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16964 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16965 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16966 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16967 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16970 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16971 return DAG.getNode(
16972 ISD::TRUNCATE, dl, VT,
16973 DAG.getNode(ISD::MUL, dl, ExVT,
16974 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16975 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16978 assert(VT == MVT::v16i8 &&
16979 "Pre-AVX2 support only supports v16i8 multiplication");
16980 MVT ExVT = MVT::v8i16;
16982 // Extract the lo parts and sign extend to i16
16984 if (Subtarget->hasSSE41()) {
16985 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16986 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16988 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16989 -1, 4, -1, 5, -1, 6, -1, 7};
16990 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16991 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16992 ALo = DAG.getBitcast(ExVT, ALo);
16993 BLo = DAG.getBitcast(ExVT, BLo);
16994 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16995 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16998 // Extract the hi parts and sign extend to i16
17000 if (Subtarget->hasSSE41()) {
17001 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17002 -1, -1, -1, -1, -1, -1, -1, -1};
17003 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17004 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17005 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17006 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17008 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17009 -1, 12, -1, 13, -1, 14, -1, 15};
17010 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17011 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17012 AHi = DAG.getBitcast(ExVT, AHi);
17013 BHi = DAG.getBitcast(ExVT, BHi);
17014 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17015 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17018 // Multiply, mask the lower 8bits of the lo/hi results and pack
17019 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17020 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17021 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17022 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17023 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17026 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17027 if (VT == MVT::v4i32) {
17028 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17029 "Should not custom lower when pmuldq is available!");
17031 // Extract the odd parts.
17032 static const int UnpackMask[] = { 1, -1, 3, -1 };
17033 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17034 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17036 // Multiply the even parts.
17037 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17038 // Now multiply odd parts.
17039 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17041 Evens = DAG.getBitcast(VT, Evens);
17042 Odds = DAG.getBitcast(VT, Odds);
17044 // Merge the two vectors back together with a shuffle. This expands into 2
17046 static const int ShufMask[] = { 0, 4, 2, 6 };
17047 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17050 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17051 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17053 // Ahi = psrlqi(a, 32);
17054 // Bhi = psrlqi(b, 32);
17056 // AloBlo = pmuludq(a, b);
17057 // AloBhi = pmuludq(a, Bhi);
17058 // AhiBlo = pmuludq(Ahi, b);
17060 // AloBhi = psllqi(AloBhi, 32);
17061 // AhiBlo = psllqi(AhiBlo, 32);
17062 // return AloBlo + AloBhi + AhiBlo;
17064 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17065 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17067 SDValue AhiBlo = Ahi;
17068 SDValue AloBhi = Bhi;
17069 // Bit cast to 32-bit vectors for MULUDQ
17070 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17071 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17072 A = DAG.getBitcast(MulVT, A);
17073 B = DAG.getBitcast(MulVT, B);
17074 Ahi = DAG.getBitcast(MulVT, Ahi);
17075 Bhi = DAG.getBitcast(MulVT, Bhi);
17077 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17078 // After shifting right const values the result may be all-zero.
17079 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17080 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17081 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17083 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17084 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17085 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17088 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17089 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17092 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17093 assert(Subtarget->isTargetWin64() && "Unexpected target");
17094 EVT VT = Op.getValueType();
17095 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17096 "Unexpected return type for lowering");
17100 switch (Op->getOpcode()) {
17101 default: llvm_unreachable("Unexpected request for libcall!");
17102 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17103 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17104 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17105 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17106 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17107 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17111 SDValue InChain = DAG.getEntryNode();
17113 TargetLowering::ArgListTy Args;
17114 TargetLowering::ArgListEntry Entry;
17115 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17116 EVT ArgVT = Op->getOperand(i).getValueType();
17117 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17118 "Unexpected argument type for lowering");
17119 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17120 Entry.Node = StackPtr;
17121 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17123 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17124 Entry.Ty = PointerType::get(ArgTy,0);
17125 Entry.isSExt = false;
17126 Entry.isZExt = false;
17127 Args.push_back(Entry);
17130 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17131 getPointerTy(DAG.getDataLayout()));
17133 TargetLowering::CallLoweringInfo CLI(DAG);
17134 CLI.setDebugLoc(dl).setChain(InChain)
17135 .setCallee(getLibcallCallingConv(LC),
17136 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17137 Callee, std::move(Args), 0)
17138 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17140 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17141 return DAG.getBitcast(VT, CallInfo.first);
17144 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17145 SelectionDAG &DAG) {
17146 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17147 EVT VT = Op0.getValueType();
17150 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17151 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17153 // PMULxD operations multiply each even value (starting at 0) of LHS with
17154 // the related value of RHS and produce a widen result.
17155 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17156 // => <2 x i64> <ae|cg>
17158 // In other word, to have all the results, we need to perform two PMULxD:
17159 // 1. one with the even values.
17160 // 2. one with the odd values.
17161 // To achieve #2, with need to place the odd values at an even position.
17163 // Place the odd value at an even position (basically, shift all values 1
17164 // step to the left):
17165 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17166 // <a|b|c|d> => <b|undef|d|undef>
17167 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17168 // <e|f|g|h> => <f|undef|h|undef>
17169 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17171 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17173 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17174 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17176 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17177 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17178 // => <2 x i64> <ae|cg>
17179 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17180 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17181 // => <2 x i64> <bf|dh>
17182 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17184 // Shuffle it back into the right order.
17185 SDValue Highs, Lows;
17186 if (VT == MVT::v8i32) {
17187 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17188 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17189 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17190 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17192 const int HighMask[] = {1, 5, 3, 7};
17193 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17194 const int LowMask[] = {0, 4, 2, 6};
17195 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17198 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17199 // unsigned multiply.
17200 if (IsSigned && !Subtarget->hasSSE41()) {
17201 SDValue ShAmt = DAG.getConstant(
17203 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17204 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17205 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17206 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17207 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17209 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17210 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17213 // The first result of MUL_LOHI is actually the low value, followed by the
17215 SDValue Ops[] = {Lows, Highs};
17216 return DAG.getMergeValues(Ops, dl);
17219 // Return true if the required (according to Opcode) shift-imm form is natively
17220 // supported by the Subtarget
17221 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17223 if (VT.getScalarSizeInBits() < 16)
17226 if (VT.is512BitVector() &&
17227 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17230 bool LShift = VT.is128BitVector() ||
17231 (VT.is256BitVector() && Subtarget->hasInt256());
17233 bool AShift = LShift && (Subtarget->hasVLX() ||
17234 (VT != MVT::v2i64 && VT != MVT::v4i64));
17235 return (Opcode == ISD::SRA) ? AShift : LShift;
17238 // The shift amount is a variable, but it is the same for all vector lanes.
17239 // These instructions are defined together with shift-immediate.
17241 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17243 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17246 // Return true if the required (according to Opcode) variable-shift form is
17247 // natively supported by the Subtarget
17248 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17251 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17254 // vXi16 supported only on AVX-512, BWI
17255 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17258 if (VT.is512BitVector() || Subtarget->hasVLX())
17261 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17262 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17263 return (Opcode == ISD::SRA) ? AShift : LShift;
17266 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17267 const X86Subtarget *Subtarget) {
17268 MVT VT = Op.getSimpleValueType();
17270 SDValue R = Op.getOperand(0);
17271 SDValue Amt = Op.getOperand(1);
17273 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17274 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17276 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17277 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17278 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17279 SDValue Ex = DAG.getBitcast(ExVT, R);
17281 if (ShiftAmt >= 32) {
17282 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17284 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17285 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17286 ShiftAmt - 32, DAG);
17287 if (VT == MVT::v2i64)
17288 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17289 if (VT == MVT::v4i64)
17290 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17291 {9, 1, 11, 3, 13, 5, 15, 7});
17293 // SRA upper i32, SHL whole i64 and select lower i32.
17294 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17297 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17298 Lower = DAG.getBitcast(ExVT, Lower);
17299 if (VT == MVT::v2i64)
17300 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17301 if (VT == MVT::v4i64)
17302 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17303 {8, 1, 10, 3, 12, 5, 14, 7});
17305 return DAG.getBitcast(VT, Ex);
17308 // Optimize shl/srl/sra with constant shift amount.
17309 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17310 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17311 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17313 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17314 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17316 // i64 SRA needs to be performed as partial shifts.
17317 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17318 Op.getOpcode() == ISD::SRA)
17319 return ArithmeticShiftRight64(ShiftAmt);
17321 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17322 unsigned NumElts = VT.getVectorNumElements();
17323 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17325 if (Op.getOpcode() == ISD::SHL) {
17326 // Simple i8 add case
17328 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17330 // Make a large shift.
17331 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17333 SHL = DAG.getBitcast(VT, SHL);
17334 // Zero out the rightmost bits.
17335 SmallVector<SDValue, 32> V(
17336 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17337 return DAG.getNode(ISD::AND, dl, VT, SHL,
17338 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17340 if (Op.getOpcode() == ISD::SRL) {
17341 // Make a large shift.
17342 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17344 SRL = DAG.getBitcast(VT, SRL);
17345 // Zero out the leftmost bits.
17346 SmallVector<SDValue, 32> V(
17347 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17348 return DAG.getNode(ISD::AND, dl, VT, SRL,
17349 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17351 if (Op.getOpcode() == ISD::SRA) {
17352 if (ShiftAmt == 7) {
17353 // ashr(R, 7) === cmp_slt(R, 0)
17354 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17355 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17358 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17359 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17360 SmallVector<SDValue, 32> V(NumElts,
17361 DAG.getConstant(128 >> ShiftAmt, dl,
17363 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17364 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17365 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17368 llvm_unreachable("Unknown shift opcode.");
17373 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17374 if (!Subtarget->is64Bit() &&
17375 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17377 // Peek through any splat that was introduced for i64 shift vectorization.
17378 int SplatIndex = -1;
17379 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17380 if (SVN->isSplat()) {
17381 SplatIndex = SVN->getSplatIndex();
17382 Amt = Amt.getOperand(0);
17383 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17384 "Splat shuffle referencing second operand");
17387 if (Amt.getOpcode() != ISD::BITCAST ||
17388 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17391 Amt = Amt.getOperand(0);
17392 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17393 VT.getVectorNumElements();
17394 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17395 uint64_t ShiftAmt = 0;
17396 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17397 for (unsigned i = 0; i != Ratio; ++i) {
17398 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17402 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17405 // Check remaining shift amounts (if not a splat).
17406 if (SplatIndex < 0) {
17407 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17408 uint64_t ShAmt = 0;
17409 for (unsigned j = 0; j != Ratio; ++j) {
17410 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17414 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17416 if (ShAmt != ShiftAmt)
17421 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17422 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17424 if (Op.getOpcode() == ISD::SRA)
17425 return ArithmeticShiftRight64(ShiftAmt);
17431 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17432 const X86Subtarget* Subtarget) {
17433 MVT VT = Op.getSimpleValueType();
17435 SDValue R = Op.getOperand(0);
17436 SDValue Amt = Op.getOperand(1);
17438 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17439 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17441 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
17442 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
17444 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
17446 EVT EltVT = VT.getVectorElementType();
17448 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
17449 // Check if this build_vector node is doing a splat.
17450 // If so, then set BaseShAmt equal to the splat value.
17451 BaseShAmt = BV->getSplatValue();
17452 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
17453 BaseShAmt = SDValue();
17455 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17456 Amt = Amt.getOperand(0);
17458 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
17459 if (SVN && SVN->isSplat()) {
17460 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
17461 SDValue InVec = Amt.getOperand(0);
17462 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17463 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
17464 "Unexpected shuffle index found!");
17465 BaseShAmt = InVec.getOperand(SplatIdx);
17466 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17467 if (ConstantSDNode *C =
17468 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17469 if (C->getZExtValue() == SplatIdx)
17470 BaseShAmt = InVec.getOperand(1);
17475 // Avoid introducing an extract element from a shuffle.
17476 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
17477 DAG.getIntPtrConstant(SplatIdx, dl));
17481 if (BaseShAmt.getNode()) {
17482 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
17483 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
17484 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
17485 else if (EltVT.bitsLT(MVT::i32))
17486 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17488 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
17492 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17493 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
17494 Amt.getOpcode() == ISD::BITCAST &&
17495 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17496 Amt = Amt.getOperand(0);
17497 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17498 VT.getVectorNumElements();
17499 std::vector<SDValue> Vals(Ratio);
17500 for (unsigned i = 0; i != Ratio; ++i)
17501 Vals[i] = Amt.getOperand(i);
17502 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17503 for (unsigned j = 0; j != Ratio; ++j)
17504 if (Vals[j] != Amt.getOperand(i + j))
17508 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
17509 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
17514 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17515 SelectionDAG &DAG) {
17516 MVT VT = Op.getSimpleValueType();
17518 SDValue R = Op.getOperand(0);
17519 SDValue Amt = Op.getOperand(1);
17521 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17522 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17524 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
17527 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
17530 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
17533 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
17534 // shifts per-lane and then shuffle the partial results back together.
17535 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
17536 // Splat the shift amounts so the scalar shifts above will catch it.
17537 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
17538 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
17539 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
17540 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
17541 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
17544 // i64 vector arithmetic shift can be emulated with the transform:
17545 // M = lshr(SIGN_BIT, Amt)
17546 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
17547 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
17548 Op.getOpcode() == ISD::SRA) {
17549 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
17550 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
17551 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17552 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
17553 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
17557 // If possible, lower this packed shift into a vector multiply instead of
17558 // expanding it into a sequence of scalar shifts.
17559 // Do this only if the vector shift count is a constant build_vector.
17560 if (Op.getOpcode() == ISD::SHL &&
17561 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17562 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17563 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17564 SmallVector<SDValue, 8> Elts;
17565 EVT SVT = VT.getScalarType();
17566 unsigned SVTBits = SVT.getSizeInBits();
17567 const APInt &One = APInt(SVTBits, 1);
17568 unsigned NumElems = VT.getVectorNumElements();
17570 for (unsigned i=0; i !=NumElems; ++i) {
17571 SDValue Op = Amt->getOperand(i);
17572 if (Op->getOpcode() == ISD::UNDEF) {
17573 Elts.push_back(Op);
17577 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17578 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17579 uint64_t ShAmt = C.getZExtValue();
17580 if (ShAmt >= SVTBits) {
17581 Elts.push_back(DAG.getUNDEF(SVT));
17584 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
17586 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17587 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17590 // Lower SHL with variable shift amount.
17591 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17592 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
17594 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
17595 DAG.getConstant(0x3f800000U, dl, VT));
17596 Op = DAG.getBitcast(MVT::v4f32, Op);
17597 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17598 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17601 // If possible, lower this shift as a sequence of two shifts by
17602 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17604 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17606 // Could be rewritten as:
17607 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17609 // The advantage is that the two shifts from the example would be
17610 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17611 // the vector shift into four scalar shifts plus four pairs of vector
17613 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17614 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17615 unsigned TargetOpcode = X86ISD::MOVSS;
17616 bool CanBeSimplified;
17617 // The splat value for the first packed shift (the 'X' from the example).
17618 SDValue Amt1 = Amt->getOperand(0);
17619 // The splat value for the second packed shift (the 'Y' from the example).
17620 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17621 Amt->getOperand(2);
17623 // See if it is possible to replace this node with a sequence of
17624 // two shifts followed by a MOVSS/MOVSD
17625 if (VT == MVT::v4i32) {
17626 // Check if it is legal to use a MOVSS.
17627 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17628 Amt2 == Amt->getOperand(3);
17629 if (!CanBeSimplified) {
17630 // Otherwise, check if we can still simplify this node using a MOVSD.
17631 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17632 Amt->getOperand(2) == Amt->getOperand(3);
17633 TargetOpcode = X86ISD::MOVSD;
17634 Amt2 = Amt->getOperand(2);
17637 // Do similar checks for the case where the machine value type
17639 CanBeSimplified = Amt1 == Amt->getOperand(1);
17640 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17641 CanBeSimplified = Amt2 == Amt->getOperand(i);
17643 if (!CanBeSimplified) {
17644 TargetOpcode = X86ISD::MOVSD;
17645 CanBeSimplified = true;
17646 Amt2 = Amt->getOperand(4);
17647 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17648 CanBeSimplified = Amt1 == Amt->getOperand(i);
17649 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17650 CanBeSimplified = Amt2 == Amt->getOperand(j);
17654 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17655 isa<ConstantSDNode>(Amt2)) {
17656 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17657 EVT CastVT = MVT::v4i32;
17659 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17660 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17662 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17663 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17664 if (TargetOpcode == X86ISD::MOVSD)
17665 CastVT = MVT::v2i64;
17666 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
17667 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
17668 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17670 return DAG.getBitcast(VT, Result);
17674 // v4i32 Non Uniform Shifts.
17675 // If the shift amount is constant we can shift each lane using the SSE2
17676 // immediate shifts, else we need to zero-extend each lane to the lower i64
17677 // and shift using the SSE2 variable shifts.
17678 // The separate results can then be blended together.
17679 if (VT == MVT::v4i32) {
17680 unsigned Opc = Op.getOpcode();
17681 SDValue Amt0, Amt1, Amt2, Amt3;
17682 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17683 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
17684 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
17685 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
17686 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
17688 // ISD::SHL is handled above but we include it here for completeness.
17691 llvm_unreachable("Unknown target vector shift node");
17693 Opc = X86ISD::VSHL;
17696 Opc = X86ISD::VSRL;
17699 Opc = X86ISD::VSRA;
17702 // The SSE2 shifts use the lower i64 as the same shift amount for
17703 // all lanes and the upper i64 is ignored. These shuffle masks
17704 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
17705 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17706 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
17707 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
17708 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
17709 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
17712 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
17713 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
17714 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
17715 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
17716 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
17717 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
17718 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
17721 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
17722 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
17723 unsigned ShiftOpcode = Op->getOpcode();
17725 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
17726 // On SSE41 targets we make use of the fact that VSELECT lowers
17727 // to PBLENDVB which selects bytes based just on the sign bit.
17728 if (Subtarget->hasSSE41()) {
17729 V0 = DAG.getBitcast(VT, V0);
17730 V1 = DAG.getBitcast(VT, V1);
17731 Sel = DAG.getBitcast(VT, Sel);
17732 return DAG.getBitcast(SelVT,
17733 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
17735 // On pre-SSE41 targets we test for the sign bit by comparing to
17736 // zero - a negative value will set all bits of the lanes to true
17737 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
17738 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
17739 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
17740 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
17743 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
17744 // We can safely do this using i16 shifts as we're only interested in
17745 // the 3 lower bits of each byte.
17746 Amt = DAG.getBitcast(ExtVT, Amt);
17747 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
17748 Amt = DAG.getBitcast(VT, Amt);
17750 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
17751 // r = VSELECT(r, shift(r, 4), a);
17753 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17754 R = SignBitSelect(VT, Amt, M, R);
17757 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17759 // r = VSELECT(r, shift(r, 2), a);
17760 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17761 R = SignBitSelect(VT, Amt, M, R);
17764 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17766 // return VSELECT(r, shift(r, 1), a);
17767 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17768 R = SignBitSelect(VT, Amt, M, R);
17772 if (Op->getOpcode() == ISD::SRA) {
17773 // For SRA we need to unpack each byte to the higher byte of a i16 vector
17774 // so we can correctly sign extend. We don't care what happens to the
17776 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
17777 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
17778 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
17779 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
17780 ALo = DAG.getBitcast(ExtVT, ALo);
17781 AHi = DAG.getBitcast(ExtVT, AHi);
17782 RLo = DAG.getBitcast(ExtVT, RLo);
17783 RHi = DAG.getBitcast(ExtVT, RHi);
17785 // r = VSELECT(r, shift(r, 4), a);
17786 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17787 DAG.getConstant(4, dl, ExtVT));
17788 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17789 DAG.getConstant(4, dl, ExtVT));
17790 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17791 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17794 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17795 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17797 // r = VSELECT(r, shift(r, 2), a);
17798 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17799 DAG.getConstant(2, dl, ExtVT));
17800 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17801 DAG.getConstant(2, dl, ExtVT));
17802 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17803 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17806 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17807 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17809 // r = VSELECT(r, shift(r, 1), a);
17810 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17811 DAG.getConstant(1, dl, ExtVT));
17812 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17813 DAG.getConstant(1, dl, ExtVT));
17814 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17815 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17817 // Logical shift the result back to the lower byte, leaving a zero upper
17819 // meaning that we can safely pack with PACKUSWB.
17821 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17823 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17824 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17828 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17829 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17830 // solution better.
17831 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17832 MVT ExtVT = MVT::v8i32;
17834 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17835 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17836 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17837 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17838 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17841 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17842 MVT ExtVT = MVT::v8i32;
17843 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17844 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17845 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17846 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17847 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17848 ALo = DAG.getBitcast(ExtVT, ALo);
17849 AHi = DAG.getBitcast(ExtVT, AHi);
17850 RLo = DAG.getBitcast(ExtVT, RLo);
17851 RHi = DAG.getBitcast(ExtVT, RHi);
17852 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17853 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17854 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17855 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17856 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17859 if (VT == MVT::v8i16) {
17860 unsigned ShiftOpcode = Op->getOpcode();
17862 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17863 // On SSE41 targets we make use of the fact that VSELECT lowers
17864 // to PBLENDVB which selects bytes based just on the sign bit.
17865 if (Subtarget->hasSSE41()) {
17866 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17867 V0 = DAG.getBitcast(ExtVT, V0);
17868 V1 = DAG.getBitcast(ExtVT, V1);
17869 Sel = DAG.getBitcast(ExtVT, Sel);
17870 return DAG.getBitcast(
17871 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17873 // On pre-SSE41 targets we splat the sign bit - a negative value will
17874 // set all bits of the lanes to true and VSELECT uses that in
17875 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17877 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17878 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17881 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17882 if (Subtarget->hasSSE41()) {
17883 // On SSE41 targets we need to replicate the shift mask in both
17884 // bytes for PBLENDVB.
17887 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17888 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17890 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17893 // r = VSELECT(r, shift(r, 8), a);
17894 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17895 R = SignBitSelect(Amt, M, R);
17898 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17900 // r = VSELECT(r, shift(r, 4), a);
17901 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17902 R = SignBitSelect(Amt, M, R);
17905 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17907 // r = VSELECT(r, shift(r, 2), a);
17908 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17909 R = SignBitSelect(Amt, M, R);
17912 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17914 // return VSELECT(r, shift(r, 1), a);
17915 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17916 R = SignBitSelect(Amt, M, R);
17920 // Decompose 256-bit shifts into smaller 128-bit shifts.
17921 if (VT.is256BitVector()) {
17922 unsigned NumElems = VT.getVectorNumElements();
17923 MVT EltVT = VT.getVectorElementType();
17924 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17926 // Extract the two vectors
17927 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17928 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17930 // Recreate the shift amount vectors
17931 SDValue Amt1, Amt2;
17932 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17933 // Constant shift amount
17934 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17935 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17936 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17938 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17939 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17941 // Variable shift amount
17942 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17943 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17946 // Issue new vector shifts for the smaller types
17947 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17948 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17950 // Concatenate the result back
17951 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17957 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17958 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17959 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17960 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17961 // has only one use.
17962 SDNode *N = Op.getNode();
17963 SDValue LHS = N->getOperand(0);
17964 SDValue RHS = N->getOperand(1);
17965 unsigned BaseOp = 0;
17968 switch (Op.getOpcode()) {
17969 default: llvm_unreachable("Unknown ovf instruction!");
17971 // A subtract of one will be selected as a INC. Note that INC doesn't
17972 // set CF, so we can't do this for UADDO.
17973 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17975 BaseOp = X86ISD::INC;
17976 Cond = X86::COND_O;
17979 BaseOp = X86ISD::ADD;
17980 Cond = X86::COND_O;
17983 BaseOp = X86ISD::ADD;
17984 Cond = X86::COND_B;
17987 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17988 // set CF, so we can't do this for USUBO.
17989 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17991 BaseOp = X86ISD::DEC;
17992 Cond = X86::COND_O;
17995 BaseOp = X86ISD::SUB;
17996 Cond = X86::COND_O;
17999 BaseOp = X86ISD::SUB;
18000 Cond = X86::COND_B;
18003 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18004 Cond = X86::COND_O;
18006 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18007 if (N->getValueType(0) == MVT::i8) {
18008 BaseOp = X86ISD::UMUL8;
18009 Cond = X86::COND_O;
18012 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18014 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18017 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18018 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18019 SDValue(Sum.getNode(), 2));
18021 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18025 // Also sets EFLAGS.
18026 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18027 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18030 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18031 DAG.getConstant(Cond, DL, MVT::i32),
18032 SDValue(Sum.getNode(), 1));
18034 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18037 /// Returns true if the operand type is exactly twice the native width, and
18038 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18039 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18040 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18041 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18042 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18045 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18046 else if (OpWidth == 128)
18047 return Subtarget->hasCmpxchg16b();
18052 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18053 return needsCmpXchgNb(SI->getValueOperand()->getType());
18056 // Note: this turns large loads into lock cmpxchg8b/16b.
18057 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18058 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18059 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18060 return needsCmpXchgNb(PTy->getElementType());
18063 TargetLoweringBase::AtomicRMWExpansionKind
18064 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18065 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18066 Type *MemType = AI->getType();
18068 // If the operand is too big, we must see if cmpxchg8/16b is available
18069 // and default to library calls otherwise.
18070 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18071 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
18072 : AtomicRMWExpansionKind::None;
18075 AtomicRMWInst::BinOp Op = AI->getOperation();
18078 llvm_unreachable("Unknown atomic operation");
18079 case AtomicRMWInst::Xchg:
18080 case AtomicRMWInst::Add:
18081 case AtomicRMWInst::Sub:
18082 // It's better to use xadd, xsub or xchg for these in all cases.
18083 return AtomicRMWExpansionKind::None;
18084 case AtomicRMWInst::Or:
18085 case AtomicRMWInst::And:
18086 case AtomicRMWInst::Xor:
18087 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18088 // prefix to a normal instruction for these operations.
18089 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
18090 : AtomicRMWExpansionKind::None;
18091 case AtomicRMWInst::Nand:
18092 case AtomicRMWInst::Max:
18093 case AtomicRMWInst::Min:
18094 case AtomicRMWInst::UMax:
18095 case AtomicRMWInst::UMin:
18096 // These always require a non-trivial set of data operations on x86. We must
18097 // use a cmpxchg loop.
18098 return AtomicRMWExpansionKind::CmpXChg;
18102 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18103 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18104 // no-sse2). There isn't any reason to disable it if the target processor
18106 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18110 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18111 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18112 Type *MemType = AI->getType();
18113 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18114 // there is no benefit in turning such RMWs into loads, and it is actually
18115 // harmful as it introduces a mfence.
18116 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18119 auto Builder = IRBuilder<>(AI);
18120 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18121 auto SynchScope = AI->getSynchScope();
18122 // We must restrict the ordering to avoid generating loads with Release or
18123 // ReleaseAcquire orderings.
18124 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18125 auto Ptr = AI->getPointerOperand();
18127 // Before the load we need a fence. Here is an example lifted from
18128 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18131 // x.store(1, relaxed);
18132 // r1 = y.fetch_add(0, release);
18134 // y.fetch_add(42, acquire);
18135 // r2 = x.load(relaxed);
18136 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18137 // lowered to just a load without a fence. A mfence flushes the store buffer,
18138 // making the optimization clearly correct.
18139 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18140 // otherwise, we might be able to be more aggressive on relaxed idempotent
18141 // rmw. In practice, they do not look useful, so we don't try to be
18142 // especially clever.
18143 if (SynchScope == SingleThread)
18144 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18145 // the IR level, so we must wrap it in an intrinsic.
18148 if (!hasMFENCE(*Subtarget))
18149 // FIXME: it might make sense to use a locked operation here but on a
18150 // different cache-line to prevent cache-line bouncing. In practice it
18151 // is probably a small win, and x86 processors without mfence are rare
18152 // enough that we do not bother.
18156 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18157 Builder.CreateCall(MFence, {});
18159 // Finally we can emit the atomic load.
18160 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18161 AI->getType()->getPrimitiveSizeInBits());
18162 Loaded->setAtomic(Order, SynchScope);
18163 AI->replaceAllUsesWith(Loaded);
18164 AI->eraseFromParent();
18168 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18169 SelectionDAG &DAG) {
18171 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18172 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18173 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18174 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18176 // The only fence that needs an instruction is a sequentially-consistent
18177 // cross-thread fence.
18178 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18179 if (hasMFENCE(*Subtarget))
18180 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18182 SDValue Chain = Op.getOperand(0);
18183 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18185 DAG.getRegister(X86::ESP, MVT::i32), // Base
18186 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18187 DAG.getRegister(0, MVT::i32), // Index
18188 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18189 DAG.getRegister(0, MVT::i32), // Segment.
18193 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18194 return SDValue(Res, 0);
18197 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18198 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18201 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18202 SelectionDAG &DAG) {
18203 MVT T = Op.getSimpleValueType();
18207 switch(T.SimpleTy) {
18208 default: llvm_unreachable("Invalid value type!");
18209 case MVT::i8: Reg = X86::AL; size = 1; break;
18210 case MVT::i16: Reg = X86::AX; size = 2; break;
18211 case MVT::i32: Reg = X86::EAX; size = 4; break;
18213 assert(Subtarget->is64Bit() && "Node not type legal!");
18214 Reg = X86::RAX; size = 8;
18217 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18218 Op.getOperand(2), SDValue());
18219 SDValue Ops[] = { cpIn.getValue(0),
18222 DAG.getTargetConstant(size, DL, MVT::i8),
18223 cpIn.getValue(1) };
18224 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18225 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18226 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18230 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18231 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18232 MVT::i32, cpOut.getValue(2));
18233 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18234 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18237 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18238 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18239 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18243 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18244 SelectionDAG &DAG) {
18245 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18246 MVT DstVT = Op.getSimpleValueType();
18248 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18249 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18250 if (DstVT != MVT::f64)
18251 // This conversion needs to be expanded.
18254 SDValue InVec = Op->getOperand(0);
18256 unsigned NumElts = SrcVT.getVectorNumElements();
18257 EVT SVT = SrcVT.getVectorElementType();
18259 // Widen the vector in input in the case of MVT::v2i32.
18260 // Example: from MVT::v2i32 to MVT::v4i32.
18261 SmallVector<SDValue, 16> Elts;
18262 for (unsigned i = 0, e = NumElts; i != e; ++i)
18263 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18264 DAG.getIntPtrConstant(i, dl)));
18266 // Explicitly mark the extra elements as Undef.
18267 Elts.append(NumElts, DAG.getUNDEF(SVT));
18269 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18270 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18271 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18272 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18273 DAG.getIntPtrConstant(0, dl));
18276 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18277 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18278 assert((DstVT == MVT::i64 ||
18279 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18280 "Unexpected custom BITCAST");
18281 // i64 <=> MMX conversions are Legal.
18282 if (SrcVT==MVT::i64 && DstVT.isVector())
18284 if (DstVT==MVT::i64 && SrcVT.isVector())
18286 // MMX <=> MMX conversions are Legal.
18287 if (SrcVT.isVector() && DstVT.isVector())
18289 // All other conversions need to be expanded.
18293 /// Compute the horizontal sum of bytes in V for the elements of VT.
18295 /// Requires V to be a byte vector and VT to be an integer vector type with
18296 /// wider elements than V's type. The width of the elements of VT determines
18297 /// how many bytes of V are summed horizontally to produce each element of the
18299 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18300 const X86Subtarget *Subtarget,
18301 SelectionDAG &DAG) {
18303 MVT ByteVecVT = V.getSimpleValueType();
18304 MVT EltVT = VT.getVectorElementType();
18305 int NumElts = VT.getVectorNumElements();
18306 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18307 "Expected value to have byte element type.");
18308 assert(EltVT != MVT::i8 &&
18309 "Horizontal byte sum only makes sense for wider elements!");
18310 unsigned VecSize = VT.getSizeInBits();
18311 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18313 // PSADBW instruction horizontally add all bytes and leave the result in i64
18314 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18315 if (EltVT == MVT::i64) {
18316 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18317 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18318 return DAG.getBitcast(VT, V);
18321 if (EltVT == MVT::i32) {
18322 // We unpack the low half and high half into i32s interleaved with zeros so
18323 // that we can use PSADBW to horizontally sum them. The most useful part of
18324 // this is that it lines up the results of two PSADBW instructions to be
18325 // two v2i64 vectors which concatenated are the 4 population counts. We can
18326 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18327 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18328 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18329 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18331 // Do the horizontal sums into two v2i64s.
18332 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18333 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18334 DAG.getBitcast(ByteVecVT, Low), Zeros);
18335 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18336 DAG.getBitcast(ByteVecVT, High), Zeros);
18338 // Merge them together.
18339 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18340 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18341 DAG.getBitcast(ShortVecVT, Low),
18342 DAG.getBitcast(ShortVecVT, High));
18344 return DAG.getBitcast(VT, V);
18347 // The only element type left is i16.
18348 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18350 // To obtain pop count for each i16 element starting from the pop count for
18351 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18352 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18353 // directly supported.
18354 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18355 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18356 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18357 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18358 DAG.getBitcast(ByteVecVT, V));
18359 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18362 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18363 const X86Subtarget *Subtarget,
18364 SelectionDAG &DAG) {
18365 MVT VT = Op.getSimpleValueType();
18366 MVT EltVT = VT.getVectorElementType();
18367 unsigned VecSize = VT.getSizeInBits();
18369 // Implement a lookup table in register by using an algorithm based on:
18370 // http://wm.ite.pl/articles/sse-popcount.html
18372 // The general idea is that every lower byte nibble in the input vector is an
18373 // index into a in-register pre-computed pop count table. We then split up the
18374 // input vector in two new ones: (1) a vector with only the shifted-right
18375 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18376 // masked out higher ones) for each byte. PSHUB is used separately with both
18377 // to index the in-register table. Next, both are added and the result is a
18378 // i8 vector where each element contains the pop count for input byte.
18380 // To obtain the pop count for elements != i8, we follow up with the same
18381 // approach and use additional tricks as described below.
18383 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18384 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18385 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18386 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18388 int NumByteElts = VecSize / 8;
18389 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18390 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18391 SmallVector<SDValue, 16> LUTVec;
18392 for (int i = 0; i < NumByteElts; ++i)
18393 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18394 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18395 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18396 DAG.getConstant(0x0F, DL, MVT::i8));
18397 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18400 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18401 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18402 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18405 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18407 // The input vector is used as the shuffle mask that index elements into the
18408 // LUT. After counting low and high nibbles, add the vector to obtain the
18409 // final pop count per i8 element.
18410 SDValue HighPopCnt =
18411 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18412 SDValue LowPopCnt =
18413 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18414 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18416 if (EltVT == MVT::i8)
18419 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
18422 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
18423 const X86Subtarget *Subtarget,
18424 SelectionDAG &DAG) {
18425 MVT VT = Op.getSimpleValueType();
18426 assert(VT.is128BitVector() &&
18427 "Only 128-bit vector bitmath lowering supported.");
18429 int VecSize = VT.getSizeInBits();
18430 MVT EltVT = VT.getVectorElementType();
18431 int Len = EltVT.getSizeInBits();
18433 // This is the vectorized version of the "best" algorithm from
18434 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
18435 // with a minor tweak to use a series of adds + shifts instead of vector
18436 // multiplications. Implemented for all integer vector types. We only use
18437 // this when we don't have SSSE3 which allows a LUT-based lowering that is
18438 // much faster, even faster than using native popcnt instructions.
18440 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
18441 MVT VT = V.getSimpleValueType();
18442 SmallVector<SDValue, 32> Shifters(
18443 VT.getVectorNumElements(),
18444 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
18445 return DAG.getNode(OpCode, DL, VT, V,
18446 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
18448 auto GetMask = [&](SDValue V, APInt Mask) {
18449 MVT VT = V.getSimpleValueType();
18450 SmallVector<SDValue, 32> Masks(
18451 VT.getVectorNumElements(),
18452 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
18453 return DAG.getNode(ISD::AND, DL, VT, V,
18454 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
18457 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
18458 // x86, so set the SRL type to have elements at least i16 wide. This is
18459 // correct because all of our SRLs are followed immediately by a mask anyways
18460 // that handles any bits that sneak into the high bits of the byte elements.
18461 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
18465 // v = v - ((v >> 1) & 0x55555555...)
18467 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
18468 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
18469 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
18471 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
18472 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
18473 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
18474 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
18475 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
18477 // v = (v + (v >> 4)) & 0x0F0F0F0F...
18478 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
18479 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
18480 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
18482 // At this point, V contains the byte-wise population count, and we are
18483 // merely doing a horizontal sum if necessary to get the wider element
18485 if (EltVT == MVT::i8)
18488 return LowerHorizontalByteSum(
18489 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
18493 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18494 SelectionDAG &DAG) {
18495 MVT VT = Op.getSimpleValueType();
18496 // FIXME: Need to add AVX-512 support here!
18497 assert((VT.is256BitVector() || VT.is128BitVector()) &&
18498 "Unknown CTPOP type to handle");
18499 SDLoc DL(Op.getNode());
18500 SDValue Op0 = Op.getOperand(0);
18502 if (!Subtarget->hasSSSE3()) {
18503 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
18504 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
18505 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
18508 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
18509 unsigned NumElems = VT.getVectorNumElements();
18511 // Extract each 128-bit vector, compute pop count and concat the result.
18512 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
18513 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
18515 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
18516 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
18517 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
18520 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
18523 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18524 SelectionDAG &DAG) {
18525 assert(Op.getValueType().isVector() &&
18526 "We only do custom lowering for vector population count.");
18527 return LowerVectorCTPOP(Op, Subtarget, DAG);
18530 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18531 SDNode *Node = Op.getNode();
18533 EVT T = Node->getValueType(0);
18534 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18535 DAG.getConstant(0, dl, T), Node->getOperand(2));
18536 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18537 cast<AtomicSDNode>(Node)->getMemoryVT(),
18538 Node->getOperand(0),
18539 Node->getOperand(1), negOp,
18540 cast<AtomicSDNode>(Node)->getMemOperand(),
18541 cast<AtomicSDNode>(Node)->getOrdering(),
18542 cast<AtomicSDNode>(Node)->getSynchScope());
18545 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18546 SDNode *Node = Op.getNode();
18548 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18550 // Convert seq_cst store -> xchg
18551 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18552 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18553 // (The only way to get a 16-byte store is cmpxchg16b)
18554 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18555 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18556 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18557 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18558 cast<AtomicSDNode>(Node)->getMemoryVT(),
18559 Node->getOperand(0),
18560 Node->getOperand(1), Node->getOperand(2),
18561 cast<AtomicSDNode>(Node)->getMemOperand(),
18562 cast<AtomicSDNode>(Node)->getOrdering(),
18563 cast<AtomicSDNode>(Node)->getSynchScope());
18564 return Swap.getValue(1);
18566 // Other atomic stores have a simple pattern.
18570 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18571 EVT VT = Op.getNode()->getSimpleValueType(0);
18573 // Let legalize expand this if it isn't a legal type yet.
18574 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18577 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18580 bool ExtraOp = false;
18581 switch (Op.getOpcode()) {
18582 default: llvm_unreachable("Invalid code");
18583 case ISD::ADDC: Opc = X86ISD::ADD; break;
18584 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18585 case ISD::SUBC: Opc = X86ISD::SUB; break;
18586 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18590 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18592 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18593 Op.getOperand(1), Op.getOperand(2));
18596 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18597 SelectionDAG &DAG) {
18598 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18600 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18601 // which returns the values as { float, float } (in XMM0) or
18602 // { double, double } (which is returned in XMM0, XMM1).
18604 SDValue Arg = Op.getOperand(0);
18605 EVT ArgVT = Arg.getValueType();
18606 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18608 TargetLowering::ArgListTy Args;
18609 TargetLowering::ArgListEntry Entry;
18613 Entry.isSExt = false;
18614 Entry.isZExt = false;
18615 Args.push_back(Entry);
18617 bool isF64 = ArgVT == MVT::f64;
18618 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18619 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18620 // the results are returned via SRet in memory.
18621 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18622 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18624 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
18626 Type *RetTy = isF64
18627 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
18628 : (Type*)VectorType::get(ArgTy, 4);
18630 TargetLowering::CallLoweringInfo CLI(DAG);
18631 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18632 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18634 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18637 // Returned in xmm0 and xmm1.
18638 return CallResult.first;
18640 // Returned in bits 0:31 and 32:64 xmm0.
18641 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18642 CallResult.first, DAG.getIntPtrConstant(0, dl));
18643 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18644 CallResult.first, DAG.getIntPtrConstant(1, dl));
18645 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18646 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18649 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
18650 SelectionDAG &DAG) {
18651 assert(Subtarget->hasAVX512() &&
18652 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18654 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
18655 EVT VT = N->getValue().getValueType();
18656 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
18659 // X86 scatter kills mask register, so its type should be added to
18660 // the list of return values
18661 if (N->getNumValues() == 1) {
18662 SDValue Index = N->getIndex();
18663 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18664 !Index.getValueType().is512BitVector())
18665 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18667 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
18668 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18669 N->getOperand(3), Index };
18671 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
18672 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
18673 return SDValue(NewScatter.getNode(), 0);
18678 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
18679 SelectionDAG &DAG) {
18680 assert(Subtarget->hasAVX512() &&
18681 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18683 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
18684 EVT VT = Op.getValueType();
18685 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
18688 SDValue Index = N->getIndex();
18689 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18690 !Index.getValueType().is512BitVector()) {
18691 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18692 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18693 N->getOperand(3), Index };
18694 DAG.UpdateNodeOperands(N, Ops);
18699 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
18700 SelectionDAG &DAG) const {
18701 // TODO: Eventually, the lowering of these nodes should be informed by or
18702 // deferred to the GC strategy for the function in which they appear. For
18703 // now, however, they must be lowered to something. Since they are logically
18704 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18705 // require special handling for these nodes), lower them as literal NOOPs for
18707 SmallVector<SDValue, 2> Ops;
18709 Ops.push_back(Op.getOperand(0));
18710 if (Op->getGluedNode())
18711 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18714 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18715 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18720 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
18721 SelectionDAG &DAG) const {
18722 // TODO: Eventually, the lowering of these nodes should be informed by or
18723 // deferred to the GC strategy for the function in which they appear. For
18724 // now, however, they must be lowered to something. Since they are logically
18725 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18726 // require special handling for these nodes), lower them as literal NOOPs for
18728 SmallVector<SDValue, 2> Ops;
18730 Ops.push_back(Op.getOperand(0));
18731 if (Op->getGluedNode())
18732 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18735 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18736 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18741 /// LowerOperation - Provide custom lowering hooks for some operations.
18743 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18744 switch (Op.getOpcode()) {
18745 default: llvm_unreachable("Should not custom lower this!");
18746 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18747 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18748 return LowerCMP_SWAP(Op, Subtarget, DAG);
18749 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
18750 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18751 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18752 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18753 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
18754 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
18755 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18756 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18757 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18758 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18759 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18760 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18761 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18762 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18763 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18764 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18765 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18766 case ISD::SHL_PARTS:
18767 case ISD::SRA_PARTS:
18768 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18769 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18770 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18771 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18772 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18773 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18774 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18775 case ISD::SIGN_EXTEND_VECTOR_INREG:
18776 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
18777 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18778 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18779 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18780 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18782 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18783 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18784 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18785 case ISD::SETCC: return LowerSETCC(Op, DAG);
18786 case ISD::SELECT: return LowerSELECT(Op, DAG);
18787 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18788 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18789 case ISD::VASTART: return LowerVASTART(Op, DAG);
18790 case ISD::VAARG: return LowerVAARG(Op, DAG);
18791 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18792 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18793 case ISD::INTRINSIC_VOID:
18794 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18795 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18796 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18797 case ISD::FRAME_TO_ARGS_OFFSET:
18798 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18799 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18800 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18801 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18802 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18803 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18804 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18805 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18806 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18807 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18808 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18809 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18810 case ISD::UMUL_LOHI:
18811 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18814 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18820 case ISD::UMULO: return LowerXALUO(Op, DAG);
18821 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18822 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18826 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18827 case ISD::ADD: return LowerADD(Op, DAG);
18828 case ISD::SUB: return LowerSUB(Op, DAG);
18832 case ISD::UMIN: return LowerMINMAX(Op, DAG);
18833 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18834 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18835 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18836 case ISD::GC_TRANSITION_START:
18837 return LowerGC_TRANSITION_START(Op, DAG);
18838 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18842 /// ReplaceNodeResults - Replace a node with an illegal result type
18843 /// with a new node built out of custom code.
18844 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18845 SmallVectorImpl<SDValue>&Results,
18846 SelectionDAG &DAG) const {
18848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18849 switch (N->getOpcode()) {
18851 llvm_unreachable("Do not know how to custom type legalize this operation!");
18852 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18853 case X86ISD::FMINC:
18855 case X86ISD::FMAXC:
18856 case X86ISD::FMAX: {
18857 EVT VT = N->getValueType(0);
18858 if (VT != MVT::v2f32)
18859 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18860 SDValue UNDEF = DAG.getUNDEF(VT);
18861 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18862 N->getOperand(0), UNDEF);
18863 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18864 N->getOperand(1), UNDEF);
18865 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18868 case ISD::SIGN_EXTEND_INREG:
18873 // We don't want to expand or promote these.
18880 case ISD::UDIVREM: {
18881 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18882 Results.push_back(V);
18885 case ISD::FP_TO_SINT:
18886 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18887 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18888 if (N->getOperand(0).getValueType() == MVT::f16)
18891 case ISD::FP_TO_UINT: {
18892 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18894 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18897 std::pair<SDValue,SDValue> Vals =
18898 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18899 SDValue FIST = Vals.first, StackSlot = Vals.second;
18900 if (FIST.getNode()) {
18901 EVT VT = N->getValueType(0);
18902 // Return a load from the stack slot.
18903 if (StackSlot.getNode())
18904 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18905 MachinePointerInfo(),
18906 false, false, false, 0));
18908 Results.push_back(FIST);
18912 case ISD::UINT_TO_FP: {
18913 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18914 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18915 N->getValueType(0) != MVT::v2f32)
18917 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18919 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18921 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18922 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18923 DAG.getBitcast(MVT::v2i64, VBias));
18924 Or = DAG.getBitcast(MVT::v2f64, Or);
18925 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18926 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18929 case ISD::FP_ROUND: {
18930 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18932 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18933 Results.push_back(V);
18936 case ISD::FP_EXTEND: {
18937 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18938 // No other ValueType for FP_EXTEND should reach this point.
18939 assert(N->getValueType(0) == MVT::v2f32 &&
18940 "Do not know how to legalize this Node");
18943 case ISD::INTRINSIC_W_CHAIN: {
18944 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18946 default : llvm_unreachable("Do not know how to custom type "
18947 "legalize this intrinsic operation!");
18948 case Intrinsic::x86_rdtsc:
18949 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18951 case Intrinsic::x86_rdtscp:
18952 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18954 case Intrinsic::x86_rdpmc:
18955 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18958 case ISD::READCYCLECOUNTER: {
18959 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18962 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18963 EVT T = N->getValueType(0);
18964 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18965 bool Regs64bit = T == MVT::i128;
18966 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18967 SDValue cpInL, cpInH;
18968 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18969 DAG.getConstant(0, dl, HalfT));
18970 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18971 DAG.getConstant(1, dl, HalfT));
18972 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18973 Regs64bit ? X86::RAX : X86::EAX,
18975 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18976 Regs64bit ? X86::RDX : X86::EDX,
18977 cpInH, cpInL.getValue(1));
18978 SDValue swapInL, swapInH;
18979 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18980 DAG.getConstant(0, dl, HalfT));
18981 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18982 DAG.getConstant(1, dl, HalfT));
18983 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18984 Regs64bit ? X86::RBX : X86::EBX,
18985 swapInL, cpInH.getValue(1));
18986 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18987 Regs64bit ? X86::RCX : X86::ECX,
18988 swapInH, swapInL.getValue(1));
18989 SDValue Ops[] = { swapInH.getValue(0),
18991 swapInH.getValue(1) };
18992 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18993 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18994 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18995 X86ISD::LCMPXCHG8_DAG;
18996 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18997 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18998 Regs64bit ? X86::RAX : X86::EAX,
18999 HalfT, Result.getValue(1));
19000 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19001 Regs64bit ? X86::RDX : X86::EDX,
19002 HalfT, cpOutL.getValue(2));
19003 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19005 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19006 MVT::i32, cpOutH.getValue(2));
19008 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19009 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19010 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19012 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19013 Results.push_back(Success);
19014 Results.push_back(EFLAGS.getValue(1));
19017 case ISD::ATOMIC_SWAP:
19018 case ISD::ATOMIC_LOAD_ADD:
19019 case ISD::ATOMIC_LOAD_SUB:
19020 case ISD::ATOMIC_LOAD_AND:
19021 case ISD::ATOMIC_LOAD_OR:
19022 case ISD::ATOMIC_LOAD_XOR:
19023 case ISD::ATOMIC_LOAD_NAND:
19024 case ISD::ATOMIC_LOAD_MIN:
19025 case ISD::ATOMIC_LOAD_MAX:
19026 case ISD::ATOMIC_LOAD_UMIN:
19027 case ISD::ATOMIC_LOAD_UMAX:
19028 case ISD::ATOMIC_LOAD: {
19029 // Delegate to generic TypeLegalization. Situations we can really handle
19030 // should have already been dealt with by AtomicExpandPass.cpp.
19033 case ISD::BITCAST: {
19034 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19035 EVT DstVT = N->getValueType(0);
19036 EVT SrcVT = N->getOperand(0)->getValueType(0);
19038 if (SrcVT != MVT::f64 ||
19039 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19042 unsigned NumElts = DstVT.getVectorNumElements();
19043 EVT SVT = DstVT.getVectorElementType();
19044 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19045 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19046 MVT::v2f64, N->getOperand(0));
19047 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19049 if (ExperimentalVectorWideningLegalization) {
19050 // If we are legalizing vectors by widening, we already have the desired
19051 // legal vector type, just return it.
19052 Results.push_back(ToVecInt);
19056 SmallVector<SDValue, 8> Elts;
19057 for (unsigned i = 0, e = NumElts; i != e; ++i)
19058 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19059 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19061 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19066 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19067 switch ((X86ISD::NodeType)Opcode) {
19068 case X86ISD::FIRST_NUMBER: break;
19069 case X86ISD::BSF: return "X86ISD::BSF";
19070 case X86ISD::BSR: return "X86ISD::BSR";
19071 case X86ISD::SHLD: return "X86ISD::SHLD";
19072 case X86ISD::SHRD: return "X86ISD::SHRD";
19073 case X86ISD::FAND: return "X86ISD::FAND";
19074 case X86ISD::FANDN: return "X86ISD::FANDN";
19075 case X86ISD::FOR: return "X86ISD::FOR";
19076 case X86ISD::FXOR: return "X86ISD::FXOR";
19077 case X86ISD::FILD: return "X86ISD::FILD";
19078 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19079 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19080 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19081 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19082 case X86ISD::FLD: return "X86ISD::FLD";
19083 case X86ISD::FST: return "X86ISD::FST";
19084 case X86ISD::CALL: return "X86ISD::CALL";
19085 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19086 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19087 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19088 case X86ISD::BT: return "X86ISD::BT";
19089 case X86ISD::CMP: return "X86ISD::CMP";
19090 case X86ISD::COMI: return "X86ISD::COMI";
19091 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19092 case X86ISD::CMPM: return "X86ISD::CMPM";
19093 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19094 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19095 case X86ISD::SETCC: return "X86ISD::SETCC";
19096 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19097 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19098 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19099 case X86ISD::CMOV: return "X86ISD::CMOV";
19100 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19101 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19102 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19103 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19104 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19105 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19106 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19107 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19108 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19109 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19110 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19111 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19112 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19113 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19114 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19115 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19116 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19117 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19118 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19119 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19120 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19121 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19122 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19123 case X86ISD::HADD: return "X86ISD::HADD";
19124 case X86ISD::HSUB: return "X86ISD::HSUB";
19125 case X86ISD::FHADD: return "X86ISD::FHADD";
19126 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19127 case X86ISD::ABS: return "X86ISD::ABS";
19128 case X86ISD::FMAX: return "X86ISD::FMAX";
19129 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19130 case X86ISD::FMIN: return "X86ISD::FMIN";
19131 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19132 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19133 case X86ISD::FMINC: return "X86ISD::FMINC";
19134 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19135 case X86ISD::FRCP: return "X86ISD::FRCP";
19136 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19137 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19138 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19139 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19140 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19141 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19142 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19143 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19144 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19145 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19146 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19147 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19148 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19149 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19150 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19151 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19152 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19153 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19154 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19155 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19156 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19157 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19158 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19159 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19160 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19161 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19162 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19163 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19164 case X86ISD::VSHL: return "X86ISD::VSHL";
19165 case X86ISD::VSRL: return "X86ISD::VSRL";
19166 case X86ISD::VSRA: return "X86ISD::VSRA";
19167 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19168 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19169 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19170 case X86ISD::CMPP: return "X86ISD::CMPP";
19171 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19172 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19173 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19174 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19175 case X86ISD::ADD: return "X86ISD::ADD";
19176 case X86ISD::SUB: return "X86ISD::SUB";
19177 case X86ISD::ADC: return "X86ISD::ADC";
19178 case X86ISD::SBB: return "X86ISD::SBB";
19179 case X86ISD::SMUL: return "X86ISD::SMUL";
19180 case X86ISD::UMUL: return "X86ISD::UMUL";
19181 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19182 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19183 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19184 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19185 case X86ISD::INC: return "X86ISD::INC";
19186 case X86ISD::DEC: return "X86ISD::DEC";
19187 case X86ISD::OR: return "X86ISD::OR";
19188 case X86ISD::XOR: return "X86ISD::XOR";
19189 case X86ISD::AND: return "X86ISD::AND";
19190 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19191 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19192 case X86ISD::PTEST: return "X86ISD::PTEST";
19193 case X86ISD::TESTP: return "X86ISD::TESTP";
19194 case X86ISD::TESTM: return "X86ISD::TESTM";
19195 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19196 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19197 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19198 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19199 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19200 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19201 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19202 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19203 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19204 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19205 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19206 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19207 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19208 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19209 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19210 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19211 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19212 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19213 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19214 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19215 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19216 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19217 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19218 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19219 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19220 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19221 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19222 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19223 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19224 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19225 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19226 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19227 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19228 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19229 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19230 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19231 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19232 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19233 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19234 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19235 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19236 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19237 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19238 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19239 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19240 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19241 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19242 case X86ISD::SAHF: return "X86ISD::SAHF";
19243 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19244 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19245 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19246 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19247 case X86ISD::FMADD: return "X86ISD::FMADD";
19248 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19249 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19250 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19251 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19252 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19253 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19254 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19255 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19256 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19257 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19258 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19259 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19260 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19261 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19262 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19263 case X86ISD::XTEST: return "X86ISD::XTEST";
19264 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19265 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19266 case X86ISD::SELECT: return "X86ISD::SELECT";
19267 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19268 case X86ISD::RCP28: return "X86ISD::RCP28";
19269 case X86ISD::EXP2: return "X86ISD::EXP2";
19270 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19271 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19272 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19273 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19274 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19275 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19276 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19277 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19278 case X86ISD::ADDS: return "X86ISD::ADDS";
19279 case X86ISD::SUBS: return "X86ISD::SUBS";
19280 case X86ISD::AVG: return "X86ISD::AVG";
19281 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19282 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19283 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19284 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19285 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19290 // isLegalAddressingMode - Return true if the addressing mode represented
19291 // by AM is legal for this target, for a load/store of the specified type.
19292 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19293 const AddrMode &AM, Type *Ty,
19294 unsigned AS) const {
19295 // X86 supports extremely general addressing modes.
19296 CodeModel::Model M = getTargetMachine().getCodeModel();
19297 Reloc::Model R = getTargetMachine().getRelocationModel();
19299 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19300 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19305 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19307 // If a reference to this global requires an extra load, we can't fold it.
19308 if (isGlobalStubReference(GVFlags))
19311 // If BaseGV requires a register for the PIC base, we cannot also have a
19312 // BaseReg specified.
19313 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19316 // If lower 4G is not available, then we must use rip-relative addressing.
19317 if ((M != CodeModel::Small || R != Reloc::Static) &&
19318 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19322 switch (AM.Scale) {
19328 // These scales always work.
19333 // These scales are formed with basereg+scalereg. Only accept if there is
19338 default: // Other stuff never works.
19345 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19346 unsigned Bits = Ty->getScalarSizeInBits();
19348 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19349 // particularly cheaper than those without.
19353 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19354 // variable shifts just as cheap as scalar ones.
19355 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19358 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19359 // fully general vector.
19363 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19364 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19366 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19367 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19368 return NumBits1 > NumBits2;
19371 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19372 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19375 if (!isTypeLegal(EVT::getEVT(Ty1)))
19378 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19380 // Assuming the caller doesn't have a zeroext or signext return parameter,
19381 // truncation all the way down to i1 is valid.
19385 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19386 return isInt<32>(Imm);
19389 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19390 // Can also use sub to handle negated immediates.
19391 return isInt<32>(Imm);
19394 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19395 if (!VT1.isInteger() || !VT2.isInteger())
19397 unsigned NumBits1 = VT1.getSizeInBits();
19398 unsigned NumBits2 = VT2.getSizeInBits();
19399 return NumBits1 > NumBits2;
19402 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19403 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19404 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19407 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19408 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19409 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19412 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19413 EVT VT1 = Val.getValueType();
19414 if (isZExtFree(VT1, VT2))
19417 if (Val.getOpcode() != ISD::LOAD)
19420 if (!VT1.isSimple() || !VT1.isInteger() ||
19421 !VT2.isSimple() || !VT2.isInteger())
19424 switch (VT1.getSimpleVT().SimpleTy) {
19429 // X86 has 8, 16, and 32-bit zero-extending loads.
19436 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
19439 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19440 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
19443 VT = VT.getScalarType();
19445 if (!VT.isSimple())
19448 switch (VT.getSimpleVT().SimpleTy) {
19459 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19460 // i16 instructions are longer (0x66 prefix) and potentially slower.
19461 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19464 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19465 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19466 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19467 /// are assumed to be legal.
19469 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19471 if (!VT.isSimple())
19474 // Not for i1 vectors
19475 if (VT.getScalarType() == MVT::i1)
19478 // Very little shuffling can be done for 64-bit vectors right now.
19479 if (VT.getSizeInBits() == 64)
19482 // We only care that the types being shuffled are legal. The lowering can
19483 // handle any possible shuffle mask that results.
19484 return isTypeLegal(VT.getSimpleVT());
19488 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19490 // Just delegate to the generic legality, clear masks aren't special.
19491 return isShuffleMaskLegal(Mask, VT);
19494 //===----------------------------------------------------------------------===//
19495 // X86 Scheduler Hooks
19496 //===----------------------------------------------------------------------===//
19498 /// Utility function to emit xbegin specifying the start of an RTM region.
19499 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19500 const TargetInstrInfo *TII) {
19501 DebugLoc DL = MI->getDebugLoc();
19503 const BasicBlock *BB = MBB->getBasicBlock();
19504 MachineFunction::iterator I = MBB;
19507 // For the v = xbegin(), we generate
19518 MachineBasicBlock *thisMBB = MBB;
19519 MachineFunction *MF = MBB->getParent();
19520 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19521 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19522 MF->insert(I, mainMBB);
19523 MF->insert(I, sinkMBB);
19525 // Transfer the remainder of BB and its successor edges to sinkMBB.
19526 sinkMBB->splice(sinkMBB->begin(), MBB,
19527 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19528 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19532 // # fallthrough to mainMBB
19533 // # abortion to sinkMBB
19534 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19535 thisMBB->addSuccessor(mainMBB);
19536 thisMBB->addSuccessor(sinkMBB);
19540 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19541 mainMBB->addSuccessor(sinkMBB);
19544 // EAX is live into the sinkMBB
19545 sinkMBB->addLiveIn(X86::EAX);
19546 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19547 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19550 MI->eraseFromParent();
19554 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19555 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19556 // in the .td file.
19557 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19558 const TargetInstrInfo *TII) {
19560 switch (MI->getOpcode()) {
19561 default: llvm_unreachable("illegal opcode!");
19562 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19563 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19564 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19565 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19566 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19567 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19568 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19569 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19572 DebugLoc dl = MI->getDebugLoc();
19573 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19575 unsigned NumArgs = MI->getNumOperands();
19576 for (unsigned i = 1; i < NumArgs; ++i) {
19577 MachineOperand &Op = MI->getOperand(i);
19578 if (!(Op.isReg() && Op.isImplicit()))
19579 MIB.addOperand(Op);
19581 if (MI->hasOneMemOperand())
19582 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19584 BuildMI(*BB, MI, dl,
19585 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19586 .addReg(X86::XMM0);
19588 MI->eraseFromParent();
19592 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19593 // defs in an instruction pattern
19594 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19595 const TargetInstrInfo *TII) {
19597 switch (MI->getOpcode()) {
19598 default: llvm_unreachable("illegal opcode!");
19599 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19600 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19601 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19602 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19603 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19604 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19605 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19606 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19609 DebugLoc dl = MI->getDebugLoc();
19610 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19612 unsigned NumArgs = MI->getNumOperands(); // remove the results
19613 for (unsigned i = 1; i < NumArgs; ++i) {
19614 MachineOperand &Op = MI->getOperand(i);
19615 if (!(Op.isReg() && Op.isImplicit()))
19616 MIB.addOperand(Op);
19618 if (MI->hasOneMemOperand())
19619 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19621 BuildMI(*BB, MI, dl,
19622 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19625 MI->eraseFromParent();
19629 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19630 const X86Subtarget *Subtarget) {
19631 DebugLoc dl = MI->getDebugLoc();
19632 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19633 // Address into RAX/EAX, other two args into ECX, EDX.
19634 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19635 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19636 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19637 for (int i = 0; i < X86::AddrNumOperands; ++i)
19638 MIB.addOperand(MI->getOperand(i));
19640 unsigned ValOps = X86::AddrNumOperands;
19641 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19642 .addReg(MI->getOperand(ValOps).getReg());
19643 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19644 .addReg(MI->getOperand(ValOps+1).getReg());
19646 // The instruction doesn't actually take any operands though.
19647 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19649 MI->eraseFromParent(); // The pseudo is gone now.
19653 MachineBasicBlock *
19654 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
19655 MachineBasicBlock *MBB) const {
19656 // Emit va_arg instruction on X86-64.
19658 // Operands to this pseudo-instruction:
19659 // 0 ) Output : destination address (reg)
19660 // 1-5) Input : va_list address (addr, i64mem)
19661 // 6 ) ArgSize : Size (in bytes) of vararg type
19662 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19663 // 8 ) Align : Alignment of type
19664 // 9 ) EFLAGS (implicit-def)
19666 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19667 static_assert(X86::AddrNumOperands == 5,
19668 "VAARG_64 assumes 5 address operands");
19670 unsigned DestReg = MI->getOperand(0).getReg();
19671 MachineOperand &Base = MI->getOperand(1);
19672 MachineOperand &Scale = MI->getOperand(2);
19673 MachineOperand &Index = MI->getOperand(3);
19674 MachineOperand &Disp = MI->getOperand(4);
19675 MachineOperand &Segment = MI->getOperand(5);
19676 unsigned ArgSize = MI->getOperand(6).getImm();
19677 unsigned ArgMode = MI->getOperand(7).getImm();
19678 unsigned Align = MI->getOperand(8).getImm();
19680 // Memory Reference
19681 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19682 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19683 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19685 // Machine Information
19686 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19687 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19688 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19689 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19690 DebugLoc DL = MI->getDebugLoc();
19692 // struct va_list {
19695 // i64 overflow_area (address)
19696 // i64 reg_save_area (address)
19698 // sizeof(va_list) = 24
19699 // alignment(va_list) = 8
19701 unsigned TotalNumIntRegs = 6;
19702 unsigned TotalNumXMMRegs = 8;
19703 bool UseGPOffset = (ArgMode == 1);
19704 bool UseFPOffset = (ArgMode == 2);
19705 unsigned MaxOffset = TotalNumIntRegs * 8 +
19706 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19708 /* Align ArgSize to a multiple of 8 */
19709 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19710 bool NeedsAlign = (Align > 8);
19712 MachineBasicBlock *thisMBB = MBB;
19713 MachineBasicBlock *overflowMBB;
19714 MachineBasicBlock *offsetMBB;
19715 MachineBasicBlock *endMBB;
19717 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19718 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19719 unsigned OffsetReg = 0;
19721 if (!UseGPOffset && !UseFPOffset) {
19722 // If we only pull from the overflow region, we don't create a branch.
19723 // We don't need to alter control flow.
19724 OffsetDestReg = 0; // unused
19725 OverflowDestReg = DestReg;
19727 offsetMBB = nullptr;
19728 overflowMBB = thisMBB;
19731 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19732 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19733 // If not, pull from overflow_area. (branch to overflowMBB)
19738 // offsetMBB overflowMBB
19743 // Registers for the PHI in endMBB
19744 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19745 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19747 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19748 MachineFunction *MF = MBB->getParent();
19749 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19750 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19751 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19753 MachineFunction::iterator MBBIter = MBB;
19756 // Insert the new basic blocks
19757 MF->insert(MBBIter, offsetMBB);
19758 MF->insert(MBBIter, overflowMBB);
19759 MF->insert(MBBIter, endMBB);
19761 // Transfer the remainder of MBB and its successor edges to endMBB.
19762 endMBB->splice(endMBB->begin(), thisMBB,
19763 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19764 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19766 // Make offsetMBB and overflowMBB successors of thisMBB
19767 thisMBB->addSuccessor(offsetMBB);
19768 thisMBB->addSuccessor(overflowMBB);
19770 // endMBB is a successor of both offsetMBB and overflowMBB
19771 offsetMBB->addSuccessor(endMBB);
19772 overflowMBB->addSuccessor(endMBB);
19774 // Load the offset value into a register
19775 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19776 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19780 .addDisp(Disp, UseFPOffset ? 4 : 0)
19781 .addOperand(Segment)
19782 .setMemRefs(MMOBegin, MMOEnd);
19784 // Check if there is enough room left to pull this argument.
19785 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19787 .addImm(MaxOffset + 8 - ArgSizeA8);
19789 // Branch to "overflowMBB" if offset >= max
19790 // Fall through to "offsetMBB" otherwise
19791 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19792 .addMBB(overflowMBB);
19795 // In offsetMBB, emit code to use the reg_save_area.
19797 assert(OffsetReg != 0);
19799 // Read the reg_save_area address.
19800 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19801 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19806 .addOperand(Segment)
19807 .setMemRefs(MMOBegin, MMOEnd);
19809 // Zero-extend the offset
19810 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19811 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19814 .addImm(X86::sub_32bit);
19816 // Add the offset to the reg_save_area to get the final address.
19817 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19818 .addReg(OffsetReg64)
19819 .addReg(RegSaveReg);
19821 // Compute the offset for the next argument
19822 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19823 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19825 .addImm(UseFPOffset ? 16 : 8);
19827 // Store it back into the va_list.
19828 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19832 .addDisp(Disp, UseFPOffset ? 4 : 0)
19833 .addOperand(Segment)
19834 .addReg(NextOffsetReg)
19835 .setMemRefs(MMOBegin, MMOEnd);
19838 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19843 // Emit code to use overflow area
19846 // Load the overflow_area address into a register.
19847 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19848 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19853 .addOperand(Segment)
19854 .setMemRefs(MMOBegin, MMOEnd);
19856 // If we need to align it, do so. Otherwise, just copy the address
19857 // to OverflowDestReg.
19859 // Align the overflow address
19860 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19861 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19863 // aligned_addr = (addr + (align-1)) & ~(align-1)
19864 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19865 .addReg(OverflowAddrReg)
19868 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19870 .addImm(~(uint64_t)(Align-1));
19872 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19873 .addReg(OverflowAddrReg);
19876 // Compute the next overflow address after this argument.
19877 // (the overflow address should be kept 8-byte aligned)
19878 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19879 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19880 .addReg(OverflowDestReg)
19881 .addImm(ArgSizeA8);
19883 // Store the new overflow address.
19884 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19889 .addOperand(Segment)
19890 .addReg(NextAddrReg)
19891 .setMemRefs(MMOBegin, MMOEnd);
19893 // If we branched, emit the PHI to the front of endMBB.
19895 BuildMI(*endMBB, endMBB->begin(), DL,
19896 TII->get(X86::PHI), DestReg)
19897 .addReg(OffsetDestReg).addMBB(offsetMBB)
19898 .addReg(OverflowDestReg).addMBB(overflowMBB);
19901 // Erase the pseudo instruction
19902 MI->eraseFromParent();
19907 MachineBasicBlock *
19908 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19910 MachineBasicBlock *MBB) const {
19911 // Emit code to save XMM registers to the stack. The ABI says that the
19912 // number of registers to save is given in %al, so it's theoretically
19913 // possible to do an indirect jump trick to avoid saving all of them,
19914 // however this code takes a simpler approach and just executes all
19915 // of the stores if %al is non-zero. It's less code, and it's probably
19916 // easier on the hardware branch predictor, and stores aren't all that
19917 // expensive anyway.
19919 // Create the new basic blocks. One block contains all the XMM stores,
19920 // and one block is the final destination regardless of whether any
19921 // stores were performed.
19922 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19923 MachineFunction *F = MBB->getParent();
19924 MachineFunction::iterator MBBIter = MBB;
19926 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19927 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19928 F->insert(MBBIter, XMMSaveMBB);
19929 F->insert(MBBIter, EndMBB);
19931 // Transfer the remainder of MBB and its successor edges to EndMBB.
19932 EndMBB->splice(EndMBB->begin(), MBB,
19933 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19934 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19936 // The original block will now fall through to the XMM save block.
19937 MBB->addSuccessor(XMMSaveMBB);
19938 // The XMMSaveMBB will fall through to the end block.
19939 XMMSaveMBB->addSuccessor(EndMBB);
19941 // Now add the instructions.
19942 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19943 DebugLoc DL = MI->getDebugLoc();
19945 unsigned CountReg = MI->getOperand(0).getReg();
19946 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19947 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19949 if (!Subtarget->isTargetWin64()) {
19950 // If %al is 0, branch around the XMM save block.
19951 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19952 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19953 MBB->addSuccessor(EndMBB);
19956 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19957 // that was just emitted, but clearly shouldn't be "saved".
19958 assert((MI->getNumOperands() <= 3 ||
19959 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19960 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19961 && "Expected last argument to be EFLAGS");
19962 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19963 // In the XMM save block, save all the XMM argument registers.
19964 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19965 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19966 MachineMemOperand *MMO = F->getMachineMemOperand(
19967 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
19968 MachineMemOperand::MOStore,
19969 /*Size=*/16, /*Align=*/16);
19970 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19971 .addFrameIndex(RegSaveFrameIndex)
19972 .addImm(/*Scale=*/1)
19973 .addReg(/*IndexReg=*/0)
19974 .addImm(/*Disp=*/Offset)
19975 .addReg(/*Segment=*/0)
19976 .addReg(MI->getOperand(i).getReg())
19977 .addMemOperand(MMO);
19980 MI->eraseFromParent(); // The pseudo instruction is gone now.
19985 // The EFLAGS operand of SelectItr might be missing a kill marker
19986 // because there were multiple uses of EFLAGS, and ISel didn't know
19987 // which to mark. Figure out whether SelectItr should have had a
19988 // kill marker, and set it if it should. Returns the correct kill
19990 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19991 MachineBasicBlock* BB,
19992 const TargetRegisterInfo* TRI) {
19993 // Scan forward through BB for a use/def of EFLAGS.
19994 MachineBasicBlock::iterator miI(std::next(SelectItr));
19995 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19996 const MachineInstr& mi = *miI;
19997 if (mi.readsRegister(X86::EFLAGS))
19999 if (mi.definesRegister(X86::EFLAGS))
20000 break; // Should have kill-flag - update below.
20003 // If we hit the end of the block, check whether EFLAGS is live into a
20005 if (miI == BB->end()) {
20006 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20007 sEnd = BB->succ_end();
20008 sItr != sEnd; ++sItr) {
20009 MachineBasicBlock* succ = *sItr;
20010 if (succ->isLiveIn(X86::EFLAGS))
20015 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20016 // out. SelectMI should have a kill flag on EFLAGS.
20017 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20021 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20022 // together with other CMOV pseudo-opcodes into a single basic-block with
20023 // conditional jump around it.
20024 static bool isCMOVPseudo(MachineInstr *MI) {
20025 switch (MI->getOpcode()) {
20026 case X86::CMOV_FR32:
20027 case X86::CMOV_FR64:
20028 case X86::CMOV_GR8:
20029 case X86::CMOV_GR16:
20030 case X86::CMOV_GR32:
20031 case X86::CMOV_RFP32:
20032 case X86::CMOV_RFP64:
20033 case X86::CMOV_RFP80:
20034 case X86::CMOV_V2F64:
20035 case X86::CMOV_V2I64:
20036 case X86::CMOV_V4F32:
20037 case X86::CMOV_V4F64:
20038 case X86::CMOV_V4I64:
20039 case X86::CMOV_V16F32:
20040 case X86::CMOV_V8F32:
20041 case X86::CMOV_V8F64:
20042 case X86::CMOV_V8I64:
20043 case X86::CMOV_V8I1:
20044 case X86::CMOV_V16I1:
20045 case X86::CMOV_V32I1:
20046 case X86::CMOV_V64I1:
20054 MachineBasicBlock *
20055 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20056 MachineBasicBlock *BB) const {
20057 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20058 DebugLoc DL = MI->getDebugLoc();
20060 // To "insert" a SELECT_CC instruction, we actually have to insert the
20061 // diamond control-flow pattern. The incoming instruction knows the
20062 // destination vreg to set, the condition code register to branch on, the
20063 // true/false values to select between, and a branch opcode to use.
20064 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20065 MachineFunction::iterator It = BB;
20071 // cmpTY ccX, r1, r2
20073 // fallthrough --> copy0MBB
20074 MachineBasicBlock *thisMBB = BB;
20075 MachineFunction *F = BB->getParent();
20077 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20078 // as described above, by inserting a BB, and then making a PHI at the join
20079 // point to select the true and false operands of the CMOV in the PHI.
20081 // The code also handles two different cases of multiple CMOV opcodes
20085 // In this case, there are multiple CMOVs in a row, all which are based on
20086 // the same condition setting (or the exact opposite condition setting).
20087 // In this case we can lower all the CMOVs using a single inserted BB, and
20088 // then make a number of PHIs at the join point to model the CMOVs. The only
20089 // trickiness here, is that in a case like:
20091 // t2 = CMOV cond1 t1, f1
20092 // t3 = CMOV cond1 t2, f2
20094 // when rewriting this into PHIs, we have to perform some renaming on the
20095 // temps since you cannot have a PHI operand refer to a PHI result earlier
20096 // in the same block. The "simple" but wrong lowering would be:
20098 // t2 = PHI t1(BB1), f1(BB2)
20099 // t3 = PHI t2(BB1), f2(BB2)
20101 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20102 // renaming is to note that on the path through BB1, t2 is really just a
20103 // copy of t1, and do that renaming, properly generating:
20105 // t2 = PHI t1(BB1), f1(BB2)
20106 // t3 = PHI t1(BB1), f2(BB2)
20108 // Case 2, we lower cascaded CMOVs such as
20110 // (CMOV (CMOV F, T, cc1), T, cc2)
20112 // to two successives branches. For that, we look for another CMOV as the
20113 // following instruction.
20115 // Without this, we would add a PHI between the two jumps, which ends up
20116 // creating a few copies all around. For instance, for
20118 // (sitofp (zext (fcmp une)))
20120 // we would generate:
20122 // ucomiss %xmm1, %xmm0
20123 // movss <1.0f>, %xmm0
20124 // movaps %xmm0, %xmm1
20126 // xorps %xmm1, %xmm1
20129 // movaps %xmm1, %xmm0
20133 // because this custom-inserter would have generated:
20145 // A: X = ...; Y = ...
20147 // C: Z = PHI [X, A], [Y, B]
20149 // E: PHI [X, C], [Z, D]
20151 // If we lower both CMOVs in a single step, we can instead generate:
20163 // A: X = ...; Y = ...
20165 // E: PHI [X, A], [X, C], [Y, D]
20167 // Which, in our sitofp/fcmp example, gives us something like:
20169 // ucomiss %xmm1, %xmm0
20170 // movss <1.0f>, %xmm0
20173 // xorps %xmm0, %xmm0
20177 MachineInstr *CascadedCMOV = nullptr;
20178 MachineInstr *LastCMOV = MI;
20179 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20180 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20181 MachineBasicBlock::iterator NextMIIt =
20182 std::next(MachineBasicBlock::iterator(MI));
20184 // Check for case 1, where there are multiple CMOVs with the same condition
20185 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20186 // number of jumps the most.
20188 if (isCMOVPseudo(MI)) {
20189 // See if we have a string of CMOVS with the same condition.
20190 while (NextMIIt != BB->end() &&
20191 isCMOVPseudo(NextMIIt) &&
20192 (NextMIIt->getOperand(3).getImm() == CC ||
20193 NextMIIt->getOperand(3).getImm() == OppCC)) {
20194 LastCMOV = &*NextMIIt;
20199 // This checks for case 2, but only do this if we didn't already find
20200 // case 1, as indicated by LastCMOV == MI.
20201 if (LastCMOV == MI &&
20202 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20203 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20204 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20205 CascadedCMOV = &*NextMIIt;
20208 MachineBasicBlock *jcc1MBB = nullptr;
20210 // If we have a cascaded CMOV, we lower it to two successive branches to
20211 // the same block. EFLAGS is used by both, so mark it as live in the second.
20212 if (CascadedCMOV) {
20213 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20214 F->insert(It, jcc1MBB);
20215 jcc1MBB->addLiveIn(X86::EFLAGS);
20218 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20219 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20220 F->insert(It, copy0MBB);
20221 F->insert(It, sinkMBB);
20223 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20224 // live into the sink and copy blocks.
20225 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20227 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20228 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20229 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20230 copy0MBB->addLiveIn(X86::EFLAGS);
20231 sinkMBB->addLiveIn(X86::EFLAGS);
20234 // Transfer the remainder of BB and its successor edges to sinkMBB.
20235 sinkMBB->splice(sinkMBB->begin(), BB,
20236 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20237 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20239 // Add the true and fallthrough blocks as its successors.
20240 if (CascadedCMOV) {
20241 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20242 BB->addSuccessor(jcc1MBB);
20244 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20245 // jump to the sinkMBB.
20246 jcc1MBB->addSuccessor(copy0MBB);
20247 jcc1MBB->addSuccessor(sinkMBB);
20249 BB->addSuccessor(copy0MBB);
20252 // The true block target of the first (or only) branch is always sinkMBB.
20253 BB->addSuccessor(sinkMBB);
20255 // Create the conditional branch instruction.
20256 unsigned Opc = X86::GetCondBranchFromCond(CC);
20257 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20259 if (CascadedCMOV) {
20260 unsigned Opc2 = X86::GetCondBranchFromCond(
20261 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20262 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20266 // %FalseValue = ...
20267 // # fallthrough to sinkMBB
20268 copy0MBB->addSuccessor(sinkMBB);
20271 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20273 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20274 MachineBasicBlock::iterator MIItEnd =
20275 std::next(MachineBasicBlock::iterator(LastCMOV));
20276 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20277 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20278 MachineInstrBuilder MIB;
20280 // As we are creating the PHIs, we have to be careful if there is more than
20281 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20282 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20283 // That also means that PHI construction must work forward from earlier to
20284 // later, and that the code must maintain a mapping from earlier PHI's
20285 // destination registers, and the registers that went into the PHI.
20287 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20288 unsigned DestReg = MIIt->getOperand(0).getReg();
20289 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20290 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20292 // If this CMOV we are generating is the opposite condition from
20293 // the jump we generated, then we have to swap the operands for the
20294 // PHI that is going to be generated.
20295 if (MIIt->getOperand(3).getImm() == OppCC)
20296 std::swap(Op1Reg, Op2Reg);
20298 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20299 Op1Reg = RegRewriteTable[Op1Reg].first;
20301 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20302 Op2Reg = RegRewriteTable[Op2Reg].second;
20304 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20305 TII->get(X86::PHI), DestReg)
20306 .addReg(Op1Reg).addMBB(copy0MBB)
20307 .addReg(Op2Reg).addMBB(thisMBB);
20309 // Add this PHI to the rewrite table.
20310 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20313 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20314 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20315 if (CascadedCMOV) {
20316 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20317 // Copy the PHI result to the register defined by the second CMOV.
20318 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20319 DL, TII->get(TargetOpcode::COPY),
20320 CascadedCMOV->getOperand(0).getReg())
20321 .addReg(MI->getOperand(0).getReg());
20322 CascadedCMOV->eraseFromParent();
20325 // Now remove the CMOV(s).
20326 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20327 (MIIt++)->eraseFromParent();
20332 MachineBasicBlock *
20333 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20334 MachineBasicBlock *BB) const {
20335 // Combine the following atomic floating-point modification pattern:
20336 // a.store(reg OP a.load(acquire), release)
20337 // Transform them into:
20338 // OPss (%gpr), %xmm
20339 // movss %xmm, (%gpr)
20340 // Or sd equivalent for 64-bit operations.
20342 switch (MI->getOpcode()) {
20343 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20344 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20345 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20347 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20348 DebugLoc DL = MI->getDebugLoc();
20349 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20350 unsigned MSrc = MI->getOperand(0).getReg();
20351 unsigned VSrc = MI->getOperand(5).getReg();
20352 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20353 .addReg(/*Base=*/MSrc)
20354 .addImm(/*Scale=*/1)
20355 .addReg(/*Index=*/0)
20358 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20359 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20361 .addReg(/*Base=*/MSrc)
20362 .addImm(/*Scale=*/1)
20363 .addReg(/*Index=*/0)
20364 .addImm(/*Disp=*/0)
20365 .addReg(/*Segment=*/0);
20366 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20367 MI->eraseFromParent(); // The pseudo instruction is gone now.
20371 MachineBasicBlock *
20372 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20373 MachineBasicBlock *BB) const {
20374 MachineFunction *MF = BB->getParent();
20375 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20376 DebugLoc DL = MI->getDebugLoc();
20377 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20379 assert(MF->shouldSplitStack());
20381 const bool Is64Bit = Subtarget->is64Bit();
20382 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20384 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20385 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20388 // ... [Till the alloca]
20389 // If stacklet is not large enough, jump to mallocMBB
20392 // Allocate by subtracting from RSP
20393 // Jump to continueMBB
20396 // Allocate by call to runtime
20400 // [rest of original BB]
20403 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20404 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20405 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20407 MachineRegisterInfo &MRI = MF->getRegInfo();
20408 const TargetRegisterClass *AddrRegClass =
20409 getRegClassFor(getPointerTy(MF->getDataLayout()));
20411 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20412 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20413 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20414 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20415 sizeVReg = MI->getOperand(1).getReg(),
20416 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20418 MachineFunction::iterator MBBIter = BB;
20421 MF->insert(MBBIter, bumpMBB);
20422 MF->insert(MBBIter, mallocMBB);
20423 MF->insert(MBBIter, continueMBB);
20425 continueMBB->splice(continueMBB->begin(), BB,
20426 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20427 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20429 // Add code to the main basic block to check if the stack limit has been hit,
20430 // and if so, jump to mallocMBB otherwise to bumpMBB.
20431 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20432 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20433 .addReg(tmpSPVReg).addReg(sizeVReg);
20434 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20435 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20436 .addReg(SPLimitVReg);
20437 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
20439 // bumpMBB simply decreases the stack pointer, since we know the current
20440 // stacklet has enough space.
20441 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20442 .addReg(SPLimitVReg);
20443 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20444 .addReg(SPLimitVReg);
20445 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20447 // Calls into a routine in libgcc to allocate more space from the heap.
20448 const uint32_t *RegMask =
20449 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
20451 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20453 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20454 .addExternalSymbol("__morestack_allocate_stack_space")
20455 .addRegMask(RegMask)
20456 .addReg(X86::RDI, RegState::Implicit)
20457 .addReg(X86::RAX, RegState::ImplicitDefine);
20458 } else if (Is64Bit) {
20459 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20461 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20462 .addExternalSymbol("__morestack_allocate_stack_space")
20463 .addRegMask(RegMask)
20464 .addReg(X86::EDI, RegState::Implicit)
20465 .addReg(X86::EAX, RegState::ImplicitDefine);
20467 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20469 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20470 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20471 .addExternalSymbol("__morestack_allocate_stack_space")
20472 .addRegMask(RegMask)
20473 .addReg(X86::EAX, RegState::ImplicitDefine);
20477 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20480 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20481 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20482 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
20484 // Set up the CFG correctly.
20485 BB->addSuccessor(bumpMBB);
20486 BB->addSuccessor(mallocMBB);
20487 mallocMBB->addSuccessor(continueMBB);
20488 bumpMBB->addSuccessor(continueMBB);
20490 // Take care of the PHI nodes.
20491 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20492 MI->getOperand(0).getReg())
20493 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20494 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20496 // Delete the original pseudo instruction.
20497 MI->eraseFromParent();
20500 return continueMBB;
20503 MachineBasicBlock *
20504 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20505 MachineBasicBlock *BB) const {
20506 DebugLoc DL = MI->getDebugLoc();
20508 assert(!Subtarget->isTargetMachO());
20510 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
20513 MI->eraseFromParent(); // The pseudo instruction is gone now.
20517 MachineBasicBlock *
20518 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20519 MachineBasicBlock *BB) const {
20520 // This is pretty easy. We're taking the value that we received from
20521 // our load from the relocation, sticking it in either RDI (x86-64)
20522 // or EAX and doing an indirect call. The return value will then
20523 // be in the normal return register.
20524 MachineFunction *F = BB->getParent();
20525 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20526 DebugLoc DL = MI->getDebugLoc();
20528 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20529 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20531 // Get a register mask for the lowered call.
20532 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20533 // proper register mask.
20534 const uint32_t *RegMask =
20535 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
20536 if (Subtarget->is64Bit()) {
20537 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20538 TII->get(X86::MOV64rm), X86::RDI)
20540 .addImm(0).addReg(0)
20541 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20542 MI->getOperand(3).getTargetFlags())
20544 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20545 addDirectMem(MIB, X86::RDI);
20546 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20547 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20548 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20549 TII->get(X86::MOV32rm), X86::EAX)
20551 .addImm(0).addReg(0)
20552 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20553 MI->getOperand(3).getTargetFlags())
20555 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20556 addDirectMem(MIB, X86::EAX);
20557 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20559 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20560 TII->get(X86::MOV32rm), X86::EAX)
20561 .addReg(TII->getGlobalBaseReg(F))
20562 .addImm(0).addReg(0)
20563 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20564 MI->getOperand(3).getTargetFlags())
20566 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20567 addDirectMem(MIB, X86::EAX);
20568 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20571 MI->eraseFromParent(); // The pseudo instruction is gone now.
20575 MachineBasicBlock *
20576 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20577 MachineBasicBlock *MBB) const {
20578 DebugLoc DL = MI->getDebugLoc();
20579 MachineFunction *MF = MBB->getParent();
20580 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20581 MachineRegisterInfo &MRI = MF->getRegInfo();
20583 const BasicBlock *BB = MBB->getBasicBlock();
20584 MachineFunction::iterator I = MBB;
20587 // Memory Reference
20588 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20589 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20592 unsigned MemOpndSlot = 0;
20594 unsigned CurOp = 0;
20596 DstReg = MI->getOperand(CurOp++).getReg();
20597 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20598 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20599 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20600 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20602 MemOpndSlot = CurOp;
20604 MVT PVT = getPointerTy(MF->getDataLayout());
20605 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20606 "Invalid Pointer Size!");
20608 // For v = setjmp(buf), we generate
20611 // buf[LabelOffset] = restoreMBB
20612 // SjLjSetup restoreMBB
20618 // v = phi(main, restore)
20621 // if base pointer being used, load it from frame
20624 MachineBasicBlock *thisMBB = MBB;
20625 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20626 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20627 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20628 MF->insert(I, mainMBB);
20629 MF->insert(I, sinkMBB);
20630 MF->push_back(restoreMBB);
20632 MachineInstrBuilder MIB;
20634 // Transfer the remainder of BB and its successor edges to sinkMBB.
20635 sinkMBB->splice(sinkMBB->begin(), MBB,
20636 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20637 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20640 unsigned PtrStoreOpc = 0;
20641 unsigned LabelReg = 0;
20642 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20643 Reloc::Model RM = MF->getTarget().getRelocationModel();
20644 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20645 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20647 // Prepare IP either in reg or imm.
20648 if (!UseImmLabel) {
20649 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20650 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20651 LabelReg = MRI.createVirtualRegister(PtrRC);
20652 if (Subtarget->is64Bit()) {
20653 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20657 .addMBB(restoreMBB)
20660 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20661 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20662 .addReg(XII->getGlobalBaseReg(MF))
20665 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20669 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20671 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20672 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20673 if (i == X86::AddrDisp)
20674 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20676 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20679 MIB.addReg(LabelReg);
20681 MIB.addMBB(restoreMBB);
20682 MIB.setMemRefs(MMOBegin, MMOEnd);
20684 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20685 .addMBB(restoreMBB);
20687 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20688 MIB.addRegMask(RegInfo->getNoPreservedMask());
20689 thisMBB->addSuccessor(mainMBB);
20690 thisMBB->addSuccessor(restoreMBB);
20694 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20695 mainMBB->addSuccessor(sinkMBB);
20698 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20699 TII->get(X86::PHI), DstReg)
20700 .addReg(mainDstReg).addMBB(mainMBB)
20701 .addReg(restoreDstReg).addMBB(restoreMBB);
20704 if (RegInfo->hasBasePointer(*MF)) {
20705 const bool Uses64BitFramePtr =
20706 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
20707 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20708 X86FI->setRestoreBasePointer(MF);
20709 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20710 unsigned BasePtr = RegInfo->getBaseRegister();
20711 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20712 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20713 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20714 .setMIFlag(MachineInstr::FrameSetup);
20716 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20717 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
20718 restoreMBB->addSuccessor(sinkMBB);
20720 MI->eraseFromParent();
20724 MachineBasicBlock *
20725 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20726 MachineBasicBlock *MBB) const {
20727 DebugLoc DL = MI->getDebugLoc();
20728 MachineFunction *MF = MBB->getParent();
20729 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20730 MachineRegisterInfo &MRI = MF->getRegInfo();
20732 // Memory Reference
20733 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20734 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20736 MVT PVT = getPointerTy(MF->getDataLayout());
20737 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20738 "Invalid Pointer Size!");
20740 const TargetRegisterClass *RC =
20741 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20742 unsigned Tmp = MRI.createVirtualRegister(RC);
20743 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20744 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20745 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20746 unsigned SP = RegInfo->getStackRegister();
20748 MachineInstrBuilder MIB;
20750 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20751 const int64_t SPOffset = 2 * PVT.getStoreSize();
20753 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20754 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20757 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20758 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20759 MIB.addOperand(MI->getOperand(i));
20760 MIB.setMemRefs(MMOBegin, MMOEnd);
20762 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20763 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20764 if (i == X86::AddrDisp)
20765 MIB.addDisp(MI->getOperand(i), LabelOffset);
20767 MIB.addOperand(MI->getOperand(i));
20769 MIB.setMemRefs(MMOBegin, MMOEnd);
20771 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20772 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20773 if (i == X86::AddrDisp)
20774 MIB.addDisp(MI->getOperand(i), SPOffset);
20776 MIB.addOperand(MI->getOperand(i));
20778 MIB.setMemRefs(MMOBegin, MMOEnd);
20780 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20782 MI->eraseFromParent();
20786 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20787 // accumulator loops. Writing back to the accumulator allows the coalescer
20788 // to remove extra copies in the loop.
20789 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
20790 MachineBasicBlock *
20791 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20792 MachineBasicBlock *MBB) const {
20793 MachineOperand &AddendOp = MI->getOperand(3);
20795 // Bail out early if the addend isn't a register - we can't switch these.
20796 if (!AddendOp.isReg())
20799 MachineFunction &MF = *MBB->getParent();
20800 MachineRegisterInfo &MRI = MF.getRegInfo();
20802 // Check whether the addend is defined by a PHI:
20803 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20804 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20805 if (!AddendDef.isPHI())
20808 // Look for the following pattern:
20810 // %addend = phi [%entry, 0], [%loop, %result]
20812 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20816 // %addend = phi [%entry, 0], [%loop, %result]
20818 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20820 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20821 assert(AddendDef.getOperand(i).isReg());
20822 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20823 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20824 if (&PHISrcInst == MI) {
20825 // Found a matching instruction.
20826 unsigned NewFMAOpc = 0;
20827 switch (MI->getOpcode()) {
20828 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20829 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20830 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20831 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20832 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20833 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20834 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20835 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20836 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20837 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20838 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20839 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20840 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20841 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20842 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20843 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20844 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20845 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20846 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20847 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20849 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20850 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20851 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20852 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20853 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20854 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20855 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20856 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20857 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20858 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20859 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20860 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20861 default: llvm_unreachable("Unrecognized FMA variant.");
20864 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
20865 MachineInstrBuilder MIB =
20866 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20867 .addOperand(MI->getOperand(0))
20868 .addOperand(MI->getOperand(3))
20869 .addOperand(MI->getOperand(2))
20870 .addOperand(MI->getOperand(1));
20871 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20872 MI->eraseFromParent();
20879 MachineBasicBlock *
20880 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20881 MachineBasicBlock *BB) const {
20882 switch (MI->getOpcode()) {
20883 default: llvm_unreachable("Unexpected instr type to insert");
20884 case X86::TAILJMPd64:
20885 case X86::TAILJMPr64:
20886 case X86::TAILJMPm64:
20887 case X86::TAILJMPd64_REX:
20888 case X86::TAILJMPr64_REX:
20889 case X86::TAILJMPm64_REX:
20890 llvm_unreachable("TAILJMP64 would not be touched here.");
20891 case X86::TCRETURNdi64:
20892 case X86::TCRETURNri64:
20893 case X86::TCRETURNmi64:
20895 case X86::WIN_ALLOCA:
20896 return EmitLoweredWinAlloca(MI, BB);
20897 case X86::SEG_ALLOCA_32:
20898 case X86::SEG_ALLOCA_64:
20899 return EmitLoweredSegAlloca(MI, BB);
20900 case X86::TLSCall_32:
20901 case X86::TLSCall_64:
20902 return EmitLoweredTLSCall(MI, BB);
20903 case X86::CMOV_FR32:
20904 case X86::CMOV_FR64:
20905 case X86::CMOV_GR8:
20906 case X86::CMOV_GR16:
20907 case X86::CMOV_GR32:
20908 case X86::CMOV_RFP32:
20909 case X86::CMOV_RFP64:
20910 case X86::CMOV_RFP80:
20911 case X86::CMOV_V2F64:
20912 case X86::CMOV_V2I64:
20913 case X86::CMOV_V4F32:
20914 case X86::CMOV_V4F64:
20915 case X86::CMOV_V4I64:
20916 case X86::CMOV_V16F32:
20917 case X86::CMOV_V8F32:
20918 case X86::CMOV_V8F64:
20919 case X86::CMOV_V8I64:
20920 case X86::CMOV_V8I1:
20921 case X86::CMOV_V16I1:
20922 case X86::CMOV_V32I1:
20923 case X86::CMOV_V64I1:
20924 return EmitLoweredSelect(MI, BB);
20926 case X86::RELEASE_FADD32mr:
20927 case X86::RELEASE_FADD64mr:
20928 return EmitLoweredAtomicFP(MI, BB);
20930 case X86::FP32_TO_INT16_IN_MEM:
20931 case X86::FP32_TO_INT32_IN_MEM:
20932 case X86::FP32_TO_INT64_IN_MEM:
20933 case X86::FP64_TO_INT16_IN_MEM:
20934 case X86::FP64_TO_INT32_IN_MEM:
20935 case X86::FP64_TO_INT64_IN_MEM:
20936 case X86::FP80_TO_INT16_IN_MEM:
20937 case X86::FP80_TO_INT32_IN_MEM:
20938 case X86::FP80_TO_INT64_IN_MEM: {
20939 MachineFunction *F = BB->getParent();
20940 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20941 DebugLoc DL = MI->getDebugLoc();
20943 // Change the floating point control register to use "round towards zero"
20944 // mode when truncating to an integer value.
20945 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20946 addFrameReference(BuildMI(*BB, MI, DL,
20947 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20949 // Load the old value of the high byte of the control word...
20951 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20952 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20955 // Set the high part to be round to zero...
20956 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20959 // Reload the modified control word now...
20960 addFrameReference(BuildMI(*BB, MI, DL,
20961 TII->get(X86::FLDCW16m)), CWFrameIdx);
20963 // Restore the memory image of control word to original value
20964 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20967 // Get the X86 opcode to use.
20969 switch (MI->getOpcode()) {
20970 default: llvm_unreachable("illegal opcode!");
20971 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20972 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20973 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20974 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20975 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20976 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20977 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20978 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20979 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20983 MachineOperand &Op = MI->getOperand(0);
20985 AM.BaseType = X86AddressMode::RegBase;
20986 AM.Base.Reg = Op.getReg();
20988 AM.BaseType = X86AddressMode::FrameIndexBase;
20989 AM.Base.FrameIndex = Op.getIndex();
20991 Op = MI->getOperand(1);
20993 AM.Scale = Op.getImm();
20994 Op = MI->getOperand(2);
20996 AM.IndexReg = Op.getImm();
20997 Op = MI->getOperand(3);
20998 if (Op.isGlobal()) {
20999 AM.GV = Op.getGlobal();
21001 AM.Disp = Op.getImm();
21003 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21004 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21006 // Reload the original control word now.
21007 addFrameReference(BuildMI(*BB, MI, DL,
21008 TII->get(X86::FLDCW16m)), CWFrameIdx);
21010 MI->eraseFromParent(); // The pseudo instruction is gone now.
21013 // String/text processing lowering.
21014 case X86::PCMPISTRM128REG:
21015 case X86::VPCMPISTRM128REG:
21016 case X86::PCMPISTRM128MEM:
21017 case X86::VPCMPISTRM128MEM:
21018 case X86::PCMPESTRM128REG:
21019 case X86::VPCMPESTRM128REG:
21020 case X86::PCMPESTRM128MEM:
21021 case X86::VPCMPESTRM128MEM:
21022 assert(Subtarget->hasSSE42() &&
21023 "Target must have SSE4.2 or AVX features enabled");
21024 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21026 // String/text processing lowering.
21027 case X86::PCMPISTRIREG:
21028 case X86::VPCMPISTRIREG:
21029 case X86::PCMPISTRIMEM:
21030 case X86::VPCMPISTRIMEM:
21031 case X86::PCMPESTRIREG:
21032 case X86::VPCMPESTRIREG:
21033 case X86::PCMPESTRIMEM:
21034 case X86::VPCMPESTRIMEM:
21035 assert(Subtarget->hasSSE42() &&
21036 "Target must have SSE4.2 or AVX features enabled");
21037 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21039 // Thread synchronization.
21041 return EmitMonitor(MI, BB, Subtarget);
21045 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21047 case X86::VASTART_SAVE_XMM_REGS:
21048 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21050 case X86::VAARG_64:
21051 return EmitVAARG64WithCustomInserter(MI, BB);
21053 case X86::EH_SjLj_SetJmp32:
21054 case X86::EH_SjLj_SetJmp64:
21055 return emitEHSjLjSetJmp(MI, BB);
21057 case X86::EH_SjLj_LongJmp32:
21058 case X86::EH_SjLj_LongJmp64:
21059 return emitEHSjLjLongJmp(MI, BB);
21061 case TargetOpcode::STATEPOINT:
21062 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21063 // this point in the process. We diverge later.
21064 return emitPatchPoint(MI, BB);
21066 case TargetOpcode::STACKMAP:
21067 case TargetOpcode::PATCHPOINT:
21068 return emitPatchPoint(MI, BB);
21070 case X86::VFMADDPDr213r:
21071 case X86::VFMADDPSr213r:
21072 case X86::VFMADDSDr213r:
21073 case X86::VFMADDSSr213r:
21074 case X86::VFMSUBPDr213r:
21075 case X86::VFMSUBPSr213r:
21076 case X86::VFMSUBSDr213r:
21077 case X86::VFMSUBSSr213r:
21078 case X86::VFNMADDPDr213r:
21079 case X86::VFNMADDPSr213r:
21080 case X86::VFNMADDSDr213r:
21081 case X86::VFNMADDSSr213r:
21082 case X86::VFNMSUBPDr213r:
21083 case X86::VFNMSUBPSr213r:
21084 case X86::VFNMSUBSDr213r:
21085 case X86::VFNMSUBSSr213r:
21086 case X86::VFMADDSUBPDr213r:
21087 case X86::VFMADDSUBPSr213r:
21088 case X86::VFMSUBADDPDr213r:
21089 case X86::VFMSUBADDPSr213r:
21090 case X86::VFMADDPDr213rY:
21091 case X86::VFMADDPSr213rY:
21092 case X86::VFMSUBPDr213rY:
21093 case X86::VFMSUBPSr213rY:
21094 case X86::VFNMADDPDr213rY:
21095 case X86::VFNMADDPSr213rY:
21096 case X86::VFNMSUBPDr213rY:
21097 case X86::VFNMSUBPSr213rY:
21098 case X86::VFMADDSUBPDr213rY:
21099 case X86::VFMADDSUBPSr213rY:
21100 case X86::VFMSUBADDPDr213rY:
21101 case X86::VFMSUBADDPSr213rY:
21102 return emitFMA3Instr(MI, BB);
21106 //===----------------------------------------------------------------------===//
21107 // X86 Optimization Hooks
21108 //===----------------------------------------------------------------------===//
21110 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21113 const SelectionDAG &DAG,
21114 unsigned Depth) const {
21115 unsigned BitWidth = KnownZero.getBitWidth();
21116 unsigned Opc = Op.getOpcode();
21117 assert((Opc >= ISD::BUILTIN_OP_END ||
21118 Opc == ISD::INTRINSIC_WO_CHAIN ||
21119 Opc == ISD::INTRINSIC_W_CHAIN ||
21120 Opc == ISD::INTRINSIC_VOID) &&
21121 "Should use MaskedValueIsZero if you don't know whether Op"
21122 " is a target node!");
21124 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21138 // These nodes' second result is a boolean.
21139 if (Op.getResNo() == 0)
21142 case X86ISD::SETCC:
21143 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21145 case ISD::INTRINSIC_WO_CHAIN: {
21146 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21147 unsigned NumLoBits = 0;
21150 case Intrinsic::x86_sse_movmsk_ps:
21151 case Intrinsic::x86_avx_movmsk_ps_256:
21152 case Intrinsic::x86_sse2_movmsk_pd:
21153 case Intrinsic::x86_avx_movmsk_pd_256:
21154 case Intrinsic::x86_mmx_pmovmskb:
21155 case Intrinsic::x86_sse2_pmovmskb_128:
21156 case Intrinsic::x86_avx2_pmovmskb: {
21157 // High bits of movmskp{s|d}, pmovmskb are known zero.
21159 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21160 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21161 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21162 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21163 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21164 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21165 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21166 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21168 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21177 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21179 const SelectionDAG &,
21180 unsigned Depth) const {
21181 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21182 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21183 return Op.getValueType().getScalarType().getSizeInBits();
21189 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21190 /// node is a GlobalAddress + offset.
21191 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21192 const GlobalValue* &GA,
21193 int64_t &Offset) const {
21194 if (N->getOpcode() == X86ISD::Wrapper) {
21195 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21196 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21197 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21201 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21204 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21205 /// same as extracting the high 128-bit part of 256-bit vector and then
21206 /// inserting the result into the low part of a new 256-bit vector
21207 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21208 EVT VT = SVOp->getValueType(0);
21209 unsigned NumElems = VT.getVectorNumElements();
21211 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21212 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21213 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21214 SVOp->getMaskElt(j) >= 0)
21220 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21221 /// same as extracting the low 128-bit part of 256-bit vector and then
21222 /// inserting the result into the high part of a new 256-bit vector
21223 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21224 EVT VT = SVOp->getValueType(0);
21225 unsigned NumElems = VT.getVectorNumElements();
21227 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21228 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21229 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21230 SVOp->getMaskElt(j) >= 0)
21236 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21237 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21238 TargetLowering::DAGCombinerInfo &DCI,
21239 const X86Subtarget* Subtarget) {
21241 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21242 SDValue V1 = SVOp->getOperand(0);
21243 SDValue V2 = SVOp->getOperand(1);
21244 EVT VT = SVOp->getValueType(0);
21245 unsigned NumElems = VT.getVectorNumElements();
21247 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21248 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21252 // V UNDEF BUILD_VECTOR UNDEF
21254 // CONCAT_VECTOR CONCAT_VECTOR
21257 // RESULT: V + zero extended
21259 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21260 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21261 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21264 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21267 // To match the shuffle mask, the first half of the mask should
21268 // be exactly the first vector, and all the rest a splat with the
21269 // first element of the second one.
21270 for (unsigned i = 0; i != NumElems/2; ++i)
21271 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21272 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21275 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21276 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21277 if (Ld->hasNUsesOfValue(1, 0)) {
21278 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21279 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21281 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21283 Ld->getPointerInfo(),
21284 Ld->getAlignment(),
21285 false/*isVolatile*/, true/*ReadMem*/,
21286 false/*WriteMem*/);
21288 // Make sure the newly-created LOAD is in the same position as Ld in
21289 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21290 // and update uses of Ld's output chain to use the TokenFactor.
21291 if (Ld->hasAnyUseOfValue(1)) {
21292 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21293 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21294 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21295 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21296 SDValue(ResNode.getNode(), 1));
21299 return DAG.getBitcast(VT, ResNode);
21303 // Emit a zeroed vector and insert the desired subvector on its
21305 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21306 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21307 return DCI.CombineTo(N, InsV);
21310 //===--------------------------------------------------------------------===//
21311 // Combine some shuffles into subvector extracts and inserts:
21314 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21315 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21316 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21317 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21318 return DCI.CombineTo(N, InsV);
21321 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21322 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21323 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21324 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21325 return DCI.CombineTo(N, InsV);
21331 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21334 /// This is the leaf of the recursive combinine below. When we have found some
21335 /// chain of single-use x86 shuffle instructions and accumulated the combined
21336 /// shuffle mask represented by them, this will try to pattern match that mask
21337 /// into either a single instruction if there is a special purpose instruction
21338 /// for this operation, or into a PSHUFB instruction which is a fully general
21339 /// instruction but should only be used to replace chains over a certain depth.
21340 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21341 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21342 TargetLowering::DAGCombinerInfo &DCI,
21343 const X86Subtarget *Subtarget) {
21344 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21346 // Find the operand that enters the chain. Note that multiple uses are OK
21347 // here, we're not going to remove the operand we find.
21348 SDValue Input = Op.getOperand(0);
21349 while (Input.getOpcode() == ISD::BITCAST)
21350 Input = Input.getOperand(0);
21352 MVT VT = Input.getSimpleValueType();
21353 MVT RootVT = Root.getSimpleValueType();
21356 // Just remove no-op shuffle masks.
21357 if (Mask.size() == 1) {
21358 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21363 // Use the float domain if the operand type is a floating point type.
21364 bool FloatDomain = VT.isFloatingPoint();
21366 // For floating point shuffles, we don't have free copies in the shuffle
21367 // instructions or the ability to load as part of the instruction, so
21368 // canonicalize their shuffles to UNPCK or MOV variants.
21370 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21371 // vectors because it can have a load folded into it that UNPCK cannot. This
21372 // doesn't preclude something switching to the shorter encoding post-RA.
21374 // FIXME: Should teach these routines about AVX vector widths.
21375 if (FloatDomain && VT.getSizeInBits() == 128) {
21376 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21377 bool Lo = Mask.equals({0, 0});
21380 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21381 // is no slower than UNPCKLPD but has the option to fold the input operand
21382 // into even an unaligned memory load.
21383 if (Lo && Subtarget->hasSSE3()) {
21384 Shuffle = X86ISD::MOVDDUP;
21385 ShuffleVT = MVT::v2f64;
21387 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21388 // than the UNPCK variants.
21389 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21390 ShuffleVT = MVT::v4f32;
21392 if (Depth == 1 && Root->getOpcode() == Shuffle)
21393 return false; // Nothing to do!
21394 Op = DAG.getBitcast(ShuffleVT, Input);
21395 DCI.AddToWorklist(Op.getNode());
21396 if (Shuffle == X86ISD::MOVDDUP)
21397 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21399 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21400 DCI.AddToWorklist(Op.getNode());
21401 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21405 if (Subtarget->hasSSE3() &&
21406 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
21407 bool Lo = Mask.equals({0, 0, 2, 2});
21408 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21409 MVT ShuffleVT = MVT::v4f32;
21410 if (Depth == 1 && Root->getOpcode() == Shuffle)
21411 return false; // Nothing to do!
21412 Op = DAG.getBitcast(ShuffleVT, Input);
21413 DCI.AddToWorklist(Op.getNode());
21414 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21415 DCI.AddToWorklist(Op.getNode());
21416 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21420 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
21421 bool Lo = Mask.equals({0, 0, 1, 1});
21422 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21423 MVT ShuffleVT = MVT::v4f32;
21424 if (Depth == 1 && Root->getOpcode() == Shuffle)
21425 return false; // Nothing to do!
21426 Op = DAG.getBitcast(ShuffleVT, Input);
21427 DCI.AddToWorklist(Op.getNode());
21428 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21429 DCI.AddToWorklist(Op.getNode());
21430 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21436 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21437 // variants as none of these have single-instruction variants that are
21438 // superior to the UNPCK formulation.
21439 if (!FloatDomain && VT.getSizeInBits() == 128 &&
21440 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21441 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
21442 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
21444 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
21445 bool Lo = Mask[0] == 0;
21446 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21447 if (Depth == 1 && Root->getOpcode() == Shuffle)
21448 return false; // Nothing to do!
21450 switch (Mask.size()) {
21452 ShuffleVT = MVT::v8i16;
21455 ShuffleVT = MVT::v16i8;
21458 llvm_unreachable("Impossible mask size!");
21460 Op = DAG.getBitcast(ShuffleVT, Input);
21461 DCI.AddToWorklist(Op.getNode());
21462 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21463 DCI.AddToWorklist(Op.getNode());
21464 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21469 // Don't try to re-form single instruction chains under any circumstances now
21470 // that we've done encoding canonicalization for them.
21474 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21475 // can replace them with a single PSHUFB instruction profitably. Intel's
21476 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21477 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21478 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21479 SmallVector<SDValue, 16> PSHUFBMask;
21480 int NumBytes = VT.getSizeInBits() / 8;
21481 int Ratio = NumBytes / Mask.size();
21482 for (int i = 0; i < NumBytes; ++i) {
21483 if (Mask[i / Ratio] == SM_SentinelUndef) {
21484 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21487 int M = Mask[i / Ratio] != SM_SentinelZero
21488 ? Ratio * Mask[i / Ratio] + i % Ratio
21490 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
21492 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
21493 Op = DAG.getBitcast(ByteVT, Input);
21494 DCI.AddToWorklist(Op.getNode());
21495 SDValue PSHUFBMaskOp =
21496 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
21497 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21498 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
21499 DCI.AddToWorklist(Op.getNode());
21500 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21505 // Failed to find any combines.
21509 /// \brief Fully generic combining of x86 shuffle instructions.
21511 /// This should be the last combine run over the x86 shuffle instructions. Once
21512 /// they have been fully optimized, this will recursively consider all chains
21513 /// of single-use shuffle instructions, build a generic model of the cumulative
21514 /// shuffle operation, and check for simpler instructions which implement this
21515 /// operation. We use this primarily for two purposes:
21517 /// 1) Collapse generic shuffles to specialized single instructions when
21518 /// equivalent. In most cases, this is just an encoding size win, but
21519 /// sometimes we will collapse multiple generic shuffles into a single
21520 /// special-purpose shuffle.
21521 /// 2) Look for sequences of shuffle instructions with 3 or more total
21522 /// instructions, and replace them with the slightly more expensive SSSE3
21523 /// PSHUFB instruction if available. We do this as the last combining step
21524 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21525 /// a suitable short sequence of other instructions. The PHUFB will either
21526 /// use a register or have to read from memory and so is slightly (but only
21527 /// slightly) more expensive than the other shuffle instructions.
21529 /// Because this is inherently a quadratic operation (for each shuffle in
21530 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21531 /// This should never be an issue in practice as the shuffle lowering doesn't
21532 /// produce sequences of more than 8 instructions.
21534 /// FIXME: We will currently miss some cases where the redundant shuffling
21535 /// would simplify under the threshold for PSHUFB formation because of
21536 /// combine-ordering. To fix this, we should do the redundant instruction
21537 /// combining in this recursive walk.
21538 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21539 ArrayRef<int> RootMask,
21540 int Depth, bool HasPSHUFB,
21542 TargetLowering::DAGCombinerInfo &DCI,
21543 const X86Subtarget *Subtarget) {
21544 // Bound the depth of our recursive combine because this is ultimately
21545 // quadratic in nature.
21549 // Directly rip through bitcasts to find the underlying operand.
21550 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21551 Op = Op.getOperand(0);
21553 MVT VT = Op.getSimpleValueType();
21554 if (!VT.isVector())
21555 return false; // Bail if we hit a non-vector.
21557 assert(Root.getSimpleValueType().isVector() &&
21558 "Shuffles operate on vector types!");
21559 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21560 "Can only combine shuffles of the same vector register size.");
21562 if (!isTargetShuffle(Op.getOpcode()))
21564 SmallVector<int, 16> OpMask;
21566 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21567 // We only can combine unary shuffles which we can decode the mask for.
21568 if (!HaveMask || !IsUnary)
21571 assert(VT.getVectorNumElements() == OpMask.size() &&
21572 "Different mask size from vector size!");
21573 assert(((RootMask.size() > OpMask.size() &&
21574 RootMask.size() % OpMask.size() == 0) ||
21575 (OpMask.size() > RootMask.size() &&
21576 OpMask.size() % RootMask.size() == 0) ||
21577 OpMask.size() == RootMask.size()) &&
21578 "The smaller number of elements must divide the larger.");
21579 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21580 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21581 assert(((RootRatio == 1 && OpRatio == 1) ||
21582 (RootRatio == 1) != (OpRatio == 1)) &&
21583 "Must not have a ratio for both incoming and op masks!");
21585 SmallVector<int, 16> Mask;
21586 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21588 // Merge this shuffle operation's mask into our accumulated mask. Note that
21589 // this shuffle's mask will be the first applied to the input, followed by the
21590 // root mask to get us all the way to the root value arrangement. The reason
21591 // for this order is that we are recursing up the operation chain.
21592 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21593 int RootIdx = i / RootRatio;
21594 if (RootMask[RootIdx] < 0) {
21595 // This is a zero or undef lane, we're done.
21596 Mask.push_back(RootMask[RootIdx]);
21600 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21601 int OpIdx = RootMaskedIdx / OpRatio;
21602 if (OpMask[OpIdx] < 0) {
21603 // The incoming lanes are zero or undef, it doesn't matter which ones we
21605 Mask.push_back(OpMask[OpIdx]);
21609 // Ok, we have non-zero lanes, map them through.
21610 Mask.push_back(OpMask[OpIdx] * OpRatio +
21611 RootMaskedIdx % OpRatio);
21614 // See if we can recurse into the operand to combine more things.
21615 switch (Op.getOpcode()) {
21616 case X86ISD::PSHUFB:
21618 case X86ISD::PSHUFD:
21619 case X86ISD::PSHUFHW:
21620 case X86ISD::PSHUFLW:
21621 if (Op.getOperand(0).hasOneUse() &&
21622 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21623 HasPSHUFB, DAG, DCI, Subtarget))
21627 case X86ISD::UNPCKL:
21628 case X86ISD::UNPCKH:
21629 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21630 // We can't check for single use, we have to check that this shuffle is the only user.
21631 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21632 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21633 HasPSHUFB, DAG, DCI, Subtarget))
21638 // Minor canonicalization of the accumulated shuffle mask to make it easier
21639 // to match below. All this does is detect masks with squential pairs of
21640 // elements, and shrink them to the half-width mask. It does this in a loop
21641 // so it will reduce the size of the mask to the minimal width mask which
21642 // performs an equivalent shuffle.
21643 SmallVector<int, 16> WidenedMask;
21644 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21645 Mask = std::move(WidenedMask);
21646 WidenedMask.clear();
21649 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21653 /// \brief Get the PSHUF-style mask from PSHUF node.
21655 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21656 /// PSHUF-style masks that can be reused with such instructions.
21657 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21658 MVT VT = N.getSimpleValueType();
21659 SmallVector<int, 4> Mask;
21661 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
21665 // If we have more than 128-bits, only the low 128-bits of shuffle mask
21666 // matter. Check that the upper masks are repeats and remove them.
21667 if (VT.getSizeInBits() > 128) {
21668 int LaneElts = 128 / VT.getScalarSizeInBits();
21670 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
21671 for (int j = 0; j < LaneElts; ++j)
21672 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
21673 "Mask doesn't repeat in high 128-bit lanes!");
21675 Mask.resize(LaneElts);
21678 switch (N.getOpcode()) {
21679 case X86ISD::PSHUFD:
21681 case X86ISD::PSHUFLW:
21684 case X86ISD::PSHUFHW:
21685 Mask.erase(Mask.begin(), Mask.begin() + 4);
21686 for (int &M : Mask)
21690 llvm_unreachable("No valid shuffle instruction found!");
21694 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21696 /// We walk up the chain and look for a combinable shuffle, skipping over
21697 /// shuffles that we could hoist this shuffle's transformation past without
21698 /// altering anything.
21700 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21702 TargetLowering::DAGCombinerInfo &DCI) {
21703 assert(N.getOpcode() == X86ISD::PSHUFD &&
21704 "Called with something other than an x86 128-bit half shuffle!");
21707 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21708 // of the shuffles in the chain so that we can form a fresh chain to replace
21710 SmallVector<SDValue, 8> Chain;
21711 SDValue V = N.getOperand(0);
21712 for (; V.hasOneUse(); V = V.getOperand(0)) {
21713 switch (V.getOpcode()) {
21715 return SDValue(); // Nothing combined!
21718 // Skip bitcasts as we always know the type for the target specific
21722 case X86ISD::PSHUFD:
21723 // Found another dword shuffle.
21726 case X86ISD::PSHUFLW:
21727 // Check that the low words (being shuffled) are the identity in the
21728 // dword shuffle, and the high words are self-contained.
21729 if (Mask[0] != 0 || Mask[1] != 1 ||
21730 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21733 Chain.push_back(V);
21736 case X86ISD::PSHUFHW:
21737 // Check that the high words (being shuffled) are the identity in the
21738 // dword shuffle, and the low words are self-contained.
21739 if (Mask[2] != 2 || Mask[3] != 3 ||
21740 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21743 Chain.push_back(V);
21746 case X86ISD::UNPCKL:
21747 case X86ISD::UNPCKH:
21748 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21749 // shuffle into a preceding word shuffle.
21750 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
21751 V.getSimpleValueType().getScalarType() != MVT::i16)
21754 // Search for a half-shuffle which we can combine with.
21755 unsigned CombineOp =
21756 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21757 if (V.getOperand(0) != V.getOperand(1) ||
21758 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21760 Chain.push_back(V);
21761 V = V.getOperand(0);
21763 switch (V.getOpcode()) {
21765 return SDValue(); // Nothing to combine.
21767 case X86ISD::PSHUFLW:
21768 case X86ISD::PSHUFHW:
21769 if (V.getOpcode() == CombineOp)
21772 Chain.push_back(V);
21776 V = V.getOperand(0);
21780 } while (V.hasOneUse());
21783 // Break out of the loop if we break out of the switch.
21787 if (!V.hasOneUse())
21788 // We fell out of the loop without finding a viable combining instruction.
21791 // Merge this node's mask and our incoming mask.
21792 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21793 for (int &M : Mask)
21795 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21796 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21798 // Rebuild the chain around this new shuffle.
21799 while (!Chain.empty()) {
21800 SDValue W = Chain.pop_back_val();
21802 if (V.getValueType() != W.getOperand(0).getValueType())
21803 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
21805 switch (W.getOpcode()) {
21807 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21809 case X86ISD::UNPCKL:
21810 case X86ISD::UNPCKH:
21811 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21814 case X86ISD::PSHUFD:
21815 case X86ISD::PSHUFLW:
21816 case X86ISD::PSHUFHW:
21817 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21821 if (V.getValueType() != N.getValueType())
21822 V = DAG.getBitcast(N.getValueType(), V);
21824 // Return the new chain to replace N.
21828 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21830 /// We walk up the chain, skipping shuffles of the other half and looking
21831 /// through shuffles which switch halves trying to find a shuffle of the same
21832 /// pair of dwords.
21833 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21835 TargetLowering::DAGCombinerInfo &DCI) {
21837 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21838 "Called with something other than an x86 128-bit half shuffle!");
21840 unsigned CombineOpcode = N.getOpcode();
21842 // Walk up a single-use chain looking for a combinable shuffle.
21843 SDValue V = N.getOperand(0);
21844 for (; V.hasOneUse(); V = V.getOperand(0)) {
21845 switch (V.getOpcode()) {
21847 return false; // Nothing combined!
21850 // Skip bitcasts as we always know the type for the target specific
21854 case X86ISD::PSHUFLW:
21855 case X86ISD::PSHUFHW:
21856 if (V.getOpcode() == CombineOpcode)
21859 // Other-half shuffles are no-ops.
21862 // Break out of the loop if we break out of the switch.
21866 if (!V.hasOneUse())
21867 // We fell out of the loop without finding a viable combining instruction.
21870 // Combine away the bottom node as its shuffle will be accumulated into
21871 // a preceding shuffle.
21872 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21874 // Record the old value.
21877 // Merge this node's mask and our incoming mask (adjusted to account for all
21878 // the pshufd instructions encountered).
21879 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21880 for (int &M : Mask)
21882 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21883 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21885 // Check that the shuffles didn't cancel each other out. If not, we need to
21886 // combine to the new one.
21888 // Replace the combinable shuffle with the combined one, updating all users
21889 // so that we re-evaluate the chain here.
21890 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21895 /// \brief Try to combine x86 target specific shuffles.
21896 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21897 TargetLowering::DAGCombinerInfo &DCI,
21898 const X86Subtarget *Subtarget) {
21900 MVT VT = N.getSimpleValueType();
21901 SmallVector<int, 4> Mask;
21903 switch (N.getOpcode()) {
21904 case X86ISD::PSHUFD:
21905 case X86ISD::PSHUFLW:
21906 case X86ISD::PSHUFHW:
21907 Mask = getPSHUFShuffleMask(N);
21908 assert(Mask.size() == 4);
21914 // Nuke no-op shuffles that show up after combining.
21915 if (isNoopShuffleMask(Mask))
21916 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21918 // Look for simplifications involving one or two shuffle instructions.
21919 SDValue V = N.getOperand(0);
21920 switch (N.getOpcode()) {
21923 case X86ISD::PSHUFLW:
21924 case X86ISD::PSHUFHW:
21925 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
21927 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21928 return SDValue(); // We combined away this shuffle, so we're done.
21930 // See if this reduces to a PSHUFD which is no more expensive and can
21931 // combine with more operations. Note that it has to at least flip the
21932 // dwords as otherwise it would have been removed as a no-op.
21933 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
21934 int DMask[] = {0, 1, 2, 3};
21935 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21936 DMask[DOffset + 0] = DOffset + 1;
21937 DMask[DOffset + 1] = DOffset + 0;
21938 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
21939 V = DAG.getBitcast(DVT, V);
21940 DCI.AddToWorklist(V.getNode());
21941 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
21942 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
21943 DCI.AddToWorklist(V.getNode());
21944 return DAG.getBitcast(VT, V);
21947 // Look for shuffle patterns which can be implemented as a single unpack.
21948 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21949 // only works when we have a PSHUFD followed by two half-shuffles.
21950 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21951 (V.getOpcode() == X86ISD::PSHUFLW ||
21952 V.getOpcode() == X86ISD::PSHUFHW) &&
21953 V.getOpcode() != N.getOpcode() &&
21955 SDValue D = V.getOperand(0);
21956 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21957 D = D.getOperand(0);
21958 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21959 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21960 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21961 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21962 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21964 for (int i = 0; i < 4; ++i) {
21965 WordMask[i + NOffset] = Mask[i] + NOffset;
21966 WordMask[i + VOffset] = VMask[i] + VOffset;
21968 // Map the word mask through the DWord mask.
21970 for (int i = 0; i < 8; ++i)
21971 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21972 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21973 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21974 // We can replace all three shuffles with an unpack.
21975 V = DAG.getBitcast(VT, D.getOperand(0));
21976 DCI.AddToWorklist(V.getNode());
21977 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21986 case X86ISD::PSHUFD:
21987 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21996 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21998 /// We combine this directly on the abstract vector shuffle nodes so it is
21999 /// easier to generically match. We also insert dummy vector shuffle nodes for
22000 /// the operands which explicitly discard the lanes which are unused by this
22001 /// operation to try to flow through the rest of the combiner the fact that
22002 /// they're unused.
22003 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22005 EVT VT = N->getValueType(0);
22007 // We only handle target-independent shuffles.
22008 // FIXME: It would be easy and harmless to use the target shuffle mask
22009 // extraction tool to support more.
22010 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22013 auto *SVN = cast<ShuffleVectorSDNode>(N);
22014 ArrayRef<int> Mask = SVN->getMask();
22015 SDValue V1 = N->getOperand(0);
22016 SDValue V2 = N->getOperand(1);
22018 // We require the first shuffle operand to be the SUB node, and the second to
22019 // be the ADD node.
22020 // FIXME: We should support the commuted patterns.
22021 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22024 // If there are other uses of these operations we can't fold them.
22025 if (!V1->hasOneUse() || !V2->hasOneUse())
22028 // Ensure that both operations have the same operands. Note that we can
22029 // commute the FADD operands.
22030 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22031 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22032 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22035 // We're looking for blends between FADD and FSUB nodes. We insist on these
22036 // nodes being lined up in a specific expected pattern.
22037 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22038 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22039 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22042 // Only specific types are legal at this point, assert so we notice if and
22043 // when these change.
22044 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22045 VT == MVT::v4f64) &&
22046 "Unknown vector type encountered!");
22048 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22051 /// PerformShuffleCombine - Performs several different shuffle combines.
22052 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22053 TargetLowering::DAGCombinerInfo &DCI,
22054 const X86Subtarget *Subtarget) {
22056 SDValue N0 = N->getOperand(0);
22057 SDValue N1 = N->getOperand(1);
22058 EVT VT = N->getValueType(0);
22060 // Don't create instructions with illegal types after legalize types has run.
22061 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22062 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22065 // If we have legalized the vector types, look for blends of FADD and FSUB
22066 // nodes that we can fuse into an ADDSUB node.
22067 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22068 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22071 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22072 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22073 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22074 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22076 // During Type Legalization, when promoting illegal vector types,
22077 // the backend might introduce new shuffle dag nodes and bitcasts.
22079 // This code performs the following transformation:
22080 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22081 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22083 // We do this only if both the bitcast and the BINOP dag nodes have
22084 // one use. Also, perform this transformation only if the new binary
22085 // operation is legal. This is to avoid introducing dag nodes that
22086 // potentially need to be further expanded (or custom lowered) into a
22087 // less optimal sequence of dag nodes.
22088 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22089 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22090 N0.getOpcode() == ISD::BITCAST) {
22091 SDValue BC0 = N0.getOperand(0);
22092 EVT SVT = BC0.getValueType();
22093 unsigned Opcode = BC0.getOpcode();
22094 unsigned NumElts = VT.getVectorNumElements();
22096 if (BC0.hasOneUse() && SVT.isVector() &&
22097 SVT.getVectorNumElements() * 2 == NumElts &&
22098 TLI.isOperationLegal(Opcode, VT)) {
22099 bool CanFold = false;
22111 unsigned SVTNumElts = SVT.getVectorNumElements();
22112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22113 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22114 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22115 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22116 CanFold = SVOp->getMaskElt(i) < 0;
22119 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22120 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22121 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22122 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22127 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22128 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22129 // consecutive, non-overlapping, and in the right order.
22130 SmallVector<SDValue, 16> Elts;
22131 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22132 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22134 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22137 if (isTargetShuffle(N->getOpcode())) {
22139 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22140 if (Shuffle.getNode())
22143 // Try recursively combining arbitrary sequences of x86 shuffle
22144 // instructions into higher-order shuffles. We do this after combining
22145 // specific PSHUF instruction sequences into their minimal form so that we
22146 // can evaluate how many specialized shuffle instructions are involved in
22147 // a particular chain.
22148 SmallVector<int, 1> NonceMask; // Just a placeholder.
22149 NonceMask.push_back(0);
22150 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22151 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22153 return SDValue(); // This routine will use CombineTo to replace N.
22159 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22160 /// specific shuffle of a load can be folded into a single element load.
22161 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22162 /// shuffles have been custom lowered so we need to handle those here.
22163 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22164 TargetLowering::DAGCombinerInfo &DCI) {
22165 if (DCI.isBeforeLegalizeOps())
22168 SDValue InVec = N->getOperand(0);
22169 SDValue EltNo = N->getOperand(1);
22171 if (!isa<ConstantSDNode>(EltNo))
22174 EVT OriginalVT = InVec.getValueType();
22176 if (InVec.getOpcode() == ISD::BITCAST) {
22177 // Don't duplicate a load with other uses.
22178 if (!InVec.hasOneUse())
22180 EVT BCVT = InVec.getOperand(0).getValueType();
22181 if (!BCVT.isVector() ||
22182 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22184 InVec = InVec.getOperand(0);
22187 EVT CurrentVT = InVec.getValueType();
22189 if (!isTargetShuffle(InVec.getOpcode()))
22192 // Don't duplicate a load with other uses.
22193 if (!InVec.hasOneUse())
22196 SmallVector<int, 16> ShuffleMask;
22198 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22199 ShuffleMask, UnaryShuffle))
22202 // Select the input vector, guarding against out of range extract vector.
22203 unsigned NumElems = CurrentVT.getVectorNumElements();
22204 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22205 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22206 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22207 : InVec.getOperand(1);
22209 // If inputs to shuffle are the same for both ops, then allow 2 uses
22210 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22211 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22213 if (LdNode.getOpcode() == ISD::BITCAST) {
22214 // Don't duplicate a load with other uses.
22215 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22218 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22219 LdNode = LdNode.getOperand(0);
22222 if (!ISD::isNormalLoad(LdNode.getNode()))
22225 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22227 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22230 EVT EltVT = N->getValueType(0);
22231 // If there's a bitcast before the shuffle, check if the load type and
22232 // alignment is valid.
22233 unsigned Align = LN0->getAlignment();
22234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22235 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22236 EltVT.getTypeForEVT(*DAG.getContext()));
22238 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22241 // All checks match so transform back to vector_shuffle so that DAG combiner
22242 // can finish the job
22245 // Create shuffle node taking into account the case that its a unary shuffle
22246 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22247 : InVec.getOperand(1);
22248 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22249 InVec.getOperand(0), Shuffle,
22251 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22252 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22256 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22257 /// special and don't usually play with other vector types, it's better to
22258 /// handle them early to be sure we emit efficient code by avoiding
22259 /// store-load conversions.
22260 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22261 if (N->getValueType(0) != MVT::x86mmx ||
22262 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22263 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22266 SDValue V = N->getOperand(0);
22267 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22268 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22269 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22270 N->getValueType(0), V.getOperand(0));
22275 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22276 /// generation and convert it from being a bunch of shuffles and extracts
22277 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22278 /// storing the value and loading scalars back, while for x64 we should
22279 /// use 64-bit extracts and shifts.
22280 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22281 TargetLowering::DAGCombinerInfo &DCI) {
22282 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22285 SDValue InputVector = N->getOperand(0);
22286 SDLoc dl(InputVector);
22287 // Detect mmx to i32 conversion through a v2i32 elt extract.
22288 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22289 N->getValueType(0) == MVT::i32 &&
22290 InputVector.getValueType() == MVT::v2i32) {
22292 // The bitcast source is a direct mmx result.
22293 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22294 if (MMXSrc.getValueType() == MVT::x86mmx)
22295 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22296 N->getValueType(0),
22297 InputVector.getNode()->getOperand(0));
22299 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22300 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22301 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22302 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22303 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22304 MMXSrcOp.getValueType() == MVT::v1i64 &&
22305 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22306 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22307 N->getValueType(0),
22308 MMXSrcOp.getOperand(0));
22311 EVT VT = N->getValueType(0);
22313 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22314 InputVector.getOpcode() == ISD::BITCAST &&
22315 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22316 uint64_t ExtractedElt =
22317 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22318 uint64_t InputValue =
22319 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22320 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22321 return DAG.getConstant(Res, dl, MVT::i1);
22323 // Only operate on vectors of 4 elements, where the alternative shuffling
22324 // gets to be more expensive.
22325 if (InputVector.getValueType() != MVT::v4i32)
22328 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22329 // single use which is a sign-extend or zero-extend, and all elements are
22331 SmallVector<SDNode *, 4> Uses;
22332 unsigned ExtractedElements = 0;
22333 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22334 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22335 if (UI.getUse().getResNo() != InputVector.getResNo())
22338 SDNode *Extract = *UI;
22339 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22342 if (Extract->getValueType(0) != MVT::i32)
22344 if (!Extract->hasOneUse())
22346 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22347 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22349 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22352 // Record which element was extracted.
22353 ExtractedElements |=
22354 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22356 Uses.push_back(Extract);
22359 // If not all the elements were used, this may not be worthwhile.
22360 if (ExtractedElements != 15)
22363 // Ok, we've now decided to do the transformation.
22364 // If 64-bit shifts are legal, use the extract-shift sequence,
22365 // otherwise bounce the vector off the cache.
22366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22369 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22370 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22371 auto &DL = DAG.getDataLayout();
22372 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22373 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22374 DAG.getConstant(0, dl, VecIdxTy));
22375 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22376 DAG.getConstant(1, dl, VecIdxTy));
22378 SDValue ShAmt = DAG.getConstant(
22379 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22380 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22381 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22382 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22383 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22384 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22385 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22387 // Store the value to a temporary stack slot.
22388 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22389 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22390 MachinePointerInfo(), false, false, 0);
22392 EVT ElementType = InputVector.getValueType().getVectorElementType();
22393 unsigned EltSize = ElementType.getSizeInBits() / 8;
22395 // Replace each use (extract) with a load of the appropriate element.
22396 for (unsigned i = 0; i < 4; ++i) {
22397 uint64_t Offset = EltSize * i;
22398 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
22399 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
22401 SDValue ScalarAddr =
22402 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
22404 // Load the scalar.
22405 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22406 ScalarAddr, MachinePointerInfo(),
22407 false, false, false, 0);
22412 // Replace the extracts
22413 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22414 UE = Uses.end(); UI != UE; ++UI) {
22415 SDNode *Extract = *UI;
22417 SDValue Idx = Extract->getOperand(1);
22418 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22419 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22422 // The replacement was made in place; don't return anything.
22427 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22428 const X86Subtarget *Subtarget) {
22430 SDValue Cond = N->getOperand(0);
22431 SDValue LHS = N->getOperand(1);
22432 SDValue RHS = N->getOperand(2);
22434 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22435 SDValue CondSrc = Cond->getOperand(0);
22436 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22437 Cond = CondSrc->getOperand(0);
22440 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22443 // A vselect where all conditions and data are constants can be optimized into
22444 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22445 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22446 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22449 unsigned MaskValue = 0;
22450 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22453 MVT VT = N->getSimpleValueType(0);
22454 unsigned NumElems = VT.getVectorNumElements();
22455 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22456 for (unsigned i = 0; i < NumElems; ++i) {
22457 // Be sure we emit undef where we can.
22458 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22459 ShuffleMask[i] = -1;
22461 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22465 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22467 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22470 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22472 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22473 TargetLowering::DAGCombinerInfo &DCI,
22474 const X86Subtarget *Subtarget) {
22476 SDValue Cond = N->getOperand(0);
22477 // Get the LHS/RHS of the select.
22478 SDValue LHS = N->getOperand(1);
22479 SDValue RHS = N->getOperand(2);
22480 EVT VT = LHS.getValueType();
22481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22483 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22484 // instructions match the semantics of the common C idiom x<y?x:y but not
22485 // x<=y?x:y, because of how they handle negative zero (which can be
22486 // ignored in unsafe-math mode).
22487 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
22488 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22489 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
22490 (Subtarget->hasSSE2() ||
22491 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22492 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22494 unsigned Opcode = 0;
22495 // Check for x CC y ? x : y.
22496 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22497 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22501 // Converting this to a min would handle NaNs incorrectly, and swapping
22502 // the operands would cause it to handle comparisons between positive
22503 // and negative zero incorrectly.
22504 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22505 if (!DAG.getTarget().Options.UnsafeFPMath &&
22506 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22508 std::swap(LHS, RHS);
22510 Opcode = X86ISD::FMIN;
22513 // Converting this to a min would handle comparisons between positive
22514 // and negative zero incorrectly.
22515 if (!DAG.getTarget().Options.UnsafeFPMath &&
22516 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22518 Opcode = X86ISD::FMIN;
22521 // Converting this to a min would handle both negative zeros and NaNs
22522 // incorrectly, but we can swap the operands to fix both.
22523 std::swap(LHS, RHS);
22527 Opcode = X86ISD::FMIN;
22531 // Converting this to a max would handle comparisons between positive
22532 // and negative zero incorrectly.
22533 if (!DAG.getTarget().Options.UnsafeFPMath &&
22534 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22536 Opcode = X86ISD::FMAX;
22539 // Converting this to a max would handle NaNs incorrectly, and swapping
22540 // the operands would cause it to handle comparisons between positive
22541 // and negative zero incorrectly.
22542 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22543 if (!DAG.getTarget().Options.UnsafeFPMath &&
22544 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22546 std::swap(LHS, RHS);
22548 Opcode = X86ISD::FMAX;
22551 // Converting this to a max would handle both negative zeros and NaNs
22552 // incorrectly, but we can swap the operands to fix both.
22553 std::swap(LHS, RHS);
22557 Opcode = X86ISD::FMAX;
22560 // Check for x CC y ? y : x -- a min/max with reversed arms.
22561 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22562 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22566 // Converting this to a min would handle comparisons between positive
22567 // and negative zero incorrectly, and swapping the operands would
22568 // cause it to handle NaNs incorrectly.
22569 if (!DAG.getTarget().Options.UnsafeFPMath &&
22570 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22571 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22573 std::swap(LHS, RHS);
22575 Opcode = X86ISD::FMIN;
22578 // Converting this to a min would handle NaNs incorrectly.
22579 if (!DAG.getTarget().Options.UnsafeFPMath &&
22580 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22582 Opcode = X86ISD::FMIN;
22585 // Converting this to a min would handle both negative zeros and NaNs
22586 // incorrectly, but we can swap the operands to fix both.
22587 std::swap(LHS, RHS);
22591 Opcode = X86ISD::FMIN;
22595 // Converting this to a max would handle NaNs incorrectly.
22596 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22598 Opcode = X86ISD::FMAX;
22601 // Converting this to a max would handle comparisons between positive
22602 // and negative zero incorrectly, and swapping the operands would
22603 // cause it to handle NaNs incorrectly.
22604 if (!DAG.getTarget().Options.UnsafeFPMath &&
22605 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22606 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22608 std::swap(LHS, RHS);
22610 Opcode = X86ISD::FMAX;
22613 // Converting this to a max would handle both negative zeros and NaNs
22614 // incorrectly, but we can swap the operands to fix both.
22615 std::swap(LHS, RHS);
22619 Opcode = X86ISD::FMAX;
22625 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22628 EVT CondVT = Cond.getValueType();
22629 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22630 CondVT.getVectorElementType() == MVT::i1) {
22631 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22632 // lowering on KNL. In this case we convert it to
22633 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22634 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22635 // Since SKX these selects have a proper lowering.
22636 EVT OpVT = LHS.getValueType();
22637 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22638 (OpVT.getVectorElementType() == MVT::i8 ||
22639 OpVT.getVectorElementType() == MVT::i16) &&
22640 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22641 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22642 DCI.AddToWorklist(Cond.getNode());
22643 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22646 // If this is a select between two integer constants, try to do some
22648 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22649 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22650 // Don't do this for crazy integer types.
22651 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22652 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22653 // so that TrueC (the true value) is larger than FalseC.
22654 bool NeedsCondInvert = false;
22656 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22657 // Efficiently invertible.
22658 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22659 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22660 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22661 NeedsCondInvert = true;
22662 std::swap(TrueC, FalseC);
22665 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22666 if (FalseC->getAPIntValue() == 0 &&
22667 TrueC->getAPIntValue().isPowerOf2()) {
22668 if (NeedsCondInvert) // Invert the condition if needed.
22669 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22670 DAG.getConstant(1, DL, Cond.getValueType()));
22672 // Zero extend the condition if needed.
22673 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22675 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22676 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22677 DAG.getConstant(ShAmt, DL, MVT::i8));
22680 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22681 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22682 if (NeedsCondInvert) // Invert the condition if needed.
22683 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22684 DAG.getConstant(1, DL, Cond.getValueType()));
22686 // Zero extend the condition if needed.
22687 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22688 FalseC->getValueType(0), Cond);
22689 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22690 SDValue(FalseC, 0));
22693 // Optimize cases that will turn into an LEA instruction. This requires
22694 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22695 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22696 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22697 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22699 bool isFastMultiplier = false;
22701 switch ((unsigned char)Diff) {
22703 case 1: // result = add base, cond
22704 case 2: // result = lea base( , cond*2)
22705 case 3: // result = lea base(cond, cond*2)
22706 case 4: // result = lea base( , cond*4)
22707 case 5: // result = lea base(cond, cond*4)
22708 case 8: // result = lea base( , cond*8)
22709 case 9: // result = lea base(cond, cond*8)
22710 isFastMultiplier = true;
22715 if (isFastMultiplier) {
22716 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22717 if (NeedsCondInvert) // Invert the condition if needed.
22718 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22719 DAG.getConstant(1, DL, Cond.getValueType()));
22721 // Zero extend the condition if needed.
22722 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22724 // Scale the condition by the difference.
22726 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22727 DAG.getConstant(Diff, DL,
22728 Cond.getValueType()));
22730 // Add the base if non-zero.
22731 if (FalseC->getAPIntValue() != 0)
22732 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22733 SDValue(FalseC, 0));
22740 // Canonicalize max and min:
22741 // (x > y) ? x : y -> (x >= y) ? x : y
22742 // (x < y) ? x : y -> (x <= y) ? x : y
22743 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22744 // the need for an extra compare
22745 // against zero. e.g.
22746 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22748 // testl %edi, %edi
22750 // cmovgl %edi, %eax
22754 // cmovsl %eax, %edi
22755 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22756 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22757 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22758 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22763 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22764 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22765 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22766 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22771 // Early exit check
22772 if (!TLI.isTypeLegal(VT))
22775 // Match VSELECTs into subs with unsigned saturation.
22776 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22777 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22778 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22779 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22780 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22782 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22783 // left side invert the predicate to simplify logic below.
22785 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22787 CC = ISD::getSetCCInverse(CC, true);
22788 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22792 if (Other.getNode() && Other->getNumOperands() == 2 &&
22793 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22794 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22795 SDValue CondRHS = Cond->getOperand(1);
22797 // Look for a general sub with unsigned saturation first.
22798 // x >= y ? x-y : 0 --> subus x, y
22799 // x > y ? x-y : 0 --> subus x, y
22800 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22801 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22802 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22804 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22805 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22806 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22807 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22808 // If the RHS is a constant we have to reverse the const
22809 // canonicalization.
22810 // x > C-1 ? x+-C : 0 --> subus x, C
22811 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22812 CondRHSConst->getAPIntValue() ==
22813 (-OpRHSConst->getAPIntValue() - 1))
22814 return DAG.getNode(
22815 X86ISD::SUBUS, DL, VT, OpLHS,
22816 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
22818 // Another special case: If C was a sign bit, the sub has been
22819 // canonicalized into a xor.
22820 // FIXME: Would it be better to use computeKnownBits to determine
22821 // whether it's safe to decanonicalize the xor?
22822 // x s< 0 ? x^C : 0 --> subus x, C
22823 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22824 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22825 OpRHSConst->getAPIntValue().isSignBit())
22826 // Note that we have to rebuild the RHS constant here to ensure we
22827 // don't rely on particular values of undef lanes.
22828 return DAG.getNode(
22829 X86ISD::SUBUS, DL, VT, OpLHS,
22830 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
22835 // Simplify vector selection if condition value type matches vselect
22837 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22838 assert(Cond.getValueType().isVector() &&
22839 "vector select expects a vector selector!");
22841 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22842 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22844 // Try invert the condition if true value is not all 1s and false value
22846 if (!TValIsAllOnes && !FValIsAllZeros &&
22847 // Check if the selector will be produced by CMPP*/PCMP*
22848 Cond.getOpcode() == ISD::SETCC &&
22849 // Check if SETCC has already been promoted
22850 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
22852 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22853 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22855 if (TValIsAllZeros || FValIsAllOnes) {
22856 SDValue CC = Cond.getOperand(2);
22857 ISD::CondCode NewCC =
22858 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22859 Cond.getOperand(0).getValueType().isInteger());
22860 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22861 std::swap(LHS, RHS);
22862 TValIsAllOnes = FValIsAllOnes;
22863 FValIsAllZeros = TValIsAllZeros;
22867 if (TValIsAllOnes || FValIsAllZeros) {
22870 if (TValIsAllOnes && FValIsAllZeros)
22872 else if (TValIsAllOnes)
22874 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22875 else if (FValIsAllZeros)
22876 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22877 DAG.getBitcast(CondVT, LHS));
22879 return DAG.getBitcast(VT, Ret);
22883 // We should generate an X86ISD::BLENDI from a vselect if its argument
22884 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22885 // constants. This specific pattern gets generated when we split a
22886 // selector for a 512 bit vector in a machine without AVX512 (but with
22887 // 256-bit vectors), during legalization:
22889 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22891 // Iff we find this pattern and the build_vectors are built from
22892 // constants, we translate the vselect into a shuffle_vector that we
22893 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22894 if ((N->getOpcode() == ISD::VSELECT ||
22895 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22896 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22897 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22898 if (Shuffle.getNode())
22902 // If this is a *dynamic* select (non-constant condition) and we can match
22903 // this node with one of the variable blend instructions, restructure the
22904 // condition so that the blends can use the high bit of each element and use
22905 // SimplifyDemandedBits to simplify the condition operand.
22906 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22907 !DCI.isBeforeLegalize() &&
22908 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22909 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22911 // Don't optimize vector selects that map to mask-registers.
22915 // We can only handle the cases where VSELECT is directly legal on the
22916 // subtarget. We custom lower VSELECT nodes with constant conditions and
22917 // this makes it hard to see whether a dynamic VSELECT will correctly
22918 // lower, so we both check the operation's status and explicitly handle the
22919 // cases where a *dynamic* blend will fail even though a constant-condition
22920 // blend could be custom lowered.
22921 // FIXME: We should find a better way to handle this class of problems.
22922 // Potentially, we should combine constant-condition vselect nodes
22923 // pre-legalization into shuffles and not mark as many types as custom
22925 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22927 // FIXME: We don't support i16-element blends currently. We could and
22928 // should support them by making *all* the bits in the condition be set
22929 // rather than just the high bit and using an i8-element blend.
22930 if (VT.getScalarType() == MVT::i16)
22932 // Dynamic blending was only available from SSE4.1 onward.
22933 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22935 // Byte blends are only available in AVX2
22936 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22937 !Subtarget->hasAVX2())
22940 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22941 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22943 APInt KnownZero, KnownOne;
22944 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22945 DCI.isBeforeLegalizeOps());
22946 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22947 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22949 // If we changed the computation somewhere in the DAG, this change
22950 // will affect all users of Cond.
22951 // Make sure it is fine and update all the nodes so that we do not
22952 // use the generic VSELECT anymore. Otherwise, we may perform
22953 // wrong optimizations as we messed up with the actual expectation
22954 // for the vector boolean values.
22955 if (Cond != TLO.Old) {
22956 // Check all uses of that condition operand to check whether it will be
22957 // consumed by non-BLEND instructions, which may depend on all bits are
22959 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22961 if (I->getOpcode() != ISD::VSELECT)
22962 // TODO: Add other opcodes eventually lowered into BLEND.
22965 // Update all the users of the condition, before committing the change,
22966 // so that the VSELECT optimizations that expect the correct vector
22967 // boolean value will not be triggered.
22968 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22970 DAG.ReplaceAllUsesOfValueWith(
22972 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22973 Cond, I->getOperand(1), I->getOperand(2)));
22974 DCI.CommitTargetLoweringOpt(TLO);
22977 // At this point, only Cond is changed. Change the condition
22978 // just for N to keep the opportunity to optimize all other
22979 // users their own way.
22980 DAG.ReplaceAllUsesOfValueWith(
22982 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22983 TLO.New, N->getOperand(1), N->getOperand(2)));
22991 // Check whether a boolean test is testing a boolean value generated by
22992 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22995 // Simplify the following patterns:
22996 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22997 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22998 // to (Op EFLAGS Cond)
23000 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23001 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23002 // to (Op EFLAGS !Cond)
23004 // where Op could be BRCOND or CMOV.
23006 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23007 // Quit if not CMP and SUB with its value result used.
23008 if (Cmp.getOpcode() != X86ISD::CMP &&
23009 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23012 // Quit if not used as a boolean value.
23013 if (CC != X86::COND_E && CC != X86::COND_NE)
23016 // Check CMP operands. One of them should be 0 or 1 and the other should be
23017 // an SetCC or extended from it.
23018 SDValue Op1 = Cmp.getOperand(0);
23019 SDValue Op2 = Cmp.getOperand(1);
23022 const ConstantSDNode* C = nullptr;
23023 bool needOppositeCond = (CC == X86::COND_E);
23024 bool checkAgainstTrue = false; // Is it a comparison against 1?
23026 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23028 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23030 else // Quit if all operands are not constants.
23033 if (C->getZExtValue() == 1) {
23034 needOppositeCond = !needOppositeCond;
23035 checkAgainstTrue = true;
23036 } else if (C->getZExtValue() != 0)
23037 // Quit if the constant is neither 0 or 1.
23040 bool truncatedToBoolWithAnd = false;
23041 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23042 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23043 SetCC.getOpcode() == ISD::TRUNCATE ||
23044 SetCC.getOpcode() == ISD::AND) {
23045 if (SetCC.getOpcode() == ISD::AND) {
23047 ConstantSDNode *CS;
23048 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23049 CS->getZExtValue() == 1)
23051 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23052 CS->getZExtValue() == 1)
23056 SetCC = SetCC.getOperand(OpIdx);
23057 truncatedToBoolWithAnd = true;
23059 SetCC = SetCC.getOperand(0);
23062 switch (SetCC.getOpcode()) {
23063 case X86ISD::SETCC_CARRY:
23064 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23065 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23066 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23067 // truncated to i1 using 'and'.
23068 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23070 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23071 "Invalid use of SETCC_CARRY!");
23073 case X86ISD::SETCC:
23074 // Set the condition code or opposite one if necessary.
23075 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23076 if (needOppositeCond)
23077 CC = X86::GetOppositeBranchCondition(CC);
23078 return SetCC.getOperand(1);
23079 case X86ISD::CMOV: {
23080 // Check whether false/true value has canonical one, i.e. 0 or 1.
23081 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23082 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23083 // Quit if true value is not a constant.
23086 // Quit if false value is not a constant.
23088 SDValue Op = SetCC.getOperand(0);
23089 // Skip 'zext' or 'trunc' node.
23090 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23091 Op.getOpcode() == ISD::TRUNCATE)
23092 Op = Op.getOperand(0);
23093 // A special case for rdrand/rdseed, where 0 is set if false cond is
23095 if ((Op.getOpcode() != X86ISD::RDRAND &&
23096 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23099 // Quit if false value is not the constant 0 or 1.
23100 bool FValIsFalse = true;
23101 if (FVal && FVal->getZExtValue() != 0) {
23102 if (FVal->getZExtValue() != 1)
23104 // If FVal is 1, opposite cond is needed.
23105 needOppositeCond = !needOppositeCond;
23106 FValIsFalse = false;
23108 // Quit if TVal is not the constant opposite of FVal.
23109 if (FValIsFalse && TVal->getZExtValue() != 1)
23111 if (!FValIsFalse && TVal->getZExtValue() != 0)
23113 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23114 if (needOppositeCond)
23115 CC = X86::GetOppositeBranchCondition(CC);
23116 return SetCC.getOperand(3);
23123 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23125 /// (X86or (X86setcc) (X86setcc))
23126 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23127 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23128 X86::CondCode &CC1, SDValue &Flags,
23130 if (Cond->getOpcode() == X86ISD::CMP) {
23131 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23132 if (!CondOp1C || !CondOp1C->isNullValue())
23135 Cond = Cond->getOperand(0);
23140 SDValue SetCC0, SetCC1;
23141 switch (Cond->getOpcode()) {
23142 default: return false;
23149 SetCC0 = Cond->getOperand(0);
23150 SetCC1 = Cond->getOperand(1);
23154 // Make sure we have SETCC nodes, using the same flags value.
23155 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23156 SetCC1.getOpcode() != X86ISD::SETCC ||
23157 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23160 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23161 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23162 Flags = SetCC0->getOperand(1);
23166 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23167 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23168 TargetLowering::DAGCombinerInfo &DCI,
23169 const X86Subtarget *Subtarget) {
23172 // If the flag operand isn't dead, don't touch this CMOV.
23173 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23176 SDValue FalseOp = N->getOperand(0);
23177 SDValue TrueOp = N->getOperand(1);
23178 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23179 SDValue Cond = N->getOperand(3);
23181 if (CC == X86::COND_E || CC == X86::COND_NE) {
23182 switch (Cond.getOpcode()) {
23186 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23187 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23188 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23194 Flags = checkBoolTestSetCCCombine(Cond, CC);
23195 if (Flags.getNode() &&
23196 // Extra check as FCMOV only supports a subset of X86 cond.
23197 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23198 SDValue Ops[] = { FalseOp, TrueOp,
23199 DAG.getConstant(CC, DL, MVT::i8), Flags };
23200 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23203 // If this is a select between two integer constants, try to do some
23204 // optimizations. Note that the operands are ordered the opposite of SELECT
23206 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23207 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23208 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23209 // larger than FalseC (the false value).
23210 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23211 CC = X86::GetOppositeBranchCondition(CC);
23212 std::swap(TrueC, FalseC);
23213 std::swap(TrueOp, FalseOp);
23216 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23217 // This is efficient for any integer data type (including i8/i16) and
23219 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23220 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23221 DAG.getConstant(CC, DL, MVT::i8), Cond);
23223 // Zero extend the condition if needed.
23224 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23226 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23227 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23228 DAG.getConstant(ShAmt, DL, MVT::i8));
23229 if (N->getNumValues() == 2) // Dead flag value?
23230 return DCI.CombineTo(N, Cond, SDValue());
23234 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23235 // for any integer data type, including i8/i16.
23236 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23237 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23238 DAG.getConstant(CC, DL, MVT::i8), Cond);
23240 // Zero extend the condition if needed.
23241 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23242 FalseC->getValueType(0), Cond);
23243 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23244 SDValue(FalseC, 0));
23246 if (N->getNumValues() == 2) // Dead flag value?
23247 return DCI.CombineTo(N, Cond, SDValue());
23251 // Optimize cases that will turn into an LEA instruction. This requires
23252 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23253 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23254 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23255 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23257 bool isFastMultiplier = false;
23259 switch ((unsigned char)Diff) {
23261 case 1: // result = add base, cond
23262 case 2: // result = lea base( , cond*2)
23263 case 3: // result = lea base(cond, cond*2)
23264 case 4: // result = lea base( , cond*4)
23265 case 5: // result = lea base(cond, cond*4)
23266 case 8: // result = lea base( , cond*8)
23267 case 9: // result = lea base(cond, cond*8)
23268 isFastMultiplier = true;
23273 if (isFastMultiplier) {
23274 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23275 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23276 DAG.getConstant(CC, DL, MVT::i8), Cond);
23277 // Zero extend the condition if needed.
23278 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23280 // Scale the condition by the difference.
23282 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23283 DAG.getConstant(Diff, DL, Cond.getValueType()));
23285 // Add the base if non-zero.
23286 if (FalseC->getAPIntValue() != 0)
23287 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23288 SDValue(FalseC, 0));
23289 if (N->getNumValues() == 2) // Dead flag value?
23290 return DCI.CombineTo(N, Cond, SDValue());
23297 // Handle these cases:
23298 // (select (x != c), e, c) -> select (x != c), e, x),
23299 // (select (x == c), c, e) -> select (x == c), x, e)
23300 // where the c is an integer constant, and the "select" is the combination
23301 // of CMOV and CMP.
23303 // The rationale for this change is that the conditional-move from a constant
23304 // needs two instructions, however, conditional-move from a register needs
23305 // only one instruction.
23307 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23308 // some instruction-combining opportunities. This opt needs to be
23309 // postponed as late as possible.
23311 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23312 // the DCI.xxxx conditions are provided to postpone the optimization as
23313 // late as possible.
23315 ConstantSDNode *CmpAgainst = nullptr;
23316 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23317 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23318 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23320 if (CC == X86::COND_NE &&
23321 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23322 CC = X86::GetOppositeBranchCondition(CC);
23323 std::swap(TrueOp, FalseOp);
23326 if (CC == X86::COND_E &&
23327 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23328 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23329 DAG.getConstant(CC, DL, MVT::i8), Cond };
23330 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23335 // Fold and/or of setcc's to double CMOV:
23336 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23337 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23339 // This combine lets us generate:
23340 // cmovcc1 (jcc1 if we don't have CMOV)
23346 // cmovne (jne if we don't have CMOV)
23347 // When we can't use the CMOV instruction, it might increase branch
23349 // When we can use CMOV, or when there is no mispredict, this improves
23350 // throughput and reduces register pressure.
23352 if (CC == X86::COND_NE) {
23354 X86::CondCode CC0, CC1;
23356 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23358 std::swap(FalseOp, TrueOp);
23359 CC0 = X86::GetOppositeBranchCondition(CC0);
23360 CC1 = X86::GetOppositeBranchCondition(CC1);
23363 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23365 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23366 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23367 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23368 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23376 /// PerformMulCombine - Optimize a single multiply with constant into two
23377 /// in order to implement it with two cheaper instructions, e.g.
23378 /// LEA + SHL, LEA + LEA.
23379 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23380 TargetLowering::DAGCombinerInfo &DCI) {
23381 // An imul is usually smaller than the alternative sequence.
23382 if (DAG.getMachineFunction().getFunction()->optForMinSize())
23385 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23388 EVT VT = N->getValueType(0);
23389 if (VT != MVT::i64 && VT != MVT::i32)
23392 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23395 uint64_t MulAmt = C->getZExtValue();
23396 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23399 uint64_t MulAmt1 = 0;
23400 uint64_t MulAmt2 = 0;
23401 if ((MulAmt % 9) == 0) {
23403 MulAmt2 = MulAmt / 9;
23404 } else if ((MulAmt % 5) == 0) {
23406 MulAmt2 = MulAmt / 5;
23407 } else if ((MulAmt % 3) == 0) {
23409 MulAmt2 = MulAmt / 3;
23412 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23415 if (isPowerOf2_64(MulAmt2) &&
23416 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23417 // If second multiplifer is pow2, issue it first. We want the multiply by
23418 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23420 std::swap(MulAmt1, MulAmt2);
23423 if (isPowerOf2_64(MulAmt1))
23424 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23425 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
23427 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23428 DAG.getConstant(MulAmt1, DL, VT));
23430 if (isPowerOf2_64(MulAmt2))
23431 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23432 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
23434 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23435 DAG.getConstant(MulAmt2, DL, VT));
23437 // Do not add new nodes to DAG combiner worklist.
23438 DCI.CombineTo(N, NewMul, false);
23443 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23444 SDValue N0 = N->getOperand(0);
23445 SDValue N1 = N->getOperand(1);
23446 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23447 EVT VT = N0.getValueType();
23449 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23450 // since the result of setcc_c is all zero's or all ones.
23451 if (VT.isInteger() && !VT.isVector() &&
23452 N1C && N0.getOpcode() == ISD::AND &&
23453 N0.getOperand(1).getOpcode() == ISD::Constant) {
23454 SDValue N00 = N0.getOperand(0);
23455 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23456 APInt ShAmt = N1C->getAPIntValue();
23457 Mask = Mask.shl(ShAmt);
23458 bool MaskOK = false;
23459 // We can handle cases concerning bit-widening nodes containing setcc_c if
23460 // we carefully interrogate the mask to make sure we are semantics
23462 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
23463 // of the underlying setcc_c operation if the setcc_c was zero extended.
23464 // Consider the following example:
23465 // zext(setcc_c) -> i32 0x0000FFFF
23466 // c1 -> i32 0x0000FFFF
23467 // c2 -> i32 0x00000001
23468 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
23469 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
23470 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23472 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
23473 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
23475 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
23476 N00.getOpcode() == ISD::ANY_EXTEND) &&
23477 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
23478 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
23480 if (MaskOK && Mask != 0) {
23482 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
23486 // Hardware support for vector shifts is sparse which makes us scalarize the
23487 // vector operations in many cases. Also, on sandybridge ADD is faster than
23489 // (shl V, 1) -> add V,V
23490 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23491 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23492 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23493 // We shift all of the values by one. In many cases we do not have
23494 // hardware support for this operation. This is better expressed as an ADD
23496 if (N1SplatC->getAPIntValue() == 1)
23497 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23503 /// \brief Returns a vector of 0s if the node in input is a vector logical
23504 /// shift by a constant amount which is known to be bigger than or equal
23505 /// to the vector element size in bits.
23506 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23507 const X86Subtarget *Subtarget) {
23508 EVT VT = N->getValueType(0);
23510 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23511 (!Subtarget->hasInt256() ||
23512 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23515 SDValue Amt = N->getOperand(1);
23517 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23518 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23519 APInt ShiftAmt = AmtSplat->getAPIntValue();
23520 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23522 // SSE2/AVX2 logical shifts always return a vector of 0s
23523 // if the shift amount is bigger than or equal to
23524 // the element size. The constant shift amount will be
23525 // encoded as a 8-bit immediate.
23526 if (ShiftAmt.trunc(8).uge(MaxAmount))
23527 return getZeroVector(VT, Subtarget, DAG, DL);
23533 /// PerformShiftCombine - Combine shifts.
23534 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23535 TargetLowering::DAGCombinerInfo &DCI,
23536 const X86Subtarget *Subtarget) {
23537 if (N->getOpcode() == ISD::SHL)
23538 if (SDValue V = PerformSHLCombine(N, DAG))
23541 // Try to fold this logical shift into a zero vector.
23542 if (N->getOpcode() != ISD::SRA)
23543 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
23549 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23550 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23551 // and friends. Likewise for OR -> CMPNEQSS.
23552 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23553 TargetLowering::DAGCombinerInfo &DCI,
23554 const X86Subtarget *Subtarget) {
23557 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23558 // we're requiring SSE2 for both.
23559 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23560 SDValue N0 = N->getOperand(0);
23561 SDValue N1 = N->getOperand(1);
23562 SDValue CMP0 = N0->getOperand(1);
23563 SDValue CMP1 = N1->getOperand(1);
23566 // The SETCCs should both refer to the same CMP.
23567 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23570 SDValue CMP00 = CMP0->getOperand(0);
23571 SDValue CMP01 = CMP0->getOperand(1);
23572 EVT VT = CMP00.getValueType();
23574 if (VT == MVT::f32 || VT == MVT::f64) {
23575 bool ExpectingFlags = false;
23576 // Check for any users that want flags:
23577 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23578 !ExpectingFlags && UI != UE; ++UI)
23579 switch (UI->getOpcode()) {
23584 ExpectingFlags = true;
23586 case ISD::CopyToReg:
23587 case ISD::SIGN_EXTEND:
23588 case ISD::ZERO_EXTEND:
23589 case ISD::ANY_EXTEND:
23593 if (!ExpectingFlags) {
23594 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23595 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23597 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23598 X86::CondCode tmp = cc0;
23603 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23604 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23605 // FIXME: need symbolic constants for these magic numbers.
23606 // See X86ATTInstPrinter.cpp:printSSECC().
23607 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23608 if (Subtarget->hasAVX512()) {
23609 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23611 DAG.getConstant(x86cc, DL, MVT::i8));
23612 if (N->getValueType(0) != MVT::i1)
23613 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23617 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23618 CMP00.getValueType(), CMP00, CMP01,
23619 DAG.getConstant(x86cc, DL,
23622 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23623 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23625 if (is64BitFP && !Subtarget->is64Bit()) {
23626 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23627 // 64-bit integer, since that's not a legal type. Since
23628 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23629 // bits, but can do this little dance to extract the lowest 32 bits
23630 // and work with those going forward.
23631 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23633 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
23634 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23635 Vector32, DAG.getIntPtrConstant(0, DL));
23639 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23640 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23641 DAG.getConstant(1, DL, IntVT));
23642 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
23644 return OneBitOfTruth;
23652 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23653 /// so it can be folded inside ANDNP.
23654 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23655 EVT VT = N->getValueType(0);
23657 // Match direct AllOnes for 128 and 256-bit vectors
23658 if (ISD::isBuildVectorAllOnes(N))
23661 // Look through a bit convert.
23662 if (N->getOpcode() == ISD::BITCAST)
23663 N = N->getOperand(0).getNode();
23665 // Sometimes the operand may come from a insert_subvector building a 256-bit
23667 if (VT.is256BitVector() &&
23668 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23669 SDValue V1 = N->getOperand(0);
23670 SDValue V2 = N->getOperand(1);
23672 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23673 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23674 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23675 ISD::isBuildVectorAllOnes(V2.getNode()))
23682 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23683 // register. In most cases we actually compare or select YMM-sized registers
23684 // and mixing the two types creates horrible code. This method optimizes
23685 // some of the transition sequences.
23686 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23687 TargetLowering::DAGCombinerInfo &DCI,
23688 const X86Subtarget *Subtarget) {
23689 EVT VT = N->getValueType(0);
23690 if (!VT.is256BitVector())
23693 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23694 N->getOpcode() == ISD::ZERO_EXTEND ||
23695 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23697 SDValue Narrow = N->getOperand(0);
23698 EVT NarrowVT = Narrow->getValueType(0);
23699 if (!NarrowVT.is128BitVector())
23702 if (Narrow->getOpcode() != ISD::XOR &&
23703 Narrow->getOpcode() != ISD::AND &&
23704 Narrow->getOpcode() != ISD::OR)
23707 SDValue N0 = Narrow->getOperand(0);
23708 SDValue N1 = Narrow->getOperand(1);
23711 // The Left side has to be a trunc.
23712 if (N0.getOpcode() != ISD::TRUNCATE)
23715 // The type of the truncated inputs.
23716 EVT WideVT = N0->getOperand(0)->getValueType(0);
23720 // The right side has to be a 'trunc' or a constant vector.
23721 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23722 ConstantSDNode *RHSConstSplat = nullptr;
23723 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23724 RHSConstSplat = RHSBV->getConstantSplatNode();
23725 if (!RHSTrunc && !RHSConstSplat)
23728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23730 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23733 // Set N0 and N1 to hold the inputs to the new wide operation.
23734 N0 = N0->getOperand(0);
23735 if (RHSConstSplat) {
23736 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23737 SDValue(RHSConstSplat, 0));
23738 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23739 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23740 } else if (RHSTrunc) {
23741 N1 = N1->getOperand(0);
23744 // Generate the wide operation.
23745 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23746 unsigned Opcode = N->getOpcode();
23748 case ISD::ANY_EXTEND:
23750 case ISD::ZERO_EXTEND: {
23751 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23752 APInt Mask = APInt::getAllOnesValue(InBits);
23753 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23754 return DAG.getNode(ISD::AND, DL, VT,
23755 Op, DAG.getConstant(Mask, DL, VT));
23757 case ISD::SIGN_EXTEND:
23758 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23759 Op, DAG.getValueType(NarrowVT));
23761 llvm_unreachable("Unexpected opcode");
23765 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
23766 TargetLowering::DAGCombinerInfo &DCI,
23767 const X86Subtarget *Subtarget) {
23768 SDValue N0 = N->getOperand(0);
23769 SDValue N1 = N->getOperand(1);
23772 // A vector zext_in_reg may be represented as a shuffle,
23773 // feeding into a bitcast (this represents anyext) feeding into
23774 // an and with a mask.
23775 // We'd like to try to combine that into a shuffle with zero
23776 // plus a bitcast, removing the and.
23777 if (N0.getOpcode() != ISD::BITCAST ||
23778 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23781 // The other side of the AND should be a splat of 2^C, where C
23782 // is the number of bits in the source type.
23783 if (N1.getOpcode() == ISD::BITCAST)
23784 N1 = N1.getOperand(0);
23785 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23787 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23789 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23790 EVT SrcType = Shuffle->getValueType(0);
23792 // We expect a single-source shuffle
23793 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23796 unsigned SrcSize = SrcType.getScalarSizeInBits();
23798 APInt SplatValue, SplatUndef;
23799 unsigned SplatBitSize;
23801 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23802 SplatBitSize, HasAnyUndefs))
23805 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23806 // Make sure the splat matches the mask we expect
23807 if (SplatBitSize > ResSize ||
23808 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23811 // Make sure the input and output size make sense
23812 if (SrcSize >= ResSize || ResSize % SrcSize)
23815 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23816 // The number of u's between each two values depends on the ratio between
23817 // the source and dest type.
23818 unsigned ZextRatio = ResSize / SrcSize;
23819 bool IsZext = true;
23820 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23821 if (i % ZextRatio) {
23822 if (Shuffle->getMaskElt(i) > 0) {
23828 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23829 // Expected element number
23839 // Ok, perform the transformation - replace the shuffle with
23840 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23841 // (instead of undef) where the k elements come from the zero vector.
23842 SmallVector<int, 8> Mask;
23843 unsigned NumElems = SrcType.getVectorNumElements();
23844 for (unsigned i = 0; i < NumElems; ++i)
23846 Mask.push_back(NumElems);
23848 Mask.push_back(i / ZextRatio);
23850 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23851 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23852 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23855 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23856 TargetLowering::DAGCombinerInfo &DCI,
23857 const X86Subtarget *Subtarget) {
23858 if (DCI.isBeforeLegalizeOps())
23861 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23864 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23867 EVT VT = N->getValueType(0);
23868 SDValue N0 = N->getOperand(0);
23869 SDValue N1 = N->getOperand(1);
23872 // Create BEXTR instructions
23873 // BEXTR is ((X >> imm) & (2**size-1))
23874 if (VT == MVT::i32 || VT == MVT::i64) {
23875 // Check for BEXTR.
23876 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23877 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23878 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23879 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23880 if (MaskNode && ShiftNode) {
23881 uint64_t Mask = MaskNode->getZExtValue();
23882 uint64_t Shift = ShiftNode->getZExtValue();
23883 if (isMask_64(Mask)) {
23884 uint64_t MaskSize = countPopulation(Mask);
23885 if (Shift + MaskSize <= VT.getSizeInBits())
23886 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23887 DAG.getConstant(Shift | (MaskSize << 8), DL,
23896 // Want to form ANDNP nodes:
23897 // 1) In the hopes of then easily combining them with OR and AND nodes
23898 // to form PBLEND/PSIGN.
23899 // 2) To match ANDN packed intrinsics
23900 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23903 // Check LHS for vnot
23904 if (N0.getOpcode() == ISD::XOR &&
23905 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23906 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23907 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23909 // Check RHS for vnot
23910 if (N1.getOpcode() == ISD::XOR &&
23911 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23912 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23913 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23918 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23919 TargetLowering::DAGCombinerInfo &DCI,
23920 const X86Subtarget *Subtarget) {
23921 if (DCI.isBeforeLegalizeOps())
23924 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23927 SDValue N0 = N->getOperand(0);
23928 SDValue N1 = N->getOperand(1);
23929 EVT VT = N->getValueType(0);
23931 // look for psign/blend
23932 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23933 if (!Subtarget->hasSSSE3() ||
23934 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23937 // Canonicalize pandn to RHS
23938 if (N0.getOpcode() == X86ISD::ANDNP)
23940 // or (and (m, y), (pandn m, x))
23941 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23942 SDValue Mask = N1.getOperand(0);
23943 SDValue X = N1.getOperand(1);
23945 if (N0.getOperand(0) == Mask)
23946 Y = N0.getOperand(1);
23947 if (N0.getOperand(1) == Mask)
23948 Y = N0.getOperand(0);
23950 // Check to see if the mask appeared in both the AND and ANDNP and
23954 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23955 // Look through mask bitcast.
23956 if (Mask.getOpcode() == ISD::BITCAST)
23957 Mask = Mask.getOperand(0);
23958 if (X.getOpcode() == ISD::BITCAST)
23959 X = X.getOperand(0);
23960 if (Y.getOpcode() == ISD::BITCAST)
23961 Y = Y.getOperand(0);
23963 EVT MaskVT = Mask.getValueType();
23965 // Validate that the Mask operand is a vector sra node.
23966 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23967 // there is no psrai.b
23968 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23969 unsigned SraAmt = ~0;
23970 if (Mask.getOpcode() == ISD::SRA) {
23971 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23972 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23973 SraAmt = AmtConst->getZExtValue();
23974 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23975 SDValue SraC = Mask.getOperand(1);
23976 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23978 if ((SraAmt + 1) != EltBits)
23983 // Now we know we at least have a plendvb with the mask val. See if
23984 // we can form a psignb/w/d.
23985 // psign = x.type == y.type == mask.type && y = sub(0, x);
23986 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23987 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23988 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23989 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23990 "Unsupported VT for PSIGN");
23991 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23992 return DAG.getBitcast(VT, Mask);
23994 // PBLENDVB only available on SSE 4.1
23995 if (!Subtarget->hasSSE41())
23998 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24000 X = DAG.getBitcast(BlendVT, X);
24001 Y = DAG.getBitcast(BlendVT, Y);
24002 Mask = DAG.getBitcast(BlendVT, Mask);
24003 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24004 return DAG.getBitcast(VT, Mask);
24008 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24011 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24012 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24014 // SHLD/SHRD instructions have lower register pressure, but on some
24015 // platforms they have higher latency than the equivalent
24016 // series of shifts/or that would otherwise be generated.
24017 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24018 // have higher latencies and we are not optimizing for size.
24019 if (!OptForSize && Subtarget->isSHLDSlow())
24022 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24024 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24026 if (!N0.hasOneUse() || !N1.hasOneUse())
24029 SDValue ShAmt0 = N0.getOperand(1);
24030 if (ShAmt0.getValueType() != MVT::i8)
24032 SDValue ShAmt1 = N1.getOperand(1);
24033 if (ShAmt1.getValueType() != MVT::i8)
24035 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24036 ShAmt0 = ShAmt0.getOperand(0);
24037 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24038 ShAmt1 = ShAmt1.getOperand(0);
24041 unsigned Opc = X86ISD::SHLD;
24042 SDValue Op0 = N0.getOperand(0);
24043 SDValue Op1 = N1.getOperand(0);
24044 if (ShAmt0.getOpcode() == ISD::SUB) {
24045 Opc = X86ISD::SHRD;
24046 std::swap(Op0, Op1);
24047 std::swap(ShAmt0, ShAmt1);
24050 unsigned Bits = VT.getSizeInBits();
24051 if (ShAmt1.getOpcode() == ISD::SUB) {
24052 SDValue Sum = ShAmt1.getOperand(0);
24053 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24054 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24055 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24056 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24057 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24058 return DAG.getNode(Opc, DL, VT,
24060 DAG.getNode(ISD::TRUNCATE, DL,
24063 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24064 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24066 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24067 return DAG.getNode(Opc, DL, VT,
24068 N0.getOperand(0), N1.getOperand(0),
24069 DAG.getNode(ISD::TRUNCATE, DL,
24076 // Generate NEG and CMOV for integer abs.
24077 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24078 EVT VT = N->getValueType(0);
24080 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24081 // 8-bit integer abs to NEG and CMOV.
24082 if (VT.isInteger() && VT.getSizeInBits() == 8)
24085 SDValue N0 = N->getOperand(0);
24086 SDValue N1 = N->getOperand(1);
24089 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24090 // and change it to SUB and CMOV.
24091 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24092 N0.getOpcode() == ISD::ADD &&
24093 N0.getOperand(1) == N1 &&
24094 N1.getOpcode() == ISD::SRA &&
24095 N1.getOperand(0) == N0.getOperand(0))
24096 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24097 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24098 // Generate SUB & CMOV.
24099 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24100 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24102 SDValue Ops[] = { N0.getOperand(0), Neg,
24103 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24104 SDValue(Neg.getNode(), 1) };
24105 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24110 // Try to turn tests against the signbit in the form of:
24111 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24114 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24115 // This is only worth doing if the output type is i8.
24116 if (N->getValueType(0) != MVT::i8)
24119 SDValue N0 = N->getOperand(0);
24120 SDValue N1 = N->getOperand(1);
24122 // We should be performing an xor against a truncated shift.
24123 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24126 // Make sure we are performing an xor against one.
24127 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24130 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24131 SDValue Shift = N0.getOperand(0);
24132 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24135 // Make sure we are truncating from one of i16, i32 or i64.
24136 EVT ShiftTy = Shift.getValueType();
24137 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24140 // Make sure the shift amount extracts the sign bit.
24141 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24142 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24145 // Create a greater-than comparison against -1.
24146 // N.B. Using SETGE against 0 works but we want a canonical looking
24147 // comparison, using SETGT matches up with what TranslateX86CC.
24149 SDValue ShiftOp = Shift.getOperand(0);
24150 EVT ShiftOpTy = ShiftOp.getValueType();
24151 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24152 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24156 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24157 TargetLowering::DAGCombinerInfo &DCI,
24158 const X86Subtarget *Subtarget) {
24159 if (DCI.isBeforeLegalizeOps())
24162 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24165 if (Subtarget->hasCMov())
24166 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24172 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24173 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24174 TargetLowering::DAGCombinerInfo &DCI,
24175 const X86Subtarget *Subtarget) {
24176 LoadSDNode *Ld = cast<LoadSDNode>(N);
24177 EVT RegVT = Ld->getValueType(0);
24178 EVT MemVT = Ld->getMemoryVT();
24180 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24182 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24183 // into two 16-byte operations.
24184 ISD::LoadExtType Ext = Ld->getExtensionType();
24186 unsigned AddressSpace = Ld->getAddressSpace();
24187 unsigned Alignment = Ld->getAlignment();
24188 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24189 Ext == ISD::NON_EXTLOAD &&
24190 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24191 AddressSpace, Alignment, &Fast) && !Fast) {
24192 unsigned NumElems = RegVT.getVectorNumElements();
24196 SDValue Ptr = Ld->getBasePtr();
24197 SDValue Increment =
24198 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24200 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24202 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24203 Ld->getPointerInfo(), Ld->isVolatile(),
24204 Ld->isNonTemporal(), Ld->isInvariant(),
24206 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24207 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24208 Ld->getPointerInfo(), Ld->isVolatile(),
24209 Ld->isNonTemporal(), Ld->isInvariant(),
24210 std::min(16U, Alignment));
24211 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24213 Load2.getValue(1));
24215 SDValue NewVec = DAG.getUNDEF(RegVT);
24216 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24217 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24218 return DCI.CombineTo(N, NewVec, TF, true);
24224 /// PerformMLOADCombine - Resolve extending loads
24225 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24226 TargetLowering::DAGCombinerInfo &DCI,
24227 const X86Subtarget *Subtarget) {
24228 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24229 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24232 EVT VT = Mld->getValueType(0);
24233 unsigned NumElems = VT.getVectorNumElements();
24234 EVT LdVT = Mld->getMemoryVT();
24237 assert(LdVT != VT && "Cannot extend to the same type");
24238 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24239 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24240 // From, To sizes and ElemCount must be pow of two
24241 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24242 "Unexpected size for extending masked load");
24244 unsigned SizeRatio = ToSz / FromSz;
24245 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24247 // Create a type on which we perform the shuffle
24248 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24249 LdVT.getScalarType(), NumElems*SizeRatio);
24250 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24252 // Convert Src0 value
24253 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24254 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24255 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24256 for (unsigned i = 0; i != NumElems; ++i)
24257 ShuffleVec[i] = i * SizeRatio;
24259 // Can't shuffle using an illegal type.
24260 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24261 && "WideVecVT should be legal");
24262 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24263 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24265 // Prepare the new mask
24267 SDValue Mask = Mld->getMask();
24268 if (Mask.getValueType() == VT) {
24269 // Mask and original value have the same type
24270 NewMask = DAG.getBitcast(WideVecVT, Mask);
24271 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24272 for (unsigned i = 0; i != NumElems; ++i)
24273 ShuffleVec[i] = i * SizeRatio;
24274 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24275 ShuffleVec[i] = NumElems*SizeRatio;
24276 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24277 DAG.getConstant(0, dl, WideVecVT),
24281 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24282 unsigned WidenNumElts = NumElems*SizeRatio;
24283 unsigned MaskNumElts = VT.getVectorNumElements();
24284 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24287 unsigned NumConcat = WidenNumElts / MaskNumElts;
24288 SmallVector<SDValue, 16> Ops(NumConcat);
24289 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24291 for (unsigned i = 1; i != NumConcat; ++i)
24294 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24297 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24298 Mld->getBasePtr(), NewMask, WideSrc0,
24299 Mld->getMemoryVT(), Mld->getMemOperand(),
24301 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24302 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24305 /// PerformMSTORECombine - Resolve truncating stores
24306 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24307 const X86Subtarget *Subtarget) {
24308 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24309 if (!Mst->isTruncatingStore())
24312 EVT VT = Mst->getValue().getValueType();
24313 unsigned NumElems = VT.getVectorNumElements();
24314 EVT StVT = Mst->getMemoryVT();
24317 assert(StVT != VT && "Cannot truncate to the same type");
24318 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24319 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24321 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24323 // The truncating store is legal in some cases. For example
24324 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24325 // are designated for truncate store.
24326 // In this case we don't need any further transformations.
24327 if (TLI.isTruncStoreLegal(VT, StVT))
24330 // From, To sizes and ElemCount must be pow of two
24331 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24332 "Unexpected size for truncating masked store");
24333 // We are going to use the original vector elt for storing.
24334 // Accumulated smaller vector elements must be a multiple of the store size.
24335 assert (((NumElems * FromSz) % ToSz) == 0 &&
24336 "Unexpected ratio for truncating masked store");
24338 unsigned SizeRatio = FromSz / ToSz;
24339 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24341 // Create a type on which we perform the shuffle
24342 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24343 StVT.getScalarType(), NumElems*SizeRatio);
24345 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24347 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
24348 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24349 for (unsigned i = 0; i != NumElems; ++i)
24350 ShuffleVec[i] = i * SizeRatio;
24352 // Can't shuffle using an illegal type.
24353 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
24354 && "WideVecVT should be legal");
24356 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24357 DAG.getUNDEF(WideVecVT),
24361 SDValue Mask = Mst->getMask();
24362 if (Mask.getValueType() == VT) {
24363 // Mask and original value have the same type
24364 NewMask = DAG.getBitcast(WideVecVT, Mask);
24365 for (unsigned i = 0; i != NumElems; ++i)
24366 ShuffleVec[i] = i * SizeRatio;
24367 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24368 ShuffleVec[i] = NumElems*SizeRatio;
24369 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24370 DAG.getConstant(0, dl, WideVecVT),
24374 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24375 unsigned WidenNumElts = NumElems*SizeRatio;
24376 unsigned MaskNumElts = VT.getVectorNumElements();
24377 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24380 unsigned NumConcat = WidenNumElts / MaskNumElts;
24381 SmallVector<SDValue, 16> Ops(NumConcat);
24382 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24384 for (unsigned i = 1; i != NumConcat; ++i)
24387 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24390 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
24391 NewMask, StVT, Mst->getMemOperand(), false);
24393 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24394 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24395 const X86Subtarget *Subtarget) {
24396 StoreSDNode *St = cast<StoreSDNode>(N);
24397 EVT VT = St->getValue().getValueType();
24398 EVT StVT = St->getMemoryVT();
24400 SDValue StoredVal = St->getOperand(1);
24401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24403 // If we are saving a concatenation of two XMM registers and 32-byte stores
24404 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24406 unsigned AddressSpace = St->getAddressSpace();
24407 unsigned Alignment = St->getAlignment();
24408 if (VT.is256BitVector() && StVT == VT &&
24409 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
24410 AddressSpace, Alignment, &Fast) && !Fast) {
24411 unsigned NumElems = VT.getVectorNumElements();
24415 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24416 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24419 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24420 SDValue Ptr0 = St->getBasePtr();
24421 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24423 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24424 St->getPointerInfo(), St->isVolatile(),
24425 St->isNonTemporal(), Alignment);
24426 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24427 St->getPointerInfo(), St->isVolatile(),
24428 St->isNonTemporal(),
24429 std::min(16U, Alignment));
24430 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24433 // Optimize trunc store (of multiple scalars) to shuffle and store.
24434 // First, pack all of the elements in one place. Next, store to memory
24435 // in fewer chunks.
24436 if (St->isTruncatingStore() && VT.isVector()) {
24437 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24438 unsigned NumElems = VT.getVectorNumElements();
24439 assert(StVT != VT && "Cannot truncate to the same type");
24440 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24441 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24443 // The truncating store is legal in some cases. For example
24444 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24445 // are designated for truncate store.
24446 // In this case we don't need any further transformations.
24447 if (TLI.isTruncStoreLegal(VT, StVT))
24450 // From, To sizes and ElemCount must be pow of two
24451 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24452 // We are going to use the original vector elt for storing.
24453 // Accumulated smaller vector elements must be a multiple of the store size.
24454 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24456 unsigned SizeRatio = FromSz / ToSz;
24458 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24460 // Create a type on which we perform the shuffle
24461 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24462 StVT.getScalarType(), NumElems*SizeRatio);
24464 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24466 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
24467 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24468 for (unsigned i = 0; i != NumElems; ++i)
24469 ShuffleVec[i] = i * SizeRatio;
24471 // Can't shuffle using an illegal type.
24472 if (!TLI.isTypeLegal(WideVecVT))
24475 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24476 DAG.getUNDEF(WideVecVT),
24478 // At this point all of the data is stored at the bottom of the
24479 // register. We now need to save it to mem.
24481 // Find the largest store unit
24482 MVT StoreType = MVT::i8;
24483 for (MVT Tp : MVT::integer_valuetypes()) {
24484 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24488 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24489 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24490 (64 <= NumElems * ToSz))
24491 StoreType = MVT::f64;
24493 // Bitcast the original vector into a vector of store-size units
24494 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24495 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24496 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24497 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
24498 SmallVector<SDValue, 8> Chains;
24499 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
24500 TLI.getPointerTy(DAG.getDataLayout()));
24501 SDValue Ptr = St->getBasePtr();
24503 // Perform one or more big stores into memory.
24504 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24505 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24506 StoreType, ShuffWide,
24507 DAG.getIntPtrConstant(i, dl));
24508 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24509 St->getPointerInfo(), St->isVolatile(),
24510 St->isNonTemporal(), St->getAlignment());
24511 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24512 Chains.push_back(Ch);
24515 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24518 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24519 // the FP state in cases where an emms may be missing.
24520 // A preferable solution to the general problem is to figure out the right
24521 // places to insert EMMS. This qualifies as a quick hack.
24523 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24524 if (VT.getSizeInBits() != 64)
24527 const Function *F = DAG.getMachineFunction().getFunction();
24528 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
24530 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
24531 if ((VT.isVector() ||
24532 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24533 isa<LoadSDNode>(St->getValue()) &&
24534 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24535 St->getChain().hasOneUse() && !St->isVolatile()) {
24536 SDNode* LdVal = St->getValue().getNode();
24537 LoadSDNode *Ld = nullptr;
24538 int TokenFactorIndex = -1;
24539 SmallVector<SDValue, 8> Ops;
24540 SDNode* ChainVal = St->getChain().getNode();
24541 // Must be a store of a load. We currently handle two cases: the load
24542 // is a direct child, and it's under an intervening TokenFactor. It is
24543 // possible to dig deeper under nested TokenFactors.
24544 if (ChainVal == LdVal)
24545 Ld = cast<LoadSDNode>(St->getChain());
24546 else if (St->getValue().hasOneUse() &&
24547 ChainVal->getOpcode() == ISD::TokenFactor) {
24548 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24549 if (ChainVal->getOperand(i).getNode() == LdVal) {
24550 TokenFactorIndex = i;
24551 Ld = cast<LoadSDNode>(St->getValue());
24553 Ops.push_back(ChainVal->getOperand(i));
24557 if (!Ld || !ISD::isNormalLoad(Ld))
24560 // If this is not the MMX case, i.e. we are just turning i64 load/store
24561 // into f64 load/store, avoid the transformation if there are multiple
24562 // uses of the loaded value.
24563 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24568 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24569 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24571 if (Subtarget->is64Bit() || F64IsLegal) {
24572 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24573 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24574 Ld->getPointerInfo(), Ld->isVolatile(),
24575 Ld->isNonTemporal(), Ld->isInvariant(),
24576 Ld->getAlignment());
24577 SDValue NewChain = NewLd.getValue(1);
24578 if (TokenFactorIndex != -1) {
24579 Ops.push_back(NewChain);
24580 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24582 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24583 St->getPointerInfo(),
24584 St->isVolatile(), St->isNonTemporal(),
24585 St->getAlignment());
24588 // Otherwise, lower to two pairs of 32-bit loads / stores.
24589 SDValue LoAddr = Ld->getBasePtr();
24590 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24591 DAG.getConstant(4, LdDL, MVT::i32));
24593 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24594 Ld->getPointerInfo(),
24595 Ld->isVolatile(), Ld->isNonTemporal(),
24596 Ld->isInvariant(), Ld->getAlignment());
24597 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24598 Ld->getPointerInfo().getWithOffset(4),
24599 Ld->isVolatile(), Ld->isNonTemporal(),
24601 MinAlign(Ld->getAlignment(), 4));
24603 SDValue NewChain = LoLd.getValue(1);
24604 if (TokenFactorIndex != -1) {
24605 Ops.push_back(LoLd);
24606 Ops.push_back(HiLd);
24607 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24610 LoAddr = St->getBasePtr();
24611 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24612 DAG.getConstant(4, StDL, MVT::i32));
24614 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24615 St->getPointerInfo(),
24616 St->isVolatile(), St->isNonTemporal(),
24617 St->getAlignment());
24618 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24619 St->getPointerInfo().getWithOffset(4),
24621 St->isNonTemporal(),
24622 MinAlign(St->getAlignment(), 4));
24623 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24626 // This is similar to the above case, but here we handle a scalar 64-bit
24627 // integer store that is extracted from a vector on a 32-bit target.
24628 // If we have SSE2, then we can treat it like a floating-point double
24629 // to get past legalization. The execution dependencies fixup pass will
24630 // choose the optimal machine instruction for the store if this really is
24631 // an integer or v2f32 rather than an f64.
24632 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
24633 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
24634 SDValue OldExtract = St->getOperand(1);
24635 SDValue ExtOp0 = OldExtract.getOperand(0);
24636 unsigned VecSize = ExtOp0.getValueSizeInBits();
24637 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
24638 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
24639 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
24640 BitCast, OldExtract.getOperand(1));
24641 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
24642 St->getPointerInfo(), St->isVolatile(),
24643 St->isNonTemporal(), St->getAlignment());
24649 /// Return 'true' if this vector operation is "horizontal"
24650 /// and return the operands for the horizontal operation in LHS and RHS. A
24651 /// horizontal operation performs the binary operation on successive elements
24652 /// of its first operand, then on successive elements of its second operand,
24653 /// returning the resulting values in a vector. For example, if
24654 /// A = < float a0, float a1, float a2, float a3 >
24656 /// B = < float b0, float b1, float b2, float b3 >
24657 /// then the result of doing a horizontal operation on A and B is
24658 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24659 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24660 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24661 /// set to A, RHS to B, and the routine returns 'true'.
24662 /// Note that the binary operation should have the property that if one of the
24663 /// operands is UNDEF then the result is UNDEF.
24664 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24665 // Look for the following pattern: if
24666 // A = < float a0, float a1, float a2, float a3 >
24667 // B = < float b0, float b1, float b2, float b3 >
24669 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24670 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24671 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24672 // which is A horizontal-op B.
24674 // At least one of the operands should be a vector shuffle.
24675 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24676 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24679 MVT VT = LHS.getSimpleValueType();
24681 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24682 "Unsupported vector type for horizontal add/sub");
24684 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24685 // operate independently on 128-bit lanes.
24686 unsigned NumElts = VT.getVectorNumElements();
24687 unsigned NumLanes = VT.getSizeInBits()/128;
24688 unsigned NumLaneElts = NumElts / NumLanes;
24689 assert((NumLaneElts % 2 == 0) &&
24690 "Vector type should have an even number of elements in each lane");
24691 unsigned HalfLaneElts = NumLaneElts/2;
24693 // View LHS in the form
24694 // LHS = VECTOR_SHUFFLE A, B, LMask
24695 // If LHS is not a shuffle then pretend it is the shuffle
24696 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24697 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24700 SmallVector<int, 16> LMask(NumElts);
24701 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24702 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24703 A = LHS.getOperand(0);
24704 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24705 B = LHS.getOperand(1);
24706 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24707 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24709 if (LHS.getOpcode() != ISD::UNDEF)
24711 for (unsigned i = 0; i != NumElts; ++i)
24715 // Likewise, view RHS in the form
24716 // RHS = VECTOR_SHUFFLE C, D, RMask
24718 SmallVector<int, 16> RMask(NumElts);
24719 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24720 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24721 C = RHS.getOperand(0);
24722 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24723 D = RHS.getOperand(1);
24724 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24725 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24727 if (RHS.getOpcode() != ISD::UNDEF)
24729 for (unsigned i = 0; i != NumElts; ++i)
24733 // Check that the shuffles are both shuffling the same vectors.
24734 if (!(A == C && B == D) && !(A == D && B == C))
24737 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24738 if (!A.getNode() && !B.getNode())
24741 // If A and B occur in reverse order in RHS, then "swap" them (which means
24742 // rewriting the mask).
24744 ShuffleVectorSDNode::commuteMask(RMask);
24746 // At this point LHS and RHS are equivalent to
24747 // LHS = VECTOR_SHUFFLE A, B, LMask
24748 // RHS = VECTOR_SHUFFLE A, B, RMask
24749 // Check that the masks correspond to performing a horizontal operation.
24750 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24751 for (unsigned i = 0; i != NumLaneElts; ++i) {
24752 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24754 // Ignore any UNDEF components.
24755 if (LIdx < 0 || RIdx < 0 ||
24756 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24757 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24760 // Check that successive elements are being operated on. If not, this is
24761 // not a horizontal operation.
24762 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24763 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24764 if (!(LIdx == Index && RIdx == Index + 1) &&
24765 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24770 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24771 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24775 /// Do target-specific dag combines on floating point adds.
24776 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24777 const X86Subtarget *Subtarget) {
24778 EVT VT = N->getValueType(0);
24779 SDValue LHS = N->getOperand(0);
24780 SDValue RHS = N->getOperand(1);
24782 // Try to synthesize horizontal adds from adds of shuffles.
24783 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24784 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24785 isHorizontalBinOp(LHS, RHS, true))
24786 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24790 /// Do target-specific dag combines on floating point subs.
24791 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24792 const X86Subtarget *Subtarget) {
24793 EVT VT = N->getValueType(0);
24794 SDValue LHS = N->getOperand(0);
24795 SDValue RHS = N->getOperand(1);
24797 // Try to synthesize horizontal subs from subs of shuffles.
24798 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24799 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24800 isHorizontalBinOp(LHS, RHS, false))
24801 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24805 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24806 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24807 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24809 // F[X]OR(0.0, x) -> x
24810 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24811 if (C->getValueAPF().isPosZero())
24812 return N->getOperand(1);
24814 // F[X]OR(x, 0.0) -> x
24815 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24816 if (C->getValueAPF().isPosZero())
24817 return N->getOperand(0);
24821 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24822 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24823 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24825 // Only perform optimizations if UnsafeMath is used.
24826 if (!DAG.getTarget().Options.UnsafeFPMath)
24829 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24830 // into FMINC and FMAXC, which are Commutative operations.
24831 unsigned NewOp = 0;
24832 switch (N->getOpcode()) {
24833 default: llvm_unreachable("unknown opcode");
24834 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24835 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24838 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24839 N->getOperand(0), N->getOperand(1));
24842 /// Do target-specific dag combines on X86ISD::FAND nodes.
24843 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24844 // FAND(0.0, x) -> 0.0
24845 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24846 if (C->getValueAPF().isPosZero())
24847 return N->getOperand(0);
24849 // FAND(x, 0.0) -> 0.0
24850 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24851 if (C->getValueAPF().isPosZero())
24852 return N->getOperand(1);
24857 /// Do target-specific dag combines on X86ISD::FANDN nodes
24858 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24859 // FANDN(0.0, x) -> x
24860 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24861 if (C->getValueAPF().isPosZero())
24862 return N->getOperand(1);
24864 // FANDN(x, 0.0) -> 0.0
24865 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24866 if (C->getValueAPF().isPosZero())
24867 return N->getOperand(1);
24872 static SDValue PerformBTCombine(SDNode *N,
24874 TargetLowering::DAGCombinerInfo &DCI) {
24875 // BT ignores high bits in the bit index operand.
24876 SDValue Op1 = N->getOperand(1);
24877 if (Op1.hasOneUse()) {
24878 unsigned BitWidth = Op1.getValueSizeInBits();
24879 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24880 APInt KnownZero, KnownOne;
24881 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24882 !DCI.isBeforeLegalizeOps());
24883 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24884 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24885 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24886 DCI.CommitTargetLoweringOpt(TLO);
24891 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24892 SDValue Op = N->getOperand(0);
24893 if (Op.getOpcode() == ISD::BITCAST)
24894 Op = Op.getOperand(0);
24895 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24896 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24897 VT.getVectorElementType().getSizeInBits() ==
24898 OpVT.getVectorElementType().getSizeInBits()) {
24899 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24904 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24905 const X86Subtarget *Subtarget) {
24906 EVT VT = N->getValueType(0);
24907 if (!VT.isVector())
24910 SDValue N0 = N->getOperand(0);
24911 SDValue N1 = N->getOperand(1);
24912 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24915 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24916 // both SSE and AVX2 since there is no sign-extended shift right
24917 // operation on a vector with 64-bit elements.
24918 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24919 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24920 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24921 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24922 SDValue N00 = N0.getOperand(0);
24924 // EXTLOAD has a better solution on AVX2,
24925 // it may be replaced with X86ISD::VSEXT node.
24926 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24927 if (!ISD::isNormalLoad(N00.getNode()))
24930 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24931 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24933 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24939 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24940 TargetLowering::DAGCombinerInfo &DCI,
24941 const X86Subtarget *Subtarget) {
24942 SDValue N0 = N->getOperand(0);
24943 EVT VT = N->getValueType(0);
24944 EVT SVT = VT.getScalarType();
24945 EVT InVT = N0.getValueType();
24946 EVT InSVT = InVT.getScalarType();
24949 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24950 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24951 // This exposes the sext to the sdivrem lowering, so that it directly extends
24952 // from AH (which we otherwise need to do contortions to access).
24953 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24954 InVT == MVT::i8 && VT == MVT::i32) {
24955 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24956 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24957 N0.getOperand(0), N0.getOperand(1));
24958 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24959 return R.getValue(1);
24962 if (!DCI.isBeforeLegalizeOps()) {
24963 if (InVT == MVT::i1) {
24964 SDValue Zero = DAG.getConstant(0, DL, VT);
24966 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24967 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24972 if (VT.isVector() && Subtarget->hasSSE2()) {
24973 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
24974 EVT InVT = N.getValueType();
24975 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24976 Size / InVT.getScalarSizeInBits());
24977 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
24978 DAG.getUNDEF(InVT));
24980 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24983 // If target-size is less than 128-bits, extend to a type that would extend
24984 // to 128 bits, extend that and extract the original target vector.
24985 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
24986 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24987 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24988 unsigned Scale = 128 / VT.getSizeInBits();
24990 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
24991 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
24992 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
24993 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
24994 DAG.getIntPtrConstant(0, DL));
24997 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24998 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24999 if (VT.getSizeInBits() == 128 &&
25000 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25001 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25002 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25003 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25006 // On pre-AVX2 targets, split into 128-bit nodes of
25007 // ISD::SIGN_EXTEND_VECTOR_INREG.
25008 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25009 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25010 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25011 unsigned NumVecs = VT.getSizeInBits() / 128;
25012 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25013 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25014 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25016 SmallVector<SDValue, 8> Opnds;
25017 for (unsigned i = 0, Offset = 0; i != NumVecs;
25018 ++i, Offset += NumSubElts) {
25019 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25020 DAG.getIntPtrConstant(Offset, DL));
25021 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25022 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25023 Opnds.push_back(SrcVec);
25025 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25029 if (!Subtarget->hasFp256())
25032 if (VT.isVector() && VT.getSizeInBits() == 256)
25033 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25039 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25040 const X86Subtarget* Subtarget) {
25042 EVT VT = N->getValueType(0);
25044 // Let legalize expand this if it isn't a legal type yet.
25045 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25048 EVT ScalarVT = VT.getScalarType();
25049 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25050 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25051 !Subtarget->hasAVX512()))
25054 SDValue A = N->getOperand(0);
25055 SDValue B = N->getOperand(1);
25056 SDValue C = N->getOperand(2);
25058 bool NegA = (A.getOpcode() == ISD::FNEG);
25059 bool NegB = (B.getOpcode() == ISD::FNEG);
25060 bool NegC = (C.getOpcode() == ISD::FNEG);
25062 // Negative multiplication when NegA xor NegB
25063 bool NegMul = (NegA != NegB);
25065 A = A.getOperand(0);
25067 B = B.getOperand(0);
25069 C = C.getOperand(0);
25073 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25075 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25077 return DAG.getNode(Opcode, dl, VT, A, B, C);
25080 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25081 TargetLowering::DAGCombinerInfo &DCI,
25082 const X86Subtarget *Subtarget) {
25083 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25084 // (and (i32 x86isd::setcc_carry), 1)
25085 // This eliminates the zext. This transformation is necessary because
25086 // ISD::SETCC is always legalized to i8.
25088 SDValue N0 = N->getOperand(0);
25089 EVT VT = N->getValueType(0);
25091 if (N0.getOpcode() == ISD::AND &&
25093 N0.getOperand(0).hasOneUse()) {
25094 SDValue N00 = N0.getOperand(0);
25095 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25096 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25097 if (!C || C->getZExtValue() != 1)
25099 return DAG.getNode(ISD::AND, dl, VT,
25100 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25101 N00.getOperand(0), N00.getOperand(1)),
25102 DAG.getConstant(1, dl, VT));
25106 if (N0.getOpcode() == ISD::TRUNCATE &&
25108 N0.getOperand(0).hasOneUse()) {
25109 SDValue N00 = N0.getOperand(0);
25110 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25111 return DAG.getNode(ISD::AND, dl, VT,
25112 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25113 N00.getOperand(0), N00.getOperand(1)),
25114 DAG.getConstant(1, dl, VT));
25118 if (VT.is256BitVector())
25119 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25122 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25123 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25124 // This exposes the zext to the udivrem lowering, so that it directly extends
25125 // from AH (which we otherwise need to do contortions to access).
25126 if (N0.getOpcode() == ISD::UDIVREM &&
25127 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25128 (VT == MVT::i32 || VT == MVT::i64)) {
25129 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25130 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25131 N0.getOperand(0), N0.getOperand(1));
25132 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25133 return R.getValue(1);
25139 // Optimize x == -y --> x+y == 0
25140 // x != -y --> x+y != 0
25141 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25142 const X86Subtarget* Subtarget) {
25143 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25144 SDValue LHS = N->getOperand(0);
25145 SDValue RHS = N->getOperand(1);
25146 EVT VT = N->getValueType(0);
25149 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25151 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25152 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25153 LHS.getOperand(1));
25154 return DAG.getSetCC(DL, N->getValueType(0), addV,
25155 DAG.getConstant(0, DL, addV.getValueType()), CC);
25157 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25158 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25159 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25160 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25161 RHS.getOperand(1));
25162 return DAG.getSetCC(DL, N->getValueType(0), addV,
25163 DAG.getConstant(0, DL, addV.getValueType()), CC);
25166 if (VT.getScalarType() == MVT::i1 &&
25167 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25169 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25170 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25171 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25173 if (!IsSEXT0 || !IsVZero1) {
25174 // Swap the operands and update the condition code.
25175 std::swap(LHS, RHS);
25176 CC = ISD::getSetCCSwappedOperands(CC);
25178 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25179 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25180 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25183 if (IsSEXT0 && IsVZero1) {
25184 assert(VT == LHS.getOperand(0).getValueType() &&
25185 "Uexpected operand type");
25186 if (CC == ISD::SETGT)
25187 return DAG.getConstant(0, DL, VT);
25188 if (CC == ISD::SETLE)
25189 return DAG.getConstant(1, DL, VT);
25190 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25191 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25193 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25194 "Unexpected condition code!");
25195 return LHS.getOperand(0);
25202 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25203 SelectionDAG &DAG) {
25205 MVT VT = Load->getSimpleValueType(0);
25206 MVT EVT = VT.getVectorElementType();
25207 SDValue Addr = Load->getOperand(1);
25208 SDValue NewAddr = DAG.getNode(
25209 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25210 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25211 Addr.getSimpleValueType()));
25214 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25215 DAG.getMachineFunction().getMachineMemOperand(
25216 Load->getMemOperand(), 0, EVT.getStoreSize()));
25220 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25221 const X86Subtarget *Subtarget) {
25223 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25224 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25225 "X86insertps is only defined for v4x32");
25227 SDValue Ld = N->getOperand(1);
25228 if (MayFoldLoad(Ld)) {
25229 // Extract the countS bits from the immediate so we can get the proper
25230 // address when narrowing the vector load to a specific element.
25231 // When the second source op is a memory address, insertps doesn't use
25232 // countS and just gets an f32 from that address.
25233 unsigned DestIndex =
25234 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25236 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25238 // Create this as a scalar to vector to match the instruction pattern.
25239 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25240 // countS bits are ignored when loading from memory on insertps, which
25241 // means we don't need to explicitly set them to 0.
25242 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25243 LoadScalarToVector, N->getOperand(2));
25248 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25249 SDValue V0 = N->getOperand(0);
25250 SDValue V1 = N->getOperand(1);
25252 EVT VT = N->getValueType(0);
25254 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25255 // operands and changing the mask to 1. This saves us a bunch of
25256 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25257 // x86InstrInfo knows how to commute this back after instruction selection
25258 // if it would help register allocation.
25260 // TODO: If optimizing for size or a processor that doesn't suffer from
25261 // partial register update stalls, this should be transformed into a MOVSD
25262 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25264 if (VT == MVT::v2f64)
25265 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25266 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25267 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25268 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25274 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25275 // as "sbb reg,reg", since it can be extended without zext and produces
25276 // an all-ones bit which is more useful than 0/1 in some cases.
25277 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25280 return DAG.getNode(ISD::AND, DL, VT,
25281 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25282 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25284 DAG.getConstant(1, DL, VT));
25285 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25286 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25287 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25288 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25292 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25293 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25294 TargetLowering::DAGCombinerInfo &DCI,
25295 const X86Subtarget *Subtarget) {
25297 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25298 SDValue EFLAGS = N->getOperand(1);
25300 if (CC == X86::COND_A) {
25301 // Try to convert COND_A into COND_B in an attempt to facilitate
25302 // materializing "setb reg".
25304 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25305 // cannot take an immediate as its first operand.
25307 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25308 EFLAGS.getValueType().isInteger() &&
25309 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25310 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25311 EFLAGS.getNode()->getVTList(),
25312 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25313 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25314 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25318 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25319 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25321 if (CC == X86::COND_B)
25322 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25324 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25325 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25326 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25332 // Optimize branch condition evaluation.
25334 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25335 TargetLowering::DAGCombinerInfo &DCI,
25336 const X86Subtarget *Subtarget) {
25338 SDValue Chain = N->getOperand(0);
25339 SDValue Dest = N->getOperand(1);
25340 SDValue EFLAGS = N->getOperand(3);
25341 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25343 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25344 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25345 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25352 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25353 SelectionDAG &DAG) {
25354 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25355 // optimize away operation when it's from a constant.
25357 // The general transformation is:
25358 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25359 // AND(VECTOR_CMP(x,y), constant2)
25360 // constant2 = UNARYOP(constant)
25362 // Early exit if this isn't a vector operation, the operand of the
25363 // unary operation isn't a bitwise AND, or if the sizes of the operations
25364 // aren't the same.
25365 EVT VT = N->getValueType(0);
25366 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25367 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25368 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25371 // Now check that the other operand of the AND is a constant. We could
25372 // make the transformation for non-constant splats as well, but it's unclear
25373 // that would be a benefit as it would not eliminate any operations, just
25374 // perform one more step in scalar code before moving to the vector unit.
25375 if (BuildVectorSDNode *BV =
25376 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25377 // Bail out if the vector isn't a constant.
25378 if (!BV->isConstant())
25381 // Everything checks out. Build up the new and improved node.
25383 EVT IntVT = BV->getValueType(0);
25384 // Create a new constant of the appropriate type for the transformed
25386 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25387 // The AND node needs bitcasts to/from an integer vector type around it.
25388 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
25389 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25390 N->getOperand(0)->getOperand(0), MaskConst);
25391 SDValue Res = DAG.getBitcast(VT, NewAnd);
25398 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25399 const X86Subtarget *Subtarget) {
25400 SDValue Op0 = N->getOperand(0);
25401 EVT VT = N->getValueType(0);
25402 EVT InVT = Op0.getValueType();
25403 EVT InSVT = InVT.getScalarType();
25404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25406 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
25407 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
25408 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25410 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25411 InVT.getVectorNumElements());
25412 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
25414 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
25415 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
25417 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25423 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25424 const X86Subtarget *Subtarget) {
25425 // First try to optimize away the conversion entirely when it's
25426 // conditionally from a constant. Vectors only.
25427 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
25430 // Now move on to more general possibilities.
25431 SDValue Op0 = N->getOperand(0);
25432 EVT VT = N->getValueType(0);
25433 EVT InVT = Op0.getValueType();
25434 EVT InSVT = InVT.getScalarType();
25436 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
25437 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
25438 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25440 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25441 InVT.getVectorNumElements());
25442 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25443 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25446 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25447 // a 32-bit target where SSE doesn't support i64->FP operations.
25448 if (Op0.getOpcode() == ISD::LOAD) {
25449 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25450 EVT LdVT = Ld->getValueType(0);
25452 // This transformation is not supported if the result type is f16
25453 if (VT == MVT::f16)
25456 if (!Ld->isVolatile() && !VT.isVector() &&
25457 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25458 !Subtarget->is64Bit() && LdVT == MVT::i64) {
25459 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
25460 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
25461 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25468 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25469 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25470 X86TargetLowering::DAGCombinerInfo &DCI) {
25471 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25472 // the result is either zero or one (depending on the input carry bit).
25473 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25474 if (X86::isZeroNode(N->getOperand(0)) &&
25475 X86::isZeroNode(N->getOperand(1)) &&
25476 // We don't have a good way to replace an EFLAGS use, so only do this when
25478 SDValue(N, 1).use_empty()) {
25480 EVT VT = N->getValueType(0);
25481 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
25482 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25483 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25484 DAG.getConstant(X86::COND_B, DL,
25487 DAG.getConstant(1, DL, VT));
25488 return DCI.CombineTo(N, Res1, CarryOut);
25494 // fold (add Y, (sete X, 0)) -> adc 0, Y
25495 // (add Y, (setne X, 0)) -> sbb -1, Y
25496 // (sub (sete X, 0), Y) -> sbb 0, Y
25497 // (sub (setne X, 0), Y) -> adc -1, Y
25498 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25501 // Look through ZExts.
25502 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25503 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25506 SDValue SetCC = Ext.getOperand(0);
25507 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25510 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25511 if (CC != X86::COND_E && CC != X86::COND_NE)
25514 SDValue Cmp = SetCC.getOperand(1);
25515 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25516 !X86::isZeroNode(Cmp.getOperand(1)) ||
25517 !Cmp.getOperand(0).getValueType().isInteger())
25520 SDValue CmpOp0 = Cmp.getOperand(0);
25521 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25522 DAG.getConstant(1, DL, CmpOp0.getValueType()));
25524 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25525 if (CC == X86::COND_NE)
25526 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25527 DL, OtherVal.getValueType(), OtherVal,
25528 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
25530 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25531 DL, OtherVal.getValueType(), OtherVal,
25532 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
25535 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25536 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25537 const X86Subtarget *Subtarget) {
25538 EVT VT = N->getValueType(0);
25539 SDValue Op0 = N->getOperand(0);
25540 SDValue Op1 = N->getOperand(1);
25542 // Try to synthesize horizontal adds from adds of shuffles.
25543 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25544 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25545 isHorizontalBinOp(Op0, Op1, true))
25546 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25548 return OptimizeConditionalInDecrement(N, DAG);
25551 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25552 const X86Subtarget *Subtarget) {
25553 SDValue Op0 = N->getOperand(0);
25554 SDValue Op1 = N->getOperand(1);
25556 // X86 can't encode an immediate LHS of a sub. See if we can push the
25557 // negation into a preceding instruction.
25558 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25559 // If the RHS of the sub is a XOR with one use and a constant, invert the
25560 // immediate. Then add one to the LHS of the sub so we can turn
25561 // X-Y -> X+~Y+1, saving one register.
25562 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25563 isa<ConstantSDNode>(Op1.getOperand(1))) {
25564 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25565 EVT VT = Op0.getValueType();
25566 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25568 DAG.getConstant(~XorC, SDLoc(Op1), VT));
25569 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25570 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
25574 // Try to synthesize horizontal adds from adds of shuffles.
25575 EVT VT = N->getValueType(0);
25576 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25577 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25578 isHorizontalBinOp(Op0, Op1, true))
25579 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25581 return OptimizeConditionalInDecrement(N, DAG);
25584 /// performVZEXTCombine - Performs build vector combines
25585 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25586 TargetLowering::DAGCombinerInfo &DCI,
25587 const X86Subtarget *Subtarget) {
25589 MVT VT = N->getSimpleValueType(0);
25590 SDValue Op = N->getOperand(0);
25591 MVT OpVT = Op.getSimpleValueType();
25592 MVT OpEltVT = OpVT.getVectorElementType();
25593 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25595 // (vzext (bitcast (vzext (x)) -> (vzext x)
25597 while (V.getOpcode() == ISD::BITCAST)
25598 V = V.getOperand(0);
25600 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25601 MVT InnerVT = V.getSimpleValueType();
25602 MVT InnerEltVT = InnerVT.getVectorElementType();
25604 // If the element sizes match exactly, we can just do one larger vzext. This
25605 // is always an exact type match as vzext operates on integer types.
25606 if (OpEltVT == InnerEltVT) {
25607 assert(OpVT == InnerVT && "Types must match for vzext!");
25608 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25611 // The only other way we can combine them is if only a single element of the
25612 // inner vzext is used in the input to the outer vzext.
25613 if (InnerEltVT.getSizeInBits() < InputBits)
25616 // In this case, the inner vzext is completely dead because we're going to
25617 // only look at bits inside of the low element. Just do the outer vzext on
25618 // a bitcast of the input to the inner.
25619 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
25622 // Check if we can bypass extracting and re-inserting an element of an input
25623 // vector. Essentially:
25624 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25625 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25626 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25627 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25628 SDValue ExtractedV = V.getOperand(0);
25629 SDValue OrigV = ExtractedV.getOperand(0);
25630 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25631 if (ExtractIdx->getZExtValue() == 0) {
25632 MVT OrigVT = OrigV.getSimpleValueType();
25633 // Extract a subvector if necessary...
25634 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25635 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25636 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25637 OrigVT.getVectorNumElements() / Ratio);
25638 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25639 DAG.getIntPtrConstant(0, DL));
25641 Op = DAG.getBitcast(OpVT, OrigV);
25642 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25649 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25650 DAGCombinerInfo &DCI) const {
25651 SelectionDAG &DAG = DCI.DAG;
25652 switch (N->getOpcode()) {
25654 case ISD::EXTRACT_VECTOR_ELT:
25655 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25658 case X86ISD::SHRUNKBLEND:
25659 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25660 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
25661 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25662 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25663 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25664 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25665 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25668 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25669 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25670 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25671 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25672 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25673 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
25674 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25675 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
25676 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
25677 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
25678 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25679 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25681 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25683 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25684 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25685 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25686 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25687 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25688 case ISD::ANY_EXTEND:
25689 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25690 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25691 case ISD::SIGN_EXTEND_INREG:
25692 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25693 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25694 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25695 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25696 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25697 case X86ISD::SHUFP: // Handle all target specific shuffles
25698 case X86ISD::PALIGNR:
25699 case X86ISD::UNPCKH:
25700 case X86ISD::UNPCKL:
25701 case X86ISD::MOVHLPS:
25702 case X86ISD::MOVLHPS:
25703 case X86ISD::PSHUFB:
25704 case X86ISD::PSHUFD:
25705 case X86ISD::PSHUFHW:
25706 case X86ISD::PSHUFLW:
25707 case X86ISD::MOVSS:
25708 case X86ISD::MOVSD:
25709 case X86ISD::VPERMILPI:
25710 case X86ISD::VPERM2X128:
25711 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25712 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25713 case X86ISD::INSERTPS: {
25714 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
25715 return PerformINSERTPSCombine(N, DAG, Subtarget);
25718 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
25724 /// isTypeDesirableForOp - Return true if the target has native support for
25725 /// the specified value type and it is 'desirable' to use the type for the
25726 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25727 /// instruction encodings are longer and some i16 instructions are slow.
25728 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25729 if (!isTypeLegal(VT))
25731 if (VT != MVT::i16)
25738 case ISD::SIGN_EXTEND:
25739 case ISD::ZERO_EXTEND:
25740 case ISD::ANY_EXTEND:
25753 /// IsDesirableToPromoteOp - This method query the target whether it is
25754 /// beneficial for dag combiner to promote the specified node. If true, it
25755 /// should return the desired promotion type by reference.
25756 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25757 EVT VT = Op.getValueType();
25758 if (VT != MVT::i16)
25761 bool Promote = false;
25762 bool Commute = false;
25763 switch (Op.getOpcode()) {
25766 LoadSDNode *LD = cast<LoadSDNode>(Op);
25767 // If the non-extending load has a single use and it's not live out, then it
25768 // might be folded.
25769 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25770 Op.hasOneUse()*/) {
25771 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25772 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25773 // The only case where we'd want to promote LOAD (rather then it being
25774 // promoted as an operand is when it's only use is liveout.
25775 if (UI->getOpcode() != ISD::CopyToReg)
25782 case ISD::SIGN_EXTEND:
25783 case ISD::ZERO_EXTEND:
25784 case ISD::ANY_EXTEND:
25789 SDValue N0 = Op.getOperand(0);
25790 // Look out for (store (shl (load), x)).
25791 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25804 SDValue N0 = Op.getOperand(0);
25805 SDValue N1 = Op.getOperand(1);
25806 if (!Commute && MayFoldLoad(N1))
25808 // Avoid disabling potential load folding opportunities.
25809 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25811 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25821 //===----------------------------------------------------------------------===//
25822 // X86 Inline Assembly Support
25823 //===----------------------------------------------------------------------===//
25825 // Helper to match a string separated by whitespace.
25826 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
25827 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
25829 for (StringRef Piece : Pieces) {
25830 if (!S.startswith(Piece)) // Check if the piece matches.
25833 S = S.substr(Piece.size());
25834 StringRef::size_type Pos = S.find_first_not_of(" \t");
25835 if (Pos == 0) // We matched a prefix.
25844 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25846 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25847 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25848 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25849 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25851 if (AsmPieces.size() == 3)
25853 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25860 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25861 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25863 std::string AsmStr = IA->getAsmString();
25865 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25866 if (!Ty || Ty->getBitWidth() % 16 != 0)
25869 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25870 SmallVector<StringRef, 4> AsmPieces;
25871 SplitString(AsmStr, AsmPieces, ";\n");
25873 switch (AsmPieces.size()) {
25874 default: return false;
25876 // FIXME: this should verify that we are targeting a 486 or better. If not,
25877 // we will turn this bswap into something that will be lowered to logical
25878 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25879 // lower so don't worry about this.
25881 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
25882 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
25883 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
25884 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
25885 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
25886 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
25887 // No need to check constraints, nothing other than the equivalent of
25888 // "=r,0" would be valid here.
25889 return IntrinsicLowering::LowerToByteSwap(CI);
25892 // rorw $$8, ${0:w} --> llvm.bswap.i16
25893 if (CI->getType()->isIntegerTy(16) &&
25894 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25895 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25896 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25898 StringRef ConstraintsStr = IA->getConstraintString();
25899 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25900 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25901 if (clobbersFlagRegisters(AsmPieces))
25902 return IntrinsicLowering::LowerToByteSwap(CI);
25906 if (CI->getType()->isIntegerTy(32) &&
25907 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25908 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25909 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25910 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25912 StringRef ConstraintsStr = IA->getConstraintString();
25913 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25914 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25915 if (clobbersFlagRegisters(AsmPieces))
25916 return IntrinsicLowering::LowerToByteSwap(CI);
25919 if (CI->getType()->isIntegerTy(64)) {
25920 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25921 if (Constraints.size() >= 2 &&
25922 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25923 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25924 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25925 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25926 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25927 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25928 return IntrinsicLowering::LowerToByteSwap(CI);
25936 /// getConstraintType - Given a constraint letter, return the type of
25937 /// constraint it is for this target.
25938 X86TargetLowering::ConstraintType
25939 X86TargetLowering::getConstraintType(StringRef Constraint) const {
25940 if (Constraint.size() == 1) {
25941 switch (Constraint[0]) {
25952 return C_RegisterClass;
25976 return TargetLowering::getConstraintType(Constraint);
25979 /// Examine constraint type and operand type and determine a weight value.
25980 /// This object must already have been set up with the operand type
25981 /// and the current alternative constraint selected.
25982 TargetLowering::ConstraintWeight
25983 X86TargetLowering::getSingleConstraintMatchWeight(
25984 AsmOperandInfo &info, const char *constraint) const {
25985 ConstraintWeight weight = CW_Invalid;
25986 Value *CallOperandVal = info.CallOperandVal;
25987 // If we don't have a value, we can't do a match,
25988 // but allow it at the lowest weight.
25989 if (!CallOperandVal)
25991 Type *type = CallOperandVal->getType();
25992 // Look at the constraint type.
25993 switch (*constraint) {
25995 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26006 if (CallOperandVal->getType()->isIntegerTy())
26007 weight = CW_SpecificReg;
26012 if (type->isFloatingPointTy())
26013 weight = CW_SpecificReg;
26016 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26017 weight = CW_SpecificReg;
26021 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26022 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26023 weight = CW_Register;
26026 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26027 if (C->getZExtValue() <= 31)
26028 weight = CW_Constant;
26032 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26033 if (C->getZExtValue() <= 63)
26034 weight = CW_Constant;
26038 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26039 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26040 weight = CW_Constant;
26044 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26045 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26046 weight = CW_Constant;
26050 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26051 if (C->getZExtValue() <= 3)
26052 weight = CW_Constant;
26056 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26057 if (C->getZExtValue() <= 0xff)
26058 weight = CW_Constant;
26063 if (isa<ConstantFP>(CallOperandVal)) {
26064 weight = CW_Constant;
26068 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26069 if ((C->getSExtValue() >= -0x80000000LL) &&
26070 (C->getSExtValue() <= 0x7fffffffLL))
26071 weight = CW_Constant;
26075 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26076 if (C->getZExtValue() <= 0xffffffff)
26077 weight = CW_Constant;
26084 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26085 /// with another that has more specific requirements based on the type of the
26086 /// corresponding operand.
26087 const char *X86TargetLowering::
26088 LowerXConstraint(EVT ConstraintVT) const {
26089 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26090 // 'f' like normal targets.
26091 if (ConstraintVT.isFloatingPoint()) {
26092 if (Subtarget->hasSSE2())
26094 if (Subtarget->hasSSE1())
26098 return TargetLowering::LowerXConstraint(ConstraintVT);
26101 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26102 /// vector. If it is invalid, don't add anything to Ops.
26103 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26104 std::string &Constraint,
26105 std::vector<SDValue>&Ops,
26106 SelectionDAG &DAG) const {
26109 // Only support length 1 constraints for now.
26110 if (Constraint.length() > 1) return;
26112 char ConstraintLetter = Constraint[0];
26113 switch (ConstraintLetter) {
26116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26117 if (C->getZExtValue() <= 31) {
26118 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26119 Op.getValueType());
26125 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26126 if (C->getZExtValue() <= 63) {
26127 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26128 Op.getValueType());
26134 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26135 if (isInt<8>(C->getSExtValue())) {
26136 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26137 Op.getValueType());
26143 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26144 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26145 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26146 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26147 Op.getValueType());
26153 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26154 if (C->getZExtValue() <= 3) {
26155 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26156 Op.getValueType());
26162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26163 if (C->getZExtValue() <= 255) {
26164 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26165 Op.getValueType());
26171 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26172 if (C->getZExtValue() <= 127) {
26173 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26174 Op.getValueType());
26180 // 32-bit signed value
26181 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26182 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26183 C->getSExtValue())) {
26184 // Widen to 64 bits here to get it sign extended.
26185 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26188 // FIXME gcc accepts some relocatable values here too, but only in certain
26189 // memory models; it's complicated.
26194 // 32-bit unsigned value
26195 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26196 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26197 C->getZExtValue())) {
26198 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26199 Op.getValueType());
26203 // FIXME gcc accepts some relocatable values here too, but only in certain
26204 // memory models; it's complicated.
26208 // Literal immediates are always ok.
26209 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26210 // Widen to 64 bits here to get it sign extended.
26211 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26215 // In any sort of PIC mode addresses need to be computed at runtime by
26216 // adding in a register or some sort of table lookup. These can't
26217 // be used as immediates.
26218 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26221 // If we are in non-pic codegen mode, we allow the address of a global (with
26222 // an optional displacement) to be used with 'i'.
26223 GlobalAddressSDNode *GA = nullptr;
26224 int64_t Offset = 0;
26226 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26228 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26229 Offset += GA->getOffset();
26231 } else if (Op.getOpcode() == ISD::ADD) {
26232 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26233 Offset += C->getZExtValue();
26234 Op = Op.getOperand(0);
26237 } else if (Op.getOpcode() == ISD::SUB) {
26238 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26239 Offset += -C->getZExtValue();
26240 Op = Op.getOperand(0);
26245 // Otherwise, this isn't something we can handle, reject it.
26249 const GlobalValue *GV = GA->getGlobal();
26250 // If we require an extra load to get this address, as in PIC mode, we
26251 // can't accept it.
26252 if (isGlobalStubReference(
26253 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26256 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26257 GA->getValueType(0), Offset);
26262 if (Result.getNode()) {
26263 Ops.push_back(Result);
26266 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26269 std::pair<unsigned, const TargetRegisterClass *>
26270 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26271 StringRef Constraint,
26273 // First, see if this is a constraint that directly corresponds to an LLVM
26275 if (Constraint.size() == 1) {
26276 // GCC Constraint Letters
26277 switch (Constraint[0]) {
26279 // TODO: Slight differences here in allocation order and leaving
26280 // RIP in the class. Do they matter any more here than they do
26281 // in the normal allocation?
26282 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26283 if (Subtarget->is64Bit()) {
26284 if (VT == MVT::i32 || VT == MVT::f32)
26285 return std::make_pair(0U, &X86::GR32RegClass);
26286 if (VT == MVT::i16)
26287 return std::make_pair(0U, &X86::GR16RegClass);
26288 if (VT == MVT::i8 || VT == MVT::i1)
26289 return std::make_pair(0U, &X86::GR8RegClass);
26290 if (VT == MVT::i64 || VT == MVT::f64)
26291 return std::make_pair(0U, &X86::GR64RegClass);
26294 // 32-bit fallthrough
26295 case 'Q': // Q_REGS
26296 if (VT == MVT::i32 || VT == MVT::f32)
26297 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26298 if (VT == MVT::i16)
26299 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26300 if (VT == MVT::i8 || VT == MVT::i1)
26301 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26302 if (VT == MVT::i64)
26303 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26305 case 'r': // GENERAL_REGS
26306 case 'l': // INDEX_REGS
26307 if (VT == MVT::i8 || VT == MVT::i1)
26308 return std::make_pair(0U, &X86::GR8RegClass);
26309 if (VT == MVT::i16)
26310 return std::make_pair(0U, &X86::GR16RegClass);
26311 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26312 return std::make_pair(0U, &X86::GR32RegClass);
26313 return std::make_pair(0U, &X86::GR64RegClass);
26314 case 'R': // LEGACY_REGS
26315 if (VT == MVT::i8 || VT == MVT::i1)
26316 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26317 if (VT == MVT::i16)
26318 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26319 if (VT == MVT::i32 || !Subtarget->is64Bit())
26320 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26321 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26322 case 'f': // FP Stack registers.
26323 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26324 // value to the correct fpstack register class.
26325 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26326 return std::make_pair(0U, &X86::RFP32RegClass);
26327 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26328 return std::make_pair(0U, &X86::RFP64RegClass);
26329 return std::make_pair(0U, &X86::RFP80RegClass);
26330 case 'y': // MMX_REGS if MMX allowed.
26331 if (!Subtarget->hasMMX()) break;
26332 return std::make_pair(0U, &X86::VR64RegClass);
26333 case 'Y': // SSE_REGS if SSE2 allowed
26334 if (!Subtarget->hasSSE2()) break;
26336 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26337 if (!Subtarget->hasSSE1()) break;
26339 switch (VT.SimpleTy) {
26341 // Scalar SSE types.
26344 return std::make_pair(0U, &X86::FR32RegClass);
26347 return std::make_pair(0U, &X86::FR64RegClass);
26355 return std::make_pair(0U, &X86::VR128RegClass);
26363 return std::make_pair(0U, &X86::VR256RegClass);
26368 return std::make_pair(0U, &X86::VR512RegClass);
26374 // Use the default implementation in TargetLowering to convert the register
26375 // constraint into a member of a register class.
26376 std::pair<unsigned, const TargetRegisterClass*> Res;
26377 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
26379 // Not found as a standard register?
26381 // Map st(0) -> st(7) -> ST0
26382 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26383 tolower(Constraint[1]) == 's' &&
26384 tolower(Constraint[2]) == 't' &&
26385 Constraint[3] == '(' &&
26386 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26387 Constraint[5] == ')' &&
26388 Constraint[6] == '}') {
26390 Res.first = X86::FP0+Constraint[4]-'0';
26391 Res.second = &X86::RFP80RegClass;
26395 // GCC allows "st(0)" to be called just plain "st".
26396 if (StringRef("{st}").equals_lower(Constraint)) {
26397 Res.first = X86::FP0;
26398 Res.second = &X86::RFP80RegClass;
26403 if (StringRef("{flags}").equals_lower(Constraint)) {
26404 Res.first = X86::EFLAGS;
26405 Res.second = &X86::CCRRegClass;
26409 // 'A' means EAX + EDX.
26410 if (Constraint == "A") {
26411 Res.first = X86::EAX;
26412 Res.second = &X86::GR32_ADRegClass;
26418 // Otherwise, check to see if this is a register class of the wrong value
26419 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26420 // turn into {ax},{dx}.
26421 // MVT::Other is used to specify clobber names.
26422 if (Res.second->hasType(VT) || VT == MVT::Other)
26423 return Res; // Correct type already, nothing to do.
26425 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
26426 // return "eax". This should even work for things like getting 64bit integer
26427 // registers when given an f64 type.
26428 const TargetRegisterClass *Class = Res.second;
26429 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
26430 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
26431 unsigned Size = VT.getSizeInBits();
26432 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
26433 : Size == 16 ? MVT::i16
26434 : Size == 32 ? MVT::i32
26435 : Size == 64 ? MVT::i64
26437 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
26439 Res.first = DestReg;
26440 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
26441 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
26442 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
26443 : &X86::GR64RegClass;
26444 assert(Res.second->contains(Res.first) && "Register in register class");
26446 // No register found/type mismatch.
26448 Res.second = nullptr;
26450 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
26451 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
26452 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
26453 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
26454 Class == &X86::VR512RegClass) {
26455 // Handle references to XMM physical registers that got mapped into the
26456 // wrong class. This can happen with constraints like {xmm0} where the
26457 // target independent register mapper will just pick the first match it can
26458 // find, ignoring the required type.
26460 if (VT == MVT::f32 || VT == MVT::i32)
26461 Res.second = &X86::FR32RegClass;
26462 else if (VT == MVT::f64 || VT == MVT::i64)
26463 Res.second = &X86::FR64RegClass;
26464 else if (X86::VR128RegClass.hasType(VT))
26465 Res.second = &X86::VR128RegClass;
26466 else if (X86::VR256RegClass.hasType(VT))
26467 Res.second = &X86::VR256RegClass;
26468 else if (X86::VR512RegClass.hasType(VT))
26469 Res.second = &X86::VR512RegClass;
26471 // Type mismatch and not a clobber: Return an error;
26473 Res.second = nullptr;
26480 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
26481 const AddrMode &AM, Type *Ty,
26482 unsigned AS) const {
26483 // Scaling factors are not free at all.
26484 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26485 // will take 2 allocations in the out of order engine instead of 1
26486 // for plain addressing mode, i.e. inst (reg1).
26488 // vaddps (%rsi,%drx), %ymm0, %ymm1
26489 // Requires two allocations (one for the load, one for the computation)
26491 // vaddps (%rsi), %ymm0, %ymm1
26492 // Requires just 1 allocation, i.e., freeing allocations for other operations
26493 // and having less micro operations to execute.
26495 // For some X86 architectures, this is even worse because for instance for
26496 // stores, the complex addressing mode forces the instruction to use the
26497 // "load" ports instead of the dedicated "store" port.
26498 // E.g., on Haswell:
26499 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26500 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26501 if (isLegalAddressingMode(DL, AM, Ty, AS))
26502 // Scale represents reg2 * scale, thus account for 1
26503 // as soon as we use a second register.
26504 return AM.Scale != 0;
26508 bool X86TargetLowering::isTargetFTOL() const {
26509 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
26512 bool X86TargetLowering::isIntDivCheap(EVT VT, bool OptSize) const {
26513 // Integer division on x86 is expensive. However, when aggressively optimizing
26514 // for code size, we prefer to use a div instruction, as it is usually smaller
26515 // than the alternative sequence.
26516 // The exception to this is vector division. Since x86 doesn't have vector
26517 // integer division, leaving the division as-is is a loss even in terms of
26518 // size, because it will have to be scalarized, while the alternative code
26519 // sequence can be performed in vector form.
26520 return OptSize && !VT.isVector();