1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1201 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::f64, Legal);
1210 if (Subtarget->hasInt256()) {
1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1224 // Don't lower v32i8 because there is no 128-bit byte mul
1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1243 // Don't lower v32i8 because there is no 128-bit byte mul
1246 // In the customized shift lowering, the legal cases in AVX2 will be
1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1256 // Custom lower several nodes for 256-bit types.
1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType)i;
1261 // Extract subvector is special because the value type
1262 // (result) is 128-bit but the source is 256-bit wide.
1263 if (VT.is128BitVector())
1264 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1266 // Do not attempt to custom lower other non-256-bit vectors
1267 if (!VT.is256BitVector())
1270 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1281 MVT VT = (MVT::SimpleValueType)i;
1283 // Do not attempt to promote non-256-bit vectors
1284 if (!VT.is256BitVector())
1287 setOperationAction(ISD::AND, VT, Promote);
1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1289 setOperationAction(ISD::OR, VT, Promote);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1291 setOperationAction(ISD::XOR, VT, Promote);
1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1293 setOperationAction(ISD::LOAD, VT, Promote);
1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1295 setOperationAction(ISD::SELECT, VT, Promote);
1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1300 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1338 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1340 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1341 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1343 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1344 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1345 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1346 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1347 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1348 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1349 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1353 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1368 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1370 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1373 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1374 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1376 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1377 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1379 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1381 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1382 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1384 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1385 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1387 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1390 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1391 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1392 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1393 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1394 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1395 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1397 // Custom lower several nodes.
1398 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1399 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1400 MVT VT = (MVT::SimpleValueType)i;
1402 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1403 // Extract subvector is special because the value type
1404 // (result) is 256/128-bit but the source is 512-bit wide.
1405 if (VT.is128BitVector() || VT.is256BitVector())
1406 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1408 if (VT.getVectorElementType() == MVT::i1)
1409 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1411 // Do not attempt to custom lower other non-512-bit vectors
1412 if (!VT.is512BitVector())
1415 if ( EltSize >= 32) {
1416 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1417 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1418 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1419 setOperationAction(ISD::VSELECT, VT, Legal);
1420 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1421 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1422 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1425 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1426 MVT VT = (MVT::SimpleValueType)i;
1428 // Do not attempt to promote non-256-bit vectors
1429 if (!VT.is512BitVector())
1432 setOperationAction(ISD::SELECT, VT, Promote);
1433 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1437 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1438 // of this type with custom code.
1439 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1440 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1441 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1445 // We want to custom lower some of our intrinsics.
1446 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1447 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1449 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1450 // handle type legalization for these operations here.
1452 // FIXME: We really should do custom legalization for addition and
1453 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1454 // than generic legalization for 64-bit multiplication-with-overflow, though.
1455 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1456 // Add/Sub/Mul with overflow operations are custom lowered.
1458 setOperationAction(ISD::SADDO, VT, Custom);
1459 setOperationAction(ISD::UADDO, VT, Custom);
1460 setOperationAction(ISD::SSUBO, VT, Custom);
1461 setOperationAction(ISD::USUBO, VT, Custom);
1462 setOperationAction(ISD::SMULO, VT, Custom);
1463 setOperationAction(ISD::UMULO, VT, Custom);
1466 // There are no 8-bit 3-address imul/mul instructions
1467 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1468 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1470 if (!Subtarget->is64Bit()) {
1471 // These libcalls are not available in 32-bit.
1472 setLibcallName(RTLIB::SHL_I128, 0);
1473 setLibcallName(RTLIB::SRL_I128, 0);
1474 setLibcallName(RTLIB::SRA_I128, 0);
1477 // Combine sin / cos into one node or libcall if possible.
1478 if (Subtarget->hasSinCos()) {
1479 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1480 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1481 if (Subtarget->isTargetDarwin()) {
1482 // For MacOSX, we don't want to the normal expansion of a libcall to
1483 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1485 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1486 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1490 // We have target-specific dag combine patterns for the following nodes:
1491 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1492 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1493 setTargetDAGCombine(ISD::VSELECT);
1494 setTargetDAGCombine(ISD::SELECT);
1495 setTargetDAGCombine(ISD::SHL);
1496 setTargetDAGCombine(ISD::SRA);
1497 setTargetDAGCombine(ISD::SRL);
1498 setTargetDAGCombine(ISD::OR);
1499 setTargetDAGCombine(ISD::AND);
1500 setTargetDAGCombine(ISD::ADD);
1501 setTargetDAGCombine(ISD::FADD);
1502 setTargetDAGCombine(ISD::FSUB);
1503 setTargetDAGCombine(ISD::FMA);
1504 setTargetDAGCombine(ISD::SUB);
1505 setTargetDAGCombine(ISD::LOAD);
1506 setTargetDAGCombine(ISD::STORE);
1507 setTargetDAGCombine(ISD::ZERO_EXTEND);
1508 setTargetDAGCombine(ISD::ANY_EXTEND);
1509 setTargetDAGCombine(ISD::SIGN_EXTEND);
1510 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1511 setTargetDAGCombine(ISD::TRUNCATE);
1512 setTargetDAGCombine(ISD::SINT_TO_FP);
1513 setTargetDAGCombine(ISD::SETCC);
1514 if (Subtarget->is64Bit())
1515 setTargetDAGCombine(ISD::MUL);
1516 setTargetDAGCombine(ISD::XOR);
1518 computeRegisterProperties();
1520 // On Darwin, -Os means optimize for size without hurting performance,
1521 // do not reduce the limit.
1522 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1523 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1524 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1525 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1526 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1527 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1528 setPrefLoopAlignment(4); // 2^4 bytes.
1530 // Predictable cmov don't hurt on atom because it's in-order.
1531 PredictableSelectIsExpensive = !Subtarget->isAtom();
1533 setPrefFunctionAlignment(4); // 2^4 bytes.
1536 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1537 if (!VT.isVector()) return MVT::i8;
1538 return VT.changeVectorElementTypeToInteger();
1541 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1542 /// the desired ByVal argument alignment.
1543 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1546 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1547 if (VTy->getBitWidth() == 128)
1549 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1550 unsigned EltAlign = 0;
1551 getMaxByValAlign(ATy->getElementType(), EltAlign);
1552 if (EltAlign > MaxAlign)
1553 MaxAlign = EltAlign;
1554 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1555 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1556 unsigned EltAlign = 0;
1557 getMaxByValAlign(STy->getElementType(i), EltAlign);
1558 if (EltAlign > MaxAlign)
1559 MaxAlign = EltAlign;
1566 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1567 /// function arguments in the caller parameter area. For X86, aggregates
1568 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1569 /// are at 4-byte boundaries.
1570 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1571 if (Subtarget->is64Bit()) {
1572 // Max of 8 and alignment of type.
1573 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1580 if (Subtarget->hasSSE1())
1581 getMaxByValAlign(Ty, Align);
1585 /// getOptimalMemOpType - Returns the target specific optimal type for load
1586 /// and store operations as a result of memset, memcpy, and memmove
1587 /// lowering. If DstAlign is zero that means it's safe to destination
1588 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1589 /// means there isn't a need to check it against alignment requirement,
1590 /// probably because the source does not need to be loaded. If 'IsMemset' is
1591 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1592 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1593 /// source is constant so it does not need to be loaded.
1594 /// It returns EVT::Other if the type should be determined using generic
1595 /// target-independent logic.
1597 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1598 unsigned DstAlign, unsigned SrcAlign,
1599 bool IsMemset, bool ZeroMemset,
1601 MachineFunction &MF) const {
1602 const Function *F = MF.getFunction();
1603 if ((!IsMemset || ZeroMemset) &&
1604 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1605 Attribute::NoImplicitFloat)) {
1607 (Subtarget->isUnalignedMemAccessFast() ||
1608 ((DstAlign == 0 || DstAlign >= 16) &&
1609 (SrcAlign == 0 || SrcAlign >= 16)))) {
1611 if (Subtarget->hasInt256())
1613 if (Subtarget->hasFp256())
1616 if (Subtarget->hasSSE2())
1618 if (Subtarget->hasSSE1())
1620 } else if (!MemcpyStrSrc && Size >= 8 &&
1621 !Subtarget->is64Bit() &&
1622 Subtarget->hasSSE2()) {
1623 // Do not use f64 to lower memcpy if source is string constant. It's
1624 // better to use i32 to avoid the loads.
1628 if (Subtarget->is64Bit() && Size >= 8)
1633 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1635 return X86ScalarSSEf32;
1636 else if (VT == MVT::f64)
1637 return X86ScalarSSEf64;
1642 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1644 *Fast = Subtarget->isUnalignedMemAccessFast();
1648 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1649 /// current function. The returned value is a member of the
1650 /// MachineJumpTableInfo::JTEntryKind enum.
1651 unsigned X86TargetLowering::getJumpTableEncoding() const {
1652 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1654 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1655 Subtarget->isPICStyleGOT())
1656 return MachineJumpTableInfo::EK_Custom32;
1658 // Otherwise, use the normal jump table encoding heuristics.
1659 return TargetLowering::getJumpTableEncoding();
1663 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1664 const MachineBasicBlock *MBB,
1665 unsigned uid,MCContext &Ctx) const{
1666 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1667 Subtarget->isPICStyleGOT());
1668 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1670 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1671 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1674 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1676 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1677 SelectionDAG &DAG) const {
1678 if (!Subtarget->is64Bit())
1679 // This doesn't have SDLoc associated with it, but is not really the
1680 // same as a Register.
1681 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1685 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1686 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1688 const MCExpr *X86TargetLowering::
1689 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1690 MCContext &Ctx) const {
1691 // X86-64 uses RIP relative addressing based on the jump table label.
1692 if (Subtarget->isPICStyleRIPRel())
1693 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1695 // Otherwise, the reference is relative to the PIC base.
1696 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1699 // FIXME: Why this routine is here? Move to RegInfo!
1700 std::pair<const TargetRegisterClass*, uint8_t>
1701 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1702 const TargetRegisterClass *RRC = 0;
1704 switch (VT.SimpleTy) {
1706 return TargetLowering::findRepresentativeClass(VT);
1707 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1708 RRC = Subtarget->is64Bit() ?
1709 (const TargetRegisterClass*)&X86::GR64RegClass :
1710 (const TargetRegisterClass*)&X86::GR32RegClass;
1713 RRC = &X86::VR64RegClass;
1715 case MVT::f32: case MVT::f64:
1716 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1717 case MVT::v4f32: case MVT::v2f64:
1718 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1720 RRC = &X86::VR128RegClass;
1723 return std::make_pair(RRC, Cost);
1726 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1727 unsigned &Offset) const {
1728 if (!Subtarget->isTargetLinux())
1731 if (Subtarget->is64Bit()) {
1732 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1734 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1746 //===----------------------------------------------------------------------===//
1747 // Return Value Calling Convention Implementation
1748 //===----------------------------------------------------------------------===//
1750 #include "X86GenCallingConv.inc"
1753 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1754 MachineFunction &MF, bool isVarArg,
1755 const SmallVectorImpl<ISD::OutputArg> &Outs,
1756 LLVMContext &Context) const {
1757 SmallVector<CCValAssign, 16> RVLocs;
1758 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1760 return CCInfo.CheckReturn(Outs, RetCC_X86);
1764 X86TargetLowering::LowerReturn(SDValue Chain,
1765 CallingConv::ID CallConv, bool isVarArg,
1766 const SmallVectorImpl<ISD::OutputArg> &Outs,
1767 const SmallVectorImpl<SDValue> &OutVals,
1768 SDLoc dl, SelectionDAG &DAG) const {
1769 MachineFunction &MF = DAG.getMachineFunction();
1770 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1772 SmallVector<CCValAssign, 16> RVLocs;
1773 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1774 RVLocs, *DAG.getContext());
1775 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1778 SmallVector<SDValue, 6> RetOps;
1779 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1780 // Operand #1 = Bytes To Pop
1781 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1784 // Copy the result values into the output registers.
1785 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1786 CCValAssign &VA = RVLocs[i];
1787 assert(VA.isRegLoc() && "Can only return in registers!");
1788 SDValue ValToCopy = OutVals[i];
1789 EVT ValVT = ValToCopy.getValueType();
1791 // Promote values to the appropriate types
1792 if (VA.getLocInfo() == CCValAssign::SExt)
1793 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1794 else if (VA.getLocInfo() == CCValAssign::ZExt)
1795 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1796 else if (VA.getLocInfo() == CCValAssign::AExt)
1797 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1798 else if (VA.getLocInfo() == CCValAssign::BCvt)
1799 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1801 // If this is x86-64, and we disabled SSE, we can't return FP values,
1802 // or SSE or MMX vectors.
1803 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1804 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1805 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1806 report_fatal_error("SSE register return with SSE disabled");
1808 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1809 // llvm-gcc has never done it right and no one has noticed, so this
1810 // should be OK for now.
1811 if (ValVT == MVT::f64 &&
1812 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1813 report_fatal_error("SSE2 register return with SSE2 disabled");
1815 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1816 // the RET instruction and handled by the FP Stackifier.
1817 if (VA.getLocReg() == X86::ST0 ||
1818 VA.getLocReg() == X86::ST1) {
1819 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1820 // change the value to the FP stack register class.
1821 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1822 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1823 RetOps.push_back(ValToCopy);
1824 // Don't emit a copytoreg.
1828 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1829 // which is returned in RAX / RDX.
1830 if (Subtarget->is64Bit()) {
1831 if (ValVT == MVT::x86mmx) {
1832 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1833 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1834 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1836 // If we don't have SSE2 available, convert to v4f32 so the generated
1837 // register is legal.
1838 if (!Subtarget->hasSSE2())
1839 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1844 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1845 Flag = Chain.getValue(1);
1846 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1849 // The x86-64 ABIs require that for returning structs by value we copy
1850 // the sret argument into %rax/%eax (depending on ABI) for the return.
1851 // Win32 requires us to put the sret argument to %eax as well.
1852 // We saved the argument into a virtual register in the entry block,
1853 // so now we copy the value out and into %rax/%eax.
1854 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1855 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1856 MachineFunction &MF = DAG.getMachineFunction();
1857 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1858 unsigned Reg = FuncInfo->getSRetReturnReg();
1860 "SRetReturnReg should have been set in LowerFormalArguments().");
1861 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1864 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1865 X86::RAX : X86::EAX;
1866 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1867 Flag = Chain.getValue(1);
1869 // RAX/EAX now acts like a return value.
1870 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1873 RetOps[0] = Chain; // Update chain.
1875 // Add the flag if we have it.
1877 RetOps.push_back(Flag);
1879 return DAG.getNode(X86ISD::RET_FLAG, dl,
1880 MVT::Other, &RetOps[0], RetOps.size());
1883 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1884 if (N->getNumValues() != 1)
1886 if (!N->hasNUsesOfValue(1, 0))
1889 SDValue TCChain = Chain;
1890 SDNode *Copy = *N->use_begin();
1891 if (Copy->getOpcode() == ISD::CopyToReg) {
1892 // If the copy has a glue operand, we conservatively assume it isn't safe to
1893 // perform a tail call.
1894 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1896 TCChain = Copy->getOperand(0);
1897 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1900 bool HasRet = false;
1901 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1903 if (UI->getOpcode() != X86ISD::RET_FLAG)
1916 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1917 ISD::NodeType ExtendKind) const {
1919 // TODO: Is this also valid on 32-bit?
1920 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1921 ReturnMVT = MVT::i8;
1923 ReturnMVT = MVT::i32;
1925 MVT MinVT = getRegisterType(ReturnMVT);
1926 return VT.bitsLT(MinVT) ? MinVT : VT;
1929 /// LowerCallResult - Lower the result values of a call into the
1930 /// appropriate copies out of appropriate physical registers.
1933 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1934 CallingConv::ID CallConv, bool isVarArg,
1935 const SmallVectorImpl<ISD::InputArg> &Ins,
1936 SDLoc dl, SelectionDAG &DAG,
1937 SmallVectorImpl<SDValue> &InVals) const {
1939 // Assign locations to each value returned by this call.
1940 SmallVector<CCValAssign, 16> RVLocs;
1941 bool Is64Bit = Subtarget->is64Bit();
1942 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1943 getTargetMachine(), RVLocs, *DAG.getContext());
1944 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1946 // Copy all of the result registers out of their specified physreg.
1947 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1948 CCValAssign &VA = RVLocs[i];
1949 EVT CopyVT = VA.getValVT();
1951 // If this is x86-64, and we disabled SSE, we can't return FP values
1952 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1953 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1954 report_fatal_error("SSE register return with SSE disabled");
1959 // If this is a call to a function that returns an fp value on the floating
1960 // point stack, we must guarantee the value is popped from the stack, so
1961 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1962 // if the return value is not used. We use the FpPOP_RETVAL instruction
1964 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1965 // If we prefer to use the value in xmm registers, copy it out as f80 and
1966 // use a truncate to move it from fp stack reg to xmm reg.
1967 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1968 SDValue Ops[] = { Chain, InFlag };
1969 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1970 MVT::Other, MVT::Glue, Ops), 1);
1971 Val = Chain.getValue(0);
1973 // Round the f80 to the right size, which also moves it to the appropriate
1975 if (CopyVT != VA.getValVT())
1976 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1977 // This truncation won't change the value.
1978 DAG.getIntPtrConstant(1));
1980 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1981 CopyVT, InFlag).getValue(1);
1982 Val = Chain.getValue(0);
1984 InFlag = Chain.getValue(2);
1985 InVals.push_back(Val);
1991 //===----------------------------------------------------------------------===//
1992 // C & StdCall & Fast Calling Convention implementation
1993 //===----------------------------------------------------------------------===//
1994 // StdCall calling convention seems to be standard for many Windows' API
1995 // routines and around. It differs from C calling convention just a little:
1996 // callee should clean up the stack, not caller. Symbols should be also
1997 // decorated in some fancy way :) It doesn't support any vector arguments.
1998 // For info on fast calling convention see Fast Calling Convention (tail call)
1999 // implementation LowerX86_32FastCCCallTo.
2001 /// CallIsStructReturn - Determines whether a call uses struct return
2003 enum StructReturnType {
2008 static StructReturnType
2009 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2011 return NotStructReturn;
2013 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2014 if (!Flags.isSRet())
2015 return NotStructReturn;
2016 if (Flags.isInReg())
2017 return RegStructReturn;
2018 return StackStructReturn;
2021 /// ArgsAreStructReturn - Determines whether a function uses struct
2022 /// return semantics.
2023 static StructReturnType
2024 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2026 return NotStructReturn;
2028 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2029 if (!Flags.isSRet())
2030 return NotStructReturn;
2031 if (Flags.isInReg())
2032 return RegStructReturn;
2033 return StackStructReturn;
2036 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2037 /// by "Src" to address "Dst" with size and alignment information specified by
2038 /// the specific parameter attribute. The copy will be passed as a byval
2039 /// function parameter.
2041 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2042 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2044 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2046 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2047 /*isVolatile*/false, /*AlwaysInline=*/true,
2048 MachinePointerInfo(), MachinePointerInfo());
2051 /// IsTailCallConvention - Return true if the calling convention is one that
2052 /// supports tail call optimization.
2053 static bool IsTailCallConvention(CallingConv::ID CC) {
2054 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2055 CC == CallingConv::HiPE);
2058 /// \brief Return true if the calling convention is a C calling convention.
2059 static bool IsCCallConvention(CallingConv::ID CC) {
2060 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2061 CC == CallingConv::X86_64_SysV);
2064 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2065 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2069 CallingConv::ID CalleeCC = CS.getCallingConv();
2070 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2076 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2077 /// a tailcall target by changing its ABI.
2078 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2079 bool GuaranteedTailCallOpt) {
2080 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2084 X86TargetLowering::LowerMemArgument(SDValue Chain,
2085 CallingConv::ID CallConv,
2086 const SmallVectorImpl<ISD::InputArg> &Ins,
2087 SDLoc dl, SelectionDAG &DAG,
2088 const CCValAssign &VA,
2089 MachineFrameInfo *MFI,
2091 // Create the nodes corresponding to a load from this parameter slot.
2092 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2093 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2094 getTargetMachine().Options.GuaranteedTailCallOpt);
2095 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2098 // If value is passed by pointer we have address passed instead of the value
2100 if (VA.getLocInfo() == CCValAssign::Indirect)
2101 ValVT = VA.getLocVT();
2103 ValVT = VA.getValVT();
2105 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2106 // changed with more analysis.
2107 // In case of tail call optimization mark all arguments mutable. Since they
2108 // could be overwritten by lowering of arguments in case of a tail call.
2109 if (Flags.isByVal()) {
2110 unsigned Bytes = Flags.getByValSize();
2111 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2112 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2113 return DAG.getFrameIndex(FI, getPointerTy());
2115 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2116 VA.getLocMemOffset(), isImmutable);
2117 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2118 return DAG.getLoad(ValVT, dl, Chain, FIN,
2119 MachinePointerInfo::getFixedStack(FI),
2120 false, false, false, 0);
2125 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2126 CallingConv::ID CallConv,
2128 const SmallVectorImpl<ISD::InputArg> &Ins,
2131 SmallVectorImpl<SDValue> &InVals)
2133 MachineFunction &MF = DAG.getMachineFunction();
2134 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2136 const Function* Fn = MF.getFunction();
2137 if (Fn->hasExternalLinkage() &&
2138 Subtarget->isTargetCygMing() &&
2139 Fn->getName() == "main")
2140 FuncInfo->setForceFramePointer(true);
2142 MachineFrameInfo *MFI = MF.getFrameInfo();
2143 bool Is64Bit = Subtarget->is64Bit();
2144 bool IsWindows = Subtarget->isTargetWindows();
2145 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2147 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2148 "Var args not supported with calling convention fastcc, ghc or hipe");
2150 // Assign locations to all of the incoming arguments.
2151 SmallVector<CCValAssign, 16> ArgLocs;
2152 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2153 ArgLocs, *DAG.getContext());
2155 // Allocate shadow area for Win64
2157 CCInfo.AllocateStack(32, 8);
2159 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2161 unsigned LastVal = ~0U;
2163 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2164 CCValAssign &VA = ArgLocs[i];
2165 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2167 assert(VA.getValNo() != LastVal &&
2168 "Don't support value assigned to multiple locs yet");
2170 LastVal = VA.getValNo();
2172 if (VA.isRegLoc()) {
2173 EVT RegVT = VA.getLocVT();
2174 const TargetRegisterClass *RC;
2175 if (RegVT == MVT::i32)
2176 RC = &X86::GR32RegClass;
2177 else if (Is64Bit && RegVT == MVT::i64)
2178 RC = &X86::GR64RegClass;
2179 else if (RegVT == MVT::f32)
2180 RC = &X86::FR32RegClass;
2181 else if (RegVT == MVT::f64)
2182 RC = &X86::FR64RegClass;
2183 else if (RegVT.is512BitVector())
2184 RC = &X86::VR512RegClass;
2185 else if (RegVT.is256BitVector())
2186 RC = &X86::VR256RegClass;
2187 else if (RegVT.is128BitVector())
2188 RC = &X86::VR128RegClass;
2189 else if (RegVT == MVT::x86mmx)
2190 RC = &X86::VR64RegClass;
2191 else if (RegVT == MVT::v8i1)
2192 RC = &X86::VK8RegClass;
2193 else if (RegVT == MVT::v16i1)
2194 RC = &X86::VK16RegClass;
2196 llvm_unreachable("Unknown argument type!");
2198 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2199 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2201 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2202 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2204 if (VA.getLocInfo() == CCValAssign::SExt)
2205 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2206 DAG.getValueType(VA.getValVT()));
2207 else if (VA.getLocInfo() == CCValAssign::ZExt)
2208 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2209 DAG.getValueType(VA.getValVT()));
2210 else if (VA.getLocInfo() == CCValAssign::BCvt)
2211 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2213 if (VA.isExtInLoc()) {
2214 // Handle MMX values passed in XMM regs.
2215 if (RegVT.isVector())
2216 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2218 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2221 assert(VA.isMemLoc());
2222 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2225 // If value is passed via pointer - do a load.
2226 if (VA.getLocInfo() == CCValAssign::Indirect)
2227 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2228 MachinePointerInfo(), false, false, false, 0);
2230 InVals.push_back(ArgValue);
2233 // The x86-64 ABIs require that for returning structs by value we copy
2234 // the sret argument into %rax/%eax (depending on ABI) for the return.
2235 // Win32 requires us to put the sret argument to %eax as well.
2236 // Save the argument into a virtual register so that we can access it
2237 // from the return points.
2238 if (MF.getFunction()->hasStructRetAttr() &&
2239 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2240 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2241 unsigned Reg = FuncInfo->getSRetReturnReg();
2243 MVT PtrTy = getPointerTy();
2244 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2245 FuncInfo->setSRetReturnReg(Reg);
2247 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2248 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2251 unsigned StackSize = CCInfo.getNextStackOffset();
2252 // Align stack specially for tail calls.
2253 if (FuncIsMadeTailCallSafe(CallConv,
2254 MF.getTarget().Options.GuaranteedTailCallOpt))
2255 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2257 // If the function takes variable number of arguments, make a frame index for
2258 // the start of the first vararg value... for expansion of llvm.va_start.
2260 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2261 CallConv != CallingConv::X86_ThisCall)) {
2262 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2265 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2267 // FIXME: We should really autogenerate these arrays
2268 static const uint16_t GPR64ArgRegsWin64[] = {
2269 X86::RCX, X86::RDX, X86::R8, X86::R9
2271 static const uint16_t GPR64ArgRegs64Bit[] = {
2272 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2274 static const uint16_t XMMArgRegs64Bit[] = {
2275 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2276 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2278 const uint16_t *GPR64ArgRegs;
2279 unsigned NumXMMRegs = 0;
2282 // The XMM registers which might contain var arg parameters are shadowed
2283 // in their paired GPR. So we only need to save the GPR to their home
2285 TotalNumIntRegs = 4;
2286 GPR64ArgRegs = GPR64ArgRegsWin64;
2288 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2289 GPR64ArgRegs = GPR64ArgRegs64Bit;
2291 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2294 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2297 bool NoImplicitFloatOps = Fn->getAttributes().
2298 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2299 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2300 "SSE register cannot be used when SSE is disabled!");
2301 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2302 NoImplicitFloatOps) &&
2303 "SSE register cannot be used when SSE is disabled!");
2304 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2305 !Subtarget->hasSSE1())
2306 // Kernel mode asks for SSE to be disabled, so don't push them
2308 TotalNumXMMRegs = 0;
2311 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2312 // Get to the caller-allocated home save location. Add 8 to account
2313 // for the return address.
2314 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2315 FuncInfo->setRegSaveFrameIndex(
2316 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2317 // Fixup to set vararg frame on shadow area (4 x i64).
2319 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2321 // For X86-64, if there are vararg parameters that are passed via
2322 // registers, then we must store them to their spots on the stack so
2323 // they may be loaded by deferencing the result of va_next.
2324 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2325 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2326 FuncInfo->setRegSaveFrameIndex(
2327 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2331 // Store the integer parameter registers.
2332 SmallVector<SDValue, 8> MemOps;
2333 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2335 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2336 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2337 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2338 DAG.getIntPtrConstant(Offset));
2339 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2340 &X86::GR64RegClass);
2341 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2343 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2344 MachinePointerInfo::getFixedStack(
2345 FuncInfo->getRegSaveFrameIndex(), Offset),
2347 MemOps.push_back(Store);
2351 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2352 // Now store the XMM (fp + vector) parameter registers.
2353 SmallVector<SDValue, 11> SaveXMMOps;
2354 SaveXMMOps.push_back(Chain);
2356 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2357 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2358 SaveXMMOps.push_back(ALVal);
2360 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2361 FuncInfo->getRegSaveFrameIndex()));
2362 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2363 FuncInfo->getVarArgsFPOffset()));
2365 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2366 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2367 &X86::VR128RegClass);
2368 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2369 SaveXMMOps.push_back(Val);
2371 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2373 &SaveXMMOps[0], SaveXMMOps.size()));
2376 if (!MemOps.empty())
2377 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2378 &MemOps[0], MemOps.size());
2382 // Some CCs need callee pop.
2383 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2384 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2385 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2387 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2388 // If this is an sret function, the return should pop the hidden pointer.
2389 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2390 argsAreStructReturn(Ins) == StackStructReturn)
2391 FuncInfo->setBytesToPopOnReturn(4);
2395 // RegSaveFrameIndex is X86-64 only.
2396 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2397 if (CallConv == CallingConv::X86_FastCall ||
2398 CallConv == CallingConv::X86_ThisCall)
2399 // fastcc functions can't have varargs.
2400 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2403 FuncInfo->setArgumentStackSize(StackSize);
2409 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2410 SDValue StackPtr, SDValue Arg,
2411 SDLoc dl, SelectionDAG &DAG,
2412 const CCValAssign &VA,
2413 ISD::ArgFlagsTy Flags) const {
2414 unsigned LocMemOffset = VA.getLocMemOffset();
2415 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2416 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2417 if (Flags.isByVal())
2418 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2420 return DAG.getStore(Chain, dl, Arg, PtrOff,
2421 MachinePointerInfo::getStack(LocMemOffset),
2425 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2426 /// optimization is performed and it is required.
2428 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2429 SDValue &OutRetAddr, SDValue Chain,
2430 bool IsTailCall, bool Is64Bit,
2431 int FPDiff, SDLoc dl) const {
2432 // Adjust the Return address stack slot.
2433 EVT VT = getPointerTy();
2434 OutRetAddr = getReturnAddressFrameIndex(DAG);
2436 // Load the "old" Return address.
2437 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2438 false, false, false, 0);
2439 return SDValue(OutRetAddr.getNode(), 1);
2442 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2443 /// optimization is performed and it is required (FPDiff!=0).
2445 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2446 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2447 unsigned SlotSize, int FPDiff, SDLoc dl) {
2448 // Store the return address to the appropriate stack slot.
2449 if (!FPDiff) return Chain;
2450 // Calculate the new stack slot for the return address.
2451 int NewReturnAddrFI =
2452 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2454 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2455 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2456 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2462 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2463 SmallVectorImpl<SDValue> &InVals) const {
2464 SelectionDAG &DAG = CLI.DAG;
2466 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2467 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2468 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2469 SDValue Chain = CLI.Chain;
2470 SDValue Callee = CLI.Callee;
2471 CallingConv::ID CallConv = CLI.CallConv;
2472 bool &isTailCall = CLI.IsTailCall;
2473 bool isVarArg = CLI.IsVarArg;
2475 MachineFunction &MF = DAG.getMachineFunction();
2476 bool Is64Bit = Subtarget->is64Bit();
2477 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2478 bool IsWindows = Subtarget->isTargetWindows();
2479 StructReturnType SR = callIsStructReturn(Outs);
2480 bool IsSibcall = false;
2482 if (MF.getTarget().Options.DisableTailCalls)
2486 // Check if it's really possible to do a tail call.
2487 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2488 isVarArg, SR != NotStructReturn,
2489 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2490 Outs, OutVals, Ins, DAG);
2492 // Sibcalls are automatically detected tailcalls which do not require
2494 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2501 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2502 "Var args not supported with calling convention fastcc, ghc or hipe");
2504 // Analyze operands of the call, assigning locations to each operand.
2505 SmallVector<CCValAssign, 16> ArgLocs;
2506 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2507 ArgLocs, *DAG.getContext());
2509 // Allocate shadow area for Win64
2511 CCInfo.AllocateStack(32, 8);
2513 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2515 // Get a count of how many bytes are to be pushed on the stack.
2516 unsigned NumBytes = CCInfo.getNextStackOffset();
2518 // This is a sibcall. The memory operands are available in caller's
2519 // own caller's stack.
2521 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2522 IsTailCallConvention(CallConv))
2523 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2526 if (isTailCall && !IsSibcall) {
2527 // Lower arguments at fp - stackoffset + fpdiff.
2528 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2529 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2531 FPDiff = NumBytesCallerPushed - NumBytes;
2533 // Set the delta of movement of the returnaddr stackslot.
2534 // But only set if delta is greater than previous delta.
2535 if (FPDiff < X86Info->getTCReturnAddrDelta())
2536 X86Info->setTCReturnAddrDelta(FPDiff);
2540 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2543 SDValue RetAddrFrIdx;
2544 // Load return address for tail calls.
2545 if (isTailCall && FPDiff)
2546 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2547 Is64Bit, FPDiff, dl);
2549 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2550 SmallVector<SDValue, 8> MemOpChains;
2553 // Walk the register/memloc assignments, inserting copies/loads. In the case
2554 // of tail call optimization arguments are handle later.
2555 const X86RegisterInfo *RegInfo =
2556 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2557 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2558 CCValAssign &VA = ArgLocs[i];
2559 EVT RegVT = VA.getLocVT();
2560 SDValue Arg = OutVals[i];
2561 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2562 bool isByVal = Flags.isByVal();
2564 // Promote the value if needed.
2565 switch (VA.getLocInfo()) {
2566 default: llvm_unreachable("Unknown loc info!");
2567 case CCValAssign::Full: break;
2568 case CCValAssign::SExt:
2569 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2571 case CCValAssign::ZExt:
2572 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2574 case CCValAssign::AExt:
2575 if (RegVT.is128BitVector()) {
2576 // Special case: passing MMX values in XMM registers.
2577 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2578 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2579 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2581 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2583 case CCValAssign::BCvt:
2584 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2586 case CCValAssign::Indirect: {
2587 // Store the argument.
2588 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2589 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2590 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2591 MachinePointerInfo::getFixedStack(FI),
2598 if (VA.isRegLoc()) {
2599 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2600 if (isVarArg && IsWin64) {
2601 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2602 // shadow reg if callee is a varargs function.
2603 unsigned ShadowReg = 0;
2604 switch (VA.getLocReg()) {
2605 case X86::XMM0: ShadowReg = X86::RCX; break;
2606 case X86::XMM1: ShadowReg = X86::RDX; break;
2607 case X86::XMM2: ShadowReg = X86::R8; break;
2608 case X86::XMM3: ShadowReg = X86::R9; break;
2611 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2613 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2614 assert(VA.isMemLoc());
2615 if (StackPtr.getNode() == 0)
2616 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2618 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2619 dl, DAG, VA, Flags));
2623 if (!MemOpChains.empty())
2624 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2625 &MemOpChains[0], MemOpChains.size());
2627 if (Subtarget->isPICStyleGOT()) {
2628 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2631 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2632 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2634 // If we are tail calling and generating PIC/GOT style code load the
2635 // address of the callee into ECX. The value in ecx is used as target of
2636 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2637 // for tail calls on PIC/GOT architectures. Normally we would just put the
2638 // address of GOT into ebx and then call target@PLT. But for tail calls
2639 // ebx would be restored (since ebx is callee saved) before jumping to the
2642 // Note: The actual moving to ECX is done further down.
2643 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2644 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2645 !G->getGlobal()->hasProtectedVisibility())
2646 Callee = LowerGlobalAddress(Callee, DAG);
2647 else if (isa<ExternalSymbolSDNode>(Callee))
2648 Callee = LowerExternalSymbol(Callee, DAG);
2652 if (Is64Bit && isVarArg && !IsWin64) {
2653 // From AMD64 ABI document:
2654 // For calls that may call functions that use varargs or stdargs
2655 // (prototype-less calls or calls to functions containing ellipsis (...) in
2656 // the declaration) %al is used as hidden argument to specify the number
2657 // of SSE registers used. The contents of %al do not need to match exactly
2658 // the number of registers, but must be an ubound on the number of SSE
2659 // registers used and is in the range 0 - 8 inclusive.
2661 // Count the number of XMM registers allocated.
2662 static const uint16_t XMMArgRegs[] = {
2663 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2664 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2666 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2667 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2668 && "SSE registers cannot be used when SSE is disabled");
2670 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2671 DAG.getConstant(NumXMMRegs, MVT::i8)));
2674 // For tail calls lower the arguments to the 'real' stack slot.
2676 // Force all the incoming stack arguments to be loaded from the stack
2677 // before any new outgoing arguments are stored to the stack, because the
2678 // outgoing stack slots may alias the incoming argument stack slots, and
2679 // the alias isn't otherwise explicit. This is slightly more conservative
2680 // than necessary, because it means that each store effectively depends
2681 // on every argument instead of just those arguments it would clobber.
2682 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2684 SmallVector<SDValue, 8> MemOpChains2;
2687 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2688 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2689 CCValAssign &VA = ArgLocs[i];
2692 assert(VA.isMemLoc());
2693 SDValue Arg = OutVals[i];
2694 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2695 // Create frame index.
2696 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2697 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2698 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2699 FIN = DAG.getFrameIndex(FI, getPointerTy());
2701 if (Flags.isByVal()) {
2702 // Copy relative to framepointer.
2703 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2704 if (StackPtr.getNode() == 0)
2705 StackPtr = DAG.getCopyFromReg(Chain, dl,
2706 RegInfo->getStackRegister(),
2708 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2710 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2714 // Store relative to framepointer.
2715 MemOpChains2.push_back(
2716 DAG.getStore(ArgChain, dl, Arg, FIN,
2717 MachinePointerInfo::getFixedStack(FI),
2723 if (!MemOpChains2.empty())
2724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2725 &MemOpChains2[0], MemOpChains2.size());
2727 // Store the return address to the appropriate stack slot.
2728 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2729 getPointerTy(), RegInfo->getSlotSize(),
2733 // Build a sequence of copy-to-reg nodes chained together with token chain
2734 // and flag operands which copy the outgoing args into registers.
2736 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2737 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2738 RegsToPass[i].second, InFlag);
2739 InFlag = Chain.getValue(1);
2742 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2743 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2744 // In the 64-bit large code model, we have to make all calls
2745 // through a register, since the call instruction's 32-bit
2746 // pc-relative offset may not be large enough to hold the whole
2748 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2749 // If the callee is a GlobalAddress node (quite common, every direct call
2750 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2753 // We should use extra load for direct calls to dllimported functions in
2755 const GlobalValue *GV = G->getGlobal();
2756 if (!GV->hasDLLImportLinkage()) {
2757 unsigned char OpFlags = 0;
2758 bool ExtraLoad = false;
2759 unsigned WrapperKind = ISD::DELETED_NODE;
2761 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2762 // external symbols most go through the PLT in PIC mode. If the symbol
2763 // has hidden or protected visibility, or if it is static or local, then
2764 // we don't need to use the PLT - we can directly call it.
2765 if (Subtarget->isTargetELF() &&
2766 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2767 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2768 OpFlags = X86II::MO_PLT;
2769 } else if (Subtarget->isPICStyleStubAny() &&
2770 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2771 (!Subtarget->getTargetTriple().isMacOSX() ||
2772 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2773 // PC-relative references to external symbols should go through $stub,
2774 // unless we're building with the leopard linker or later, which
2775 // automatically synthesizes these stubs.
2776 OpFlags = X86II::MO_DARWIN_STUB;
2777 } else if (Subtarget->isPICStyleRIPRel() &&
2778 isa<Function>(GV) &&
2779 cast<Function>(GV)->getAttributes().
2780 hasAttribute(AttributeSet::FunctionIndex,
2781 Attribute::NonLazyBind)) {
2782 // If the function is marked as non-lazy, generate an indirect call
2783 // which loads from the GOT directly. This avoids runtime overhead
2784 // at the cost of eager binding (and one extra byte of encoding).
2785 OpFlags = X86II::MO_GOTPCREL;
2786 WrapperKind = X86ISD::WrapperRIP;
2790 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2791 G->getOffset(), OpFlags);
2793 // Add a wrapper if needed.
2794 if (WrapperKind != ISD::DELETED_NODE)
2795 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2796 // Add extra indirection if needed.
2798 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2799 MachinePointerInfo::getGOT(),
2800 false, false, false, 0);
2802 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2803 unsigned char OpFlags = 0;
2805 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2806 // external symbols should go through the PLT.
2807 if (Subtarget->isTargetELF() &&
2808 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2809 OpFlags = X86II::MO_PLT;
2810 } else if (Subtarget->isPICStyleStubAny() &&
2811 (!Subtarget->getTargetTriple().isMacOSX() ||
2812 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2813 // PC-relative references to external symbols should go through $stub,
2814 // unless we're building with the leopard linker or later, which
2815 // automatically synthesizes these stubs.
2816 OpFlags = X86II::MO_DARWIN_STUB;
2819 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2823 // Returns a chain & a flag for retval copy to use.
2824 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2825 SmallVector<SDValue, 8> Ops;
2827 if (!IsSibcall && isTailCall) {
2828 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2829 DAG.getIntPtrConstant(0, true), InFlag, dl);
2830 InFlag = Chain.getValue(1);
2833 Ops.push_back(Chain);
2834 Ops.push_back(Callee);
2837 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2839 // Add argument registers to the end of the list so that they are known live
2841 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2842 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2843 RegsToPass[i].second.getValueType()));
2845 // Add a register mask operand representing the call-preserved registers.
2846 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2847 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2848 assert(Mask && "Missing call preserved mask for calling convention");
2849 Ops.push_back(DAG.getRegisterMask(Mask));
2851 if (InFlag.getNode())
2852 Ops.push_back(InFlag);
2856 //// If this is the first return lowered for this function, add the regs
2857 //// to the liveout set for the function.
2858 // This isn't right, although it's probably harmless on x86; liveouts
2859 // should be computed from returns not tail calls. Consider a void
2860 // function making a tail call to a function returning int.
2861 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2864 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2865 InFlag = Chain.getValue(1);
2867 // Create the CALLSEQ_END node.
2868 unsigned NumBytesForCalleeToPush;
2869 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2870 getTargetMachine().Options.GuaranteedTailCallOpt))
2871 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2872 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2873 SR == StackStructReturn)
2874 // If this is a call to a struct-return function, the callee
2875 // pops the hidden struct pointer, so we have to push it back.
2876 // This is common for Darwin/X86, Linux & Mingw32 targets.
2877 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2878 NumBytesForCalleeToPush = 4;
2880 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2882 // Returns a flag for retval copy to use.
2884 Chain = DAG.getCALLSEQ_END(Chain,
2885 DAG.getIntPtrConstant(NumBytes, true),
2886 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2889 InFlag = Chain.getValue(1);
2892 // Handle result values, copying them out of physregs into vregs that we
2894 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2895 Ins, dl, DAG, InVals);
2898 //===----------------------------------------------------------------------===//
2899 // Fast Calling Convention (tail call) implementation
2900 //===----------------------------------------------------------------------===//
2902 // Like std call, callee cleans arguments, convention except that ECX is
2903 // reserved for storing the tail called function address. Only 2 registers are
2904 // free for argument passing (inreg). Tail call optimization is performed
2906 // * tailcallopt is enabled
2907 // * caller/callee are fastcc
2908 // On X86_64 architecture with GOT-style position independent code only local
2909 // (within module) calls are supported at the moment.
2910 // To keep the stack aligned according to platform abi the function
2911 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2912 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2913 // If a tail called function callee has more arguments than the caller the
2914 // caller needs to make sure that there is room to move the RETADDR to. This is
2915 // achieved by reserving an area the size of the argument delta right after the
2916 // original REtADDR, but before the saved framepointer or the spilled registers
2917 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2929 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2930 /// for a 16 byte align requirement.
2932 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2933 SelectionDAG& DAG) const {
2934 MachineFunction &MF = DAG.getMachineFunction();
2935 const TargetMachine &TM = MF.getTarget();
2936 const X86RegisterInfo *RegInfo =
2937 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2938 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2939 unsigned StackAlignment = TFI.getStackAlignment();
2940 uint64_t AlignMask = StackAlignment - 1;
2941 int64_t Offset = StackSize;
2942 unsigned SlotSize = RegInfo->getSlotSize();
2943 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2944 // Number smaller than 12 so just add the difference.
2945 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2947 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2948 Offset = ((~AlignMask) & Offset) + StackAlignment +
2949 (StackAlignment-SlotSize);
2954 /// MatchingStackOffset - Return true if the given stack call argument is
2955 /// already available in the same position (relatively) of the caller's
2956 /// incoming argument stack.
2958 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2959 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2960 const X86InstrInfo *TII) {
2961 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2963 if (Arg.getOpcode() == ISD::CopyFromReg) {
2964 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2965 if (!TargetRegisterInfo::isVirtualRegister(VR))
2967 MachineInstr *Def = MRI->getVRegDef(VR);
2970 if (!Flags.isByVal()) {
2971 if (!TII->isLoadFromStackSlot(Def, FI))
2974 unsigned Opcode = Def->getOpcode();
2975 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2976 Def->getOperand(1).isFI()) {
2977 FI = Def->getOperand(1).getIndex();
2978 Bytes = Flags.getByValSize();
2982 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2983 if (Flags.isByVal())
2984 // ByVal argument is passed in as a pointer but it's now being
2985 // dereferenced. e.g.
2986 // define @foo(%struct.X* %A) {
2987 // tail call @bar(%struct.X* byval %A)
2990 SDValue Ptr = Ld->getBasePtr();
2991 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2994 FI = FINode->getIndex();
2995 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2996 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2997 FI = FINode->getIndex();
2998 Bytes = Flags.getByValSize();
3002 assert(FI != INT_MAX);
3003 if (!MFI->isFixedObjectIndex(FI))
3005 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3008 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3009 /// for tail call optimization. Targets which want to do tail call
3010 /// optimization should implement this function.
3012 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3013 CallingConv::ID CalleeCC,
3015 bool isCalleeStructRet,
3016 bool isCallerStructRet,
3018 const SmallVectorImpl<ISD::OutputArg> &Outs,
3019 const SmallVectorImpl<SDValue> &OutVals,
3020 const SmallVectorImpl<ISD::InputArg> &Ins,
3021 SelectionDAG &DAG) const {
3022 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3025 // If -tailcallopt is specified, make fastcc functions tail-callable.
3026 const MachineFunction &MF = DAG.getMachineFunction();
3027 const Function *CallerF = MF.getFunction();
3029 // If the function return type is x86_fp80 and the callee return type is not,
3030 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3031 // perform a tailcall optimization here.
3032 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3035 CallingConv::ID CallerCC = CallerF->getCallingConv();
3036 bool CCMatch = CallerCC == CalleeCC;
3037 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3038 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3040 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3041 if (IsTailCallConvention(CalleeCC) && CCMatch)
3046 // Look for obvious safe cases to perform tail call optimization that do not
3047 // require ABI changes. This is what gcc calls sibcall.
3049 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3050 // emit a special epilogue.
3051 const X86RegisterInfo *RegInfo =
3052 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3053 if (RegInfo->needsStackRealignment(MF))
3056 // Also avoid sibcall optimization if either caller or callee uses struct
3057 // return semantics.
3058 if (isCalleeStructRet || isCallerStructRet)
3061 // An stdcall caller is expected to clean up its arguments; the callee
3062 // isn't going to do that.
3063 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3066 // Do not sibcall optimize vararg calls unless all arguments are passed via
3068 if (isVarArg && !Outs.empty()) {
3070 // Optimizing for varargs on Win64 is unlikely to be safe without
3071 // additional testing.
3072 if (IsCalleeWin64 || IsCallerWin64)
3075 SmallVector<CCValAssign, 16> ArgLocs;
3076 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3077 getTargetMachine(), ArgLocs, *DAG.getContext());
3079 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3080 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3081 if (!ArgLocs[i].isRegLoc())
3085 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3086 // stack. Therefore, if it's not used by the call it is not safe to optimize
3087 // this into a sibcall.
3088 bool Unused = false;
3089 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3096 SmallVector<CCValAssign, 16> RVLocs;
3097 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3098 getTargetMachine(), RVLocs, *DAG.getContext());
3099 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3100 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3101 CCValAssign &VA = RVLocs[i];
3102 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3107 // If the calling conventions do not match, then we'd better make sure the
3108 // results are returned in the same way as what the caller expects.
3110 SmallVector<CCValAssign, 16> RVLocs1;
3111 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3112 getTargetMachine(), RVLocs1, *DAG.getContext());
3113 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3115 SmallVector<CCValAssign, 16> RVLocs2;
3116 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3117 getTargetMachine(), RVLocs2, *DAG.getContext());
3118 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3120 if (RVLocs1.size() != RVLocs2.size())
3122 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3123 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3125 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3127 if (RVLocs1[i].isRegLoc()) {
3128 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3131 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3137 // If the callee takes no arguments then go on to check the results of the
3139 if (!Outs.empty()) {
3140 // Check if stack adjustment is needed. For now, do not do this if any
3141 // argument is passed on the stack.
3142 SmallVector<CCValAssign, 16> ArgLocs;
3143 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3144 getTargetMachine(), ArgLocs, *DAG.getContext());
3146 // Allocate shadow area for Win64
3148 CCInfo.AllocateStack(32, 8);
3150 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3151 if (CCInfo.getNextStackOffset()) {
3152 MachineFunction &MF = DAG.getMachineFunction();
3153 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3156 // Check if the arguments are already laid out in the right way as
3157 // the caller's fixed stack objects.
3158 MachineFrameInfo *MFI = MF.getFrameInfo();
3159 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3160 const X86InstrInfo *TII =
3161 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3162 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3163 CCValAssign &VA = ArgLocs[i];
3164 SDValue Arg = OutVals[i];
3165 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3166 if (VA.getLocInfo() == CCValAssign::Indirect)
3168 if (!VA.isRegLoc()) {
3169 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3176 // If the tailcall address may be in a register, then make sure it's
3177 // possible to register allocate for it. In 32-bit, the call address can
3178 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3179 // callee-saved registers are restored. These happen to be the same
3180 // registers used to pass 'inreg' arguments so watch out for those.
3181 if (!Subtarget->is64Bit() &&
3182 ((!isa<GlobalAddressSDNode>(Callee) &&
3183 !isa<ExternalSymbolSDNode>(Callee)) ||
3184 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3185 unsigned NumInRegs = 0;
3186 // In PIC we need an extra register to formulate the address computation
3188 unsigned MaxInRegs =
3189 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3191 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3192 CCValAssign &VA = ArgLocs[i];
3195 unsigned Reg = VA.getLocReg();
3198 case X86::EAX: case X86::EDX: case X86::ECX:
3199 if (++NumInRegs == MaxInRegs)
3211 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3212 const TargetLibraryInfo *libInfo) const {
3213 return X86::createFastISel(funcInfo, libInfo);
3216 //===----------------------------------------------------------------------===//
3217 // Other Lowering Hooks
3218 //===----------------------------------------------------------------------===//
3220 static bool MayFoldLoad(SDValue Op) {
3221 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3224 static bool MayFoldIntoStore(SDValue Op) {
3225 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3228 static bool isTargetShuffle(unsigned Opcode) {
3230 default: return false;
3231 case X86ISD::PSHUFD:
3232 case X86ISD::PSHUFHW:
3233 case X86ISD::PSHUFLW:
3235 case X86ISD::PALIGNR:
3236 case X86ISD::MOVLHPS:
3237 case X86ISD::MOVLHPD:
3238 case X86ISD::MOVHLPS:
3239 case X86ISD::MOVLPS:
3240 case X86ISD::MOVLPD:
3241 case X86ISD::MOVSHDUP:
3242 case X86ISD::MOVSLDUP:
3243 case X86ISD::MOVDDUP:
3246 case X86ISD::UNPCKL:
3247 case X86ISD::UNPCKH:
3248 case X86ISD::VPERMILP:
3249 case X86ISD::VPERM2X128:
3250 case X86ISD::VPERMI:
3255 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3256 SDValue V1, SelectionDAG &DAG) {
3258 default: llvm_unreachable("Unknown x86 shuffle node");
3259 case X86ISD::MOVSHDUP:
3260 case X86ISD::MOVSLDUP:
3261 case X86ISD::MOVDDUP:
3262 return DAG.getNode(Opc, dl, VT, V1);
3266 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3267 SDValue V1, unsigned TargetMask,
3268 SelectionDAG &DAG) {
3270 default: llvm_unreachable("Unknown x86 shuffle node");
3271 case X86ISD::PSHUFD:
3272 case X86ISD::PSHUFHW:
3273 case X86ISD::PSHUFLW:
3274 case X86ISD::VPERMILP:
3275 case X86ISD::VPERMI:
3276 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3280 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3281 SDValue V1, SDValue V2, unsigned TargetMask,
3282 SelectionDAG &DAG) {
3284 default: llvm_unreachable("Unknown x86 shuffle node");
3285 case X86ISD::PALIGNR:
3287 case X86ISD::VPERM2X128:
3288 return DAG.getNode(Opc, dl, VT, V1, V2,
3289 DAG.getConstant(TargetMask, MVT::i8));
3293 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3294 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3296 default: llvm_unreachable("Unknown x86 shuffle node");
3297 case X86ISD::MOVLHPS:
3298 case X86ISD::MOVLHPD:
3299 case X86ISD::MOVHLPS:
3300 case X86ISD::MOVLPS:
3301 case X86ISD::MOVLPD:
3304 case X86ISD::UNPCKL:
3305 case X86ISD::UNPCKH:
3306 return DAG.getNode(Opc, dl, VT, V1, V2);
3310 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3311 MachineFunction &MF = DAG.getMachineFunction();
3312 const X86RegisterInfo *RegInfo =
3313 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3314 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3315 int ReturnAddrIndex = FuncInfo->getRAIndex();
3317 if (ReturnAddrIndex == 0) {
3318 // Set up a frame object for the return address.
3319 unsigned SlotSize = RegInfo->getSlotSize();
3320 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3323 FuncInfo->setRAIndex(ReturnAddrIndex);
3326 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3329 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3330 bool hasSymbolicDisplacement) {
3331 // Offset should fit into 32 bit immediate field.
3332 if (!isInt<32>(Offset))
3335 // If we don't have a symbolic displacement - we don't have any extra
3337 if (!hasSymbolicDisplacement)
3340 // FIXME: Some tweaks might be needed for medium code model.
3341 if (M != CodeModel::Small && M != CodeModel::Kernel)
3344 // For small code model we assume that latest object is 16MB before end of 31
3345 // bits boundary. We may also accept pretty large negative constants knowing
3346 // that all objects are in the positive half of address space.
3347 if (M == CodeModel::Small && Offset < 16*1024*1024)
3350 // For kernel code model we know that all object resist in the negative half
3351 // of 32bits address space. We may not accept negative offsets, since they may
3352 // be just off and we may accept pretty large positive ones.
3353 if (M == CodeModel::Kernel && Offset > 0)
3359 /// isCalleePop - Determines whether the callee is required to pop its
3360 /// own arguments. Callee pop is necessary to support tail calls.
3361 bool X86::isCalleePop(CallingConv::ID CallingConv,
3362 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3366 switch (CallingConv) {
3369 case CallingConv::X86_StdCall:
3371 case CallingConv::X86_FastCall:
3373 case CallingConv::X86_ThisCall:
3375 case CallingConv::Fast:
3377 case CallingConv::GHC:
3379 case CallingConv::HiPE:
3384 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3385 /// specific condition code, returning the condition code and the LHS/RHS of the
3386 /// comparison to make.
3387 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3388 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3390 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3391 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3392 // X > -1 -> X == 0, jump !sign.
3393 RHS = DAG.getConstant(0, RHS.getValueType());
3394 return X86::COND_NS;
3396 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3397 // X < 0 -> X == 0, jump on sign.
3400 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3402 RHS = DAG.getConstant(0, RHS.getValueType());
3403 return X86::COND_LE;
3407 switch (SetCCOpcode) {
3408 default: llvm_unreachable("Invalid integer condition!");
3409 case ISD::SETEQ: return X86::COND_E;
3410 case ISD::SETGT: return X86::COND_G;
3411 case ISD::SETGE: return X86::COND_GE;
3412 case ISD::SETLT: return X86::COND_L;
3413 case ISD::SETLE: return X86::COND_LE;
3414 case ISD::SETNE: return X86::COND_NE;
3415 case ISD::SETULT: return X86::COND_B;
3416 case ISD::SETUGT: return X86::COND_A;
3417 case ISD::SETULE: return X86::COND_BE;
3418 case ISD::SETUGE: return X86::COND_AE;
3422 // First determine if it is required or is profitable to flip the operands.
3424 // If LHS is a foldable load, but RHS is not, flip the condition.
3425 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3426 !ISD::isNON_EXTLoad(RHS.getNode())) {
3427 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3428 std::swap(LHS, RHS);
3431 switch (SetCCOpcode) {
3437 std::swap(LHS, RHS);
3441 // On a floating point condition, the flags are set as follows:
3443 // 0 | 0 | 0 | X > Y
3444 // 0 | 0 | 1 | X < Y
3445 // 1 | 0 | 0 | X == Y
3446 // 1 | 1 | 1 | unordered
3447 switch (SetCCOpcode) {
3448 default: llvm_unreachable("Condcode should be pre-legalized away");
3450 case ISD::SETEQ: return X86::COND_E;
3451 case ISD::SETOLT: // flipped
3453 case ISD::SETGT: return X86::COND_A;
3454 case ISD::SETOLE: // flipped
3456 case ISD::SETGE: return X86::COND_AE;
3457 case ISD::SETUGT: // flipped
3459 case ISD::SETLT: return X86::COND_B;
3460 case ISD::SETUGE: // flipped
3462 case ISD::SETLE: return X86::COND_BE;
3464 case ISD::SETNE: return X86::COND_NE;
3465 case ISD::SETUO: return X86::COND_P;
3466 case ISD::SETO: return X86::COND_NP;
3468 case ISD::SETUNE: return X86::COND_INVALID;
3472 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3473 /// code. Current x86 isa includes the following FP cmov instructions:
3474 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3475 static bool hasFPCMov(unsigned X86CC) {
3491 /// isFPImmLegal - Returns true if the target can instruction select the
3492 /// specified FP immediate natively. If false, the legalizer will
3493 /// materialize the FP immediate as a load from a constant pool.
3494 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3495 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3496 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3502 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3503 /// the specified range (L, H].
3504 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3505 return (Val < 0) || (Val >= Low && Val < Hi);
3508 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3509 /// specified value.
3510 static bool isUndefOrEqual(int Val, int CmpVal) {
3511 return (Val < 0 || Val == CmpVal);
3514 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3515 /// from position Pos and ending in Pos+Size, falls within the specified
3516 /// sequential range (L, L+Pos]. or is undef.
3517 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3518 unsigned Pos, unsigned Size, int Low) {
3519 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3520 if (!isUndefOrEqual(Mask[i], Low))
3525 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3526 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3527 /// the second operand.
3528 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3529 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3530 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3531 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3532 return (Mask[0] < 2 && Mask[1] < 2);
3536 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3537 /// is suitable for input to PSHUFHW.
3538 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3539 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3542 // Lower quadword copied in order or undef.
3543 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3546 // Upper quadword shuffled.
3547 for (unsigned i = 4; i != 8; ++i)
3548 if (!isUndefOrInRange(Mask[i], 4, 8))
3551 if (VT == MVT::v16i16) {
3552 // Lower quadword copied in order or undef.
3553 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3556 // Upper quadword shuffled.
3557 for (unsigned i = 12; i != 16; ++i)
3558 if (!isUndefOrInRange(Mask[i], 12, 16))
3565 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3566 /// is suitable for input to PSHUFLW.
3567 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3568 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3571 // Upper quadword copied in order.
3572 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3575 // Lower quadword shuffled.
3576 for (unsigned i = 0; i != 4; ++i)
3577 if (!isUndefOrInRange(Mask[i], 0, 4))
3580 if (VT == MVT::v16i16) {
3581 // Upper quadword copied in order.
3582 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3585 // Lower quadword shuffled.
3586 for (unsigned i = 8; i != 12; ++i)
3587 if (!isUndefOrInRange(Mask[i], 8, 12))
3594 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3595 /// is suitable for input to PALIGNR.
3596 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3597 const X86Subtarget *Subtarget) {
3598 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3599 (VT.is256BitVector() && !Subtarget->hasInt256()))
3602 unsigned NumElts = VT.getVectorNumElements();
3603 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3604 unsigned NumLaneElts = NumElts/NumLanes;
3606 // Do not handle 64-bit element shuffles with palignr.
3607 if (NumLaneElts == 2)
3610 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3612 for (i = 0; i != NumLaneElts; ++i) {
3617 // Lane is all undef, go to next lane
3618 if (i == NumLaneElts)
3621 int Start = Mask[i+l];
3623 // Make sure its in this lane in one of the sources
3624 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3625 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3628 // If not lane 0, then we must match lane 0
3629 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3632 // Correct second source to be contiguous with first source
3633 if (Start >= (int)NumElts)
3634 Start -= NumElts - NumLaneElts;
3636 // Make sure we're shifting in the right direction.
3637 if (Start <= (int)(i+l))
3642 // Check the rest of the elements to see if they are consecutive.
3643 for (++i; i != NumLaneElts; ++i) {
3644 int Idx = Mask[i+l];
3646 // Make sure its in this lane
3647 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3648 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3651 // If not lane 0, then we must match lane 0
3652 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3655 if (Idx >= (int)NumElts)
3656 Idx -= NumElts - NumLaneElts;
3658 if (!isUndefOrEqual(Idx, Start+i))
3667 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3668 /// the two vector operands have swapped position.
3669 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3670 unsigned NumElems) {
3671 for (unsigned i = 0; i != NumElems; ++i) {
3675 else if (idx < (int)NumElems)
3676 Mask[i] = idx + NumElems;
3678 Mask[i] = idx - NumElems;
3682 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3683 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3684 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3685 /// reverse of what x86 shuffles want.
3686 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3688 unsigned NumElems = VT.getVectorNumElements();
3689 unsigned NumLanes = VT.getSizeInBits()/128;
3690 unsigned NumLaneElems = NumElems/NumLanes;
3692 if (NumLaneElems != 2 && NumLaneElems != 4)
3695 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3696 bool symetricMaskRequired =
3697 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3699 // VSHUFPSY divides the resulting vector into 4 chunks.
3700 // The sources are also splitted into 4 chunks, and each destination
3701 // chunk must come from a different source chunk.
3703 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3704 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3706 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3707 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3709 // VSHUFPDY divides the resulting vector into 4 chunks.
3710 // The sources are also splitted into 4 chunks, and each destination
3711 // chunk must come from a different source chunk.
3713 // SRC1 => X3 X2 X1 X0
3714 // SRC2 => Y3 Y2 Y1 Y0
3716 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3718 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3719 unsigned HalfLaneElems = NumLaneElems/2;
3720 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3721 for (unsigned i = 0; i != NumLaneElems; ++i) {
3722 int Idx = Mask[i+l];
3723 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3724 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3726 // For VSHUFPSY, the mask of the second half must be the same as the
3727 // first but with the appropriate offsets. This works in the same way as
3728 // VPERMILPS works with masks.
3729 if (!symetricMaskRequired || Idx < 0)
3731 if (MaskVal[i] < 0) {
3732 MaskVal[i] = Idx - l;
3735 if ((signed)(Idx - l) != MaskVal[i])
3743 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3744 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3745 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3746 if (!VT.is128BitVector())
3749 unsigned NumElems = VT.getVectorNumElements();
3754 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3755 return isUndefOrEqual(Mask[0], 6) &&
3756 isUndefOrEqual(Mask[1], 7) &&
3757 isUndefOrEqual(Mask[2], 2) &&
3758 isUndefOrEqual(Mask[3], 3);
3761 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3762 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3764 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3765 if (!VT.is128BitVector())
3768 unsigned NumElems = VT.getVectorNumElements();
3773 return isUndefOrEqual(Mask[0], 2) &&
3774 isUndefOrEqual(Mask[1], 3) &&
3775 isUndefOrEqual(Mask[2], 2) &&
3776 isUndefOrEqual(Mask[3], 3);
3779 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3780 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3781 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3782 if (!VT.is128BitVector())
3785 unsigned NumElems = VT.getVectorNumElements();
3787 if (NumElems != 2 && NumElems != 4)
3790 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3791 if (!isUndefOrEqual(Mask[i], i + NumElems))
3794 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3795 if (!isUndefOrEqual(Mask[i], i))
3801 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3802 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3803 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3804 if (!VT.is128BitVector())
3807 unsigned NumElems = VT.getVectorNumElements();
3809 if (NumElems != 2 && NumElems != 4)
3812 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3813 if (!isUndefOrEqual(Mask[i], i))
3816 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3817 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3824 // Some special combinations that can be optimized.
3827 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3828 SelectionDAG &DAG) {
3829 MVT VT = SVOp->getSimpleValueType(0);
3832 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3835 ArrayRef<int> Mask = SVOp->getMask();
3837 // These are the special masks that may be optimized.
3838 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3839 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3840 bool MatchEvenMask = true;
3841 bool MatchOddMask = true;
3842 for (int i=0; i<8; ++i) {
3843 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3844 MatchEvenMask = false;
3845 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3846 MatchOddMask = false;
3849 if (!MatchEvenMask && !MatchOddMask)
3852 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3854 SDValue Op0 = SVOp->getOperand(0);
3855 SDValue Op1 = SVOp->getOperand(1);
3857 if (MatchEvenMask) {
3858 // Shift the second operand right to 32 bits.
3859 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3860 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3862 // Shift the first operand left to 32 bits.
3863 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3864 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3866 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3867 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3870 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3871 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3872 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3873 bool HasInt256, bool V2IsSplat = false) {
3875 assert(VT.getSizeInBits() >= 128 &&
3876 "Unsupported vector type for unpckl");
3878 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3880 unsigned NumOf256BitLanes;
3881 unsigned NumElts = VT.getVectorNumElements();
3882 if (VT.is256BitVector()) {
3883 if (NumElts != 4 && NumElts != 8 &&
3884 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3887 NumOf256BitLanes = 1;
3888 } else if (VT.is512BitVector()) {
3889 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3890 "Unsupported vector type for unpckh");
3892 NumOf256BitLanes = 2;
3895 NumOf256BitLanes = 1;
3898 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3899 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3901 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3902 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3903 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3904 int BitI = Mask[l256*NumEltsInStride+l+i];
3905 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3906 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3908 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3910 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3918 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3919 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3920 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3921 bool HasInt256, bool V2IsSplat = false) {
3922 assert(VT.getSizeInBits() >= 128 &&
3923 "Unsupported vector type for unpckh");
3925 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3927 unsigned NumOf256BitLanes;
3928 unsigned NumElts = VT.getVectorNumElements();
3929 if (VT.is256BitVector()) {
3930 if (NumElts != 4 && NumElts != 8 &&
3931 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3934 NumOf256BitLanes = 1;
3935 } else if (VT.is512BitVector()) {
3936 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3937 "Unsupported vector type for unpckh");
3939 NumOf256BitLanes = 2;
3942 NumOf256BitLanes = 1;
3945 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3946 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3948 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3949 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3950 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3951 int BitI = Mask[l256*NumEltsInStride+l+i];
3952 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3953 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3955 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3957 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3965 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3966 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3968 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3969 unsigned NumElts = VT.getVectorNumElements();
3970 bool Is256BitVec = VT.is256BitVector();
3972 if (VT.is512BitVector())
3974 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3975 "Unsupported vector type for unpckh");
3977 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3978 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3981 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3982 // FIXME: Need a better way to get rid of this, there's no latency difference
3983 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3984 // the former later. We should also remove the "_undef" special mask.
3985 if (NumElts == 4 && Is256BitVec)
3988 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3989 // independently on 128-bit lanes.
3990 unsigned NumLanes = VT.getSizeInBits()/128;
3991 unsigned NumLaneElts = NumElts/NumLanes;
3993 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
3994 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3995 int BitI = Mask[l+i];
3996 int BitI1 = Mask[l+i+1];
3998 if (!isUndefOrEqual(BitI, j))
4000 if (!isUndefOrEqual(BitI1, j))
4008 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4009 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4011 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4012 unsigned NumElts = VT.getVectorNumElements();
4014 if (VT.is512BitVector())
4017 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4018 "Unsupported vector type for unpckh");
4020 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4021 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4024 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4025 // independently on 128-bit lanes.
4026 unsigned NumLanes = VT.getSizeInBits()/128;
4027 unsigned NumLaneElts = NumElts/NumLanes;
4029 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4030 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4031 int BitI = Mask[l+i];
4032 int BitI1 = Mask[l+i+1];
4033 if (!isUndefOrEqual(BitI, j))
4035 if (!isUndefOrEqual(BitI1, j))
4042 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4043 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4044 /// MOVSD, and MOVD, i.e. setting the lowest element.
4045 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4046 if (VT.getVectorElementType().getSizeInBits() < 32)
4048 if (!VT.is128BitVector())
4051 unsigned NumElts = VT.getVectorNumElements();
4053 if (!isUndefOrEqual(Mask[0], NumElts))
4056 for (unsigned i = 1; i != NumElts; ++i)
4057 if (!isUndefOrEqual(Mask[i], i))
4063 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4064 /// as permutations between 128-bit chunks or halves. As an example: this
4066 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4067 /// The first half comes from the second half of V1 and the second half from the
4068 /// the second half of V2.
4069 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4070 if (!HasFp256 || !VT.is256BitVector())
4073 // The shuffle result is divided into half A and half B. In total the two
4074 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4075 // B must come from C, D, E or F.
4076 unsigned HalfSize = VT.getVectorNumElements()/2;
4077 bool MatchA = false, MatchB = false;
4079 // Check if A comes from one of C, D, E, F.
4080 for (unsigned Half = 0; Half != 4; ++Half) {
4081 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4087 // Check if B comes from one of C, D, E, F.
4088 for (unsigned Half = 0; Half != 4; ++Half) {
4089 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4095 return MatchA && MatchB;
4098 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4099 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4100 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4101 MVT VT = SVOp->getSimpleValueType(0);
4103 unsigned HalfSize = VT.getVectorNumElements()/2;
4105 unsigned FstHalf = 0, SndHalf = 0;
4106 for (unsigned i = 0; i < HalfSize; ++i) {
4107 if (SVOp->getMaskElt(i) > 0) {
4108 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4112 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4113 if (SVOp->getMaskElt(i) > 0) {
4114 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4119 return (FstHalf | (SndHalf << 4));
4122 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4123 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4124 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4128 unsigned NumElts = VT.getVectorNumElements();
4130 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4131 for (unsigned i = 0; i != NumElts; ++i) {
4134 Imm8 |= Mask[i] << (i*2);
4139 unsigned LaneSize = 4;
4140 SmallVector<int, 4> MaskVal(LaneSize, -1);
4142 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4143 for (unsigned i = 0; i != LaneSize; ++i) {
4144 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4148 if (MaskVal[i] < 0) {
4149 MaskVal[i] = Mask[i+l] - l;
4150 Imm8 |= MaskVal[i] << (i*2);
4153 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4160 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4162 /// Note that VPERMIL mask matching is different depending whether theunderlying
4163 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4164 /// to the same elements of the low, but to the higher half of the source.
4165 /// In VPERMILPD the two lanes could be shuffled independently of each other
4166 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4167 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4168 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4169 if (VT.getSizeInBits() < 256 || EltSize < 32)
4171 bool symetricMaskRequired = (EltSize == 32);
4172 unsigned NumElts = VT.getVectorNumElements();
4174 unsigned NumLanes = VT.getSizeInBits()/128;
4175 unsigned LaneSize = NumElts/NumLanes;
4176 // 2 or 4 elements in one lane
4178 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4179 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4180 for (unsigned i = 0; i != LaneSize; ++i) {
4181 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4183 if (symetricMaskRequired) {
4184 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4185 ExpectedMaskVal[i] = Mask[i+l] - l;
4188 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4196 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4197 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4198 /// element of vector 2 and the other elements to come from vector 1 in order.
4199 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4200 bool V2IsSplat = false, bool V2IsUndef = false) {
4201 if (!VT.is128BitVector())
4204 unsigned NumOps = VT.getVectorNumElements();
4205 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4208 if (!isUndefOrEqual(Mask[0], 0))
4211 for (unsigned i = 1; i != NumOps; ++i)
4212 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4213 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4214 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4220 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4221 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4222 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4223 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4224 const X86Subtarget *Subtarget) {
4225 if (!Subtarget->hasSSE3())
4228 unsigned NumElems = VT.getVectorNumElements();
4230 if ((VT.is128BitVector() && NumElems != 4) ||
4231 (VT.is256BitVector() && NumElems != 8) ||
4232 (VT.is512BitVector() && NumElems != 16))
4235 // "i+1" is the value the indexed mask element must have
4236 for (unsigned i = 0; i != NumElems; i += 2)
4237 if (!isUndefOrEqual(Mask[i], i+1) ||
4238 !isUndefOrEqual(Mask[i+1], i+1))
4244 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4245 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4246 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4247 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4248 const X86Subtarget *Subtarget) {
4249 if (!Subtarget->hasSSE3())
4252 unsigned NumElems = VT.getVectorNumElements();
4254 if ((VT.is128BitVector() && NumElems != 4) ||
4255 (VT.is256BitVector() && NumElems != 8) ||
4256 (VT.is512BitVector() && NumElems != 16))
4259 // "i" is the value the indexed mask element must have
4260 for (unsigned i = 0; i != NumElems; i += 2)
4261 if (!isUndefOrEqual(Mask[i], i) ||
4262 !isUndefOrEqual(Mask[i+1], i))
4268 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4269 /// specifies a shuffle of elements that is suitable for input to 256-bit
4270 /// version of MOVDDUP.
4271 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4272 if (!HasFp256 || !VT.is256BitVector())
4275 unsigned NumElts = VT.getVectorNumElements();
4279 for (unsigned i = 0; i != NumElts/2; ++i)
4280 if (!isUndefOrEqual(Mask[i], 0))
4282 for (unsigned i = NumElts/2; i != NumElts; ++i)
4283 if (!isUndefOrEqual(Mask[i], NumElts/2))
4288 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4289 /// specifies a shuffle of elements that is suitable for input to 128-bit
4290 /// version of MOVDDUP.
4291 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4292 if (!VT.is128BitVector())
4295 unsigned e = VT.getVectorNumElements() / 2;
4296 for (unsigned i = 0; i != e; ++i)
4297 if (!isUndefOrEqual(Mask[i], i))
4299 for (unsigned i = 0; i != e; ++i)
4300 if (!isUndefOrEqual(Mask[e+i], i))
4305 /// isVEXTRACTIndex - Return true if the specified
4306 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4307 /// suitable for instruction that extract 128 or 256 bit vectors
4308 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4309 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4310 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4313 // The index should be aligned on a vecWidth-bit boundary.
4315 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4317 MVT VT = N->getSimpleValueType(0);
4318 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4319 bool Result = (Index * ElSize) % vecWidth == 0;
4324 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4325 /// operand specifies a subvector insert that is suitable for input to
4326 /// insertion of 128 or 256-bit subvectors
4327 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4328 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4329 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4331 // The index should be aligned on a vecWidth-bit boundary.
4333 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4335 MVT VT = N->getSimpleValueType(0);
4336 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4337 bool Result = (Index * ElSize) % vecWidth == 0;
4342 bool X86::isVINSERT128Index(SDNode *N) {
4343 return isVINSERTIndex(N, 128);
4346 bool X86::isVINSERT256Index(SDNode *N) {
4347 return isVINSERTIndex(N, 256);
4350 bool X86::isVEXTRACT128Index(SDNode *N) {
4351 return isVEXTRACTIndex(N, 128);
4354 bool X86::isVEXTRACT256Index(SDNode *N) {
4355 return isVEXTRACTIndex(N, 256);
4358 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4359 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4360 /// Handles 128-bit and 256-bit.
4361 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4362 MVT VT = N->getSimpleValueType(0);
4364 assert((VT.getSizeInBits() >= 128) &&
4365 "Unsupported vector type for PSHUF/SHUFP");
4367 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4368 // independently on 128-bit lanes.
4369 unsigned NumElts = VT.getVectorNumElements();
4370 unsigned NumLanes = VT.getSizeInBits()/128;
4371 unsigned NumLaneElts = NumElts/NumLanes;
4373 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4374 "Only supports 2, 4 or 8 elements per lane");
4376 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4378 for (unsigned i = 0; i != NumElts; ++i) {
4379 int Elt = N->getMaskElt(i);
4380 if (Elt < 0) continue;
4381 Elt &= NumLaneElts - 1;
4382 unsigned ShAmt = (i << Shift) % 8;
4383 Mask |= Elt << ShAmt;
4389 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4390 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4391 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4392 MVT VT = N->getSimpleValueType(0);
4394 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4395 "Unsupported vector type for PSHUFHW");
4397 unsigned NumElts = VT.getVectorNumElements();
4400 for (unsigned l = 0; l != NumElts; l += 8) {
4401 // 8 nodes per lane, but we only care about the last 4.
4402 for (unsigned i = 0; i < 4; ++i) {
4403 int Elt = N->getMaskElt(l+i+4);
4404 if (Elt < 0) continue;
4405 Elt &= 0x3; // only 2-bits.
4406 Mask |= Elt << (i * 2);
4413 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4414 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4415 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4416 MVT VT = N->getSimpleValueType(0);
4418 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4419 "Unsupported vector type for PSHUFHW");
4421 unsigned NumElts = VT.getVectorNumElements();
4424 for (unsigned l = 0; l != NumElts; l += 8) {
4425 // 8 nodes per lane, but we only care about the first 4.
4426 for (unsigned i = 0; i < 4; ++i) {
4427 int Elt = N->getMaskElt(l+i);
4428 if (Elt < 0) continue;
4429 Elt &= 0x3; // only 2-bits
4430 Mask |= Elt << (i * 2);
4437 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4438 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4439 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4440 MVT VT = SVOp->getSimpleValueType(0);
4441 unsigned EltSize = VT.is512BitVector() ? 1 :
4442 VT.getVectorElementType().getSizeInBits() >> 3;
4444 unsigned NumElts = VT.getVectorNumElements();
4445 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4446 unsigned NumLaneElts = NumElts/NumLanes;
4450 for (i = 0; i != NumElts; ++i) {
4451 Val = SVOp->getMaskElt(i);
4455 if (Val >= (int)NumElts)
4456 Val -= NumElts - NumLaneElts;
4458 assert(Val - i > 0 && "PALIGNR imm should be positive");
4459 return (Val - i) * EltSize;
4462 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4463 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4464 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4465 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4468 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4470 MVT VecVT = N->getOperand(0).getSimpleValueType();
4471 MVT ElVT = VecVT.getVectorElementType();
4473 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4474 return Index / NumElemsPerChunk;
4477 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4478 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4479 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4480 llvm_unreachable("Illegal insert subvector for VINSERT");
4483 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4485 MVT VecVT = N->getSimpleValueType(0);
4486 MVT ElVT = VecVT.getVectorElementType();
4488 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4489 return Index / NumElemsPerChunk;
4492 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4493 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4494 /// and VINSERTI128 instructions.
4495 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4496 return getExtractVEXTRACTImmediate(N, 128);
4499 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4500 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4501 /// and VINSERTI64x4 instructions.
4502 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4503 return getExtractVEXTRACTImmediate(N, 256);
4506 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4507 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4508 /// and VINSERTI128 instructions.
4509 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4510 return getInsertVINSERTImmediate(N, 128);
4513 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4514 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4515 /// and VINSERTI64x4 instructions.
4516 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4517 return getInsertVINSERTImmediate(N, 256);
4520 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4522 bool X86::isZeroNode(SDValue Elt) {
4523 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4524 return CN->isNullValue();
4525 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4526 return CFP->getValueAPF().isPosZero();
4530 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4531 /// their permute mask.
4532 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4533 SelectionDAG &DAG) {
4534 MVT VT = SVOp->getSimpleValueType(0);
4535 unsigned NumElems = VT.getVectorNumElements();
4536 SmallVector<int, 8> MaskVec;
4538 for (unsigned i = 0; i != NumElems; ++i) {
4539 int Idx = SVOp->getMaskElt(i);
4541 if (Idx < (int)NumElems)
4546 MaskVec.push_back(Idx);
4548 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4549 SVOp->getOperand(0), &MaskVec[0]);
4552 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4553 /// match movhlps. The lower half elements should come from upper half of
4554 /// V1 (and in order), and the upper half elements should come from the upper
4555 /// half of V2 (and in order).
4556 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4557 if (!VT.is128BitVector())
4559 if (VT.getVectorNumElements() != 4)
4561 for (unsigned i = 0, e = 2; i != e; ++i)
4562 if (!isUndefOrEqual(Mask[i], i+2))
4564 for (unsigned i = 2; i != 4; ++i)
4565 if (!isUndefOrEqual(Mask[i], i+4))
4570 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4571 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4573 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4574 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4576 N = N->getOperand(0).getNode();
4577 if (!ISD::isNON_EXTLoad(N))
4580 *LD = cast<LoadSDNode>(N);
4584 // Test whether the given value is a vector value which will be legalized
4586 static bool WillBeConstantPoolLoad(SDNode *N) {
4587 if (N->getOpcode() != ISD::BUILD_VECTOR)
4590 // Check for any non-constant elements.
4591 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4592 switch (N->getOperand(i).getNode()->getOpcode()) {
4594 case ISD::ConstantFP:
4601 // Vectors of all-zeros and all-ones are materialized with special
4602 // instructions rather than being loaded.
4603 return !ISD::isBuildVectorAllZeros(N) &&
4604 !ISD::isBuildVectorAllOnes(N);
4607 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4608 /// match movlp{s|d}. The lower half elements should come from lower half of
4609 /// V1 (and in order), and the upper half elements should come from the upper
4610 /// half of V2 (and in order). And since V1 will become the source of the
4611 /// MOVLP, it must be either a vector load or a scalar load to vector.
4612 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4613 ArrayRef<int> Mask, MVT VT) {
4614 if (!VT.is128BitVector())
4617 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4619 // Is V2 is a vector load, don't do this transformation. We will try to use
4620 // load folding shufps op.
4621 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4624 unsigned NumElems = VT.getVectorNumElements();
4626 if (NumElems != 2 && NumElems != 4)
4628 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4629 if (!isUndefOrEqual(Mask[i], i))
4631 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4632 if (!isUndefOrEqual(Mask[i], i+NumElems))
4637 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4639 static bool isSplatVector(SDNode *N) {
4640 if (N->getOpcode() != ISD::BUILD_VECTOR)
4643 SDValue SplatValue = N->getOperand(0);
4644 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4645 if (N->getOperand(i) != SplatValue)
4650 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4651 /// to an zero vector.
4652 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4653 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4654 SDValue V1 = N->getOperand(0);
4655 SDValue V2 = N->getOperand(1);
4656 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4657 for (unsigned i = 0; i != NumElems; ++i) {
4658 int Idx = N->getMaskElt(i);
4659 if (Idx >= (int)NumElems) {
4660 unsigned Opc = V2.getOpcode();
4661 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4663 if (Opc != ISD::BUILD_VECTOR ||
4664 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4666 } else if (Idx >= 0) {
4667 unsigned Opc = V1.getOpcode();
4668 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4670 if (Opc != ISD::BUILD_VECTOR ||
4671 !X86::isZeroNode(V1.getOperand(Idx)))
4678 /// getZeroVector - Returns a vector of specified type with all zero elements.
4680 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4681 SelectionDAG &DAG, SDLoc dl) {
4682 assert(VT.isVector() && "Expected a vector type");
4684 // Always build SSE zero vectors as <4 x i32> bitcasted
4685 // to their dest type. This ensures they get CSE'd.
4687 if (VT.is128BitVector()) { // SSE
4688 if (Subtarget->hasSSE2()) { // SSE2
4689 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4690 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4692 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4693 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4695 } else if (VT.is256BitVector()) { // AVX
4696 if (Subtarget->hasInt256()) { // AVX2
4697 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4698 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4699 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4700 array_lengthof(Ops));
4702 // 256-bit logic and arithmetic instructions in AVX are all
4703 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4704 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4705 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4706 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4707 array_lengthof(Ops));
4709 } else if (VT.is512BitVector()) { // AVX-512
4710 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4711 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4712 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4713 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4715 llvm_unreachable("Unexpected vector type");
4717 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4720 /// getOnesVector - Returns a vector of specified type with all bits set.
4721 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4722 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4723 /// Then bitcast to their original type, ensuring they get CSE'd.
4724 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4726 assert(VT.isVector() && "Expected a vector type");
4728 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4730 if (VT.is256BitVector()) {
4731 if (HasInt256) { // AVX2
4732 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4733 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4734 array_lengthof(Ops));
4736 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4737 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4739 } else if (VT.is128BitVector()) {
4740 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4742 llvm_unreachable("Unexpected vector type");
4744 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4747 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4748 /// that point to V2 points to its first element.
4749 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4750 for (unsigned i = 0; i != NumElems; ++i) {
4751 if (Mask[i] > (int)NumElems) {
4757 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4758 /// operation of specified width.
4759 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4761 unsigned NumElems = VT.getVectorNumElements();
4762 SmallVector<int, 8> Mask;
4763 Mask.push_back(NumElems);
4764 for (unsigned i = 1; i != NumElems; ++i)
4766 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4769 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4770 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4772 unsigned NumElems = VT.getVectorNumElements();
4773 SmallVector<int, 8> Mask;
4774 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4776 Mask.push_back(i + NumElems);
4778 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4781 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4782 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4784 unsigned NumElems = VT.getVectorNumElements();
4785 SmallVector<int, 8> Mask;
4786 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4787 Mask.push_back(i + Half);
4788 Mask.push_back(i + NumElems + Half);
4790 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4793 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4794 // a generic shuffle instruction because the target has no such instructions.
4795 // Generate shuffles which repeat i16 and i8 several times until they can be
4796 // represented by v4f32 and then be manipulated by target suported shuffles.
4797 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4798 MVT VT = V.getSimpleValueType();
4799 int NumElems = VT.getVectorNumElements();
4802 while (NumElems > 4) {
4803 if (EltNo < NumElems/2) {
4804 V = getUnpackl(DAG, dl, VT, V, V);
4806 V = getUnpackh(DAG, dl, VT, V, V);
4807 EltNo -= NumElems/2;
4814 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4815 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4816 MVT VT = V.getSimpleValueType();
4819 if (VT.is128BitVector()) {
4820 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4821 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4822 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4824 } else if (VT.is256BitVector()) {
4825 // To use VPERMILPS to splat scalars, the second half of indicies must
4826 // refer to the higher part, which is a duplication of the lower one,
4827 // because VPERMILPS can only handle in-lane permutations.
4828 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4829 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4831 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4832 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4835 llvm_unreachable("Vector size not supported");
4837 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4840 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4841 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4842 MVT SrcVT = SV->getSimpleValueType(0);
4843 SDValue V1 = SV->getOperand(0);
4846 int EltNo = SV->getSplatIndex();
4847 int NumElems = SrcVT.getVectorNumElements();
4848 bool Is256BitVec = SrcVT.is256BitVector();
4850 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4851 "Unknown how to promote splat for type");
4853 // Extract the 128-bit part containing the splat element and update
4854 // the splat element index when it refers to the higher register.
4856 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4857 if (EltNo >= NumElems/2)
4858 EltNo -= NumElems/2;
4861 // All i16 and i8 vector types can't be used directly by a generic shuffle
4862 // instruction because the target has no such instruction. Generate shuffles
4863 // which repeat i16 and i8 several times until they fit in i32, and then can
4864 // be manipulated by target suported shuffles.
4865 MVT EltVT = SrcVT.getVectorElementType();
4866 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4867 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4869 // Recreate the 256-bit vector and place the same 128-bit vector
4870 // into the low and high part. This is necessary because we want
4871 // to use VPERM* to shuffle the vectors
4873 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4876 return getLegalSplat(DAG, V1, EltNo);
4879 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4880 /// vector of zero or undef vector. This produces a shuffle where the low
4881 /// element of V2 is swizzled into the zero/undef vector, landing at element
4882 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4883 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4885 const X86Subtarget *Subtarget,
4886 SelectionDAG &DAG) {
4887 MVT VT = V2.getSimpleValueType();
4889 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4890 unsigned NumElems = VT.getVectorNumElements();
4891 SmallVector<int, 16> MaskVec;
4892 for (unsigned i = 0; i != NumElems; ++i)
4893 // If this is the insertion idx, put the low elt of V2 here.
4894 MaskVec.push_back(i == Idx ? NumElems : i);
4895 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4898 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4899 /// target specific opcode. Returns true if the Mask could be calculated.
4900 /// Sets IsUnary to true if only uses one source.
4901 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4902 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4903 unsigned NumElems = VT.getVectorNumElements();
4907 switch(N->getOpcode()) {
4909 ImmN = N->getOperand(N->getNumOperands()-1);
4910 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4912 case X86ISD::UNPCKH:
4913 DecodeUNPCKHMask(VT, Mask);
4915 case X86ISD::UNPCKL:
4916 DecodeUNPCKLMask(VT, Mask);
4918 case X86ISD::MOVHLPS:
4919 DecodeMOVHLPSMask(NumElems, Mask);
4921 case X86ISD::MOVLHPS:
4922 DecodeMOVLHPSMask(NumElems, Mask);
4924 case X86ISD::PALIGNR:
4925 ImmN = N->getOperand(N->getNumOperands()-1);
4926 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4928 case X86ISD::PSHUFD:
4929 case X86ISD::VPERMILP:
4930 ImmN = N->getOperand(N->getNumOperands()-1);
4931 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4934 case X86ISD::PSHUFHW:
4935 ImmN = N->getOperand(N->getNumOperands()-1);
4936 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4939 case X86ISD::PSHUFLW:
4940 ImmN = N->getOperand(N->getNumOperands()-1);
4941 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4944 case X86ISD::VPERMI:
4945 ImmN = N->getOperand(N->getNumOperands()-1);
4946 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4950 case X86ISD::MOVSD: {
4951 // The index 0 always comes from the first element of the second source,
4952 // this is why MOVSS and MOVSD are used in the first place. The other
4953 // elements come from the other positions of the first source vector
4954 Mask.push_back(NumElems);
4955 for (unsigned i = 1; i != NumElems; ++i) {
4960 case X86ISD::VPERM2X128:
4961 ImmN = N->getOperand(N->getNumOperands()-1);
4962 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4963 if (Mask.empty()) return false;
4965 case X86ISD::MOVDDUP:
4966 case X86ISD::MOVLHPD:
4967 case X86ISD::MOVLPD:
4968 case X86ISD::MOVLPS:
4969 case X86ISD::MOVSHDUP:
4970 case X86ISD::MOVSLDUP:
4971 // Not yet implemented
4973 default: llvm_unreachable("unknown target shuffle node");
4979 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4980 /// element of the result of the vector shuffle.
4981 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4984 return SDValue(); // Limit search depth.
4986 SDValue V = SDValue(N, 0);
4987 EVT VT = V.getValueType();
4988 unsigned Opcode = V.getOpcode();
4990 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4991 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4992 int Elt = SV->getMaskElt(Index);
4995 return DAG.getUNDEF(VT.getVectorElementType());
4997 unsigned NumElems = VT.getVectorNumElements();
4998 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4999 : SV->getOperand(1);
5000 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5003 // Recurse into target specific vector shuffles to find scalars.
5004 if (isTargetShuffle(Opcode)) {
5005 MVT ShufVT = V.getSimpleValueType();
5006 unsigned NumElems = ShufVT.getVectorNumElements();
5007 SmallVector<int, 16> ShuffleMask;
5010 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5013 int Elt = ShuffleMask[Index];
5015 return DAG.getUNDEF(ShufVT.getVectorElementType());
5017 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5019 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5023 // Actual nodes that may contain scalar elements
5024 if (Opcode == ISD::BITCAST) {
5025 V = V.getOperand(0);
5026 EVT SrcVT = V.getValueType();
5027 unsigned NumElems = VT.getVectorNumElements();
5029 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5033 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5034 return (Index == 0) ? V.getOperand(0)
5035 : DAG.getUNDEF(VT.getVectorElementType());
5037 if (V.getOpcode() == ISD::BUILD_VECTOR)
5038 return V.getOperand(Index);
5043 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5044 /// shuffle operation which come from a consecutively from a zero. The
5045 /// search can start in two different directions, from left or right.
5046 /// We count undefs as zeros until PreferredNum is reached.
5047 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5048 unsigned NumElems, bool ZerosFromLeft,
5050 unsigned PreferredNum = -1U) {
5051 unsigned NumZeros = 0;
5052 for (unsigned i = 0; i != NumElems; ++i) {
5053 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5054 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5058 if (X86::isZeroNode(Elt))
5060 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5061 NumZeros = std::min(NumZeros + 1, PreferredNum);
5069 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5070 /// correspond consecutively to elements from one of the vector operands,
5071 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5073 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5074 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5075 unsigned NumElems, unsigned &OpNum) {
5076 bool SeenV1 = false;
5077 bool SeenV2 = false;
5079 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5080 int Idx = SVOp->getMaskElt(i);
5081 // Ignore undef indicies
5085 if (Idx < (int)NumElems)
5090 // Only accept consecutive elements from the same vector
5091 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5095 OpNum = SeenV1 ? 0 : 1;
5099 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5100 /// logical left shift of a vector.
5101 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5102 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5104 SVOp->getSimpleValueType(0).getVectorNumElements();
5105 unsigned NumZeros = getNumOfConsecutiveZeros(
5106 SVOp, NumElems, false /* check zeros from right */, DAG,
5107 SVOp->getMaskElt(0));
5113 // Considering the elements in the mask that are not consecutive zeros,
5114 // check if they consecutively come from only one of the source vectors.
5116 // V1 = {X, A, B, C} 0
5118 // vector_shuffle V1, V2 <1, 2, 3, X>
5120 if (!isShuffleMaskConsecutive(SVOp,
5121 0, // Mask Start Index
5122 NumElems-NumZeros, // Mask End Index(exclusive)
5123 NumZeros, // Where to start looking in the src vector
5124 NumElems, // Number of elements in vector
5125 OpSrc)) // Which source operand ?
5130 ShVal = SVOp->getOperand(OpSrc);
5134 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5135 /// logical left shift of a vector.
5136 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5137 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5139 SVOp->getSimpleValueType(0).getVectorNumElements();
5140 unsigned NumZeros = getNumOfConsecutiveZeros(
5141 SVOp, NumElems, true /* check zeros from left */, DAG,
5142 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5148 // Considering the elements in the mask that are not consecutive zeros,
5149 // check if they consecutively come from only one of the source vectors.
5151 // 0 { A, B, X, X } = V2
5153 // vector_shuffle V1, V2 <X, X, 4, 5>
5155 if (!isShuffleMaskConsecutive(SVOp,
5156 NumZeros, // Mask Start Index
5157 NumElems, // Mask End Index(exclusive)
5158 0, // Where to start looking in the src vector
5159 NumElems, // Number of elements in vector
5160 OpSrc)) // Which source operand ?
5165 ShVal = SVOp->getOperand(OpSrc);
5169 /// isVectorShift - Returns true if the shuffle can be implemented as a
5170 /// logical left or right shift of a vector.
5171 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5172 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5173 // Although the logic below support any bitwidth size, there are no
5174 // shift instructions which handle more than 128-bit vectors.
5175 if (!SVOp->getSimpleValueType(0).is128BitVector())
5178 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5179 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5185 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5187 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5188 unsigned NumNonZero, unsigned NumZero,
5190 const X86Subtarget* Subtarget,
5191 const TargetLowering &TLI) {
5198 for (unsigned i = 0; i < 16; ++i) {
5199 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5200 if (ThisIsNonZero && First) {
5202 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5204 V = DAG.getUNDEF(MVT::v8i16);
5209 SDValue ThisElt(0, 0), LastElt(0, 0);
5210 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5211 if (LastIsNonZero) {
5212 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5213 MVT::i16, Op.getOperand(i-1));
5215 if (ThisIsNonZero) {
5216 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5217 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5218 ThisElt, DAG.getConstant(8, MVT::i8));
5220 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5224 if (ThisElt.getNode())
5225 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5226 DAG.getIntPtrConstant(i/2));
5230 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5233 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5235 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5236 unsigned NumNonZero, unsigned NumZero,
5238 const X86Subtarget* Subtarget,
5239 const TargetLowering &TLI) {
5246 for (unsigned i = 0; i < 8; ++i) {
5247 bool isNonZero = (NonZeros & (1 << i)) != 0;
5251 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5253 V = DAG.getUNDEF(MVT::v8i16);
5256 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5257 MVT::v8i16, V, Op.getOperand(i),
5258 DAG.getIntPtrConstant(i));
5265 /// getVShift - Return a vector logical shift node.
5267 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5268 unsigned NumBits, SelectionDAG &DAG,
5269 const TargetLowering &TLI, SDLoc dl) {
5270 assert(VT.is128BitVector() && "Unknown type for VShift");
5271 EVT ShVT = MVT::v2i64;
5272 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5273 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5274 return DAG.getNode(ISD::BITCAST, dl, VT,
5275 DAG.getNode(Opc, dl, ShVT, SrcOp,
5276 DAG.getConstant(NumBits,
5277 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5281 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5283 // Check if the scalar load can be widened into a vector load. And if
5284 // the address is "base + cst" see if the cst can be "absorbed" into
5285 // the shuffle mask.
5286 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5287 SDValue Ptr = LD->getBasePtr();
5288 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5290 EVT PVT = LD->getValueType(0);
5291 if (PVT != MVT::i32 && PVT != MVT::f32)
5296 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5297 FI = FINode->getIndex();
5299 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5300 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5301 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5302 Offset = Ptr.getConstantOperandVal(1);
5303 Ptr = Ptr.getOperand(0);
5308 // FIXME: 256-bit vector instructions don't require a strict alignment,
5309 // improve this code to support it better.
5310 unsigned RequiredAlign = VT.getSizeInBits()/8;
5311 SDValue Chain = LD->getChain();
5312 // Make sure the stack object alignment is at least 16 or 32.
5313 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5314 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5315 if (MFI->isFixedObjectIndex(FI)) {
5316 // Can't change the alignment. FIXME: It's possible to compute
5317 // the exact stack offset and reference FI + adjust offset instead.
5318 // If someone *really* cares about this. That's the way to implement it.
5321 MFI->setObjectAlignment(FI, RequiredAlign);
5325 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5326 // Ptr + (Offset & ~15).
5329 if ((Offset % RequiredAlign) & 3)
5331 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5333 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5334 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5336 int EltNo = (Offset - StartOffset) >> 2;
5337 unsigned NumElems = VT.getVectorNumElements();
5339 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5340 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5341 LD->getPointerInfo().getWithOffset(StartOffset),
5342 false, false, false, 0);
5344 SmallVector<int, 8> Mask;
5345 for (unsigned i = 0; i != NumElems; ++i)
5346 Mask.push_back(EltNo);
5348 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5354 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5355 /// vector of type 'VT', see if the elements can be replaced by a single large
5356 /// load which has the same value as a build_vector whose operands are 'elts'.
5358 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5360 /// FIXME: we'd also like to handle the case where the last elements are zero
5361 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5362 /// There's even a handy isZeroNode for that purpose.
5363 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5364 SDLoc &DL, SelectionDAG &DAG) {
5365 EVT EltVT = VT.getVectorElementType();
5366 unsigned NumElems = Elts.size();
5368 LoadSDNode *LDBase = NULL;
5369 unsigned LastLoadedElt = -1U;
5371 // For each element in the initializer, see if we've found a load or an undef.
5372 // If we don't find an initial load element, or later load elements are
5373 // non-consecutive, bail out.
5374 for (unsigned i = 0; i < NumElems; ++i) {
5375 SDValue Elt = Elts[i];
5377 if (!Elt.getNode() ||
5378 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5381 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5383 LDBase = cast<LoadSDNode>(Elt.getNode());
5387 if (Elt.getOpcode() == ISD::UNDEF)
5390 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5391 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5396 // If we have found an entire vector of loads and undefs, then return a large
5397 // load of the entire vector width starting at the base pointer. If we found
5398 // consecutive loads for the low half, generate a vzext_load node.
5399 if (LastLoadedElt == NumElems - 1) {
5400 SDValue NewLd = SDValue();
5401 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5402 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5403 LDBase->getPointerInfo(),
5404 LDBase->isVolatile(), LDBase->isNonTemporal(),
5405 LDBase->isInvariant(), 0);
5406 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5407 LDBase->getPointerInfo(),
5408 LDBase->isVolatile(), LDBase->isNonTemporal(),
5409 LDBase->isInvariant(), LDBase->getAlignment());
5411 if (LDBase->hasAnyUseOfValue(1)) {
5412 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5414 SDValue(NewLd.getNode(), 1));
5415 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5416 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5417 SDValue(NewLd.getNode(), 1));
5422 if (NumElems == 4 && LastLoadedElt == 1 &&
5423 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5424 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5425 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5427 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5428 array_lengthof(Ops), MVT::i64,
5429 LDBase->getPointerInfo(),
5430 LDBase->getAlignment(),
5431 false/*isVolatile*/, true/*ReadMem*/,
5434 // Make sure the newly-created LOAD is in the same position as LDBase in
5435 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5436 // update uses of LDBase's output chain to use the TokenFactor.
5437 if (LDBase->hasAnyUseOfValue(1)) {
5438 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5439 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5440 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5441 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5442 SDValue(ResNode.getNode(), 1));
5445 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5450 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5451 /// to generate a splat value for the following cases:
5452 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5453 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5454 /// a scalar load, or a constant.
5455 /// The VBROADCAST node is returned when a pattern is found,
5456 /// or SDValue() otherwise.
5457 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5458 SelectionDAG &DAG) {
5459 if (!Subtarget->hasFp256())
5462 MVT VT = Op.getSimpleValueType();
5465 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5466 "Unsupported vector type for broadcast.");
5471 switch (Op.getOpcode()) {
5473 // Unknown pattern found.
5476 case ISD::BUILD_VECTOR: {
5477 // The BUILD_VECTOR node must be a splat.
5478 if (!isSplatVector(Op.getNode()))
5481 Ld = Op.getOperand(0);
5482 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5483 Ld.getOpcode() == ISD::ConstantFP);
5485 // The suspected load node has several users. Make sure that all
5486 // of its users are from the BUILD_VECTOR node.
5487 // Constants may have multiple users.
5488 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5493 case ISD::VECTOR_SHUFFLE: {
5494 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5496 // Shuffles must have a splat mask where the first element is
5498 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5501 SDValue Sc = Op.getOperand(0);
5502 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5503 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5505 if (!Subtarget->hasInt256())
5508 // Use the register form of the broadcast instruction available on AVX2.
5509 if (VT.getSizeInBits() >= 256)
5510 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5511 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5514 Ld = Sc.getOperand(0);
5515 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5516 Ld.getOpcode() == ISD::ConstantFP);
5518 // The scalar_to_vector node and the suspected
5519 // load node must have exactly one user.
5520 // Constants may have multiple users.
5522 // AVX-512 has register version of the broadcast
5523 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5524 Ld.getValueType().getSizeInBits() >= 32;
5525 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5532 bool IsGE256 = (VT.getSizeInBits() >= 256);
5534 // Handle the broadcasting a single constant scalar from the constant pool
5535 // into a vector. On Sandybridge it is still better to load a constant vector
5536 // from the constant pool and not to broadcast it from a scalar.
5537 if (ConstSplatVal && Subtarget->hasInt256()) {
5538 EVT CVT = Ld.getValueType();
5539 assert(!CVT.isVector() && "Must not broadcast a vector type");
5540 unsigned ScalarSize = CVT.getSizeInBits();
5542 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5543 const Constant *C = 0;
5544 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5545 C = CI->getConstantIntValue();
5546 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5547 C = CF->getConstantFPValue();
5549 assert(C && "Invalid constant type");
5551 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5552 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5553 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5554 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5555 MachinePointerInfo::getConstantPool(),
5556 false, false, false, Alignment);
5558 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5562 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5563 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5565 // Handle AVX2 in-register broadcasts.
5566 if (!IsLoad && Subtarget->hasInt256() &&
5567 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5568 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5570 // The scalar source must be a normal load.
5574 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5575 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5577 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5578 // double since there is no vbroadcastsd xmm
5579 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5580 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5581 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5584 // Unsupported broadcast.
5588 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5589 MVT VT = Op.getSimpleValueType();
5591 // Skip if insert_vec_elt is not supported.
5592 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5593 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5597 unsigned NumElems = Op.getNumOperands();
5601 SmallVector<unsigned, 4> InsertIndices;
5602 SmallVector<int, 8> Mask(NumElems, -1);
5604 for (unsigned i = 0; i != NumElems; ++i) {
5605 unsigned Opc = Op.getOperand(i).getOpcode();
5607 if (Opc == ISD::UNDEF)
5610 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5611 // Quit if more than 1 elements need inserting.
5612 if (InsertIndices.size() > 1)
5615 InsertIndices.push_back(i);
5619 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5620 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5622 // Quit if extracted from vector of different type.
5623 if (ExtractedFromVec.getValueType() != VT)
5626 // Quit if non-constant index.
5627 if (!isa<ConstantSDNode>(ExtIdx))
5630 if (VecIn1.getNode() == 0)
5631 VecIn1 = ExtractedFromVec;
5632 else if (VecIn1 != ExtractedFromVec) {
5633 if (VecIn2.getNode() == 0)
5634 VecIn2 = ExtractedFromVec;
5635 else if (VecIn2 != ExtractedFromVec)
5636 // Quit if more than 2 vectors to shuffle
5640 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5642 if (ExtractedFromVec == VecIn1)
5644 else if (ExtractedFromVec == VecIn2)
5645 Mask[i] = Idx + NumElems;
5648 if (VecIn1.getNode() == 0)
5651 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5652 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5653 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5654 unsigned Idx = InsertIndices[i];
5655 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5656 DAG.getIntPtrConstant(Idx));
5662 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5664 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5666 MVT VT = Op.getSimpleValueType();
5667 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5668 "Unexpected type in LowerBUILD_VECTORvXi1!");
5671 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5672 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5673 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5674 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5675 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5676 Ops, VT.getVectorNumElements());
5679 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5680 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5681 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5682 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5683 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5684 Ops, VT.getVectorNumElements());
5687 bool AllContants = true;
5688 uint64_t Immediate = 0;
5689 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5690 SDValue In = Op.getOperand(idx);
5691 if (In.getOpcode() == ISD::UNDEF)
5693 if (!isa<ConstantSDNode>(In)) {
5694 AllContants = false;
5697 if (cast<ConstantSDNode>(In)->getZExtValue())
5698 Immediate |= (1ULL << idx);
5702 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5703 DAG.getConstant(Immediate, MVT::i16));
5704 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5705 DAG.getIntPtrConstant(0));
5708 // Splat vector (with undefs)
5709 SDValue In = Op.getOperand(0);
5710 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5711 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5712 llvm_unreachable("Unsupported predicate operation");
5715 SDValue EFLAGS, X86CC;
5716 if (In.getOpcode() == ISD::SETCC) {
5717 SDValue Op0 = In.getOperand(0);
5718 SDValue Op1 = In.getOperand(1);
5719 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5720 bool isFP = Op1.getValueType().isFloatingPoint();
5721 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5723 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5725 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5726 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5727 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5728 } else if (In.getOpcode() == X86ISD::SETCC) {
5729 X86CC = In.getOperand(0);
5730 EFLAGS = In.getOperand(1);
5739 // res = allOnes ### CMOVNE -1, %res
5742 MVT InVT = In.getSimpleValueType();
5743 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5744 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5745 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5748 if (VT == MVT::v16i1) {
5749 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5750 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5751 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5752 Cst0, Cst1, X86CC, EFLAGS);
5753 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5756 if (VT == MVT::v8i1) {
5757 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5758 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5759 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5760 Cst0, Cst1, X86CC, EFLAGS);
5761 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5762 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5764 llvm_unreachable("Unsupported predicate operation");
5768 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5771 MVT VT = Op.getSimpleValueType();
5772 MVT ExtVT = VT.getVectorElementType();
5773 unsigned NumElems = Op.getNumOperands();
5775 // Generate vectors for predicate vectors.
5776 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5777 return LowerBUILD_VECTORvXi1(Op, DAG);
5779 // Vectors containing all zeros can be matched by pxor and xorps later
5780 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5781 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5782 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5783 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5786 return getZeroVector(VT, Subtarget, DAG, dl);
5789 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5790 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5791 // vpcmpeqd on 256-bit vectors.
5792 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5793 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5796 if (!VT.is512BitVector())
5797 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5800 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5801 if (Broadcast.getNode())
5804 unsigned EVTBits = ExtVT.getSizeInBits();
5806 unsigned NumZero = 0;
5807 unsigned NumNonZero = 0;
5808 unsigned NonZeros = 0;
5809 bool IsAllConstants = true;
5810 SmallSet<SDValue, 8> Values;
5811 for (unsigned i = 0; i < NumElems; ++i) {
5812 SDValue Elt = Op.getOperand(i);
5813 if (Elt.getOpcode() == ISD::UNDEF)
5816 if (Elt.getOpcode() != ISD::Constant &&
5817 Elt.getOpcode() != ISD::ConstantFP)
5818 IsAllConstants = false;
5819 if (X86::isZeroNode(Elt))
5822 NonZeros |= (1 << i);
5827 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5828 if (NumNonZero == 0)
5829 return DAG.getUNDEF(VT);
5831 // Special case for single non-zero, non-undef, element.
5832 if (NumNonZero == 1) {
5833 unsigned Idx = countTrailingZeros(NonZeros);
5834 SDValue Item = Op.getOperand(Idx);
5836 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5837 // the value are obviously zero, truncate the value to i32 and do the
5838 // insertion that way. Only do this if the value is non-constant or if the
5839 // value is a constant being inserted into element 0. It is cheaper to do
5840 // a constant pool load than it is to do a movd + shuffle.
5841 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5842 (!IsAllConstants || Idx == 0)) {
5843 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5845 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5846 EVT VecVT = MVT::v4i32;
5847 unsigned VecElts = 4;
5849 // Truncate the value (which may itself be a constant) to i32, and
5850 // convert it to a vector with movd (S2V+shuffle to zero extend).
5851 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5852 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5853 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5855 // Now we have our 32-bit value zero extended in the low element of
5856 // a vector. If Idx != 0, swizzle it into place.
5858 SmallVector<int, 4> Mask;
5859 Mask.push_back(Idx);
5860 for (unsigned i = 1; i != VecElts; ++i)
5862 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5865 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5869 // If we have a constant or non-constant insertion into the low element of
5870 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5871 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5872 // depending on what the source datatype is.
5875 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5877 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5878 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5879 if (VT.is256BitVector() || VT.is512BitVector()) {
5880 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5881 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5882 Item, DAG.getIntPtrConstant(0));
5884 assert(VT.is128BitVector() && "Expected an SSE value type!");
5885 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5886 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5887 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5890 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5891 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5892 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5893 if (VT.is256BitVector()) {
5894 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5895 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5897 assert(VT.is128BitVector() && "Expected an SSE value type!");
5898 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5900 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5904 // Is it a vector logical left shift?
5905 if (NumElems == 2 && Idx == 1 &&
5906 X86::isZeroNode(Op.getOperand(0)) &&
5907 !X86::isZeroNode(Op.getOperand(1))) {
5908 unsigned NumBits = VT.getSizeInBits();
5909 return getVShift(true, VT,
5910 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5911 VT, Op.getOperand(1)),
5912 NumBits/2, DAG, *this, dl);
5915 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5918 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5919 // is a non-constant being inserted into an element other than the low one,
5920 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5921 // movd/movss) to move this into the low element, then shuffle it into
5923 if (EVTBits == 32) {
5924 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5926 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5927 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5928 SmallVector<int, 8> MaskVec;
5929 for (unsigned i = 0; i != NumElems; ++i)
5930 MaskVec.push_back(i == Idx ? 0 : 1);
5931 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5935 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5936 if (Values.size() == 1) {
5937 if (EVTBits == 32) {
5938 // Instead of a shuffle like this:
5939 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5940 // Check if it's possible to issue this instead.
5941 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5942 unsigned Idx = countTrailingZeros(NonZeros);
5943 SDValue Item = Op.getOperand(Idx);
5944 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5945 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5950 // A vector full of immediates; various special cases are already
5951 // handled, so this is best done with a single constant-pool load.
5955 // For AVX-length vectors, build the individual 128-bit pieces and use
5956 // shuffles to put them in place.
5957 if (VT.is256BitVector()) {
5958 SmallVector<SDValue, 32> V;
5959 for (unsigned i = 0; i != NumElems; ++i)
5960 V.push_back(Op.getOperand(i));
5962 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5964 // Build both the lower and upper subvector.
5965 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5966 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5969 // Recreate the wider vector with the lower and upper part.
5970 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5973 // Let legalizer expand 2-wide build_vectors.
5974 if (EVTBits == 64) {
5975 if (NumNonZero == 1) {
5976 // One half is zero or undef.
5977 unsigned Idx = countTrailingZeros(NonZeros);
5978 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5979 Op.getOperand(Idx));
5980 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5985 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5986 if (EVTBits == 8 && NumElems == 16) {
5987 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5989 if (V.getNode()) return V;
5992 if (EVTBits == 16 && NumElems == 8) {
5993 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5995 if (V.getNode()) return V;
5998 // If element VT is == 32 bits, turn it into a number of shuffles.
5999 SmallVector<SDValue, 8> V(NumElems);
6000 if (NumElems == 4 && NumZero > 0) {
6001 for (unsigned i = 0; i < 4; ++i) {
6002 bool isZero = !(NonZeros & (1 << i));
6004 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6006 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6009 for (unsigned i = 0; i < 2; ++i) {
6010 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6013 V[i] = V[i*2]; // Must be a zero vector.
6016 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6019 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6022 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6027 bool Reverse1 = (NonZeros & 0x3) == 2;
6028 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6032 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6033 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6035 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6038 if (Values.size() > 1 && VT.is128BitVector()) {
6039 // Check for a build vector of consecutive loads.
6040 for (unsigned i = 0; i < NumElems; ++i)
6041 V[i] = Op.getOperand(i);
6043 // Check for elements which are consecutive loads.
6044 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6048 // Check for a build vector from mostly shuffle plus few inserting.
6049 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6053 // For SSE 4.1, use insertps to put the high elements into the low element.
6054 if (getSubtarget()->hasSSE41()) {
6056 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6057 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6059 Result = DAG.getUNDEF(VT);
6061 for (unsigned i = 1; i < NumElems; ++i) {
6062 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6063 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6064 Op.getOperand(i), DAG.getIntPtrConstant(i));
6069 // Otherwise, expand into a number of unpckl*, start by extending each of
6070 // our (non-undef) elements to the full vector width with the element in the
6071 // bottom slot of the vector (which generates no code for SSE).
6072 for (unsigned i = 0; i < NumElems; ++i) {
6073 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6074 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6076 V[i] = DAG.getUNDEF(VT);
6079 // Next, we iteratively mix elements, e.g. for v4f32:
6080 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6081 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6082 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6083 unsigned EltStride = NumElems >> 1;
6084 while (EltStride != 0) {
6085 for (unsigned i = 0; i < EltStride; ++i) {
6086 // If V[i+EltStride] is undef and this is the first round of mixing,
6087 // then it is safe to just drop this shuffle: V[i] is already in the
6088 // right place, the one element (since it's the first round) being
6089 // inserted as undef can be dropped. This isn't safe for successive
6090 // rounds because they will permute elements within both vectors.
6091 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6092 EltStride == NumElems/2)
6095 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6104 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6105 // to create 256-bit vectors from two other 128-bit ones.
6106 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6108 MVT ResVT = Op.getSimpleValueType();
6110 assert((ResVT.is256BitVector() ||
6111 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6113 SDValue V1 = Op.getOperand(0);
6114 SDValue V2 = Op.getOperand(1);
6115 unsigned NumElems = ResVT.getVectorNumElements();
6116 if(ResVT.is256BitVector())
6117 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6119 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6122 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6123 assert(Op.getNumOperands() == 2);
6125 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6126 // from two other 128-bit ones.
6127 return LowerAVXCONCAT_VECTORS(Op, DAG);
6130 // Try to lower a shuffle node into a simple blend instruction.
6132 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6133 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6134 SDValue V1 = SVOp->getOperand(0);
6135 SDValue V2 = SVOp->getOperand(1);
6137 MVT VT = SVOp->getSimpleValueType(0);
6138 MVT EltVT = VT.getVectorElementType();
6139 unsigned NumElems = VT.getVectorNumElements();
6141 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6143 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6146 // Check the mask for BLEND and build the value.
6147 unsigned MaskValue = 0;
6148 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6149 unsigned NumLanes = (NumElems-1)/8 + 1;
6150 unsigned NumElemsInLane = NumElems / NumLanes;
6152 // Blend for v16i16 should be symetric for the both lanes.
6153 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6155 int SndLaneEltIdx = (NumLanes == 2) ?
6156 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6157 int EltIdx = SVOp->getMaskElt(i);
6159 if ((EltIdx < 0 || EltIdx == (int)i) &&
6160 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6163 if (((unsigned)EltIdx == (i + NumElems)) &&
6164 (SndLaneEltIdx < 0 ||
6165 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6166 MaskValue |= (1<<i);
6171 // Convert i32 vectors to floating point if it is not AVX2.
6172 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6174 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6175 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6177 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6178 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6181 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6182 DAG.getConstant(MaskValue, MVT::i32));
6183 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6186 // v8i16 shuffles - Prefer shuffles in the following order:
6187 // 1. [all] pshuflw, pshufhw, optional move
6188 // 2. [ssse3] 1 x pshufb
6189 // 3. [ssse3] 2 x pshufb + 1 x por
6190 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6192 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6193 SelectionDAG &DAG) {
6194 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6195 SDValue V1 = SVOp->getOperand(0);
6196 SDValue V2 = SVOp->getOperand(1);
6198 SmallVector<int, 8> MaskVals;
6200 // Determine if more than 1 of the words in each of the low and high quadwords
6201 // of the result come from the same quadword of one of the two inputs. Undef
6202 // mask values count as coming from any quadword, for better codegen.
6203 unsigned LoQuad[] = { 0, 0, 0, 0 };
6204 unsigned HiQuad[] = { 0, 0, 0, 0 };
6205 std::bitset<4> InputQuads;
6206 for (unsigned i = 0; i < 8; ++i) {
6207 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6208 int EltIdx = SVOp->getMaskElt(i);
6209 MaskVals.push_back(EltIdx);
6218 InputQuads.set(EltIdx / 4);
6221 int BestLoQuad = -1;
6222 unsigned MaxQuad = 1;
6223 for (unsigned i = 0; i < 4; ++i) {
6224 if (LoQuad[i] > MaxQuad) {
6226 MaxQuad = LoQuad[i];
6230 int BestHiQuad = -1;
6232 for (unsigned i = 0; i < 4; ++i) {
6233 if (HiQuad[i] > MaxQuad) {
6235 MaxQuad = HiQuad[i];
6239 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6240 // of the two input vectors, shuffle them into one input vector so only a
6241 // single pshufb instruction is necessary. If There are more than 2 input
6242 // quads, disable the next transformation since it does not help SSSE3.
6243 bool V1Used = InputQuads[0] || InputQuads[1];
6244 bool V2Used = InputQuads[2] || InputQuads[3];
6245 if (Subtarget->hasSSSE3()) {
6246 if (InputQuads.count() == 2 && V1Used && V2Used) {
6247 BestLoQuad = InputQuads[0] ? 0 : 1;
6248 BestHiQuad = InputQuads[2] ? 2 : 3;
6250 if (InputQuads.count() > 2) {
6256 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6257 // the shuffle mask. If a quad is scored as -1, that means that it contains
6258 // words from all 4 input quadwords.
6260 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6262 BestLoQuad < 0 ? 0 : BestLoQuad,
6263 BestHiQuad < 0 ? 1 : BestHiQuad
6265 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6266 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6267 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6268 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6270 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6271 // source words for the shuffle, to aid later transformations.
6272 bool AllWordsInNewV = true;
6273 bool InOrder[2] = { true, true };
6274 for (unsigned i = 0; i != 8; ++i) {
6275 int idx = MaskVals[i];
6277 InOrder[i/4] = false;
6278 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6280 AllWordsInNewV = false;
6284 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6285 if (AllWordsInNewV) {
6286 for (int i = 0; i != 8; ++i) {
6287 int idx = MaskVals[i];
6290 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6291 if ((idx != i) && idx < 4)
6293 if ((idx != i) && idx > 3)
6302 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6303 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6304 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6305 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6306 unsigned TargetMask = 0;
6307 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6308 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6309 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6310 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6311 getShufflePSHUFLWImmediate(SVOp);
6312 V1 = NewV.getOperand(0);
6313 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6317 // Promote splats to a larger type which usually leads to more efficient code.
6318 // FIXME: Is this true if pshufb is available?
6319 if (SVOp->isSplat())
6320 return PromoteSplat(SVOp, DAG);
6322 // If we have SSSE3, and all words of the result are from 1 input vector,
6323 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6324 // is present, fall back to case 4.
6325 if (Subtarget->hasSSSE3()) {
6326 SmallVector<SDValue,16> pshufbMask;
6328 // If we have elements from both input vectors, set the high bit of the
6329 // shuffle mask element to zero out elements that come from V2 in the V1
6330 // mask, and elements that come from V1 in the V2 mask, so that the two
6331 // results can be OR'd together.
6332 bool TwoInputs = V1Used && V2Used;
6333 for (unsigned i = 0; i != 8; ++i) {
6334 int EltIdx = MaskVals[i] * 2;
6335 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6336 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6337 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6338 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6340 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6341 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6342 DAG.getNode(ISD::BUILD_VECTOR, dl,
6343 MVT::v16i8, &pshufbMask[0], 16));
6345 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6347 // Calculate the shuffle mask for the second input, shuffle it, and
6348 // OR it with the first shuffled input.
6350 for (unsigned i = 0; i != 8; ++i) {
6351 int EltIdx = MaskVals[i] * 2;
6352 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6353 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6354 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6355 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6357 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6358 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6359 DAG.getNode(ISD::BUILD_VECTOR, dl,
6360 MVT::v16i8, &pshufbMask[0], 16));
6361 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6362 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6365 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6366 // and update MaskVals with new element order.
6367 std::bitset<8> InOrder;
6368 if (BestLoQuad >= 0) {
6369 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6370 for (int i = 0; i != 4; ++i) {
6371 int idx = MaskVals[i];
6374 } else if ((idx / 4) == BestLoQuad) {
6379 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6382 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6383 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6384 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6386 getShufflePSHUFLWImmediate(SVOp), DAG);
6390 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6391 // and update MaskVals with the new element order.
6392 if (BestHiQuad >= 0) {
6393 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6394 for (unsigned i = 4; i != 8; ++i) {
6395 int idx = MaskVals[i];
6398 } else if ((idx / 4) == BestHiQuad) {
6399 MaskV[i] = (idx & 3) + 4;
6403 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6406 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6407 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6408 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6410 getShufflePSHUFHWImmediate(SVOp), DAG);
6414 // In case BestHi & BestLo were both -1, which means each quadword has a word
6415 // from each of the four input quadwords, calculate the InOrder bitvector now
6416 // before falling through to the insert/extract cleanup.
6417 if (BestLoQuad == -1 && BestHiQuad == -1) {
6419 for (int i = 0; i != 8; ++i)
6420 if (MaskVals[i] < 0 || MaskVals[i] == i)
6424 // The other elements are put in the right place using pextrw and pinsrw.
6425 for (unsigned i = 0; i != 8; ++i) {
6428 int EltIdx = MaskVals[i];
6431 SDValue ExtOp = (EltIdx < 8) ?
6432 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6433 DAG.getIntPtrConstant(EltIdx)) :
6434 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6435 DAG.getIntPtrConstant(EltIdx - 8));
6436 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6437 DAG.getIntPtrConstant(i));
6442 // v16i8 shuffles - Prefer shuffles in the following order:
6443 // 1. [ssse3] 1 x pshufb
6444 // 2. [ssse3] 2 x pshufb + 1 x por
6445 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6446 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6447 const X86Subtarget* Subtarget,
6448 SelectionDAG &DAG) {
6449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6450 SDValue V1 = SVOp->getOperand(0);
6451 SDValue V2 = SVOp->getOperand(1);
6453 ArrayRef<int> MaskVals = SVOp->getMask();
6455 // Promote splats to a larger type which usually leads to more efficient code.
6456 // FIXME: Is this true if pshufb is available?
6457 if (SVOp->isSplat())
6458 return PromoteSplat(SVOp, DAG);
6460 // If we have SSSE3, case 1 is generated when all result bytes come from
6461 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6462 // present, fall back to case 3.
6464 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6465 if (Subtarget->hasSSSE3()) {
6466 SmallVector<SDValue,16> pshufbMask;
6468 // If all result elements are from one input vector, then only translate
6469 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6471 // Otherwise, we have elements from both input vectors, and must zero out
6472 // elements that come from V2 in the first mask, and V1 in the second mask
6473 // so that we can OR them together.
6474 for (unsigned i = 0; i != 16; ++i) {
6475 int EltIdx = MaskVals[i];
6476 if (EltIdx < 0 || EltIdx >= 16)
6478 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6480 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6481 DAG.getNode(ISD::BUILD_VECTOR, dl,
6482 MVT::v16i8, &pshufbMask[0], 16));
6484 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6485 // the 2nd operand if it's undefined or zero.
6486 if (V2.getOpcode() == ISD::UNDEF ||
6487 ISD::isBuildVectorAllZeros(V2.getNode()))
6490 // Calculate the shuffle mask for the second input, shuffle it, and
6491 // OR it with the first shuffled input.
6493 for (unsigned i = 0; i != 16; ++i) {
6494 int EltIdx = MaskVals[i];
6495 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6496 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6498 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6499 DAG.getNode(ISD::BUILD_VECTOR, dl,
6500 MVT::v16i8, &pshufbMask[0], 16));
6501 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6504 // No SSSE3 - Calculate in place words and then fix all out of place words
6505 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6506 // the 16 different words that comprise the two doublequadword input vectors.
6507 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6508 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6510 for (int i = 0; i != 8; ++i) {
6511 int Elt0 = MaskVals[i*2];
6512 int Elt1 = MaskVals[i*2+1];
6514 // This word of the result is all undef, skip it.
6515 if (Elt0 < 0 && Elt1 < 0)
6518 // This word of the result is already in the correct place, skip it.
6519 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6522 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6523 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6526 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6527 // using a single extract together, load it and store it.
6528 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6529 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6530 DAG.getIntPtrConstant(Elt1 / 2));
6531 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6532 DAG.getIntPtrConstant(i));
6536 // If Elt1 is defined, extract it from the appropriate source. If the
6537 // source byte is not also odd, shift the extracted word left 8 bits
6538 // otherwise clear the bottom 8 bits if we need to do an or.
6540 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6541 DAG.getIntPtrConstant(Elt1 / 2));
6542 if ((Elt1 & 1) == 0)
6543 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6545 TLI.getShiftAmountTy(InsElt.getValueType())));
6547 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6548 DAG.getConstant(0xFF00, MVT::i16));
6550 // If Elt0 is defined, extract it from the appropriate source. If the
6551 // source byte is not also even, shift the extracted word right 8 bits. If
6552 // Elt1 was also defined, OR the extracted values together before
6553 // inserting them in the result.
6555 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6556 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6557 if ((Elt0 & 1) != 0)
6558 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6560 TLI.getShiftAmountTy(InsElt0.getValueType())));
6562 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6563 DAG.getConstant(0x00FF, MVT::i16));
6564 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6567 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6568 DAG.getIntPtrConstant(i));
6570 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6573 // v32i8 shuffles - Translate to VPSHUFB if possible.
6575 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6576 const X86Subtarget *Subtarget,
6577 SelectionDAG &DAG) {
6578 MVT VT = SVOp->getSimpleValueType(0);
6579 SDValue V1 = SVOp->getOperand(0);
6580 SDValue V2 = SVOp->getOperand(1);
6582 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6584 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6585 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6586 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6588 // VPSHUFB may be generated if
6589 // (1) one of input vector is undefined or zeroinitializer.
6590 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6591 // And (2) the mask indexes don't cross the 128-bit lane.
6592 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6593 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6596 if (V1IsAllZero && !V2IsAllZero) {
6597 CommuteVectorShuffleMask(MaskVals, 32);
6600 SmallVector<SDValue, 32> pshufbMask;
6601 for (unsigned i = 0; i != 32; i++) {
6602 int EltIdx = MaskVals[i];
6603 if (EltIdx < 0 || EltIdx >= 32)
6606 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6607 // Cross lane is not allowed.
6611 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6613 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6614 DAG.getNode(ISD::BUILD_VECTOR, dl,
6615 MVT::v32i8, &pshufbMask[0], 32));
6618 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6619 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6620 /// done when every pair / quad of shuffle mask elements point to elements in
6621 /// the right sequence. e.g.
6622 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6624 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6625 SelectionDAG &DAG) {
6626 MVT VT = SVOp->getSimpleValueType(0);
6628 unsigned NumElems = VT.getVectorNumElements();
6631 switch (VT.SimpleTy) {
6632 default: llvm_unreachable("Unexpected!");
6633 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6634 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6635 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6636 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6637 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6638 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6641 SmallVector<int, 8> MaskVec;
6642 for (unsigned i = 0; i != NumElems; i += Scale) {
6644 for (unsigned j = 0; j != Scale; ++j) {
6645 int EltIdx = SVOp->getMaskElt(i+j);
6649 StartIdx = (EltIdx / Scale);
6650 if (EltIdx != (int)(StartIdx*Scale + j))
6653 MaskVec.push_back(StartIdx);
6656 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6657 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6658 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6661 /// getVZextMovL - Return a zero-extending vector move low node.
6663 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6664 SDValue SrcOp, SelectionDAG &DAG,
6665 const X86Subtarget *Subtarget, SDLoc dl) {
6666 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6667 LoadSDNode *LD = NULL;
6668 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6669 LD = dyn_cast<LoadSDNode>(SrcOp);
6671 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6673 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6674 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6675 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6676 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6677 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6679 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6680 return DAG.getNode(ISD::BITCAST, dl, VT,
6681 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6682 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6690 return DAG.getNode(ISD::BITCAST, dl, VT,
6691 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6692 DAG.getNode(ISD::BITCAST, dl,
6696 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6697 /// which could not be matched by any known target speficic shuffle
6699 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6701 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6702 if (NewOp.getNode())
6705 MVT VT = SVOp->getSimpleValueType(0);
6707 unsigned NumElems = VT.getVectorNumElements();
6708 unsigned NumLaneElems = NumElems / 2;
6711 MVT EltVT = VT.getVectorElementType();
6712 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6715 SmallVector<int, 16> Mask;
6716 for (unsigned l = 0; l < 2; ++l) {
6717 // Build a shuffle mask for the output, discovering on the fly which
6718 // input vectors to use as shuffle operands (recorded in InputUsed).
6719 // If building a suitable shuffle vector proves too hard, then bail
6720 // out with UseBuildVector set.
6721 bool UseBuildVector = false;
6722 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6723 unsigned LaneStart = l * NumLaneElems;
6724 for (unsigned i = 0; i != NumLaneElems; ++i) {
6725 // The mask element. This indexes into the input.
6726 int Idx = SVOp->getMaskElt(i+LaneStart);
6728 // the mask element does not index into any input vector.
6733 // The input vector this mask element indexes into.
6734 int Input = Idx / NumLaneElems;
6736 // Turn the index into an offset from the start of the input vector.
6737 Idx -= Input * NumLaneElems;
6739 // Find or create a shuffle vector operand to hold this input.
6741 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6742 if (InputUsed[OpNo] == Input)
6743 // This input vector is already an operand.
6745 if (InputUsed[OpNo] < 0) {
6746 // Create a new operand for this input vector.
6747 InputUsed[OpNo] = Input;
6752 if (OpNo >= array_lengthof(InputUsed)) {
6753 // More than two input vectors used! Give up on trying to create a
6754 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6755 UseBuildVector = true;
6759 // Add the mask index for the new shuffle vector.
6760 Mask.push_back(Idx + OpNo * NumLaneElems);
6763 if (UseBuildVector) {
6764 SmallVector<SDValue, 16> SVOps;
6765 for (unsigned i = 0; i != NumLaneElems; ++i) {
6766 // The mask element. This indexes into the input.
6767 int Idx = SVOp->getMaskElt(i+LaneStart);
6769 SVOps.push_back(DAG.getUNDEF(EltVT));
6773 // The input vector this mask element indexes into.
6774 int Input = Idx / NumElems;
6776 // Turn the index into an offset from the start of the input vector.
6777 Idx -= Input * NumElems;
6779 // Extract the vector element by hand.
6780 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6781 SVOp->getOperand(Input),
6782 DAG.getIntPtrConstant(Idx)));
6785 // Construct the output using a BUILD_VECTOR.
6786 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6788 } else if (InputUsed[0] < 0) {
6789 // No input vectors were used! The result is undefined.
6790 Output[l] = DAG.getUNDEF(NVT);
6792 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6793 (InputUsed[0] % 2) * NumLaneElems,
6795 // If only one input was used, use an undefined vector for the other.
6796 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6797 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6798 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6799 // At least one input vector was used. Create a new shuffle vector.
6800 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6806 // Concatenate the result back
6807 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6810 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6811 /// 4 elements, and match them with several different shuffle types.
6813 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6814 SDValue V1 = SVOp->getOperand(0);
6815 SDValue V2 = SVOp->getOperand(1);
6817 MVT VT = SVOp->getSimpleValueType(0);
6819 assert(VT.is128BitVector() && "Unsupported vector size");
6821 std::pair<int, int> Locs[4];
6822 int Mask1[] = { -1, -1, -1, -1 };
6823 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6827 for (unsigned i = 0; i != 4; ++i) {
6828 int Idx = PermMask[i];
6830 Locs[i] = std::make_pair(-1, -1);
6832 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6834 Locs[i] = std::make_pair(0, NumLo);
6838 Locs[i] = std::make_pair(1, NumHi);
6840 Mask1[2+NumHi] = Idx;
6846 if (NumLo <= 2 && NumHi <= 2) {
6847 // If no more than two elements come from either vector. This can be
6848 // implemented with two shuffles. First shuffle gather the elements.
6849 // The second shuffle, which takes the first shuffle as both of its
6850 // vector operands, put the elements into the right order.
6851 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6853 int Mask2[] = { -1, -1, -1, -1 };
6855 for (unsigned i = 0; i != 4; ++i)
6856 if (Locs[i].first != -1) {
6857 unsigned Idx = (i < 2) ? 0 : 4;
6858 Idx += Locs[i].first * 2 + Locs[i].second;
6862 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6865 if (NumLo == 3 || NumHi == 3) {
6866 // Otherwise, we must have three elements from one vector, call it X, and
6867 // one element from the other, call it Y. First, use a shufps to build an
6868 // intermediate vector with the one element from Y and the element from X
6869 // that will be in the same half in the final destination (the indexes don't
6870 // matter). Then, use a shufps to build the final vector, taking the half
6871 // containing the element from Y from the intermediate, and the other half
6874 // Normalize it so the 3 elements come from V1.
6875 CommuteVectorShuffleMask(PermMask, 4);
6879 // Find the element from V2.
6881 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6882 int Val = PermMask[HiIndex];
6889 Mask1[0] = PermMask[HiIndex];
6891 Mask1[2] = PermMask[HiIndex^1];
6893 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6896 Mask1[0] = PermMask[0];
6897 Mask1[1] = PermMask[1];
6898 Mask1[2] = HiIndex & 1 ? 6 : 4;
6899 Mask1[3] = HiIndex & 1 ? 4 : 6;
6900 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6903 Mask1[0] = HiIndex & 1 ? 2 : 0;
6904 Mask1[1] = HiIndex & 1 ? 0 : 2;
6905 Mask1[2] = PermMask[2];
6906 Mask1[3] = PermMask[3];
6911 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6914 // Break it into (shuffle shuffle_hi, shuffle_lo).
6915 int LoMask[] = { -1, -1, -1, -1 };
6916 int HiMask[] = { -1, -1, -1, -1 };
6918 int *MaskPtr = LoMask;
6919 unsigned MaskIdx = 0;
6922 for (unsigned i = 0; i != 4; ++i) {
6929 int Idx = PermMask[i];
6931 Locs[i] = std::make_pair(-1, -1);
6932 } else if (Idx < 4) {
6933 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6934 MaskPtr[LoIdx] = Idx;
6937 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6938 MaskPtr[HiIdx] = Idx;
6943 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6944 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6945 int MaskOps[] = { -1, -1, -1, -1 };
6946 for (unsigned i = 0; i != 4; ++i)
6947 if (Locs[i].first != -1)
6948 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6949 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6952 static bool MayFoldVectorLoad(SDValue V) {
6953 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6954 V = V.getOperand(0);
6956 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6957 V = V.getOperand(0);
6958 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6959 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6960 // BUILD_VECTOR (load), undef
6961 V = V.getOperand(0);
6963 return MayFoldLoad(V);
6967 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6968 MVT VT = Op.getSimpleValueType();
6970 // Canonizalize to v2f64.
6971 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6972 return DAG.getNode(ISD::BITCAST, dl, VT,
6973 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6978 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6980 SDValue V1 = Op.getOperand(0);
6981 SDValue V2 = Op.getOperand(1);
6982 MVT VT = Op.getSimpleValueType();
6984 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6986 if (HasSSE2 && VT == MVT::v2f64)
6987 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6989 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6990 return DAG.getNode(ISD::BITCAST, dl, VT,
6991 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6992 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6993 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6997 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
6998 SDValue V1 = Op.getOperand(0);
6999 SDValue V2 = Op.getOperand(1);
7000 MVT VT = Op.getSimpleValueType();
7002 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7003 "unsupported shuffle type");
7005 if (V2.getOpcode() == ISD::UNDEF)
7009 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7013 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7014 SDValue V1 = Op.getOperand(0);
7015 SDValue V2 = Op.getOperand(1);
7016 MVT VT = Op.getSimpleValueType();
7017 unsigned NumElems = VT.getVectorNumElements();
7019 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7020 // operand of these instructions is only memory, so check if there's a
7021 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7023 bool CanFoldLoad = false;
7025 // Trivial case, when V2 comes from a load.
7026 if (MayFoldVectorLoad(V2))
7029 // When V1 is a load, it can be folded later into a store in isel, example:
7030 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7032 // (MOVLPSmr addr:$src1, VR128:$src2)
7033 // So, recognize this potential and also use MOVLPS or MOVLPD
7034 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7039 if (HasSSE2 && NumElems == 2)
7040 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7043 // If we don't care about the second element, proceed to use movss.
7044 if (SVOp->getMaskElt(1) != -1)
7045 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7048 // movl and movlp will both match v2i64, but v2i64 is never matched by
7049 // movl earlier because we make it strict to avoid messing with the movlp load
7050 // folding logic (see the code above getMOVLP call). Match it here then,
7051 // this is horrible, but will stay like this until we move all shuffle
7052 // matching to x86 specific nodes. Note that for the 1st condition all
7053 // types are matched with movsd.
7055 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7056 // as to remove this logic from here, as much as possible
7057 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7058 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7059 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7062 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7064 // Invert the operand order and use SHUFPS to match it.
7065 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7066 getShuffleSHUFImmediate(SVOp), DAG);
7069 // Reduce a vector shuffle to zext.
7070 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7071 SelectionDAG &DAG) {
7072 // PMOVZX is only available from SSE41.
7073 if (!Subtarget->hasSSE41())
7076 MVT VT = Op.getSimpleValueType();
7078 // Only AVX2 support 256-bit vector integer extending.
7079 if (!Subtarget->hasInt256() && VT.is256BitVector())
7082 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7084 SDValue V1 = Op.getOperand(0);
7085 SDValue V2 = Op.getOperand(1);
7086 unsigned NumElems = VT.getVectorNumElements();
7088 // Extending is an unary operation and the element type of the source vector
7089 // won't be equal to or larger than i64.
7090 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7091 VT.getVectorElementType() == MVT::i64)
7094 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7095 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7096 while ((1U << Shift) < NumElems) {
7097 if (SVOp->getMaskElt(1U << Shift) == 1)
7100 // The maximal ratio is 8, i.e. from i8 to i64.
7105 // Check the shuffle mask.
7106 unsigned Mask = (1U << Shift) - 1;
7107 for (unsigned i = 0; i != NumElems; ++i) {
7108 int EltIdx = SVOp->getMaskElt(i);
7109 if ((i & Mask) != 0 && EltIdx != -1)
7111 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7115 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7116 MVT NeVT = MVT::getIntegerVT(NBits);
7117 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7119 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7122 // Simplify the operand as it's prepared to be fed into shuffle.
7123 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7124 if (V1.getOpcode() == ISD::BITCAST &&
7125 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7126 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7127 V1.getOperand(0).getOperand(0)
7128 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7129 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7130 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7131 ConstantSDNode *CIdx =
7132 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7133 // If it's foldable, i.e. normal load with single use, we will let code
7134 // selection to fold it. Otherwise, we will short the conversion sequence.
7135 if (CIdx && CIdx->getZExtValue() == 0 &&
7136 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7137 MVT FullVT = V.getSimpleValueType();
7138 MVT V1VT = V1.getSimpleValueType();
7139 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7140 // The "ext_vec_elt" node is wider than the result node.
7141 // In this case we should extract subvector from V.
7142 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7143 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7144 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7145 FullVT.getVectorNumElements()/Ratio);
7146 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7147 DAG.getIntPtrConstant(0));
7149 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7153 return DAG.getNode(ISD::BITCAST, DL, VT,
7154 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7158 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7159 SelectionDAG &DAG) {
7160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7161 MVT VT = Op.getSimpleValueType();
7163 SDValue V1 = Op.getOperand(0);
7164 SDValue V2 = Op.getOperand(1);
7166 if (isZeroShuffle(SVOp))
7167 return getZeroVector(VT, Subtarget, DAG, dl);
7169 // Handle splat operations
7170 if (SVOp->isSplat()) {
7171 // Use vbroadcast whenever the splat comes from a foldable load
7172 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7173 if (Broadcast.getNode())
7177 // Check integer expanding shuffles.
7178 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7179 if (NewOp.getNode())
7182 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7184 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7185 VT == MVT::v16i16 || VT == MVT::v32i8) {
7186 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7187 if (NewOp.getNode())
7188 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7189 } else if ((VT == MVT::v4i32 ||
7190 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7191 // FIXME: Figure out a cleaner way to do this.
7192 // Try to make use of movq to zero out the top part.
7193 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7194 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7195 if (NewOp.getNode()) {
7196 MVT NewVT = NewOp.getSimpleValueType();
7197 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7198 NewVT, true, false))
7199 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7200 DAG, Subtarget, dl);
7202 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7203 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7204 if (NewOp.getNode()) {
7205 MVT NewVT = NewOp.getSimpleValueType();
7206 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7207 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7208 DAG, Subtarget, dl);
7216 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7217 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7218 SDValue V1 = Op.getOperand(0);
7219 SDValue V2 = Op.getOperand(1);
7220 MVT VT = Op.getSimpleValueType();
7222 unsigned NumElems = VT.getVectorNumElements();
7223 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7224 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7225 bool V1IsSplat = false;
7226 bool V2IsSplat = false;
7227 bool HasSSE2 = Subtarget->hasSSE2();
7228 bool HasFp256 = Subtarget->hasFp256();
7229 bool HasInt256 = Subtarget->hasInt256();
7230 MachineFunction &MF = DAG.getMachineFunction();
7231 bool OptForSize = MF.getFunction()->getAttributes().
7232 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7234 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7236 if (V1IsUndef && V2IsUndef)
7237 return DAG.getUNDEF(VT);
7239 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7241 // Vector shuffle lowering takes 3 steps:
7243 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7244 // narrowing and commutation of operands should be handled.
7245 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7247 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7248 // so the shuffle can be broken into other shuffles and the legalizer can
7249 // try the lowering again.
7251 // The general idea is that no vector_shuffle operation should be left to
7252 // be matched during isel, all of them must be converted to a target specific
7255 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7256 // narrowing and commutation of operands should be handled. The actual code
7257 // doesn't include all of those, work in progress...
7258 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7259 if (NewOp.getNode())
7262 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7264 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7265 // unpckh_undef). Only use pshufd if speed is more important than size.
7266 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7267 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7268 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7269 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7271 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7272 V2IsUndef && MayFoldVectorLoad(V1))
7273 return getMOVDDup(Op, dl, V1, DAG);
7275 if (isMOVHLPS_v_undef_Mask(M, VT))
7276 return getMOVHighToLow(Op, dl, DAG);
7278 // Use to match splats
7279 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7280 (VT == MVT::v2f64 || VT == MVT::v2i64))
7281 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7283 if (isPSHUFDMask(M, VT)) {
7284 // The actual implementation will match the mask in the if above and then
7285 // during isel it can match several different instructions, not only pshufd
7286 // as its name says, sad but true, emulate the behavior for now...
7287 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7288 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7290 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7292 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7293 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7295 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7296 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7299 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7303 if (isPALIGNRMask(M, VT, Subtarget))
7304 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7305 getShufflePALIGNRImmediate(SVOp),
7308 // Check if this can be converted into a logical shift.
7309 bool isLeft = false;
7312 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7313 if (isShift && ShVal.hasOneUse()) {
7314 // If the shifted value has multiple uses, it may be cheaper to use
7315 // v_set0 + movlhps or movhlps, etc.
7316 MVT EltVT = VT.getVectorElementType();
7317 ShAmt *= EltVT.getSizeInBits();
7318 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7321 if (isMOVLMask(M, VT)) {
7322 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7323 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7324 if (!isMOVLPMask(M, VT)) {
7325 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7326 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7328 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7329 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7333 // FIXME: fold these into legal mask.
7334 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7335 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7337 if (isMOVHLPSMask(M, VT))
7338 return getMOVHighToLow(Op, dl, DAG);
7340 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7341 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7343 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7344 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7346 if (isMOVLPMask(M, VT))
7347 return getMOVLP(Op, dl, DAG, HasSSE2);
7349 if (ShouldXformToMOVHLPS(M, VT) ||
7350 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7351 return CommuteVectorShuffle(SVOp, DAG);
7354 // No better options. Use a vshldq / vsrldq.
7355 MVT EltVT = VT.getVectorElementType();
7356 ShAmt *= EltVT.getSizeInBits();
7357 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7360 bool Commuted = false;
7361 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7362 // 1,1,1,1 -> v8i16 though.
7363 V1IsSplat = isSplatVector(V1.getNode());
7364 V2IsSplat = isSplatVector(V2.getNode());
7366 // Canonicalize the splat or undef, if present, to be on the RHS.
7367 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7368 CommuteVectorShuffleMask(M, NumElems);
7370 std::swap(V1IsSplat, V2IsSplat);
7374 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7375 // Shuffling low element of v1 into undef, just return v1.
7378 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7379 // the instruction selector will not match, so get a canonical MOVL with
7380 // swapped operands to undo the commute.
7381 return getMOVL(DAG, dl, VT, V2, V1);
7384 if (isUNPCKLMask(M, VT, HasInt256))
7385 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7387 if (isUNPCKHMask(M, VT, HasInt256))
7388 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7391 // Normalize mask so all entries that point to V2 points to its first
7392 // element then try to match unpck{h|l} again. If match, return a
7393 // new vector_shuffle with the corrected mask.p
7394 SmallVector<int, 8> NewMask(M.begin(), M.end());
7395 NormalizeMask(NewMask, NumElems);
7396 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7397 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7398 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7399 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7403 // Commute is back and try unpck* again.
7404 // FIXME: this seems wrong.
7405 CommuteVectorShuffleMask(M, NumElems);
7407 std::swap(V1IsSplat, V2IsSplat);
7410 if (isUNPCKLMask(M, VT, HasInt256))
7411 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7413 if (isUNPCKHMask(M, VT, HasInt256))
7414 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7417 // Normalize the node to match x86 shuffle ops if needed
7418 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7419 return CommuteVectorShuffle(SVOp, DAG);
7421 // The checks below are all present in isShuffleMaskLegal, but they are
7422 // inlined here right now to enable us to directly emit target specific
7423 // nodes, and remove one by one until they don't return Op anymore.
7425 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7426 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7427 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7428 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7431 if (isPSHUFHWMask(M, VT, HasInt256))
7432 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7433 getShufflePSHUFHWImmediate(SVOp),
7436 if (isPSHUFLWMask(M, VT, HasInt256))
7437 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7438 getShufflePSHUFLWImmediate(SVOp),
7441 if (isSHUFPMask(M, VT))
7442 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7443 getShuffleSHUFImmediate(SVOp), DAG);
7445 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7446 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7447 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7448 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7450 //===--------------------------------------------------------------------===//
7451 // Generate target specific nodes for 128 or 256-bit shuffles only
7452 // supported in the AVX instruction set.
7455 // Handle VMOVDDUPY permutations
7456 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7457 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7459 // Handle VPERMILPS/D* permutations
7460 if (isVPERMILPMask(M, VT)) {
7461 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7462 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7463 getShuffleSHUFImmediate(SVOp), DAG);
7464 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7465 getShuffleSHUFImmediate(SVOp), DAG);
7468 // Handle VPERM2F128/VPERM2I128 permutations
7469 if (isVPERM2X128Mask(M, VT, HasFp256))
7470 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7471 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7473 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7474 if (BlendOp.getNode())
7478 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7479 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7481 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7482 VT.is512BitVector()) {
7483 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7484 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7485 SmallVector<SDValue, 16> permclMask;
7486 for (unsigned i = 0; i != NumElems; ++i) {
7487 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7490 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7491 &permclMask[0], NumElems);
7493 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7494 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7495 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7496 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7497 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7500 //===--------------------------------------------------------------------===//
7501 // Since no target specific shuffle was selected for this generic one,
7502 // lower it into other known shuffles. FIXME: this isn't true yet, but
7503 // this is the plan.
7506 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7507 if (VT == MVT::v8i16) {
7508 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7509 if (NewOp.getNode())
7513 if (VT == MVT::v16i8) {
7514 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7515 if (NewOp.getNode())
7519 if (VT == MVT::v32i8) {
7520 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7521 if (NewOp.getNode())
7525 // Handle all 128-bit wide vectors with 4 elements, and match them with
7526 // several different shuffle types.
7527 if (NumElems == 4 && VT.is128BitVector())
7528 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7530 // Handle general 256-bit shuffles
7531 if (VT.is256BitVector())
7532 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7537 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7538 MVT VT = Op.getSimpleValueType();
7541 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7544 if (VT.getSizeInBits() == 8) {
7545 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7546 Op.getOperand(0), Op.getOperand(1));
7547 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7548 DAG.getValueType(VT));
7549 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7552 if (VT.getSizeInBits() == 16) {
7553 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7554 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7556 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7557 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7558 DAG.getNode(ISD::BITCAST, dl,
7562 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7563 Op.getOperand(0), Op.getOperand(1));
7564 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7565 DAG.getValueType(VT));
7566 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7569 if (VT == MVT::f32) {
7570 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7571 // the result back to FR32 register. It's only worth matching if the
7572 // result has a single use which is a store or a bitcast to i32. And in
7573 // the case of a store, it's not worth it if the index is a constant 0,
7574 // because a MOVSSmr can be used instead, which is smaller and faster.
7575 if (!Op.hasOneUse())
7577 SDNode *User = *Op.getNode()->use_begin();
7578 if ((User->getOpcode() != ISD::STORE ||
7579 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7580 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7581 (User->getOpcode() != ISD::BITCAST ||
7582 User->getValueType(0) != MVT::i32))
7584 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7585 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7588 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7591 if (VT == MVT::i32 || VT == MVT::i64) {
7592 // ExtractPS/pextrq works with constant index.
7593 if (isa<ConstantSDNode>(Op.getOperand(1)))
7600 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7601 SelectionDAG &DAG) const {
7603 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7606 SDValue Vec = Op.getOperand(0);
7607 MVT VecVT = Vec.getSimpleValueType();
7609 // If this is a 256-bit vector result, first extract the 128-bit vector and
7610 // then extract the element from the 128-bit vector.
7611 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7612 SDValue Idx = Op.getOperand(1);
7613 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7615 // Get the 128-bit vector.
7616 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7617 MVT EltVT = VecVT.getVectorElementType();
7619 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7621 //if (IdxVal >= NumElems/2)
7622 // IdxVal -= NumElems/2;
7623 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7624 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7625 DAG.getConstant(IdxVal, MVT::i32));
7628 assert(VecVT.is128BitVector() && "Unexpected vector length");
7630 if (Subtarget->hasSSE41()) {
7631 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7636 MVT VT = Op.getSimpleValueType();
7637 // TODO: handle v16i8.
7638 if (VT.getSizeInBits() == 16) {
7639 SDValue Vec = Op.getOperand(0);
7640 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7642 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7643 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7644 DAG.getNode(ISD::BITCAST, dl,
7647 // Transform it so it match pextrw which produces a 32-bit result.
7648 MVT EltVT = MVT::i32;
7649 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7650 Op.getOperand(0), Op.getOperand(1));
7651 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7652 DAG.getValueType(VT));
7653 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7656 if (VT.getSizeInBits() == 32) {
7657 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7661 // SHUFPS the element to the lowest double word, then movss.
7662 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7663 MVT VVT = Op.getOperand(0).getSimpleValueType();
7664 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7665 DAG.getUNDEF(VVT), Mask);
7666 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7667 DAG.getIntPtrConstant(0));
7670 if (VT.getSizeInBits() == 64) {
7671 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7672 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7673 // to match extract_elt for f64.
7674 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7678 // UNPCKHPD the element to the lowest double word, then movsd.
7679 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7680 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7681 int Mask[2] = { 1, -1 };
7682 MVT VVT = Op.getOperand(0).getSimpleValueType();
7683 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7684 DAG.getUNDEF(VVT), Mask);
7685 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7686 DAG.getIntPtrConstant(0));
7692 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7693 MVT VT = Op.getSimpleValueType();
7694 MVT EltVT = VT.getVectorElementType();
7697 SDValue N0 = Op.getOperand(0);
7698 SDValue N1 = Op.getOperand(1);
7699 SDValue N2 = Op.getOperand(2);
7701 if (!VT.is128BitVector())
7704 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7705 isa<ConstantSDNode>(N2)) {
7707 if (VT == MVT::v8i16)
7708 Opc = X86ISD::PINSRW;
7709 else if (VT == MVT::v16i8)
7710 Opc = X86ISD::PINSRB;
7712 Opc = X86ISD::PINSRB;
7714 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7716 if (N1.getValueType() != MVT::i32)
7717 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7718 if (N2.getValueType() != MVT::i32)
7719 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7720 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7723 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7724 // Bits [7:6] of the constant are the source select. This will always be
7725 // zero here. The DAG Combiner may combine an extract_elt index into these
7726 // bits. For example (insert (extract, 3), 2) could be matched by putting
7727 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7728 // Bits [5:4] of the constant are the destination select. This is the
7729 // value of the incoming immediate.
7730 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7731 // combine either bitwise AND or insert of float 0.0 to set these bits.
7732 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7733 // Create this as a scalar to vector..
7734 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7735 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7738 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7739 // PINSR* works with constant index.
7746 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7747 MVT VT = Op.getSimpleValueType();
7748 MVT EltVT = VT.getVectorElementType();
7751 SDValue N0 = Op.getOperand(0);
7752 SDValue N1 = Op.getOperand(1);
7753 SDValue N2 = Op.getOperand(2);
7755 // If this is a 256-bit vector result, first extract the 128-bit vector,
7756 // insert the element into the extracted half and then place it back.
7757 if (VT.is256BitVector() || VT.is512BitVector()) {
7758 if (!isa<ConstantSDNode>(N2))
7761 // Get the desired 128-bit vector half.
7762 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7763 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7765 // Insert the element into the desired half.
7766 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7767 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7769 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7770 DAG.getConstant(IdxIn128, MVT::i32));
7772 // Insert the changed part back to the 256-bit vector
7773 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7776 if (Subtarget->hasSSE41())
7777 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7779 if (EltVT == MVT::i8)
7782 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7783 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7784 // as its second argument.
7785 if (N1.getValueType() != MVT::i32)
7786 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7787 if (N2.getValueType() != MVT::i32)
7788 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7789 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7794 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7796 MVT OpVT = Op.getSimpleValueType();
7798 // If this is a 256-bit vector result, first insert into a 128-bit
7799 // vector and then insert into the 256-bit vector.
7800 if (!OpVT.is128BitVector()) {
7801 // Insert into a 128-bit vector.
7802 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7803 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7804 OpVT.getVectorNumElements() / SizeFactor);
7806 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7808 // Insert the 128-bit vector.
7809 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7812 if (OpVT == MVT::v1i64 &&
7813 Op.getOperand(0).getValueType() == MVT::i64)
7814 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7816 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7817 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7818 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7819 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7822 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7823 // a simple subregister reference or explicit instructions to grab
7824 // upper bits of a vector.
7825 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7826 SelectionDAG &DAG) {
7828 SDValue In = Op.getOperand(0);
7829 SDValue Idx = Op.getOperand(1);
7830 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7831 MVT ResVT = Op.getSimpleValueType();
7832 MVT InVT = In.getSimpleValueType();
7834 if (Subtarget->hasFp256()) {
7835 if (ResVT.is128BitVector() &&
7836 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7837 isa<ConstantSDNode>(Idx)) {
7838 return Extract128BitVector(In, IdxVal, DAG, dl);
7840 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7841 isa<ConstantSDNode>(Idx)) {
7842 return Extract256BitVector(In, IdxVal, DAG, dl);
7848 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7849 // simple superregister reference or explicit instructions to insert
7850 // the upper bits of a vector.
7851 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7852 SelectionDAG &DAG) {
7853 if (Subtarget->hasFp256()) {
7854 SDLoc dl(Op.getNode());
7855 SDValue Vec = Op.getNode()->getOperand(0);
7856 SDValue SubVec = Op.getNode()->getOperand(1);
7857 SDValue Idx = Op.getNode()->getOperand(2);
7859 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7860 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7861 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7862 isa<ConstantSDNode>(Idx)) {
7863 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7864 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7867 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7868 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7869 isa<ConstantSDNode>(Idx)) {
7870 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7871 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7877 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7878 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7879 // one of the above mentioned nodes. It has to be wrapped because otherwise
7880 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7881 // be used to form addressing mode. These wrapped nodes will be selected
7884 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7885 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7887 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7889 unsigned char OpFlag = 0;
7890 unsigned WrapperKind = X86ISD::Wrapper;
7891 CodeModel::Model M = getTargetMachine().getCodeModel();
7893 if (Subtarget->isPICStyleRIPRel() &&
7894 (M == CodeModel::Small || M == CodeModel::Kernel))
7895 WrapperKind = X86ISD::WrapperRIP;
7896 else if (Subtarget->isPICStyleGOT())
7897 OpFlag = X86II::MO_GOTOFF;
7898 else if (Subtarget->isPICStyleStubPIC())
7899 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7901 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7903 CP->getOffset(), OpFlag);
7905 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7906 // With PIC, the address is actually $g + Offset.
7908 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7909 DAG.getNode(X86ISD::GlobalBaseReg,
7910 SDLoc(), getPointerTy()),
7917 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7918 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7920 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7922 unsigned char OpFlag = 0;
7923 unsigned WrapperKind = X86ISD::Wrapper;
7924 CodeModel::Model M = getTargetMachine().getCodeModel();
7926 if (Subtarget->isPICStyleRIPRel() &&
7927 (M == CodeModel::Small || M == CodeModel::Kernel))
7928 WrapperKind = X86ISD::WrapperRIP;
7929 else if (Subtarget->isPICStyleGOT())
7930 OpFlag = X86II::MO_GOTOFF;
7931 else if (Subtarget->isPICStyleStubPIC())
7932 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7934 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7937 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7939 // With PIC, the address is actually $g + Offset.
7941 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7942 DAG.getNode(X86ISD::GlobalBaseReg,
7943 SDLoc(), getPointerTy()),
7950 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7951 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7953 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7955 unsigned char OpFlag = 0;
7956 unsigned WrapperKind = X86ISD::Wrapper;
7957 CodeModel::Model M = getTargetMachine().getCodeModel();
7959 if (Subtarget->isPICStyleRIPRel() &&
7960 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7961 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7962 OpFlag = X86II::MO_GOTPCREL;
7963 WrapperKind = X86ISD::WrapperRIP;
7964 } else if (Subtarget->isPICStyleGOT()) {
7965 OpFlag = X86II::MO_GOT;
7966 } else if (Subtarget->isPICStyleStubPIC()) {
7967 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7968 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7969 OpFlag = X86II::MO_DARWIN_NONLAZY;
7972 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7975 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7977 // With PIC, the address is actually $g + Offset.
7978 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7979 !Subtarget->is64Bit()) {
7980 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7981 DAG.getNode(X86ISD::GlobalBaseReg,
7982 SDLoc(), getPointerTy()),
7986 // For symbols that require a load from a stub to get the address, emit the
7988 if (isGlobalStubReference(OpFlag))
7989 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7990 MachinePointerInfo::getGOT(), false, false, false, 0);
7996 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7997 // Create the TargetBlockAddressAddress node.
7998 unsigned char OpFlags =
7999 Subtarget->ClassifyBlockAddressReference();
8000 CodeModel::Model M = getTargetMachine().getCodeModel();
8001 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8002 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8004 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8007 if (Subtarget->isPICStyleRIPRel() &&
8008 (M == CodeModel::Small || M == CodeModel::Kernel))
8009 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8011 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8013 // With PIC, the address is actually $g + Offset.
8014 if (isGlobalRelativeToPICBase(OpFlags)) {
8015 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8016 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8024 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8025 int64_t Offset, SelectionDAG &DAG) const {
8026 // Create the TargetGlobalAddress node, folding in the constant
8027 // offset if it is legal.
8028 unsigned char OpFlags =
8029 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8030 CodeModel::Model M = getTargetMachine().getCodeModel();
8032 if (OpFlags == X86II::MO_NO_FLAG &&
8033 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8034 // A direct static reference to a global.
8035 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8038 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8041 if (Subtarget->isPICStyleRIPRel() &&
8042 (M == CodeModel::Small || M == CodeModel::Kernel))
8043 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8045 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8047 // With PIC, the address is actually $g + Offset.
8048 if (isGlobalRelativeToPICBase(OpFlags)) {
8049 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8050 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8054 // For globals that require a load from a stub to get the address, emit the
8056 if (isGlobalStubReference(OpFlags))
8057 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8058 MachinePointerInfo::getGOT(), false, false, false, 0);
8060 // If there was a non-zero offset that we didn't fold, create an explicit
8063 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8064 DAG.getConstant(Offset, getPointerTy()));
8070 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8071 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8072 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8073 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8077 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8078 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8079 unsigned char OperandFlags, bool LocalDynamic = false) {
8080 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8081 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8083 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8084 GA->getValueType(0),
8088 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8092 SDValue Ops[] = { Chain, TGA, *InFlag };
8093 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8095 SDValue Ops[] = { Chain, TGA };
8096 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8099 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8100 MFI->setAdjustsStack(true);
8102 SDValue Flag = Chain.getValue(1);
8103 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8106 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8108 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8111 SDLoc dl(GA); // ? function entry point might be better
8112 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8113 DAG.getNode(X86ISD::GlobalBaseReg,
8114 SDLoc(), PtrVT), InFlag);
8115 InFlag = Chain.getValue(1);
8117 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8120 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8122 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8124 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8125 X86::RAX, X86II::MO_TLSGD);
8128 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8134 // Get the start address of the TLS block for this module.
8135 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8136 .getInfo<X86MachineFunctionInfo>();
8137 MFI->incNumLocalDynamicTLSAccesses();
8141 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8142 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8145 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8146 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8147 InFlag = Chain.getValue(1);
8148 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8149 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8152 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8156 unsigned char OperandFlags = X86II::MO_DTPOFF;
8157 unsigned WrapperKind = X86ISD::Wrapper;
8158 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8159 GA->getValueType(0),
8160 GA->getOffset(), OperandFlags);
8161 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8163 // Add x@dtpoff with the base.
8164 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8167 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8168 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8169 const EVT PtrVT, TLSModel::Model model,
8170 bool is64Bit, bool isPIC) {
8173 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8174 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8175 is64Bit ? 257 : 256));
8177 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
8178 DAG.getIntPtrConstant(0),
8179 MachinePointerInfo(Ptr),
8180 false, false, false, 0);
8182 unsigned char OperandFlags = 0;
8183 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8185 unsigned WrapperKind = X86ISD::Wrapper;
8186 if (model == TLSModel::LocalExec) {
8187 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8188 } else if (model == TLSModel::InitialExec) {
8190 OperandFlags = X86II::MO_GOTTPOFF;
8191 WrapperKind = X86ISD::WrapperRIP;
8193 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8196 llvm_unreachable("Unexpected model");
8199 // emit "addl x@ntpoff,%eax" (local exec)
8200 // or "addl x@indntpoff,%eax" (initial exec)
8201 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8202 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8203 GA->getValueType(0),
8204 GA->getOffset(), OperandFlags);
8205 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8207 if (model == TLSModel::InitialExec) {
8208 if (isPIC && !is64Bit) {
8209 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8210 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8214 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8215 MachinePointerInfo::getGOT(), false, false, false,
8219 // The address of the thread local variable is the add of the thread
8220 // pointer with the offset of the variable.
8221 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8225 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8227 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8228 const GlobalValue *GV = GA->getGlobal();
8230 if (Subtarget->isTargetELF()) {
8231 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8234 case TLSModel::GeneralDynamic:
8235 if (Subtarget->is64Bit())
8236 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8237 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8238 case TLSModel::LocalDynamic:
8239 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8240 Subtarget->is64Bit());
8241 case TLSModel::InitialExec:
8242 case TLSModel::LocalExec:
8243 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8244 Subtarget->is64Bit(),
8245 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8247 llvm_unreachable("Unknown TLS model.");
8250 if (Subtarget->isTargetDarwin()) {
8251 // Darwin only has one model of TLS. Lower to that.
8252 unsigned char OpFlag = 0;
8253 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8254 X86ISD::WrapperRIP : X86ISD::Wrapper;
8256 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8258 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8259 !Subtarget->is64Bit();
8261 OpFlag = X86II::MO_TLVP_PIC_BASE;
8263 OpFlag = X86II::MO_TLVP;
8265 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8266 GA->getValueType(0),
8267 GA->getOffset(), OpFlag);
8268 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8270 // With PIC32, the address is actually $g + Offset.
8272 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8273 DAG.getNode(X86ISD::GlobalBaseReg,
8274 SDLoc(), getPointerTy()),
8277 // Lowering the machine isd will make sure everything is in the right
8279 SDValue Chain = DAG.getEntryNode();
8280 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8281 SDValue Args[] = { Chain, Offset };
8282 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8284 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8285 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8286 MFI->setAdjustsStack(true);
8288 // And our return value (tls address) is in the standard call return value
8290 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8291 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8295 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8296 // Just use the implicit TLS architecture
8297 // Need to generate someting similar to:
8298 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8300 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8301 // mov rcx, qword [rdx+rcx*8]
8302 // mov eax, .tls$:tlsvar
8303 // [rax+rcx] contains the address
8304 // Windows 64bit: gs:0x58
8305 // Windows 32bit: fs:__tls_array
8307 // If GV is an alias then use the aliasee for determining
8308 // thread-localness.
8309 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8310 GV = GA->resolveAliasedGlobal(false);
8312 SDValue Chain = DAG.getEntryNode();
8314 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8315 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8316 // use its literal value of 0x2C.
8317 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8318 ? Type::getInt8PtrTy(*DAG.getContext(),
8320 : Type::getInt32PtrTy(*DAG.getContext(),
8323 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8324 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8325 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8327 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8328 MachinePointerInfo(Ptr),
8329 false, false, false, 0);
8331 // Load the _tls_index variable
8332 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8333 if (Subtarget->is64Bit())
8334 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8335 IDX, MachinePointerInfo(), MVT::i32,
8338 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8339 false, false, false, 0);
8341 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8343 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8345 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8346 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8347 false, false, false, 0);
8349 // Get the offset of start of .tls section
8350 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8351 GA->getValueType(0),
8352 GA->getOffset(), X86II::MO_SECREL);
8353 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8355 // The address of the thread local variable is the add of the thread
8356 // pointer with the offset of the variable.
8357 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8360 llvm_unreachable("TLS not implemented for this target.");
8363 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8364 /// and take a 2 x i32 value to shift plus a shift amount.
8365 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8366 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8367 EVT VT = Op.getValueType();
8368 unsigned VTBits = VT.getSizeInBits();
8370 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8371 SDValue ShOpLo = Op.getOperand(0);
8372 SDValue ShOpHi = Op.getOperand(1);
8373 SDValue ShAmt = Op.getOperand(2);
8374 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8375 DAG.getConstant(VTBits - 1, MVT::i8))
8376 : DAG.getConstant(0, VT);
8379 if (Op.getOpcode() == ISD::SHL_PARTS) {
8380 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8381 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8383 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8384 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8387 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8388 DAG.getConstant(VTBits, MVT::i8));
8389 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8390 AndNode, DAG.getConstant(0, MVT::i8));
8393 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8394 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8395 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8397 if (Op.getOpcode() == ISD::SHL_PARTS) {
8398 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8399 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8401 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8402 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8405 SDValue Ops[2] = { Lo, Hi };
8406 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8409 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8410 SelectionDAG &DAG) const {
8411 EVT SrcVT = Op.getOperand(0).getValueType();
8413 if (SrcVT.isVector())
8416 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8417 "Unknown SINT_TO_FP to lower!");
8419 // These are really Legal; return the operand so the caller accepts it as
8421 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8423 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8424 Subtarget->is64Bit()) {
8429 unsigned Size = SrcVT.getSizeInBits()/8;
8430 MachineFunction &MF = DAG.getMachineFunction();
8431 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8432 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8433 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8435 MachinePointerInfo::getFixedStack(SSFI),
8437 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8440 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8442 SelectionDAG &DAG) const {
8446 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8448 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8450 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8452 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8454 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8455 MachineMemOperand *MMO;
8457 int SSFI = FI->getIndex();
8459 DAG.getMachineFunction()
8460 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8461 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8463 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8464 StackSlot = StackSlot.getOperand(1);
8466 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8467 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8469 Tys, Ops, array_lengthof(Ops),
8473 Chain = Result.getValue(1);
8474 SDValue InFlag = Result.getValue(2);
8476 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8477 // shouldn't be necessary except that RFP cannot be live across
8478 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8479 MachineFunction &MF = DAG.getMachineFunction();
8480 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8481 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8482 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8483 Tys = DAG.getVTList(MVT::Other);
8485 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8487 MachineMemOperand *MMO =
8488 DAG.getMachineFunction()
8489 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8490 MachineMemOperand::MOStore, SSFISize, SSFISize);
8492 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8493 Ops, array_lengthof(Ops),
8494 Op.getValueType(), MMO);
8495 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8496 MachinePointerInfo::getFixedStack(SSFI),
8497 false, false, false, 0);
8503 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8504 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8505 SelectionDAG &DAG) const {
8506 // This algorithm is not obvious. Here it is what we're trying to output:
8509 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8510 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8514 pshufd $0x4e, %xmm0, %xmm1
8520 LLVMContext *Context = DAG.getContext();
8522 // Build some magic constants.
8523 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8524 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8525 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8527 SmallVector<Constant*,2> CV1;
8529 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8530 APInt(64, 0x4330000000000000ULL))));
8532 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8533 APInt(64, 0x4530000000000000ULL))));
8534 Constant *C1 = ConstantVector::get(CV1);
8535 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8537 // Load the 64-bit value into an XMM register.
8538 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8540 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8541 MachinePointerInfo::getConstantPool(),
8542 false, false, false, 16);
8543 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8544 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8547 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8548 MachinePointerInfo::getConstantPool(),
8549 false, false, false, 16);
8550 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8551 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8554 if (Subtarget->hasSSE3()) {
8555 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8556 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8558 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8559 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8561 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8562 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8566 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8567 DAG.getIntPtrConstant(0));
8570 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8571 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8572 SelectionDAG &DAG) const {
8574 // FP constant to bias correct the final result.
8575 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8578 // Load the 32-bit value into an XMM register.
8579 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8582 // Zero out the upper parts of the register.
8583 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8585 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8586 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8587 DAG.getIntPtrConstant(0));
8589 // Or the load with the bias.
8590 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8591 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8592 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8594 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8595 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8596 MVT::v2f64, Bias)));
8597 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8598 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8599 DAG.getIntPtrConstant(0));
8601 // Subtract the bias.
8602 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8604 // Handle final rounding.
8605 EVT DestVT = Op.getValueType();
8607 if (DestVT.bitsLT(MVT::f64))
8608 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8609 DAG.getIntPtrConstant(0));
8610 if (DestVT.bitsGT(MVT::f64))
8611 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8613 // Handle final rounding.
8617 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8618 SelectionDAG &DAG) const {
8619 SDValue N0 = Op.getOperand(0);
8620 EVT SVT = N0.getValueType();
8623 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8624 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8625 "Custom UINT_TO_FP is not supported!");
8627 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8628 SVT.getVectorNumElements());
8629 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8630 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8633 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8634 SelectionDAG &DAG) const {
8635 SDValue N0 = Op.getOperand(0);
8638 if (Op.getValueType().isVector())
8639 return lowerUINT_TO_FP_vec(Op, DAG);
8641 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8642 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8643 // the optimization here.
8644 if (DAG.SignBitIsZero(N0))
8645 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8647 EVT SrcVT = N0.getValueType();
8648 EVT DstVT = Op.getValueType();
8649 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8650 return LowerUINT_TO_FP_i64(Op, DAG);
8651 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8652 return LowerUINT_TO_FP_i32(Op, DAG);
8653 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8656 // Make a 64-bit buffer, and use it to build an FILD.
8657 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8658 if (SrcVT == MVT::i32) {
8659 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8660 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8661 getPointerTy(), StackSlot, WordOff);
8662 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8663 StackSlot, MachinePointerInfo(),
8665 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8666 OffsetSlot, MachinePointerInfo(),
8668 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8672 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8673 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8674 StackSlot, MachinePointerInfo(),
8676 // For i64 source, we need to add the appropriate power of 2 if the input
8677 // was negative. This is the same as the optimization in
8678 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8679 // we must be careful to do the computation in x87 extended precision, not
8680 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8681 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8682 MachineMemOperand *MMO =
8683 DAG.getMachineFunction()
8684 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8685 MachineMemOperand::MOLoad, 8, 8);
8687 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8688 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8689 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8690 array_lengthof(Ops), MVT::i64, MMO);
8692 APInt FF(32, 0x5F800000ULL);
8694 // Check whether the sign bit is set.
8695 SDValue SignSet = DAG.getSetCC(dl,
8696 getSetCCResultType(*DAG.getContext(), MVT::i64),
8697 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8700 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8701 SDValue FudgePtr = DAG.getConstantPool(
8702 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8705 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8706 SDValue Zero = DAG.getIntPtrConstant(0);
8707 SDValue Four = DAG.getIntPtrConstant(4);
8708 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8710 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8712 // Load the value out, extending it from f32 to f80.
8713 // FIXME: Avoid the extend by constructing the right constant pool?
8714 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8715 FudgePtr, MachinePointerInfo::getConstantPool(),
8716 MVT::f32, false, false, 4);
8717 // Extend everything to 80 bits to force it to be done on x87.
8718 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8719 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8722 std::pair<SDValue,SDValue>
8723 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8724 bool IsSigned, bool IsReplace) const {
8727 EVT DstTy = Op.getValueType();
8729 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8730 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8734 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8735 DstTy.getSimpleVT() >= MVT::i16 &&
8736 "Unknown FP_TO_INT to lower!");
8738 // These are really Legal.
8739 if (DstTy == MVT::i32 &&
8740 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8741 return std::make_pair(SDValue(), SDValue());
8742 if (Subtarget->is64Bit() &&
8743 DstTy == MVT::i64 &&
8744 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8745 return std::make_pair(SDValue(), SDValue());
8747 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8748 // stack slot, or into the FTOL runtime function.
8749 MachineFunction &MF = DAG.getMachineFunction();
8750 unsigned MemSize = DstTy.getSizeInBits()/8;
8751 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8752 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8755 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8756 Opc = X86ISD::WIN_FTOL;
8758 switch (DstTy.getSimpleVT().SimpleTy) {
8759 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8760 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8761 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8762 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8765 SDValue Chain = DAG.getEntryNode();
8766 SDValue Value = Op.getOperand(0);
8767 EVT TheVT = Op.getOperand(0).getValueType();
8768 // FIXME This causes a redundant load/store if the SSE-class value is already
8769 // in memory, such as if it is on the callstack.
8770 if (isScalarFPTypeInSSEReg(TheVT)) {
8771 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8772 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8773 MachinePointerInfo::getFixedStack(SSFI),
8775 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8777 Chain, StackSlot, DAG.getValueType(TheVT)
8780 MachineMemOperand *MMO =
8781 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8782 MachineMemOperand::MOLoad, MemSize, MemSize);
8783 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8784 array_lengthof(Ops), DstTy, MMO);
8785 Chain = Value.getValue(1);
8786 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8787 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8790 MachineMemOperand *MMO =
8791 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8792 MachineMemOperand::MOStore, MemSize, MemSize);
8794 if (Opc != X86ISD::WIN_FTOL) {
8795 // Build the FP_TO_INT*_IN_MEM
8796 SDValue Ops[] = { Chain, Value, StackSlot };
8797 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8798 Ops, array_lengthof(Ops), DstTy,
8800 return std::make_pair(FIST, StackSlot);
8802 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8803 DAG.getVTList(MVT::Other, MVT::Glue),
8805 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8806 MVT::i32, ftol.getValue(1));
8807 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8808 MVT::i32, eax.getValue(2));
8809 SDValue Ops[] = { eax, edx };
8810 SDValue pair = IsReplace
8811 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8812 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8813 return std::make_pair(pair, SDValue());
8817 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8818 const X86Subtarget *Subtarget) {
8819 MVT VT = Op->getSimpleValueType(0);
8820 SDValue In = Op->getOperand(0);
8821 MVT InVT = In.getSimpleValueType();
8824 // Optimize vectors in AVX mode:
8827 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8828 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8829 // Concat upper and lower parts.
8832 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8833 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8834 // Concat upper and lower parts.
8837 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8838 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8841 if (Subtarget->hasInt256())
8842 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8844 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8845 SDValue Undef = DAG.getUNDEF(InVT);
8846 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8847 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8848 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8850 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8851 VT.getVectorNumElements()/2);
8853 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8854 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8856 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8859 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8860 SelectionDAG &DAG) {
8861 if (Subtarget->hasFp256()) {
8862 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8870 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8871 SelectionDAG &DAG) {
8873 MVT VT = Op.getSimpleValueType();
8874 SDValue In = Op.getOperand(0);
8875 MVT SVT = In.getSimpleValueType();
8877 if (Subtarget->hasFp256()) {
8878 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8883 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8884 VT.getVectorNumElements() != SVT.getVectorNumElements())
8887 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8889 // AVX2 has better support of integer extending.
8890 if (Subtarget->hasInt256())
8891 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8893 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8894 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8895 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8896 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8897 DAG.getUNDEF(MVT::v8i16),
8900 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8903 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8905 MVT VT = Op.getSimpleValueType();
8906 SDValue In = Op.getOperand(0);
8907 MVT SVT = In.getSimpleValueType();
8909 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8910 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8911 if (Subtarget->hasInt256()) {
8912 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8913 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8914 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8916 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8917 DAG.getIntPtrConstant(0));
8920 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8921 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8922 DAG.getIntPtrConstant(0));
8923 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8924 DAG.getIntPtrConstant(2));
8926 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8927 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8930 static const int ShufMask1[] = {0, 2, 0, 0};
8931 SDValue Undef = DAG.getUNDEF(VT);
8932 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8933 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8935 // The MOVLHPS mask:
8936 static const int ShufMask2[] = {0, 1, 4, 5};
8937 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8940 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8941 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8942 if (Subtarget->hasInt256()) {
8943 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8945 SmallVector<SDValue,32> pshufbMask;
8946 for (unsigned i = 0; i < 2; ++i) {
8947 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8948 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8949 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8950 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8951 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8952 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8953 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8954 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8955 for (unsigned j = 0; j < 8; ++j)
8956 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8958 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8959 &pshufbMask[0], 32);
8960 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8961 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8963 static const int ShufMask[] = {0, 2, -1, -1};
8964 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8966 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8967 DAG.getIntPtrConstant(0));
8968 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8971 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8972 DAG.getIntPtrConstant(0));
8974 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8975 DAG.getIntPtrConstant(4));
8977 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8978 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8981 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8982 -1, -1, -1, -1, -1, -1, -1, -1};
8984 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8985 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8986 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8988 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8989 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8991 // The MOVLHPS Mask:
8992 static const int ShufMask2[] = {0, 1, 4, 5};
8993 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8994 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8997 // Handle truncation of V256 to V128 using shuffles.
8998 if (!VT.is128BitVector() || !SVT.is256BitVector())
9001 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
9003 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9005 unsigned NumElems = VT.getVectorNumElements();
9006 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9009 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9010 // Prepare truncation shuffle mask
9011 for (unsigned i = 0; i != NumElems; ++i)
9013 SDValue V = DAG.getVectorShuffle(NVT, DL,
9014 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9015 DAG.getUNDEF(NVT), &MaskVec[0]);
9016 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9017 DAG.getIntPtrConstant(0));
9020 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9021 SelectionDAG &DAG) const {
9022 MVT VT = Op.getSimpleValueType();
9023 if (VT.isVector()) {
9024 if (VT == MVT::v8i16)
9025 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9026 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9027 MVT::v8i32, Op.getOperand(0)));
9031 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9032 /*IsSigned=*/ true, /*IsReplace=*/ false);
9033 SDValue FIST = Vals.first, StackSlot = Vals.second;
9034 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9035 if (FIST.getNode() == 0) return Op;
9037 if (StackSlot.getNode())
9039 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9040 FIST, StackSlot, MachinePointerInfo(),
9041 false, false, false, 0);
9043 // The node is the result.
9047 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9048 SelectionDAG &DAG) const {
9049 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9050 /*IsSigned=*/ false, /*IsReplace=*/ false);
9051 SDValue FIST = Vals.first, StackSlot = Vals.second;
9052 assert(FIST.getNode() && "Unexpected failure");
9054 if (StackSlot.getNode())
9056 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9057 FIST, StackSlot, MachinePointerInfo(),
9058 false, false, false, 0);
9060 // The node is the result.
9064 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9066 MVT VT = Op.getSimpleValueType();
9067 SDValue In = Op.getOperand(0);
9068 MVT SVT = In.getSimpleValueType();
9070 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9072 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9073 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9074 In, DAG.getUNDEF(SVT)));
9077 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9078 LLVMContext *Context = DAG.getContext();
9080 MVT VT = Op.getSimpleValueType();
9082 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9083 if (VT.isVector()) {
9084 EltVT = VT.getVectorElementType();
9085 NumElts = VT.getVectorNumElements();
9088 if (EltVT == MVT::f64)
9089 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9090 APInt(64, ~(1ULL << 63))));
9092 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9093 APInt(32, ~(1U << 31))));
9094 C = ConstantVector::getSplat(NumElts, C);
9095 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9096 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9097 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9098 MachinePointerInfo::getConstantPool(),
9099 false, false, false, Alignment);
9100 if (VT.isVector()) {
9101 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9102 return DAG.getNode(ISD::BITCAST, dl, VT,
9103 DAG.getNode(ISD::AND, dl, ANDVT,
9104 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9106 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9108 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9111 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9112 LLVMContext *Context = DAG.getContext();
9114 MVT VT = Op.getSimpleValueType();
9116 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9117 if (VT.isVector()) {
9118 EltVT = VT.getVectorElementType();
9119 NumElts = VT.getVectorNumElements();
9122 if (EltVT == MVT::f64)
9123 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9124 APInt(64, 1ULL << 63)));
9126 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9127 APInt(32, 1U << 31)));
9128 C = ConstantVector::getSplat(NumElts, C);
9129 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9130 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9131 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9132 MachinePointerInfo::getConstantPool(),
9133 false, false, false, Alignment);
9134 if (VT.isVector()) {
9135 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9136 return DAG.getNode(ISD::BITCAST, dl, VT,
9137 DAG.getNode(ISD::XOR, dl, XORVT,
9138 DAG.getNode(ISD::BITCAST, dl, XORVT,
9140 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9143 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9146 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9147 LLVMContext *Context = DAG.getContext();
9148 SDValue Op0 = Op.getOperand(0);
9149 SDValue Op1 = Op.getOperand(1);
9151 MVT VT = Op.getSimpleValueType();
9152 MVT SrcVT = Op1.getSimpleValueType();
9154 // If second operand is smaller, extend it first.
9155 if (SrcVT.bitsLT(VT)) {
9156 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9159 // And if it is bigger, shrink it first.
9160 if (SrcVT.bitsGT(VT)) {
9161 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9165 // At this point the operands and the result should have the same
9166 // type, and that won't be f80 since that is not custom lowered.
9168 // First get the sign bit of second operand.
9169 SmallVector<Constant*,4> CV;
9170 if (SrcVT == MVT::f64) {
9171 const fltSemantics &Sem = APFloat::IEEEdouble;
9172 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9173 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9175 const fltSemantics &Sem = APFloat::IEEEsingle;
9176 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9177 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9178 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9179 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9181 Constant *C = ConstantVector::get(CV);
9182 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9183 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9184 MachinePointerInfo::getConstantPool(),
9185 false, false, false, 16);
9186 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9188 // Shift sign bit right or left if the two operands have different types.
9189 if (SrcVT.bitsGT(VT)) {
9190 // Op0 is MVT::f32, Op1 is MVT::f64.
9191 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9192 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9193 DAG.getConstant(32, MVT::i32));
9194 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9195 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9196 DAG.getIntPtrConstant(0));
9199 // Clear first operand sign bit.
9201 if (VT == MVT::f64) {
9202 const fltSemantics &Sem = APFloat::IEEEdouble;
9203 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9204 APInt(64, ~(1ULL << 63)))));
9205 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9207 const fltSemantics &Sem = APFloat::IEEEsingle;
9208 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9209 APInt(32, ~(1U << 31)))));
9210 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9211 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9212 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9214 C = ConstantVector::get(CV);
9215 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9216 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9217 MachinePointerInfo::getConstantPool(),
9218 false, false, false, 16);
9219 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9221 // Or the value with the sign bit.
9222 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9225 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9226 SDValue N0 = Op.getOperand(0);
9228 MVT VT = Op.getSimpleValueType();
9230 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9231 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9232 DAG.getConstant(1, VT));
9233 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9236 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9238 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9239 SelectionDAG &DAG) {
9240 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9242 if (!Subtarget->hasSSE41())
9245 if (!Op->hasOneUse())
9248 SDNode *N = Op.getNode();
9251 SmallVector<SDValue, 8> Opnds;
9252 DenseMap<SDValue, unsigned> VecInMap;
9253 EVT VT = MVT::Other;
9255 // Recognize a special case where a vector is casted into wide integer to
9257 Opnds.push_back(N->getOperand(0));
9258 Opnds.push_back(N->getOperand(1));
9260 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9261 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9262 // BFS traverse all OR'd operands.
9263 if (I->getOpcode() == ISD::OR) {
9264 Opnds.push_back(I->getOperand(0));
9265 Opnds.push_back(I->getOperand(1));
9266 // Re-evaluate the number of nodes to be traversed.
9267 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9271 // Quit if a non-EXTRACT_VECTOR_ELT
9272 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9275 // Quit if without a constant index.
9276 SDValue Idx = I->getOperand(1);
9277 if (!isa<ConstantSDNode>(Idx))
9280 SDValue ExtractedFromVec = I->getOperand(0);
9281 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9282 if (M == VecInMap.end()) {
9283 VT = ExtractedFromVec.getValueType();
9284 // Quit if not 128/256-bit vector.
9285 if (!VT.is128BitVector() && !VT.is256BitVector())
9287 // Quit if not the same type.
9288 if (VecInMap.begin() != VecInMap.end() &&
9289 VT != VecInMap.begin()->first.getValueType())
9291 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9293 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9296 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9297 "Not extracted from 128-/256-bit vector.");
9299 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9300 SmallVector<SDValue, 8> VecIns;
9302 for (DenseMap<SDValue, unsigned>::const_iterator
9303 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9304 // Quit if not all elements are used.
9305 if (I->second != FullMask)
9307 VecIns.push_back(I->first);
9310 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9312 // Cast all vectors into TestVT for PTEST.
9313 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9314 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9316 // If more than one full vectors are evaluated, OR them first before PTEST.
9317 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9318 // Each iteration will OR 2 nodes and append the result until there is only
9319 // 1 node left, i.e. the final OR'd value of all vectors.
9320 SDValue LHS = VecIns[Slot];
9321 SDValue RHS = VecIns[Slot + 1];
9322 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9325 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9326 VecIns.back(), VecIns.back());
9329 /// Emit nodes that will be selected as "test Op0,Op0", or something
9331 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9332 SelectionDAG &DAG) const {
9335 // CF and OF aren't always set the way we want. Determine which
9336 // of these we need.
9337 bool NeedCF = false;
9338 bool NeedOF = false;
9341 case X86::COND_A: case X86::COND_AE:
9342 case X86::COND_B: case X86::COND_BE:
9345 case X86::COND_G: case X86::COND_GE:
9346 case X86::COND_L: case X86::COND_LE:
9347 case X86::COND_O: case X86::COND_NO:
9352 // See if we can use the EFLAGS value from the operand instead of
9353 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9354 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9355 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9356 // Emit a CMP with 0, which is the TEST pattern.
9357 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9358 DAG.getConstant(0, Op.getValueType()));
9360 unsigned Opcode = 0;
9361 unsigned NumOperands = 0;
9363 // Truncate operations may prevent the merge of the SETCC instruction
9364 // and the arithmetic intruction before it. Attempt to truncate the operands
9365 // of the arithmetic instruction and use a reduced bit-width instruction.
9366 bool NeedTruncation = false;
9367 SDValue ArithOp = Op;
9368 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9369 SDValue Arith = Op->getOperand(0);
9370 // Both the trunc and the arithmetic op need to have one user each.
9371 if (Arith->hasOneUse())
9372 switch (Arith.getOpcode()) {
9379 NeedTruncation = true;
9385 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9386 // which may be the result of a CAST. We use the variable 'Op', which is the
9387 // non-casted variable when we check for possible users.
9388 switch (ArithOp.getOpcode()) {
9390 // Due to an isel shortcoming, be conservative if this add is likely to be
9391 // selected as part of a load-modify-store instruction. When the root node
9392 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9393 // uses of other nodes in the match, such as the ADD in this case. This
9394 // leads to the ADD being left around and reselected, with the result being
9395 // two adds in the output. Alas, even if none our users are stores, that
9396 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9397 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9398 // climbing the DAG back to the root, and it doesn't seem to be worth the
9400 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9401 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9402 if (UI->getOpcode() != ISD::CopyToReg &&
9403 UI->getOpcode() != ISD::SETCC &&
9404 UI->getOpcode() != ISD::STORE)
9407 if (ConstantSDNode *C =
9408 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9409 // An add of one will be selected as an INC.
9410 if (C->getAPIntValue() == 1) {
9411 Opcode = X86ISD::INC;
9416 // An add of negative one (subtract of one) will be selected as a DEC.
9417 if (C->getAPIntValue().isAllOnesValue()) {
9418 Opcode = X86ISD::DEC;
9424 // Otherwise use a regular EFLAGS-setting add.
9425 Opcode = X86ISD::ADD;
9429 // If the primary and result isn't used, don't bother using X86ISD::AND,
9430 // because a TEST instruction will be better.
9431 bool NonFlagUse = false;
9432 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9433 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9435 unsigned UOpNo = UI.getOperandNo();
9436 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9437 // Look pass truncate.
9438 UOpNo = User->use_begin().getOperandNo();
9439 User = *User->use_begin();
9442 if (User->getOpcode() != ISD::BRCOND &&
9443 User->getOpcode() != ISD::SETCC &&
9444 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9457 // Due to the ISEL shortcoming noted above, be conservative if this op is
9458 // likely to be selected as part of a load-modify-store instruction.
9459 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9460 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9461 if (UI->getOpcode() == ISD::STORE)
9464 // Otherwise use a regular EFLAGS-setting instruction.
9465 switch (ArithOp.getOpcode()) {
9466 default: llvm_unreachable("unexpected operator!");
9467 case ISD::SUB: Opcode = X86ISD::SUB; break;
9468 case ISD::XOR: Opcode = X86ISD::XOR; break;
9469 case ISD::AND: Opcode = X86ISD::AND; break;
9471 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9472 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9473 if (EFLAGS.getNode())
9476 Opcode = X86ISD::OR;
9490 return SDValue(Op.getNode(), 1);
9496 // If we found that truncation is beneficial, perform the truncation and
9498 if (NeedTruncation) {
9499 EVT VT = Op.getValueType();
9500 SDValue WideVal = Op->getOperand(0);
9501 EVT WideVT = WideVal.getValueType();
9502 unsigned ConvertedOp = 0;
9503 // Use a target machine opcode to prevent further DAGCombine
9504 // optimizations that may separate the arithmetic operations
9505 // from the setcc node.
9506 switch (WideVal.getOpcode()) {
9508 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9509 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9510 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9511 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9512 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9516 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9517 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9518 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9519 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9520 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9526 // Emit a CMP with 0, which is the TEST pattern.
9527 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9528 DAG.getConstant(0, Op.getValueType()));
9530 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9531 SmallVector<SDValue, 4> Ops;
9532 for (unsigned i = 0; i != NumOperands; ++i)
9533 Ops.push_back(Op.getOperand(i));
9535 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9536 DAG.ReplaceAllUsesWith(Op, New);
9537 return SDValue(New.getNode(), 1);
9540 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9542 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9543 SelectionDAG &DAG) const {
9544 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9545 if (C->getAPIntValue() == 0)
9546 return EmitTest(Op0, X86CC, DAG);
9549 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9550 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9551 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9552 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9553 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9555 return SDValue(Sub.getNode(), 1);
9557 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9560 /// Convert a comparison if required by the subtarget.
9561 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9562 SelectionDAG &DAG) const {
9563 // If the subtarget does not support the FUCOMI instruction, floating-point
9564 // comparisons have to be converted.
9565 if (Subtarget->hasCMov() ||
9566 Cmp.getOpcode() != X86ISD::CMP ||
9567 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9568 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9571 // The instruction selector will select an FUCOM instruction instead of
9572 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9573 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9574 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9576 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9577 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9578 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9579 DAG.getConstant(8, MVT::i8));
9580 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9581 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9584 static bool isAllOnes(SDValue V) {
9585 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9586 return C && C->isAllOnesValue();
9589 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9590 /// if it's possible.
9591 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9592 SDLoc dl, SelectionDAG &DAG) const {
9593 SDValue Op0 = And.getOperand(0);
9594 SDValue Op1 = And.getOperand(1);
9595 if (Op0.getOpcode() == ISD::TRUNCATE)
9596 Op0 = Op0.getOperand(0);
9597 if (Op1.getOpcode() == ISD::TRUNCATE)
9598 Op1 = Op1.getOperand(0);
9601 if (Op1.getOpcode() == ISD::SHL)
9602 std::swap(Op0, Op1);
9603 if (Op0.getOpcode() == ISD::SHL) {
9604 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9605 if (And00C->getZExtValue() == 1) {
9606 // If we looked past a truncate, check that it's only truncating away
9608 unsigned BitWidth = Op0.getValueSizeInBits();
9609 unsigned AndBitWidth = And.getValueSizeInBits();
9610 if (BitWidth > AndBitWidth) {
9612 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9613 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9617 RHS = Op0.getOperand(1);
9619 } else if (Op1.getOpcode() == ISD::Constant) {
9620 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9621 uint64_t AndRHSVal = AndRHS->getZExtValue();
9622 SDValue AndLHS = Op0;
9624 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9625 LHS = AndLHS.getOperand(0);
9626 RHS = AndLHS.getOperand(1);
9629 // Use BT if the immediate can't be encoded in a TEST instruction.
9630 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9632 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9636 if (LHS.getNode()) {
9637 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9638 // instruction. Since the shift amount is in-range-or-undefined, we know
9639 // that doing a bittest on the i32 value is ok. We extend to i32 because
9640 // the encoding for the i16 version is larger than the i32 version.
9641 // Also promote i16 to i32 for performance / code size reason.
9642 if (LHS.getValueType() == MVT::i8 ||
9643 LHS.getValueType() == MVT::i16)
9644 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9646 // If the operand types disagree, extend the shift amount to match. Since
9647 // BT ignores high bits (like shifts) we can use anyextend.
9648 if (LHS.getValueType() != RHS.getValueType())
9649 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9651 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9652 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9653 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9654 DAG.getConstant(Cond, MVT::i8), BT);
9660 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9662 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9667 // SSE Condition code mapping:
9676 switch (SetCCOpcode) {
9677 default: llvm_unreachable("Unexpected SETCC condition");
9679 case ISD::SETEQ: SSECC = 0; break;
9681 case ISD::SETGT: Swap = true; // Fallthrough
9683 case ISD::SETOLT: SSECC = 1; break;
9685 case ISD::SETGE: Swap = true; // Fallthrough
9687 case ISD::SETOLE: SSECC = 2; break;
9688 case ISD::SETUO: SSECC = 3; break;
9690 case ISD::SETNE: SSECC = 4; break;
9691 case ISD::SETULE: Swap = true; // Fallthrough
9692 case ISD::SETUGE: SSECC = 5; break;
9693 case ISD::SETULT: Swap = true; // Fallthrough
9694 case ISD::SETUGT: SSECC = 6; break;
9695 case ISD::SETO: SSECC = 7; break;
9697 case ISD::SETONE: SSECC = 8; break;
9700 std::swap(Op0, Op1);
9705 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9706 // ones, and then concatenate the result back.
9707 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9708 MVT VT = Op.getSimpleValueType();
9710 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9711 "Unsupported value type for operation");
9713 unsigned NumElems = VT.getVectorNumElements();
9715 SDValue CC = Op.getOperand(2);
9717 // Extract the LHS vectors
9718 SDValue LHS = Op.getOperand(0);
9719 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9720 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9722 // Extract the RHS vectors
9723 SDValue RHS = Op.getOperand(1);
9724 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9725 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9727 // Issue the operation on the smaller types and concatenate the result back
9728 MVT EltVT = VT.getVectorElementType();
9729 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9730 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9731 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9732 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9735 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9737 SDValue Op0 = Op.getOperand(0);
9738 SDValue Op1 = Op.getOperand(1);
9739 SDValue CC = Op.getOperand(2);
9740 MVT VT = Op.getSimpleValueType();
9742 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9743 Op.getValueType().getScalarType() == MVT::i1 &&
9744 "Cannot set masked compare for this operation");
9746 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9749 bool Unsigned = false;
9751 switch (SetCCOpcode) {
9752 default: llvm_unreachable("Unexpected SETCC condition");
9753 case ISD::SETNE: SSECC = 4; break;
9754 case ISD::SETEQ: SSECC = 0; break;
9755 case ISD::SETUGT: Unsigned = true;
9756 case ISD::SETGT: SSECC = 6; break; // NLE
9757 case ISD::SETULT: Unsigned = true;
9758 case ISD::SETLT: SSECC = 1; break;
9759 case ISD::SETUGE: Unsigned = true;
9760 case ISD::SETGE: SSECC = 5; break; // NLT
9761 case ISD::SETULE: Unsigned = true;
9762 case ISD::SETLE: SSECC = 2; break;
9764 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9765 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9766 DAG.getConstant(SSECC, MVT::i8));
9770 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9771 SelectionDAG &DAG) {
9773 SDValue Op0 = Op.getOperand(0);
9774 SDValue Op1 = Op.getOperand(1);
9775 SDValue CC = Op.getOperand(2);
9776 MVT VT = Op.getSimpleValueType();
9777 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9778 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9783 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9784 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9787 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9788 unsigned Opc = X86ISD::CMPP;
9789 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9790 assert(VT.getVectorNumElements() <= 16);
9793 // In the two special cases we can't handle, emit two comparisons.
9796 unsigned CombineOpc;
9797 if (SetCCOpcode == ISD::SETUEQ) {
9798 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9800 assert(SetCCOpcode == ISD::SETONE);
9801 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9804 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9805 DAG.getConstant(CC0, MVT::i8));
9806 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9807 DAG.getConstant(CC1, MVT::i8));
9808 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9810 // Handle all other FP comparisons here.
9811 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9812 DAG.getConstant(SSECC, MVT::i8));
9815 // Break 256-bit integer vector compare into smaller ones.
9816 if (VT.is256BitVector() && !Subtarget->hasInt256())
9817 return Lower256IntVSETCC(Op, DAG);
9819 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9820 EVT OpVT = Op1.getValueType();
9821 if (Subtarget->hasAVX512()) {
9822 if (Op1.getValueType().is512BitVector() ||
9823 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9824 return LowerIntVSETCC_AVX512(Op, DAG);
9826 // In AVX-512 architecture setcc returns mask with i1 elements,
9827 // But there is no compare instruction for i8 and i16 elements.
9828 // We are not talking about 512-bit operands in this case, these
9829 // types are illegal.
9831 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9832 OpVT.getVectorElementType().getSizeInBits() >= 8))
9833 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9834 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9837 // We are handling one of the integer comparisons here. Since SSE only has
9838 // GT and EQ comparisons for integer, swapping operands and multiple
9839 // operations may be required for some comparisons.
9841 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9843 switch (SetCCOpcode) {
9844 default: llvm_unreachable("Unexpected SETCC condition");
9845 case ISD::SETNE: Invert = true;
9846 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9847 case ISD::SETLT: Swap = true;
9848 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9849 case ISD::SETGE: Swap = true;
9850 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9851 Invert = true; break;
9852 case ISD::SETULT: Swap = true;
9853 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9854 FlipSigns = true; break;
9855 case ISD::SETUGE: Swap = true;
9856 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9857 FlipSigns = true; Invert = true; break;
9860 // Special case: Use min/max operations for SETULE/SETUGE
9861 MVT VET = VT.getVectorElementType();
9863 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9864 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9867 switch (SetCCOpcode) {
9869 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9870 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9873 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9877 std::swap(Op0, Op1);
9879 // Check that the operation in question is available (most are plain SSE2,
9880 // but PCMPGTQ and PCMPEQQ have different requirements).
9881 if (VT == MVT::v2i64) {
9882 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9883 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9885 // First cast everything to the right type.
9886 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9887 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9889 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9890 // bits of the inputs before performing those operations. The lower
9891 // compare is always unsigned.
9894 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9896 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9897 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9898 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9899 Sign, Zero, Sign, Zero);
9901 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9902 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9904 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9905 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9906 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9908 // Create masks for only the low parts/high parts of the 64 bit integers.
9909 static const int MaskHi[] = { 1, 1, 3, 3 };
9910 static const int MaskLo[] = { 0, 0, 2, 2 };
9911 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9912 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9913 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9915 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9916 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9919 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9921 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9924 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9925 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9926 // pcmpeqd + pshufd + pand.
9927 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9929 // First cast everything to the right type.
9930 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9931 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9934 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9936 // Make sure the lower and upper halves are both all-ones.
9937 static const int Mask[] = { 1, 0, 3, 2 };
9938 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9939 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9942 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9944 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9948 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9949 // bits of the inputs before performing those operations.
9951 EVT EltVT = VT.getVectorElementType();
9952 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
9953 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
9954 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
9957 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9959 // If the logical-not of the result is required, perform that now.
9961 Result = DAG.getNOT(dl, Result, VT);
9964 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
9969 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9971 MVT VT = Op.getSimpleValueType();
9973 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9975 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9976 SDValue Op0 = Op.getOperand(0);
9977 SDValue Op1 = Op.getOperand(1);
9979 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9981 // Optimize to BT if possible.
9982 // Lower (X & (1 << N)) == 0 to BT(X, N).
9983 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9984 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9985 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9986 Op1.getOpcode() == ISD::Constant &&
9987 cast<ConstantSDNode>(Op1)->isNullValue() &&
9988 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9989 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9990 if (NewSetCC.getNode())
9994 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9996 if (Op1.getOpcode() == ISD::Constant &&
9997 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9998 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9999 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10001 // If the input is a setcc, then reuse the input setcc or use a new one with
10002 // the inverted condition.
10003 if (Op0.getOpcode() == X86ISD::SETCC) {
10004 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10005 bool Invert = (CC == ISD::SETNE) ^
10006 cast<ConstantSDNode>(Op1)->isNullValue();
10007 if (!Invert) return Op0;
10009 CCode = X86::GetOppositeBranchCondition(CCode);
10010 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10011 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10015 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10016 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10017 if (X86CC == X86::COND_INVALID)
10020 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10021 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10022 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10023 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10026 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10027 static bool isX86LogicalCmp(SDValue Op) {
10028 unsigned Opc = Op.getNode()->getOpcode();
10029 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10030 Opc == X86ISD::SAHF)
10032 if (Op.getResNo() == 1 &&
10033 (Opc == X86ISD::ADD ||
10034 Opc == X86ISD::SUB ||
10035 Opc == X86ISD::ADC ||
10036 Opc == X86ISD::SBB ||
10037 Opc == X86ISD::SMUL ||
10038 Opc == X86ISD::UMUL ||
10039 Opc == X86ISD::INC ||
10040 Opc == X86ISD::DEC ||
10041 Opc == X86ISD::OR ||
10042 Opc == X86ISD::XOR ||
10043 Opc == X86ISD::AND))
10046 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10052 static bool isZero(SDValue V) {
10053 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10054 return C && C->isNullValue();
10057 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10058 if (V.getOpcode() != ISD::TRUNCATE)
10061 SDValue VOp0 = V.getOperand(0);
10062 unsigned InBits = VOp0.getValueSizeInBits();
10063 unsigned Bits = V.getValueSizeInBits();
10064 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10067 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10068 bool addTest = true;
10069 SDValue Cond = Op.getOperand(0);
10070 SDValue Op1 = Op.getOperand(1);
10071 SDValue Op2 = Op.getOperand(2);
10073 EVT VT = Op1.getValueType();
10076 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10077 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10078 // sequence later on.
10079 if (Cond.getOpcode() == ISD::SETCC &&
10080 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10081 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10082 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10083 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10084 int SSECC = translateX86FSETCC(
10085 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10088 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10089 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10090 DAG.getConstant(SSECC, MVT::i8));
10091 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10092 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10093 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10097 if (Cond.getOpcode() == ISD::SETCC) {
10098 SDValue NewCond = LowerSETCC(Cond, DAG);
10099 if (NewCond.getNode())
10103 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10104 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10105 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10106 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10107 if (Cond.getOpcode() == X86ISD::SETCC &&
10108 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10109 isZero(Cond.getOperand(1).getOperand(1))) {
10110 SDValue Cmp = Cond.getOperand(1);
10112 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10114 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10115 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10116 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10118 SDValue CmpOp0 = Cmp.getOperand(0);
10119 // Apply further optimizations for special cases
10120 // (select (x != 0), -1, 0) -> neg & sbb
10121 // (select (x == 0), 0, -1) -> neg & sbb
10122 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10123 if (YC->isNullValue() &&
10124 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10125 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10126 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10127 DAG.getConstant(0, CmpOp0.getValueType()),
10129 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10130 DAG.getConstant(X86::COND_B, MVT::i8),
10131 SDValue(Neg.getNode(), 1));
10135 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10136 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10137 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10139 SDValue Res = // Res = 0 or -1.
10140 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10141 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10143 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10144 Res = DAG.getNOT(DL, Res, Res.getValueType());
10146 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10147 if (N2C == 0 || !N2C->isNullValue())
10148 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10153 // Look past (and (setcc_carry (cmp ...)), 1).
10154 if (Cond.getOpcode() == ISD::AND &&
10155 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10156 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10157 if (C && C->getAPIntValue() == 1)
10158 Cond = Cond.getOperand(0);
10161 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10162 // setting operand in place of the X86ISD::SETCC.
10163 unsigned CondOpcode = Cond.getOpcode();
10164 if (CondOpcode == X86ISD::SETCC ||
10165 CondOpcode == X86ISD::SETCC_CARRY) {
10166 CC = Cond.getOperand(0);
10168 SDValue Cmp = Cond.getOperand(1);
10169 unsigned Opc = Cmp.getOpcode();
10170 MVT VT = Op.getSimpleValueType();
10172 bool IllegalFPCMov = false;
10173 if (VT.isFloatingPoint() && !VT.isVector() &&
10174 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10175 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10177 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10178 Opc == X86ISD::BT) { // FIXME
10182 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10183 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10184 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10185 Cond.getOperand(0).getValueType() != MVT::i8)) {
10186 SDValue LHS = Cond.getOperand(0);
10187 SDValue RHS = Cond.getOperand(1);
10188 unsigned X86Opcode;
10191 switch (CondOpcode) {
10192 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10193 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10194 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10195 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10196 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10197 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10198 default: llvm_unreachable("unexpected overflowing operator");
10200 if (CondOpcode == ISD::UMULO)
10201 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10204 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10206 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10208 if (CondOpcode == ISD::UMULO)
10209 Cond = X86Op.getValue(2);
10211 Cond = X86Op.getValue(1);
10213 CC = DAG.getConstant(X86Cond, MVT::i8);
10218 // Look pass the truncate if the high bits are known zero.
10219 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10220 Cond = Cond.getOperand(0);
10222 // We know the result of AND is compared against zero. Try to match
10224 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10225 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10226 if (NewSetCC.getNode()) {
10227 CC = NewSetCC.getOperand(0);
10228 Cond = NewSetCC.getOperand(1);
10235 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10236 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10239 // a < b ? -1 : 0 -> RES = ~setcc_carry
10240 // a < b ? 0 : -1 -> RES = setcc_carry
10241 // a >= b ? -1 : 0 -> RES = setcc_carry
10242 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10243 if (Cond.getOpcode() == X86ISD::SUB) {
10244 Cond = ConvertCmpIfNecessary(Cond, DAG);
10245 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10247 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10248 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10249 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10250 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10251 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10252 return DAG.getNOT(DL, Res, Res.getValueType());
10257 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10258 // widen the cmov and push the truncate through. This avoids introducing a new
10259 // branch during isel and doesn't add any extensions.
10260 if (Op.getValueType() == MVT::i8 &&
10261 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10262 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10263 if (T1.getValueType() == T2.getValueType() &&
10264 // Blacklist CopyFromReg to avoid partial register stalls.
10265 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10266 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10267 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10268 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10272 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10273 // condition is true.
10274 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10275 SDValue Ops[] = { Op2, Op1, CC, Cond };
10276 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10279 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10280 MVT VT = Op->getSimpleValueType(0);
10281 SDValue In = Op->getOperand(0);
10282 MVT InVT = In.getSimpleValueType();
10285 if (InVT.getVectorElementType().getSizeInBits() >=8 &&
10286 VT.getVectorElementType().getSizeInBits() >= 32)
10287 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10289 if (InVT.getVectorElementType() == MVT::i1) {
10290 unsigned int NumElts = InVT.getVectorNumElements();
10291 assert ((NumElts == 8 || NumElts == 16) &&
10292 "Unsupported SIGN_EXTEND operation");
10293 if (VT.getVectorElementType().getSizeInBits() >= 32) {
10295 ConstantInt::get(*DAG.getContext(),
10296 (NumElts == 8)? APInt(64, ~0ULL): APInt(32, ~0U));
10297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10298 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10299 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10300 SDValue Ld = DAG.getLoad(VT.getScalarType(), dl, DAG.getEntryNode(), CP,
10301 MachinePointerInfo::getConstantPool(),
10302 false, false, false, Alignment);
10303 return DAG.getNode(X86ISD::VBROADCASTM, dl, VT, In, Ld);
10309 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10310 SelectionDAG &DAG) {
10311 MVT VT = Op->getSimpleValueType(0);
10312 SDValue In = Op->getOperand(0);
10313 MVT InVT = In.getSimpleValueType();
10316 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10317 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10319 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10320 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10323 if (Subtarget->hasInt256())
10324 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10326 // Optimize vectors in AVX mode
10327 // Sign extend v8i16 to v8i32 and
10330 // Divide input vector into two parts
10331 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10332 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10333 // concat the vectors to original VT
10335 unsigned NumElems = InVT.getVectorNumElements();
10336 SDValue Undef = DAG.getUNDEF(InVT);
10338 SmallVector<int,8> ShufMask1(NumElems, -1);
10339 for (unsigned i = 0; i != NumElems/2; ++i)
10342 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10344 SmallVector<int,8> ShufMask2(NumElems, -1);
10345 for (unsigned i = 0; i != NumElems/2; ++i)
10346 ShufMask2[i] = i + NumElems/2;
10348 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10350 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10351 VT.getVectorNumElements()/2);
10353 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10354 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10356 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10359 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10360 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10361 // from the AND / OR.
10362 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10363 Opc = Op.getOpcode();
10364 if (Opc != ISD::OR && Opc != ISD::AND)
10366 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10367 Op.getOperand(0).hasOneUse() &&
10368 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10369 Op.getOperand(1).hasOneUse());
10372 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10373 // 1 and that the SETCC node has a single use.
10374 static bool isXor1OfSetCC(SDValue Op) {
10375 if (Op.getOpcode() != ISD::XOR)
10377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10378 if (N1C && N1C->getAPIntValue() == 1) {
10379 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10380 Op.getOperand(0).hasOneUse();
10385 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10386 bool addTest = true;
10387 SDValue Chain = Op.getOperand(0);
10388 SDValue Cond = Op.getOperand(1);
10389 SDValue Dest = Op.getOperand(2);
10392 bool Inverted = false;
10394 if (Cond.getOpcode() == ISD::SETCC) {
10395 // Check for setcc([su]{add,sub,mul}o == 0).
10396 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10397 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10398 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10399 Cond.getOperand(0).getResNo() == 1 &&
10400 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10401 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10402 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10403 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10404 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10405 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10407 Cond = Cond.getOperand(0);
10409 SDValue NewCond = LowerSETCC(Cond, DAG);
10410 if (NewCond.getNode())
10415 // FIXME: LowerXALUO doesn't handle these!!
10416 else if (Cond.getOpcode() == X86ISD::ADD ||
10417 Cond.getOpcode() == X86ISD::SUB ||
10418 Cond.getOpcode() == X86ISD::SMUL ||
10419 Cond.getOpcode() == X86ISD::UMUL)
10420 Cond = LowerXALUO(Cond, DAG);
10423 // Look pass (and (setcc_carry (cmp ...)), 1).
10424 if (Cond.getOpcode() == ISD::AND &&
10425 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10426 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10427 if (C && C->getAPIntValue() == 1)
10428 Cond = Cond.getOperand(0);
10431 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10432 // setting operand in place of the X86ISD::SETCC.
10433 unsigned CondOpcode = Cond.getOpcode();
10434 if (CondOpcode == X86ISD::SETCC ||
10435 CondOpcode == X86ISD::SETCC_CARRY) {
10436 CC = Cond.getOperand(0);
10438 SDValue Cmp = Cond.getOperand(1);
10439 unsigned Opc = Cmp.getOpcode();
10440 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10441 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10445 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10449 // These can only come from an arithmetic instruction with overflow,
10450 // e.g. SADDO, UADDO.
10451 Cond = Cond.getNode()->getOperand(1);
10457 CondOpcode = Cond.getOpcode();
10458 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10459 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10460 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10461 Cond.getOperand(0).getValueType() != MVT::i8)) {
10462 SDValue LHS = Cond.getOperand(0);
10463 SDValue RHS = Cond.getOperand(1);
10464 unsigned X86Opcode;
10467 switch (CondOpcode) {
10468 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10469 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10470 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10471 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10472 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10473 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10474 default: llvm_unreachable("unexpected overflowing operator");
10477 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10478 if (CondOpcode == ISD::UMULO)
10479 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10482 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10484 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10486 if (CondOpcode == ISD::UMULO)
10487 Cond = X86Op.getValue(2);
10489 Cond = X86Op.getValue(1);
10491 CC = DAG.getConstant(X86Cond, MVT::i8);
10495 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10496 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10497 if (CondOpc == ISD::OR) {
10498 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10499 // two branches instead of an explicit OR instruction with a
10501 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10502 isX86LogicalCmp(Cmp)) {
10503 CC = Cond.getOperand(0).getOperand(0);
10504 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10505 Chain, Dest, CC, Cmp);
10506 CC = Cond.getOperand(1).getOperand(0);
10510 } else { // ISD::AND
10511 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10512 // two branches instead of an explicit AND instruction with a
10513 // separate test. However, we only do this if this block doesn't
10514 // have a fall-through edge, because this requires an explicit
10515 // jmp when the condition is false.
10516 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10517 isX86LogicalCmp(Cmp) &&
10518 Op.getNode()->hasOneUse()) {
10519 X86::CondCode CCode =
10520 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10521 CCode = X86::GetOppositeBranchCondition(CCode);
10522 CC = DAG.getConstant(CCode, MVT::i8);
10523 SDNode *User = *Op.getNode()->use_begin();
10524 // Look for an unconditional branch following this conditional branch.
10525 // We need this because we need to reverse the successors in order
10526 // to implement FCMP_OEQ.
10527 if (User->getOpcode() == ISD::BR) {
10528 SDValue FalseBB = User->getOperand(1);
10530 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10531 assert(NewBR == User);
10535 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10536 Chain, Dest, CC, Cmp);
10537 X86::CondCode CCode =
10538 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10539 CCode = X86::GetOppositeBranchCondition(CCode);
10540 CC = DAG.getConstant(CCode, MVT::i8);
10546 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10547 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10548 // It should be transformed during dag combiner except when the condition
10549 // is set by a arithmetics with overflow node.
10550 X86::CondCode CCode =
10551 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10552 CCode = X86::GetOppositeBranchCondition(CCode);
10553 CC = DAG.getConstant(CCode, MVT::i8);
10554 Cond = Cond.getOperand(0).getOperand(1);
10556 } else if (Cond.getOpcode() == ISD::SETCC &&
10557 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10558 // For FCMP_OEQ, we can emit
10559 // two branches instead of an explicit AND instruction with a
10560 // separate test. However, we only do this if this block doesn't
10561 // have a fall-through edge, because this requires an explicit
10562 // jmp when the condition is false.
10563 if (Op.getNode()->hasOneUse()) {
10564 SDNode *User = *Op.getNode()->use_begin();
10565 // Look for an unconditional branch following this conditional branch.
10566 // We need this because we need to reverse the successors in order
10567 // to implement FCMP_OEQ.
10568 if (User->getOpcode() == ISD::BR) {
10569 SDValue FalseBB = User->getOperand(1);
10571 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10572 assert(NewBR == User);
10576 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10577 Cond.getOperand(0), Cond.getOperand(1));
10578 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10579 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10580 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10581 Chain, Dest, CC, Cmp);
10582 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10587 } else if (Cond.getOpcode() == ISD::SETCC &&
10588 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10589 // For FCMP_UNE, we can emit
10590 // two branches instead of an explicit AND instruction with a
10591 // separate test. However, we only do this if this block doesn't
10592 // have a fall-through edge, because this requires an explicit
10593 // jmp when the condition is false.
10594 if (Op.getNode()->hasOneUse()) {
10595 SDNode *User = *Op.getNode()->use_begin();
10596 // Look for an unconditional branch following this conditional branch.
10597 // We need this because we need to reverse the successors in order
10598 // to implement FCMP_UNE.
10599 if (User->getOpcode() == ISD::BR) {
10600 SDValue FalseBB = User->getOperand(1);
10602 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10603 assert(NewBR == User);
10606 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10607 Cond.getOperand(0), Cond.getOperand(1));
10608 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10609 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10610 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10611 Chain, Dest, CC, Cmp);
10612 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10622 // Look pass the truncate if the high bits are known zero.
10623 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10624 Cond = Cond.getOperand(0);
10626 // We know the result of AND is compared against zero. Try to match
10628 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10629 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10630 if (NewSetCC.getNode()) {
10631 CC = NewSetCC.getOperand(0);
10632 Cond = NewSetCC.getOperand(1);
10639 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10640 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10642 Cond = ConvertCmpIfNecessary(Cond, DAG);
10643 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10644 Chain, Dest, CC, Cond);
10647 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10648 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10649 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10650 // that the guard pages used by the OS virtual memory manager are allocated in
10651 // correct sequence.
10653 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10654 SelectionDAG &DAG) const {
10655 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10656 getTargetMachine().Options.EnableSegmentedStacks) &&
10657 "This should be used only on Windows targets or when segmented stacks "
10659 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10663 SDValue Chain = Op.getOperand(0);
10664 SDValue Size = Op.getOperand(1);
10665 // FIXME: Ensure alignment here
10667 bool Is64Bit = Subtarget->is64Bit();
10668 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10670 if (getTargetMachine().Options.EnableSegmentedStacks) {
10671 MachineFunction &MF = DAG.getMachineFunction();
10672 MachineRegisterInfo &MRI = MF.getRegInfo();
10675 // The 64 bit implementation of segmented stacks needs to clobber both r10
10676 // r11. This makes it impossible to use it along with nested parameters.
10677 const Function *F = MF.getFunction();
10679 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10681 if (I->hasNestAttr())
10682 report_fatal_error("Cannot use segmented stacks with functions that "
10683 "have nested arguments.");
10686 const TargetRegisterClass *AddrRegClass =
10687 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10688 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10689 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10690 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10691 DAG.getRegister(Vreg, SPTy));
10692 SDValue Ops1[2] = { Value, Chain };
10693 return DAG.getMergeValues(Ops1, 2, dl);
10696 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10698 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10699 Flag = Chain.getValue(1);
10700 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10702 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10703 Flag = Chain.getValue(1);
10705 const X86RegisterInfo *RegInfo =
10706 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10707 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10710 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10711 return DAG.getMergeValues(Ops1, 2, dl);
10715 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10716 MachineFunction &MF = DAG.getMachineFunction();
10717 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10719 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10722 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10723 // vastart just stores the address of the VarArgsFrameIndex slot into the
10724 // memory location argument.
10725 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10727 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10728 MachinePointerInfo(SV), false, false, 0);
10732 // gp_offset (0 - 6 * 8)
10733 // fp_offset (48 - 48 + 8 * 16)
10734 // overflow_arg_area (point to parameters coming in memory).
10736 SmallVector<SDValue, 8> MemOps;
10737 SDValue FIN = Op.getOperand(1);
10739 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10740 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10742 FIN, MachinePointerInfo(SV), false, false, 0);
10743 MemOps.push_back(Store);
10746 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10747 FIN, DAG.getIntPtrConstant(4));
10748 Store = DAG.getStore(Op.getOperand(0), DL,
10749 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10751 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10752 MemOps.push_back(Store);
10754 // Store ptr to overflow_arg_area
10755 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10756 FIN, DAG.getIntPtrConstant(4));
10757 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10759 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10760 MachinePointerInfo(SV, 8),
10762 MemOps.push_back(Store);
10764 // Store ptr to reg_save_area.
10765 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10766 FIN, DAG.getIntPtrConstant(8));
10767 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10769 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10770 MachinePointerInfo(SV, 16), false, false, 0);
10771 MemOps.push_back(Store);
10772 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10773 &MemOps[0], MemOps.size());
10776 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10777 assert(Subtarget->is64Bit() &&
10778 "LowerVAARG only handles 64-bit va_arg!");
10779 assert((Subtarget->isTargetLinux() ||
10780 Subtarget->isTargetDarwin()) &&
10781 "Unhandled target in LowerVAARG");
10782 assert(Op.getNode()->getNumOperands() == 4);
10783 SDValue Chain = Op.getOperand(0);
10784 SDValue SrcPtr = Op.getOperand(1);
10785 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10786 unsigned Align = Op.getConstantOperandVal(3);
10789 EVT ArgVT = Op.getNode()->getValueType(0);
10790 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10791 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10794 // Decide which area this value should be read from.
10795 // TODO: Implement the AMD64 ABI in its entirety. This simple
10796 // selection mechanism works only for the basic types.
10797 if (ArgVT == MVT::f80) {
10798 llvm_unreachable("va_arg for f80 not yet implemented");
10799 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10800 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10801 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10802 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10804 llvm_unreachable("Unhandled argument type in LowerVAARG");
10807 if (ArgMode == 2) {
10808 // Sanity Check: Make sure using fp_offset makes sense.
10809 assert(!getTargetMachine().Options.UseSoftFloat &&
10810 !(DAG.getMachineFunction()
10811 .getFunction()->getAttributes()
10812 .hasAttribute(AttributeSet::FunctionIndex,
10813 Attribute::NoImplicitFloat)) &&
10814 Subtarget->hasSSE1());
10817 // Insert VAARG_64 node into the DAG
10818 // VAARG_64 returns two values: Variable Argument Address, Chain
10819 SmallVector<SDValue, 11> InstOps;
10820 InstOps.push_back(Chain);
10821 InstOps.push_back(SrcPtr);
10822 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10823 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10824 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10825 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10826 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10827 VTs, &InstOps[0], InstOps.size(),
10829 MachinePointerInfo(SV),
10831 /*Volatile=*/false,
10833 /*WriteMem=*/true);
10834 Chain = VAARG.getValue(1);
10836 // Load the next argument and return it
10837 return DAG.getLoad(ArgVT, dl,
10840 MachinePointerInfo(),
10841 false, false, false, 0);
10844 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10845 SelectionDAG &DAG) {
10846 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10847 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10848 SDValue Chain = Op.getOperand(0);
10849 SDValue DstPtr = Op.getOperand(1);
10850 SDValue SrcPtr = Op.getOperand(2);
10851 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10852 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10855 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10856 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10858 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10861 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10862 // may or may not be a constant. Takes immediate version of shift as input.
10863 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10864 SDValue SrcOp, SDValue ShAmt,
10865 SelectionDAG &DAG) {
10866 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10868 if (isa<ConstantSDNode>(ShAmt)) {
10869 // Constant may be a TargetConstant. Use a regular constant.
10870 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10872 default: llvm_unreachable("Unknown target vector shift node");
10873 case X86ISD::VSHLI:
10874 case X86ISD::VSRLI:
10875 case X86ISD::VSRAI:
10876 return DAG.getNode(Opc, dl, VT, SrcOp,
10877 DAG.getConstant(ShiftAmt, MVT::i32));
10881 // Change opcode to non-immediate version
10883 default: llvm_unreachable("Unknown target vector shift node");
10884 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10885 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10886 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10889 // Need to build a vector containing shift amount
10890 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10893 ShOps[1] = DAG.getConstant(0, MVT::i32);
10894 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10895 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10897 // The return type has to be a 128-bit type with the same element
10898 // type as the input type.
10899 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10900 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10902 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10903 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10906 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10908 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10910 default: return SDValue(); // Don't custom lower most intrinsics.
10911 // Comparison intrinsics.
10912 case Intrinsic::x86_sse_comieq_ss:
10913 case Intrinsic::x86_sse_comilt_ss:
10914 case Intrinsic::x86_sse_comile_ss:
10915 case Intrinsic::x86_sse_comigt_ss:
10916 case Intrinsic::x86_sse_comige_ss:
10917 case Intrinsic::x86_sse_comineq_ss:
10918 case Intrinsic::x86_sse_ucomieq_ss:
10919 case Intrinsic::x86_sse_ucomilt_ss:
10920 case Intrinsic::x86_sse_ucomile_ss:
10921 case Intrinsic::x86_sse_ucomigt_ss:
10922 case Intrinsic::x86_sse_ucomige_ss:
10923 case Intrinsic::x86_sse_ucomineq_ss:
10924 case Intrinsic::x86_sse2_comieq_sd:
10925 case Intrinsic::x86_sse2_comilt_sd:
10926 case Intrinsic::x86_sse2_comile_sd:
10927 case Intrinsic::x86_sse2_comigt_sd:
10928 case Intrinsic::x86_sse2_comige_sd:
10929 case Intrinsic::x86_sse2_comineq_sd:
10930 case Intrinsic::x86_sse2_ucomieq_sd:
10931 case Intrinsic::x86_sse2_ucomilt_sd:
10932 case Intrinsic::x86_sse2_ucomile_sd:
10933 case Intrinsic::x86_sse2_ucomigt_sd:
10934 case Intrinsic::x86_sse2_ucomige_sd:
10935 case Intrinsic::x86_sse2_ucomineq_sd: {
10939 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10940 case Intrinsic::x86_sse_comieq_ss:
10941 case Intrinsic::x86_sse2_comieq_sd:
10942 Opc = X86ISD::COMI;
10945 case Intrinsic::x86_sse_comilt_ss:
10946 case Intrinsic::x86_sse2_comilt_sd:
10947 Opc = X86ISD::COMI;
10950 case Intrinsic::x86_sse_comile_ss:
10951 case Intrinsic::x86_sse2_comile_sd:
10952 Opc = X86ISD::COMI;
10955 case Intrinsic::x86_sse_comigt_ss:
10956 case Intrinsic::x86_sse2_comigt_sd:
10957 Opc = X86ISD::COMI;
10960 case Intrinsic::x86_sse_comige_ss:
10961 case Intrinsic::x86_sse2_comige_sd:
10962 Opc = X86ISD::COMI;
10965 case Intrinsic::x86_sse_comineq_ss:
10966 case Intrinsic::x86_sse2_comineq_sd:
10967 Opc = X86ISD::COMI;
10970 case Intrinsic::x86_sse_ucomieq_ss:
10971 case Intrinsic::x86_sse2_ucomieq_sd:
10972 Opc = X86ISD::UCOMI;
10975 case Intrinsic::x86_sse_ucomilt_ss:
10976 case Intrinsic::x86_sse2_ucomilt_sd:
10977 Opc = X86ISD::UCOMI;
10980 case Intrinsic::x86_sse_ucomile_ss:
10981 case Intrinsic::x86_sse2_ucomile_sd:
10982 Opc = X86ISD::UCOMI;
10985 case Intrinsic::x86_sse_ucomigt_ss:
10986 case Intrinsic::x86_sse2_ucomigt_sd:
10987 Opc = X86ISD::UCOMI;
10990 case Intrinsic::x86_sse_ucomige_ss:
10991 case Intrinsic::x86_sse2_ucomige_sd:
10992 Opc = X86ISD::UCOMI;
10995 case Intrinsic::x86_sse_ucomineq_ss:
10996 case Intrinsic::x86_sse2_ucomineq_sd:
10997 Opc = X86ISD::UCOMI;
11002 SDValue LHS = Op.getOperand(1);
11003 SDValue RHS = Op.getOperand(2);
11004 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11005 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11006 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11007 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11008 DAG.getConstant(X86CC, MVT::i8), Cond);
11009 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11012 // Arithmetic intrinsics.
11013 case Intrinsic::x86_sse2_pmulu_dq:
11014 case Intrinsic::x86_avx2_pmulu_dq:
11015 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11016 Op.getOperand(1), Op.getOperand(2));
11018 // SSE2/AVX2 sub with unsigned saturation intrinsics
11019 case Intrinsic::x86_sse2_psubus_b:
11020 case Intrinsic::x86_sse2_psubus_w:
11021 case Intrinsic::x86_avx2_psubus_b:
11022 case Intrinsic::x86_avx2_psubus_w:
11023 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11024 Op.getOperand(1), Op.getOperand(2));
11026 // SSE3/AVX horizontal add/sub intrinsics
11027 case Intrinsic::x86_sse3_hadd_ps:
11028 case Intrinsic::x86_sse3_hadd_pd:
11029 case Intrinsic::x86_avx_hadd_ps_256:
11030 case Intrinsic::x86_avx_hadd_pd_256:
11031 case Intrinsic::x86_sse3_hsub_ps:
11032 case Intrinsic::x86_sse3_hsub_pd:
11033 case Intrinsic::x86_avx_hsub_ps_256:
11034 case Intrinsic::x86_avx_hsub_pd_256:
11035 case Intrinsic::x86_ssse3_phadd_w_128:
11036 case Intrinsic::x86_ssse3_phadd_d_128:
11037 case Intrinsic::x86_avx2_phadd_w:
11038 case Intrinsic::x86_avx2_phadd_d:
11039 case Intrinsic::x86_ssse3_phsub_w_128:
11040 case Intrinsic::x86_ssse3_phsub_d_128:
11041 case Intrinsic::x86_avx2_phsub_w:
11042 case Intrinsic::x86_avx2_phsub_d: {
11045 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11046 case Intrinsic::x86_sse3_hadd_ps:
11047 case Intrinsic::x86_sse3_hadd_pd:
11048 case Intrinsic::x86_avx_hadd_ps_256:
11049 case Intrinsic::x86_avx_hadd_pd_256:
11050 Opcode = X86ISD::FHADD;
11052 case Intrinsic::x86_sse3_hsub_ps:
11053 case Intrinsic::x86_sse3_hsub_pd:
11054 case Intrinsic::x86_avx_hsub_ps_256:
11055 case Intrinsic::x86_avx_hsub_pd_256:
11056 Opcode = X86ISD::FHSUB;
11058 case Intrinsic::x86_ssse3_phadd_w_128:
11059 case Intrinsic::x86_ssse3_phadd_d_128:
11060 case Intrinsic::x86_avx2_phadd_w:
11061 case Intrinsic::x86_avx2_phadd_d:
11062 Opcode = X86ISD::HADD;
11064 case Intrinsic::x86_ssse3_phsub_w_128:
11065 case Intrinsic::x86_ssse3_phsub_d_128:
11066 case Intrinsic::x86_avx2_phsub_w:
11067 case Intrinsic::x86_avx2_phsub_d:
11068 Opcode = X86ISD::HSUB;
11071 return DAG.getNode(Opcode, dl, Op.getValueType(),
11072 Op.getOperand(1), Op.getOperand(2));
11075 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11076 case Intrinsic::x86_sse2_pmaxu_b:
11077 case Intrinsic::x86_sse41_pmaxuw:
11078 case Intrinsic::x86_sse41_pmaxud:
11079 case Intrinsic::x86_avx2_pmaxu_b:
11080 case Intrinsic::x86_avx2_pmaxu_w:
11081 case Intrinsic::x86_avx2_pmaxu_d:
11082 case Intrinsic::x86_sse2_pminu_b:
11083 case Intrinsic::x86_sse41_pminuw:
11084 case Intrinsic::x86_sse41_pminud:
11085 case Intrinsic::x86_avx2_pminu_b:
11086 case Intrinsic::x86_avx2_pminu_w:
11087 case Intrinsic::x86_avx2_pminu_d:
11088 case Intrinsic::x86_sse41_pmaxsb:
11089 case Intrinsic::x86_sse2_pmaxs_w:
11090 case Intrinsic::x86_sse41_pmaxsd:
11091 case Intrinsic::x86_avx2_pmaxs_b:
11092 case Intrinsic::x86_avx2_pmaxs_w:
11093 case Intrinsic::x86_avx2_pmaxs_d:
11094 case Intrinsic::x86_sse41_pminsb:
11095 case Intrinsic::x86_sse2_pmins_w:
11096 case Intrinsic::x86_sse41_pminsd:
11097 case Intrinsic::x86_avx2_pmins_b:
11098 case Intrinsic::x86_avx2_pmins_w:
11099 case Intrinsic::x86_avx2_pmins_d: {
11102 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11103 case Intrinsic::x86_sse2_pmaxu_b:
11104 case Intrinsic::x86_sse41_pmaxuw:
11105 case Intrinsic::x86_sse41_pmaxud:
11106 case Intrinsic::x86_avx2_pmaxu_b:
11107 case Intrinsic::x86_avx2_pmaxu_w:
11108 case Intrinsic::x86_avx2_pmaxu_d:
11109 Opcode = X86ISD::UMAX;
11111 case Intrinsic::x86_sse2_pminu_b:
11112 case Intrinsic::x86_sse41_pminuw:
11113 case Intrinsic::x86_sse41_pminud:
11114 case Intrinsic::x86_avx2_pminu_b:
11115 case Intrinsic::x86_avx2_pminu_w:
11116 case Intrinsic::x86_avx2_pminu_d:
11117 Opcode = X86ISD::UMIN;
11119 case Intrinsic::x86_sse41_pmaxsb:
11120 case Intrinsic::x86_sse2_pmaxs_w:
11121 case Intrinsic::x86_sse41_pmaxsd:
11122 case Intrinsic::x86_avx2_pmaxs_b:
11123 case Intrinsic::x86_avx2_pmaxs_w:
11124 case Intrinsic::x86_avx2_pmaxs_d:
11125 Opcode = X86ISD::SMAX;
11127 case Intrinsic::x86_sse41_pminsb:
11128 case Intrinsic::x86_sse2_pmins_w:
11129 case Intrinsic::x86_sse41_pminsd:
11130 case Intrinsic::x86_avx2_pmins_b:
11131 case Intrinsic::x86_avx2_pmins_w:
11132 case Intrinsic::x86_avx2_pmins_d:
11133 Opcode = X86ISD::SMIN;
11136 return DAG.getNode(Opcode, dl, Op.getValueType(),
11137 Op.getOperand(1), Op.getOperand(2));
11140 // SSE/SSE2/AVX floating point max/min intrinsics.
11141 case Intrinsic::x86_sse_max_ps:
11142 case Intrinsic::x86_sse2_max_pd:
11143 case Intrinsic::x86_avx_max_ps_256:
11144 case Intrinsic::x86_avx_max_pd_256:
11145 case Intrinsic::x86_sse_min_ps:
11146 case Intrinsic::x86_sse2_min_pd:
11147 case Intrinsic::x86_avx_min_ps_256:
11148 case Intrinsic::x86_avx_min_pd_256: {
11151 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11152 case Intrinsic::x86_sse_max_ps:
11153 case Intrinsic::x86_sse2_max_pd:
11154 case Intrinsic::x86_avx_max_ps_256:
11155 case Intrinsic::x86_avx_max_pd_256:
11156 Opcode = X86ISD::FMAX;
11158 case Intrinsic::x86_sse_min_ps:
11159 case Intrinsic::x86_sse2_min_pd:
11160 case Intrinsic::x86_avx_min_ps_256:
11161 case Intrinsic::x86_avx_min_pd_256:
11162 Opcode = X86ISD::FMIN;
11165 return DAG.getNode(Opcode, dl, Op.getValueType(),
11166 Op.getOperand(1), Op.getOperand(2));
11169 // AVX2 variable shift intrinsics
11170 case Intrinsic::x86_avx2_psllv_d:
11171 case Intrinsic::x86_avx2_psllv_q:
11172 case Intrinsic::x86_avx2_psllv_d_256:
11173 case Intrinsic::x86_avx2_psllv_q_256:
11174 case Intrinsic::x86_avx2_psrlv_d:
11175 case Intrinsic::x86_avx2_psrlv_q:
11176 case Intrinsic::x86_avx2_psrlv_d_256:
11177 case Intrinsic::x86_avx2_psrlv_q_256:
11178 case Intrinsic::x86_avx2_psrav_d:
11179 case Intrinsic::x86_avx2_psrav_d_256: {
11182 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11183 case Intrinsic::x86_avx2_psllv_d:
11184 case Intrinsic::x86_avx2_psllv_q:
11185 case Intrinsic::x86_avx2_psllv_d_256:
11186 case Intrinsic::x86_avx2_psllv_q_256:
11189 case Intrinsic::x86_avx2_psrlv_d:
11190 case Intrinsic::x86_avx2_psrlv_q:
11191 case Intrinsic::x86_avx2_psrlv_d_256:
11192 case Intrinsic::x86_avx2_psrlv_q_256:
11195 case Intrinsic::x86_avx2_psrav_d:
11196 case Intrinsic::x86_avx2_psrav_d_256:
11200 return DAG.getNode(Opcode, dl, Op.getValueType(),
11201 Op.getOperand(1), Op.getOperand(2));
11204 case Intrinsic::x86_ssse3_pshuf_b_128:
11205 case Intrinsic::x86_avx2_pshuf_b:
11206 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11207 Op.getOperand(1), Op.getOperand(2));
11209 case Intrinsic::x86_ssse3_psign_b_128:
11210 case Intrinsic::x86_ssse3_psign_w_128:
11211 case Intrinsic::x86_ssse3_psign_d_128:
11212 case Intrinsic::x86_avx2_psign_b:
11213 case Intrinsic::x86_avx2_psign_w:
11214 case Intrinsic::x86_avx2_psign_d:
11215 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11216 Op.getOperand(1), Op.getOperand(2));
11218 case Intrinsic::x86_sse41_insertps:
11219 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11220 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11222 case Intrinsic::x86_avx_vperm2f128_ps_256:
11223 case Intrinsic::x86_avx_vperm2f128_pd_256:
11224 case Intrinsic::x86_avx_vperm2f128_si_256:
11225 case Intrinsic::x86_avx2_vperm2i128:
11226 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11227 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11229 case Intrinsic::x86_avx2_permd:
11230 case Intrinsic::x86_avx2_permps:
11231 // Operands intentionally swapped. Mask is last operand to intrinsic,
11232 // but second operand for node/intruction.
11233 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11234 Op.getOperand(2), Op.getOperand(1));
11236 case Intrinsic::x86_sse_sqrt_ps:
11237 case Intrinsic::x86_sse2_sqrt_pd:
11238 case Intrinsic::x86_avx_sqrt_ps_256:
11239 case Intrinsic::x86_avx_sqrt_pd_256:
11240 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11242 // ptest and testp intrinsics. The intrinsic these come from are designed to
11243 // return an integer value, not just an instruction so lower it to the ptest
11244 // or testp pattern and a setcc for the result.
11245 case Intrinsic::x86_sse41_ptestz:
11246 case Intrinsic::x86_sse41_ptestc:
11247 case Intrinsic::x86_sse41_ptestnzc:
11248 case Intrinsic::x86_avx_ptestz_256:
11249 case Intrinsic::x86_avx_ptestc_256:
11250 case Intrinsic::x86_avx_ptestnzc_256:
11251 case Intrinsic::x86_avx_vtestz_ps:
11252 case Intrinsic::x86_avx_vtestc_ps:
11253 case Intrinsic::x86_avx_vtestnzc_ps:
11254 case Intrinsic::x86_avx_vtestz_pd:
11255 case Intrinsic::x86_avx_vtestc_pd:
11256 case Intrinsic::x86_avx_vtestnzc_pd:
11257 case Intrinsic::x86_avx_vtestz_ps_256:
11258 case Intrinsic::x86_avx_vtestc_ps_256:
11259 case Intrinsic::x86_avx_vtestnzc_ps_256:
11260 case Intrinsic::x86_avx_vtestz_pd_256:
11261 case Intrinsic::x86_avx_vtestc_pd_256:
11262 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11263 bool IsTestPacked = false;
11266 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11267 case Intrinsic::x86_avx_vtestz_ps:
11268 case Intrinsic::x86_avx_vtestz_pd:
11269 case Intrinsic::x86_avx_vtestz_ps_256:
11270 case Intrinsic::x86_avx_vtestz_pd_256:
11271 IsTestPacked = true; // Fallthrough
11272 case Intrinsic::x86_sse41_ptestz:
11273 case Intrinsic::x86_avx_ptestz_256:
11275 X86CC = X86::COND_E;
11277 case Intrinsic::x86_avx_vtestc_ps:
11278 case Intrinsic::x86_avx_vtestc_pd:
11279 case Intrinsic::x86_avx_vtestc_ps_256:
11280 case Intrinsic::x86_avx_vtestc_pd_256:
11281 IsTestPacked = true; // Fallthrough
11282 case Intrinsic::x86_sse41_ptestc:
11283 case Intrinsic::x86_avx_ptestc_256:
11285 X86CC = X86::COND_B;
11287 case Intrinsic::x86_avx_vtestnzc_ps:
11288 case Intrinsic::x86_avx_vtestnzc_pd:
11289 case Intrinsic::x86_avx_vtestnzc_ps_256:
11290 case Intrinsic::x86_avx_vtestnzc_pd_256:
11291 IsTestPacked = true; // Fallthrough
11292 case Intrinsic::x86_sse41_ptestnzc:
11293 case Intrinsic::x86_avx_ptestnzc_256:
11295 X86CC = X86::COND_A;
11299 SDValue LHS = Op.getOperand(1);
11300 SDValue RHS = Op.getOperand(2);
11301 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11302 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11303 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11304 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11305 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11307 case Intrinsic::x86_avx512_kortestz:
11308 case Intrinsic::x86_avx512_kortestc: {
11309 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11310 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11311 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11312 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11313 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11314 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11315 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11318 // SSE/AVX shift intrinsics
11319 case Intrinsic::x86_sse2_psll_w:
11320 case Intrinsic::x86_sse2_psll_d:
11321 case Intrinsic::x86_sse2_psll_q:
11322 case Intrinsic::x86_avx2_psll_w:
11323 case Intrinsic::x86_avx2_psll_d:
11324 case Intrinsic::x86_avx2_psll_q:
11325 case Intrinsic::x86_sse2_psrl_w:
11326 case Intrinsic::x86_sse2_psrl_d:
11327 case Intrinsic::x86_sse2_psrl_q:
11328 case Intrinsic::x86_avx2_psrl_w:
11329 case Intrinsic::x86_avx2_psrl_d:
11330 case Intrinsic::x86_avx2_psrl_q:
11331 case Intrinsic::x86_sse2_psra_w:
11332 case Intrinsic::x86_sse2_psra_d:
11333 case Intrinsic::x86_avx2_psra_w:
11334 case Intrinsic::x86_avx2_psra_d: {
11337 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11338 case Intrinsic::x86_sse2_psll_w:
11339 case Intrinsic::x86_sse2_psll_d:
11340 case Intrinsic::x86_sse2_psll_q:
11341 case Intrinsic::x86_avx2_psll_w:
11342 case Intrinsic::x86_avx2_psll_d:
11343 case Intrinsic::x86_avx2_psll_q:
11344 Opcode = X86ISD::VSHL;
11346 case Intrinsic::x86_sse2_psrl_w:
11347 case Intrinsic::x86_sse2_psrl_d:
11348 case Intrinsic::x86_sse2_psrl_q:
11349 case Intrinsic::x86_avx2_psrl_w:
11350 case Intrinsic::x86_avx2_psrl_d:
11351 case Intrinsic::x86_avx2_psrl_q:
11352 Opcode = X86ISD::VSRL;
11354 case Intrinsic::x86_sse2_psra_w:
11355 case Intrinsic::x86_sse2_psra_d:
11356 case Intrinsic::x86_avx2_psra_w:
11357 case Intrinsic::x86_avx2_psra_d:
11358 Opcode = X86ISD::VSRA;
11361 return DAG.getNode(Opcode, dl, Op.getValueType(),
11362 Op.getOperand(1), Op.getOperand(2));
11365 // SSE/AVX immediate shift intrinsics
11366 case Intrinsic::x86_sse2_pslli_w:
11367 case Intrinsic::x86_sse2_pslli_d:
11368 case Intrinsic::x86_sse2_pslli_q:
11369 case Intrinsic::x86_avx2_pslli_w:
11370 case Intrinsic::x86_avx2_pslli_d:
11371 case Intrinsic::x86_avx2_pslli_q:
11372 case Intrinsic::x86_sse2_psrli_w:
11373 case Intrinsic::x86_sse2_psrli_d:
11374 case Intrinsic::x86_sse2_psrli_q:
11375 case Intrinsic::x86_avx2_psrli_w:
11376 case Intrinsic::x86_avx2_psrli_d:
11377 case Intrinsic::x86_avx2_psrli_q:
11378 case Intrinsic::x86_sse2_psrai_w:
11379 case Intrinsic::x86_sse2_psrai_d:
11380 case Intrinsic::x86_avx2_psrai_w:
11381 case Intrinsic::x86_avx2_psrai_d: {
11384 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11385 case Intrinsic::x86_sse2_pslli_w:
11386 case Intrinsic::x86_sse2_pslli_d:
11387 case Intrinsic::x86_sse2_pslli_q:
11388 case Intrinsic::x86_avx2_pslli_w:
11389 case Intrinsic::x86_avx2_pslli_d:
11390 case Intrinsic::x86_avx2_pslli_q:
11391 Opcode = X86ISD::VSHLI;
11393 case Intrinsic::x86_sse2_psrli_w:
11394 case Intrinsic::x86_sse2_psrli_d:
11395 case Intrinsic::x86_sse2_psrli_q:
11396 case Intrinsic::x86_avx2_psrli_w:
11397 case Intrinsic::x86_avx2_psrli_d:
11398 case Intrinsic::x86_avx2_psrli_q:
11399 Opcode = X86ISD::VSRLI;
11401 case Intrinsic::x86_sse2_psrai_w:
11402 case Intrinsic::x86_sse2_psrai_d:
11403 case Intrinsic::x86_avx2_psrai_w:
11404 case Intrinsic::x86_avx2_psrai_d:
11405 Opcode = X86ISD::VSRAI;
11408 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11409 Op.getOperand(1), Op.getOperand(2), DAG);
11412 case Intrinsic::x86_sse42_pcmpistria128:
11413 case Intrinsic::x86_sse42_pcmpestria128:
11414 case Intrinsic::x86_sse42_pcmpistric128:
11415 case Intrinsic::x86_sse42_pcmpestric128:
11416 case Intrinsic::x86_sse42_pcmpistrio128:
11417 case Intrinsic::x86_sse42_pcmpestrio128:
11418 case Intrinsic::x86_sse42_pcmpistris128:
11419 case Intrinsic::x86_sse42_pcmpestris128:
11420 case Intrinsic::x86_sse42_pcmpistriz128:
11421 case Intrinsic::x86_sse42_pcmpestriz128: {
11425 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11426 case Intrinsic::x86_sse42_pcmpistria128:
11427 Opcode = X86ISD::PCMPISTRI;
11428 X86CC = X86::COND_A;
11430 case Intrinsic::x86_sse42_pcmpestria128:
11431 Opcode = X86ISD::PCMPESTRI;
11432 X86CC = X86::COND_A;
11434 case Intrinsic::x86_sse42_pcmpistric128:
11435 Opcode = X86ISD::PCMPISTRI;
11436 X86CC = X86::COND_B;
11438 case Intrinsic::x86_sse42_pcmpestric128:
11439 Opcode = X86ISD::PCMPESTRI;
11440 X86CC = X86::COND_B;
11442 case Intrinsic::x86_sse42_pcmpistrio128:
11443 Opcode = X86ISD::PCMPISTRI;
11444 X86CC = X86::COND_O;
11446 case Intrinsic::x86_sse42_pcmpestrio128:
11447 Opcode = X86ISD::PCMPESTRI;
11448 X86CC = X86::COND_O;
11450 case Intrinsic::x86_sse42_pcmpistris128:
11451 Opcode = X86ISD::PCMPISTRI;
11452 X86CC = X86::COND_S;
11454 case Intrinsic::x86_sse42_pcmpestris128:
11455 Opcode = X86ISD::PCMPESTRI;
11456 X86CC = X86::COND_S;
11458 case Intrinsic::x86_sse42_pcmpistriz128:
11459 Opcode = X86ISD::PCMPISTRI;
11460 X86CC = X86::COND_E;
11462 case Intrinsic::x86_sse42_pcmpestriz128:
11463 Opcode = X86ISD::PCMPESTRI;
11464 X86CC = X86::COND_E;
11467 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11468 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11469 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11470 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11471 DAG.getConstant(X86CC, MVT::i8),
11472 SDValue(PCMP.getNode(), 1));
11473 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11476 case Intrinsic::x86_sse42_pcmpistri128:
11477 case Intrinsic::x86_sse42_pcmpestri128: {
11479 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11480 Opcode = X86ISD::PCMPISTRI;
11482 Opcode = X86ISD::PCMPESTRI;
11484 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11485 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11486 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11488 case Intrinsic::x86_fma_vfmadd_ps:
11489 case Intrinsic::x86_fma_vfmadd_pd:
11490 case Intrinsic::x86_fma_vfmsub_ps:
11491 case Intrinsic::x86_fma_vfmsub_pd:
11492 case Intrinsic::x86_fma_vfnmadd_ps:
11493 case Intrinsic::x86_fma_vfnmadd_pd:
11494 case Intrinsic::x86_fma_vfnmsub_ps:
11495 case Intrinsic::x86_fma_vfnmsub_pd:
11496 case Intrinsic::x86_fma_vfmaddsub_ps:
11497 case Intrinsic::x86_fma_vfmaddsub_pd:
11498 case Intrinsic::x86_fma_vfmsubadd_ps:
11499 case Intrinsic::x86_fma_vfmsubadd_pd:
11500 case Intrinsic::x86_fma_vfmadd_ps_256:
11501 case Intrinsic::x86_fma_vfmadd_pd_256:
11502 case Intrinsic::x86_fma_vfmsub_ps_256:
11503 case Intrinsic::x86_fma_vfmsub_pd_256:
11504 case Intrinsic::x86_fma_vfnmadd_ps_256:
11505 case Intrinsic::x86_fma_vfnmadd_pd_256:
11506 case Intrinsic::x86_fma_vfnmsub_ps_256:
11507 case Intrinsic::x86_fma_vfnmsub_pd_256:
11508 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11509 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11510 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11511 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11514 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11515 case Intrinsic::x86_fma_vfmadd_ps:
11516 case Intrinsic::x86_fma_vfmadd_pd:
11517 case Intrinsic::x86_fma_vfmadd_ps_256:
11518 case Intrinsic::x86_fma_vfmadd_pd_256:
11519 Opc = X86ISD::FMADD;
11521 case Intrinsic::x86_fma_vfmsub_ps:
11522 case Intrinsic::x86_fma_vfmsub_pd:
11523 case Intrinsic::x86_fma_vfmsub_ps_256:
11524 case Intrinsic::x86_fma_vfmsub_pd_256:
11525 Opc = X86ISD::FMSUB;
11527 case Intrinsic::x86_fma_vfnmadd_ps:
11528 case Intrinsic::x86_fma_vfnmadd_pd:
11529 case Intrinsic::x86_fma_vfnmadd_ps_256:
11530 case Intrinsic::x86_fma_vfnmadd_pd_256:
11531 Opc = X86ISD::FNMADD;
11533 case Intrinsic::x86_fma_vfnmsub_ps:
11534 case Intrinsic::x86_fma_vfnmsub_pd:
11535 case Intrinsic::x86_fma_vfnmsub_ps_256:
11536 case Intrinsic::x86_fma_vfnmsub_pd_256:
11537 Opc = X86ISD::FNMSUB;
11539 case Intrinsic::x86_fma_vfmaddsub_ps:
11540 case Intrinsic::x86_fma_vfmaddsub_pd:
11541 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11542 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11543 Opc = X86ISD::FMADDSUB;
11545 case Intrinsic::x86_fma_vfmsubadd_ps:
11546 case Intrinsic::x86_fma_vfmsubadd_pd:
11547 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11548 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11549 Opc = X86ISD::FMSUBADD;
11553 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11554 Op.getOperand(2), Op.getOperand(3));
11559 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
11561 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11563 default: return SDValue(); // Don't custom lower most intrinsics.
11565 // RDRAND/RDSEED intrinsics.
11566 case Intrinsic::x86_rdrand_16:
11567 case Intrinsic::x86_rdrand_32:
11568 case Intrinsic::x86_rdrand_64:
11569 case Intrinsic::x86_rdseed_16:
11570 case Intrinsic::x86_rdseed_32:
11571 case Intrinsic::x86_rdseed_64: {
11572 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11573 IntNo == Intrinsic::x86_rdseed_32 ||
11574 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11576 // Emit the node with the right value type.
11577 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11578 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11580 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11581 // Otherwise return the value from Rand, which is always 0, casted to i32.
11582 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11583 DAG.getConstant(1, Op->getValueType(1)),
11584 DAG.getConstant(X86::COND_B, MVT::i32),
11585 SDValue(Result.getNode(), 1) };
11586 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11587 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11588 Ops, array_lengthof(Ops));
11590 // Return { result, isValid, chain }.
11591 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11592 SDValue(Result.getNode(), 2));
11595 // XTEST intrinsics.
11596 case Intrinsic::x86_xtest: {
11597 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11598 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11599 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11600 DAG.getConstant(X86::COND_NE, MVT::i8),
11602 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11603 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11604 Ret, SDValue(InTrans.getNode(), 1));
11609 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11610 SelectionDAG &DAG) const {
11611 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11612 MFI->setReturnAddressIsTaken(true);
11614 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11616 EVT PtrVT = getPointerTy();
11619 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11620 const X86RegisterInfo *RegInfo =
11621 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11622 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11623 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11624 DAG.getNode(ISD::ADD, dl, PtrVT,
11625 FrameAddr, Offset),
11626 MachinePointerInfo(), false, false, false, 0);
11629 // Just load the return address.
11630 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11631 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11632 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11635 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11636 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11637 MFI->setFrameAddressIsTaken(true);
11639 EVT VT = Op.getValueType();
11640 SDLoc dl(Op); // FIXME probably not meaningful
11641 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11642 const X86RegisterInfo *RegInfo =
11643 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11644 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11645 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11646 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11647 "Invalid Frame Register!");
11648 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11650 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11651 MachinePointerInfo(),
11652 false, false, false, 0);
11656 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11657 SelectionDAG &DAG) const {
11658 const X86RegisterInfo *RegInfo =
11659 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11660 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11663 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11664 SDValue Chain = Op.getOperand(0);
11665 SDValue Offset = Op.getOperand(1);
11666 SDValue Handler = Op.getOperand(2);
11669 EVT PtrVT = getPointerTy();
11670 const X86RegisterInfo *RegInfo =
11671 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11672 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11673 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11674 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11675 "Invalid Frame Register!");
11676 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11677 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11679 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11680 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11681 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
11682 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
11684 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
11686 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
11687 DAG.getRegister(StoreAddrReg, PtrVT));
11690 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
11691 SelectionDAG &DAG) const {
11693 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
11694 DAG.getVTList(MVT::i32, MVT::Other),
11695 Op.getOperand(0), Op.getOperand(1));
11698 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
11699 SelectionDAG &DAG) const {
11701 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
11702 Op.getOperand(0), Op.getOperand(1));
11705 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
11706 return Op.getOperand(0);
11709 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
11710 SelectionDAG &DAG) const {
11711 SDValue Root = Op.getOperand(0);
11712 SDValue Trmp = Op.getOperand(1); // trampoline
11713 SDValue FPtr = Op.getOperand(2); // nested function
11714 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
11717 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11718 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
11720 if (Subtarget->is64Bit()) {
11721 SDValue OutChains[6];
11723 // Large code-model.
11724 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11725 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11727 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
11728 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
11730 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
11732 // Load the pointer to the nested function into R11.
11733 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11734 SDValue Addr = Trmp;
11735 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11736 Addr, MachinePointerInfo(TrmpAddr),
11739 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11740 DAG.getConstant(2, MVT::i64));
11741 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11742 MachinePointerInfo(TrmpAddr, 2),
11745 // Load the 'nest' parameter value into R10.
11746 // R10 is specified in X86CallingConv.td
11747 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11748 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11749 DAG.getConstant(10, MVT::i64));
11750 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11751 Addr, MachinePointerInfo(TrmpAddr, 10),
11754 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11755 DAG.getConstant(12, MVT::i64));
11756 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11757 MachinePointerInfo(TrmpAddr, 12),
11760 // Jump to the nested function.
11761 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11762 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11763 DAG.getConstant(20, MVT::i64));
11764 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11765 Addr, MachinePointerInfo(TrmpAddr, 20),
11768 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11769 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11770 DAG.getConstant(22, MVT::i64));
11771 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11772 MachinePointerInfo(TrmpAddr, 22),
11775 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11777 const Function *Func =
11778 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11779 CallingConv::ID CC = Func->getCallingConv();
11784 llvm_unreachable("Unsupported calling convention");
11785 case CallingConv::C:
11786 case CallingConv::X86_StdCall: {
11787 // Pass 'nest' parameter in ECX.
11788 // Must be kept in sync with X86CallingConv.td
11789 NestReg = X86::ECX;
11791 // Check that ECX wasn't needed by an 'inreg' parameter.
11792 FunctionType *FTy = Func->getFunctionType();
11793 const AttributeSet &Attrs = Func->getAttributes();
11795 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11796 unsigned InRegCount = 0;
11799 for (FunctionType::param_iterator I = FTy->param_begin(),
11800 E = FTy->param_end(); I != E; ++I, ++Idx)
11801 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11802 // FIXME: should only count parameters that are lowered to integers.
11803 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11805 if (InRegCount > 2) {
11806 report_fatal_error("Nest register in use - reduce number of inreg"
11812 case CallingConv::X86_FastCall:
11813 case CallingConv::X86_ThisCall:
11814 case CallingConv::Fast:
11815 // Pass 'nest' parameter in EAX.
11816 // Must be kept in sync with X86CallingConv.td
11817 NestReg = X86::EAX;
11821 SDValue OutChains[4];
11822 SDValue Addr, Disp;
11824 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11825 DAG.getConstant(10, MVT::i32));
11826 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11828 // This is storing the opcode for MOV32ri.
11829 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11830 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11831 OutChains[0] = DAG.getStore(Root, dl,
11832 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11833 Trmp, MachinePointerInfo(TrmpAddr),
11836 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11837 DAG.getConstant(1, MVT::i32));
11838 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11839 MachinePointerInfo(TrmpAddr, 1),
11842 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11843 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11844 DAG.getConstant(5, MVT::i32));
11845 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11846 MachinePointerInfo(TrmpAddr, 5),
11849 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11850 DAG.getConstant(6, MVT::i32));
11851 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11852 MachinePointerInfo(TrmpAddr, 6),
11855 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11859 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11860 SelectionDAG &DAG) const {
11862 The rounding mode is in bits 11:10 of FPSR, and has the following
11864 00 Round to nearest
11869 FLT_ROUNDS, on the other hand, expects the following:
11876 To perform the conversion, we do:
11877 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11880 MachineFunction &MF = DAG.getMachineFunction();
11881 const TargetMachine &TM = MF.getTarget();
11882 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11883 unsigned StackAlignment = TFI.getStackAlignment();
11884 EVT VT = Op.getValueType();
11887 // Save FP Control Word to stack slot
11888 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11889 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11891 MachineMemOperand *MMO =
11892 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11893 MachineMemOperand::MOStore, 2, 2);
11895 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11896 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11897 DAG.getVTList(MVT::Other),
11898 Ops, array_lengthof(Ops), MVT::i16,
11901 // Load FP Control Word from stack slot
11902 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11903 MachinePointerInfo(), false, false, false, 0);
11905 // Transform as necessary
11907 DAG.getNode(ISD::SRL, DL, MVT::i16,
11908 DAG.getNode(ISD::AND, DL, MVT::i16,
11909 CWD, DAG.getConstant(0x800, MVT::i16)),
11910 DAG.getConstant(11, MVT::i8));
11912 DAG.getNode(ISD::SRL, DL, MVT::i16,
11913 DAG.getNode(ISD::AND, DL, MVT::i16,
11914 CWD, DAG.getConstant(0x400, MVT::i16)),
11915 DAG.getConstant(9, MVT::i8));
11918 DAG.getNode(ISD::AND, DL, MVT::i16,
11919 DAG.getNode(ISD::ADD, DL, MVT::i16,
11920 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11921 DAG.getConstant(1, MVT::i16)),
11922 DAG.getConstant(3, MVT::i16));
11924 return DAG.getNode((VT.getSizeInBits() < 16 ?
11925 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11928 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11929 EVT VT = Op.getValueType();
11931 unsigned NumBits = VT.getSizeInBits();
11934 Op = Op.getOperand(0);
11935 if (VT == MVT::i8) {
11936 // Zero extend to i32 since there is not an i8 bsr.
11938 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11941 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11942 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11943 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11945 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11948 DAG.getConstant(NumBits+NumBits-1, OpVT),
11949 DAG.getConstant(X86::COND_E, MVT::i8),
11952 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11954 // Finally xor with NumBits-1.
11955 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11958 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11962 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11963 EVT VT = Op.getValueType();
11965 unsigned NumBits = VT.getSizeInBits();
11968 Op = Op.getOperand(0);
11969 if (VT == MVT::i8) {
11970 // Zero extend to i32 since there is not an i8 bsr.
11972 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11975 // Issue a bsr (scan bits in reverse).
11976 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11977 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11979 // And xor with NumBits-1.
11980 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11983 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11987 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11988 EVT VT = Op.getValueType();
11989 unsigned NumBits = VT.getSizeInBits();
11991 Op = Op.getOperand(0);
11993 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11994 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11995 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11997 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12000 DAG.getConstant(NumBits, VT),
12001 DAG.getConstant(X86::COND_E, MVT::i8),
12004 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12007 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12008 // ones, and then concatenate the result back.
12009 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12010 EVT VT = Op.getValueType();
12012 assert(VT.is256BitVector() && VT.isInteger() &&
12013 "Unsupported value type for operation");
12015 unsigned NumElems = VT.getVectorNumElements();
12018 // Extract the LHS vectors
12019 SDValue LHS = Op.getOperand(0);
12020 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12021 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12023 // Extract the RHS vectors
12024 SDValue RHS = Op.getOperand(1);
12025 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12026 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12028 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12029 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12031 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12032 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12033 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12036 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12037 assert(Op.getValueType().is256BitVector() &&
12038 Op.getValueType().isInteger() &&
12039 "Only handle AVX 256-bit vector integer operation");
12040 return Lower256IntArith(Op, DAG);
12043 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12044 assert(Op.getValueType().is256BitVector() &&
12045 Op.getValueType().isInteger() &&
12046 "Only handle AVX 256-bit vector integer operation");
12047 return Lower256IntArith(Op, DAG);
12050 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12051 SelectionDAG &DAG) {
12053 EVT VT = Op.getValueType();
12055 // Decompose 256-bit ops into smaller 128-bit ops.
12056 if (VT.is256BitVector() && !Subtarget->hasInt256())
12057 return Lower256IntArith(Op, DAG);
12059 SDValue A = Op.getOperand(0);
12060 SDValue B = Op.getOperand(1);
12062 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12063 if (VT == MVT::v4i32) {
12064 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12065 "Should not custom lower when pmuldq is available!");
12067 // Extract the odd parts.
12068 static const int UnpackMask[] = { 1, -1, 3, -1 };
12069 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12070 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12072 // Multiply the even parts.
12073 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12074 // Now multiply odd parts.
12075 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12077 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12078 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12080 // Merge the two vectors back together with a shuffle. This expands into 2
12082 static const int ShufMask[] = { 0, 4, 2, 6 };
12083 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12086 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
12087 "Only know how to lower V2I64/V4I64 multiply");
12089 // Ahi = psrlqi(a, 32);
12090 // Bhi = psrlqi(b, 32);
12092 // AloBlo = pmuludq(a, b);
12093 // AloBhi = pmuludq(a, Bhi);
12094 // AhiBlo = pmuludq(Ahi, b);
12096 // AloBhi = psllqi(AloBhi, 32);
12097 // AhiBlo = psllqi(AhiBlo, 32);
12098 // return AloBlo + AloBhi + AhiBlo;
12100 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
12102 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
12103 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
12105 // Bit cast to 32-bit vectors for MULUDQ
12106 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
12107 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12108 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12109 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12110 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12112 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12113 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12114 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12116 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
12117 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
12119 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12120 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12123 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12124 EVT VT = Op.getValueType();
12125 EVT EltTy = VT.getVectorElementType();
12126 unsigned NumElts = VT.getVectorNumElements();
12127 SDValue N0 = Op.getOperand(0);
12130 // Lower sdiv X, pow2-const.
12131 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12135 APInt SplatValue, SplatUndef;
12136 unsigned SplatBitSize;
12138 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12140 EltTy.getSizeInBits() < SplatBitSize)
12143 if ((SplatValue != 0) &&
12144 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12145 unsigned lg2 = SplatValue.countTrailingZeros();
12146 // Splat the sign bit.
12147 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
12148 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
12149 // Add (N0 < 0) ? abs2 - 1 : 0;
12150 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
12151 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
12152 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12153 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
12154 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
12156 // If we're dividing by a positive value, we're done. Otherwise, we must
12157 // negate the result.
12158 if (SplatValue.isNonNegative())
12161 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12162 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12163 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12168 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12169 const X86Subtarget *Subtarget) {
12170 EVT VT = Op.getValueType();
12172 SDValue R = Op.getOperand(0);
12173 SDValue Amt = Op.getOperand(1);
12175 // Optimize shl/srl/sra with constant shift amount.
12176 if (isSplatVector(Amt.getNode())) {
12177 SDValue SclrAmt = Amt->getOperand(0);
12178 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12179 uint64_t ShiftAmt = C->getZExtValue();
12181 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12182 (Subtarget->hasInt256() &&
12183 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12184 (Subtarget->hasAVX512() &&
12185 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12186 if (Op.getOpcode() == ISD::SHL)
12187 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12188 DAG.getConstant(ShiftAmt, MVT::i32));
12189 if (Op.getOpcode() == ISD::SRL)
12190 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12191 DAG.getConstant(ShiftAmt, MVT::i32));
12192 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12193 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12194 DAG.getConstant(ShiftAmt, MVT::i32));
12197 if (VT == MVT::v16i8) {
12198 if (Op.getOpcode() == ISD::SHL) {
12199 // Make a large shift.
12200 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
12201 DAG.getConstant(ShiftAmt, MVT::i32));
12202 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12203 // Zero out the rightmost bits.
12204 SmallVector<SDValue, 16> V(16,
12205 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12207 return DAG.getNode(ISD::AND, dl, VT, SHL,
12208 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12210 if (Op.getOpcode() == ISD::SRL) {
12211 // Make a large shift.
12212 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
12213 DAG.getConstant(ShiftAmt, MVT::i32));
12214 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12215 // Zero out the leftmost bits.
12216 SmallVector<SDValue, 16> V(16,
12217 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12219 return DAG.getNode(ISD::AND, dl, VT, SRL,
12220 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12222 if (Op.getOpcode() == ISD::SRA) {
12223 if (ShiftAmt == 7) {
12224 // R s>> 7 === R s< 0
12225 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12226 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12229 // R s>> a === ((R u>> a) ^ m) - m
12230 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12231 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12233 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12234 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12235 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12238 llvm_unreachable("Unknown shift opcode.");
12241 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12242 if (Op.getOpcode() == ISD::SHL) {
12243 // Make a large shift.
12244 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
12245 DAG.getConstant(ShiftAmt, MVT::i32));
12246 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12247 // Zero out the rightmost bits.
12248 SmallVector<SDValue, 32> V(32,
12249 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12251 return DAG.getNode(ISD::AND, dl, VT, SHL,
12252 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12254 if (Op.getOpcode() == ISD::SRL) {
12255 // Make a large shift.
12256 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
12257 DAG.getConstant(ShiftAmt, MVT::i32));
12258 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12259 // Zero out the leftmost bits.
12260 SmallVector<SDValue, 32> V(32,
12261 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12263 return DAG.getNode(ISD::AND, dl, VT, SRL,
12264 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12266 if (Op.getOpcode() == ISD::SRA) {
12267 if (ShiftAmt == 7) {
12268 // R s>> 7 === R s< 0
12269 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12270 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12273 // R s>> a === ((R u>> a) ^ m) - m
12274 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12275 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12277 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12278 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12279 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12282 llvm_unreachable("Unknown shift opcode.");
12287 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12288 if (!Subtarget->is64Bit() &&
12289 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12290 Amt.getOpcode() == ISD::BITCAST &&
12291 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12292 Amt = Amt.getOperand(0);
12293 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12294 VT.getVectorNumElements();
12295 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12296 uint64_t ShiftAmt = 0;
12297 for (unsigned i = 0; i != Ratio; ++i) {
12298 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12302 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12304 // Check remaining shift amounts.
12305 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12306 uint64_t ShAmt = 0;
12307 for (unsigned j = 0; j != Ratio; ++j) {
12308 ConstantSDNode *C =
12309 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12313 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12315 if (ShAmt != ShiftAmt)
12318 switch (Op.getOpcode()) {
12320 llvm_unreachable("Unknown shift opcode!");
12322 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12323 DAG.getConstant(ShiftAmt, MVT::i32));
12325 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12326 DAG.getConstant(ShiftAmt, MVT::i32));
12328 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12329 DAG.getConstant(ShiftAmt, MVT::i32));
12336 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12337 const X86Subtarget* Subtarget) {
12338 EVT VT = Op.getValueType();
12340 SDValue R = Op.getOperand(0);
12341 SDValue Amt = Op.getOperand(1);
12343 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12344 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12345 (Subtarget->hasInt256() &&
12346 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12347 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12348 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12350 EVT EltVT = VT.getVectorElementType();
12352 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12353 unsigned NumElts = VT.getVectorNumElements();
12355 for (i = 0; i != NumElts; ++i) {
12356 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12360 for (j = i; j != NumElts; ++j) {
12361 SDValue Arg = Amt.getOperand(j);
12362 if (Arg.getOpcode() == ISD::UNDEF) continue;
12363 if (Arg != Amt.getOperand(i))
12366 if (i != NumElts && j == NumElts)
12367 BaseShAmt = Amt.getOperand(i);
12369 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12370 Amt = Amt.getOperand(0);
12371 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12372 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12373 SDValue InVec = Amt.getOperand(0);
12374 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12375 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12377 for (; i != NumElts; ++i) {
12378 SDValue Arg = InVec.getOperand(i);
12379 if (Arg.getOpcode() == ISD::UNDEF) continue;
12383 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12384 if (ConstantSDNode *C =
12385 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12386 unsigned SplatIdx =
12387 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12388 if (C->getZExtValue() == SplatIdx)
12389 BaseShAmt = InVec.getOperand(1);
12392 if (BaseShAmt.getNode() == 0)
12393 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12394 DAG.getIntPtrConstant(0));
12398 if (BaseShAmt.getNode()) {
12399 if (EltVT.bitsGT(MVT::i32))
12400 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12401 else if (EltVT.bitsLT(MVT::i32))
12402 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12404 switch (Op.getOpcode()) {
12406 llvm_unreachable("Unknown shift opcode!");
12408 switch (VT.getSimpleVT().SimpleTy) {
12409 default: return SDValue();
12418 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12421 switch (VT.getSimpleVT().SimpleTy) {
12422 default: return SDValue();
12429 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12432 switch (VT.getSimpleVT().SimpleTy) {
12433 default: return SDValue();
12442 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12448 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12449 if (!Subtarget->is64Bit() &&
12450 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12451 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12452 Amt.getOpcode() == ISD::BITCAST &&
12453 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12454 Amt = Amt.getOperand(0);
12455 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12456 VT.getVectorNumElements();
12457 std::vector<SDValue> Vals(Ratio);
12458 for (unsigned i = 0; i != Ratio; ++i)
12459 Vals[i] = Amt.getOperand(i);
12460 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12461 for (unsigned j = 0; j != Ratio; ++j)
12462 if (Vals[j] != Amt.getOperand(i + j))
12465 switch (Op.getOpcode()) {
12467 llvm_unreachable("Unknown shift opcode!");
12469 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12471 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12473 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12480 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12481 SelectionDAG &DAG) {
12483 EVT VT = Op.getValueType();
12485 SDValue R = Op.getOperand(0);
12486 SDValue Amt = Op.getOperand(1);
12489 if (!Subtarget->hasSSE2())
12492 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12496 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12500 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12502 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12503 if (Subtarget->hasInt256()) {
12504 if (Op.getOpcode() == ISD::SRL &&
12505 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12506 VT == MVT::v4i64 || VT == MVT::v8i32))
12508 if (Op.getOpcode() == ISD::SHL &&
12509 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12510 VT == MVT::v4i64 || VT == MVT::v8i32))
12512 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12516 // Lower SHL with variable shift amount.
12517 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12518 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12520 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12521 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12522 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12523 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12525 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12526 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12529 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12530 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12532 // Turn 'a' into a mask suitable for VSELECT
12533 SDValue VSelM = DAG.getConstant(0x80, VT);
12534 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12535 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12537 SDValue CM1 = DAG.getConstant(0x0f, VT);
12538 SDValue CM2 = DAG.getConstant(0x3f, VT);
12540 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12541 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12542 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12543 DAG.getConstant(4, MVT::i32), DAG);
12544 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12545 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12548 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12549 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12550 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12552 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12553 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12554 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12555 DAG.getConstant(2, MVT::i32), DAG);
12556 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12557 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12560 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12561 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12562 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12564 // return VSELECT(r, r+r, a);
12565 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12566 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12570 // Decompose 256-bit shifts into smaller 128-bit shifts.
12571 if (VT.is256BitVector()) {
12572 unsigned NumElems = VT.getVectorNumElements();
12573 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12574 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12576 // Extract the two vectors
12577 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12578 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12580 // Recreate the shift amount vectors
12581 SDValue Amt1, Amt2;
12582 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12583 // Constant shift amount
12584 SmallVector<SDValue, 4> Amt1Csts;
12585 SmallVector<SDValue, 4> Amt2Csts;
12586 for (unsigned i = 0; i != NumElems/2; ++i)
12587 Amt1Csts.push_back(Amt->getOperand(i));
12588 for (unsigned i = NumElems/2; i != NumElems; ++i)
12589 Amt2Csts.push_back(Amt->getOperand(i));
12591 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12592 &Amt1Csts[0], NumElems/2);
12593 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12594 &Amt2Csts[0], NumElems/2);
12596 // Variable shift amount
12597 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12598 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12601 // Issue new vector shifts for the smaller types
12602 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12603 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12605 // Concatenate the result back
12606 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12612 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12613 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12614 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12615 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12616 // has only one use.
12617 SDNode *N = Op.getNode();
12618 SDValue LHS = N->getOperand(0);
12619 SDValue RHS = N->getOperand(1);
12620 unsigned BaseOp = 0;
12623 switch (Op.getOpcode()) {
12624 default: llvm_unreachable("Unknown ovf instruction!");
12626 // A subtract of one will be selected as a INC. Note that INC doesn't
12627 // set CF, so we can't do this for UADDO.
12628 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12630 BaseOp = X86ISD::INC;
12631 Cond = X86::COND_O;
12634 BaseOp = X86ISD::ADD;
12635 Cond = X86::COND_O;
12638 BaseOp = X86ISD::ADD;
12639 Cond = X86::COND_B;
12642 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12643 // set CF, so we can't do this for USUBO.
12644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12646 BaseOp = X86ISD::DEC;
12647 Cond = X86::COND_O;
12650 BaseOp = X86ISD::SUB;
12651 Cond = X86::COND_O;
12654 BaseOp = X86ISD::SUB;
12655 Cond = X86::COND_B;
12658 BaseOp = X86ISD::SMUL;
12659 Cond = X86::COND_O;
12661 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12662 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12664 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12667 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12668 DAG.getConstant(X86::COND_O, MVT::i32),
12669 SDValue(Sum.getNode(), 2));
12671 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12675 // Also sets EFLAGS.
12676 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12677 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
12680 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12681 DAG.getConstant(Cond, MVT::i32),
12682 SDValue(Sum.getNode(), 1));
12684 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12687 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
12688 SelectionDAG &DAG) const {
12690 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
12691 EVT VT = Op.getValueType();
12693 if (!Subtarget->hasSSE2() || !VT.isVector())
12696 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
12697 ExtraVT.getScalarType().getSizeInBits();
12698 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
12700 switch (VT.getSimpleVT().SimpleTy) {
12701 default: return SDValue();
12704 if (!Subtarget->hasFp256())
12706 if (!Subtarget->hasInt256()) {
12707 // needs to be split
12708 unsigned NumElems = VT.getVectorNumElements();
12710 // Extract the LHS vectors
12711 SDValue LHS = Op.getOperand(0);
12712 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12713 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12715 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12716 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12718 EVT ExtraEltVT = ExtraVT.getVectorElementType();
12719 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
12720 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
12722 SDValue Extra = DAG.getValueType(ExtraVT);
12724 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
12725 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
12727 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
12732 // (sext (vzext x)) -> (vsext x)
12733 SDValue Op0 = Op.getOperand(0);
12734 SDValue Op00 = Op0.getOperand(0);
12736 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
12737 if (Op0.getOpcode() == ISD::BITCAST &&
12738 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
12739 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
12740 if (Tmp1.getNode()) {
12741 SDValue Tmp1Op0 = Tmp1.getOperand(0);
12742 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
12743 "This optimization is invalid without a VZEXT.");
12744 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
12747 // If the above didn't work, then just use Shift-Left + Shift-Right.
12748 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
12749 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
12754 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
12755 SelectionDAG &DAG) {
12757 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
12758 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
12759 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
12760 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
12762 // The only fence that needs an instruction is a sequentially-consistent
12763 // cross-thread fence.
12764 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
12765 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
12766 // no-sse2). There isn't any reason to disable it if the target processor
12768 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
12769 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
12771 SDValue Chain = Op.getOperand(0);
12772 SDValue Zero = DAG.getConstant(0, MVT::i32);
12774 DAG.getRegister(X86::ESP, MVT::i32), // Base
12775 DAG.getTargetConstant(1, MVT::i8), // Scale
12776 DAG.getRegister(0, MVT::i32), // Index
12777 DAG.getTargetConstant(0, MVT::i32), // Disp
12778 DAG.getRegister(0, MVT::i32), // Segment.
12782 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
12783 return SDValue(Res, 0);
12786 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
12787 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
12790 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
12791 SelectionDAG &DAG) {
12792 EVT T = Op.getValueType();
12796 switch(T.getSimpleVT().SimpleTy) {
12797 default: llvm_unreachable("Invalid value type!");
12798 case MVT::i8: Reg = X86::AL; size = 1; break;
12799 case MVT::i16: Reg = X86::AX; size = 2; break;
12800 case MVT::i32: Reg = X86::EAX; size = 4; break;
12802 assert(Subtarget->is64Bit() && "Node not type legal!");
12803 Reg = X86::RAX; size = 8;
12806 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
12807 Op.getOperand(2), SDValue());
12808 SDValue Ops[] = { cpIn.getValue(0),
12811 DAG.getTargetConstant(size, MVT::i8),
12812 cpIn.getValue(1) };
12813 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12814 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
12815 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
12816 Ops, array_lengthof(Ops), T, MMO);
12818 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
12822 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
12823 SelectionDAG &DAG) {
12824 assert(Subtarget->is64Bit() && "Result not type legalized?");
12825 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12826 SDValue TheChain = Op.getOperand(0);
12828 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12829 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
12830 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
12832 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
12833 DAG.getConstant(32, MVT::i8));
12835 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
12838 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
12841 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
12842 SelectionDAG &DAG) {
12843 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
12844 MVT DstVT = Op.getSimpleValueType();
12845 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
12846 Subtarget->hasMMX() && "Unexpected custom BITCAST");
12847 assert((DstVT == MVT::i64 ||
12848 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
12849 "Unexpected custom BITCAST");
12850 // i64 <=> MMX conversions are Legal.
12851 if (SrcVT==MVT::i64 && DstVT.isVector())
12853 if (DstVT==MVT::i64 && SrcVT.isVector())
12855 // MMX <=> MMX conversions are Legal.
12856 if (SrcVT.isVector() && DstVT.isVector())
12858 // All other conversions need to be expanded.
12862 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
12863 SDNode *Node = Op.getNode();
12865 EVT T = Node->getValueType(0);
12866 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
12867 DAG.getConstant(0, T), Node->getOperand(2));
12868 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
12869 cast<AtomicSDNode>(Node)->getMemoryVT(),
12870 Node->getOperand(0),
12871 Node->getOperand(1), negOp,
12872 cast<AtomicSDNode>(Node)->getSrcValue(),
12873 cast<AtomicSDNode>(Node)->getAlignment(),
12874 cast<AtomicSDNode>(Node)->getOrdering(),
12875 cast<AtomicSDNode>(Node)->getSynchScope());
12878 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
12879 SDNode *Node = Op.getNode();
12881 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12883 // Convert seq_cst store -> xchg
12884 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
12885 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12886 // (The only way to get a 16-byte store is cmpxchg16b)
12887 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
12888 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
12889 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12890 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
12891 cast<AtomicSDNode>(Node)->getMemoryVT(),
12892 Node->getOperand(0),
12893 Node->getOperand(1), Node->getOperand(2),
12894 cast<AtomicSDNode>(Node)->getMemOperand(),
12895 cast<AtomicSDNode>(Node)->getOrdering(),
12896 cast<AtomicSDNode>(Node)->getSynchScope());
12897 return Swap.getValue(1);
12899 // Other atomic stores have a simple pattern.
12903 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
12904 EVT VT = Op.getNode()->getValueType(0);
12906 // Let legalize expand this if it isn't a legal type yet.
12907 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
12910 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12913 bool ExtraOp = false;
12914 switch (Op.getOpcode()) {
12915 default: llvm_unreachable("Invalid code");
12916 case ISD::ADDC: Opc = X86ISD::ADD; break;
12917 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12918 case ISD::SUBC: Opc = X86ISD::SUB; break;
12919 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12923 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
12925 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
12926 Op.getOperand(1), Op.getOperand(2));
12929 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
12930 SelectionDAG &DAG) {
12931 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
12933 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
12934 // which returns the values as { float, float } (in XMM0) or
12935 // { double, double } (which is returned in XMM0, XMM1).
12937 SDValue Arg = Op.getOperand(0);
12938 EVT ArgVT = Arg.getValueType();
12939 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
12941 TargetLowering::ArgListTy Args;
12942 TargetLowering::ArgListEntry Entry;
12946 Entry.isSExt = false;
12947 Entry.isZExt = false;
12948 Args.push_back(Entry);
12950 bool isF64 = ArgVT == MVT::f64;
12951 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
12952 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12953 // the results are returned via SRet in memory.
12954 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
12955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12956 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
12958 Type *RetTy = isF64
12959 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
12960 : (Type*)VectorType::get(ArgTy, 4);
12962 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
12963 false, false, false, false, 0,
12964 CallingConv::C, /*isTaillCall=*/false,
12965 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
12966 Callee, Args, DAG, dl);
12967 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
12970 // Returned in xmm0 and xmm1.
12971 return CallResult.first;
12973 // Returned in bits 0:31 and 32:64 xmm0.
12974 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12975 CallResult.first, DAG.getIntPtrConstant(0));
12976 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12977 CallResult.first, DAG.getIntPtrConstant(1));
12978 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
12979 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
12982 /// LowerOperation - Provide custom lowering hooks for some operations.
12984 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12985 switch (Op.getOpcode()) {
12986 default: llvm_unreachable("Should not custom lower this!");
12987 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12988 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12989 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12990 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12991 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12992 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12993 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12994 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12995 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12996 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12997 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12998 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12999 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13000 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13001 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13002 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13003 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13004 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13005 case ISD::SHL_PARTS:
13006 case ISD::SRA_PARTS:
13007 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13008 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13009 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13010 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13011 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13012 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13013 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13014 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13015 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13016 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13017 case ISD::FABS: return LowerFABS(Op, DAG);
13018 case ISD::FNEG: return LowerFNEG(Op, DAG);
13019 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13020 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13021 case ISD::SETCC: return LowerSETCC(Op, DAG);
13022 case ISD::SELECT: return LowerSELECT(Op, DAG);
13023 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13024 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13025 case ISD::VASTART: return LowerVASTART(Op, DAG);
13026 case ISD::VAARG: return LowerVAARG(Op, DAG);
13027 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13028 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13029 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
13030 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13031 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13032 case ISD::FRAME_TO_ARGS_OFFSET:
13033 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13034 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13035 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13036 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13037 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13038 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13039 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13040 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13041 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13042 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13043 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13044 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13047 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13053 case ISD::UMULO: return LowerXALUO(Op, DAG);
13054 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13055 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13059 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13060 case ISD::ADD: return LowerADD(Op, DAG);
13061 case ISD::SUB: return LowerSUB(Op, DAG);
13062 case ISD::SDIV: return LowerSDIV(Op, DAG);
13063 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13067 static void ReplaceATOMIC_LOAD(SDNode *Node,
13068 SmallVectorImpl<SDValue> &Results,
13069 SelectionDAG &DAG) {
13071 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13073 // Convert wide load -> cmpxchg8b/cmpxchg16b
13074 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13075 // (The only way to get a 16-byte load is cmpxchg16b)
13076 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13077 SDValue Zero = DAG.getConstant(0, VT);
13078 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13079 Node->getOperand(0),
13080 Node->getOperand(1), Zero, Zero,
13081 cast<AtomicSDNode>(Node)->getMemOperand(),
13082 cast<AtomicSDNode>(Node)->getOrdering(),
13083 cast<AtomicSDNode>(Node)->getSynchScope());
13084 Results.push_back(Swap.getValue(0));
13085 Results.push_back(Swap.getValue(1));
13089 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13090 SelectionDAG &DAG, unsigned NewOp) {
13092 assert (Node->getValueType(0) == MVT::i64 &&
13093 "Only know how to expand i64 atomics");
13095 SDValue Chain = Node->getOperand(0);
13096 SDValue In1 = Node->getOperand(1);
13097 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13098 Node->getOperand(2), DAG.getIntPtrConstant(0));
13099 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13100 Node->getOperand(2), DAG.getIntPtrConstant(1));
13101 SDValue Ops[] = { Chain, In1, In2L, In2H };
13102 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13104 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13105 cast<MemSDNode>(Node)->getMemOperand());
13106 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13107 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13108 Results.push_back(Result.getValue(2));
13111 /// ReplaceNodeResults - Replace a node with an illegal result type
13112 /// with a new node built out of custom code.
13113 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13114 SmallVectorImpl<SDValue>&Results,
13115 SelectionDAG &DAG) const {
13117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13118 switch (N->getOpcode()) {
13120 llvm_unreachable("Do not know how to custom type legalize this operation!");
13121 case ISD::SIGN_EXTEND_INREG:
13126 // We don't want to expand or promote these.
13128 case ISD::FP_TO_SINT:
13129 case ISD::FP_TO_UINT: {
13130 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13132 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13135 std::pair<SDValue,SDValue> Vals =
13136 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13137 SDValue FIST = Vals.first, StackSlot = Vals.second;
13138 if (FIST.getNode() != 0) {
13139 EVT VT = N->getValueType(0);
13140 // Return a load from the stack slot.
13141 if (StackSlot.getNode() != 0)
13142 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13143 MachinePointerInfo(),
13144 false, false, false, 0));
13146 Results.push_back(FIST);
13150 case ISD::UINT_TO_FP: {
13151 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13152 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13153 N->getValueType(0) != MVT::v2f32)
13155 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13157 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13159 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13160 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13161 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13162 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13163 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13164 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13167 case ISD::FP_ROUND: {
13168 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13170 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13171 Results.push_back(V);
13174 case ISD::READCYCLECOUNTER: {
13175 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13176 SDValue TheChain = N->getOperand(0);
13177 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13178 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13180 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13182 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13183 SDValue Ops[] = { eax, edx };
13184 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13185 array_lengthof(Ops)));
13186 Results.push_back(edx.getValue(1));
13189 case ISD::ATOMIC_CMP_SWAP: {
13190 EVT T = N->getValueType(0);
13191 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13192 bool Regs64bit = T == MVT::i128;
13193 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13194 SDValue cpInL, cpInH;
13195 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13196 DAG.getConstant(0, HalfT));
13197 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13198 DAG.getConstant(1, HalfT));
13199 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13200 Regs64bit ? X86::RAX : X86::EAX,
13202 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13203 Regs64bit ? X86::RDX : X86::EDX,
13204 cpInH, cpInL.getValue(1));
13205 SDValue swapInL, swapInH;
13206 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13207 DAG.getConstant(0, HalfT));
13208 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13209 DAG.getConstant(1, HalfT));
13210 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13211 Regs64bit ? X86::RBX : X86::EBX,
13212 swapInL, cpInH.getValue(1));
13213 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13214 Regs64bit ? X86::RCX : X86::ECX,
13215 swapInH, swapInL.getValue(1));
13216 SDValue Ops[] = { swapInH.getValue(0),
13218 swapInH.getValue(1) };
13219 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13220 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13221 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13222 X86ISD::LCMPXCHG8_DAG;
13223 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13224 Ops, array_lengthof(Ops), T, MMO);
13225 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13226 Regs64bit ? X86::RAX : X86::EAX,
13227 HalfT, Result.getValue(1));
13228 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13229 Regs64bit ? X86::RDX : X86::EDX,
13230 HalfT, cpOutL.getValue(2));
13231 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13232 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13233 Results.push_back(cpOutH.getValue(1));
13236 case ISD::ATOMIC_LOAD_ADD:
13237 case ISD::ATOMIC_LOAD_AND:
13238 case ISD::ATOMIC_LOAD_NAND:
13239 case ISD::ATOMIC_LOAD_OR:
13240 case ISD::ATOMIC_LOAD_SUB:
13241 case ISD::ATOMIC_LOAD_XOR:
13242 case ISD::ATOMIC_LOAD_MAX:
13243 case ISD::ATOMIC_LOAD_MIN:
13244 case ISD::ATOMIC_LOAD_UMAX:
13245 case ISD::ATOMIC_LOAD_UMIN:
13246 case ISD::ATOMIC_SWAP: {
13248 switch (N->getOpcode()) {
13249 default: llvm_unreachable("Unexpected opcode");
13250 case ISD::ATOMIC_LOAD_ADD:
13251 Opc = X86ISD::ATOMADD64_DAG;
13253 case ISD::ATOMIC_LOAD_AND:
13254 Opc = X86ISD::ATOMAND64_DAG;
13256 case ISD::ATOMIC_LOAD_NAND:
13257 Opc = X86ISD::ATOMNAND64_DAG;
13259 case ISD::ATOMIC_LOAD_OR:
13260 Opc = X86ISD::ATOMOR64_DAG;
13262 case ISD::ATOMIC_LOAD_SUB:
13263 Opc = X86ISD::ATOMSUB64_DAG;
13265 case ISD::ATOMIC_LOAD_XOR:
13266 Opc = X86ISD::ATOMXOR64_DAG;
13268 case ISD::ATOMIC_LOAD_MAX:
13269 Opc = X86ISD::ATOMMAX64_DAG;
13271 case ISD::ATOMIC_LOAD_MIN:
13272 Opc = X86ISD::ATOMMIN64_DAG;
13274 case ISD::ATOMIC_LOAD_UMAX:
13275 Opc = X86ISD::ATOMUMAX64_DAG;
13277 case ISD::ATOMIC_LOAD_UMIN:
13278 Opc = X86ISD::ATOMUMIN64_DAG;
13280 case ISD::ATOMIC_SWAP:
13281 Opc = X86ISD::ATOMSWAP64_DAG;
13284 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13287 case ISD::ATOMIC_LOAD:
13288 ReplaceATOMIC_LOAD(N, Results, DAG);
13292 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13294 default: return NULL;
13295 case X86ISD::BSF: return "X86ISD::BSF";
13296 case X86ISD::BSR: return "X86ISD::BSR";
13297 case X86ISD::SHLD: return "X86ISD::SHLD";
13298 case X86ISD::SHRD: return "X86ISD::SHRD";
13299 case X86ISD::FAND: return "X86ISD::FAND";
13300 case X86ISD::FANDN: return "X86ISD::FANDN";
13301 case X86ISD::FOR: return "X86ISD::FOR";
13302 case X86ISD::FXOR: return "X86ISD::FXOR";
13303 case X86ISD::FSRL: return "X86ISD::FSRL";
13304 case X86ISD::FILD: return "X86ISD::FILD";
13305 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13306 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13307 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13308 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13309 case X86ISD::FLD: return "X86ISD::FLD";
13310 case X86ISD::FST: return "X86ISD::FST";
13311 case X86ISD::CALL: return "X86ISD::CALL";
13312 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13313 case X86ISD::BT: return "X86ISD::BT";
13314 case X86ISD::CMP: return "X86ISD::CMP";
13315 case X86ISD::COMI: return "X86ISD::COMI";
13316 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13317 case X86ISD::CMPM: return "X86ISD::CMPM";
13318 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13319 case X86ISD::SETCC: return "X86ISD::SETCC";
13320 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13321 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13322 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13323 case X86ISD::CMOV: return "X86ISD::CMOV";
13324 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13325 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13326 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13327 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13328 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13329 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13330 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13331 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13332 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13333 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13334 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13335 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13336 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13337 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13338 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13339 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13340 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13341 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13342 case X86ISD::HADD: return "X86ISD::HADD";
13343 case X86ISD::HSUB: return "X86ISD::HSUB";
13344 case X86ISD::FHADD: return "X86ISD::FHADD";
13345 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13346 case X86ISD::UMAX: return "X86ISD::UMAX";
13347 case X86ISD::UMIN: return "X86ISD::UMIN";
13348 case X86ISD::SMAX: return "X86ISD::SMAX";
13349 case X86ISD::SMIN: return "X86ISD::SMIN";
13350 case X86ISD::FMAX: return "X86ISD::FMAX";
13351 case X86ISD::FMIN: return "X86ISD::FMIN";
13352 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13353 case X86ISD::FMINC: return "X86ISD::FMINC";
13354 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13355 case X86ISD::FRCP: return "X86ISD::FRCP";
13356 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13357 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13358 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13359 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13360 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13361 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13362 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13363 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13364 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13365 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13366 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13367 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13368 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13369 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13370 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13371 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13372 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13373 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13374 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13375 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13376 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13377 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13378 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13379 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13380 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13381 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13382 case X86ISD::VSHL: return "X86ISD::VSHL";
13383 case X86ISD::VSRL: return "X86ISD::VSRL";
13384 case X86ISD::VSRA: return "X86ISD::VSRA";
13385 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13386 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13387 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13388 case X86ISD::CMPP: return "X86ISD::CMPP";
13389 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13390 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13391 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13392 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13393 case X86ISD::ADD: return "X86ISD::ADD";
13394 case X86ISD::SUB: return "X86ISD::SUB";
13395 case X86ISD::ADC: return "X86ISD::ADC";
13396 case X86ISD::SBB: return "X86ISD::SBB";
13397 case X86ISD::SMUL: return "X86ISD::SMUL";
13398 case X86ISD::UMUL: return "X86ISD::UMUL";
13399 case X86ISD::INC: return "X86ISD::INC";
13400 case X86ISD::DEC: return "X86ISD::DEC";
13401 case X86ISD::OR: return "X86ISD::OR";
13402 case X86ISD::XOR: return "X86ISD::XOR";
13403 case X86ISD::AND: return "X86ISD::AND";
13404 case X86ISD::BLSI: return "X86ISD::BLSI";
13405 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13406 case X86ISD::BLSR: return "X86ISD::BLSR";
13407 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13408 case X86ISD::PTEST: return "X86ISD::PTEST";
13409 case X86ISD::TESTP: return "X86ISD::TESTP";
13410 case X86ISD::TESTM: return "X86ISD::TESTM";
13411 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13412 case X86ISD::KTEST: return "X86ISD::KTEST";
13413 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13414 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13415 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13416 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13417 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13418 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13419 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13420 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13421 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13422 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13423 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13424 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13425 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13426 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13427 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13428 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13429 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13430 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13431 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13432 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13433 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13434 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13435 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13436 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13437 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13438 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13439 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13440 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13441 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13442 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13443 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13444 case X86ISD::SAHF: return "X86ISD::SAHF";
13445 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13446 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13447 case X86ISD::FMADD: return "X86ISD::FMADD";
13448 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13449 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13450 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13451 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13452 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13453 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13454 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13455 case X86ISD::XTEST: return "X86ISD::XTEST";
13459 // isLegalAddressingMode - Return true if the addressing mode represented
13460 // by AM is legal for this target, for a load/store of the specified type.
13461 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13463 // X86 supports extremely general addressing modes.
13464 CodeModel::Model M = getTargetMachine().getCodeModel();
13465 Reloc::Model R = getTargetMachine().getRelocationModel();
13467 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13468 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13473 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13475 // If a reference to this global requires an extra load, we can't fold it.
13476 if (isGlobalStubReference(GVFlags))
13479 // If BaseGV requires a register for the PIC base, we cannot also have a
13480 // BaseReg specified.
13481 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13484 // If lower 4G is not available, then we must use rip-relative addressing.
13485 if ((M != CodeModel::Small || R != Reloc::Static) &&
13486 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13490 switch (AM.Scale) {
13496 // These scales always work.
13501 // These scales are formed with basereg+scalereg. Only accept if there is
13506 default: // Other stuff never works.
13513 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13514 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13516 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13517 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13518 return NumBits1 > NumBits2;
13521 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13522 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13525 if (!isTypeLegal(EVT::getEVT(Ty1)))
13528 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13530 // Assuming the caller doesn't have a zeroext or signext return parameter,
13531 // truncation all the way down to i1 is valid.
13535 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13536 return isInt<32>(Imm);
13539 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13540 // Can also use sub to handle negated immediates.
13541 return isInt<32>(Imm);
13544 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13545 if (!VT1.isInteger() || !VT2.isInteger())
13547 unsigned NumBits1 = VT1.getSizeInBits();
13548 unsigned NumBits2 = VT2.getSizeInBits();
13549 return NumBits1 > NumBits2;
13552 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13553 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13554 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13557 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13558 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13559 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13562 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13563 EVT VT1 = Val.getValueType();
13564 if (isZExtFree(VT1, VT2))
13567 if (Val.getOpcode() != ISD::LOAD)
13570 if (!VT1.isSimple() || !VT1.isInteger() ||
13571 !VT2.isSimple() || !VT2.isInteger())
13574 switch (VT1.getSimpleVT().SimpleTy) {
13579 // X86 has 8, 16, and 32-bit zero-extending loads.
13587 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13588 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13591 VT = VT.getScalarType();
13593 if (!VT.isSimple())
13596 switch (VT.getSimpleVT().SimpleTy) {
13607 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13608 // i16 instructions are longer (0x66 prefix) and potentially slower.
13609 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13612 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13613 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13614 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13615 /// are assumed to be legal.
13617 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13619 if (!VT.isSimple())
13622 MVT SVT = VT.getSimpleVT();
13624 // Very little shuffling can be done for 64-bit vectors right now.
13625 if (VT.getSizeInBits() == 64)
13628 // FIXME: pshufb, blends, shifts.
13629 return (SVT.getVectorNumElements() == 2 ||
13630 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13631 isMOVLMask(M, SVT) ||
13632 isSHUFPMask(M, SVT) ||
13633 isPSHUFDMask(M, SVT) ||
13634 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13635 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13636 isPALIGNRMask(M, SVT, Subtarget) ||
13637 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13638 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13639 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13640 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
13644 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13646 if (!VT.isSimple())
13649 MVT SVT = VT.getSimpleVT();
13650 unsigned NumElts = SVT.getVectorNumElements();
13651 // FIXME: This collection of masks seems suspect.
13654 if (NumElts == 4 && SVT.is128BitVector()) {
13655 return (isMOVLMask(Mask, SVT) ||
13656 isCommutedMOVLMask(Mask, SVT, true) ||
13657 isSHUFPMask(Mask, SVT) ||
13658 isSHUFPMask(Mask, SVT, /* Commuted */ true));
13663 //===----------------------------------------------------------------------===//
13664 // X86 Scheduler Hooks
13665 //===----------------------------------------------------------------------===//
13667 /// Utility function to emit xbegin specifying the start of an RTM region.
13668 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
13669 const TargetInstrInfo *TII) {
13670 DebugLoc DL = MI->getDebugLoc();
13672 const BasicBlock *BB = MBB->getBasicBlock();
13673 MachineFunction::iterator I = MBB;
13676 // For the v = xbegin(), we generate
13687 MachineBasicBlock *thisMBB = MBB;
13688 MachineFunction *MF = MBB->getParent();
13689 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13690 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13691 MF->insert(I, mainMBB);
13692 MF->insert(I, sinkMBB);
13694 // Transfer the remainder of BB and its successor edges to sinkMBB.
13695 sinkMBB->splice(sinkMBB->begin(), MBB,
13696 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13697 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13701 // # fallthrough to mainMBB
13702 // # abortion to sinkMBB
13703 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
13704 thisMBB->addSuccessor(mainMBB);
13705 thisMBB->addSuccessor(sinkMBB);
13709 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
13710 mainMBB->addSuccessor(sinkMBB);
13713 // EAX is live into the sinkMBB
13714 sinkMBB->addLiveIn(X86::EAX);
13715 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13716 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13719 MI->eraseFromParent();
13723 // Get CMPXCHG opcode for the specified data type.
13724 static unsigned getCmpXChgOpcode(EVT VT) {
13725 switch (VT.getSimpleVT().SimpleTy) {
13726 case MVT::i8: return X86::LCMPXCHG8;
13727 case MVT::i16: return X86::LCMPXCHG16;
13728 case MVT::i32: return X86::LCMPXCHG32;
13729 case MVT::i64: return X86::LCMPXCHG64;
13733 llvm_unreachable("Invalid operand size!");
13736 // Get LOAD opcode for the specified data type.
13737 static unsigned getLoadOpcode(EVT VT) {
13738 switch (VT.getSimpleVT().SimpleTy) {
13739 case MVT::i8: return X86::MOV8rm;
13740 case MVT::i16: return X86::MOV16rm;
13741 case MVT::i32: return X86::MOV32rm;
13742 case MVT::i64: return X86::MOV64rm;
13746 llvm_unreachable("Invalid operand size!");
13749 // Get opcode of the non-atomic one from the specified atomic instruction.
13750 static unsigned getNonAtomicOpcode(unsigned Opc) {
13752 case X86::ATOMAND8: return X86::AND8rr;
13753 case X86::ATOMAND16: return X86::AND16rr;
13754 case X86::ATOMAND32: return X86::AND32rr;
13755 case X86::ATOMAND64: return X86::AND64rr;
13756 case X86::ATOMOR8: return X86::OR8rr;
13757 case X86::ATOMOR16: return X86::OR16rr;
13758 case X86::ATOMOR32: return X86::OR32rr;
13759 case X86::ATOMOR64: return X86::OR64rr;
13760 case X86::ATOMXOR8: return X86::XOR8rr;
13761 case X86::ATOMXOR16: return X86::XOR16rr;
13762 case X86::ATOMXOR32: return X86::XOR32rr;
13763 case X86::ATOMXOR64: return X86::XOR64rr;
13765 llvm_unreachable("Unhandled atomic-load-op opcode!");
13768 // Get opcode of the non-atomic one from the specified atomic instruction with
13770 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
13771 unsigned &ExtraOpc) {
13773 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
13774 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
13775 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
13776 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
13777 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
13778 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
13779 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
13780 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
13781 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
13782 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
13783 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
13784 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
13785 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
13786 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
13787 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
13788 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
13789 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
13790 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
13791 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
13792 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
13794 llvm_unreachable("Unhandled atomic-load-op opcode!");
13797 // Get opcode of the non-atomic one from the specified atomic instruction for
13798 // 64-bit data type on 32-bit target.
13799 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
13801 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
13802 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
13803 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
13804 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
13805 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
13806 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
13807 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
13808 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
13809 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
13810 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
13812 llvm_unreachable("Unhandled atomic-load-op opcode!");
13815 // Get opcode of the non-atomic one from the specified atomic instruction for
13816 // 64-bit data type on 32-bit target with extra opcode.
13817 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
13819 unsigned &ExtraOpc) {
13821 case X86::ATOMNAND6432:
13822 ExtraOpc = X86::NOT32r;
13823 HiOpc = X86::AND32rr;
13824 return X86::AND32rr;
13826 llvm_unreachable("Unhandled atomic-load-op opcode!");
13829 // Get pseudo CMOV opcode from the specified data type.
13830 static unsigned getPseudoCMOVOpc(EVT VT) {
13831 switch (VT.getSimpleVT().SimpleTy) {
13832 case MVT::i8: return X86::CMOV_GR8;
13833 case MVT::i16: return X86::CMOV_GR16;
13834 case MVT::i32: return X86::CMOV_GR32;
13838 llvm_unreachable("Unknown CMOV opcode!");
13841 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
13842 // They will be translated into a spin-loop or compare-exchange loop from
13845 // dst = atomic-fetch-op MI.addr, MI.val
13851 // t1 = LOAD MI.addr
13853 // t4 = phi(t1, t3 / loop)
13854 // t2 = OP MI.val, t4
13856 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
13862 MachineBasicBlock *
13863 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
13864 MachineBasicBlock *MBB) const {
13865 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13866 DebugLoc DL = MI->getDebugLoc();
13868 MachineFunction *MF = MBB->getParent();
13869 MachineRegisterInfo &MRI = MF->getRegInfo();
13871 const BasicBlock *BB = MBB->getBasicBlock();
13872 MachineFunction::iterator I = MBB;
13875 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
13876 "Unexpected number of operands");
13878 assert(MI->hasOneMemOperand() &&
13879 "Expected atomic-load-op to have one memoperand");
13881 // Memory Reference
13882 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13883 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13885 unsigned DstReg, SrcReg;
13886 unsigned MemOpndSlot;
13888 unsigned CurOp = 0;
13890 DstReg = MI->getOperand(CurOp++).getReg();
13891 MemOpndSlot = CurOp;
13892 CurOp += X86::AddrNumOperands;
13893 SrcReg = MI->getOperand(CurOp++).getReg();
13895 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
13896 MVT::SimpleValueType VT = *RC->vt_begin();
13897 unsigned t1 = MRI.createVirtualRegister(RC);
13898 unsigned t2 = MRI.createVirtualRegister(RC);
13899 unsigned t3 = MRI.createVirtualRegister(RC);
13900 unsigned t4 = MRI.createVirtualRegister(RC);
13901 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
13903 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
13904 unsigned LOADOpc = getLoadOpcode(VT);
13906 // For the atomic load-arith operator, we generate
13909 // t1 = LOAD [MI.addr]
13911 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
13912 // t1 = OP MI.val, EAX
13914 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
13920 MachineBasicBlock *thisMBB = MBB;
13921 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13922 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13923 MF->insert(I, mainMBB);
13924 MF->insert(I, sinkMBB);
13926 MachineInstrBuilder MIB;
13928 // Transfer the remainder of BB and its successor edges to sinkMBB.
13929 sinkMBB->splice(sinkMBB->begin(), MBB,
13930 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13931 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13934 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
13935 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13936 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13938 NewMO.setIsKill(false);
13939 MIB.addOperand(NewMO);
13941 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13942 unsigned flags = (*MMOI)->getFlags();
13943 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13944 MachineMemOperand *MMO =
13945 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13946 (*MMOI)->getSize(),
13947 (*MMOI)->getBaseAlignment(),
13948 (*MMOI)->getTBAAInfo(),
13949 (*MMOI)->getRanges());
13950 MIB.addMemOperand(MMO);
13953 thisMBB->addSuccessor(mainMBB);
13956 MachineBasicBlock *origMainMBB = mainMBB;
13959 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
13960 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13962 unsigned Opc = MI->getOpcode();
13965 llvm_unreachable("Unhandled atomic-load-op opcode!");
13966 case X86::ATOMAND8:
13967 case X86::ATOMAND16:
13968 case X86::ATOMAND32:
13969 case X86::ATOMAND64:
13971 case X86::ATOMOR16:
13972 case X86::ATOMOR32:
13973 case X86::ATOMOR64:
13974 case X86::ATOMXOR8:
13975 case X86::ATOMXOR16:
13976 case X86::ATOMXOR32:
13977 case X86::ATOMXOR64: {
13978 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
13979 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
13983 case X86::ATOMNAND8:
13984 case X86::ATOMNAND16:
13985 case X86::ATOMNAND32:
13986 case X86::ATOMNAND64: {
13987 unsigned Tmp = MRI.createVirtualRegister(RC);
13989 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
13990 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
13992 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
13995 case X86::ATOMMAX8:
13996 case X86::ATOMMAX16:
13997 case X86::ATOMMAX32:
13998 case X86::ATOMMAX64:
13999 case X86::ATOMMIN8:
14000 case X86::ATOMMIN16:
14001 case X86::ATOMMIN32:
14002 case X86::ATOMMIN64:
14003 case X86::ATOMUMAX8:
14004 case X86::ATOMUMAX16:
14005 case X86::ATOMUMAX32:
14006 case X86::ATOMUMAX64:
14007 case X86::ATOMUMIN8:
14008 case X86::ATOMUMIN16:
14009 case X86::ATOMUMIN32:
14010 case X86::ATOMUMIN64: {
14012 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14014 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14018 if (Subtarget->hasCMov()) {
14019 if (VT != MVT::i8) {
14021 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14025 // Promote i8 to i32 to use CMOV32
14026 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14027 const TargetRegisterClass *RC32 =
14028 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14029 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14030 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14031 unsigned Tmp = MRI.createVirtualRegister(RC32);
14033 unsigned Undef = MRI.createVirtualRegister(RC32);
14034 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14036 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14039 .addImm(X86::sub_8bit);
14040 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14043 .addImm(X86::sub_8bit);
14045 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14049 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14050 .addReg(Tmp, 0, X86::sub_8bit);
14053 // Use pseudo select and lower them.
14054 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14055 "Invalid atomic-load-op transformation!");
14056 unsigned SelOpc = getPseudoCMOVOpc(VT);
14057 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14058 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14059 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14060 .addReg(SrcReg).addReg(t4)
14062 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14063 // Replace the original PHI node as mainMBB is changed after CMOV
14065 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14066 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14067 Phi->eraseFromParent();
14073 // Copy PhyReg back from virtual register.
14074 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14077 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14078 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14079 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14081 NewMO.setIsKill(false);
14082 MIB.addOperand(NewMO);
14085 MIB.setMemRefs(MMOBegin, MMOEnd);
14087 // Copy PhyReg back to virtual register.
14088 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14091 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14093 mainMBB->addSuccessor(origMainMBB);
14094 mainMBB->addSuccessor(sinkMBB);
14097 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14098 TII->get(TargetOpcode::COPY), DstReg)
14101 MI->eraseFromParent();
14105 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14106 // instructions. They will be translated into a spin-loop or compare-exchange
14110 // dst = atomic-fetch-op MI.addr, MI.val
14116 // t1L = LOAD [MI.addr + 0]
14117 // t1H = LOAD [MI.addr + 4]
14119 // t4L = phi(t1L, t3L / loop)
14120 // t4H = phi(t1H, t3H / loop)
14121 // t2L = OP MI.val.lo, t4L
14122 // t2H = OP MI.val.hi, t4H
14127 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14135 MachineBasicBlock *
14136 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14137 MachineBasicBlock *MBB) const {
14138 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14139 DebugLoc DL = MI->getDebugLoc();
14141 MachineFunction *MF = MBB->getParent();
14142 MachineRegisterInfo &MRI = MF->getRegInfo();
14144 const BasicBlock *BB = MBB->getBasicBlock();
14145 MachineFunction::iterator I = MBB;
14148 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14149 "Unexpected number of operands");
14151 assert(MI->hasOneMemOperand() &&
14152 "Expected atomic-load-op32 to have one memoperand");
14154 // Memory Reference
14155 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14156 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14158 unsigned DstLoReg, DstHiReg;
14159 unsigned SrcLoReg, SrcHiReg;
14160 unsigned MemOpndSlot;
14162 unsigned CurOp = 0;
14164 DstLoReg = MI->getOperand(CurOp++).getReg();
14165 DstHiReg = MI->getOperand(CurOp++).getReg();
14166 MemOpndSlot = CurOp;
14167 CurOp += X86::AddrNumOperands;
14168 SrcLoReg = MI->getOperand(CurOp++).getReg();
14169 SrcHiReg = MI->getOperand(CurOp++).getReg();
14171 const TargetRegisterClass *RC = &X86::GR32RegClass;
14172 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14174 unsigned t1L = MRI.createVirtualRegister(RC);
14175 unsigned t1H = MRI.createVirtualRegister(RC);
14176 unsigned t2L = MRI.createVirtualRegister(RC);
14177 unsigned t2H = MRI.createVirtualRegister(RC);
14178 unsigned t3L = MRI.createVirtualRegister(RC);
14179 unsigned t3H = MRI.createVirtualRegister(RC);
14180 unsigned t4L = MRI.createVirtualRegister(RC);
14181 unsigned t4H = MRI.createVirtualRegister(RC);
14183 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14184 unsigned LOADOpc = X86::MOV32rm;
14186 // For the atomic load-arith operator, we generate
14189 // t1L = LOAD [MI.addr + 0]
14190 // t1H = LOAD [MI.addr + 4]
14192 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14193 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14194 // t2L = OP MI.val.lo, t4L
14195 // t2H = OP MI.val.hi, t4H
14198 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14206 MachineBasicBlock *thisMBB = MBB;
14207 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14208 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14209 MF->insert(I, mainMBB);
14210 MF->insert(I, sinkMBB);
14212 MachineInstrBuilder MIB;
14214 // Transfer the remainder of BB and its successor edges to sinkMBB.
14215 sinkMBB->splice(sinkMBB->begin(), MBB,
14216 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14217 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14221 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14222 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14223 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14225 NewMO.setIsKill(false);
14226 MIB.addOperand(NewMO);
14228 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14229 unsigned flags = (*MMOI)->getFlags();
14230 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14231 MachineMemOperand *MMO =
14232 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14233 (*MMOI)->getSize(),
14234 (*MMOI)->getBaseAlignment(),
14235 (*MMOI)->getTBAAInfo(),
14236 (*MMOI)->getRanges());
14237 MIB.addMemOperand(MMO);
14239 MachineInstr *LowMI = MIB;
14242 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14243 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14244 if (i == X86::AddrDisp) {
14245 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14247 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14249 NewMO.setIsKill(false);
14250 MIB.addOperand(NewMO);
14253 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14255 thisMBB->addSuccessor(mainMBB);
14258 MachineBasicBlock *origMainMBB = mainMBB;
14261 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14262 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14263 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14264 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14266 unsigned Opc = MI->getOpcode();
14269 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14270 case X86::ATOMAND6432:
14271 case X86::ATOMOR6432:
14272 case X86::ATOMXOR6432:
14273 case X86::ATOMADD6432:
14274 case X86::ATOMSUB6432: {
14276 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14277 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14279 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14283 case X86::ATOMNAND6432: {
14284 unsigned HiOpc, NOTOpc;
14285 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14286 unsigned TmpL = MRI.createVirtualRegister(RC);
14287 unsigned TmpH = MRI.createVirtualRegister(RC);
14288 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14290 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14292 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14293 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14296 case X86::ATOMMAX6432:
14297 case X86::ATOMMIN6432:
14298 case X86::ATOMUMAX6432:
14299 case X86::ATOMUMIN6432: {
14301 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14302 unsigned cL = MRI.createVirtualRegister(RC8);
14303 unsigned cH = MRI.createVirtualRegister(RC8);
14304 unsigned cL32 = MRI.createVirtualRegister(RC);
14305 unsigned cH32 = MRI.createVirtualRegister(RC);
14306 unsigned cc = MRI.createVirtualRegister(RC);
14307 // cl := cmp src_lo, lo
14308 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14309 .addReg(SrcLoReg).addReg(t4L);
14310 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14311 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14312 // ch := cmp src_hi, hi
14313 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14314 .addReg(SrcHiReg).addReg(t4H);
14315 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14316 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14317 // cc := if (src_hi == hi) ? cl : ch;
14318 if (Subtarget->hasCMov()) {
14319 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14320 .addReg(cH32).addReg(cL32);
14322 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14323 .addReg(cH32).addReg(cL32)
14324 .addImm(X86::COND_E);
14325 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14327 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14328 if (Subtarget->hasCMov()) {
14329 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14330 .addReg(SrcLoReg).addReg(t4L);
14331 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14332 .addReg(SrcHiReg).addReg(t4H);
14334 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14335 .addReg(SrcLoReg).addReg(t4L)
14336 .addImm(X86::COND_NE);
14337 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14338 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14339 // 2nd CMOV lowering.
14340 mainMBB->addLiveIn(X86::EFLAGS);
14341 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14342 .addReg(SrcHiReg).addReg(t4H)
14343 .addImm(X86::COND_NE);
14344 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14345 // Replace the original PHI node as mainMBB is changed after CMOV
14347 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14348 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14349 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14350 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14351 PhiL->eraseFromParent();
14352 PhiH->eraseFromParent();
14356 case X86::ATOMSWAP6432: {
14358 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14359 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14360 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14365 // Copy EDX:EAX back from HiReg:LoReg
14366 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14367 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14368 // Copy ECX:EBX from t1H:t1L
14369 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14370 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14372 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14373 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14374 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14376 NewMO.setIsKill(false);
14377 MIB.addOperand(NewMO);
14379 MIB.setMemRefs(MMOBegin, MMOEnd);
14381 // Copy EDX:EAX back to t3H:t3L
14382 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14383 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14385 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14387 mainMBB->addSuccessor(origMainMBB);
14388 mainMBB->addSuccessor(sinkMBB);
14391 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14392 TII->get(TargetOpcode::COPY), DstLoReg)
14394 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14395 TII->get(TargetOpcode::COPY), DstHiReg)
14398 MI->eraseFromParent();
14402 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14403 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14404 // in the .td file.
14405 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14406 const TargetInstrInfo *TII) {
14408 switch (MI->getOpcode()) {
14409 default: llvm_unreachable("illegal opcode!");
14410 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14411 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14412 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14413 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14414 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14415 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14416 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14417 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14420 DebugLoc dl = MI->getDebugLoc();
14421 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14423 unsigned NumArgs = MI->getNumOperands();
14424 for (unsigned i = 1; i < NumArgs; ++i) {
14425 MachineOperand &Op = MI->getOperand(i);
14426 if (!(Op.isReg() && Op.isImplicit()))
14427 MIB.addOperand(Op);
14429 if (MI->hasOneMemOperand())
14430 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14432 BuildMI(*BB, MI, dl,
14433 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14434 .addReg(X86::XMM0);
14436 MI->eraseFromParent();
14440 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14441 // defs in an instruction pattern
14442 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14443 const TargetInstrInfo *TII) {
14445 switch (MI->getOpcode()) {
14446 default: llvm_unreachable("illegal opcode!");
14447 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14448 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14449 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14450 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14451 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14452 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14453 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14454 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14457 DebugLoc dl = MI->getDebugLoc();
14458 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14460 unsigned NumArgs = MI->getNumOperands(); // remove the results
14461 for (unsigned i = 1; i < NumArgs; ++i) {
14462 MachineOperand &Op = MI->getOperand(i);
14463 if (!(Op.isReg() && Op.isImplicit()))
14464 MIB.addOperand(Op);
14466 if (MI->hasOneMemOperand())
14467 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14469 BuildMI(*BB, MI, dl,
14470 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14473 MI->eraseFromParent();
14477 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14478 const TargetInstrInfo *TII,
14479 const X86Subtarget* Subtarget) {
14480 DebugLoc dl = MI->getDebugLoc();
14482 // Address into RAX/EAX, other two args into ECX, EDX.
14483 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14484 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14485 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14486 for (int i = 0; i < X86::AddrNumOperands; ++i)
14487 MIB.addOperand(MI->getOperand(i));
14489 unsigned ValOps = X86::AddrNumOperands;
14490 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14491 .addReg(MI->getOperand(ValOps).getReg());
14492 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14493 .addReg(MI->getOperand(ValOps+1).getReg());
14495 // The instruction doesn't actually take any operands though.
14496 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14498 MI->eraseFromParent(); // The pseudo is gone now.
14502 MachineBasicBlock *
14503 X86TargetLowering::EmitVAARG64WithCustomInserter(
14505 MachineBasicBlock *MBB) const {
14506 // Emit va_arg instruction on X86-64.
14508 // Operands to this pseudo-instruction:
14509 // 0 ) Output : destination address (reg)
14510 // 1-5) Input : va_list address (addr, i64mem)
14511 // 6 ) ArgSize : Size (in bytes) of vararg type
14512 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14513 // 8 ) Align : Alignment of type
14514 // 9 ) EFLAGS (implicit-def)
14516 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14517 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14519 unsigned DestReg = MI->getOperand(0).getReg();
14520 MachineOperand &Base = MI->getOperand(1);
14521 MachineOperand &Scale = MI->getOperand(2);
14522 MachineOperand &Index = MI->getOperand(3);
14523 MachineOperand &Disp = MI->getOperand(4);
14524 MachineOperand &Segment = MI->getOperand(5);
14525 unsigned ArgSize = MI->getOperand(6).getImm();
14526 unsigned ArgMode = MI->getOperand(7).getImm();
14527 unsigned Align = MI->getOperand(8).getImm();
14529 // Memory Reference
14530 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14531 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14532 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14534 // Machine Information
14535 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14536 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14537 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14538 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14539 DebugLoc DL = MI->getDebugLoc();
14541 // struct va_list {
14544 // i64 overflow_area (address)
14545 // i64 reg_save_area (address)
14547 // sizeof(va_list) = 24
14548 // alignment(va_list) = 8
14550 unsigned TotalNumIntRegs = 6;
14551 unsigned TotalNumXMMRegs = 8;
14552 bool UseGPOffset = (ArgMode == 1);
14553 bool UseFPOffset = (ArgMode == 2);
14554 unsigned MaxOffset = TotalNumIntRegs * 8 +
14555 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14557 /* Align ArgSize to a multiple of 8 */
14558 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14559 bool NeedsAlign = (Align > 8);
14561 MachineBasicBlock *thisMBB = MBB;
14562 MachineBasicBlock *overflowMBB;
14563 MachineBasicBlock *offsetMBB;
14564 MachineBasicBlock *endMBB;
14566 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14567 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14568 unsigned OffsetReg = 0;
14570 if (!UseGPOffset && !UseFPOffset) {
14571 // If we only pull from the overflow region, we don't create a branch.
14572 // We don't need to alter control flow.
14573 OffsetDestReg = 0; // unused
14574 OverflowDestReg = DestReg;
14577 overflowMBB = thisMBB;
14580 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14581 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14582 // If not, pull from overflow_area. (branch to overflowMBB)
14587 // offsetMBB overflowMBB
14592 // Registers for the PHI in endMBB
14593 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14594 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14596 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14597 MachineFunction *MF = MBB->getParent();
14598 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14599 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14600 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14602 MachineFunction::iterator MBBIter = MBB;
14605 // Insert the new basic blocks
14606 MF->insert(MBBIter, offsetMBB);
14607 MF->insert(MBBIter, overflowMBB);
14608 MF->insert(MBBIter, endMBB);
14610 // Transfer the remainder of MBB and its successor edges to endMBB.
14611 endMBB->splice(endMBB->begin(), thisMBB,
14612 llvm::next(MachineBasicBlock::iterator(MI)),
14614 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14616 // Make offsetMBB and overflowMBB successors of thisMBB
14617 thisMBB->addSuccessor(offsetMBB);
14618 thisMBB->addSuccessor(overflowMBB);
14620 // endMBB is a successor of both offsetMBB and overflowMBB
14621 offsetMBB->addSuccessor(endMBB);
14622 overflowMBB->addSuccessor(endMBB);
14624 // Load the offset value into a register
14625 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14626 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14630 .addDisp(Disp, UseFPOffset ? 4 : 0)
14631 .addOperand(Segment)
14632 .setMemRefs(MMOBegin, MMOEnd);
14634 // Check if there is enough room left to pull this argument.
14635 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14637 .addImm(MaxOffset + 8 - ArgSizeA8);
14639 // Branch to "overflowMBB" if offset >= max
14640 // Fall through to "offsetMBB" otherwise
14641 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14642 .addMBB(overflowMBB);
14645 // In offsetMBB, emit code to use the reg_save_area.
14647 assert(OffsetReg != 0);
14649 // Read the reg_save_area address.
14650 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14651 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14656 .addOperand(Segment)
14657 .setMemRefs(MMOBegin, MMOEnd);
14659 // Zero-extend the offset
14660 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14661 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
14664 .addImm(X86::sub_32bit);
14666 // Add the offset to the reg_save_area to get the final address.
14667 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
14668 .addReg(OffsetReg64)
14669 .addReg(RegSaveReg);
14671 // Compute the offset for the next argument
14672 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14673 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
14675 .addImm(UseFPOffset ? 16 : 8);
14677 // Store it back into the va_list.
14678 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
14682 .addDisp(Disp, UseFPOffset ? 4 : 0)
14683 .addOperand(Segment)
14684 .addReg(NextOffsetReg)
14685 .setMemRefs(MMOBegin, MMOEnd);
14688 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
14693 // Emit code to use overflow area
14696 // Load the overflow_area address into a register.
14697 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
14698 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
14703 .addOperand(Segment)
14704 .setMemRefs(MMOBegin, MMOEnd);
14706 // If we need to align it, do so. Otherwise, just copy the address
14707 // to OverflowDestReg.
14709 // Align the overflow address
14710 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
14711 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
14713 // aligned_addr = (addr + (align-1)) & ~(align-1)
14714 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
14715 .addReg(OverflowAddrReg)
14718 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
14720 .addImm(~(uint64_t)(Align-1));
14722 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
14723 .addReg(OverflowAddrReg);
14726 // Compute the next overflow address after this argument.
14727 // (the overflow address should be kept 8-byte aligned)
14728 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
14729 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
14730 .addReg(OverflowDestReg)
14731 .addImm(ArgSizeA8);
14733 // Store the new overflow address.
14734 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
14739 .addOperand(Segment)
14740 .addReg(NextAddrReg)
14741 .setMemRefs(MMOBegin, MMOEnd);
14743 // If we branched, emit the PHI to the front of endMBB.
14745 BuildMI(*endMBB, endMBB->begin(), DL,
14746 TII->get(X86::PHI), DestReg)
14747 .addReg(OffsetDestReg).addMBB(offsetMBB)
14748 .addReg(OverflowDestReg).addMBB(overflowMBB);
14751 // Erase the pseudo instruction
14752 MI->eraseFromParent();
14757 MachineBasicBlock *
14758 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
14760 MachineBasicBlock *MBB) const {
14761 // Emit code to save XMM registers to the stack. The ABI says that the
14762 // number of registers to save is given in %al, so it's theoretically
14763 // possible to do an indirect jump trick to avoid saving all of them,
14764 // however this code takes a simpler approach and just executes all
14765 // of the stores if %al is non-zero. It's less code, and it's probably
14766 // easier on the hardware branch predictor, and stores aren't all that
14767 // expensive anyway.
14769 // Create the new basic blocks. One block contains all the XMM stores,
14770 // and one block is the final destination regardless of whether any
14771 // stores were performed.
14772 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14773 MachineFunction *F = MBB->getParent();
14774 MachineFunction::iterator MBBIter = MBB;
14776 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
14777 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
14778 F->insert(MBBIter, XMMSaveMBB);
14779 F->insert(MBBIter, EndMBB);
14781 // Transfer the remainder of MBB and its successor edges to EndMBB.
14782 EndMBB->splice(EndMBB->begin(), MBB,
14783 llvm::next(MachineBasicBlock::iterator(MI)),
14785 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
14787 // The original block will now fall through to the XMM save block.
14788 MBB->addSuccessor(XMMSaveMBB);
14789 // The XMMSaveMBB will fall through to the end block.
14790 XMMSaveMBB->addSuccessor(EndMBB);
14792 // Now add the instructions.
14793 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14794 DebugLoc DL = MI->getDebugLoc();
14796 unsigned CountReg = MI->getOperand(0).getReg();
14797 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
14798 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
14800 if (!Subtarget->isTargetWin64()) {
14801 // If %al is 0, branch around the XMM save block.
14802 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
14803 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
14804 MBB->addSuccessor(EndMBB);
14807 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
14808 // In the XMM save block, save all the XMM argument registers.
14809 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
14810 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
14811 MachineMemOperand *MMO =
14812 F->getMachineMemOperand(
14813 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
14814 MachineMemOperand::MOStore,
14815 /*Size=*/16, /*Align=*/16);
14816 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
14817 .addFrameIndex(RegSaveFrameIndex)
14818 .addImm(/*Scale=*/1)
14819 .addReg(/*IndexReg=*/0)
14820 .addImm(/*Disp=*/Offset)
14821 .addReg(/*Segment=*/0)
14822 .addReg(MI->getOperand(i).getReg())
14823 .addMemOperand(MMO);
14826 MI->eraseFromParent(); // The pseudo instruction is gone now.
14831 // The EFLAGS operand of SelectItr might be missing a kill marker
14832 // because there were multiple uses of EFLAGS, and ISel didn't know
14833 // which to mark. Figure out whether SelectItr should have had a
14834 // kill marker, and set it if it should. Returns the correct kill
14836 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
14837 MachineBasicBlock* BB,
14838 const TargetRegisterInfo* TRI) {
14839 // Scan forward through BB for a use/def of EFLAGS.
14840 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
14841 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
14842 const MachineInstr& mi = *miI;
14843 if (mi.readsRegister(X86::EFLAGS))
14845 if (mi.definesRegister(X86::EFLAGS))
14846 break; // Should have kill-flag - update below.
14849 // If we hit the end of the block, check whether EFLAGS is live into a
14851 if (miI == BB->end()) {
14852 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
14853 sEnd = BB->succ_end();
14854 sItr != sEnd; ++sItr) {
14855 MachineBasicBlock* succ = *sItr;
14856 if (succ->isLiveIn(X86::EFLAGS))
14861 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
14862 // out. SelectMI should have a kill flag on EFLAGS.
14863 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
14867 MachineBasicBlock *
14868 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
14869 MachineBasicBlock *BB) const {
14870 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14871 DebugLoc DL = MI->getDebugLoc();
14873 // To "insert" a SELECT_CC instruction, we actually have to insert the
14874 // diamond control-flow pattern. The incoming instruction knows the
14875 // destination vreg to set, the condition code register to branch on, the
14876 // true/false values to select between, and a branch opcode to use.
14877 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14878 MachineFunction::iterator It = BB;
14884 // cmpTY ccX, r1, r2
14886 // fallthrough --> copy0MBB
14887 MachineBasicBlock *thisMBB = BB;
14888 MachineFunction *F = BB->getParent();
14889 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
14890 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
14891 F->insert(It, copy0MBB);
14892 F->insert(It, sinkMBB);
14894 // If the EFLAGS register isn't dead in the terminator, then claim that it's
14895 // live into the sink and copy blocks.
14896 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14897 if (!MI->killsRegister(X86::EFLAGS) &&
14898 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
14899 copy0MBB->addLiveIn(X86::EFLAGS);
14900 sinkMBB->addLiveIn(X86::EFLAGS);
14903 // Transfer the remainder of BB and its successor edges to sinkMBB.
14904 sinkMBB->splice(sinkMBB->begin(), BB,
14905 llvm::next(MachineBasicBlock::iterator(MI)),
14907 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
14909 // Add the true and fallthrough blocks as its successors.
14910 BB->addSuccessor(copy0MBB);
14911 BB->addSuccessor(sinkMBB);
14913 // Create the conditional branch instruction.
14915 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
14916 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
14919 // %FalseValue = ...
14920 // # fallthrough to sinkMBB
14921 copy0MBB->addSuccessor(sinkMBB);
14924 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
14926 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14927 TII->get(X86::PHI), MI->getOperand(0).getReg())
14928 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
14929 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
14931 MI->eraseFromParent(); // The pseudo instruction is gone now.
14935 MachineBasicBlock *
14936 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
14937 bool Is64Bit) const {
14938 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14939 DebugLoc DL = MI->getDebugLoc();
14940 MachineFunction *MF = BB->getParent();
14941 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14943 assert(getTargetMachine().Options.EnableSegmentedStacks);
14945 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
14946 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
14949 // ... [Till the alloca]
14950 // If stacklet is not large enough, jump to mallocMBB
14953 // Allocate by subtracting from RSP
14954 // Jump to continueMBB
14957 // Allocate by call to runtime
14961 // [rest of original BB]
14964 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14965 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14966 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14968 MachineRegisterInfo &MRI = MF->getRegInfo();
14969 const TargetRegisterClass *AddrRegClass =
14970 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
14972 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14973 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14974 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
14975 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
14976 sizeVReg = MI->getOperand(1).getReg(),
14977 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
14979 MachineFunction::iterator MBBIter = BB;
14982 MF->insert(MBBIter, bumpMBB);
14983 MF->insert(MBBIter, mallocMBB);
14984 MF->insert(MBBIter, continueMBB);
14986 continueMBB->splice(continueMBB->begin(), BB, llvm::next
14987 (MachineBasicBlock::iterator(MI)), BB->end());
14988 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
14990 // Add code to the main basic block to check if the stack limit has been hit,
14991 // and if so, jump to mallocMBB otherwise to bumpMBB.
14992 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
14993 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
14994 .addReg(tmpSPVReg).addReg(sizeVReg);
14995 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
14996 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
14997 .addReg(SPLimitVReg);
14998 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15000 // bumpMBB simply decreases the stack pointer, since we know the current
15001 // stacklet has enough space.
15002 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15003 .addReg(SPLimitVReg);
15004 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15005 .addReg(SPLimitVReg);
15006 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15008 // Calls into a routine in libgcc to allocate more space from the heap.
15009 const uint32_t *RegMask =
15010 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15012 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15014 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15015 .addExternalSymbol("__morestack_allocate_stack_space")
15016 .addRegMask(RegMask)
15017 .addReg(X86::RDI, RegState::Implicit)
15018 .addReg(X86::RAX, RegState::ImplicitDefine);
15020 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15022 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15023 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15024 .addExternalSymbol("__morestack_allocate_stack_space")
15025 .addRegMask(RegMask)
15026 .addReg(X86::EAX, RegState::ImplicitDefine);
15030 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15033 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15034 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15035 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15037 // Set up the CFG correctly.
15038 BB->addSuccessor(bumpMBB);
15039 BB->addSuccessor(mallocMBB);
15040 mallocMBB->addSuccessor(continueMBB);
15041 bumpMBB->addSuccessor(continueMBB);
15043 // Take care of the PHI nodes.
15044 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15045 MI->getOperand(0).getReg())
15046 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15047 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15049 // Delete the original pseudo instruction.
15050 MI->eraseFromParent();
15053 return continueMBB;
15056 MachineBasicBlock *
15057 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15058 MachineBasicBlock *BB) const {
15059 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15060 DebugLoc DL = MI->getDebugLoc();
15062 assert(!Subtarget->isTargetEnvMacho());
15064 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15065 // non-trivial part is impdef of ESP.
15067 if (Subtarget->isTargetWin64()) {
15068 if (Subtarget->isTargetCygMing()) {
15069 // ___chkstk(Mingw64):
15070 // Clobbers R10, R11, RAX and EFLAGS.
15072 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15073 .addExternalSymbol("___chkstk")
15074 .addReg(X86::RAX, RegState::Implicit)
15075 .addReg(X86::RSP, RegState::Implicit)
15076 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15077 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15078 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15080 // __chkstk(MSVCRT): does not update stack pointer.
15081 // Clobbers R10, R11 and EFLAGS.
15082 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15083 .addExternalSymbol("__chkstk")
15084 .addReg(X86::RAX, RegState::Implicit)
15085 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15086 // RAX has the offset to be subtracted from RSP.
15087 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15092 const char *StackProbeSymbol =
15093 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15095 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15096 .addExternalSymbol(StackProbeSymbol)
15097 .addReg(X86::EAX, RegState::Implicit)
15098 .addReg(X86::ESP, RegState::Implicit)
15099 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15100 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15101 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15104 MI->eraseFromParent(); // The pseudo instruction is gone now.
15108 MachineBasicBlock *
15109 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15110 MachineBasicBlock *BB) const {
15111 // This is pretty easy. We're taking the value that we received from
15112 // our load from the relocation, sticking it in either RDI (x86-64)
15113 // or EAX and doing an indirect call. The return value will then
15114 // be in the normal return register.
15115 const X86InstrInfo *TII
15116 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15117 DebugLoc DL = MI->getDebugLoc();
15118 MachineFunction *F = BB->getParent();
15120 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15121 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15123 // Get a register mask for the lowered call.
15124 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15125 // proper register mask.
15126 const uint32_t *RegMask =
15127 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15128 if (Subtarget->is64Bit()) {
15129 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15130 TII->get(X86::MOV64rm), X86::RDI)
15132 .addImm(0).addReg(0)
15133 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15134 MI->getOperand(3).getTargetFlags())
15136 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15137 addDirectMem(MIB, X86::RDI);
15138 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15139 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15140 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15141 TII->get(X86::MOV32rm), X86::EAX)
15143 .addImm(0).addReg(0)
15144 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15145 MI->getOperand(3).getTargetFlags())
15147 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15148 addDirectMem(MIB, X86::EAX);
15149 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15151 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15152 TII->get(X86::MOV32rm), X86::EAX)
15153 .addReg(TII->getGlobalBaseReg(F))
15154 .addImm(0).addReg(0)
15155 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15156 MI->getOperand(3).getTargetFlags())
15158 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15159 addDirectMem(MIB, X86::EAX);
15160 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15163 MI->eraseFromParent(); // The pseudo instruction is gone now.
15167 MachineBasicBlock *
15168 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15169 MachineBasicBlock *MBB) const {
15170 DebugLoc DL = MI->getDebugLoc();
15171 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15173 MachineFunction *MF = MBB->getParent();
15174 MachineRegisterInfo &MRI = MF->getRegInfo();
15176 const BasicBlock *BB = MBB->getBasicBlock();
15177 MachineFunction::iterator I = MBB;
15180 // Memory Reference
15181 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15182 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15185 unsigned MemOpndSlot = 0;
15187 unsigned CurOp = 0;
15189 DstReg = MI->getOperand(CurOp++).getReg();
15190 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15191 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15192 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15193 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15195 MemOpndSlot = CurOp;
15197 MVT PVT = getPointerTy();
15198 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15199 "Invalid Pointer Size!");
15201 // For v = setjmp(buf), we generate
15204 // buf[LabelOffset] = restoreMBB
15205 // SjLjSetup restoreMBB
15211 // v = phi(main, restore)
15216 MachineBasicBlock *thisMBB = MBB;
15217 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15218 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15219 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15220 MF->insert(I, mainMBB);
15221 MF->insert(I, sinkMBB);
15222 MF->push_back(restoreMBB);
15224 MachineInstrBuilder MIB;
15226 // Transfer the remainder of BB and its successor edges to sinkMBB.
15227 sinkMBB->splice(sinkMBB->begin(), MBB,
15228 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15229 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15232 unsigned PtrStoreOpc = 0;
15233 unsigned LabelReg = 0;
15234 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15235 Reloc::Model RM = getTargetMachine().getRelocationModel();
15236 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15237 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15239 // Prepare IP either in reg or imm.
15240 if (!UseImmLabel) {
15241 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15242 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15243 LabelReg = MRI.createVirtualRegister(PtrRC);
15244 if (Subtarget->is64Bit()) {
15245 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15249 .addMBB(restoreMBB)
15252 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15253 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15254 .addReg(XII->getGlobalBaseReg(MF))
15257 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15261 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15263 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15264 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15265 if (i == X86::AddrDisp)
15266 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15268 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15271 MIB.addReg(LabelReg);
15273 MIB.addMBB(restoreMBB);
15274 MIB.setMemRefs(MMOBegin, MMOEnd);
15276 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15277 .addMBB(restoreMBB);
15279 const X86RegisterInfo *RegInfo =
15280 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15281 MIB.addRegMask(RegInfo->getNoPreservedMask());
15282 thisMBB->addSuccessor(mainMBB);
15283 thisMBB->addSuccessor(restoreMBB);
15287 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15288 mainMBB->addSuccessor(sinkMBB);
15291 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15292 TII->get(X86::PHI), DstReg)
15293 .addReg(mainDstReg).addMBB(mainMBB)
15294 .addReg(restoreDstReg).addMBB(restoreMBB);
15297 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15298 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15299 restoreMBB->addSuccessor(sinkMBB);
15301 MI->eraseFromParent();
15305 MachineBasicBlock *
15306 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15307 MachineBasicBlock *MBB) const {
15308 DebugLoc DL = MI->getDebugLoc();
15309 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15311 MachineFunction *MF = MBB->getParent();
15312 MachineRegisterInfo &MRI = MF->getRegInfo();
15314 // Memory Reference
15315 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15316 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15318 MVT PVT = getPointerTy();
15319 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15320 "Invalid Pointer Size!");
15322 const TargetRegisterClass *RC =
15323 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15324 unsigned Tmp = MRI.createVirtualRegister(RC);
15325 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15326 const X86RegisterInfo *RegInfo =
15327 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15328 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15329 unsigned SP = RegInfo->getStackRegister();
15331 MachineInstrBuilder MIB;
15333 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15334 const int64_t SPOffset = 2 * PVT.getStoreSize();
15336 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15337 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15340 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15341 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15342 MIB.addOperand(MI->getOperand(i));
15343 MIB.setMemRefs(MMOBegin, MMOEnd);
15345 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15346 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15347 if (i == X86::AddrDisp)
15348 MIB.addDisp(MI->getOperand(i), LabelOffset);
15350 MIB.addOperand(MI->getOperand(i));
15352 MIB.setMemRefs(MMOBegin, MMOEnd);
15354 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15355 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15356 if (i == X86::AddrDisp)
15357 MIB.addDisp(MI->getOperand(i), SPOffset);
15359 MIB.addOperand(MI->getOperand(i));
15361 MIB.setMemRefs(MMOBegin, MMOEnd);
15363 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15365 MI->eraseFromParent();
15369 MachineBasicBlock *
15370 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15371 MachineBasicBlock *BB) const {
15372 switch (MI->getOpcode()) {
15373 default: llvm_unreachable("Unexpected instr type to insert");
15374 case X86::TAILJMPd64:
15375 case X86::TAILJMPr64:
15376 case X86::TAILJMPm64:
15377 llvm_unreachable("TAILJMP64 would not be touched here.");
15378 case X86::TCRETURNdi64:
15379 case X86::TCRETURNri64:
15380 case X86::TCRETURNmi64:
15382 case X86::WIN_ALLOCA:
15383 return EmitLoweredWinAlloca(MI, BB);
15384 case X86::SEG_ALLOCA_32:
15385 return EmitLoweredSegAlloca(MI, BB, false);
15386 case X86::SEG_ALLOCA_64:
15387 return EmitLoweredSegAlloca(MI, BB, true);
15388 case X86::TLSCall_32:
15389 case X86::TLSCall_64:
15390 return EmitLoweredTLSCall(MI, BB);
15391 case X86::CMOV_GR8:
15392 case X86::CMOV_FR32:
15393 case X86::CMOV_FR64:
15394 case X86::CMOV_V4F32:
15395 case X86::CMOV_V2F64:
15396 case X86::CMOV_V2I64:
15397 case X86::CMOV_V8F32:
15398 case X86::CMOV_V4F64:
15399 case X86::CMOV_V4I64:
15400 case X86::CMOV_GR16:
15401 case X86::CMOV_GR32:
15402 case X86::CMOV_RFP32:
15403 case X86::CMOV_RFP64:
15404 case X86::CMOV_RFP80:
15405 return EmitLoweredSelect(MI, BB);
15407 case X86::FP32_TO_INT16_IN_MEM:
15408 case X86::FP32_TO_INT32_IN_MEM:
15409 case X86::FP32_TO_INT64_IN_MEM:
15410 case X86::FP64_TO_INT16_IN_MEM:
15411 case X86::FP64_TO_INT32_IN_MEM:
15412 case X86::FP64_TO_INT64_IN_MEM:
15413 case X86::FP80_TO_INT16_IN_MEM:
15414 case X86::FP80_TO_INT32_IN_MEM:
15415 case X86::FP80_TO_INT64_IN_MEM: {
15416 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15417 DebugLoc DL = MI->getDebugLoc();
15419 // Change the floating point control register to use "round towards zero"
15420 // mode when truncating to an integer value.
15421 MachineFunction *F = BB->getParent();
15422 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15423 addFrameReference(BuildMI(*BB, MI, DL,
15424 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15426 // Load the old value of the high byte of the control word...
15428 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15429 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15432 // Set the high part to be round to zero...
15433 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15436 // Reload the modified control word now...
15437 addFrameReference(BuildMI(*BB, MI, DL,
15438 TII->get(X86::FLDCW16m)), CWFrameIdx);
15440 // Restore the memory image of control word to original value
15441 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15444 // Get the X86 opcode to use.
15446 switch (MI->getOpcode()) {
15447 default: llvm_unreachable("illegal opcode!");
15448 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15449 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15450 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15451 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15452 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15453 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15454 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15455 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15456 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15460 MachineOperand &Op = MI->getOperand(0);
15462 AM.BaseType = X86AddressMode::RegBase;
15463 AM.Base.Reg = Op.getReg();
15465 AM.BaseType = X86AddressMode::FrameIndexBase;
15466 AM.Base.FrameIndex = Op.getIndex();
15468 Op = MI->getOperand(1);
15470 AM.Scale = Op.getImm();
15471 Op = MI->getOperand(2);
15473 AM.IndexReg = Op.getImm();
15474 Op = MI->getOperand(3);
15475 if (Op.isGlobal()) {
15476 AM.GV = Op.getGlobal();
15478 AM.Disp = Op.getImm();
15480 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15481 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15483 // Reload the original control word now.
15484 addFrameReference(BuildMI(*BB, MI, DL,
15485 TII->get(X86::FLDCW16m)), CWFrameIdx);
15487 MI->eraseFromParent(); // The pseudo instruction is gone now.
15490 // String/text processing lowering.
15491 case X86::PCMPISTRM128REG:
15492 case X86::VPCMPISTRM128REG:
15493 case X86::PCMPISTRM128MEM:
15494 case X86::VPCMPISTRM128MEM:
15495 case X86::PCMPESTRM128REG:
15496 case X86::VPCMPESTRM128REG:
15497 case X86::PCMPESTRM128MEM:
15498 case X86::VPCMPESTRM128MEM:
15499 assert(Subtarget->hasSSE42() &&
15500 "Target must have SSE4.2 or AVX features enabled");
15501 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15503 // String/text processing lowering.
15504 case X86::PCMPISTRIREG:
15505 case X86::VPCMPISTRIREG:
15506 case X86::PCMPISTRIMEM:
15507 case X86::VPCMPISTRIMEM:
15508 case X86::PCMPESTRIREG:
15509 case X86::VPCMPESTRIREG:
15510 case X86::PCMPESTRIMEM:
15511 case X86::VPCMPESTRIMEM:
15512 assert(Subtarget->hasSSE42() &&
15513 "Target must have SSE4.2 or AVX features enabled");
15514 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15516 // Thread synchronization.
15518 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15522 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15524 // Atomic Lowering.
15525 case X86::ATOMAND8:
15526 case X86::ATOMAND16:
15527 case X86::ATOMAND32:
15528 case X86::ATOMAND64:
15531 case X86::ATOMOR16:
15532 case X86::ATOMOR32:
15533 case X86::ATOMOR64:
15535 case X86::ATOMXOR16:
15536 case X86::ATOMXOR8:
15537 case X86::ATOMXOR32:
15538 case X86::ATOMXOR64:
15540 case X86::ATOMNAND8:
15541 case X86::ATOMNAND16:
15542 case X86::ATOMNAND32:
15543 case X86::ATOMNAND64:
15545 case X86::ATOMMAX8:
15546 case X86::ATOMMAX16:
15547 case X86::ATOMMAX32:
15548 case X86::ATOMMAX64:
15550 case X86::ATOMMIN8:
15551 case X86::ATOMMIN16:
15552 case X86::ATOMMIN32:
15553 case X86::ATOMMIN64:
15555 case X86::ATOMUMAX8:
15556 case X86::ATOMUMAX16:
15557 case X86::ATOMUMAX32:
15558 case X86::ATOMUMAX64:
15560 case X86::ATOMUMIN8:
15561 case X86::ATOMUMIN16:
15562 case X86::ATOMUMIN32:
15563 case X86::ATOMUMIN64:
15564 return EmitAtomicLoadArith(MI, BB);
15566 // This group does 64-bit operations on a 32-bit host.
15567 case X86::ATOMAND6432:
15568 case X86::ATOMOR6432:
15569 case X86::ATOMXOR6432:
15570 case X86::ATOMNAND6432:
15571 case X86::ATOMADD6432:
15572 case X86::ATOMSUB6432:
15573 case X86::ATOMMAX6432:
15574 case X86::ATOMMIN6432:
15575 case X86::ATOMUMAX6432:
15576 case X86::ATOMUMIN6432:
15577 case X86::ATOMSWAP6432:
15578 return EmitAtomicLoadArith6432(MI, BB);
15580 case X86::VASTART_SAVE_XMM_REGS:
15581 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15583 case X86::VAARG_64:
15584 return EmitVAARG64WithCustomInserter(MI, BB);
15586 case X86::EH_SjLj_SetJmp32:
15587 case X86::EH_SjLj_SetJmp64:
15588 return emitEHSjLjSetJmp(MI, BB);
15590 case X86::EH_SjLj_LongJmp32:
15591 case X86::EH_SjLj_LongJmp64:
15592 return emitEHSjLjLongJmp(MI, BB);
15596 //===----------------------------------------------------------------------===//
15597 // X86 Optimization Hooks
15598 //===----------------------------------------------------------------------===//
15600 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15603 const SelectionDAG &DAG,
15604 unsigned Depth) const {
15605 unsigned BitWidth = KnownZero.getBitWidth();
15606 unsigned Opc = Op.getOpcode();
15607 assert((Opc >= ISD::BUILTIN_OP_END ||
15608 Opc == ISD::INTRINSIC_WO_CHAIN ||
15609 Opc == ISD::INTRINSIC_W_CHAIN ||
15610 Opc == ISD::INTRINSIC_VOID) &&
15611 "Should use MaskedValueIsZero if you don't know whether Op"
15612 " is a target node!");
15614 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15628 // These nodes' second result is a boolean.
15629 if (Op.getResNo() == 0)
15632 case X86ISD::SETCC:
15633 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15635 case ISD::INTRINSIC_WO_CHAIN: {
15636 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15637 unsigned NumLoBits = 0;
15640 case Intrinsic::x86_sse_movmsk_ps:
15641 case Intrinsic::x86_avx_movmsk_ps_256:
15642 case Intrinsic::x86_sse2_movmsk_pd:
15643 case Intrinsic::x86_avx_movmsk_pd_256:
15644 case Intrinsic::x86_mmx_pmovmskb:
15645 case Intrinsic::x86_sse2_pmovmskb_128:
15646 case Intrinsic::x86_avx2_pmovmskb: {
15647 // High bits of movmskp{s|d}, pmovmskb are known zero.
15649 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15650 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15651 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15652 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15653 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15654 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15655 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15656 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15658 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
15667 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
15668 unsigned Depth) const {
15669 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
15670 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
15671 return Op.getValueType().getScalarType().getSizeInBits();
15677 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
15678 /// node is a GlobalAddress + offset.
15679 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
15680 const GlobalValue* &GA,
15681 int64_t &Offset) const {
15682 if (N->getOpcode() == X86ISD::Wrapper) {
15683 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
15684 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
15685 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
15689 return TargetLowering::isGAPlusOffset(N, GA, Offset);
15692 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
15693 /// same as extracting the high 128-bit part of 256-bit vector and then
15694 /// inserting the result into the low part of a new 256-bit vector
15695 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
15696 EVT VT = SVOp->getValueType(0);
15697 unsigned NumElems = VT.getVectorNumElements();
15699 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15700 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
15701 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15702 SVOp->getMaskElt(j) >= 0)
15708 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
15709 /// same as extracting the low 128-bit part of 256-bit vector and then
15710 /// inserting the result into the high part of a new 256-bit vector
15711 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
15712 EVT VT = SVOp->getValueType(0);
15713 unsigned NumElems = VT.getVectorNumElements();
15715 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15716 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
15717 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15718 SVOp->getMaskElt(j) >= 0)
15724 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
15725 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
15726 TargetLowering::DAGCombinerInfo &DCI,
15727 const X86Subtarget* Subtarget) {
15729 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
15730 SDValue V1 = SVOp->getOperand(0);
15731 SDValue V2 = SVOp->getOperand(1);
15732 EVT VT = SVOp->getValueType(0);
15733 unsigned NumElems = VT.getVectorNumElements();
15735 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
15736 V2.getOpcode() == ISD::CONCAT_VECTORS) {
15740 // V UNDEF BUILD_VECTOR UNDEF
15742 // CONCAT_VECTOR CONCAT_VECTOR
15745 // RESULT: V + zero extended
15747 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
15748 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
15749 V1.getOperand(1).getOpcode() != ISD::UNDEF)
15752 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
15755 // To match the shuffle mask, the first half of the mask should
15756 // be exactly the first vector, and all the rest a splat with the
15757 // first element of the second one.
15758 for (unsigned i = 0; i != NumElems/2; ++i)
15759 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
15760 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
15763 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
15764 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
15765 if (Ld->hasNUsesOfValue(1, 0)) {
15766 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
15767 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
15769 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
15770 array_lengthof(Ops),
15772 Ld->getPointerInfo(),
15773 Ld->getAlignment(),
15774 false/*isVolatile*/, true/*ReadMem*/,
15775 false/*WriteMem*/);
15777 // Make sure the newly-created LOAD is in the same position as Ld in
15778 // terms of dependency. We create a TokenFactor for Ld and ResNode,
15779 // and update uses of Ld's output chain to use the TokenFactor.
15780 if (Ld->hasAnyUseOfValue(1)) {
15781 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
15782 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
15783 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
15784 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
15785 SDValue(ResNode.getNode(), 1));
15788 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
15792 // Emit a zeroed vector and insert the desired subvector on its
15794 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15795 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
15796 return DCI.CombineTo(N, InsV);
15799 //===--------------------------------------------------------------------===//
15800 // Combine some shuffles into subvector extracts and inserts:
15803 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15804 if (isShuffleHigh128VectorInsertLow(SVOp)) {
15805 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
15806 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
15807 return DCI.CombineTo(N, InsV);
15810 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15811 if (isShuffleLow128VectorInsertHigh(SVOp)) {
15812 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
15813 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
15814 return DCI.CombineTo(N, InsV);
15820 /// PerformShuffleCombine - Performs several different shuffle combines.
15821 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
15822 TargetLowering::DAGCombinerInfo &DCI,
15823 const X86Subtarget *Subtarget) {
15825 EVT VT = N->getValueType(0);
15827 // Don't create instructions with illegal types after legalize types has run.
15828 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15829 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
15832 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
15833 if (Subtarget->hasFp256() && VT.is256BitVector() &&
15834 N->getOpcode() == ISD::VECTOR_SHUFFLE)
15835 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
15837 // Only handle 128 wide vector from here on.
15838 if (!VT.is128BitVector())
15841 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
15842 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
15843 // consecutive, non-overlapping, and in the right order.
15844 SmallVector<SDValue, 16> Elts;
15845 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
15846 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
15848 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
15851 /// PerformTruncateCombine - Converts truncate operation to
15852 /// a sequence of vector shuffle operations.
15853 /// It is possible when we truncate 256-bit vector to 128-bit vector
15854 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
15855 TargetLowering::DAGCombinerInfo &DCI,
15856 const X86Subtarget *Subtarget) {
15860 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
15861 /// specific shuffle of a load can be folded into a single element load.
15862 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
15863 /// shuffles have been customed lowered so we need to handle those here.
15864 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
15865 TargetLowering::DAGCombinerInfo &DCI) {
15866 if (DCI.isBeforeLegalizeOps())
15869 SDValue InVec = N->getOperand(0);
15870 SDValue EltNo = N->getOperand(1);
15872 if (!isa<ConstantSDNode>(EltNo))
15875 EVT VT = InVec.getValueType();
15877 bool HasShuffleIntoBitcast = false;
15878 if (InVec.getOpcode() == ISD::BITCAST) {
15879 // Don't duplicate a load with other uses.
15880 if (!InVec.hasOneUse())
15882 EVT BCVT = InVec.getOperand(0).getValueType();
15883 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
15885 InVec = InVec.getOperand(0);
15886 HasShuffleIntoBitcast = true;
15889 if (!isTargetShuffle(InVec.getOpcode()))
15892 // Don't duplicate a load with other uses.
15893 if (!InVec.hasOneUse())
15896 SmallVector<int, 16> ShuffleMask;
15898 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
15902 // Select the input vector, guarding against out of range extract vector.
15903 unsigned NumElems = VT.getVectorNumElements();
15904 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
15905 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
15906 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
15907 : InVec.getOperand(1);
15909 // If inputs to shuffle are the same for both ops, then allow 2 uses
15910 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
15912 if (LdNode.getOpcode() == ISD::BITCAST) {
15913 // Don't duplicate a load with other uses.
15914 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
15917 AllowedUses = 1; // only allow 1 load use if we have a bitcast
15918 LdNode = LdNode.getOperand(0);
15921 if (!ISD::isNormalLoad(LdNode.getNode()))
15924 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
15926 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
15929 if (HasShuffleIntoBitcast) {
15930 // If there's a bitcast before the shuffle, check if the load type and
15931 // alignment is valid.
15932 unsigned Align = LN0->getAlignment();
15933 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15934 unsigned NewAlign = TLI.getDataLayout()->
15935 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
15937 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
15941 // All checks match so transform back to vector_shuffle so that DAG combiner
15942 // can finish the job
15945 // Create shuffle node taking into account the case that its a unary shuffle
15946 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
15947 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
15948 InVec.getOperand(0), Shuffle,
15950 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
15951 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
15955 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
15956 /// generation and convert it from being a bunch of shuffles and extracts
15957 /// to a simple store and scalar loads to extract the elements.
15958 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
15959 TargetLowering::DAGCombinerInfo &DCI) {
15960 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
15961 if (NewOp.getNode())
15964 SDValue InputVector = N->getOperand(0);
15965 // Detect whether we are trying to convert from mmx to i32 and the bitcast
15966 // from mmx to v2i32 has a single usage.
15967 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
15968 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
15969 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
15970 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
15971 N->getValueType(0),
15972 InputVector.getNode()->getOperand(0));
15974 // Only operate on vectors of 4 elements, where the alternative shuffling
15975 // gets to be more expensive.
15976 if (InputVector.getValueType() != MVT::v4i32)
15979 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
15980 // single use which is a sign-extend or zero-extend, and all elements are
15982 SmallVector<SDNode *, 4> Uses;
15983 unsigned ExtractedElements = 0;
15984 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
15985 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
15986 if (UI.getUse().getResNo() != InputVector.getResNo())
15989 SDNode *Extract = *UI;
15990 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
15993 if (Extract->getValueType(0) != MVT::i32)
15995 if (!Extract->hasOneUse())
15997 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
15998 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16000 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16003 // Record which element was extracted.
16004 ExtractedElements |=
16005 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16007 Uses.push_back(Extract);
16010 // If not all the elements were used, this may not be worthwhile.
16011 if (ExtractedElements != 15)
16014 // Ok, we've now decided to do the transformation.
16015 SDLoc dl(InputVector);
16017 // Store the value to a temporary stack slot.
16018 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16019 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16020 MachinePointerInfo(), false, false, 0);
16022 // Replace each use (extract) with a load of the appropriate element.
16023 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16024 UE = Uses.end(); UI != UE; ++UI) {
16025 SDNode *Extract = *UI;
16027 // cOMpute the element's address.
16028 SDValue Idx = Extract->getOperand(1);
16030 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16031 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16032 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16033 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16035 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16036 StackPtr, OffsetVal);
16038 // Load the scalar.
16039 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16040 ScalarAddr, MachinePointerInfo(),
16041 false, false, false, 0);
16043 // Replace the exact with the load.
16044 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16047 // The replacement was made in place; don't return anything.
16051 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16052 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
16053 SDValue RHS, SelectionDAG &DAG,
16054 const X86Subtarget *Subtarget) {
16055 if (!VT.isVector())
16058 switch (VT.getSimpleVT().SimpleTy) {
16063 if (!Subtarget->hasAVX2())
16068 if (!Subtarget->hasSSE2())
16072 // SSE2 has only a small subset of the operations.
16073 bool hasUnsigned = Subtarget->hasSSE41() ||
16074 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16075 bool hasSigned = Subtarget->hasSSE41() ||
16076 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16078 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16080 // Check for x CC y ? x : y.
16081 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16082 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16087 return hasUnsigned ? X86ISD::UMIN : 0;
16090 return hasUnsigned ? X86ISD::UMAX : 0;
16093 return hasSigned ? X86ISD::SMIN : 0;
16096 return hasSigned ? X86ISD::SMAX : 0;
16098 // Check for x CC y ? y : x -- a min/max with reversed arms.
16099 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16100 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16105 return hasUnsigned ? X86ISD::UMAX : 0;
16108 return hasUnsigned ? X86ISD::UMIN : 0;
16111 return hasSigned ? X86ISD::SMAX : 0;
16114 return hasSigned ? X86ISD::SMIN : 0;
16121 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16123 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16124 TargetLowering::DAGCombinerInfo &DCI,
16125 const X86Subtarget *Subtarget) {
16127 SDValue Cond = N->getOperand(0);
16128 // Get the LHS/RHS of the select.
16129 SDValue LHS = N->getOperand(1);
16130 SDValue RHS = N->getOperand(2);
16131 EVT VT = LHS.getValueType();
16133 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16134 // instructions match the semantics of the common C idiom x<y?x:y but not
16135 // x<=y?x:y, because of how they handle negative zero (which can be
16136 // ignored in unsafe-math mode).
16137 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16138 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
16139 (Subtarget->hasSSE2() ||
16140 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16141 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16143 unsigned Opcode = 0;
16144 // Check for x CC y ? x : y.
16145 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16146 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16150 // Converting this to a min would handle NaNs incorrectly, and swapping
16151 // the operands would cause it to handle comparisons between positive
16152 // and negative zero incorrectly.
16153 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16154 if (!DAG.getTarget().Options.UnsafeFPMath &&
16155 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16157 std::swap(LHS, RHS);
16159 Opcode = X86ISD::FMIN;
16162 // Converting this to a min would handle comparisons between positive
16163 // and negative zero incorrectly.
16164 if (!DAG.getTarget().Options.UnsafeFPMath &&
16165 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16167 Opcode = X86ISD::FMIN;
16170 // Converting this to a min would handle both negative zeros and NaNs
16171 // incorrectly, but we can swap the operands to fix both.
16172 std::swap(LHS, RHS);
16176 Opcode = X86ISD::FMIN;
16180 // Converting this to a max would handle comparisons between positive
16181 // and negative zero incorrectly.
16182 if (!DAG.getTarget().Options.UnsafeFPMath &&
16183 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16185 Opcode = X86ISD::FMAX;
16188 // Converting this to a max would handle NaNs incorrectly, and swapping
16189 // the operands would cause it to handle comparisons between positive
16190 // and negative zero incorrectly.
16191 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16192 if (!DAG.getTarget().Options.UnsafeFPMath &&
16193 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16195 std::swap(LHS, RHS);
16197 Opcode = X86ISD::FMAX;
16200 // Converting this to a max would handle both negative zeros and NaNs
16201 // incorrectly, but we can swap the operands to fix both.
16202 std::swap(LHS, RHS);
16206 Opcode = X86ISD::FMAX;
16209 // Check for x CC y ? y : x -- a min/max with reversed arms.
16210 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16211 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16215 // Converting this to a min would handle comparisons between positive
16216 // and negative zero incorrectly, and swapping the operands would
16217 // cause it to handle NaNs incorrectly.
16218 if (!DAG.getTarget().Options.UnsafeFPMath &&
16219 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16220 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16222 std::swap(LHS, RHS);
16224 Opcode = X86ISD::FMIN;
16227 // Converting this to a min would handle NaNs incorrectly.
16228 if (!DAG.getTarget().Options.UnsafeFPMath &&
16229 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16231 Opcode = X86ISD::FMIN;
16234 // Converting this to a min would handle both negative zeros and NaNs
16235 // incorrectly, but we can swap the operands to fix both.
16236 std::swap(LHS, RHS);
16240 Opcode = X86ISD::FMIN;
16244 // Converting this to a max would handle NaNs incorrectly.
16245 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16247 Opcode = X86ISD::FMAX;
16250 // Converting this to a max would handle comparisons between positive
16251 // and negative zero incorrectly, and swapping the operands would
16252 // cause it to handle NaNs incorrectly.
16253 if (!DAG.getTarget().Options.UnsafeFPMath &&
16254 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16255 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16257 std::swap(LHS, RHS);
16259 Opcode = X86ISD::FMAX;
16262 // Converting this to a max would handle both negative zeros and NaNs
16263 // incorrectly, but we can swap the operands to fix both.
16264 std::swap(LHS, RHS);
16268 Opcode = X86ISD::FMAX;
16274 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16277 // If this is a select between two integer constants, try to do some
16279 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16280 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16281 // Don't do this for crazy integer types.
16282 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16283 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16284 // so that TrueC (the true value) is larger than FalseC.
16285 bool NeedsCondInvert = false;
16287 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16288 // Efficiently invertible.
16289 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16290 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16291 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16292 NeedsCondInvert = true;
16293 std::swap(TrueC, FalseC);
16296 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16297 if (FalseC->getAPIntValue() == 0 &&
16298 TrueC->getAPIntValue().isPowerOf2()) {
16299 if (NeedsCondInvert) // Invert the condition if needed.
16300 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16301 DAG.getConstant(1, Cond.getValueType()));
16303 // Zero extend the condition if needed.
16304 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16306 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16307 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16308 DAG.getConstant(ShAmt, MVT::i8));
16311 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16312 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16313 if (NeedsCondInvert) // Invert the condition if needed.
16314 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16315 DAG.getConstant(1, Cond.getValueType()));
16317 // Zero extend the condition if needed.
16318 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16319 FalseC->getValueType(0), Cond);
16320 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16321 SDValue(FalseC, 0));
16324 // Optimize cases that will turn into an LEA instruction. This requires
16325 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16326 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16327 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16328 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16330 bool isFastMultiplier = false;
16332 switch ((unsigned char)Diff) {
16334 case 1: // result = add base, cond
16335 case 2: // result = lea base( , cond*2)
16336 case 3: // result = lea base(cond, cond*2)
16337 case 4: // result = lea base( , cond*4)
16338 case 5: // result = lea base(cond, cond*4)
16339 case 8: // result = lea base( , cond*8)
16340 case 9: // result = lea base(cond, cond*8)
16341 isFastMultiplier = true;
16346 if (isFastMultiplier) {
16347 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16348 if (NeedsCondInvert) // Invert the condition if needed.
16349 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16350 DAG.getConstant(1, Cond.getValueType()));
16352 // Zero extend the condition if needed.
16353 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16355 // Scale the condition by the difference.
16357 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16358 DAG.getConstant(Diff, Cond.getValueType()));
16360 // Add the base if non-zero.
16361 if (FalseC->getAPIntValue() != 0)
16362 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16363 SDValue(FalseC, 0));
16370 // Canonicalize max and min:
16371 // (x > y) ? x : y -> (x >= y) ? x : y
16372 // (x < y) ? x : y -> (x <= y) ? x : y
16373 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16374 // the need for an extra compare
16375 // against zero. e.g.
16376 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16378 // testl %edi, %edi
16380 // cmovgl %edi, %eax
16384 // cmovsl %eax, %edi
16385 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16386 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16387 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16388 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16393 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16394 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16395 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16396 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16401 // Match VSELECTs into subs with unsigned saturation.
16402 if (!DCI.isBeforeLegalize() &&
16403 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16404 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16405 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16406 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16407 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16409 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16410 // left side invert the predicate to simplify logic below.
16412 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16414 CC = ISD::getSetCCInverse(CC, true);
16415 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16419 if (Other.getNode() && Other->getNumOperands() == 2 &&
16420 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16421 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16422 SDValue CondRHS = Cond->getOperand(1);
16424 // Look for a general sub with unsigned saturation first.
16425 // x >= y ? x-y : 0 --> subus x, y
16426 // x > y ? x-y : 0 --> subus x, y
16427 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16428 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16429 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16431 // If the RHS is a constant we have to reverse the const canonicalization.
16432 // x > C-1 ? x+-C : 0 --> subus x, C
16433 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16434 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16435 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16436 if (CondRHS.getConstantOperandVal(0) == -A-1)
16437 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16438 DAG.getConstant(-A, VT));
16441 // Another special case: If C was a sign bit, the sub has been
16442 // canonicalized into a xor.
16443 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16444 // it's safe to decanonicalize the xor?
16445 // x s< 0 ? x^C : 0 --> subus x, C
16446 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16447 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16448 isSplatVector(OpRHS.getNode())) {
16449 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16451 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16456 // Try to match a min/max vector operation.
16457 if (!DCI.isBeforeLegalize() &&
16458 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
16459 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
16460 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
16462 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16463 if (!DCI.isBeforeLegalize() && N->getOpcode() == ISD::VSELECT &&
16464 Cond.getOpcode() == ISD::SETCC) {
16466 assert(Cond.getValueType().isVector() &&
16467 "vector select expects a vector selector!");
16469 EVT IntVT = Cond.getValueType();
16470 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16471 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16473 if (!TValIsAllOnes && !FValIsAllZeros) {
16474 // Try invert the condition if true value is not all 1s and false value
16476 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16477 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16479 if (TValIsAllZeros || FValIsAllOnes) {
16480 SDValue CC = Cond.getOperand(2);
16481 ISD::CondCode NewCC =
16482 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16483 Cond.getOperand(0).getValueType().isInteger());
16484 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16485 std::swap(LHS, RHS);
16486 TValIsAllOnes = FValIsAllOnes;
16487 FValIsAllZeros = TValIsAllZeros;
16491 if (TValIsAllOnes || FValIsAllZeros) {
16494 if (TValIsAllOnes && FValIsAllZeros)
16496 else if (TValIsAllOnes)
16497 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16498 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16499 else if (FValIsAllZeros)
16500 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16501 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16503 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16507 // If we know that this node is legal then we know that it is going to be
16508 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16509 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16510 // to simplify previous instructions.
16511 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16512 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16513 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16514 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16516 // Don't optimize vector selects that map to mask-registers.
16520 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16521 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16523 APInt KnownZero, KnownOne;
16524 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16525 DCI.isBeforeLegalizeOps());
16526 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16527 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16528 DCI.CommitTargetLoweringOpt(TLO);
16534 // Check whether a boolean test is testing a boolean value generated by
16535 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16538 // Simplify the following patterns:
16539 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16540 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16541 // to (Op EFLAGS Cond)
16543 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16544 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16545 // to (Op EFLAGS !Cond)
16547 // where Op could be BRCOND or CMOV.
16549 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16550 // Quit if not CMP and SUB with its value result used.
16551 if (Cmp.getOpcode() != X86ISD::CMP &&
16552 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16555 // Quit if not used as a boolean value.
16556 if (CC != X86::COND_E && CC != X86::COND_NE)
16559 // Check CMP operands. One of them should be 0 or 1 and the other should be
16560 // an SetCC or extended from it.
16561 SDValue Op1 = Cmp.getOperand(0);
16562 SDValue Op2 = Cmp.getOperand(1);
16565 const ConstantSDNode* C = 0;
16566 bool needOppositeCond = (CC == X86::COND_E);
16567 bool checkAgainstTrue = false; // Is it a comparison against 1?
16569 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16571 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16573 else // Quit if all operands are not constants.
16576 if (C->getZExtValue() == 1) {
16577 needOppositeCond = !needOppositeCond;
16578 checkAgainstTrue = true;
16579 } else if (C->getZExtValue() != 0)
16580 // Quit if the constant is neither 0 or 1.
16583 bool truncatedToBoolWithAnd = false;
16584 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
16585 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
16586 SetCC.getOpcode() == ISD::TRUNCATE ||
16587 SetCC.getOpcode() == ISD::AND) {
16588 if (SetCC.getOpcode() == ISD::AND) {
16590 ConstantSDNode *CS;
16591 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
16592 CS->getZExtValue() == 1)
16594 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
16595 CS->getZExtValue() == 1)
16599 SetCC = SetCC.getOperand(OpIdx);
16600 truncatedToBoolWithAnd = true;
16602 SetCC = SetCC.getOperand(0);
16605 switch (SetCC.getOpcode()) {
16606 case X86ISD::SETCC_CARRY:
16607 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
16608 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
16609 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
16610 // truncated to i1 using 'and'.
16611 if (checkAgainstTrue && !truncatedToBoolWithAnd)
16613 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
16614 "Invalid use of SETCC_CARRY!");
16616 case X86ISD::SETCC:
16617 // Set the condition code or opposite one if necessary.
16618 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
16619 if (needOppositeCond)
16620 CC = X86::GetOppositeBranchCondition(CC);
16621 return SetCC.getOperand(1);
16622 case X86ISD::CMOV: {
16623 // Check whether false/true value has canonical one, i.e. 0 or 1.
16624 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
16625 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
16626 // Quit if true value is not a constant.
16629 // Quit if false value is not a constant.
16631 SDValue Op = SetCC.getOperand(0);
16632 // Skip 'zext' or 'trunc' node.
16633 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
16634 Op.getOpcode() == ISD::TRUNCATE)
16635 Op = Op.getOperand(0);
16636 // A special case for rdrand/rdseed, where 0 is set if false cond is
16638 if ((Op.getOpcode() != X86ISD::RDRAND &&
16639 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
16642 // Quit if false value is not the constant 0 or 1.
16643 bool FValIsFalse = true;
16644 if (FVal && FVal->getZExtValue() != 0) {
16645 if (FVal->getZExtValue() != 1)
16647 // If FVal is 1, opposite cond is needed.
16648 needOppositeCond = !needOppositeCond;
16649 FValIsFalse = false;
16651 // Quit if TVal is not the constant opposite of FVal.
16652 if (FValIsFalse && TVal->getZExtValue() != 1)
16654 if (!FValIsFalse && TVal->getZExtValue() != 0)
16656 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
16657 if (needOppositeCond)
16658 CC = X86::GetOppositeBranchCondition(CC);
16659 return SetCC.getOperand(3);
16666 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
16667 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
16668 TargetLowering::DAGCombinerInfo &DCI,
16669 const X86Subtarget *Subtarget) {
16672 // If the flag operand isn't dead, don't touch this CMOV.
16673 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
16676 SDValue FalseOp = N->getOperand(0);
16677 SDValue TrueOp = N->getOperand(1);
16678 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
16679 SDValue Cond = N->getOperand(3);
16681 if (CC == X86::COND_E || CC == X86::COND_NE) {
16682 switch (Cond.getOpcode()) {
16686 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
16687 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
16688 return (CC == X86::COND_E) ? FalseOp : TrueOp;
16694 Flags = checkBoolTestSetCCCombine(Cond, CC);
16695 if (Flags.getNode() &&
16696 // Extra check as FCMOV only supports a subset of X86 cond.
16697 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
16698 SDValue Ops[] = { FalseOp, TrueOp,
16699 DAG.getConstant(CC, MVT::i8), Flags };
16700 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
16701 Ops, array_lengthof(Ops));
16704 // If this is a select between two integer constants, try to do some
16705 // optimizations. Note that the operands are ordered the opposite of SELECT
16707 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
16708 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
16709 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
16710 // larger than FalseC (the false value).
16711 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
16712 CC = X86::GetOppositeBranchCondition(CC);
16713 std::swap(TrueC, FalseC);
16714 std::swap(TrueOp, FalseOp);
16717 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
16718 // This is efficient for any integer data type (including i8/i16) and
16720 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
16721 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16722 DAG.getConstant(CC, MVT::i8), Cond);
16724 // Zero extend the condition if needed.
16725 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
16727 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16728 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
16729 DAG.getConstant(ShAmt, MVT::i8));
16730 if (N->getNumValues() == 2) // Dead flag value?
16731 return DCI.CombineTo(N, Cond, SDValue());
16735 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
16736 // for any integer data type, including i8/i16.
16737 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16738 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16739 DAG.getConstant(CC, MVT::i8), Cond);
16741 // Zero extend the condition if needed.
16742 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16743 FalseC->getValueType(0), Cond);
16744 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16745 SDValue(FalseC, 0));
16747 if (N->getNumValues() == 2) // Dead flag value?
16748 return DCI.CombineTo(N, Cond, SDValue());
16752 // Optimize cases that will turn into an LEA instruction. This requires
16753 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16754 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16755 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16756 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16758 bool isFastMultiplier = false;
16760 switch ((unsigned char)Diff) {
16762 case 1: // result = add base, cond
16763 case 2: // result = lea base( , cond*2)
16764 case 3: // result = lea base(cond, cond*2)
16765 case 4: // result = lea base( , cond*4)
16766 case 5: // result = lea base(cond, cond*4)
16767 case 8: // result = lea base( , cond*8)
16768 case 9: // result = lea base(cond, cond*8)
16769 isFastMultiplier = true;
16774 if (isFastMultiplier) {
16775 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16776 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16777 DAG.getConstant(CC, MVT::i8), Cond);
16778 // Zero extend the condition if needed.
16779 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16781 // Scale the condition by the difference.
16783 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16784 DAG.getConstant(Diff, Cond.getValueType()));
16786 // Add the base if non-zero.
16787 if (FalseC->getAPIntValue() != 0)
16788 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16789 SDValue(FalseC, 0));
16790 if (N->getNumValues() == 2) // Dead flag value?
16791 return DCI.CombineTo(N, Cond, SDValue());
16798 // Handle these cases:
16799 // (select (x != c), e, c) -> select (x != c), e, x),
16800 // (select (x == c), c, e) -> select (x == c), x, e)
16801 // where the c is an integer constant, and the "select" is the combination
16802 // of CMOV and CMP.
16804 // The rationale for this change is that the conditional-move from a constant
16805 // needs two instructions, however, conditional-move from a register needs
16806 // only one instruction.
16808 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
16809 // some instruction-combining opportunities. This opt needs to be
16810 // postponed as late as possible.
16812 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
16813 // the DCI.xxxx conditions are provided to postpone the optimization as
16814 // late as possible.
16816 ConstantSDNode *CmpAgainst = 0;
16817 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
16818 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
16819 !isa<ConstantSDNode>(Cond.getOperand(0))) {
16821 if (CC == X86::COND_NE &&
16822 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
16823 CC = X86::GetOppositeBranchCondition(CC);
16824 std::swap(TrueOp, FalseOp);
16827 if (CC == X86::COND_E &&
16828 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
16829 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
16830 DAG.getConstant(CC, MVT::i8), Cond };
16831 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
16832 array_lengthof(Ops));
16840 /// PerformMulCombine - Optimize a single multiply with constant into two
16841 /// in order to implement it with two cheaper instructions, e.g.
16842 /// LEA + SHL, LEA + LEA.
16843 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
16844 TargetLowering::DAGCombinerInfo &DCI) {
16845 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16848 EVT VT = N->getValueType(0);
16849 if (VT != MVT::i64)
16852 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
16855 uint64_t MulAmt = C->getZExtValue();
16856 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
16859 uint64_t MulAmt1 = 0;
16860 uint64_t MulAmt2 = 0;
16861 if ((MulAmt % 9) == 0) {
16863 MulAmt2 = MulAmt / 9;
16864 } else if ((MulAmt % 5) == 0) {
16866 MulAmt2 = MulAmt / 5;
16867 } else if ((MulAmt % 3) == 0) {
16869 MulAmt2 = MulAmt / 3;
16872 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
16875 if (isPowerOf2_64(MulAmt2) &&
16876 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
16877 // If second multiplifer is pow2, issue it first. We want the multiply by
16878 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
16880 std::swap(MulAmt1, MulAmt2);
16883 if (isPowerOf2_64(MulAmt1))
16884 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
16885 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
16887 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
16888 DAG.getConstant(MulAmt1, VT));
16890 if (isPowerOf2_64(MulAmt2))
16891 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
16892 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
16894 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
16895 DAG.getConstant(MulAmt2, VT));
16897 // Do not add new nodes to DAG combiner worklist.
16898 DCI.CombineTo(N, NewMul, false);
16903 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
16904 SDValue N0 = N->getOperand(0);
16905 SDValue N1 = N->getOperand(1);
16906 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
16907 EVT VT = N0.getValueType();
16909 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
16910 // since the result of setcc_c is all zero's or all ones.
16911 if (VT.isInteger() && !VT.isVector() &&
16912 N1C && N0.getOpcode() == ISD::AND &&
16913 N0.getOperand(1).getOpcode() == ISD::Constant) {
16914 SDValue N00 = N0.getOperand(0);
16915 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
16916 ((N00.getOpcode() == ISD::ANY_EXTEND ||
16917 N00.getOpcode() == ISD::ZERO_EXTEND) &&
16918 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
16919 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
16920 APInt ShAmt = N1C->getAPIntValue();
16921 Mask = Mask.shl(ShAmt);
16923 return DAG.getNode(ISD::AND, SDLoc(N), VT,
16924 N00, DAG.getConstant(Mask, VT));
16928 // Hardware support for vector shifts is sparse which makes us scalarize the
16929 // vector operations in many cases. Also, on sandybridge ADD is faster than
16931 // (shl V, 1) -> add V,V
16932 if (isSplatVector(N1.getNode())) {
16933 assert(N0.getValueType().isVector() && "Invalid vector shift type");
16934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
16935 // We shift all of the values by one. In many cases we do not have
16936 // hardware support for this operation. This is better expressed as an ADD
16938 if (N1C && (1 == N1C->getZExtValue())) {
16939 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
16946 /// \brief Returns a vector of 0s if the node in input is a vector logical
16947 /// shift by a constant amount which is known to be bigger than or equal
16948 /// to the vector element size in bits.
16949 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
16950 const X86Subtarget *Subtarget) {
16951 EVT VT = N->getValueType(0);
16953 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
16954 (!Subtarget->hasInt256() ||
16955 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
16958 SDValue Amt = N->getOperand(1);
16960 if (isSplatVector(Amt.getNode())) {
16961 SDValue SclrAmt = Amt->getOperand(0);
16962 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
16963 APInt ShiftAmt = C->getAPIntValue();
16964 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
16966 // SSE2/AVX2 logical shifts always return a vector of 0s
16967 // if the shift amount is bigger than or equal to
16968 // the element size. The constant shift amount will be
16969 // encoded as a 8-bit immediate.
16970 if (ShiftAmt.trunc(8).uge(MaxAmount))
16971 return getZeroVector(VT, Subtarget, DAG, DL);
16978 /// PerformShiftCombine - Combine shifts.
16979 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
16980 TargetLowering::DAGCombinerInfo &DCI,
16981 const X86Subtarget *Subtarget) {
16982 if (N->getOpcode() == ISD::SHL) {
16983 SDValue V = PerformSHLCombine(N, DAG);
16984 if (V.getNode()) return V;
16987 if (N->getOpcode() != ISD::SRA) {
16988 // Try to fold this logical shift into a zero vector.
16989 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
16990 if (V.getNode()) return V;
16996 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
16997 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
16998 // and friends. Likewise for OR -> CMPNEQSS.
16999 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17000 TargetLowering::DAGCombinerInfo &DCI,
17001 const X86Subtarget *Subtarget) {
17004 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17005 // we're requiring SSE2 for both.
17006 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17007 SDValue N0 = N->getOperand(0);
17008 SDValue N1 = N->getOperand(1);
17009 SDValue CMP0 = N0->getOperand(1);
17010 SDValue CMP1 = N1->getOperand(1);
17013 // The SETCCs should both refer to the same CMP.
17014 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17017 SDValue CMP00 = CMP0->getOperand(0);
17018 SDValue CMP01 = CMP0->getOperand(1);
17019 EVT VT = CMP00.getValueType();
17021 if (VT == MVT::f32 || VT == MVT::f64) {
17022 bool ExpectingFlags = false;
17023 // Check for any users that want flags:
17024 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17025 !ExpectingFlags && UI != UE; ++UI)
17026 switch (UI->getOpcode()) {
17031 ExpectingFlags = true;
17033 case ISD::CopyToReg:
17034 case ISD::SIGN_EXTEND:
17035 case ISD::ZERO_EXTEND:
17036 case ISD::ANY_EXTEND:
17040 if (!ExpectingFlags) {
17041 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17042 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17044 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17045 X86::CondCode tmp = cc0;
17050 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17051 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17052 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17053 X86ISD::NodeType NTOperator = is64BitFP ?
17054 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17055 // FIXME: need symbolic constants for these magic numbers.
17056 // See X86ATTInstPrinter.cpp:printSSECC().
17057 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17058 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17059 DAG.getConstant(x86cc, MVT::i8));
17060 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17062 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17063 DAG.getConstant(1, MVT::i32));
17064 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17065 return OneBitOfTruth;
17073 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17074 /// so it can be folded inside ANDNP.
17075 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17076 EVT VT = N->getValueType(0);
17078 // Match direct AllOnes for 128 and 256-bit vectors
17079 if (ISD::isBuildVectorAllOnes(N))
17082 // Look through a bit convert.
17083 if (N->getOpcode() == ISD::BITCAST)
17084 N = N->getOperand(0).getNode();
17086 // Sometimes the operand may come from a insert_subvector building a 256-bit
17088 if (VT.is256BitVector() &&
17089 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17090 SDValue V1 = N->getOperand(0);
17091 SDValue V2 = N->getOperand(1);
17093 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17094 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17095 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17096 ISD::isBuildVectorAllOnes(V2.getNode()))
17103 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17104 // register. In most cases we actually compare or select YMM-sized registers
17105 // and mixing the two types creates horrible code. This method optimizes
17106 // some of the transition sequences.
17107 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17108 TargetLowering::DAGCombinerInfo &DCI,
17109 const X86Subtarget *Subtarget) {
17110 EVT VT = N->getValueType(0);
17111 if (!VT.is256BitVector())
17114 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17115 N->getOpcode() == ISD::ZERO_EXTEND ||
17116 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17118 SDValue Narrow = N->getOperand(0);
17119 EVT NarrowVT = Narrow->getValueType(0);
17120 if (!NarrowVT.is128BitVector())
17123 if (Narrow->getOpcode() != ISD::XOR &&
17124 Narrow->getOpcode() != ISD::AND &&
17125 Narrow->getOpcode() != ISD::OR)
17128 SDValue N0 = Narrow->getOperand(0);
17129 SDValue N1 = Narrow->getOperand(1);
17132 // The Left side has to be a trunc.
17133 if (N0.getOpcode() != ISD::TRUNCATE)
17136 // The type of the truncated inputs.
17137 EVT WideVT = N0->getOperand(0)->getValueType(0);
17141 // The right side has to be a 'trunc' or a constant vector.
17142 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17143 bool RHSConst = (isSplatVector(N1.getNode()) &&
17144 isa<ConstantSDNode>(N1->getOperand(0)));
17145 if (!RHSTrunc && !RHSConst)
17148 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17150 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17153 // Set N0 and N1 to hold the inputs to the new wide operation.
17154 N0 = N0->getOperand(0);
17156 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17157 N1->getOperand(0));
17158 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17159 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17160 } else if (RHSTrunc) {
17161 N1 = N1->getOperand(0);
17164 // Generate the wide operation.
17165 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17166 unsigned Opcode = N->getOpcode();
17168 case ISD::ANY_EXTEND:
17170 case ISD::ZERO_EXTEND: {
17171 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17172 APInt Mask = APInt::getAllOnesValue(InBits);
17173 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17174 return DAG.getNode(ISD::AND, DL, VT,
17175 Op, DAG.getConstant(Mask, VT));
17177 case ISD::SIGN_EXTEND:
17178 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17179 Op, DAG.getValueType(NarrowVT));
17181 llvm_unreachable("Unexpected opcode");
17185 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17186 TargetLowering::DAGCombinerInfo &DCI,
17187 const X86Subtarget *Subtarget) {
17188 EVT VT = N->getValueType(0);
17189 if (DCI.isBeforeLegalizeOps())
17192 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17196 // Create BLSI, and BLSR instructions
17197 // BLSI is X & (-X)
17198 // BLSR is X & (X-1)
17199 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
17200 SDValue N0 = N->getOperand(0);
17201 SDValue N1 = N->getOperand(1);
17204 // Check LHS for neg
17205 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17206 isZero(N0.getOperand(0)))
17207 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17209 // Check RHS for neg
17210 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17211 isZero(N1.getOperand(0)))
17212 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17214 // Check LHS for X-1
17215 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17216 isAllOnes(N0.getOperand(1)))
17217 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17219 // Check RHS for X-1
17220 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17221 isAllOnes(N1.getOperand(1)))
17222 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17227 // Want to form ANDNP nodes:
17228 // 1) In the hopes of then easily combining them with OR and AND nodes
17229 // to form PBLEND/PSIGN.
17230 // 2) To match ANDN packed intrinsics
17231 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17234 SDValue N0 = N->getOperand(0);
17235 SDValue N1 = N->getOperand(1);
17238 // Check LHS for vnot
17239 if (N0.getOpcode() == ISD::XOR &&
17240 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17241 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17242 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17244 // Check RHS for vnot
17245 if (N1.getOpcode() == ISD::XOR &&
17246 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17247 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17248 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17253 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17254 TargetLowering::DAGCombinerInfo &DCI,
17255 const X86Subtarget *Subtarget) {
17256 EVT VT = N->getValueType(0);
17257 if (DCI.isBeforeLegalizeOps())
17260 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17264 SDValue N0 = N->getOperand(0);
17265 SDValue N1 = N->getOperand(1);
17267 // look for psign/blend
17268 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17269 if (!Subtarget->hasSSSE3() ||
17270 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17273 // Canonicalize pandn to RHS
17274 if (N0.getOpcode() == X86ISD::ANDNP)
17276 // or (and (m, y), (pandn m, x))
17277 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17278 SDValue Mask = N1.getOperand(0);
17279 SDValue X = N1.getOperand(1);
17281 if (N0.getOperand(0) == Mask)
17282 Y = N0.getOperand(1);
17283 if (N0.getOperand(1) == Mask)
17284 Y = N0.getOperand(0);
17286 // Check to see if the mask appeared in both the AND and ANDNP and
17290 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17291 // Look through mask bitcast.
17292 if (Mask.getOpcode() == ISD::BITCAST)
17293 Mask = Mask.getOperand(0);
17294 if (X.getOpcode() == ISD::BITCAST)
17295 X = X.getOperand(0);
17296 if (Y.getOpcode() == ISD::BITCAST)
17297 Y = Y.getOperand(0);
17299 EVT MaskVT = Mask.getValueType();
17301 // Validate that the Mask operand is a vector sra node.
17302 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17303 // there is no psrai.b
17304 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17305 unsigned SraAmt = ~0;
17306 if (Mask.getOpcode() == ISD::SRA) {
17307 SDValue Amt = Mask.getOperand(1);
17308 if (isSplatVector(Amt.getNode())) {
17309 SDValue SclrAmt = Amt->getOperand(0);
17310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17311 SraAmt = C->getZExtValue();
17313 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17314 SDValue SraC = Mask.getOperand(1);
17315 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17317 if ((SraAmt + 1) != EltBits)
17322 // Now we know we at least have a plendvb with the mask val. See if
17323 // we can form a psignb/w/d.
17324 // psign = x.type == y.type == mask.type && y = sub(0, x);
17325 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17326 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17327 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17328 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17329 "Unsupported VT for PSIGN");
17330 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17331 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17333 // PBLENDVB only available on SSE 4.1
17334 if (!Subtarget->hasSSE41())
17337 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17339 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17340 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17341 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17342 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17343 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17347 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17350 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17351 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17353 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17355 if (!N0.hasOneUse() || !N1.hasOneUse())
17358 SDValue ShAmt0 = N0.getOperand(1);
17359 if (ShAmt0.getValueType() != MVT::i8)
17361 SDValue ShAmt1 = N1.getOperand(1);
17362 if (ShAmt1.getValueType() != MVT::i8)
17364 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17365 ShAmt0 = ShAmt0.getOperand(0);
17366 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17367 ShAmt1 = ShAmt1.getOperand(0);
17370 unsigned Opc = X86ISD::SHLD;
17371 SDValue Op0 = N0.getOperand(0);
17372 SDValue Op1 = N1.getOperand(0);
17373 if (ShAmt0.getOpcode() == ISD::SUB) {
17374 Opc = X86ISD::SHRD;
17375 std::swap(Op0, Op1);
17376 std::swap(ShAmt0, ShAmt1);
17379 unsigned Bits = VT.getSizeInBits();
17380 if (ShAmt1.getOpcode() == ISD::SUB) {
17381 SDValue Sum = ShAmt1.getOperand(0);
17382 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17383 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17384 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17385 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17386 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17387 return DAG.getNode(Opc, DL, VT,
17389 DAG.getNode(ISD::TRUNCATE, DL,
17392 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17393 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17395 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17396 return DAG.getNode(Opc, DL, VT,
17397 N0.getOperand(0), N1.getOperand(0),
17398 DAG.getNode(ISD::TRUNCATE, DL,
17405 // Generate NEG and CMOV for integer abs.
17406 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17407 EVT VT = N->getValueType(0);
17409 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17410 // 8-bit integer abs to NEG and CMOV.
17411 if (VT.isInteger() && VT.getSizeInBits() == 8)
17414 SDValue N0 = N->getOperand(0);
17415 SDValue N1 = N->getOperand(1);
17418 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17419 // and change it to SUB and CMOV.
17420 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17421 N0.getOpcode() == ISD::ADD &&
17422 N0.getOperand(1) == N1 &&
17423 N1.getOpcode() == ISD::SRA &&
17424 N1.getOperand(0) == N0.getOperand(0))
17425 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17426 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17427 // Generate SUB & CMOV.
17428 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17429 DAG.getConstant(0, VT), N0.getOperand(0));
17431 SDValue Ops[] = { N0.getOperand(0), Neg,
17432 DAG.getConstant(X86::COND_GE, MVT::i8),
17433 SDValue(Neg.getNode(), 1) };
17434 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17435 Ops, array_lengthof(Ops));
17440 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17441 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17442 TargetLowering::DAGCombinerInfo &DCI,
17443 const X86Subtarget *Subtarget) {
17444 EVT VT = N->getValueType(0);
17445 if (DCI.isBeforeLegalizeOps())
17448 if (Subtarget->hasCMov()) {
17449 SDValue RV = performIntegerAbsCombine(N, DAG);
17454 // Try forming BMI if it is available.
17455 if (!Subtarget->hasBMI())
17458 if (VT != MVT::i32 && VT != MVT::i64)
17461 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17463 // Create BLSMSK instructions by finding X ^ (X-1)
17464 SDValue N0 = N->getOperand(0);
17465 SDValue N1 = N->getOperand(1);
17468 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17469 isAllOnes(N0.getOperand(1)))
17470 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17472 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17473 isAllOnes(N1.getOperand(1)))
17474 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17479 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17480 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17481 TargetLowering::DAGCombinerInfo &DCI,
17482 const X86Subtarget *Subtarget) {
17483 LoadSDNode *Ld = cast<LoadSDNode>(N);
17484 EVT RegVT = Ld->getValueType(0);
17485 EVT MemVT = Ld->getMemoryVT();
17487 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17488 unsigned RegSz = RegVT.getSizeInBits();
17490 // On Sandybridge unaligned 256bit loads are inefficient.
17491 ISD::LoadExtType Ext = Ld->getExtensionType();
17492 unsigned Alignment = Ld->getAlignment();
17493 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17494 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17495 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17496 unsigned NumElems = RegVT.getVectorNumElements();
17500 SDValue Ptr = Ld->getBasePtr();
17501 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17503 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17505 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17506 Ld->getPointerInfo(), Ld->isVolatile(),
17507 Ld->isNonTemporal(), Ld->isInvariant(),
17509 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17510 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17511 Ld->getPointerInfo(), Ld->isVolatile(),
17512 Ld->isNonTemporal(), Ld->isInvariant(),
17513 std::min(16U, Alignment));
17514 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17516 Load2.getValue(1));
17518 SDValue NewVec = DAG.getUNDEF(RegVT);
17519 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17520 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17521 return DCI.CombineTo(N, NewVec, TF, true);
17524 // If this is a vector EXT Load then attempt to optimize it using a
17525 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17526 // expansion is still better than scalar code.
17527 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17528 // emit a shuffle and a arithmetic shift.
17529 // TODO: It is possible to support ZExt by zeroing the undef values
17530 // during the shuffle phase or after the shuffle.
17531 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
17532 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
17533 assert(MemVT != RegVT && "Cannot extend to the same type");
17534 assert(MemVT.isVector() && "Must load a vector from memory");
17536 unsigned NumElems = RegVT.getVectorNumElements();
17537 unsigned MemSz = MemVT.getSizeInBits();
17538 assert(RegSz > MemSz && "Register size must be greater than the mem size");
17540 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
17543 // All sizes must be a power of two.
17544 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
17547 // Attempt to load the original value using scalar loads.
17548 // Find the largest scalar type that divides the total loaded size.
17549 MVT SclrLoadTy = MVT::i8;
17550 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17551 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17552 MVT Tp = (MVT::SimpleValueType)tp;
17553 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
17558 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17559 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
17561 SclrLoadTy = MVT::f64;
17563 // Calculate the number of scalar loads that we need to perform
17564 // in order to load our vector from memory.
17565 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
17566 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
17569 unsigned loadRegZize = RegSz;
17570 if (Ext == ISD::SEXTLOAD && RegSz == 256)
17573 // Represent our vector as a sequence of elements which are the
17574 // largest scalar that we can load.
17575 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
17576 loadRegZize/SclrLoadTy.getSizeInBits());
17578 // Represent the data using the same element type that is stored in
17579 // memory. In practice, we ''widen'' MemVT.
17581 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17582 loadRegZize/MemVT.getScalarType().getSizeInBits());
17584 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
17585 "Invalid vector type");
17587 // We can't shuffle using an illegal type.
17588 if (!TLI.isTypeLegal(WideVecVT))
17591 SmallVector<SDValue, 8> Chains;
17592 SDValue Ptr = Ld->getBasePtr();
17593 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
17594 TLI.getPointerTy());
17595 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
17597 for (unsigned i = 0; i < NumLoads; ++i) {
17598 // Perform a single load.
17599 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
17600 Ptr, Ld->getPointerInfo(),
17601 Ld->isVolatile(), Ld->isNonTemporal(),
17602 Ld->isInvariant(), Ld->getAlignment());
17603 Chains.push_back(ScalarLoad.getValue(1));
17604 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
17605 // another round of DAGCombining.
17607 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
17609 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
17610 ScalarLoad, DAG.getIntPtrConstant(i));
17612 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17615 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17618 // Bitcast the loaded value to a vector of the original element type, in
17619 // the size of the target vector type.
17620 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
17621 unsigned SizeRatio = RegSz/MemSz;
17623 if (Ext == ISD::SEXTLOAD) {
17624 // If we have SSE4.1 we can directly emit a VSEXT node.
17625 if (Subtarget->hasSSE41()) {
17626 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
17627 return DCI.CombineTo(N, Sext, TF, true);
17630 // Otherwise we'll shuffle the small elements in the high bits of the
17631 // larger type and perform an arithmetic shift. If the shift is not legal
17632 // it's better to scalarize.
17633 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
17636 // Redistribute the loaded elements into the different locations.
17637 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17638 for (unsigned i = 0; i != NumElems; ++i)
17639 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
17641 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
17642 DAG.getUNDEF(WideVecVT),
17645 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
17647 // Build the arithmetic shift.
17648 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
17649 MemVT.getVectorElementType().getSizeInBits();
17650 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
17651 DAG.getConstant(Amt, RegVT));
17653 return DCI.CombineTo(N, Shuff, TF, true);
17656 // Redistribute the loaded elements into the different locations.
17657 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17658 for (unsigned i = 0; i != NumElems; ++i)
17659 ShuffleVec[i*SizeRatio] = i;
17661 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
17662 DAG.getUNDEF(WideVecVT),
17665 // Bitcast to the requested type.
17666 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
17667 // Replace the original load with the new sequence
17668 // and return the new chain.
17669 return DCI.CombineTo(N, Shuff, TF, true);
17675 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
17676 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
17677 const X86Subtarget *Subtarget) {
17678 StoreSDNode *St = cast<StoreSDNode>(N);
17679 EVT VT = St->getValue().getValueType();
17680 EVT StVT = St->getMemoryVT();
17682 SDValue StoredVal = St->getOperand(1);
17683 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17685 // If we are saving a concatenation of two XMM registers, perform two stores.
17686 // On Sandy Bridge, 256-bit memory operations are executed by two
17687 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
17688 // memory operation.
17689 unsigned Alignment = St->getAlignment();
17690 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
17691 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
17692 StVT == VT && !IsAligned) {
17693 unsigned NumElems = VT.getVectorNumElements();
17697 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
17698 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
17700 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
17701 SDValue Ptr0 = St->getBasePtr();
17702 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
17704 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
17705 St->getPointerInfo(), St->isVolatile(),
17706 St->isNonTemporal(), Alignment);
17707 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
17708 St->getPointerInfo(), St->isVolatile(),
17709 St->isNonTemporal(),
17710 std::min(16U, Alignment));
17711 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
17714 // Optimize trunc store (of multiple scalars) to shuffle and store.
17715 // First, pack all of the elements in one place. Next, store to memory
17716 // in fewer chunks.
17717 if (St->isTruncatingStore() && VT.isVector()) {
17718 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17719 unsigned NumElems = VT.getVectorNumElements();
17720 assert(StVT != VT && "Cannot truncate to the same type");
17721 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
17722 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
17724 // From, To sizes and ElemCount must be pow of two
17725 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
17726 // We are going to use the original vector elt for storing.
17727 // Accumulated smaller vector elements must be a multiple of the store size.
17728 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
17730 unsigned SizeRatio = FromSz / ToSz;
17732 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
17734 // Create a type on which we perform the shuffle
17735 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
17736 StVT.getScalarType(), NumElems*SizeRatio);
17738 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
17740 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
17741 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17742 for (unsigned i = 0; i != NumElems; ++i)
17743 ShuffleVec[i] = i * SizeRatio;
17745 // Can't shuffle using an illegal type.
17746 if (!TLI.isTypeLegal(WideVecVT))
17749 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
17750 DAG.getUNDEF(WideVecVT),
17752 // At this point all of the data is stored at the bottom of the
17753 // register. We now need to save it to mem.
17755 // Find the largest store unit
17756 MVT StoreType = MVT::i8;
17757 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17758 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17759 MVT Tp = (MVT::SimpleValueType)tp;
17760 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
17764 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17765 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
17766 (64 <= NumElems * ToSz))
17767 StoreType = MVT::f64;
17769 // Bitcast the original vector into a vector of store-size units
17770 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
17771 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
17772 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
17773 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
17774 SmallVector<SDValue, 8> Chains;
17775 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
17776 TLI.getPointerTy());
17777 SDValue Ptr = St->getBasePtr();
17779 // Perform one or more big stores into memory.
17780 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
17781 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
17782 StoreType, ShuffWide,
17783 DAG.getIntPtrConstant(i));
17784 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
17785 St->getPointerInfo(), St->isVolatile(),
17786 St->isNonTemporal(), St->getAlignment());
17787 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17788 Chains.push_back(Ch);
17791 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17795 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
17796 // the FP state in cases where an emms may be missing.
17797 // A preferable solution to the general problem is to figure out the right
17798 // places to insert EMMS. This qualifies as a quick hack.
17800 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
17801 if (VT.getSizeInBits() != 64)
17804 const Function *F = DAG.getMachineFunction().getFunction();
17805 bool NoImplicitFloatOps = F->getAttributes().
17806 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
17807 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
17808 && Subtarget->hasSSE2();
17809 if ((VT.isVector() ||
17810 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
17811 isa<LoadSDNode>(St->getValue()) &&
17812 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
17813 St->getChain().hasOneUse() && !St->isVolatile()) {
17814 SDNode* LdVal = St->getValue().getNode();
17815 LoadSDNode *Ld = 0;
17816 int TokenFactorIndex = -1;
17817 SmallVector<SDValue, 8> Ops;
17818 SDNode* ChainVal = St->getChain().getNode();
17819 // Must be a store of a load. We currently handle two cases: the load
17820 // is a direct child, and it's under an intervening TokenFactor. It is
17821 // possible to dig deeper under nested TokenFactors.
17822 if (ChainVal == LdVal)
17823 Ld = cast<LoadSDNode>(St->getChain());
17824 else if (St->getValue().hasOneUse() &&
17825 ChainVal->getOpcode() == ISD::TokenFactor) {
17826 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
17827 if (ChainVal->getOperand(i).getNode() == LdVal) {
17828 TokenFactorIndex = i;
17829 Ld = cast<LoadSDNode>(St->getValue());
17831 Ops.push_back(ChainVal->getOperand(i));
17835 if (!Ld || !ISD::isNormalLoad(Ld))
17838 // If this is not the MMX case, i.e. we are just turning i64 load/store
17839 // into f64 load/store, avoid the transformation if there are multiple
17840 // uses of the loaded value.
17841 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
17846 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
17847 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
17849 if (Subtarget->is64Bit() || F64IsLegal) {
17850 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
17851 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
17852 Ld->getPointerInfo(), Ld->isVolatile(),
17853 Ld->isNonTemporal(), Ld->isInvariant(),
17854 Ld->getAlignment());
17855 SDValue NewChain = NewLd.getValue(1);
17856 if (TokenFactorIndex != -1) {
17857 Ops.push_back(NewChain);
17858 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17861 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
17862 St->getPointerInfo(),
17863 St->isVolatile(), St->isNonTemporal(),
17864 St->getAlignment());
17867 // Otherwise, lower to two pairs of 32-bit loads / stores.
17868 SDValue LoAddr = Ld->getBasePtr();
17869 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
17870 DAG.getConstant(4, MVT::i32));
17872 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
17873 Ld->getPointerInfo(),
17874 Ld->isVolatile(), Ld->isNonTemporal(),
17875 Ld->isInvariant(), Ld->getAlignment());
17876 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
17877 Ld->getPointerInfo().getWithOffset(4),
17878 Ld->isVolatile(), Ld->isNonTemporal(),
17880 MinAlign(Ld->getAlignment(), 4));
17882 SDValue NewChain = LoLd.getValue(1);
17883 if (TokenFactorIndex != -1) {
17884 Ops.push_back(LoLd);
17885 Ops.push_back(HiLd);
17886 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17890 LoAddr = St->getBasePtr();
17891 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
17892 DAG.getConstant(4, MVT::i32));
17894 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
17895 St->getPointerInfo(),
17896 St->isVolatile(), St->isNonTemporal(),
17897 St->getAlignment());
17898 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
17899 St->getPointerInfo().getWithOffset(4),
17901 St->isNonTemporal(),
17902 MinAlign(St->getAlignment(), 4));
17903 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
17908 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
17909 /// and return the operands for the horizontal operation in LHS and RHS. A
17910 /// horizontal operation performs the binary operation on successive elements
17911 /// of its first operand, then on successive elements of its second operand,
17912 /// returning the resulting values in a vector. For example, if
17913 /// A = < float a0, float a1, float a2, float a3 >
17915 /// B = < float b0, float b1, float b2, float b3 >
17916 /// then the result of doing a horizontal operation on A and B is
17917 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
17918 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
17919 /// A horizontal-op B, for some already available A and B, and if so then LHS is
17920 /// set to A, RHS to B, and the routine returns 'true'.
17921 /// Note that the binary operation should have the property that if one of the
17922 /// operands is UNDEF then the result is UNDEF.
17923 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
17924 // Look for the following pattern: if
17925 // A = < float a0, float a1, float a2, float a3 >
17926 // B = < float b0, float b1, float b2, float b3 >
17928 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
17929 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
17930 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
17931 // which is A horizontal-op B.
17933 // At least one of the operands should be a vector shuffle.
17934 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
17935 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
17938 MVT VT = LHS.getSimpleValueType();
17940 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17941 "Unsupported vector type for horizontal add/sub");
17943 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
17944 // operate independently on 128-bit lanes.
17945 unsigned NumElts = VT.getVectorNumElements();
17946 unsigned NumLanes = VT.getSizeInBits()/128;
17947 unsigned NumLaneElts = NumElts / NumLanes;
17948 assert((NumLaneElts % 2 == 0) &&
17949 "Vector type should have an even number of elements in each lane");
17950 unsigned HalfLaneElts = NumLaneElts/2;
17952 // View LHS in the form
17953 // LHS = VECTOR_SHUFFLE A, B, LMask
17954 // If LHS is not a shuffle then pretend it is the shuffle
17955 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
17956 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
17959 SmallVector<int, 16> LMask(NumElts);
17960 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17961 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
17962 A = LHS.getOperand(0);
17963 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
17964 B = LHS.getOperand(1);
17965 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
17966 std::copy(Mask.begin(), Mask.end(), LMask.begin());
17968 if (LHS.getOpcode() != ISD::UNDEF)
17970 for (unsigned i = 0; i != NumElts; ++i)
17974 // Likewise, view RHS in the form
17975 // RHS = VECTOR_SHUFFLE C, D, RMask
17977 SmallVector<int, 16> RMask(NumElts);
17978 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17979 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
17980 C = RHS.getOperand(0);
17981 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
17982 D = RHS.getOperand(1);
17983 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
17984 std::copy(Mask.begin(), Mask.end(), RMask.begin());
17986 if (RHS.getOpcode() != ISD::UNDEF)
17988 for (unsigned i = 0; i != NumElts; ++i)
17992 // Check that the shuffles are both shuffling the same vectors.
17993 if (!(A == C && B == D) && !(A == D && B == C))
17996 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
17997 if (!A.getNode() && !B.getNode())
18000 // If A and B occur in reverse order in RHS, then "swap" them (which means
18001 // rewriting the mask).
18003 CommuteVectorShuffleMask(RMask, NumElts);
18005 // At this point LHS and RHS are equivalent to
18006 // LHS = VECTOR_SHUFFLE A, B, LMask
18007 // RHS = VECTOR_SHUFFLE A, B, RMask
18008 // Check that the masks correspond to performing a horizontal operation.
18009 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18010 for (unsigned i = 0; i != NumLaneElts; ++i) {
18011 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18013 // Ignore any UNDEF components.
18014 if (LIdx < 0 || RIdx < 0 ||
18015 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18016 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18019 // Check that successive elements are being operated on. If not, this is
18020 // not a horizontal operation.
18021 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18022 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18023 if (!(LIdx == Index && RIdx == Index + 1) &&
18024 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18029 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18030 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18034 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18035 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18036 const X86Subtarget *Subtarget) {
18037 EVT VT = N->getValueType(0);
18038 SDValue LHS = N->getOperand(0);
18039 SDValue RHS = N->getOperand(1);
18041 // Try to synthesize horizontal adds from adds of shuffles.
18042 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18043 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18044 isHorizontalBinOp(LHS, RHS, true))
18045 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18049 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18050 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18051 const X86Subtarget *Subtarget) {
18052 EVT VT = N->getValueType(0);
18053 SDValue LHS = N->getOperand(0);
18054 SDValue RHS = N->getOperand(1);
18056 // Try to synthesize horizontal subs from subs of shuffles.
18057 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18058 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18059 isHorizontalBinOp(LHS, RHS, false))
18060 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18064 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18065 /// X86ISD::FXOR nodes.
18066 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18067 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18068 // F[X]OR(0.0, x) -> x
18069 // F[X]OR(x, 0.0) -> x
18070 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18071 if (C->getValueAPF().isPosZero())
18072 return N->getOperand(1);
18073 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18074 if (C->getValueAPF().isPosZero())
18075 return N->getOperand(0);
18079 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18080 /// X86ISD::FMAX nodes.
18081 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18082 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18084 // Only perform optimizations if UnsafeMath is used.
18085 if (!DAG.getTarget().Options.UnsafeFPMath)
18088 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18089 // into FMINC and FMAXC, which are Commutative operations.
18090 unsigned NewOp = 0;
18091 switch (N->getOpcode()) {
18092 default: llvm_unreachable("unknown opcode");
18093 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18094 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18097 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18098 N->getOperand(0), N->getOperand(1));
18101 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18102 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18103 // FAND(0.0, x) -> 0.0
18104 // FAND(x, 0.0) -> 0.0
18105 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18106 if (C->getValueAPF().isPosZero())
18107 return N->getOperand(0);
18108 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18109 if (C->getValueAPF().isPosZero())
18110 return N->getOperand(1);
18114 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18115 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18116 // FANDN(x, 0.0) -> 0.0
18117 // FANDN(0.0, x) -> x
18118 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18119 if (C->getValueAPF().isPosZero())
18120 return N->getOperand(1);
18121 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18122 if (C->getValueAPF().isPosZero())
18123 return N->getOperand(1);
18127 static SDValue PerformBTCombine(SDNode *N,
18129 TargetLowering::DAGCombinerInfo &DCI) {
18130 // BT ignores high bits in the bit index operand.
18131 SDValue Op1 = N->getOperand(1);
18132 if (Op1.hasOneUse()) {
18133 unsigned BitWidth = Op1.getValueSizeInBits();
18134 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18135 APInt KnownZero, KnownOne;
18136 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18137 !DCI.isBeforeLegalizeOps());
18138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18139 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18140 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18141 DCI.CommitTargetLoweringOpt(TLO);
18146 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18147 SDValue Op = N->getOperand(0);
18148 if (Op.getOpcode() == ISD::BITCAST)
18149 Op = Op.getOperand(0);
18150 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18151 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18152 VT.getVectorElementType().getSizeInBits() ==
18153 OpVT.getVectorElementType().getSizeInBits()) {
18154 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18159 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18160 const X86Subtarget *Subtarget) {
18161 EVT VT = N->getValueType(0);
18162 if (!VT.isVector())
18165 SDValue N0 = N->getOperand(0);
18166 SDValue N1 = N->getOperand(1);
18167 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18170 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18171 // both SSE and AVX2 since there is no sign-extended shift right
18172 // operation on a vector with 64-bit elements.
18173 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18174 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18175 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18176 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18177 SDValue N00 = N0.getOperand(0);
18179 // EXTLOAD has a better solution on AVX2,
18180 // it may be replaced with X86ISD::VSEXT node.
18181 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18182 if (!ISD::isNormalLoad(N00.getNode()))
18185 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18186 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18188 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18194 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18195 TargetLowering::DAGCombinerInfo &DCI,
18196 const X86Subtarget *Subtarget) {
18197 if (!DCI.isBeforeLegalizeOps())
18200 if (!Subtarget->hasFp256())
18203 EVT VT = N->getValueType(0);
18204 if (VT.isVector() && VT.getSizeInBits() == 256) {
18205 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18213 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18214 const X86Subtarget* Subtarget) {
18216 EVT VT = N->getValueType(0);
18218 // Let legalize expand this if it isn't a legal type yet.
18219 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18222 EVT ScalarVT = VT.getScalarType();
18223 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18224 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18227 SDValue A = N->getOperand(0);
18228 SDValue B = N->getOperand(1);
18229 SDValue C = N->getOperand(2);
18231 bool NegA = (A.getOpcode() == ISD::FNEG);
18232 bool NegB = (B.getOpcode() == ISD::FNEG);
18233 bool NegC = (C.getOpcode() == ISD::FNEG);
18235 // Negative multiplication when NegA xor NegB
18236 bool NegMul = (NegA != NegB);
18238 A = A.getOperand(0);
18240 B = B.getOperand(0);
18242 C = C.getOperand(0);
18246 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18248 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18250 return DAG.getNode(Opcode, dl, VT, A, B, C);
18253 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18254 TargetLowering::DAGCombinerInfo &DCI,
18255 const X86Subtarget *Subtarget) {
18256 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18257 // (and (i32 x86isd::setcc_carry), 1)
18258 // This eliminates the zext. This transformation is necessary because
18259 // ISD::SETCC is always legalized to i8.
18261 SDValue N0 = N->getOperand(0);
18262 EVT VT = N->getValueType(0);
18264 if (N0.getOpcode() == ISD::AND &&
18266 N0.getOperand(0).hasOneUse()) {
18267 SDValue N00 = N0.getOperand(0);
18268 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18269 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18270 if (!C || C->getZExtValue() != 1)
18272 return DAG.getNode(ISD::AND, dl, VT,
18273 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18274 N00.getOperand(0), N00.getOperand(1)),
18275 DAG.getConstant(1, VT));
18279 if (VT.is256BitVector()) {
18280 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18288 // Optimize x == -y --> x+y == 0
18289 // x != -y --> x+y != 0
18290 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18291 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18292 SDValue LHS = N->getOperand(0);
18293 SDValue RHS = N->getOperand(1);
18295 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18296 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18297 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18298 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18299 LHS.getValueType(), RHS, LHS.getOperand(1));
18300 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18301 addV, DAG.getConstant(0, addV.getValueType()), CC);
18303 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18304 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18305 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18306 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18307 RHS.getValueType(), LHS, RHS.getOperand(1));
18308 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18309 addV, DAG.getConstant(0, addV.getValueType()), CC);
18314 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18315 // as "sbb reg,reg", since it can be extended without zext and produces
18316 // an all-ones bit which is more useful than 0/1 in some cases.
18317 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18318 return DAG.getNode(ISD::AND, DL, MVT::i8,
18319 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18320 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18321 DAG.getConstant(1, MVT::i8));
18324 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18325 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18326 TargetLowering::DAGCombinerInfo &DCI,
18327 const X86Subtarget *Subtarget) {
18329 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18330 SDValue EFLAGS = N->getOperand(1);
18332 if (CC == X86::COND_A) {
18333 // Try to convert COND_A into COND_B in an attempt to facilitate
18334 // materializing "setb reg".
18336 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18337 // cannot take an immediate as its first operand.
18339 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18340 EFLAGS.getValueType().isInteger() &&
18341 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18342 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18343 EFLAGS.getNode()->getVTList(),
18344 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18345 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18346 return MaterializeSETB(DL, NewEFLAGS, DAG);
18350 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18351 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18353 if (CC == X86::COND_B)
18354 return MaterializeSETB(DL, EFLAGS, DAG);
18358 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18359 if (Flags.getNode()) {
18360 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18361 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18367 // Optimize branch condition evaluation.
18369 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18370 TargetLowering::DAGCombinerInfo &DCI,
18371 const X86Subtarget *Subtarget) {
18373 SDValue Chain = N->getOperand(0);
18374 SDValue Dest = N->getOperand(1);
18375 SDValue EFLAGS = N->getOperand(3);
18376 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18380 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18381 if (Flags.getNode()) {
18382 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18383 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18390 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18391 const X86TargetLowering *XTLI) {
18392 SDValue Op0 = N->getOperand(0);
18393 EVT InVT = Op0->getValueType(0);
18395 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18396 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18398 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18399 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18400 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18403 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18404 // a 32-bit target where SSE doesn't support i64->FP operations.
18405 if (Op0.getOpcode() == ISD::LOAD) {
18406 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18407 EVT VT = Ld->getValueType(0);
18408 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18409 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18410 !XTLI->getSubtarget()->is64Bit() &&
18411 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18412 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18413 Ld->getChain(), Op0, DAG);
18414 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18421 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18422 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18423 X86TargetLowering::DAGCombinerInfo &DCI) {
18424 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18425 // the result is either zero or one (depending on the input carry bit).
18426 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18427 if (X86::isZeroNode(N->getOperand(0)) &&
18428 X86::isZeroNode(N->getOperand(1)) &&
18429 // We don't have a good way to replace an EFLAGS use, so only do this when
18431 SDValue(N, 1).use_empty()) {
18433 EVT VT = N->getValueType(0);
18434 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18435 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18436 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18437 DAG.getConstant(X86::COND_B,MVT::i8),
18439 DAG.getConstant(1, VT));
18440 return DCI.CombineTo(N, Res1, CarryOut);
18446 // fold (add Y, (sete X, 0)) -> adc 0, Y
18447 // (add Y, (setne X, 0)) -> sbb -1, Y
18448 // (sub (sete X, 0), Y) -> sbb 0, Y
18449 // (sub (setne X, 0), Y) -> adc -1, Y
18450 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18453 // Look through ZExts.
18454 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18455 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18458 SDValue SetCC = Ext.getOperand(0);
18459 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18462 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18463 if (CC != X86::COND_E && CC != X86::COND_NE)
18466 SDValue Cmp = SetCC.getOperand(1);
18467 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18468 !X86::isZeroNode(Cmp.getOperand(1)) ||
18469 !Cmp.getOperand(0).getValueType().isInteger())
18472 SDValue CmpOp0 = Cmp.getOperand(0);
18473 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18474 DAG.getConstant(1, CmpOp0.getValueType()));
18476 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18477 if (CC == X86::COND_NE)
18478 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18479 DL, OtherVal.getValueType(), OtherVal,
18480 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18481 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18482 DL, OtherVal.getValueType(), OtherVal,
18483 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18486 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18487 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18488 const X86Subtarget *Subtarget) {
18489 EVT VT = N->getValueType(0);
18490 SDValue Op0 = N->getOperand(0);
18491 SDValue Op1 = N->getOperand(1);
18493 // Try to synthesize horizontal adds from adds of shuffles.
18494 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18495 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18496 isHorizontalBinOp(Op0, Op1, true))
18497 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18499 return OptimizeConditionalInDecrement(N, DAG);
18502 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18503 const X86Subtarget *Subtarget) {
18504 SDValue Op0 = N->getOperand(0);
18505 SDValue Op1 = N->getOperand(1);
18507 // X86 can't encode an immediate LHS of a sub. See if we can push the
18508 // negation into a preceding instruction.
18509 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18510 // If the RHS of the sub is a XOR with one use and a constant, invert the
18511 // immediate. Then add one to the LHS of the sub so we can turn
18512 // X-Y -> X+~Y+1, saving one register.
18513 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18514 isa<ConstantSDNode>(Op1.getOperand(1))) {
18515 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18516 EVT VT = Op0.getValueType();
18517 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18519 DAG.getConstant(~XorC, VT));
18520 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18521 DAG.getConstant(C->getAPIntValue()+1, VT));
18525 // Try to synthesize horizontal adds from adds of shuffles.
18526 EVT VT = N->getValueType(0);
18527 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18528 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18529 isHorizontalBinOp(Op0, Op1, true))
18530 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
18532 return OptimizeConditionalInDecrement(N, DAG);
18535 /// performVZEXTCombine - Performs build vector combines
18536 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
18537 TargetLowering::DAGCombinerInfo &DCI,
18538 const X86Subtarget *Subtarget) {
18539 // (vzext (bitcast (vzext (x)) -> (vzext x)
18540 SDValue In = N->getOperand(0);
18541 while (In.getOpcode() == ISD::BITCAST)
18542 In = In.getOperand(0);
18544 if (In.getOpcode() != X86ISD::VZEXT)
18547 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
18551 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
18552 DAGCombinerInfo &DCI) const {
18553 SelectionDAG &DAG = DCI.DAG;
18554 switch (N->getOpcode()) {
18556 case ISD::EXTRACT_VECTOR_ELT:
18557 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
18559 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
18560 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
18561 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
18562 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
18563 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
18564 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
18567 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
18568 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
18569 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
18570 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
18571 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
18572 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
18573 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
18574 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
18575 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
18577 case X86ISD::FOR: return PerformFORCombine(N, DAG);
18579 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
18580 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
18581 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
18582 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
18583 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
18584 case ISD::ANY_EXTEND:
18585 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
18586 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
18587 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
18588 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
18589 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
18590 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
18591 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
18592 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
18593 case X86ISD::SHUFP: // Handle all target specific shuffles
18594 case X86ISD::PALIGNR:
18595 case X86ISD::UNPCKH:
18596 case X86ISD::UNPCKL:
18597 case X86ISD::MOVHLPS:
18598 case X86ISD::MOVLHPS:
18599 case X86ISD::PSHUFD:
18600 case X86ISD::PSHUFHW:
18601 case X86ISD::PSHUFLW:
18602 case X86ISD::MOVSS:
18603 case X86ISD::MOVSD:
18604 case X86ISD::VPERMILP:
18605 case X86ISD::VPERM2X128:
18606 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
18607 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
18613 /// isTypeDesirableForOp - Return true if the target has native support for
18614 /// the specified value type and it is 'desirable' to use the type for the
18615 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
18616 /// instruction encodings are longer and some i16 instructions are slow.
18617 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
18618 if (!isTypeLegal(VT))
18620 if (VT != MVT::i16)
18627 case ISD::SIGN_EXTEND:
18628 case ISD::ZERO_EXTEND:
18629 case ISD::ANY_EXTEND:
18642 /// IsDesirableToPromoteOp - This method query the target whether it is
18643 /// beneficial for dag combiner to promote the specified node. If true, it
18644 /// should return the desired promotion type by reference.
18645 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
18646 EVT VT = Op.getValueType();
18647 if (VT != MVT::i16)
18650 bool Promote = false;
18651 bool Commute = false;
18652 switch (Op.getOpcode()) {
18655 LoadSDNode *LD = cast<LoadSDNode>(Op);
18656 // If the non-extending load has a single use and it's not live out, then it
18657 // might be folded.
18658 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
18659 Op.hasOneUse()*/) {
18660 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
18661 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
18662 // The only case where we'd want to promote LOAD (rather then it being
18663 // promoted as an operand is when it's only use is liveout.
18664 if (UI->getOpcode() != ISD::CopyToReg)
18671 case ISD::SIGN_EXTEND:
18672 case ISD::ZERO_EXTEND:
18673 case ISD::ANY_EXTEND:
18678 SDValue N0 = Op.getOperand(0);
18679 // Look out for (store (shl (load), x)).
18680 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
18693 SDValue N0 = Op.getOperand(0);
18694 SDValue N1 = Op.getOperand(1);
18695 if (!Commute && MayFoldLoad(N1))
18697 // Avoid disabling potential load folding opportunities.
18698 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
18700 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
18710 //===----------------------------------------------------------------------===//
18711 // X86 Inline Assembly Support
18712 //===----------------------------------------------------------------------===//
18715 // Helper to match a string separated by whitespace.
18716 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
18717 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
18719 for (unsigned i = 0, e = args.size(); i != e; ++i) {
18720 StringRef piece(*args[i]);
18721 if (!s.startswith(piece)) // Check if the piece matches.
18724 s = s.substr(piece.size());
18725 StringRef::size_type pos = s.find_first_not_of(" \t");
18726 if (pos == 0) // We matched a prefix.
18734 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
18737 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
18738 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
18740 std::string AsmStr = IA->getAsmString();
18742 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
18743 if (!Ty || Ty->getBitWidth() % 16 != 0)
18746 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
18747 SmallVector<StringRef, 4> AsmPieces;
18748 SplitString(AsmStr, AsmPieces, ";\n");
18750 switch (AsmPieces.size()) {
18751 default: return false;
18753 // FIXME: this should verify that we are targeting a 486 or better. If not,
18754 // we will turn this bswap into something that will be lowered to logical
18755 // ops instead of emitting the bswap asm. For now, we don't support 486 or
18756 // lower so don't worry about this.
18758 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
18759 matchAsm(AsmPieces[0], "bswapl", "$0") ||
18760 matchAsm(AsmPieces[0], "bswapq", "$0") ||
18761 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
18762 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
18763 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
18764 // No need to check constraints, nothing other than the equivalent of
18765 // "=r,0" would be valid here.
18766 return IntrinsicLowering::LowerToByteSwap(CI);
18769 // rorw $$8, ${0:w} --> llvm.bswap.i16
18770 if (CI->getType()->isIntegerTy(16) &&
18771 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18772 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
18773 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
18775 const std::string &ConstraintsStr = IA->getConstraintString();
18776 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18777 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18778 if (AsmPieces.size() == 4 &&
18779 AsmPieces[0] == "~{cc}" &&
18780 AsmPieces[1] == "~{dirflag}" &&
18781 AsmPieces[2] == "~{flags}" &&
18782 AsmPieces[3] == "~{fpsr}")
18783 return IntrinsicLowering::LowerToByteSwap(CI);
18787 if (CI->getType()->isIntegerTy(32) &&
18788 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18789 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
18790 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
18791 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
18793 const std::string &ConstraintsStr = IA->getConstraintString();
18794 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18795 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18796 if (AsmPieces.size() == 4 &&
18797 AsmPieces[0] == "~{cc}" &&
18798 AsmPieces[1] == "~{dirflag}" &&
18799 AsmPieces[2] == "~{flags}" &&
18800 AsmPieces[3] == "~{fpsr}")
18801 return IntrinsicLowering::LowerToByteSwap(CI);
18804 if (CI->getType()->isIntegerTy(64)) {
18805 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
18806 if (Constraints.size() >= 2 &&
18807 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
18808 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
18809 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
18810 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
18811 matchAsm(AsmPieces[1], "bswap", "%edx") &&
18812 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
18813 return IntrinsicLowering::LowerToByteSwap(CI);
18821 /// getConstraintType - Given a constraint letter, return the type of
18822 /// constraint it is for this target.
18823 X86TargetLowering::ConstraintType
18824 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
18825 if (Constraint.size() == 1) {
18826 switch (Constraint[0]) {
18837 return C_RegisterClass;
18861 return TargetLowering::getConstraintType(Constraint);
18864 /// Examine constraint type and operand type and determine a weight value.
18865 /// This object must already have been set up with the operand type
18866 /// and the current alternative constraint selected.
18867 TargetLowering::ConstraintWeight
18868 X86TargetLowering::getSingleConstraintMatchWeight(
18869 AsmOperandInfo &info, const char *constraint) const {
18870 ConstraintWeight weight = CW_Invalid;
18871 Value *CallOperandVal = info.CallOperandVal;
18872 // If we don't have a value, we can't do a match,
18873 // but allow it at the lowest weight.
18874 if (CallOperandVal == NULL)
18876 Type *type = CallOperandVal->getType();
18877 // Look at the constraint type.
18878 switch (*constraint) {
18880 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
18891 if (CallOperandVal->getType()->isIntegerTy())
18892 weight = CW_SpecificReg;
18897 if (type->isFloatingPointTy())
18898 weight = CW_SpecificReg;
18901 if (type->isX86_MMXTy() && Subtarget->hasMMX())
18902 weight = CW_SpecificReg;
18906 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
18907 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
18908 weight = CW_Register;
18911 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
18912 if (C->getZExtValue() <= 31)
18913 weight = CW_Constant;
18917 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18918 if (C->getZExtValue() <= 63)
18919 weight = CW_Constant;
18923 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18924 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
18925 weight = CW_Constant;
18929 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18930 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
18931 weight = CW_Constant;
18935 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18936 if (C->getZExtValue() <= 3)
18937 weight = CW_Constant;
18941 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18942 if (C->getZExtValue() <= 0xff)
18943 weight = CW_Constant;
18948 if (dyn_cast<ConstantFP>(CallOperandVal)) {
18949 weight = CW_Constant;
18953 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18954 if ((C->getSExtValue() >= -0x80000000LL) &&
18955 (C->getSExtValue() <= 0x7fffffffLL))
18956 weight = CW_Constant;
18960 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18961 if (C->getZExtValue() <= 0xffffffff)
18962 weight = CW_Constant;
18969 /// LowerXConstraint - try to replace an X constraint, which matches anything,
18970 /// with another that has more specific requirements based on the type of the
18971 /// corresponding operand.
18972 const char *X86TargetLowering::
18973 LowerXConstraint(EVT ConstraintVT) const {
18974 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
18975 // 'f' like normal targets.
18976 if (ConstraintVT.isFloatingPoint()) {
18977 if (Subtarget->hasSSE2())
18979 if (Subtarget->hasSSE1())
18983 return TargetLowering::LowerXConstraint(ConstraintVT);
18986 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
18987 /// vector. If it is invalid, don't add anything to Ops.
18988 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
18989 std::string &Constraint,
18990 std::vector<SDValue>&Ops,
18991 SelectionDAG &DAG) const {
18992 SDValue Result(0, 0);
18994 // Only support length 1 constraints for now.
18995 if (Constraint.length() > 1) return;
18997 char ConstraintLetter = Constraint[0];
18998 switch (ConstraintLetter) {
19001 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19002 if (C->getZExtValue() <= 31) {
19003 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19010 if (C->getZExtValue() <= 63) {
19011 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19018 if (isInt<8>(C->getSExtValue())) {
19019 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19026 if (C->getZExtValue() <= 255) {
19027 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19033 // 32-bit signed value
19034 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19035 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19036 C->getSExtValue())) {
19037 // Widen to 64 bits here to get it sign extended.
19038 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19041 // FIXME gcc accepts some relocatable values here too, but only in certain
19042 // memory models; it's complicated.
19047 // 32-bit unsigned value
19048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19049 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19050 C->getZExtValue())) {
19051 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19055 // FIXME gcc accepts some relocatable values here too, but only in certain
19056 // memory models; it's complicated.
19060 // Literal immediates are always ok.
19061 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19062 // Widen to 64 bits here to get it sign extended.
19063 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19067 // In any sort of PIC mode addresses need to be computed at runtime by
19068 // adding in a register or some sort of table lookup. These can't
19069 // be used as immediates.
19070 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19073 // If we are in non-pic codegen mode, we allow the address of a global (with
19074 // an optional displacement) to be used with 'i'.
19075 GlobalAddressSDNode *GA = 0;
19076 int64_t Offset = 0;
19078 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19080 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19081 Offset += GA->getOffset();
19083 } else if (Op.getOpcode() == ISD::ADD) {
19084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19085 Offset += C->getZExtValue();
19086 Op = Op.getOperand(0);
19089 } else if (Op.getOpcode() == ISD::SUB) {
19090 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19091 Offset += -C->getZExtValue();
19092 Op = Op.getOperand(0);
19097 // Otherwise, this isn't something we can handle, reject it.
19101 const GlobalValue *GV = GA->getGlobal();
19102 // If we require an extra load to get this address, as in PIC mode, we
19103 // can't accept it.
19104 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19105 getTargetMachine())))
19108 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19109 GA->getValueType(0), Offset);
19114 if (Result.getNode()) {
19115 Ops.push_back(Result);
19118 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19121 std::pair<unsigned, const TargetRegisterClass*>
19122 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19124 // First, see if this is a constraint that directly corresponds to an LLVM
19126 if (Constraint.size() == 1) {
19127 // GCC Constraint Letters
19128 switch (Constraint[0]) {
19130 // TODO: Slight differences here in allocation order and leaving
19131 // RIP in the class. Do they matter any more here than they do
19132 // in the normal allocation?
19133 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19134 if (Subtarget->is64Bit()) {
19135 if (VT == MVT::i32 || VT == MVT::f32)
19136 return std::make_pair(0U, &X86::GR32RegClass);
19137 if (VT == MVT::i16)
19138 return std::make_pair(0U, &X86::GR16RegClass);
19139 if (VT == MVT::i8 || VT == MVT::i1)
19140 return std::make_pair(0U, &X86::GR8RegClass);
19141 if (VT == MVT::i64 || VT == MVT::f64)
19142 return std::make_pair(0U, &X86::GR64RegClass);
19145 // 32-bit fallthrough
19146 case 'Q': // Q_REGS
19147 if (VT == MVT::i32 || VT == MVT::f32)
19148 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19149 if (VT == MVT::i16)
19150 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19151 if (VT == MVT::i8 || VT == MVT::i1)
19152 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19153 if (VT == MVT::i64)
19154 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19156 case 'r': // GENERAL_REGS
19157 case 'l': // INDEX_REGS
19158 if (VT == MVT::i8 || VT == MVT::i1)
19159 return std::make_pair(0U, &X86::GR8RegClass);
19160 if (VT == MVT::i16)
19161 return std::make_pair(0U, &X86::GR16RegClass);
19162 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19163 return std::make_pair(0U, &X86::GR32RegClass);
19164 return std::make_pair(0U, &X86::GR64RegClass);
19165 case 'R': // LEGACY_REGS
19166 if (VT == MVT::i8 || VT == MVT::i1)
19167 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19168 if (VT == MVT::i16)
19169 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19170 if (VT == MVT::i32 || !Subtarget->is64Bit())
19171 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19172 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19173 case 'f': // FP Stack registers.
19174 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19175 // value to the correct fpstack register class.
19176 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19177 return std::make_pair(0U, &X86::RFP32RegClass);
19178 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19179 return std::make_pair(0U, &X86::RFP64RegClass);
19180 return std::make_pair(0U, &X86::RFP80RegClass);
19181 case 'y': // MMX_REGS if MMX allowed.
19182 if (!Subtarget->hasMMX()) break;
19183 return std::make_pair(0U, &X86::VR64RegClass);
19184 case 'Y': // SSE_REGS if SSE2 allowed
19185 if (!Subtarget->hasSSE2()) break;
19187 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19188 if (!Subtarget->hasSSE1()) break;
19190 switch (VT.SimpleTy) {
19192 // Scalar SSE types.
19195 return std::make_pair(0U, &X86::FR32RegClass);
19198 return std::make_pair(0U, &X86::FR64RegClass);
19206 return std::make_pair(0U, &X86::VR128RegClass);
19214 return std::make_pair(0U, &X86::VR256RegClass);
19219 return std::make_pair(0U, &X86::VR512RegClass);
19225 // Use the default implementation in TargetLowering to convert the register
19226 // constraint into a member of a register class.
19227 std::pair<unsigned, const TargetRegisterClass*> Res;
19228 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19230 // Not found as a standard register?
19231 if (Res.second == 0) {
19232 // Map st(0) -> st(7) -> ST0
19233 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19234 tolower(Constraint[1]) == 's' &&
19235 tolower(Constraint[2]) == 't' &&
19236 Constraint[3] == '(' &&
19237 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19238 Constraint[5] == ')' &&
19239 Constraint[6] == '}') {
19241 Res.first = X86::ST0+Constraint[4]-'0';
19242 Res.second = &X86::RFP80RegClass;
19246 // GCC allows "st(0)" to be called just plain "st".
19247 if (StringRef("{st}").equals_lower(Constraint)) {
19248 Res.first = X86::ST0;
19249 Res.second = &X86::RFP80RegClass;
19254 if (StringRef("{flags}").equals_lower(Constraint)) {
19255 Res.first = X86::EFLAGS;
19256 Res.second = &X86::CCRRegClass;
19260 // 'A' means EAX + EDX.
19261 if (Constraint == "A") {
19262 Res.first = X86::EAX;
19263 Res.second = &X86::GR32_ADRegClass;
19269 // Otherwise, check to see if this is a register class of the wrong value
19270 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19271 // turn into {ax},{dx}.
19272 if (Res.second->hasType(VT))
19273 return Res; // Correct type already, nothing to do.
19275 // All of the single-register GCC register classes map their values onto
19276 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19277 // really want an 8-bit or 32-bit register, map to the appropriate register
19278 // class and return the appropriate register.
19279 if (Res.second == &X86::GR16RegClass) {
19280 if (VT == MVT::i8 || VT == MVT::i1) {
19281 unsigned DestReg = 0;
19282 switch (Res.first) {
19284 case X86::AX: DestReg = X86::AL; break;
19285 case X86::DX: DestReg = X86::DL; break;
19286 case X86::CX: DestReg = X86::CL; break;
19287 case X86::BX: DestReg = X86::BL; break;
19290 Res.first = DestReg;
19291 Res.second = &X86::GR8RegClass;
19293 } else if (VT == MVT::i32 || VT == MVT::f32) {
19294 unsigned DestReg = 0;
19295 switch (Res.first) {
19297 case X86::AX: DestReg = X86::EAX; break;
19298 case X86::DX: DestReg = X86::EDX; break;
19299 case X86::CX: DestReg = X86::ECX; break;
19300 case X86::BX: DestReg = X86::EBX; break;
19301 case X86::SI: DestReg = X86::ESI; break;
19302 case X86::DI: DestReg = X86::EDI; break;
19303 case X86::BP: DestReg = X86::EBP; break;
19304 case X86::SP: DestReg = X86::ESP; break;
19307 Res.first = DestReg;
19308 Res.second = &X86::GR32RegClass;
19310 } else if (VT == MVT::i64 || VT == MVT::f64) {
19311 unsigned DestReg = 0;
19312 switch (Res.first) {
19314 case X86::AX: DestReg = X86::RAX; break;
19315 case X86::DX: DestReg = X86::RDX; break;
19316 case X86::CX: DestReg = X86::RCX; break;
19317 case X86::BX: DestReg = X86::RBX; break;
19318 case X86::SI: DestReg = X86::RSI; break;
19319 case X86::DI: DestReg = X86::RDI; break;
19320 case X86::BP: DestReg = X86::RBP; break;
19321 case X86::SP: DestReg = X86::RSP; break;
19324 Res.first = DestReg;
19325 Res.second = &X86::GR64RegClass;
19328 } else if (Res.second == &X86::FR32RegClass ||
19329 Res.second == &X86::FR64RegClass ||
19330 Res.second == &X86::VR128RegClass ||
19331 Res.second == &X86::VR256RegClass ||
19332 Res.second == &X86::FR32XRegClass ||
19333 Res.second == &X86::FR64XRegClass ||
19334 Res.second == &X86::VR128XRegClass ||
19335 Res.second == &X86::VR256XRegClass ||
19336 Res.second == &X86::VR512RegClass) {
19337 // Handle references to XMM physical registers that got mapped into the
19338 // wrong class. This can happen with constraints like {xmm0} where the
19339 // target independent register mapper will just pick the first match it can
19340 // find, ignoring the required type.
19342 if (VT == MVT::f32 || VT == MVT::i32)
19343 Res.second = &X86::FR32RegClass;
19344 else if (VT == MVT::f64 || VT == MVT::i64)
19345 Res.second = &X86::FR64RegClass;
19346 else if (X86::VR128RegClass.hasType(VT))
19347 Res.second = &X86::VR128RegClass;
19348 else if (X86::VR256RegClass.hasType(VT))
19349 Res.second = &X86::VR256RegClass;
19350 else if (X86::VR512RegClass.hasType(VT))
19351 Res.second = &X86::VR512RegClass;