1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1518 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1520 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1521 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1524 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1535 if (Subtarget->hasDQI()) {
1536 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1537 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1538 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1540 // Custom lower several nodes.
1541 for (MVT VT : MVT::vector_valuetypes()) {
1542 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 setOperationAction(ISD::AND, VT, Legal);
1545 setOperationAction(ISD::OR, VT, Legal);
1546 setOperationAction(ISD::XOR, VT, Legal);
1548 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1549 setOperationAction(ISD::MGATHER, VT, Custom);
1550 setOperationAction(ISD::MSCATTER, VT, Custom);
1552 // Extract subvector is special because the value type
1553 // (result) is 256/128-bit but the source is 512-bit wide.
1554 if (VT.is128BitVector() || VT.is256BitVector()) {
1555 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1557 if (VT.getVectorElementType() == MVT::i1)
1558 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1560 // Do not attempt to custom lower other non-512-bit vectors
1561 if (!VT.is512BitVector())
1564 if (EltSize >= 32) {
1565 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1566 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1567 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1568 setOperationAction(ISD::VSELECT, VT, Legal);
1569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1570 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1572 setOperationAction(ISD::MLOAD, VT, Legal);
1573 setOperationAction(ISD::MSTORE, VT, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 MVT VT = (MVT::SimpleValueType)i;
1579 // Do not attempt to promote non-512-bit vectors.
1580 if (!VT.is512BitVector())
1583 setOperationAction(ISD::SELECT, VT, Promote);
1584 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1588 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1589 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1592 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1593 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1595 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1596 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1597 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1598 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1599 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1602 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1603 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1604 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1605 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1606 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1607 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1608 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1609 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1610 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1611 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1612 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1613 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1614 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1615 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1616 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1617 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1618 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1619 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1620 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1621 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1622 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1623 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1624 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1625 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1626 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1629 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1630 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1631 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1632 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1633 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1634 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1635 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1636 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1638 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1639 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1640 if (Subtarget->hasVLX())
1641 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1643 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1644 const MVT VT = (MVT::SimpleValueType)i;
1646 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1648 // Do not attempt to promote non-512-bit vectors.
1649 if (!VT.is512BitVector())
1653 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1654 setOperationAction(ISD::VSELECT, VT, Legal);
1659 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1660 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1661 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1663 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1664 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1665 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1666 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1667 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1668 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1669 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1670 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1671 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1672 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1676 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1677 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1678 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1679 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1680 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1681 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1682 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1683 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1685 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1686 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1687 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1688 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1689 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1690 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1691 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1692 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1695 // We want to custom lower some of our intrinsics.
1696 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1697 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1698 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1699 if (!Subtarget->is64Bit())
1700 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1702 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1703 // handle type legalization for these operations here.
1705 // FIXME: We really should do custom legalization for addition and
1706 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1707 // than generic legalization for 64-bit multiplication-with-overflow, though.
1708 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1709 // Add/Sub/Mul with overflow operations are custom lowered.
1711 setOperationAction(ISD::SADDO, VT, Custom);
1712 setOperationAction(ISD::UADDO, VT, Custom);
1713 setOperationAction(ISD::SSUBO, VT, Custom);
1714 setOperationAction(ISD::USUBO, VT, Custom);
1715 setOperationAction(ISD::SMULO, VT, Custom);
1716 setOperationAction(ISD::UMULO, VT, Custom);
1719 if (!Subtarget->is64Bit()) {
1720 // These libcalls are not available in 32-bit.
1721 setLibcallName(RTLIB::SHL_I128, nullptr);
1722 setLibcallName(RTLIB::SRL_I128, nullptr);
1723 setLibcallName(RTLIB::SRA_I128, nullptr);
1726 // Combine sin / cos into one node or libcall if possible.
1727 if (Subtarget->hasSinCos()) {
1728 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1729 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1730 if (Subtarget->isTargetDarwin()) {
1731 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1732 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1733 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1734 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1738 if (Subtarget->isTargetWin64()) {
1739 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1740 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1741 setOperationAction(ISD::SREM, MVT::i128, Custom);
1742 setOperationAction(ISD::UREM, MVT::i128, Custom);
1743 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1744 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1747 // We have target-specific dag combine patterns for the following nodes:
1748 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1749 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1750 setTargetDAGCombine(ISD::BITCAST);
1751 setTargetDAGCombine(ISD::VSELECT);
1752 setTargetDAGCombine(ISD::SELECT);
1753 setTargetDAGCombine(ISD::SHL);
1754 setTargetDAGCombine(ISD::SRA);
1755 setTargetDAGCombine(ISD::SRL);
1756 setTargetDAGCombine(ISD::OR);
1757 setTargetDAGCombine(ISD::AND);
1758 setTargetDAGCombine(ISD::ADD);
1759 setTargetDAGCombine(ISD::FADD);
1760 setTargetDAGCombine(ISD::FSUB);
1761 setTargetDAGCombine(ISD::FMA);
1762 setTargetDAGCombine(ISD::SUB);
1763 setTargetDAGCombine(ISD::LOAD);
1764 setTargetDAGCombine(ISD::MLOAD);
1765 setTargetDAGCombine(ISD::STORE);
1766 setTargetDAGCombine(ISD::MSTORE);
1767 setTargetDAGCombine(ISD::ZERO_EXTEND);
1768 setTargetDAGCombine(ISD::ANY_EXTEND);
1769 setTargetDAGCombine(ISD::SIGN_EXTEND);
1770 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1771 setTargetDAGCombine(ISD::SINT_TO_FP);
1772 setTargetDAGCombine(ISD::UINT_TO_FP);
1773 setTargetDAGCombine(ISD::SETCC);
1774 setTargetDAGCombine(ISD::BUILD_VECTOR);
1775 setTargetDAGCombine(ISD::MUL);
1776 setTargetDAGCombine(ISD::XOR);
1778 computeRegisterProperties(Subtarget->getRegisterInfo());
1780 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1781 MaxStoresPerMemsetOptSize = 8;
1782 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1783 MaxStoresPerMemcpyOptSize = 4;
1784 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1785 MaxStoresPerMemmoveOptSize = 4;
1786 setPrefLoopAlignment(4); // 2^4 bytes.
1788 // Predictable cmov don't hurt on atom because it's in-order.
1789 PredictableSelectIsExpensive = !Subtarget->isAtom();
1790 EnableExtLdPromotion = true;
1791 setPrefFunctionAlignment(4); // 2^4 bytes.
1793 verifyIntrinsicTables();
1796 // This has so far only been implemented for 64-bit MachO.
1797 bool X86TargetLowering::useLoadStackGuardNode() const {
1798 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1801 TargetLoweringBase::LegalizeTypeAction
1802 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1803 if (ExperimentalVectorWideningLegalization &&
1804 VT.getVectorNumElements() != 1 &&
1805 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1806 return TypeWidenVector;
1808 return TargetLoweringBase::getPreferredVectorAction(VT);
1811 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1814 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1816 const unsigned NumElts = VT.getVectorNumElements();
1817 const EVT EltVT = VT.getVectorElementType();
1818 if (VT.is512BitVector()) {
1819 if (Subtarget->hasAVX512())
1820 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1821 EltVT == MVT::f32 || EltVT == MVT::f64)
1823 case 8: return MVT::v8i1;
1824 case 16: return MVT::v16i1;
1826 if (Subtarget->hasBWI())
1827 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1829 case 32: return MVT::v32i1;
1830 case 64: return MVT::v64i1;
1834 if (VT.is256BitVector() || VT.is128BitVector()) {
1835 if (Subtarget->hasVLX())
1836 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1837 EltVT == MVT::f32 || EltVT == MVT::f64)
1839 case 2: return MVT::v2i1;
1840 case 4: return MVT::v4i1;
1841 case 8: return MVT::v8i1;
1843 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1844 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1846 case 8: return MVT::v8i1;
1847 case 16: return MVT::v16i1;
1848 case 32: return MVT::v32i1;
1852 return VT.changeVectorElementTypeToInteger();
1855 /// Helper for getByValTypeAlignment to determine
1856 /// the desired ByVal argument alignment.
1857 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1860 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1861 if (VTy->getBitWidth() == 128)
1863 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1864 unsigned EltAlign = 0;
1865 getMaxByValAlign(ATy->getElementType(), EltAlign);
1866 if (EltAlign > MaxAlign)
1867 MaxAlign = EltAlign;
1868 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1869 for (auto *EltTy : STy->elements()) {
1870 unsigned EltAlign = 0;
1871 getMaxByValAlign(EltTy, EltAlign);
1872 if (EltAlign > MaxAlign)
1873 MaxAlign = EltAlign;
1880 /// Return the desired alignment for ByVal aggregate
1881 /// function arguments in the caller parameter area. For X86, aggregates
1882 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1883 /// are at 4-byte boundaries.
1884 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1885 const DataLayout &DL) const {
1886 if (Subtarget->is64Bit()) {
1887 // Max of 8 and alignment of type.
1888 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1895 if (Subtarget->hasSSE1())
1896 getMaxByValAlign(Ty, Align);
1900 /// Returns the target specific optimal type for load
1901 /// and store operations as a result of memset, memcpy, and memmove
1902 /// lowering. If DstAlign is zero that means it's safe to destination
1903 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1904 /// means there isn't a need to check it against alignment requirement,
1905 /// probably because the source does not need to be loaded. If 'IsMemset' is
1906 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1907 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1908 /// source is constant so it does not need to be loaded.
1909 /// It returns EVT::Other if the type should be determined using generic
1910 /// target-independent logic.
1912 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1913 unsigned DstAlign, unsigned SrcAlign,
1914 bool IsMemset, bool ZeroMemset,
1916 MachineFunction &MF) const {
1917 const Function *F = MF.getFunction();
1918 if ((!IsMemset || ZeroMemset) &&
1919 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1921 (!Subtarget->isUnalignedMem16Slow() ||
1922 ((DstAlign == 0 || DstAlign >= 16) &&
1923 (SrcAlign == 0 || SrcAlign >= 16)))) {
1925 // FIXME: Check if unaligned 32-byte accesses are slow.
1926 if (Subtarget->hasInt256())
1928 if (Subtarget->hasFp256())
1931 if (Subtarget->hasSSE2())
1933 if (Subtarget->hasSSE1())
1935 } else if (!MemcpyStrSrc && Size >= 8 &&
1936 !Subtarget->is64Bit() &&
1937 Subtarget->hasSSE2()) {
1938 // Do not use f64 to lower memcpy if source is string constant. It's
1939 // better to use i32 to avoid the loads.
1943 // This is a compromise. If we reach here, unaligned accesses may be slow on
1944 // this target. However, creating smaller, aligned accesses could be even
1945 // slower and would certainly be a lot more code.
1946 if (Subtarget->is64Bit() && Size >= 8)
1951 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1953 return X86ScalarSSEf32;
1954 else if (VT == MVT::f64)
1955 return X86ScalarSSEf64;
1960 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1965 switch (VT.getSizeInBits()) {
1967 // 8-byte and under are always assumed to be fast.
1971 *Fast = !Subtarget->isUnalignedMem16Slow();
1974 *Fast = !Subtarget->isUnalignedMem32Slow();
1976 // TODO: What about AVX-512 (512-bit) accesses?
1979 // Misaligned accesses of any size are always allowed.
1983 /// Return the entry encoding for a jump table in the
1984 /// current function. The returned value is a member of the
1985 /// MachineJumpTableInfo::JTEntryKind enum.
1986 unsigned X86TargetLowering::getJumpTableEncoding() const {
1987 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1989 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1990 Subtarget->isPICStyleGOT())
1991 return MachineJumpTableInfo::EK_Custom32;
1993 // Otherwise, use the normal jump table encoding heuristics.
1994 return TargetLowering::getJumpTableEncoding();
1997 bool X86TargetLowering::useSoftFloat() const {
1998 return Subtarget->useSoftFloat();
2002 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2003 const MachineBasicBlock *MBB,
2004 unsigned uid,MCContext &Ctx) const{
2005 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2006 Subtarget->isPICStyleGOT());
2007 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2009 return MCSymbolRefExpr::create(MBB->getSymbol(),
2010 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2013 /// Returns relocation base for the given PIC jumptable.
2014 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2015 SelectionDAG &DAG) const {
2016 if (!Subtarget->is64Bit())
2017 // This doesn't have SDLoc associated with it, but is not really the
2018 // same as a Register.
2019 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2020 getPointerTy(DAG.getDataLayout()));
2024 /// This returns the relocation base for the given PIC jumptable,
2025 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2026 const MCExpr *X86TargetLowering::
2027 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2028 MCContext &Ctx) const {
2029 // X86-64 uses RIP relative addressing based on the jump table label.
2030 if (Subtarget->isPICStyleRIPRel())
2031 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2033 // Otherwise, the reference is relative to the PIC base.
2034 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2037 std::pair<const TargetRegisterClass *, uint8_t>
2038 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2040 const TargetRegisterClass *RRC = nullptr;
2042 switch (VT.SimpleTy) {
2044 return TargetLowering::findRepresentativeClass(TRI, VT);
2045 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2046 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2049 RRC = &X86::VR64RegClass;
2051 case MVT::f32: case MVT::f64:
2052 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2053 case MVT::v4f32: case MVT::v2f64:
2054 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2056 RRC = &X86::VR128RegClass;
2059 return std::make_pair(RRC, Cost);
2062 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2063 unsigned &Offset) const {
2064 if (!Subtarget->isTargetLinux())
2067 if (Subtarget->is64Bit()) {
2068 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2070 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2082 /// Android provides a fixed TLS slot for the SafeStack pointer.
2083 /// See the definition of TLS_SLOT_SAFESTACK in
2084 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2085 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2086 unsigned &Offset) const {
2087 if (!Subtarget->isTargetAndroid())
2090 if (Subtarget->is64Bit()) {
2091 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2093 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2105 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2106 unsigned DestAS) const {
2107 assert(SrcAS != DestAS && "Expected different address spaces!");
2109 return SrcAS < 256 && DestAS < 256;
2112 //===----------------------------------------------------------------------===//
2113 // Return Value Calling Convention Implementation
2114 //===----------------------------------------------------------------------===//
2116 #include "X86GenCallingConv.inc"
2118 bool X86TargetLowering::CanLowerReturn(
2119 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2120 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2121 SmallVector<CCValAssign, 16> RVLocs;
2122 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2123 return CCInfo.CheckReturn(Outs, RetCC_X86);
2126 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2127 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2132 X86TargetLowering::LowerReturn(SDValue Chain,
2133 CallingConv::ID CallConv, bool isVarArg,
2134 const SmallVectorImpl<ISD::OutputArg> &Outs,
2135 const SmallVectorImpl<SDValue> &OutVals,
2136 SDLoc dl, SelectionDAG &DAG) const {
2137 MachineFunction &MF = DAG.getMachineFunction();
2138 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2140 SmallVector<CCValAssign, 16> RVLocs;
2141 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2142 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2145 SmallVector<SDValue, 6> RetOps;
2146 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2147 // Operand #1 = Bytes To Pop
2148 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2151 // Copy the result values into the output registers.
2152 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2153 CCValAssign &VA = RVLocs[i];
2154 assert(VA.isRegLoc() && "Can only return in registers!");
2155 SDValue ValToCopy = OutVals[i];
2156 EVT ValVT = ValToCopy.getValueType();
2158 // Promote values to the appropriate types.
2159 if (VA.getLocInfo() == CCValAssign::SExt)
2160 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2161 else if (VA.getLocInfo() == CCValAssign::ZExt)
2162 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2163 else if (VA.getLocInfo() == CCValAssign::AExt) {
2164 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2165 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2167 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2169 else if (VA.getLocInfo() == CCValAssign::BCvt)
2170 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2172 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2173 "Unexpected FP-extend for return value.");
2175 // If this is x86-64, and we disabled SSE, we can't return FP values,
2176 // or SSE or MMX vectors.
2177 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2178 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2179 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2180 report_fatal_error("SSE register return with SSE disabled");
2182 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2183 // llvm-gcc has never done it right and no one has noticed, so this
2184 // should be OK for now.
2185 if (ValVT == MVT::f64 &&
2186 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2187 report_fatal_error("SSE2 register return with SSE2 disabled");
2189 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2190 // the RET instruction and handled by the FP Stackifier.
2191 if (VA.getLocReg() == X86::FP0 ||
2192 VA.getLocReg() == X86::FP1) {
2193 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2194 // change the value to the FP stack register class.
2195 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2196 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2197 RetOps.push_back(ValToCopy);
2198 // Don't emit a copytoreg.
2202 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2203 // which is returned in RAX / RDX.
2204 if (Subtarget->is64Bit()) {
2205 if (ValVT == MVT::x86mmx) {
2206 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2207 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2208 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2210 // If we don't have SSE2 available, convert to v4f32 so the generated
2211 // register is legal.
2212 if (!Subtarget->hasSSE2())
2213 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2218 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2219 Flag = Chain.getValue(1);
2220 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2223 // All x86 ABIs require that for returning structs by value we copy
2224 // the sret argument into %rax/%eax (depending on ABI) for the return.
2225 // We saved the argument into a virtual register in the entry block,
2226 // so now we copy the value out and into %rax/%eax.
2228 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2229 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2230 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2231 // either case FuncInfo->setSRetReturnReg() will have been called.
2232 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2233 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2234 getPointerTy(MF.getDataLayout()));
2237 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2238 X86::RAX : X86::EAX;
2239 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2240 Flag = Chain.getValue(1);
2242 // RAX/EAX now acts like a return value.
2244 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2247 RetOps[0] = Chain; // Update chain.
2249 // Add the flag if we have it.
2251 RetOps.push_back(Flag);
2253 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2256 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2257 if (N->getNumValues() != 1)
2259 if (!N->hasNUsesOfValue(1, 0))
2262 SDValue TCChain = Chain;
2263 SDNode *Copy = *N->use_begin();
2264 if (Copy->getOpcode() == ISD::CopyToReg) {
2265 // If the copy has a glue operand, we conservatively assume it isn't safe to
2266 // perform a tail call.
2267 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2269 TCChain = Copy->getOperand(0);
2270 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2273 bool HasRet = false;
2274 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2276 if (UI->getOpcode() != X86ISD::RET_FLAG)
2278 // If we are returning more than one value, we can definitely
2279 // not make a tail call see PR19530
2280 if (UI->getNumOperands() > 4)
2282 if (UI->getNumOperands() == 4 &&
2283 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2296 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2297 ISD::NodeType ExtendKind) const {
2299 // TODO: Is this also valid on 32-bit?
2300 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2301 ReturnMVT = MVT::i8;
2303 ReturnMVT = MVT::i32;
2305 EVT MinVT = getRegisterType(Context, ReturnMVT);
2306 return VT.bitsLT(MinVT) ? MinVT : VT;
2309 /// Lower the result values of a call into the
2310 /// appropriate copies out of appropriate physical registers.
2313 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2314 CallingConv::ID CallConv, bool isVarArg,
2315 const SmallVectorImpl<ISD::InputArg> &Ins,
2316 SDLoc dl, SelectionDAG &DAG,
2317 SmallVectorImpl<SDValue> &InVals) const {
2319 // Assign locations to each value returned by this call.
2320 SmallVector<CCValAssign, 16> RVLocs;
2321 bool Is64Bit = Subtarget->is64Bit();
2322 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2324 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2326 // Copy all of the result registers out of their specified physreg.
2327 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2328 CCValAssign &VA = RVLocs[i];
2329 EVT CopyVT = VA.getLocVT();
2331 // If this is x86-64, and we disabled SSE, we can't return FP values
2332 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2333 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2334 report_fatal_error("SSE register return with SSE disabled");
2337 // If we prefer to use the value in xmm registers, copy it out as f80 and
2338 // use a truncate to move it from fp stack reg to xmm reg.
2339 bool RoundAfterCopy = false;
2340 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2341 isScalarFPTypeInSSEReg(VA.getValVT())) {
2343 RoundAfterCopy = (CopyVT != VA.getLocVT());
2346 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2347 CopyVT, InFlag).getValue(1);
2348 SDValue Val = Chain.getValue(0);
2351 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2352 // This truncation won't change the value.
2353 DAG.getIntPtrConstant(1, dl));
2355 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2356 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2358 InFlag = Chain.getValue(2);
2359 InVals.push_back(Val);
2365 //===----------------------------------------------------------------------===//
2366 // C & StdCall & Fast Calling Convention implementation
2367 //===----------------------------------------------------------------------===//
2368 // StdCall calling convention seems to be standard for many Windows' API
2369 // routines and around. It differs from C calling convention just a little:
2370 // callee should clean up the stack, not caller. Symbols should be also
2371 // decorated in some fancy way :) It doesn't support any vector arguments.
2372 // For info on fast calling convention see Fast Calling Convention (tail call)
2373 // implementation LowerX86_32FastCCCallTo.
2375 /// CallIsStructReturn - Determines whether a call uses struct return
2377 enum StructReturnType {
2382 static StructReturnType
2383 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2385 return NotStructReturn;
2387 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2388 if (!Flags.isSRet())
2389 return NotStructReturn;
2390 if (Flags.isInReg())
2391 return RegStructReturn;
2392 return StackStructReturn;
2395 /// Determines whether a function uses struct return semantics.
2396 static StructReturnType
2397 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2399 return NotStructReturn;
2401 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2402 if (!Flags.isSRet())
2403 return NotStructReturn;
2404 if (Flags.isInReg())
2405 return RegStructReturn;
2406 return StackStructReturn;
2409 /// Make a copy of an aggregate at address specified by "Src" to address
2410 /// "Dst" with size and alignment information specified by the specific
2411 /// parameter attribute. The copy will be passed as a byval function parameter.
2413 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2414 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2416 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2418 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2419 /*isVolatile*/false, /*AlwaysInline=*/true,
2420 /*isTailCall*/false,
2421 MachinePointerInfo(), MachinePointerInfo());
2424 /// Return true if the calling convention is one that
2425 /// supports tail call optimization.
2426 static bool IsTailCallConvention(CallingConv::ID CC) {
2427 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2428 CC == CallingConv::HiPE);
2431 /// \brief Return true if the calling convention is a C calling convention.
2432 static bool IsCCallConvention(CallingConv::ID CC) {
2433 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2434 CC == CallingConv::X86_64_SysV);
2437 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2439 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2440 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2444 CallingConv::ID CalleeCC = CS.getCallingConv();
2445 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2451 /// Return true if the function is being made into
2452 /// a tailcall target by changing its ABI.
2453 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2454 bool GuaranteedTailCallOpt) {
2455 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2459 X86TargetLowering::LowerMemArgument(SDValue Chain,
2460 CallingConv::ID CallConv,
2461 const SmallVectorImpl<ISD::InputArg> &Ins,
2462 SDLoc dl, SelectionDAG &DAG,
2463 const CCValAssign &VA,
2464 MachineFrameInfo *MFI,
2466 // Create the nodes corresponding to a load from this parameter slot.
2467 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2468 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2469 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2470 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2473 // If value is passed by pointer we have address passed instead of the value
2475 bool ExtendedInMem = VA.isExtInLoc() &&
2476 VA.getValVT().getScalarType() == MVT::i1;
2478 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2479 ValVT = VA.getLocVT();
2481 ValVT = VA.getValVT();
2483 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2484 // changed with more analysis.
2485 // In case of tail call optimization mark all arguments mutable. Since they
2486 // could be overwritten by lowering of arguments in case of a tail call.
2487 if (Flags.isByVal()) {
2488 unsigned Bytes = Flags.getByValSize();
2489 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2490 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2491 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2493 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2494 VA.getLocMemOffset(), isImmutable);
2495 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2496 SDValue Val = DAG.getLoad(
2497 ValVT, dl, Chain, FIN,
2498 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2500 return ExtendedInMem ?
2501 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2505 // FIXME: Get this from tablegen.
2506 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2507 const X86Subtarget *Subtarget) {
2508 assert(Subtarget->is64Bit());
2510 if (Subtarget->isCallingConvWin64(CallConv)) {
2511 static const MCPhysReg GPR64ArgRegsWin64[] = {
2512 X86::RCX, X86::RDX, X86::R8, X86::R9
2514 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2517 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2518 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2520 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2523 // FIXME: Get this from tablegen.
2524 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2525 CallingConv::ID CallConv,
2526 const X86Subtarget *Subtarget) {
2527 assert(Subtarget->is64Bit());
2528 if (Subtarget->isCallingConvWin64(CallConv)) {
2529 // The XMM registers which might contain var arg parameters are shadowed
2530 // in their paired GPR. So we only need to save the GPR to their home
2532 // TODO: __vectorcall will change this.
2536 const Function *Fn = MF.getFunction();
2537 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2538 bool isSoftFloat = Subtarget->useSoftFloat();
2539 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2540 "SSE register cannot be used when SSE is disabled!");
2541 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2542 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2546 static const MCPhysReg XMMArgRegs64Bit[] = {
2547 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2548 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2550 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2553 SDValue X86TargetLowering::LowerFormalArguments(
2554 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2555 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2556 SmallVectorImpl<SDValue> &InVals) const {
2557 MachineFunction &MF = DAG.getMachineFunction();
2558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2559 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2561 const Function* Fn = MF.getFunction();
2562 if (Fn->hasExternalLinkage() &&
2563 Subtarget->isTargetCygMing() &&
2564 Fn->getName() == "main")
2565 FuncInfo->setForceFramePointer(true);
2567 MachineFrameInfo *MFI = MF.getFrameInfo();
2568 bool Is64Bit = Subtarget->is64Bit();
2569 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2571 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2572 "Var args not supported with calling convention fastcc, ghc or hipe");
2574 // Assign locations to all of the incoming arguments.
2575 SmallVector<CCValAssign, 16> ArgLocs;
2576 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2578 // Allocate shadow area for Win64
2580 CCInfo.AllocateStack(32, 8);
2582 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2584 unsigned LastVal = ~0U;
2586 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2587 CCValAssign &VA = ArgLocs[i];
2588 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2590 assert(VA.getValNo() != LastVal &&
2591 "Don't support value assigned to multiple locs yet");
2593 LastVal = VA.getValNo();
2595 if (VA.isRegLoc()) {
2596 EVT RegVT = VA.getLocVT();
2597 const TargetRegisterClass *RC;
2598 if (RegVT == MVT::i32)
2599 RC = &X86::GR32RegClass;
2600 else if (Is64Bit && RegVT == MVT::i64)
2601 RC = &X86::GR64RegClass;
2602 else if (RegVT == MVT::f32)
2603 RC = &X86::FR32RegClass;
2604 else if (RegVT == MVT::f64)
2605 RC = &X86::FR64RegClass;
2606 else if (RegVT.is512BitVector())
2607 RC = &X86::VR512RegClass;
2608 else if (RegVT.is256BitVector())
2609 RC = &X86::VR256RegClass;
2610 else if (RegVT.is128BitVector())
2611 RC = &X86::VR128RegClass;
2612 else if (RegVT == MVT::x86mmx)
2613 RC = &X86::VR64RegClass;
2614 else if (RegVT == MVT::i1)
2615 RC = &X86::VK1RegClass;
2616 else if (RegVT == MVT::v8i1)
2617 RC = &X86::VK8RegClass;
2618 else if (RegVT == MVT::v16i1)
2619 RC = &X86::VK16RegClass;
2620 else if (RegVT == MVT::v32i1)
2621 RC = &X86::VK32RegClass;
2622 else if (RegVT == MVT::v64i1)
2623 RC = &X86::VK64RegClass;
2625 llvm_unreachable("Unknown argument type!");
2627 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2628 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2630 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2631 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2633 if (VA.getLocInfo() == CCValAssign::SExt)
2634 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2635 DAG.getValueType(VA.getValVT()));
2636 else if (VA.getLocInfo() == CCValAssign::ZExt)
2637 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2638 DAG.getValueType(VA.getValVT()));
2639 else if (VA.getLocInfo() == CCValAssign::BCvt)
2640 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2642 if (VA.isExtInLoc()) {
2643 // Handle MMX values passed in XMM regs.
2644 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2645 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2647 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2650 assert(VA.isMemLoc());
2651 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2654 // If value is passed via pointer - do a load.
2655 if (VA.getLocInfo() == CCValAssign::Indirect)
2656 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2657 MachinePointerInfo(), false, false, false, 0);
2659 InVals.push_back(ArgValue);
2662 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2663 // All x86 ABIs require that for returning structs by value we copy the
2664 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2665 // the argument into a virtual register so that we can access it from the
2667 if (Ins[i].Flags.isSRet()) {
2668 unsigned Reg = FuncInfo->getSRetReturnReg();
2670 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2671 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2672 FuncInfo->setSRetReturnReg(Reg);
2674 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2675 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2680 unsigned StackSize = CCInfo.getNextStackOffset();
2681 // Align stack specially for tail calls.
2682 if (FuncIsMadeTailCallSafe(CallConv,
2683 MF.getTarget().Options.GuaranteedTailCallOpt))
2684 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2686 // If the function takes variable number of arguments, make a frame index for
2687 // the start of the first vararg value... for expansion of llvm.va_start. We
2688 // can skip this if there are no va_start calls.
2689 if (MFI->hasVAStart() &&
2690 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2691 CallConv != CallingConv::X86_ThisCall))) {
2692 FuncInfo->setVarArgsFrameIndex(
2693 MFI->CreateFixedObject(1, StackSize, true));
2696 MachineModuleInfo &MMI = MF.getMMI();
2697 const Function *WinEHParent = nullptr;
2698 if (MMI.hasWinEHFuncInfo(Fn))
2699 WinEHParent = MMI.getWinEHParent(Fn);
2700 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2702 // Figure out if XMM registers are in use.
2703 assert(!(Subtarget->useSoftFloat() &&
2704 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2705 "SSE register cannot be used when SSE is disabled!");
2707 // 64-bit calling conventions support varargs and register parameters, so we
2708 // have to do extra work to spill them in the prologue.
2709 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2710 // Find the first unallocated argument registers.
2711 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2712 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2713 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2714 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2715 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2716 "SSE register cannot be used when SSE is disabled!");
2718 // Gather all the live in physical registers.
2719 SmallVector<SDValue, 6> LiveGPRs;
2720 SmallVector<SDValue, 8> LiveXMMRegs;
2722 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2723 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2725 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2727 if (!ArgXMMs.empty()) {
2728 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2729 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2730 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2731 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2732 LiveXMMRegs.push_back(
2733 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2738 // Get to the caller-allocated home save location. Add 8 to account
2739 // for the return address.
2740 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2741 FuncInfo->setRegSaveFrameIndex(
2742 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2743 // Fixup to set vararg frame on shadow area (4 x i64).
2745 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2747 // For X86-64, if there are vararg parameters that are passed via
2748 // registers, then we must store them to their spots on the stack so
2749 // they may be loaded by deferencing the result of va_next.
2750 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2751 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2752 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2753 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2756 // Store the integer parameter registers.
2757 SmallVector<SDValue, 8> MemOps;
2758 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2759 getPointerTy(DAG.getDataLayout()));
2760 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2761 for (SDValue Val : LiveGPRs) {
2762 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2763 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2765 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2766 MachinePointerInfo::getFixedStack(
2767 DAG.getMachineFunction(),
2768 FuncInfo->getRegSaveFrameIndex(), Offset),
2770 MemOps.push_back(Store);
2774 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2775 // Now store the XMM (fp + vector) parameter registers.
2776 SmallVector<SDValue, 12> SaveXMMOps;
2777 SaveXMMOps.push_back(Chain);
2778 SaveXMMOps.push_back(ALVal);
2779 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2780 FuncInfo->getRegSaveFrameIndex(), dl));
2781 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2782 FuncInfo->getVarArgsFPOffset(), dl));
2783 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2785 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2786 MVT::Other, SaveXMMOps));
2789 if (!MemOps.empty())
2790 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2793 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2794 // Find the largest legal vector type.
2795 MVT VecVT = MVT::Other;
2796 // FIXME: Only some x86_32 calling conventions support AVX512.
2797 if (Subtarget->hasAVX512() &&
2798 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2799 CallConv == CallingConv::Intel_OCL_BI)))
2800 VecVT = MVT::v16f32;
2801 else if (Subtarget->hasAVX())
2803 else if (Subtarget->hasSSE2())
2806 // We forward some GPRs and some vector types.
2807 SmallVector<MVT, 2> RegParmTypes;
2808 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2809 RegParmTypes.push_back(IntVT);
2810 if (VecVT != MVT::Other)
2811 RegParmTypes.push_back(VecVT);
2813 // Compute the set of forwarded registers. The rest are scratch.
2814 SmallVectorImpl<ForwardedRegister> &Forwards =
2815 FuncInfo->getForwardedMustTailRegParms();
2816 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2818 // Conservatively forward AL on x86_64, since it might be used for varargs.
2819 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2820 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2821 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2824 // Copy all forwards from physical to virtual registers.
2825 for (ForwardedRegister &F : Forwards) {
2826 // FIXME: Can we use a less constrained schedule?
2827 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2828 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2829 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2833 // Some CCs need callee pop.
2834 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2835 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2836 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2838 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2839 // If this is an sret function, the return should pop the hidden pointer.
2840 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2841 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2842 argsAreStructReturn(Ins) == StackStructReturn)
2843 FuncInfo->setBytesToPopOnReturn(4);
2847 // RegSaveFrameIndex is X86-64 only.
2848 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2849 if (CallConv == CallingConv::X86_FastCall ||
2850 CallConv == CallingConv::X86_ThisCall)
2851 // fastcc functions can't have varargs.
2852 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2855 FuncInfo->setArgumentStackSize(StackSize);
2857 if (IsWinEHParent) {
2859 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2860 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2861 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2862 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2863 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2864 MachinePointerInfo::getFixedStack(
2865 DAG.getMachineFunction(), UnwindHelpFI),
2866 /*isVolatile=*/true,
2867 /*isNonTemporal=*/false, /*Alignment=*/0);
2869 // Functions using Win32 EH are considered to have opaque SP adjustments
2870 // to force local variables to be addressed from the frame or base
2872 MFI->setHasOpaqueSPAdjustment(true);
2880 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2881 SDValue StackPtr, SDValue Arg,
2882 SDLoc dl, SelectionDAG &DAG,
2883 const CCValAssign &VA,
2884 ISD::ArgFlagsTy Flags) const {
2885 unsigned LocMemOffset = VA.getLocMemOffset();
2886 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2887 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2889 if (Flags.isByVal())
2890 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2892 return DAG.getStore(
2893 Chain, dl, Arg, PtrOff,
2894 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2898 /// Emit a load of return address if tail call
2899 /// optimization is performed and it is required.
2901 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2902 SDValue &OutRetAddr, SDValue Chain,
2903 bool IsTailCall, bool Is64Bit,
2904 int FPDiff, SDLoc dl) const {
2905 // Adjust the Return address stack slot.
2906 EVT VT = getPointerTy(DAG.getDataLayout());
2907 OutRetAddr = getReturnAddressFrameIndex(DAG);
2909 // Load the "old" Return address.
2910 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2911 false, false, false, 0);
2912 return SDValue(OutRetAddr.getNode(), 1);
2915 /// Emit a store of the return address if tail call
2916 /// optimization is performed and it is required (FPDiff!=0).
2917 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2918 SDValue Chain, SDValue RetAddrFrIdx,
2919 EVT PtrVT, unsigned SlotSize,
2920 int FPDiff, SDLoc dl) {
2921 // Store the return address to the appropriate stack slot.
2922 if (!FPDiff) return Chain;
2923 // Calculate the new stack slot for the return address.
2924 int NewReturnAddrFI =
2925 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2927 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2928 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2929 MachinePointerInfo::getFixedStack(
2930 DAG.getMachineFunction(), NewReturnAddrFI),
2935 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2936 /// operation of specified width.
2937 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2939 unsigned NumElems = VT.getVectorNumElements();
2940 SmallVector<int, 8> Mask;
2941 Mask.push_back(NumElems);
2942 for (unsigned i = 1; i != NumElems; ++i)
2944 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2948 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2949 SmallVectorImpl<SDValue> &InVals) const {
2950 SelectionDAG &DAG = CLI.DAG;
2952 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2953 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2954 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2955 SDValue Chain = CLI.Chain;
2956 SDValue Callee = CLI.Callee;
2957 CallingConv::ID CallConv = CLI.CallConv;
2958 bool &isTailCall = CLI.IsTailCall;
2959 bool isVarArg = CLI.IsVarArg;
2961 MachineFunction &MF = DAG.getMachineFunction();
2962 bool Is64Bit = Subtarget->is64Bit();
2963 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2964 StructReturnType SR = callIsStructReturn(Outs);
2965 bool IsSibcall = false;
2966 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2967 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2969 if (Attr.getValueAsString() == "true")
2972 if (Subtarget->isPICStyleGOT() &&
2973 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2974 // If we are using a GOT, disable tail calls to external symbols with
2975 // default visibility. Tail calling such a symbol requires using a GOT
2976 // relocation, which forces early binding of the symbol. This breaks code
2977 // that require lazy function symbol resolution. Using musttail or
2978 // GuaranteedTailCallOpt will override this.
2979 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2980 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2981 G->getGlobal()->hasDefaultVisibility()))
2985 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2987 // Force this to be a tail call. The verifier rules are enough to ensure
2988 // that we can lower this successfully without moving the return address
2991 } else if (isTailCall) {
2992 // Check if it's really possible to do a tail call.
2993 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2994 isVarArg, SR != NotStructReturn,
2995 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2996 Outs, OutVals, Ins, DAG);
2998 // Sibcalls are automatically detected tailcalls which do not require
3000 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3007 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3008 "Var args not supported with calling convention fastcc, ghc or hipe");
3010 // Analyze operands of the call, assigning locations to each operand.
3011 SmallVector<CCValAssign, 16> ArgLocs;
3012 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3014 // Allocate shadow area for Win64
3016 CCInfo.AllocateStack(32, 8);
3018 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3020 // Get a count of how many bytes are to be pushed on the stack.
3021 unsigned NumBytes = CCInfo.getNextStackOffset();
3023 // This is a sibcall. The memory operands are available in caller's
3024 // own caller's stack.
3026 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3027 IsTailCallConvention(CallConv))
3028 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3031 if (isTailCall && !IsSibcall && !IsMustTail) {
3032 // Lower arguments at fp - stackoffset + fpdiff.
3033 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3035 FPDiff = NumBytesCallerPushed - NumBytes;
3037 // Set the delta of movement of the returnaddr stackslot.
3038 // But only set if delta is greater than previous delta.
3039 if (FPDiff < X86Info->getTCReturnAddrDelta())
3040 X86Info->setTCReturnAddrDelta(FPDiff);
3043 unsigned NumBytesToPush = NumBytes;
3044 unsigned NumBytesToPop = NumBytes;
3046 // If we have an inalloca argument, all stack space has already been allocated
3047 // for us and be right at the top of the stack. We don't support multiple
3048 // arguments passed in memory when using inalloca.
3049 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3051 if (!ArgLocs.back().isMemLoc())
3052 report_fatal_error("cannot use inalloca attribute on a register "
3054 if (ArgLocs.back().getLocMemOffset() != 0)
3055 report_fatal_error("any parameter with the inalloca attribute must be "
3056 "the only memory argument");
3060 Chain = DAG.getCALLSEQ_START(
3061 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3063 SDValue RetAddrFrIdx;
3064 // Load return address for tail calls.
3065 if (isTailCall && FPDiff)
3066 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3067 Is64Bit, FPDiff, dl);
3069 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3070 SmallVector<SDValue, 8> MemOpChains;
3073 // Walk the register/memloc assignments, inserting copies/loads. In the case
3074 // of tail call optimization arguments are handle later.
3075 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3076 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3077 // Skip inalloca arguments, they have already been written.
3078 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3079 if (Flags.isInAlloca())
3082 CCValAssign &VA = ArgLocs[i];
3083 EVT RegVT = VA.getLocVT();
3084 SDValue Arg = OutVals[i];
3085 bool isByVal = Flags.isByVal();
3087 // Promote the value if needed.
3088 switch (VA.getLocInfo()) {
3089 default: llvm_unreachable("Unknown loc info!");
3090 case CCValAssign::Full: break;
3091 case CCValAssign::SExt:
3092 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3094 case CCValAssign::ZExt:
3095 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3097 case CCValAssign::AExt:
3098 if (Arg.getValueType().isVector() &&
3099 Arg.getValueType().getScalarType() == MVT::i1)
3100 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3101 else if (RegVT.is128BitVector()) {
3102 // Special case: passing MMX values in XMM registers.
3103 Arg = DAG.getBitcast(MVT::i64, Arg);
3104 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3105 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3107 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3109 case CCValAssign::BCvt:
3110 Arg = DAG.getBitcast(RegVT, Arg);
3112 case CCValAssign::Indirect: {
3113 // Store the argument.
3114 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3115 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3116 Chain = DAG.getStore(
3117 Chain, dl, Arg, SpillSlot,
3118 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3125 if (VA.isRegLoc()) {
3126 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3127 if (isVarArg && IsWin64) {
3128 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3129 // shadow reg if callee is a varargs function.
3130 unsigned ShadowReg = 0;
3131 switch (VA.getLocReg()) {
3132 case X86::XMM0: ShadowReg = X86::RCX; break;
3133 case X86::XMM1: ShadowReg = X86::RDX; break;
3134 case X86::XMM2: ShadowReg = X86::R8; break;
3135 case X86::XMM3: ShadowReg = X86::R9; break;
3138 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3140 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3141 assert(VA.isMemLoc());
3142 if (!StackPtr.getNode())
3143 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3144 getPointerTy(DAG.getDataLayout()));
3145 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3146 dl, DAG, VA, Flags));
3150 if (!MemOpChains.empty())
3151 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3153 if (Subtarget->isPICStyleGOT()) {
3154 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3157 RegsToPass.push_back(std::make_pair(
3158 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3159 getPointerTy(DAG.getDataLayout()))));
3161 // If we are tail calling and generating PIC/GOT style code load the
3162 // address of the callee into ECX. The value in ecx is used as target of
3163 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3164 // for tail calls on PIC/GOT architectures. Normally we would just put the
3165 // address of GOT into ebx and then call target@PLT. But for tail calls
3166 // ebx would be restored (since ebx is callee saved) before jumping to the
3169 // Note: The actual moving to ECX is done further down.
3170 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3171 if (G && !G->getGlobal()->hasLocalLinkage() &&
3172 G->getGlobal()->hasDefaultVisibility())
3173 Callee = LowerGlobalAddress(Callee, DAG);
3174 else if (isa<ExternalSymbolSDNode>(Callee))
3175 Callee = LowerExternalSymbol(Callee, DAG);
3179 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3180 // From AMD64 ABI document:
3181 // For calls that may call functions that use varargs or stdargs
3182 // (prototype-less calls or calls to functions containing ellipsis (...) in
3183 // the declaration) %al is used as hidden argument to specify the number
3184 // of SSE registers used. The contents of %al do not need to match exactly
3185 // the number of registers, but must be an ubound on the number of SSE
3186 // registers used and is in the range 0 - 8 inclusive.
3188 // Count the number of XMM registers allocated.
3189 static const MCPhysReg XMMArgRegs[] = {
3190 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3191 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3193 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3194 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3195 && "SSE registers cannot be used when SSE is disabled");
3197 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3198 DAG.getConstant(NumXMMRegs, dl,
3202 if (isVarArg && IsMustTail) {
3203 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3204 for (const auto &F : Forwards) {
3205 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3206 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3210 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3211 // don't need this because the eligibility check rejects calls that require
3212 // shuffling arguments passed in memory.
3213 if (!IsSibcall && isTailCall) {
3214 // Force all the incoming stack arguments to be loaded from the stack
3215 // before any new outgoing arguments are stored to the stack, because the
3216 // outgoing stack slots may alias the incoming argument stack slots, and
3217 // the alias isn't otherwise explicit. This is slightly more conservative
3218 // than necessary, because it means that each store effectively depends
3219 // on every argument instead of just those arguments it would clobber.
3220 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3222 SmallVector<SDValue, 8> MemOpChains2;
3225 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3226 CCValAssign &VA = ArgLocs[i];
3229 assert(VA.isMemLoc());
3230 SDValue Arg = OutVals[i];
3231 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3232 // Skip inalloca arguments. They don't require any work.
3233 if (Flags.isInAlloca())
3235 // Create frame index.
3236 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3237 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3238 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3239 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3241 if (Flags.isByVal()) {
3242 // Copy relative to framepointer.
3243 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3244 if (!StackPtr.getNode())
3245 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3246 getPointerTy(DAG.getDataLayout()));
3247 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3250 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3254 // Store relative to framepointer.
3255 MemOpChains2.push_back(DAG.getStore(
3256 ArgChain, dl, Arg, FIN,
3257 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3262 if (!MemOpChains2.empty())
3263 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3265 // Store the return address to the appropriate stack slot.
3266 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3267 getPointerTy(DAG.getDataLayout()),
3268 RegInfo->getSlotSize(), FPDiff, dl);
3271 // Build a sequence of copy-to-reg nodes chained together with token chain
3272 // and flag operands which copy the outgoing args into registers.
3274 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3275 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3276 RegsToPass[i].second, InFlag);
3277 InFlag = Chain.getValue(1);
3280 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3281 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3282 // In the 64-bit large code model, we have to make all calls
3283 // through a register, since the call instruction's 32-bit
3284 // pc-relative offset may not be large enough to hold the whole
3286 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3287 // If the callee is a GlobalAddress node (quite common, every direct call
3288 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3290 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3292 // We should use extra load for direct calls to dllimported functions in
3294 const GlobalValue *GV = G->getGlobal();
3295 if (!GV->hasDLLImportStorageClass()) {
3296 unsigned char OpFlags = 0;
3297 bool ExtraLoad = false;
3298 unsigned WrapperKind = ISD::DELETED_NODE;
3300 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3301 // external symbols most go through the PLT in PIC mode. If the symbol
3302 // has hidden or protected visibility, or if it is static or local, then
3303 // we don't need to use the PLT - we can directly call it.
3304 if (Subtarget->isTargetELF() &&
3305 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3306 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3307 OpFlags = X86II::MO_PLT;
3308 } else if (Subtarget->isPICStyleStubAny() &&
3309 !GV->isStrongDefinitionForLinker() &&
3310 (!Subtarget->getTargetTriple().isMacOSX() ||
3311 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3312 // PC-relative references to external symbols should go through $stub,
3313 // unless we're building with the leopard linker or later, which
3314 // automatically synthesizes these stubs.
3315 OpFlags = X86II::MO_DARWIN_STUB;
3316 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3317 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3318 // If the function is marked as non-lazy, generate an indirect call
3319 // which loads from the GOT directly. This avoids runtime overhead
3320 // at the cost of eager binding (and one extra byte of encoding).
3321 OpFlags = X86II::MO_GOTPCREL;
3322 WrapperKind = X86ISD::WrapperRIP;
3326 Callee = DAG.getTargetGlobalAddress(
3327 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3329 // Add a wrapper if needed.
3330 if (WrapperKind != ISD::DELETED_NODE)
3331 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3332 getPointerTy(DAG.getDataLayout()), Callee);
3333 // Add extra indirection if needed.
3335 Callee = DAG.getLoad(
3336 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3337 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3340 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3341 unsigned char OpFlags = 0;
3343 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3344 // external symbols should go through the PLT.
3345 if (Subtarget->isTargetELF() &&
3346 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3347 OpFlags = X86II::MO_PLT;
3348 } else if (Subtarget->isPICStyleStubAny() &&
3349 (!Subtarget->getTargetTriple().isMacOSX() ||
3350 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3351 // PC-relative references to external symbols should go through $stub,
3352 // unless we're building with the leopard linker or later, which
3353 // automatically synthesizes these stubs.
3354 OpFlags = X86II::MO_DARWIN_STUB;
3357 Callee = DAG.getTargetExternalSymbol(
3358 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3359 } else if (Subtarget->isTarget64BitILP32() &&
3360 Callee->getValueType(0) == MVT::i32) {
3361 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3362 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3365 // Returns a chain & a flag for retval copy to use.
3366 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3367 SmallVector<SDValue, 8> Ops;
3369 if (!IsSibcall && isTailCall) {
3370 Chain = DAG.getCALLSEQ_END(Chain,
3371 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3372 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3373 InFlag = Chain.getValue(1);
3376 Ops.push_back(Chain);
3377 Ops.push_back(Callee);
3380 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3382 // Add argument registers to the end of the list so that they are known live
3384 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3385 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3386 RegsToPass[i].second.getValueType()));
3388 // Add a register mask operand representing the call-preserved registers.
3389 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3390 assert(Mask && "Missing call preserved mask for calling convention");
3392 // If this is an invoke in a 32-bit function using an MSVC personality, assume
3393 // the function clobbers all registers. If an exception is thrown, the runtime
3394 // will not restore CSRs.
3395 // FIXME: Model this more precisely so that we can register allocate across
3396 // the normal edge and spill and fill across the exceptional edge.
3397 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3398 const Function *CallerFn = MF.getFunction();
3399 EHPersonality Pers =
3400 CallerFn->hasPersonalityFn()
3401 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3402 : EHPersonality::Unknown;
3403 if (isMSVCEHPersonality(Pers))
3404 Mask = RegInfo->getNoPreservedMask();
3407 Ops.push_back(DAG.getRegisterMask(Mask));
3409 if (InFlag.getNode())
3410 Ops.push_back(InFlag);
3414 //// If this is the first return lowered for this function, add the regs
3415 //// to the liveout set for the function.
3416 // This isn't right, although it's probably harmless on x86; liveouts
3417 // should be computed from returns not tail calls. Consider a void
3418 // function making a tail call to a function returning int.
3419 MF.getFrameInfo()->setHasTailCall();
3420 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3423 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3424 InFlag = Chain.getValue(1);
3426 // Create the CALLSEQ_END node.
3427 unsigned NumBytesForCalleeToPop;
3428 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3429 DAG.getTarget().Options.GuaranteedTailCallOpt))
3430 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3431 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3432 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3433 SR == StackStructReturn)
3434 // If this is a call to a struct-return function, the callee
3435 // pops the hidden struct pointer, so we have to push it back.
3436 // This is common for Darwin/X86, Linux & Mingw32 targets.
3437 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3438 NumBytesForCalleeToPop = 4;
3440 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3442 // Returns a flag for retval copy to use.
3444 Chain = DAG.getCALLSEQ_END(Chain,
3445 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3446 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3449 InFlag = Chain.getValue(1);
3452 // Handle result values, copying them out of physregs into vregs that we
3454 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3455 Ins, dl, DAG, InVals);
3458 //===----------------------------------------------------------------------===//
3459 // Fast Calling Convention (tail call) implementation
3460 //===----------------------------------------------------------------------===//
3462 // Like std call, callee cleans arguments, convention except that ECX is
3463 // reserved for storing the tail called function address. Only 2 registers are
3464 // free for argument passing (inreg). Tail call optimization is performed
3466 // * tailcallopt is enabled
3467 // * caller/callee are fastcc
3468 // On X86_64 architecture with GOT-style position independent code only local
3469 // (within module) calls are supported at the moment.
3470 // To keep the stack aligned according to platform abi the function
3471 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3472 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3473 // If a tail called function callee has more arguments than the caller the
3474 // caller needs to make sure that there is room to move the RETADDR to. This is
3475 // achieved by reserving an area the size of the argument delta right after the
3476 // original RETADDR, but before the saved framepointer or the spilled registers
3477 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3489 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3492 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3493 SelectionDAG& DAG) const {
3494 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3495 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3496 unsigned StackAlignment = TFI.getStackAlignment();
3497 uint64_t AlignMask = StackAlignment - 1;
3498 int64_t Offset = StackSize;
3499 unsigned SlotSize = RegInfo->getSlotSize();
3500 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3501 // Number smaller than 12 so just add the difference.
3502 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3504 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3505 Offset = ((~AlignMask) & Offset) + StackAlignment +
3506 (StackAlignment-SlotSize);
3511 /// Return true if the given stack call argument is already available in the
3512 /// same position (relatively) of the caller's incoming argument stack.
3514 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3515 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3516 const X86InstrInfo *TII) {
3517 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3519 if (Arg.getOpcode() == ISD::CopyFromReg) {
3520 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3521 if (!TargetRegisterInfo::isVirtualRegister(VR))
3523 MachineInstr *Def = MRI->getVRegDef(VR);
3526 if (!Flags.isByVal()) {
3527 if (!TII->isLoadFromStackSlot(Def, FI))
3530 unsigned Opcode = Def->getOpcode();
3531 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3532 Opcode == X86::LEA64_32r) &&
3533 Def->getOperand(1).isFI()) {
3534 FI = Def->getOperand(1).getIndex();
3535 Bytes = Flags.getByValSize();
3539 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3540 if (Flags.isByVal())
3541 // ByVal argument is passed in as a pointer but it's now being
3542 // dereferenced. e.g.
3543 // define @foo(%struct.X* %A) {
3544 // tail call @bar(%struct.X* byval %A)
3547 SDValue Ptr = Ld->getBasePtr();
3548 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3551 FI = FINode->getIndex();
3552 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3553 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3554 FI = FINode->getIndex();
3555 Bytes = Flags.getByValSize();
3559 assert(FI != INT_MAX);
3560 if (!MFI->isFixedObjectIndex(FI))
3562 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3565 /// Check whether the call is eligible for tail call optimization. Targets
3566 /// that want to do tail call optimization should implement this function.
3567 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3568 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3569 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3570 const SmallVectorImpl<ISD::OutputArg> &Outs,
3571 const SmallVectorImpl<SDValue> &OutVals,
3572 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3573 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3576 // If -tailcallopt is specified, make fastcc functions tail-callable.
3577 const MachineFunction &MF = DAG.getMachineFunction();
3578 const Function *CallerF = MF.getFunction();
3580 // If the function return type is x86_fp80 and the callee return type is not,
3581 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3582 // perform a tailcall optimization here.
3583 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3586 CallingConv::ID CallerCC = CallerF->getCallingConv();
3587 bool CCMatch = CallerCC == CalleeCC;
3588 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3589 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3591 // Win64 functions have extra shadow space for argument homing. Don't do the
3592 // sibcall if the caller and callee have mismatched expectations for this
3594 if (IsCalleeWin64 != IsCallerWin64)
3597 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3598 if (IsTailCallConvention(CalleeCC) && CCMatch)
3603 // Look for obvious safe cases to perform tail call optimization that do not
3604 // require ABI changes. This is what gcc calls sibcall.
3606 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3607 // emit a special epilogue.
3608 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3609 if (RegInfo->needsStackRealignment(MF))
3612 // Also avoid sibcall optimization if either caller or callee uses struct
3613 // return semantics.
3614 if (isCalleeStructRet || isCallerStructRet)
3617 // An stdcall/thiscall caller is expected to clean up its arguments; the
3618 // callee isn't going to do that.
3619 // FIXME: this is more restrictive than needed. We could produce a tailcall
3620 // when the stack adjustment matches. For example, with a thiscall that takes
3621 // only one argument.
3622 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3623 CallerCC == CallingConv::X86_ThisCall))
3626 // Do not sibcall optimize vararg calls unless all arguments are passed via
3628 if (isVarArg && !Outs.empty()) {
3630 // Optimizing for varargs on Win64 is unlikely to be safe without
3631 // additional testing.
3632 if (IsCalleeWin64 || IsCallerWin64)
3635 SmallVector<CCValAssign, 16> ArgLocs;
3636 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3639 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3640 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3641 if (!ArgLocs[i].isRegLoc())
3645 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3646 // stack. Therefore, if it's not used by the call it is not safe to optimize
3647 // this into a sibcall.
3648 bool Unused = false;
3649 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3656 SmallVector<CCValAssign, 16> RVLocs;
3657 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3659 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3660 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3661 CCValAssign &VA = RVLocs[i];
3662 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3667 // If the calling conventions do not match, then we'd better make sure the
3668 // results are returned in the same way as what the caller expects.
3670 SmallVector<CCValAssign, 16> RVLocs1;
3671 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3673 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3675 SmallVector<CCValAssign, 16> RVLocs2;
3676 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3678 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3680 if (RVLocs1.size() != RVLocs2.size())
3682 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3683 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3685 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3687 if (RVLocs1[i].isRegLoc()) {
3688 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3691 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3697 // If the callee takes no arguments then go on to check the results of the
3699 if (!Outs.empty()) {
3700 // Check if stack adjustment is needed. For now, do not do this if any
3701 // argument is passed on the stack.
3702 SmallVector<CCValAssign, 16> ArgLocs;
3703 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3706 // Allocate shadow area for Win64
3708 CCInfo.AllocateStack(32, 8);
3710 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3711 if (CCInfo.getNextStackOffset()) {
3712 MachineFunction &MF = DAG.getMachineFunction();
3713 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3716 // Check if the arguments are already laid out in the right way as
3717 // the caller's fixed stack objects.
3718 MachineFrameInfo *MFI = MF.getFrameInfo();
3719 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3720 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3721 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3722 CCValAssign &VA = ArgLocs[i];
3723 SDValue Arg = OutVals[i];
3724 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3725 if (VA.getLocInfo() == CCValAssign::Indirect)
3727 if (!VA.isRegLoc()) {
3728 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3735 // If the tailcall address may be in a register, then make sure it's
3736 // possible to register allocate for it. In 32-bit, the call address can
3737 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3738 // callee-saved registers are restored. These happen to be the same
3739 // registers used to pass 'inreg' arguments so watch out for those.
3740 if (!Subtarget->is64Bit() &&
3741 ((!isa<GlobalAddressSDNode>(Callee) &&
3742 !isa<ExternalSymbolSDNode>(Callee)) ||
3743 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3744 unsigned NumInRegs = 0;
3745 // In PIC we need an extra register to formulate the address computation
3747 unsigned MaxInRegs =
3748 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3750 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3751 CCValAssign &VA = ArgLocs[i];
3754 unsigned Reg = VA.getLocReg();
3757 case X86::EAX: case X86::EDX: case X86::ECX:
3758 if (++NumInRegs == MaxInRegs)
3770 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3771 const TargetLibraryInfo *libInfo) const {
3772 return X86::createFastISel(funcInfo, libInfo);
3775 //===----------------------------------------------------------------------===//
3776 // Other Lowering Hooks
3777 //===----------------------------------------------------------------------===//
3779 static bool MayFoldLoad(SDValue Op) {
3780 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3783 static bool MayFoldIntoStore(SDValue Op) {
3784 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3787 static bool isTargetShuffle(unsigned Opcode) {
3789 default: return false;
3790 case X86ISD::BLENDI:
3791 case X86ISD::PSHUFB:
3792 case X86ISD::PSHUFD:
3793 case X86ISD::PSHUFHW:
3794 case X86ISD::PSHUFLW:
3796 case X86ISD::PALIGNR:
3797 case X86ISD::MOVLHPS:
3798 case X86ISD::MOVLHPD:
3799 case X86ISD::MOVHLPS:
3800 case X86ISD::MOVLPS:
3801 case X86ISD::MOVLPD:
3802 case X86ISD::MOVSHDUP:
3803 case X86ISD::MOVSLDUP:
3804 case X86ISD::MOVDDUP:
3807 case X86ISD::UNPCKL:
3808 case X86ISD::UNPCKH:
3809 case X86ISD::VPERMILPI:
3810 case X86ISD::VPERM2X128:
3811 case X86ISD::VPERMI:
3812 case X86ISD::VPERMV:
3813 case X86ISD::VPERMV3:
3818 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3819 SDValue V1, unsigned TargetMask,
3820 SelectionDAG &DAG) {
3822 default: llvm_unreachable("Unknown x86 shuffle node");
3823 case X86ISD::PSHUFD:
3824 case X86ISD::PSHUFHW:
3825 case X86ISD::PSHUFLW:
3826 case X86ISD::VPERMILPI:
3827 case X86ISD::VPERMI:
3828 return DAG.getNode(Opc, dl, VT, V1,
3829 DAG.getConstant(TargetMask, dl, MVT::i8));
3833 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3834 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3836 default: llvm_unreachable("Unknown x86 shuffle node");
3837 case X86ISD::MOVLHPS:
3838 case X86ISD::MOVLHPD:
3839 case X86ISD::MOVHLPS:
3840 case X86ISD::MOVLPS:
3841 case X86ISD::MOVLPD:
3844 case X86ISD::UNPCKL:
3845 case X86ISD::UNPCKH:
3846 return DAG.getNode(Opc, dl, VT, V1, V2);
3850 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3851 MachineFunction &MF = DAG.getMachineFunction();
3852 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3853 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3854 int ReturnAddrIndex = FuncInfo->getRAIndex();
3856 if (ReturnAddrIndex == 0) {
3857 // Set up a frame object for the return address.
3858 unsigned SlotSize = RegInfo->getSlotSize();
3859 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3862 FuncInfo->setRAIndex(ReturnAddrIndex);
3865 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3868 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3869 bool hasSymbolicDisplacement) {
3870 // Offset should fit into 32 bit immediate field.
3871 if (!isInt<32>(Offset))
3874 // If we don't have a symbolic displacement - we don't have any extra
3876 if (!hasSymbolicDisplacement)
3879 // FIXME: Some tweaks might be needed for medium code model.
3880 if (M != CodeModel::Small && M != CodeModel::Kernel)
3883 // For small code model we assume that latest object is 16MB before end of 31
3884 // bits boundary. We may also accept pretty large negative constants knowing
3885 // that all objects are in the positive half of address space.
3886 if (M == CodeModel::Small && Offset < 16*1024*1024)
3889 // For kernel code model we know that all object resist in the negative half
3890 // of 32bits address space. We may not accept negative offsets, since they may
3891 // be just off and we may accept pretty large positive ones.
3892 if (M == CodeModel::Kernel && Offset >= 0)
3898 /// Determines whether the callee is required to pop its own arguments.
3899 /// Callee pop is necessary to support tail calls.
3900 bool X86::isCalleePop(CallingConv::ID CallingConv,
3901 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3902 switch (CallingConv) {
3905 case CallingConv::X86_StdCall:
3906 case CallingConv::X86_FastCall:
3907 case CallingConv::X86_ThisCall:
3909 case CallingConv::Fast:
3910 case CallingConv::GHC:
3911 case CallingConv::HiPE:
3918 /// \brief Return true if the condition is an unsigned comparison operation.
3919 static bool isX86CCUnsigned(unsigned X86CC) {
3921 default: llvm_unreachable("Invalid integer condition!");
3922 case X86::COND_E: return true;
3923 case X86::COND_G: return false;
3924 case X86::COND_GE: return false;
3925 case X86::COND_L: return false;
3926 case X86::COND_LE: return false;
3927 case X86::COND_NE: return true;
3928 case X86::COND_B: return true;
3929 case X86::COND_A: return true;
3930 case X86::COND_BE: return true;
3931 case X86::COND_AE: return true;
3933 llvm_unreachable("covered switch fell through?!");
3936 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3937 /// condition code, returning the condition code and the LHS/RHS of the
3938 /// comparison to make.
3939 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3940 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3942 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3943 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3944 // X > -1 -> X == 0, jump !sign.
3945 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3946 return X86::COND_NS;
3948 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3949 // X < 0 -> X == 0, jump on sign.
3952 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3954 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3955 return X86::COND_LE;
3959 switch (SetCCOpcode) {
3960 default: llvm_unreachable("Invalid integer condition!");
3961 case ISD::SETEQ: return X86::COND_E;
3962 case ISD::SETGT: return X86::COND_G;
3963 case ISD::SETGE: return X86::COND_GE;
3964 case ISD::SETLT: return X86::COND_L;
3965 case ISD::SETLE: return X86::COND_LE;
3966 case ISD::SETNE: return X86::COND_NE;
3967 case ISD::SETULT: return X86::COND_B;
3968 case ISD::SETUGT: return X86::COND_A;
3969 case ISD::SETULE: return X86::COND_BE;
3970 case ISD::SETUGE: return X86::COND_AE;
3974 // First determine if it is required or is profitable to flip the operands.
3976 // If LHS is a foldable load, but RHS is not, flip the condition.
3977 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3978 !ISD::isNON_EXTLoad(RHS.getNode())) {
3979 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3980 std::swap(LHS, RHS);
3983 switch (SetCCOpcode) {
3989 std::swap(LHS, RHS);
3993 // On a floating point condition, the flags are set as follows:
3995 // 0 | 0 | 0 | X > Y
3996 // 0 | 0 | 1 | X < Y
3997 // 1 | 0 | 0 | X == Y
3998 // 1 | 1 | 1 | unordered
3999 switch (SetCCOpcode) {
4000 default: llvm_unreachable("Condcode should be pre-legalized away");
4002 case ISD::SETEQ: return X86::COND_E;
4003 case ISD::SETOLT: // flipped
4005 case ISD::SETGT: return X86::COND_A;
4006 case ISD::SETOLE: // flipped
4008 case ISD::SETGE: return X86::COND_AE;
4009 case ISD::SETUGT: // flipped
4011 case ISD::SETLT: return X86::COND_B;
4012 case ISD::SETUGE: // flipped
4014 case ISD::SETLE: return X86::COND_BE;
4016 case ISD::SETNE: return X86::COND_NE;
4017 case ISD::SETUO: return X86::COND_P;
4018 case ISD::SETO: return X86::COND_NP;
4020 case ISD::SETUNE: return X86::COND_INVALID;
4024 /// Is there a floating point cmov for the specific X86 condition code?
4025 /// Current x86 isa includes the following FP cmov instructions:
4026 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4027 static bool hasFPCMov(unsigned X86CC) {
4043 /// Returns true if the target can instruction select the
4044 /// specified FP immediate natively. If false, the legalizer will
4045 /// materialize the FP immediate as a load from a constant pool.
4046 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4047 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4048 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4054 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4055 ISD::LoadExtType ExtTy,
4057 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4058 // relocation target a movq or addq instruction: don't let the load shrink.
4059 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4060 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4061 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4062 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4066 /// \brief Returns true if it is beneficial to convert a load of a constant
4067 /// to just the constant itself.
4068 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4070 assert(Ty->isIntegerTy());
4072 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4073 if (BitSize == 0 || BitSize > 64)
4078 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4079 unsigned Index) const {
4080 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4083 return (Index == 0 || Index == ResVT.getVectorNumElements());
4086 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4087 // Speculate cttz only if we can directly use TZCNT.
4088 return Subtarget->hasBMI();
4091 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4092 // Speculate ctlz only if we can directly use LZCNT.
4093 return Subtarget->hasLZCNT();
4096 /// Return true if every element in Mask, beginning
4097 /// from position Pos and ending in Pos+Size is undef.
4098 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4099 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4105 /// Return true if Val is undef or if its value falls within the
4106 /// specified range (L, H].
4107 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4108 return (Val < 0) || (Val >= Low && Val < Hi);
4111 /// Val is either less than zero (undef) or equal to the specified value.
4112 static bool isUndefOrEqual(int Val, int CmpVal) {
4113 return (Val < 0 || Val == CmpVal);
4116 /// Return true if every element in Mask, beginning
4117 /// from position Pos and ending in Pos+Size, falls within the specified
4118 /// sequential range (Low, Low+Size]. or is undef.
4119 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4120 unsigned Pos, unsigned Size, int Low) {
4121 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4122 if (!isUndefOrEqual(Mask[i], Low))
4127 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4128 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4129 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4130 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4131 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4134 // The index should be aligned on a vecWidth-bit boundary.
4136 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4138 MVT VT = N->getSimpleValueType(0);
4139 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4140 bool Result = (Index * ElSize) % vecWidth == 0;
4145 /// Return true if the specified INSERT_SUBVECTOR
4146 /// operand specifies a subvector insert that is suitable for input to
4147 /// insertion of 128 or 256-bit subvectors
4148 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4149 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4150 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4152 // The index should be aligned on a vecWidth-bit boundary.
4154 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4156 MVT VT = N->getSimpleValueType(0);
4157 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4158 bool Result = (Index * ElSize) % vecWidth == 0;
4163 bool X86::isVINSERT128Index(SDNode *N) {
4164 return isVINSERTIndex(N, 128);
4167 bool X86::isVINSERT256Index(SDNode *N) {
4168 return isVINSERTIndex(N, 256);
4171 bool X86::isVEXTRACT128Index(SDNode *N) {
4172 return isVEXTRACTIndex(N, 128);
4175 bool X86::isVEXTRACT256Index(SDNode *N) {
4176 return isVEXTRACTIndex(N, 256);
4179 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4180 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4181 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4182 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4185 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4187 MVT VecVT = N->getOperand(0).getSimpleValueType();
4188 MVT ElVT = VecVT.getVectorElementType();
4190 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4191 return Index / NumElemsPerChunk;
4194 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4195 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4196 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4197 llvm_unreachable("Illegal insert subvector for VINSERT");
4200 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4202 MVT VecVT = N->getSimpleValueType(0);
4203 MVT ElVT = VecVT.getVectorElementType();
4205 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4206 return Index / NumElemsPerChunk;
4209 /// Return the appropriate immediate to extract the specified
4210 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4211 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4212 return getExtractVEXTRACTImmediate(N, 128);
4215 /// Return the appropriate immediate to extract the specified
4216 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4217 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4218 return getExtractVEXTRACTImmediate(N, 256);
4221 /// Return the appropriate immediate to insert at the specified
4222 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4223 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4224 return getInsertVINSERTImmediate(N, 128);
4227 /// Return the appropriate immediate to insert at the specified
4228 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4229 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4230 return getInsertVINSERTImmediate(N, 256);
4233 /// Returns true if Elt is a constant integer zero
4234 static bool isZero(SDValue V) {
4235 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4236 return C && C->isNullValue();
4239 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4240 bool X86::isZeroNode(SDValue Elt) {
4243 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4244 return CFP->getValueAPF().isPosZero();
4248 /// Returns a vector of specified type with all zero elements.
4249 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4250 SelectionDAG &DAG, SDLoc dl) {
4251 assert(VT.isVector() && "Expected a vector type");
4253 // Always build SSE zero vectors as <4 x i32> bitcasted
4254 // to their dest type. This ensures they get CSE'd.
4256 if (VT.is128BitVector()) { // SSE
4257 if (Subtarget->hasSSE2()) { // SSE2
4258 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4261 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4262 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4264 } else if (VT.is256BitVector()) { // AVX
4265 if (Subtarget->hasInt256()) { // AVX2
4266 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4267 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4268 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4270 // 256-bit logic and arithmetic instructions in AVX are all
4271 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4272 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4273 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4274 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4276 } else if (VT.is512BitVector()) { // AVX-512
4277 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4278 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4279 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4280 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4281 } else if (VT.getScalarType() == MVT::i1) {
4283 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4284 && "Unexpected vector type");
4285 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4286 && "Unexpected vector type");
4287 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4288 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4289 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4291 llvm_unreachable("Unexpected vector type");
4293 return DAG.getBitcast(VT, Vec);
4296 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4297 SelectionDAG &DAG, SDLoc dl,
4298 unsigned vectorWidth) {
4299 assert((vectorWidth == 128 || vectorWidth == 256) &&
4300 "Unsupported vector width");
4301 EVT VT = Vec.getValueType();
4302 EVT ElVT = VT.getVectorElementType();
4303 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4304 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4305 VT.getVectorNumElements()/Factor);
4307 // Extract from UNDEF is UNDEF.
4308 if (Vec.getOpcode() == ISD::UNDEF)
4309 return DAG.getUNDEF(ResultVT);
4311 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4312 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4314 // This is the index of the first element of the vectorWidth-bit chunk
4316 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4319 // If the input is a buildvector just emit a smaller one.
4320 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4321 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4322 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4325 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4326 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4329 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4330 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4331 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4332 /// instructions or a simple subregister reference. Idx is an index in the
4333 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4334 /// lowering EXTRACT_VECTOR_ELT operations easier.
4335 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4336 SelectionDAG &DAG, SDLoc dl) {
4337 assert((Vec.getValueType().is256BitVector() ||
4338 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4339 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4342 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4343 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4344 SelectionDAG &DAG, SDLoc dl) {
4345 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4346 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4349 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4350 unsigned IdxVal, SelectionDAG &DAG,
4351 SDLoc dl, unsigned vectorWidth) {
4352 assert((vectorWidth == 128 || vectorWidth == 256) &&
4353 "Unsupported vector width");
4354 // Inserting UNDEF is Result
4355 if (Vec.getOpcode() == ISD::UNDEF)
4357 EVT VT = Vec.getValueType();
4358 EVT ElVT = VT.getVectorElementType();
4359 EVT ResultVT = Result.getValueType();
4361 // Insert the relevant vectorWidth bits.
4362 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4364 // This is the index of the first element of the vectorWidth-bit chunk
4366 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4369 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4370 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4373 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4374 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4375 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4376 /// simple superregister reference. Idx is an index in the 128 bits
4377 /// we want. It need not be aligned to a 128-bit boundary. That makes
4378 /// lowering INSERT_VECTOR_ELT operations easier.
4379 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4380 SelectionDAG &DAG, SDLoc dl) {
4381 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4383 // For insertion into the zero index (low half) of a 256-bit vector, it is
4384 // more efficient to generate a blend with immediate instead of an insert*128.
4385 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4386 // extend the subvector to the size of the result vector. Make sure that
4387 // we are not recursing on that node by checking for undef here.
4388 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4389 Result.getOpcode() != ISD::UNDEF) {
4390 EVT ResultVT = Result.getValueType();
4391 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4392 SDValue Undef = DAG.getUNDEF(ResultVT);
4393 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4396 // The blend instruction, and therefore its mask, depend on the data type.
4397 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4398 if (ScalarType.isFloatingPoint()) {
4399 // Choose either vblendps (float) or vblendpd (double).
4400 unsigned ScalarSize = ScalarType.getSizeInBits();
4401 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4402 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4403 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4404 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4407 const X86Subtarget &Subtarget =
4408 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4410 // AVX2 is needed for 256-bit integer blend support.
4411 // Integers must be cast to 32-bit because there is only vpblendd;
4412 // vpblendw can't be used for this because it has a handicapped mask.
4414 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4415 // is still more efficient than using the wrong domain vinsertf128 that
4416 // will be created by InsertSubVector().
4417 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4419 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4420 Vec256 = DAG.getBitcast(CastVT, Vec256);
4421 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4422 return DAG.getBitcast(ResultVT, Vec256);
4425 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4428 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4429 SelectionDAG &DAG, SDLoc dl) {
4430 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4431 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4434 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4435 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4436 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4437 /// large BUILD_VECTORS.
4438 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4439 unsigned NumElems, SelectionDAG &DAG,
4441 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4442 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4445 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4446 unsigned NumElems, SelectionDAG &DAG,
4448 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4449 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4452 /// Returns a vector of specified type with all bits set.
4453 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4454 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4455 /// Then bitcast to their original type, ensuring they get CSE'd.
4456 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4457 SelectionDAG &DAG, SDLoc dl) {
4458 assert(VT.isVector() && "Expected a vector type");
4460 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4462 if (VT.is512BitVector()) {
4463 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4464 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4465 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4466 } else if (VT.is256BitVector()) {
4467 if (Subtarget->hasInt256()) { // AVX2
4468 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4469 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4471 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4472 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4474 } else if (VT.is128BitVector()) {
4475 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4477 llvm_unreachable("Unexpected vector type");
4479 return DAG.getBitcast(VT, Vec);
4482 /// Returns a vector_shuffle node for an unpackl operation.
4483 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4485 unsigned NumElems = VT.getVectorNumElements();
4486 SmallVector<int, 8> Mask;
4487 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4489 Mask.push_back(i + NumElems);
4491 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4494 /// Returns a vector_shuffle node for an unpackh operation.
4495 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4497 unsigned NumElems = VT.getVectorNumElements();
4498 SmallVector<int, 8> Mask;
4499 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4500 Mask.push_back(i + Half);
4501 Mask.push_back(i + NumElems + Half);
4503 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4506 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4507 /// This produces a shuffle where the low element of V2 is swizzled into the
4508 /// zero/undef vector, landing at element Idx.
4509 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4510 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4512 const X86Subtarget *Subtarget,
4513 SelectionDAG &DAG) {
4514 MVT VT = V2.getSimpleValueType();
4516 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4517 unsigned NumElems = VT.getVectorNumElements();
4518 SmallVector<int, 16> MaskVec;
4519 for (unsigned i = 0; i != NumElems; ++i)
4520 // If this is the insertion idx, put the low elt of V2 here.
4521 MaskVec.push_back(i == Idx ? NumElems : i);
4522 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4525 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4526 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4527 /// uses one source. Note that this will set IsUnary for shuffles which use a
4528 /// single input multiple times, and in those cases it will
4529 /// adjust the mask to only have indices within that single input.
4530 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4531 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4532 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4533 unsigned NumElems = VT.getVectorNumElements();
4537 bool IsFakeUnary = false;
4538 switch(N->getOpcode()) {
4539 case X86ISD::BLENDI:
4540 ImmN = N->getOperand(N->getNumOperands()-1);
4541 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4544 ImmN = N->getOperand(N->getNumOperands()-1);
4545 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4546 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4548 case X86ISD::UNPCKH:
4549 DecodeUNPCKHMask(VT, Mask);
4550 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4552 case X86ISD::UNPCKL:
4553 DecodeUNPCKLMask(VT, Mask);
4554 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4556 case X86ISD::MOVHLPS:
4557 DecodeMOVHLPSMask(NumElems, Mask);
4558 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4560 case X86ISD::MOVLHPS:
4561 DecodeMOVLHPSMask(NumElems, Mask);
4562 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4564 case X86ISD::PALIGNR:
4565 ImmN = N->getOperand(N->getNumOperands()-1);
4566 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4568 case X86ISD::PSHUFD:
4569 case X86ISD::VPERMILPI:
4570 ImmN = N->getOperand(N->getNumOperands()-1);
4571 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4574 case X86ISD::PSHUFHW:
4575 ImmN = N->getOperand(N->getNumOperands()-1);
4576 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4579 case X86ISD::PSHUFLW:
4580 ImmN = N->getOperand(N->getNumOperands()-1);
4581 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4584 case X86ISD::PSHUFB: {
4586 SDValue MaskNode = N->getOperand(1);
4587 while (MaskNode->getOpcode() == ISD::BITCAST)
4588 MaskNode = MaskNode->getOperand(0);
4590 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4591 // If we have a build-vector, then things are easy.
4592 EVT VT = MaskNode.getValueType();
4593 assert(VT.isVector() &&
4594 "Can't produce a non-vector with a build_vector!");
4595 if (!VT.isInteger())
4598 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4600 SmallVector<uint64_t, 32> RawMask;
4601 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4602 SDValue Op = MaskNode->getOperand(i);
4603 if (Op->getOpcode() == ISD::UNDEF) {
4604 RawMask.push_back((uint64_t)SM_SentinelUndef);
4607 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4610 APInt MaskElement = CN->getAPIntValue();
4612 // We now have to decode the element which could be any integer size and
4613 // extract each byte of it.
4614 for (int j = 0; j < NumBytesPerElement; ++j) {
4615 // Note that this is x86 and so always little endian: the low byte is
4616 // the first byte of the mask.
4617 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4618 MaskElement = MaskElement.lshr(8);
4621 DecodePSHUFBMask(RawMask, Mask);
4625 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4629 SDValue Ptr = MaskLoad->getBasePtr();
4630 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4631 Ptr->getOpcode() == X86ISD::WrapperRIP)
4632 Ptr = Ptr->getOperand(0);
4634 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4635 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4638 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4639 DecodePSHUFBMask(C, Mask);
4647 case X86ISD::VPERMI:
4648 ImmN = N->getOperand(N->getNumOperands()-1);
4649 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4654 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4656 case X86ISD::VPERM2X128:
4657 ImmN = N->getOperand(N->getNumOperands()-1);
4658 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4659 if (Mask.empty()) return false;
4660 // Mask only contains negative index if an element is zero.
4661 if (std::any_of(Mask.begin(), Mask.end(),
4662 [](int M){ return M == SM_SentinelZero; }))
4665 case X86ISD::MOVSLDUP:
4666 DecodeMOVSLDUPMask(VT, Mask);
4669 case X86ISD::MOVSHDUP:
4670 DecodeMOVSHDUPMask(VT, Mask);
4673 case X86ISD::MOVDDUP:
4674 DecodeMOVDDUPMask(VT, Mask);
4677 case X86ISD::MOVLHPD:
4678 case X86ISD::MOVLPD:
4679 case X86ISD::MOVLPS:
4680 // Not yet implemented
4682 case X86ISD::VPERMV: {
4684 SDValue MaskNode = N->getOperand(0);
4685 while (MaskNode->getOpcode() == ISD::BITCAST)
4686 MaskNode = MaskNode->getOperand(0);
4688 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4689 SmallVector<uint64_t, 32> RawMask;
4690 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4691 // If we have a build-vector, then things are easy.
4692 assert(MaskNode.getValueType().isInteger() &&
4693 MaskNode.getValueType().getVectorNumElements() ==
4694 VT.getVectorNumElements());
4696 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4697 SDValue Op = MaskNode->getOperand(i);
4698 if (Op->getOpcode() == ISD::UNDEF)
4699 RawMask.push_back((uint64_t)SM_SentinelUndef);
4700 else if (isa<ConstantSDNode>(Op)) {
4701 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4702 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4706 DecodeVPERMVMask(RawMask, Mask);
4709 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4710 unsigned NumEltsInMask = MaskNode->getNumOperands();
4711 MaskNode = MaskNode->getOperand(0);
4712 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4714 APInt MaskEltValue = CN->getAPIntValue();
4715 for (unsigned i = 0; i < NumEltsInMask; ++i)
4716 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4717 DecodeVPERMVMask(RawMask, Mask);
4720 // It may be a scalar load
4723 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4727 SDValue Ptr = MaskLoad->getBasePtr();
4728 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4729 Ptr->getOpcode() == X86ISD::WrapperRIP)
4730 Ptr = Ptr->getOperand(0);
4732 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4733 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4736 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4738 DecodeVPERMVMask(C, VT, Mask);
4745 case X86ISD::VPERMV3: {
4747 SDValue MaskNode = N->getOperand(1);
4748 while (MaskNode->getOpcode() == ISD::BITCAST)
4749 MaskNode = MaskNode->getOperand(1);
4751 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4752 // If we have a build-vector, then things are easy.
4753 assert(MaskNode.getValueType().isInteger() &&
4754 MaskNode.getValueType().getVectorNumElements() ==
4755 VT.getVectorNumElements());
4757 SmallVector<uint64_t, 32> RawMask;
4758 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4760 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4761 SDValue Op = MaskNode->getOperand(i);
4762 if (Op->getOpcode() == ISD::UNDEF)
4763 RawMask.push_back((uint64_t)SM_SentinelUndef);
4765 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4768 APInt MaskElement = CN->getAPIntValue();
4769 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4772 DecodeVPERMV3Mask(RawMask, Mask);
4776 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4780 SDValue Ptr = MaskLoad->getBasePtr();
4781 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4782 Ptr->getOpcode() == X86ISD::WrapperRIP)
4783 Ptr = Ptr->getOperand(0);
4785 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4786 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4789 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4791 DecodeVPERMV3Mask(C, VT, Mask);
4798 default: llvm_unreachable("unknown target shuffle node");
4801 // If we have a fake unary shuffle, the shuffle mask is spread across two
4802 // inputs that are actually the same node. Re-map the mask to always point
4803 // into the first input.
4806 if (M >= (int)Mask.size())
4812 /// Returns the scalar element that will make up the ith
4813 /// element of the result of the vector shuffle.
4814 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4817 return SDValue(); // Limit search depth.
4819 SDValue V = SDValue(N, 0);
4820 EVT VT = V.getValueType();
4821 unsigned Opcode = V.getOpcode();
4823 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4824 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4825 int Elt = SV->getMaskElt(Index);
4828 return DAG.getUNDEF(VT.getVectorElementType());
4830 unsigned NumElems = VT.getVectorNumElements();
4831 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4832 : SV->getOperand(1);
4833 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4836 // Recurse into target specific vector shuffles to find scalars.
4837 if (isTargetShuffle(Opcode)) {
4838 MVT ShufVT = V.getSimpleValueType();
4839 unsigned NumElems = ShufVT.getVectorNumElements();
4840 SmallVector<int, 16> ShuffleMask;
4843 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4846 int Elt = ShuffleMask[Index];
4848 return DAG.getUNDEF(ShufVT.getVectorElementType());
4850 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4852 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4856 // Actual nodes that may contain scalar elements
4857 if (Opcode == ISD::BITCAST) {
4858 V = V.getOperand(0);
4859 EVT SrcVT = V.getValueType();
4860 unsigned NumElems = VT.getVectorNumElements();
4862 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4866 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4867 return (Index == 0) ? V.getOperand(0)
4868 : DAG.getUNDEF(VT.getVectorElementType());
4870 if (V.getOpcode() == ISD::BUILD_VECTOR)
4871 return V.getOperand(Index);
4876 /// Custom lower build_vector of v16i8.
4877 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4878 unsigned NumNonZero, unsigned NumZero,
4880 const X86Subtarget* Subtarget,
4881 const TargetLowering &TLI) {
4889 // SSE4.1 - use PINSRB to insert each byte directly.
4890 if (Subtarget->hasSSE41()) {
4891 for (unsigned i = 0; i < 16; ++i) {
4892 bool isNonZero = (NonZeros & (1 << i)) != 0;
4896 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4898 V = DAG.getUNDEF(MVT::v16i8);
4901 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4902 MVT::v16i8, V, Op.getOperand(i),
4903 DAG.getIntPtrConstant(i, dl));
4910 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4911 for (unsigned i = 0; i < 16; ++i) {
4912 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4913 if (ThisIsNonZero && First) {
4915 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4917 V = DAG.getUNDEF(MVT::v8i16);
4922 SDValue ThisElt, LastElt;
4923 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4924 if (LastIsNonZero) {
4925 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4926 MVT::i16, Op.getOperand(i-1));
4928 if (ThisIsNonZero) {
4929 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4930 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4931 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4933 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4937 if (ThisElt.getNode())
4938 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4939 DAG.getIntPtrConstant(i/2, dl));
4943 return DAG.getBitcast(MVT::v16i8, V);
4946 /// Custom lower build_vector of v8i16.
4947 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4948 unsigned NumNonZero, unsigned NumZero,
4950 const X86Subtarget* Subtarget,
4951 const TargetLowering &TLI) {
4958 for (unsigned i = 0; i < 8; ++i) {
4959 bool isNonZero = (NonZeros & (1 << i)) != 0;
4963 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4965 V = DAG.getUNDEF(MVT::v8i16);
4968 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4969 MVT::v8i16, V, Op.getOperand(i),
4970 DAG.getIntPtrConstant(i, dl));
4977 /// Custom lower build_vector of v4i32 or v4f32.
4978 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4979 const X86Subtarget *Subtarget,
4980 const TargetLowering &TLI) {
4981 // Find all zeroable elements.
4982 std::bitset<4> Zeroable;
4983 for (int i=0; i < 4; ++i) {
4984 SDValue Elt = Op->getOperand(i);
4985 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4987 assert(Zeroable.size() - Zeroable.count() > 1 &&
4988 "We expect at least two non-zero elements!");
4990 // We only know how to deal with build_vector nodes where elements are either
4991 // zeroable or extract_vector_elt with constant index.
4992 SDValue FirstNonZero;
4993 unsigned FirstNonZeroIdx;
4994 for (unsigned i=0; i < 4; ++i) {
4997 SDValue Elt = Op->getOperand(i);
4998 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4999 !isa<ConstantSDNode>(Elt.getOperand(1)))
5001 // Make sure that this node is extracting from a 128-bit vector.
5002 MVT VT = Elt.getOperand(0).getSimpleValueType();
5003 if (!VT.is128BitVector())
5005 if (!FirstNonZero.getNode()) {
5007 FirstNonZeroIdx = i;
5011 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5012 SDValue V1 = FirstNonZero.getOperand(0);
5013 MVT VT = V1.getSimpleValueType();
5015 // See if this build_vector can be lowered as a blend with zero.
5017 unsigned EltMaskIdx, EltIdx;
5019 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5020 if (Zeroable[EltIdx]) {
5021 // The zero vector will be on the right hand side.
5022 Mask[EltIdx] = EltIdx+4;
5026 Elt = Op->getOperand(EltIdx);
5027 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5028 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5029 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5031 Mask[EltIdx] = EltIdx;
5035 // Let the shuffle legalizer deal with blend operations.
5036 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5037 if (V1.getSimpleValueType() != VT)
5038 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5039 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5042 // See if we can lower this build_vector to a INSERTPS.
5043 if (!Subtarget->hasSSE41())
5046 SDValue V2 = Elt.getOperand(0);
5047 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5050 bool CanFold = true;
5051 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5055 SDValue Current = Op->getOperand(i);
5056 SDValue SrcVector = Current->getOperand(0);
5059 CanFold = SrcVector == V1 &&
5060 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5066 assert(V1.getNode() && "Expected at least two non-zero elements!");
5067 if (V1.getSimpleValueType() != MVT::v4f32)
5068 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5069 if (V2.getSimpleValueType() != MVT::v4f32)
5070 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5072 // Ok, we can emit an INSERTPS instruction.
5073 unsigned ZMask = Zeroable.to_ulong();
5075 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5076 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5078 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5079 DAG.getIntPtrConstant(InsertPSMask, DL));
5080 return DAG.getBitcast(VT, Result);
5083 /// Return a vector logical shift node.
5084 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5085 unsigned NumBits, SelectionDAG &DAG,
5086 const TargetLowering &TLI, SDLoc dl) {
5087 assert(VT.is128BitVector() && "Unknown type for VShift");
5088 MVT ShVT = MVT::v2i64;
5089 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5090 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5091 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5092 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5093 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5094 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5098 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5100 // Check if the scalar load can be widened into a vector load. And if
5101 // the address is "base + cst" see if the cst can be "absorbed" into
5102 // the shuffle mask.
5103 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5104 SDValue Ptr = LD->getBasePtr();
5105 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5107 EVT PVT = LD->getValueType(0);
5108 if (PVT != MVT::i32 && PVT != MVT::f32)
5113 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5114 FI = FINode->getIndex();
5116 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5117 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5118 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5119 Offset = Ptr.getConstantOperandVal(1);
5120 Ptr = Ptr.getOperand(0);
5125 // FIXME: 256-bit vector instructions don't require a strict alignment,
5126 // improve this code to support it better.
5127 unsigned RequiredAlign = VT.getSizeInBits()/8;
5128 SDValue Chain = LD->getChain();
5129 // Make sure the stack object alignment is at least 16 or 32.
5130 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5131 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5132 if (MFI->isFixedObjectIndex(FI)) {
5133 // Can't change the alignment. FIXME: It's possible to compute
5134 // the exact stack offset and reference FI + adjust offset instead.
5135 // If someone *really* cares about this. That's the way to implement it.
5138 MFI->setObjectAlignment(FI, RequiredAlign);
5142 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5143 // Ptr + (Offset & ~15).
5146 if ((Offset % RequiredAlign) & 3)
5148 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5151 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5152 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5155 int EltNo = (Offset - StartOffset) >> 2;
5156 unsigned NumElems = VT.getVectorNumElements();
5158 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5159 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5160 LD->getPointerInfo().getWithOffset(StartOffset),
5161 false, false, false, 0);
5163 SmallVector<int, 8> Mask(NumElems, EltNo);
5165 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5171 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5172 /// elements can be replaced by a single large load which has the same value as
5173 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5175 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5177 /// FIXME: we'd also like to handle the case where the last elements are zero
5178 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5179 /// There's even a handy isZeroNode for that purpose.
5180 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5181 SDLoc &DL, SelectionDAG &DAG,
5182 bool isAfterLegalize) {
5183 unsigned NumElems = Elts.size();
5185 LoadSDNode *LDBase = nullptr;
5186 unsigned LastLoadedElt = -1U;
5188 // For each element in the initializer, see if we've found a load or an undef.
5189 // If we don't find an initial load element, or later load elements are
5190 // non-consecutive, bail out.
5191 for (unsigned i = 0; i < NumElems; ++i) {
5192 SDValue Elt = Elts[i];
5193 // Look through a bitcast.
5194 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5195 Elt = Elt.getOperand(0);
5196 if (!Elt.getNode() ||
5197 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5200 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5202 LDBase = cast<LoadSDNode>(Elt.getNode());
5206 if (Elt.getOpcode() == ISD::UNDEF)
5209 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5210 EVT LdVT = Elt.getValueType();
5211 // Each loaded element must be the correct fractional portion of the
5212 // requested vector load.
5213 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5215 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5220 // If we have found an entire vector of loads and undefs, then return a large
5221 // load of the entire vector width starting at the base pointer. If we found
5222 // consecutive loads for the low half, generate a vzext_load node.
5223 if (LastLoadedElt == NumElems - 1) {
5224 assert(LDBase && "Did not find base load for merging consecutive loads");
5225 EVT EltVT = LDBase->getValueType(0);
5226 // Ensure that the input vector size for the merged loads matches the
5227 // cumulative size of the input elements.
5228 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5231 if (isAfterLegalize &&
5232 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5235 SDValue NewLd = SDValue();
5237 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5238 LDBase->getPointerInfo(), LDBase->isVolatile(),
5239 LDBase->isNonTemporal(), LDBase->isInvariant(),
5240 LDBase->getAlignment());
5242 if (LDBase->hasAnyUseOfValue(1)) {
5243 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5245 SDValue(NewLd.getNode(), 1));
5246 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5247 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5248 SDValue(NewLd.getNode(), 1));
5254 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5255 //of a v4i32 / v4f32. It's probably worth generalizing.
5256 EVT EltVT = VT.getVectorElementType();
5257 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5258 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5259 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5260 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5262 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5263 LDBase->getPointerInfo(),
5264 LDBase->getAlignment(),
5265 false/*isVolatile*/, true/*ReadMem*/,
5268 // Make sure the newly-created LOAD is in the same position as LDBase in
5269 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5270 // update uses of LDBase's output chain to use the TokenFactor.
5271 if (LDBase->hasAnyUseOfValue(1)) {
5272 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5273 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5274 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5275 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5276 SDValue(ResNode.getNode(), 1));
5279 return DAG.getBitcast(VT, ResNode);
5284 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5285 /// to generate a splat value for the following cases:
5286 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5287 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5288 /// a scalar load, or a constant.
5289 /// The VBROADCAST node is returned when a pattern is found,
5290 /// or SDValue() otherwise.
5291 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5292 SelectionDAG &DAG) {
5293 // VBROADCAST requires AVX.
5294 // TODO: Splats could be generated for non-AVX CPUs using SSE
5295 // instructions, but there's less potential gain for only 128-bit vectors.
5296 if (!Subtarget->hasAVX())
5299 MVT VT = Op.getSimpleValueType();
5302 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5303 "Unsupported vector type for broadcast.");
5308 switch (Op.getOpcode()) {
5310 // Unknown pattern found.
5313 case ISD::BUILD_VECTOR: {
5314 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5315 BitVector UndefElements;
5316 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5318 // We need a splat of a single value to use broadcast, and it doesn't
5319 // make any sense if the value is only in one element of the vector.
5320 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5324 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5325 Ld.getOpcode() == ISD::ConstantFP);
5327 // Make sure that all of the users of a non-constant load are from the
5328 // BUILD_VECTOR node.
5329 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5334 case ISD::VECTOR_SHUFFLE: {
5335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5337 // Shuffles must have a splat mask where the first element is
5339 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5342 SDValue Sc = Op.getOperand(0);
5343 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5344 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5346 if (!Subtarget->hasInt256())
5349 // Use the register form of the broadcast instruction available on AVX2.
5350 if (VT.getSizeInBits() >= 256)
5351 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5352 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5355 Ld = Sc.getOperand(0);
5356 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5357 Ld.getOpcode() == ISD::ConstantFP);
5359 // The scalar_to_vector node and the suspected
5360 // load node must have exactly one user.
5361 // Constants may have multiple users.
5363 // AVX-512 has register version of the broadcast
5364 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5365 Ld.getValueType().getSizeInBits() >= 32;
5366 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5373 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5374 bool IsGE256 = (VT.getSizeInBits() >= 256);
5376 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5377 // instruction to save 8 or more bytes of constant pool data.
5378 // TODO: If multiple splats are generated to load the same constant,
5379 // it may be detrimental to overall size. There needs to be a way to detect
5380 // that condition to know if this is truly a size win.
5381 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5383 // Handle broadcasting a single constant scalar from the constant pool
5385 // On Sandybridge (no AVX2), it is still better to load a constant vector
5386 // from the constant pool and not to broadcast it from a scalar.
5387 // But override that restriction when optimizing for size.
5388 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5389 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5390 EVT CVT = Ld.getValueType();
5391 assert(!CVT.isVector() && "Must not broadcast a vector type");
5393 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5394 // For size optimization, also splat v2f64 and v2i64, and for size opt
5395 // with AVX2, also splat i8 and i16.
5396 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5397 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5398 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5399 const Constant *C = nullptr;
5400 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5401 C = CI->getConstantIntValue();
5402 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5403 C = CF->getConstantFPValue();
5405 assert(C && "Invalid constant type");
5407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5409 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5410 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5412 CVT, dl, DAG.getEntryNode(), CP,
5413 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5414 false, false, Alignment);
5416 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5420 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5422 // Handle AVX2 in-register broadcasts.
5423 if (!IsLoad && Subtarget->hasInt256() &&
5424 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5425 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5427 // The scalar source must be a normal load.
5431 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5432 (Subtarget->hasVLX() && ScalarSize == 64))
5433 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5435 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5436 // double since there is no vbroadcastsd xmm
5437 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5438 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5439 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5442 // Unsupported broadcast.
5446 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5447 /// underlying vector and index.
5449 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5451 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5453 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5454 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5457 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5459 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5461 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5462 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5465 // In this case the vector is the extract_subvector expression and the index
5466 // is 2, as specified by the shuffle.
5467 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5468 SDValue ShuffleVec = SVOp->getOperand(0);
5469 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5470 assert(ShuffleVecVT.getVectorElementType() ==
5471 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5473 int ShuffleIdx = SVOp->getMaskElt(Idx);
5474 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5475 ExtractedFromVec = ShuffleVec;
5481 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5482 MVT VT = Op.getSimpleValueType();
5484 // Skip if insert_vec_elt is not supported.
5485 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5486 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5490 unsigned NumElems = Op.getNumOperands();
5494 SmallVector<unsigned, 4> InsertIndices;
5495 SmallVector<int, 8> Mask(NumElems, -1);
5497 for (unsigned i = 0; i != NumElems; ++i) {
5498 unsigned Opc = Op.getOperand(i).getOpcode();
5500 if (Opc == ISD::UNDEF)
5503 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5504 // Quit if more than 1 elements need inserting.
5505 if (InsertIndices.size() > 1)
5508 InsertIndices.push_back(i);
5512 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5513 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5514 // Quit if non-constant index.
5515 if (!isa<ConstantSDNode>(ExtIdx))
5517 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5519 // Quit if extracted from vector of different type.
5520 if (ExtractedFromVec.getValueType() != VT)
5523 if (!VecIn1.getNode())
5524 VecIn1 = ExtractedFromVec;
5525 else if (VecIn1 != ExtractedFromVec) {
5526 if (!VecIn2.getNode())
5527 VecIn2 = ExtractedFromVec;
5528 else if (VecIn2 != ExtractedFromVec)
5529 // Quit if more than 2 vectors to shuffle
5533 if (ExtractedFromVec == VecIn1)
5535 else if (ExtractedFromVec == VecIn2)
5536 Mask[i] = Idx + NumElems;
5539 if (!VecIn1.getNode())
5542 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5543 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5544 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5545 unsigned Idx = InsertIndices[i];
5546 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5547 DAG.getIntPtrConstant(Idx, DL));
5553 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5554 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5555 Op.getScalarValueSizeInBits() == 1 &&
5556 "Can not convert non-constant vector");
5557 uint64_t Immediate = 0;
5558 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5559 SDValue In = Op.getOperand(idx);
5560 if (In.getOpcode() != ISD::UNDEF)
5561 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5565 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5566 return DAG.getConstant(Immediate, dl, VT);
5568 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5570 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5572 MVT VT = Op.getSimpleValueType();
5573 assert((VT.getVectorElementType() == MVT::i1) &&
5574 "Unexpected type in LowerBUILD_VECTORvXi1!");
5577 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5578 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5579 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5580 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5583 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5584 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5585 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5586 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5589 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5590 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5591 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5592 return DAG.getBitcast(VT, Imm);
5593 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5594 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5595 DAG.getIntPtrConstant(0, dl));
5598 // Vector has one or more non-const elements
5599 uint64_t Immediate = 0;
5600 SmallVector<unsigned, 16> NonConstIdx;
5601 bool IsSplat = true;
5602 bool HasConstElts = false;
5604 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5605 SDValue In = Op.getOperand(idx);
5606 if (In.getOpcode() == ISD::UNDEF)
5608 if (!isa<ConstantSDNode>(In))
5609 NonConstIdx.push_back(idx);
5611 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5612 HasConstElts = true;
5616 else if (In != Op.getOperand(SplatIdx))
5620 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5622 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5623 DAG.getConstant(1, dl, VT),
5624 DAG.getConstant(0, dl, VT));
5626 // insert elements one by one
5630 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5631 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5633 else if (HasConstElts)
5634 Imm = DAG.getConstant(0, dl, VT);
5636 Imm = DAG.getUNDEF(VT);
5637 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5638 DstVec = DAG.getBitcast(VT, Imm);
5640 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5641 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5642 DAG.getIntPtrConstant(0, dl));
5645 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5646 unsigned InsertIdx = NonConstIdx[i];
5647 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5648 Op.getOperand(InsertIdx),
5649 DAG.getIntPtrConstant(InsertIdx, dl));
5654 /// \brief Return true if \p N implements a horizontal binop and return the
5655 /// operands for the horizontal binop into V0 and V1.
5657 /// This is a helper function of LowerToHorizontalOp().
5658 /// This function checks that the build_vector \p N in input implements a
5659 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5660 /// operation to match.
5661 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5662 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5663 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5666 /// This function only analyzes elements of \p N whose indices are
5667 /// in range [BaseIdx, LastIdx).
5668 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5670 unsigned BaseIdx, unsigned LastIdx,
5671 SDValue &V0, SDValue &V1) {
5672 EVT VT = N->getValueType(0);
5674 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5675 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5676 "Invalid Vector in input!");
5678 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5679 bool CanFold = true;
5680 unsigned ExpectedVExtractIdx = BaseIdx;
5681 unsigned NumElts = LastIdx - BaseIdx;
5682 V0 = DAG.getUNDEF(VT);
5683 V1 = DAG.getUNDEF(VT);
5685 // Check if N implements a horizontal binop.
5686 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5687 SDValue Op = N->getOperand(i + BaseIdx);
5690 if (Op->getOpcode() == ISD::UNDEF) {
5691 // Update the expected vector extract index.
5692 if (i * 2 == NumElts)
5693 ExpectedVExtractIdx = BaseIdx;
5694 ExpectedVExtractIdx += 2;
5698 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5703 SDValue Op0 = Op.getOperand(0);
5704 SDValue Op1 = Op.getOperand(1);
5706 // Try to match the following pattern:
5707 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5708 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5709 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5710 Op0.getOperand(0) == Op1.getOperand(0) &&
5711 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5712 isa<ConstantSDNode>(Op1.getOperand(1)));
5716 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5717 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5719 if (i * 2 < NumElts) {
5720 if (V0.getOpcode() == ISD::UNDEF) {
5721 V0 = Op0.getOperand(0);
5722 if (V0.getValueType() != VT)
5726 if (V1.getOpcode() == ISD::UNDEF) {
5727 V1 = Op0.getOperand(0);
5728 if (V1.getValueType() != VT)
5731 if (i * 2 == NumElts)
5732 ExpectedVExtractIdx = BaseIdx;
5735 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5736 if (I0 == ExpectedVExtractIdx)
5737 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5738 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5739 // Try to match the following dag sequence:
5740 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5741 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5745 ExpectedVExtractIdx += 2;
5751 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5752 /// a concat_vector.
5754 /// This is a helper function of LowerToHorizontalOp().
5755 /// This function expects two 256-bit vectors called V0 and V1.
5756 /// At first, each vector is split into two separate 128-bit vectors.
5757 /// Then, the resulting 128-bit vectors are used to implement two
5758 /// horizontal binary operations.
5760 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5762 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5763 /// the two new horizontal binop.
5764 /// When Mode is set, the first horizontal binop dag node would take as input
5765 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5766 /// horizontal binop dag node would take as input the lower 128-bit of V1
5767 /// and the upper 128-bit of V1.
5769 /// HADD V0_LO, V0_HI
5770 /// HADD V1_LO, V1_HI
5772 /// Otherwise, the first horizontal binop dag node takes as input the lower
5773 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5774 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5776 /// HADD V0_LO, V1_LO
5777 /// HADD V0_HI, V1_HI
5779 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5780 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5781 /// the upper 128-bits of the result.
5782 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5783 SDLoc DL, SelectionDAG &DAG,
5784 unsigned X86Opcode, bool Mode,
5785 bool isUndefLO, bool isUndefHI) {
5786 EVT VT = V0.getValueType();
5787 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5788 "Invalid nodes in input!");
5790 unsigned NumElts = VT.getVectorNumElements();
5791 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5792 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5793 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5794 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5795 EVT NewVT = V0_LO.getValueType();
5797 SDValue LO = DAG.getUNDEF(NewVT);
5798 SDValue HI = DAG.getUNDEF(NewVT);
5801 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5802 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5803 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5804 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5805 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5807 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5808 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5809 V1_LO->getOpcode() != ISD::UNDEF))
5810 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5812 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5813 V1_HI->getOpcode() != ISD::UNDEF))
5814 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5817 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5820 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5822 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5823 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5824 EVT VT = BV->getValueType(0);
5825 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5826 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5830 unsigned NumElts = VT.getVectorNumElements();
5831 SDValue InVec0 = DAG.getUNDEF(VT);
5832 SDValue InVec1 = DAG.getUNDEF(VT);
5834 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5835 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5837 // Odd-numbered elements in the input build vector are obtained from
5838 // adding two integer/float elements.
5839 // Even-numbered elements in the input build vector are obtained from
5840 // subtracting two integer/float elements.
5841 unsigned ExpectedOpcode = ISD::FSUB;
5842 unsigned NextExpectedOpcode = ISD::FADD;
5843 bool AddFound = false;
5844 bool SubFound = false;
5846 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5847 SDValue Op = BV->getOperand(i);
5849 // Skip 'undef' values.
5850 unsigned Opcode = Op.getOpcode();
5851 if (Opcode == ISD::UNDEF) {
5852 std::swap(ExpectedOpcode, NextExpectedOpcode);
5856 // Early exit if we found an unexpected opcode.
5857 if (Opcode != ExpectedOpcode)
5860 SDValue Op0 = Op.getOperand(0);
5861 SDValue Op1 = Op.getOperand(1);
5863 // Try to match the following pattern:
5864 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5865 // Early exit if we cannot match that sequence.
5866 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5867 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5868 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5869 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5870 Op0.getOperand(1) != Op1.getOperand(1))
5873 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5877 // We found a valid add/sub node. Update the information accordingly.
5883 // Update InVec0 and InVec1.
5884 if (InVec0.getOpcode() == ISD::UNDEF) {
5885 InVec0 = Op0.getOperand(0);
5886 if (InVec0.getValueType() != VT)
5889 if (InVec1.getOpcode() == ISD::UNDEF) {
5890 InVec1 = Op1.getOperand(0);
5891 if (InVec1.getValueType() != VT)
5895 // Make sure that operands in input to each add/sub node always
5896 // come from a same pair of vectors.
5897 if (InVec0 != Op0.getOperand(0)) {
5898 if (ExpectedOpcode == ISD::FSUB)
5901 // FADD is commutable. Try to commute the operands
5902 // and then test again.
5903 std::swap(Op0, Op1);
5904 if (InVec0 != Op0.getOperand(0))
5908 if (InVec1 != Op1.getOperand(0))
5911 // Update the pair of expected opcodes.
5912 std::swap(ExpectedOpcode, NextExpectedOpcode);
5915 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5916 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5917 InVec1.getOpcode() != ISD::UNDEF)
5918 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5923 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5924 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5925 const X86Subtarget *Subtarget,
5926 SelectionDAG &DAG) {
5927 EVT VT = BV->getValueType(0);
5928 unsigned NumElts = VT.getVectorNumElements();
5929 unsigned NumUndefsLO = 0;
5930 unsigned NumUndefsHI = 0;
5931 unsigned Half = NumElts/2;
5933 // Count the number of UNDEF operands in the build_vector in input.
5934 for (unsigned i = 0, e = Half; i != e; ++i)
5935 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5938 for (unsigned i = Half, e = NumElts; i != e; ++i)
5939 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5942 // Early exit if this is either a build_vector of all UNDEFs or all the
5943 // operands but one are UNDEF.
5944 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5948 SDValue InVec0, InVec1;
5949 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5950 // Try to match an SSE3 float HADD/HSUB.
5951 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5952 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5954 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5955 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5956 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5957 // Try to match an SSSE3 integer HADD/HSUB.
5958 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5959 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5961 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5962 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5965 if (!Subtarget->hasAVX())
5968 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5969 // Try to match an AVX horizontal add/sub of packed single/double
5970 // precision floating point values from 256-bit vectors.
5971 SDValue InVec2, InVec3;
5972 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5973 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5974 ((InVec0.getOpcode() == ISD::UNDEF ||
5975 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5976 ((InVec1.getOpcode() == ISD::UNDEF ||
5977 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5978 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5980 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5981 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5982 ((InVec0.getOpcode() == ISD::UNDEF ||
5983 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5984 ((InVec1.getOpcode() == ISD::UNDEF ||
5985 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5986 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5987 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5988 // Try to match an AVX2 horizontal add/sub of signed integers.
5989 SDValue InVec2, InVec3;
5991 bool CanFold = true;
5993 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5994 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5995 ((InVec0.getOpcode() == ISD::UNDEF ||
5996 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5997 ((InVec1.getOpcode() == ISD::UNDEF ||
5998 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5999 X86Opcode = X86ISD::HADD;
6000 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6001 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6002 ((InVec0.getOpcode() == ISD::UNDEF ||
6003 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6004 ((InVec1.getOpcode() == ISD::UNDEF ||
6005 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6006 X86Opcode = X86ISD::HSUB;
6011 // Fold this build_vector into a single horizontal add/sub.
6012 // Do this only if the target has AVX2.
6013 if (Subtarget->hasAVX2())
6014 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6016 // Do not try to expand this build_vector into a pair of horizontal
6017 // add/sub if we can emit a pair of scalar add/sub.
6018 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6021 // Convert this build_vector into a pair of horizontal binop followed by
6023 bool isUndefLO = NumUndefsLO == Half;
6024 bool isUndefHI = NumUndefsHI == Half;
6025 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6026 isUndefLO, isUndefHI);
6030 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6031 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6033 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6034 X86Opcode = X86ISD::HADD;
6035 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6036 X86Opcode = X86ISD::HSUB;
6037 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6038 X86Opcode = X86ISD::FHADD;
6039 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6040 X86Opcode = X86ISD::FHSUB;
6044 // Don't try to expand this build_vector into a pair of horizontal add/sub
6045 // if we can simply emit a pair of scalar add/sub.
6046 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6049 // Convert this build_vector into two horizontal add/sub followed by
6051 bool isUndefLO = NumUndefsLO == Half;
6052 bool isUndefHI = NumUndefsHI == Half;
6053 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6054 isUndefLO, isUndefHI);
6061 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6064 MVT VT = Op.getSimpleValueType();
6065 MVT ExtVT = VT.getVectorElementType();
6066 unsigned NumElems = Op.getNumOperands();
6068 // Generate vectors for predicate vectors.
6069 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6070 return LowerBUILD_VECTORvXi1(Op, DAG);
6072 // Vectors containing all zeros can be matched by pxor and xorps later
6073 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6074 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6075 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6076 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6079 return getZeroVector(VT, Subtarget, DAG, dl);
6082 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6083 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6084 // vpcmpeqd on 256-bit vectors.
6085 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6086 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6089 if (!VT.is512BitVector())
6090 return getOnesVector(VT, Subtarget, DAG, dl);
6093 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6094 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6096 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6097 return HorizontalOp;
6098 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6101 unsigned EVTBits = ExtVT.getSizeInBits();
6103 unsigned NumZero = 0;
6104 unsigned NumNonZero = 0;
6105 unsigned NonZeros = 0;
6106 bool IsAllConstants = true;
6107 SmallSet<SDValue, 8> Values;
6108 for (unsigned i = 0; i < NumElems; ++i) {
6109 SDValue Elt = Op.getOperand(i);
6110 if (Elt.getOpcode() == ISD::UNDEF)
6113 if (Elt.getOpcode() != ISD::Constant &&
6114 Elt.getOpcode() != ISD::ConstantFP)
6115 IsAllConstants = false;
6116 if (X86::isZeroNode(Elt))
6119 NonZeros |= (1 << i);
6124 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6125 if (NumNonZero == 0)
6126 return DAG.getUNDEF(VT);
6128 // Special case for single non-zero, non-undef, element.
6129 if (NumNonZero == 1) {
6130 unsigned Idx = countTrailingZeros(NonZeros);
6131 SDValue Item = Op.getOperand(Idx);
6133 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6134 // the value are obviously zero, truncate the value to i32 and do the
6135 // insertion that way. Only do this if the value is non-constant or if the
6136 // value is a constant being inserted into element 0. It is cheaper to do
6137 // a constant pool load than it is to do a movd + shuffle.
6138 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6139 (!IsAllConstants || Idx == 0)) {
6140 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6142 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6143 EVT VecVT = MVT::v4i32;
6145 // Truncate the value (which may itself be a constant) to i32, and
6146 // convert it to a vector with movd (S2V+shuffle to zero extend).
6147 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6148 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6149 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6150 Item, Idx * 2, true, Subtarget, DAG));
6154 // If we have a constant or non-constant insertion into the low element of
6155 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6156 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6157 // depending on what the source datatype is.
6160 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6162 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6163 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6164 if (VT.is512BitVector()) {
6165 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6166 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6167 Item, DAG.getIntPtrConstant(0, dl));
6169 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6170 "Expected an SSE value type!");
6171 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6172 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6173 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6176 // We can't directly insert an i8 or i16 into a vector, so zero extend
6178 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6179 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6180 if (VT.is256BitVector()) {
6181 if (Subtarget->hasAVX()) {
6182 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6183 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6185 // Without AVX, we need to extend to a 128-bit vector and then
6186 // insert into the 256-bit vector.
6187 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6188 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6189 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6192 assert(VT.is128BitVector() && "Expected an SSE value type!");
6193 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6194 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6196 return DAG.getBitcast(VT, Item);
6200 // Is it a vector logical left shift?
6201 if (NumElems == 2 && Idx == 1 &&
6202 X86::isZeroNode(Op.getOperand(0)) &&
6203 !X86::isZeroNode(Op.getOperand(1))) {
6204 unsigned NumBits = VT.getSizeInBits();
6205 return getVShift(true, VT,
6206 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6207 VT, Op.getOperand(1)),
6208 NumBits/2, DAG, *this, dl);
6211 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6214 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6215 // is a non-constant being inserted into an element other than the low one,
6216 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6217 // movd/movss) to move this into the low element, then shuffle it into
6219 if (EVTBits == 32) {
6220 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6221 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6225 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6226 if (Values.size() == 1) {
6227 if (EVTBits == 32) {
6228 // Instead of a shuffle like this:
6229 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6230 // Check if it's possible to issue this instead.
6231 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6232 unsigned Idx = countTrailingZeros(NonZeros);
6233 SDValue Item = Op.getOperand(Idx);
6234 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6235 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6240 // A vector full of immediates; various special cases are already
6241 // handled, so this is best done with a single constant-pool load.
6245 // For AVX-length vectors, see if we can use a vector load to get all of the
6246 // elements, otherwise build the individual 128-bit pieces and use
6247 // shuffles to put them in place.
6248 if (VT.is256BitVector() || VT.is512BitVector()) {
6249 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6251 // Check for a build vector of consecutive loads.
6252 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6255 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6257 // Build both the lower and upper subvector.
6258 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6259 makeArrayRef(&V[0], NumElems/2));
6260 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6261 makeArrayRef(&V[NumElems / 2], NumElems/2));
6263 // Recreate the wider vector with the lower and upper part.
6264 if (VT.is256BitVector())
6265 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6266 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6269 // Let legalizer expand 2-wide build_vectors.
6270 if (EVTBits == 64) {
6271 if (NumNonZero == 1) {
6272 // One half is zero or undef.
6273 unsigned Idx = countTrailingZeros(NonZeros);
6274 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6275 Op.getOperand(Idx));
6276 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6281 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6282 if (EVTBits == 8 && NumElems == 16)
6283 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6287 if (EVTBits == 16 && NumElems == 8)
6288 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6292 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6293 if (EVTBits == 32 && NumElems == 4)
6294 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6297 // If element VT is == 32 bits, turn it into a number of shuffles.
6298 SmallVector<SDValue, 8> V(NumElems);
6299 if (NumElems == 4 && NumZero > 0) {
6300 for (unsigned i = 0; i < 4; ++i) {
6301 bool isZero = !(NonZeros & (1 << i));
6303 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6305 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6308 for (unsigned i = 0; i < 2; ++i) {
6309 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6312 V[i] = V[i*2]; // Must be a zero vector.
6315 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6318 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6321 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6326 bool Reverse1 = (NonZeros & 0x3) == 2;
6327 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6331 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6332 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6334 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6337 if (Values.size() > 1 && VT.is128BitVector()) {
6338 // Check for a build vector of consecutive loads.
6339 for (unsigned i = 0; i < NumElems; ++i)
6340 V[i] = Op.getOperand(i);
6342 // Check for elements which are consecutive loads.
6343 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6346 // Check for a build vector from mostly shuffle plus few inserting.
6347 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6350 // For SSE 4.1, use insertps to put the high elements into the low element.
6351 if (Subtarget->hasSSE41()) {
6353 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6354 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6356 Result = DAG.getUNDEF(VT);
6358 for (unsigned i = 1; i < NumElems; ++i) {
6359 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6360 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6361 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6366 // Otherwise, expand into a number of unpckl*, start by extending each of
6367 // our (non-undef) elements to the full vector width with the element in the
6368 // bottom slot of the vector (which generates no code for SSE).
6369 for (unsigned i = 0; i < NumElems; ++i) {
6370 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6371 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6373 V[i] = DAG.getUNDEF(VT);
6376 // Next, we iteratively mix elements, e.g. for v4f32:
6377 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6378 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6379 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6380 unsigned EltStride = NumElems >> 1;
6381 while (EltStride != 0) {
6382 for (unsigned i = 0; i < EltStride; ++i) {
6383 // If V[i+EltStride] is undef and this is the first round of mixing,
6384 // then it is safe to just drop this shuffle: V[i] is already in the
6385 // right place, the one element (since it's the first round) being
6386 // inserted as undef can be dropped. This isn't safe for successive
6387 // rounds because they will permute elements within both vectors.
6388 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6389 EltStride == NumElems/2)
6392 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6401 // 256-bit AVX can use the vinsertf128 instruction
6402 // to create 256-bit vectors from two other 128-bit ones.
6403 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6405 MVT ResVT = Op.getSimpleValueType();
6407 assert((ResVT.is256BitVector() ||
6408 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6410 SDValue V1 = Op.getOperand(0);
6411 SDValue V2 = Op.getOperand(1);
6412 unsigned NumElems = ResVT.getVectorNumElements();
6413 if (ResVT.is256BitVector())
6414 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6416 if (Op.getNumOperands() == 4) {
6417 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6418 ResVT.getVectorNumElements()/2);
6419 SDValue V3 = Op.getOperand(2);
6420 SDValue V4 = Op.getOperand(3);
6421 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6422 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6424 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6427 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6428 const X86Subtarget *Subtarget,
6429 SelectionDAG & DAG) {
6431 MVT ResVT = Op.getSimpleValueType();
6432 unsigned NumOfOperands = Op.getNumOperands();
6434 assert(isPowerOf2_32(NumOfOperands) &&
6435 "Unexpected number of operands in CONCAT_VECTORS");
6437 if (NumOfOperands > 2) {
6438 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6439 ResVT.getVectorNumElements()/2);
6440 SmallVector<SDValue, 2> Ops;
6441 for (unsigned i = 0; i < NumOfOperands/2; i++)
6442 Ops.push_back(Op.getOperand(i));
6443 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6445 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6446 Ops.push_back(Op.getOperand(i));
6447 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6448 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6451 SDValue V1 = Op.getOperand(0);
6452 SDValue V2 = Op.getOperand(1);
6453 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6454 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6456 if (IsZeroV1 && IsZeroV2)
6457 return getZeroVector(ResVT, Subtarget, DAG, dl);
6459 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6460 SDValue Undef = DAG.getUNDEF(ResVT);
6461 unsigned NumElems = ResVT.getVectorNumElements();
6462 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6464 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6465 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6469 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6470 // Zero the upper bits of V1
6471 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6472 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6475 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6478 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6479 const X86Subtarget *Subtarget,
6480 SelectionDAG &DAG) {
6481 MVT VT = Op.getSimpleValueType();
6482 if (VT.getVectorElementType() == MVT::i1)
6483 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6485 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6486 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6487 Op.getNumOperands() == 4)));
6489 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6490 // from two other 128-bit ones.
6492 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6493 return LowerAVXCONCAT_VECTORS(Op, DAG);
6496 //===----------------------------------------------------------------------===//
6497 // Vector shuffle lowering
6499 // This is an experimental code path for lowering vector shuffles on x86. It is
6500 // designed to handle arbitrary vector shuffles and blends, gracefully
6501 // degrading performance as necessary. It works hard to recognize idiomatic
6502 // shuffles and lower them to optimal instruction patterns without leaving
6503 // a framework that allows reasonably efficient handling of all vector shuffle
6505 //===----------------------------------------------------------------------===//
6507 /// \brief Tiny helper function to identify a no-op mask.
6509 /// This is a somewhat boring predicate function. It checks whether the mask
6510 /// array input, which is assumed to be a single-input shuffle mask of the kind
6511 /// used by the X86 shuffle instructions (not a fully general
6512 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6513 /// in-place shuffle are 'no-op's.
6514 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6515 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6516 if (Mask[i] != -1 && Mask[i] != i)
6521 /// \brief Helper function to classify a mask as a single-input mask.
6523 /// This isn't a generic single-input test because in the vector shuffle
6524 /// lowering we canonicalize single inputs to be the first input operand. This
6525 /// means we can more quickly test for a single input by only checking whether
6526 /// an input from the second operand exists. We also assume that the size of
6527 /// mask corresponds to the size of the input vectors which isn't true in the
6528 /// fully general case.
6529 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6531 if (M >= (int)Mask.size())
6536 /// \brief Test whether there are elements crossing 128-bit lanes in this
6539 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6540 /// and we routinely test for these.
6541 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6542 int LaneSize = 128 / VT.getScalarSizeInBits();
6543 int Size = Mask.size();
6544 for (int i = 0; i < Size; ++i)
6545 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6550 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6552 /// This checks a shuffle mask to see if it is performing the same
6553 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6554 /// that it is also not lane-crossing. It may however involve a blend from the
6555 /// same lane of a second vector.
6557 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6558 /// non-trivial to compute in the face of undef lanes. The representation is
6559 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6560 /// entries from both V1 and V2 inputs to the wider mask.
6562 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6563 SmallVectorImpl<int> &RepeatedMask) {
6564 int LaneSize = 128 / VT.getScalarSizeInBits();
6565 RepeatedMask.resize(LaneSize, -1);
6566 int Size = Mask.size();
6567 for (int i = 0; i < Size; ++i) {
6570 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6571 // This entry crosses lanes, so there is no way to model this shuffle.
6574 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6575 if (RepeatedMask[i % LaneSize] == -1)
6576 // This is the first non-undef entry in this slot of a 128-bit lane.
6577 RepeatedMask[i % LaneSize] =
6578 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6579 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6580 // Found a mismatch with the repeated mask.
6586 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6589 /// This is a fast way to test a shuffle mask against a fixed pattern:
6591 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6593 /// It returns true if the mask is exactly as wide as the argument list, and
6594 /// each element of the mask is either -1 (signifying undef) or the value given
6595 /// in the argument.
6596 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6597 ArrayRef<int> ExpectedMask) {
6598 if (Mask.size() != ExpectedMask.size())
6601 int Size = Mask.size();
6603 // If the values are build vectors, we can look through them to find
6604 // equivalent inputs that make the shuffles equivalent.
6605 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6606 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6608 for (int i = 0; i < Size; ++i)
6609 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6610 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6611 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6612 if (!MaskBV || !ExpectedBV ||
6613 MaskBV->getOperand(Mask[i] % Size) !=
6614 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6621 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6623 /// This helper function produces an 8-bit shuffle immediate corresponding to
6624 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6625 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6628 /// NB: We rely heavily on "undef" masks preserving the input lane.
6629 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6630 SelectionDAG &DAG) {
6631 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6632 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6633 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6634 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6635 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6638 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6639 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6640 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6641 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6642 return DAG.getConstant(Imm, DL, MVT::i8);
6645 /// \brief Compute whether each element of a shuffle is zeroable.
6647 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6648 /// Either it is an undef element in the shuffle mask, the element of the input
6649 /// referenced is undef, or the element of the input referenced is known to be
6650 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6651 /// as many lanes with this technique as possible to simplify the remaining
6653 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6654 SDValue V1, SDValue V2) {
6655 SmallBitVector Zeroable(Mask.size(), false);
6657 while (V1.getOpcode() == ISD::BITCAST)
6658 V1 = V1->getOperand(0);
6659 while (V2.getOpcode() == ISD::BITCAST)
6660 V2 = V2->getOperand(0);
6662 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6663 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6665 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6667 // Handle the easy cases.
6668 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6673 // If this is an index into a build_vector node (which has the same number
6674 // of elements), dig out the input value and use it.
6675 SDValue V = M < Size ? V1 : V2;
6676 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6679 SDValue Input = V.getOperand(M % Size);
6680 // The UNDEF opcode check really should be dead code here, but not quite
6681 // worth asserting on (it isn't invalid, just unexpected).
6682 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6689 // X86 has dedicated unpack instructions that can handle specific blend
6690 // operations: UNPCKH and UNPCKL.
6691 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6692 SDValue V1, SDValue V2,
6693 SelectionDAG &DAG) {
6694 int NumElts = VT.getVectorNumElements();
6697 bool UnpcklSwapped = true;
6698 bool UnpckhSwapped = true;
6699 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6701 for (int i = 0; i < NumElts; ++i) {
6702 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6704 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6705 int HiPos = LoPos + NumEltsInLane / 2;
6706 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6707 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6711 if (Mask[i] != LoPos)
6713 if (Mask[i] != HiPos)
6715 if (Mask[i] != LoPosSwapped)
6716 UnpcklSwapped = false;
6717 if (Mask[i] != HiPosSwapped)
6718 UnpckhSwapped = false;
6719 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6723 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6725 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6727 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6729 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6731 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6735 /// \brief Try to emit a bitmask instruction for a shuffle.
6737 /// This handles cases where we can model a blend exactly as a bitmask due to
6738 /// one of the inputs being zeroable.
6739 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6740 SDValue V2, ArrayRef<int> Mask,
6741 SelectionDAG &DAG) {
6742 MVT EltVT = VT.getScalarType();
6743 int NumEltBits = EltVT.getSizeInBits();
6744 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6745 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6746 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6748 if (EltVT.isFloatingPoint()) {
6749 Zero = DAG.getBitcast(EltVT, Zero);
6750 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6752 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6753 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6755 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6758 if (Mask[i] % Size != i)
6759 return SDValue(); // Not a blend.
6761 V = Mask[i] < Size ? V1 : V2;
6762 else if (V != (Mask[i] < Size ? V1 : V2))
6763 return SDValue(); // Can only let one input through the mask.
6765 VMaskOps[i] = AllOnes;
6768 return SDValue(); // No non-zeroable elements!
6770 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6771 V = DAG.getNode(VT.isFloatingPoint()
6772 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6777 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6779 /// This is used as a fallback approach when first class blend instructions are
6780 /// unavailable. Currently it is only suitable for integer vectors, but could
6781 /// be generalized for floating point vectors if desirable.
6782 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6783 SDValue V2, ArrayRef<int> Mask,
6784 SelectionDAG &DAG) {
6785 assert(VT.isInteger() && "Only supports integer vector types!");
6786 MVT EltVT = VT.getScalarType();
6787 int NumEltBits = EltVT.getSizeInBits();
6788 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6789 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6791 SmallVector<SDValue, 16> MaskOps;
6792 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6793 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6794 return SDValue(); // Shuffled input!
6795 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6798 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6799 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6800 // We have to cast V2 around.
6801 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6802 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6803 DAG.getBitcast(MaskVT, V1Mask),
6804 DAG.getBitcast(MaskVT, V2)));
6805 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6808 /// \brief Try to emit a blend instruction for a shuffle.
6810 /// This doesn't do any checks for the availability of instructions for blending
6811 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6812 /// be matched in the backend with the type given. What it does check for is
6813 /// that the shuffle mask is in fact a blend.
6814 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6815 SDValue V2, ArrayRef<int> Mask,
6816 const X86Subtarget *Subtarget,
6817 SelectionDAG &DAG) {
6818 unsigned BlendMask = 0;
6819 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6820 if (Mask[i] >= Size) {
6821 if (Mask[i] != i + Size)
6822 return SDValue(); // Shuffled V2 input!
6823 BlendMask |= 1u << i;
6826 if (Mask[i] >= 0 && Mask[i] != i)
6827 return SDValue(); // Shuffled V1 input!
6829 switch (VT.SimpleTy) {
6834 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6835 DAG.getConstant(BlendMask, DL, MVT::i8));
6839 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6843 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6844 // that instruction.
6845 if (Subtarget->hasAVX2()) {
6846 // Scale the blend by the number of 32-bit dwords per element.
6847 int Scale = VT.getScalarSizeInBits() / 32;
6849 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6850 if (Mask[i] >= Size)
6851 for (int j = 0; j < Scale; ++j)
6852 BlendMask |= 1u << (i * Scale + j);
6854 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6855 V1 = DAG.getBitcast(BlendVT, V1);
6856 V2 = DAG.getBitcast(BlendVT, V2);
6857 return DAG.getBitcast(
6858 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6859 DAG.getConstant(BlendMask, DL, MVT::i8)));
6863 // For integer shuffles we need to expand the mask and cast the inputs to
6864 // v8i16s prior to blending.
6865 int Scale = 8 / VT.getVectorNumElements();
6867 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6868 if (Mask[i] >= Size)
6869 for (int j = 0; j < Scale; ++j)
6870 BlendMask |= 1u << (i * Scale + j);
6872 V1 = DAG.getBitcast(MVT::v8i16, V1);
6873 V2 = DAG.getBitcast(MVT::v8i16, V2);
6874 return DAG.getBitcast(VT,
6875 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6876 DAG.getConstant(BlendMask, DL, MVT::i8)));
6880 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6881 SmallVector<int, 8> RepeatedMask;
6882 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6883 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6884 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6886 for (int i = 0; i < 8; ++i)
6887 if (RepeatedMask[i] >= 16)
6888 BlendMask |= 1u << i;
6889 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6890 DAG.getConstant(BlendMask, DL, MVT::i8));
6896 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6897 "256-bit byte-blends require AVX2 support!");
6899 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6900 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6903 // Scale the blend by the number of bytes per element.
6904 int Scale = VT.getScalarSizeInBits() / 8;
6906 // This form of blend is always done on bytes. Compute the byte vector
6908 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6910 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6911 // mix of LLVM's code generator and the x86 backend. We tell the code
6912 // generator that boolean values in the elements of an x86 vector register
6913 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6914 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6915 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6916 // of the element (the remaining are ignored) and 0 in that high bit would
6917 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6918 // the LLVM model for boolean values in vector elements gets the relevant
6919 // bit set, it is set backwards and over constrained relative to x86's
6921 SmallVector<SDValue, 32> VSELECTMask;
6922 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6923 for (int j = 0; j < Scale; ++j)
6924 VSELECTMask.push_back(
6925 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6926 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6929 V1 = DAG.getBitcast(BlendVT, V1);
6930 V2 = DAG.getBitcast(BlendVT, V2);
6931 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6932 DAG.getNode(ISD::BUILD_VECTOR, DL,
6933 BlendVT, VSELECTMask),
6938 llvm_unreachable("Not a supported integer vector type!");
6942 /// \brief Try to lower as a blend of elements from two inputs followed by
6943 /// a single-input permutation.
6945 /// This matches the pattern where we can blend elements from two inputs and
6946 /// then reduce the shuffle to a single-input permutation.
6947 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6950 SelectionDAG &DAG) {
6951 // We build up the blend mask while checking whether a blend is a viable way
6952 // to reduce the shuffle.
6953 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6954 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6956 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6960 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6962 if (BlendMask[Mask[i] % Size] == -1)
6963 BlendMask[Mask[i] % Size] = Mask[i];
6964 else if (BlendMask[Mask[i] % Size] != Mask[i])
6965 return SDValue(); // Can't blend in the needed input!
6967 PermuteMask[i] = Mask[i] % Size;
6970 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6971 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6974 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6975 /// blends and permutes.
6977 /// This matches the extremely common pattern for handling combined
6978 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6979 /// operations. It will try to pick the best arrangement of shuffles and
6981 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6985 SelectionDAG &DAG) {
6986 // Shuffle the input elements into the desired positions in V1 and V2 and
6987 // blend them together.
6988 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6989 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6990 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6991 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6992 if (Mask[i] >= 0 && Mask[i] < Size) {
6993 V1Mask[i] = Mask[i];
6995 } else if (Mask[i] >= Size) {
6996 V2Mask[i] = Mask[i] - Size;
6997 BlendMask[i] = i + Size;
7000 // Try to lower with the simpler initial blend strategy unless one of the
7001 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7002 // shuffle may be able to fold with a load or other benefit. However, when
7003 // we'll have to do 2x as many shuffles in order to achieve this, blending
7004 // first is a better strategy.
7005 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7006 if (SDValue BlendPerm =
7007 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7010 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7011 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7012 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7015 /// \brief Try to lower a vector shuffle as a byte rotation.
7017 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7018 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7019 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7020 /// try to generically lower a vector shuffle through such an pattern. It
7021 /// does not check for the profitability of lowering either as PALIGNR or
7022 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7023 /// This matches shuffle vectors that look like:
7025 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7027 /// Essentially it concatenates V1 and V2, shifts right by some number of
7028 /// elements, and takes the low elements as the result. Note that while this is
7029 /// specified as a *right shift* because x86 is little-endian, it is a *left
7030 /// rotate* of the vector lanes.
7031 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7034 const X86Subtarget *Subtarget,
7035 SelectionDAG &DAG) {
7036 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7038 int NumElts = Mask.size();
7039 int NumLanes = VT.getSizeInBits() / 128;
7040 int NumLaneElts = NumElts / NumLanes;
7042 // We need to detect various ways of spelling a rotation:
7043 // [11, 12, 13, 14, 15, 0, 1, 2]
7044 // [-1, 12, 13, 14, -1, -1, 1, -1]
7045 // [-1, -1, -1, -1, -1, -1, 1, 2]
7046 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7047 // [-1, 4, 5, 6, -1, -1, 9, -1]
7048 // [-1, 4, 5, 6, -1, -1, -1, -1]
7051 for (int l = 0; l < NumElts; l += NumLaneElts) {
7052 for (int i = 0; i < NumLaneElts; ++i) {
7053 if (Mask[l + i] == -1)
7055 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7057 // Get the mod-Size index and lane correct it.
7058 int LaneIdx = (Mask[l + i] % NumElts) - l;
7059 // Make sure it was in this lane.
7060 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7063 // Determine where a rotated vector would have started.
7064 int StartIdx = i - LaneIdx;
7066 // The identity rotation isn't interesting, stop.
7069 // If we found the tail of a vector the rotation must be the missing
7070 // front. If we found the head of a vector, it must be how much of the
7072 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7075 Rotation = CandidateRotation;
7076 else if (Rotation != CandidateRotation)
7077 // The rotations don't match, so we can't match this mask.
7080 // Compute which value this mask is pointing at.
7081 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7083 // Compute which of the two target values this index should be assigned
7084 // to. This reflects whether the high elements are remaining or the low
7085 // elements are remaining.
7086 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7088 // Either set up this value if we've not encountered it before, or check
7089 // that it remains consistent.
7092 else if (TargetV != MaskV)
7093 // This may be a rotation, but it pulls from the inputs in some
7094 // unsupported interleaving.
7099 // Check that we successfully analyzed the mask, and normalize the results.
7100 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7101 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7107 // The actual rotate instruction rotates bytes, so we need to scale the
7108 // rotation based on how many bytes are in the vector lane.
7109 int Scale = 16 / NumLaneElts;
7111 // SSSE3 targets can use the palignr instruction.
7112 if (Subtarget->hasSSSE3()) {
7113 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7114 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7115 Lo = DAG.getBitcast(AlignVT, Lo);
7116 Hi = DAG.getBitcast(AlignVT, Hi);
7118 return DAG.getBitcast(
7119 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7120 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7123 assert(VT.getSizeInBits() == 128 &&
7124 "Rotate-based lowering only supports 128-bit lowering!");
7125 assert(Mask.size() <= 16 &&
7126 "Can shuffle at most 16 bytes in a 128-bit vector!");
7128 // Default SSE2 implementation
7129 int LoByteShift = 16 - Rotation * Scale;
7130 int HiByteShift = Rotation * Scale;
7132 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7133 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7134 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7136 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7137 DAG.getConstant(LoByteShift, DL, MVT::i8));
7138 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7139 DAG.getConstant(HiByteShift, DL, MVT::i8));
7140 return DAG.getBitcast(VT,
7141 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7144 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7146 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7147 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7148 /// matches elements from one of the input vectors shuffled to the left or
7149 /// right with zeroable elements 'shifted in'. It handles both the strictly
7150 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7153 /// PSHL : (little-endian) left bit shift.
7154 /// [ zz, 0, zz, 2 ]
7155 /// [ -1, 4, zz, -1 ]
7156 /// PSRL : (little-endian) right bit shift.
7158 /// [ -1, -1, 7, zz]
7159 /// PSLLDQ : (little-endian) left byte shift
7160 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7161 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7162 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7163 /// PSRLDQ : (little-endian) right byte shift
7164 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7165 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7166 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7167 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7168 SDValue V2, ArrayRef<int> Mask,
7169 SelectionDAG &DAG) {
7170 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7172 int Size = Mask.size();
7173 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7175 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7176 for (int i = 0; i < Size; i += Scale)
7177 for (int j = 0; j < Shift; ++j)
7178 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7184 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7185 for (int i = 0; i != Size; i += Scale) {
7186 unsigned Pos = Left ? i + Shift : i;
7187 unsigned Low = Left ? i : i + Shift;
7188 unsigned Len = Scale - Shift;
7189 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7190 Low + (V == V1 ? 0 : Size)))
7194 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7195 bool ByteShift = ShiftEltBits > 64;
7196 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7197 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7198 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7200 // Normalize the scale for byte shifts to still produce an i64 element
7202 Scale = ByteShift ? Scale / 2 : Scale;
7204 // We need to round trip through the appropriate type for the shift.
7205 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7206 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7207 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7208 "Illegal integer vector type");
7209 V = DAG.getBitcast(ShiftVT, V);
7211 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7212 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7213 return DAG.getBitcast(VT, V);
7216 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7217 // keep doubling the size of the integer elements up to that. We can
7218 // then shift the elements of the integer vector by whole multiples of
7219 // their width within the elements of the larger integer vector. Test each
7220 // multiple to see if we can find a match with the moved element indices
7221 // and that the shifted in elements are all zeroable.
7222 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7223 for (int Shift = 1; Shift != Scale; ++Shift)
7224 for (bool Left : {true, false})
7225 if (CheckZeros(Shift, Scale, Left))
7226 for (SDValue V : {V1, V2})
7227 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7234 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7235 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7236 SDValue V2, ArrayRef<int> Mask,
7237 SelectionDAG &DAG) {
7238 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7239 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7241 int Size = Mask.size();
7242 int HalfSize = Size / 2;
7243 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7245 // Upper half must be undefined.
7246 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7249 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7250 // Remainder of lower half result is zero and upper half is all undef.
7251 auto LowerAsEXTRQ = [&]() {
7252 // Determine the extraction length from the part of the
7253 // lower half that isn't zeroable.
7255 for (; Len >= 0; --Len)
7256 if (!Zeroable[Len - 1])
7258 assert(Len > 0 && "Zeroable shuffle mask");
7260 // Attempt to match first Len sequential elements from the lower half.
7263 for (int i = 0; i != Len; ++i) {
7267 SDValue &V = (M < Size ? V1 : V2);
7270 // All mask elements must be in the lower half.
7274 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7285 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7286 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7287 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7288 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7289 DAG.getConstant(BitLen, DL, MVT::i8),
7290 DAG.getConstant(BitIdx, DL, MVT::i8));
7293 if (SDValue ExtrQ = LowerAsEXTRQ())
7296 // INSERTQ: Extract lowest Len elements from lower half of second source and
7297 // insert over first source, starting at Idx.
7298 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7299 auto LowerAsInsertQ = [&]() {
7300 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7303 // Attempt to match first source from mask before insertion point.
7304 if (isUndefInRange(Mask, 0, Idx)) {
7306 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7308 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7314 // Extend the extraction length looking to match both the insertion of
7315 // the second source and the remaining elements of the first.
7316 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7321 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7323 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7329 // Match the remaining elements of the lower half.
7330 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7332 } else if ((!Base || (Base == V1)) &&
7333 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7335 } else if ((!Base || (Base == V2)) &&
7336 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7343 // We may not have a base (first source) - this can safely be undefined.
7345 Base = DAG.getUNDEF(VT);
7347 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7348 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7349 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7350 DAG.getConstant(BitLen, DL, MVT::i8),
7351 DAG.getConstant(BitIdx, DL, MVT::i8));
7358 if (SDValue InsertQ = LowerAsInsertQ())
7364 /// \brief Lower a vector shuffle as a zero or any extension.
7366 /// Given a specific number of elements, element bit width, and extension
7367 /// stride, produce either a zero or any extension based on the available
7368 /// features of the subtarget. The extended elements are consecutive and
7369 /// begin and can start from an offseted element index in the input; to
7370 /// avoid excess shuffling the offset must either being in the bottom lane
7371 /// or at the start of a higher lane. All extended elements must be from
7373 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7374 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7375 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7376 assert(Scale > 1 && "Need a scale to extend.");
7377 int EltBits = VT.getScalarSizeInBits();
7378 int NumElements = VT.getVectorNumElements();
7379 int NumEltsPerLane = 128 / EltBits;
7380 int OffsetLane = Offset / NumEltsPerLane;
7381 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7382 "Only 8, 16, and 32 bit elements can be extended.");
7383 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7384 assert(0 <= Offset && "Extension offset must be positive.");
7385 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7386 "Extension offset must be in the first lane or start an upper lane.");
7388 // Check that an index is in same lane as the base offset.
7389 auto SafeOffset = [&](int Idx) {
7390 return OffsetLane == (Idx / NumEltsPerLane);
7393 // Shift along an input so that the offset base moves to the first element.
7394 auto ShuffleOffset = [&](SDValue V) {
7398 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7399 for (int i = 0; i * Scale < NumElements; ++i) {
7400 int SrcIdx = i + Offset;
7401 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7403 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7406 // Found a valid zext mask! Try various lowering strategies based on the
7407 // input type and available ISA extensions.
7408 if (Subtarget->hasSSE41()) {
7409 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7410 // PUNPCK will catch this in a later shuffle match.
7411 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7413 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7414 NumElements / Scale);
7415 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7416 return DAG.getBitcast(VT, InputV);
7419 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7421 // For any extends we can cheat for larger element sizes and use shuffle
7422 // instructions that can fold with a load and/or copy.
7423 if (AnyExt && EltBits == 32) {
7424 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7426 return DAG.getBitcast(
7427 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7428 DAG.getBitcast(MVT::v4i32, InputV),
7429 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7431 if (AnyExt && EltBits == 16 && Scale > 2) {
7432 int PSHUFDMask[4] = {Offset / 2, -1,
7433 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7434 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7435 DAG.getBitcast(MVT::v4i32, InputV),
7436 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7437 int PSHUFWMask[4] = {1, -1, -1, -1};
7438 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7439 return DAG.getBitcast(
7440 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7441 DAG.getBitcast(MVT::v8i16, InputV),
7442 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7445 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7447 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7448 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7449 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7451 int LoIdx = Offset * EltBits;
7452 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7453 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7454 DAG.getConstant(EltBits, DL, MVT::i8),
7455 DAG.getConstant(LoIdx, DL, MVT::i8)));
7457 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7458 !SafeOffset(Offset + 1))
7459 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7461 int HiIdx = (Offset + 1) * EltBits;
7462 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7463 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7464 DAG.getConstant(EltBits, DL, MVT::i8),
7465 DAG.getConstant(HiIdx, DL, MVT::i8)));
7466 return DAG.getNode(ISD::BITCAST, DL, VT,
7467 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7470 // If this would require more than 2 unpack instructions to expand, use
7471 // pshufb when available. We can only use more than 2 unpack instructions
7472 // when zero extending i8 elements which also makes it easier to use pshufb.
7473 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7474 assert(NumElements == 16 && "Unexpected byte vector width!");
7475 SDValue PSHUFBMask[16];
7476 for (int i = 0; i < 16; ++i) {
7477 int Idx = Offset + (i / Scale);
7478 PSHUFBMask[i] = DAG.getConstant(
7479 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7481 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7482 return DAG.getBitcast(VT,
7483 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7484 DAG.getNode(ISD::BUILD_VECTOR, DL,
7485 MVT::v16i8, PSHUFBMask)));
7488 // If we are extending from an offset, ensure we start on a boundary that
7489 // we can unpack from.
7490 int AlignToUnpack = Offset % (NumElements / Scale);
7491 if (AlignToUnpack) {
7492 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7493 for (int i = AlignToUnpack; i < NumElements; ++i)
7494 ShMask[i - AlignToUnpack] = i;
7495 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7496 Offset -= AlignToUnpack;
7499 // Otherwise emit a sequence of unpacks.
7501 unsigned UnpackLoHi = X86ISD::UNPCKL;
7502 if (Offset >= (NumElements / 2)) {
7503 UnpackLoHi = X86ISD::UNPCKH;
7504 Offset -= (NumElements / 2);
7507 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7508 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7509 : getZeroVector(InputVT, Subtarget, DAG, DL);
7510 InputV = DAG.getBitcast(InputVT, InputV);
7511 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7515 } while (Scale > 1);
7516 return DAG.getBitcast(VT, InputV);
7519 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7521 /// This routine will try to do everything in its power to cleverly lower
7522 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7523 /// check for the profitability of this lowering, it tries to aggressively
7524 /// match this pattern. It will use all of the micro-architectural details it
7525 /// can to emit an efficient lowering. It handles both blends with all-zero
7526 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7527 /// masking out later).
7529 /// The reason we have dedicated lowering for zext-style shuffles is that they
7530 /// are both incredibly common and often quite performance sensitive.
7531 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7532 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7533 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7534 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7536 int Bits = VT.getSizeInBits();
7537 int NumLanes = Bits / 128;
7538 int NumElements = VT.getVectorNumElements();
7539 int NumEltsPerLane = NumElements / NumLanes;
7540 assert(VT.getScalarSizeInBits() <= 32 &&
7541 "Exceeds 32-bit integer zero extension limit");
7542 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7544 // Define a helper function to check a particular ext-scale and lower to it if
7546 auto Lower = [&](int Scale) -> SDValue {
7551 for (int i = 0; i < NumElements; ++i) {
7554 continue; // Valid anywhere but doesn't tell us anything.
7555 if (i % Scale != 0) {
7556 // Each of the extended elements need to be zeroable.
7560 // We no longer are in the anyext case.
7565 // Each of the base elements needs to be consecutive indices into the
7566 // same input vector.
7567 SDValue V = M < NumElements ? V1 : V2;
7568 M = M % NumElements;
7571 Offset = M - (i / Scale);
7572 } else if (InputV != V)
7573 return SDValue(); // Flip-flopping inputs.
7575 // Offset must start in the lowest 128-bit lane or at the start of an
7577 // FIXME: Is it ever worth allowing a negative base offset?
7578 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7579 (Offset % NumEltsPerLane) == 0))
7582 // If we are offsetting, all referenced entries must come from the same
7584 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7587 if ((M % NumElements) != (Offset + (i / Scale)))
7588 return SDValue(); // Non-consecutive strided elements.
7592 // If we fail to find an input, we have a zero-shuffle which should always
7593 // have already been handled.
7594 // FIXME: Maybe handle this here in case during blending we end up with one?
7598 // If we are offsetting, don't extend if we only match a single input, we
7599 // can always do better by using a basic PSHUF or PUNPCK.
7600 if (Offset != 0 && Matches < 2)
7603 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7604 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7607 // The widest scale possible for extending is to a 64-bit integer.
7608 assert(Bits % 64 == 0 &&
7609 "The number of bits in a vector must be divisible by 64 on x86!");
7610 int NumExtElements = Bits / 64;
7612 // Each iteration, try extending the elements half as much, but into twice as
7614 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7615 assert(NumElements % NumExtElements == 0 &&
7616 "The input vector size must be divisible by the extended size.");
7617 if (SDValue V = Lower(NumElements / NumExtElements))
7621 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7625 // Returns one of the source operands if the shuffle can be reduced to a
7626 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7627 auto CanZExtLowHalf = [&]() {
7628 for (int i = NumElements / 2; i != NumElements; ++i)
7631 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7633 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7638 if (SDValue V = CanZExtLowHalf()) {
7639 V = DAG.getBitcast(MVT::v2i64, V);
7640 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7641 return DAG.getBitcast(VT, V);
7644 // No viable ext lowering found.
7648 /// \brief Try to get a scalar value for a specific element of a vector.
7650 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7651 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7652 SelectionDAG &DAG) {
7653 MVT VT = V.getSimpleValueType();
7654 MVT EltVT = VT.getVectorElementType();
7655 while (V.getOpcode() == ISD::BITCAST)
7656 V = V.getOperand(0);
7657 // If the bitcasts shift the element size, we can't extract an equivalent
7659 MVT NewVT = V.getSimpleValueType();
7660 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7663 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7664 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7665 // Ensure the scalar operand is the same size as the destination.
7666 // FIXME: Add support for scalar truncation where possible.
7667 SDValue S = V.getOperand(Idx);
7668 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7669 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7675 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7677 /// This is particularly important because the set of instructions varies
7678 /// significantly based on whether the operand is a load or not.
7679 static bool isShuffleFoldableLoad(SDValue V) {
7680 while (V.getOpcode() == ISD::BITCAST)
7681 V = V.getOperand(0);
7683 return ISD::isNON_EXTLoad(V.getNode());
7686 /// \brief Try to lower insertion of a single element into a zero vector.
7688 /// This is a common pattern that we have especially efficient patterns to lower
7689 /// across all subtarget feature sets.
7690 static SDValue lowerVectorShuffleAsElementInsertion(
7691 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7692 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7693 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7695 MVT EltVT = VT.getVectorElementType();
7697 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7698 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7700 bool IsV1Zeroable = true;
7701 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7702 if (i != V2Index && !Zeroable[i]) {
7703 IsV1Zeroable = false;
7707 // Check for a single input from a SCALAR_TO_VECTOR node.
7708 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7709 // all the smarts here sunk into that routine. However, the current
7710 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7711 // vector shuffle lowering is dead.
7712 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7714 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7715 // We need to zext the scalar if it is smaller than an i32.
7716 V2S = DAG.getBitcast(EltVT, V2S);
7717 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7718 // Using zext to expand a narrow element won't work for non-zero
7723 // Zero-extend directly to i32.
7725 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7727 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7728 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7729 EltVT == MVT::i16) {
7730 // Either not inserting from the low element of the input or the input
7731 // element size is too small to use VZEXT_MOVL to clear the high bits.
7735 if (!IsV1Zeroable) {
7736 // If V1 can't be treated as a zero vector we have fewer options to lower
7737 // this. We can't support integer vectors or non-zero targets cheaply, and
7738 // the V1 elements can't be permuted in any way.
7739 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7740 if (!VT.isFloatingPoint() || V2Index != 0)
7742 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7743 V1Mask[V2Index] = -1;
7744 if (!isNoopShuffleMask(V1Mask))
7746 // This is essentially a special case blend operation, but if we have
7747 // general purpose blend operations, they are always faster. Bail and let
7748 // the rest of the lowering handle these as blends.
7749 if (Subtarget->hasSSE41())
7752 // Otherwise, use MOVSD or MOVSS.
7753 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7754 "Only two types of floating point element types to handle!");
7755 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7759 // This lowering only works for the low element with floating point vectors.
7760 if (VT.isFloatingPoint() && V2Index != 0)
7763 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7765 V2 = DAG.getBitcast(VT, V2);
7768 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7769 // the desired position. Otherwise it is more efficient to do a vector
7770 // shift left. We know that we can do a vector shift left because all
7771 // the inputs are zero.
7772 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7773 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7774 V2Shuffle[V2Index] = 0;
7775 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7777 V2 = DAG.getBitcast(MVT::v2i64, V2);
7779 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7780 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7781 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7782 DAG.getDataLayout(), VT)));
7783 V2 = DAG.getBitcast(VT, V2);
7789 /// \brief Try to lower broadcast of a single element.
7791 /// For convenience, this code also bundles all of the subtarget feature set
7792 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7793 /// a convenient way to factor it out.
7794 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7796 const X86Subtarget *Subtarget,
7797 SelectionDAG &DAG) {
7798 if (!Subtarget->hasAVX())
7800 if (VT.isInteger() && !Subtarget->hasAVX2())
7803 // Check that the mask is a broadcast.
7804 int BroadcastIdx = -1;
7806 if (M >= 0 && BroadcastIdx == -1)
7808 else if (M >= 0 && M != BroadcastIdx)
7811 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7812 "a sorted mask where the broadcast "
7815 // Go up the chain of (vector) values to find a scalar load that we can
7816 // combine with the broadcast.
7818 switch (V.getOpcode()) {
7819 case ISD::CONCAT_VECTORS: {
7820 int OperandSize = Mask.size() / V.getNumOperands();
7821 V = V.getOperand(BroadcastIdx / OperandSize);
7822 BroadcastIdx %= OperandSize;
7826 case ISD::INSERT_SUBVECTOR: {
7827 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7828 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7832 int BeginIdx = (int)ConstantIdx->getZExtValue();
7834 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7835 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7836 BroadcastIdx -= BeginIdx;
7847 // Check if this is a broadcast of a scalar. We special case lowering
7848 // for scalars so that we can more effectively fold with loads.
7849 // First, look through bitcast: if the original value has a larger element
7850 // type than the shuffle, the broadcast element is in essence truncated.
7851 // Make that explicit to ease folding.
7852 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7853 EVT EltVT = VT.getVectorElementType();
7854 SDValue V0 = V.getOperand(0);
7855 EVT V0VT = V0.getValueType();
7857 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7858 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7859 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7860 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7865 // Also check the simpler case, where we can directly reuse the scalar.
7866 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7867 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7868 V = V.getOperand(BroadcastIdx);
7870 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7871 // Only AVX2 has register broadcasts.
7872 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7874 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7875 // We can't broadcast from a vector register without AVX2, and we can only
7876 // broadcast from the zero-element of a vector register.
7880 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7883 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7884 // INSERTPS when the V1 elements are already in the correct locations
7885 // because otherwise we can just always use two SHUFPS instructions which
7886 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7887 // perform INSERTPS if a single V1 element is out of place and all V2
7888 // elements are zeroable.
7889 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7891 SelectionDAG &DAG) {
7892 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7893 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7894 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7895 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7897 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7900 int V1DstIndex = -1;
7901 int V2DstIndex = -1;
7902 bool V1UsedInPlace = false;
7904 for (int i = 0; i < 4; ++i) {
7905 // Synthesize a zero mask from the zeroable elements (includes undefs).
7911 // Flag if we use any V1 inputs in place.
7913 V1UsedInPlace = true;
7917 // We can only insert a single non-zeroable element.
7918 if (V1DstIndex != -1 || V2DstIndex != -1)
7922 // V1 input out of place for insertion.
7925 // V2 input for insertion.
7930 // Don't bother if we have no (non-zeroable) element for insertion.
7931 if (V1DstIndex == -1 && V2DstIndex == -1)
7934 // Determine element insertion src/dst indices. The src index is from the
7935 // start of the inserted vector, not the start of the concatenated vector.
7936 unsigned V2SrcIndex = 0;
7937 if (V1DstIndex != -1) {
7938 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7939 // and don't use the original V2 at all.
7940 V2SrcIndex = Mask[V1DstIndex];
7941 V2DstIndex = V1DstIndex;
7944 V2SrcIndex = Mask[V2DstIndex] - 4;
7947 // If no V1 inputs are used in place, then the result is created only from
7948 // the zero mask and the V2 insertion - so remove V1 dependency.
7950 V1 = DAG.getUNDEF(MVT::v4f32);
7952 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7953 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7955 // Insert the V2 element into the desired position.
7957 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7958 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7961 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7962 /// UNPCK instruction.
7964 /// This specifically targets cases where we end up with alternating between
7965 /// the two inputs, and so can permute them into something that feeds a single
7966 /// UNPCK instruction. Note that this routine only targets integer vectors
7967 /// because for floating point vectors we have a generalized SHUFPS lowering
7968 /// strategy that handles everything that doesn't *exactly* match an unpack,
7969 /// making this clever lowering unnecessary.
7970 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
7971 SDValue V1, SDValue V2,
7973 SelectionDAG &DAG) {
7974 assert(!VT.isFloatingPoint() &&
7975 "This routine only supports integer vectors.");
7976 assert(!isSingleInputShuffleMask(Mask) &&
7977 "This routine should only be used when blending two inputs.");
7978 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7980 int Size = Mask.size();
7982 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7983 return M >= 0 && M % Size < Size / 2;
7985 int NumHiInputs = std::count_if(
7986 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7988 bool UnpackLo = NumLoInputs >= NumHiInputs;
7990 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7991 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7992 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7994 for (int i = 0; i < Size; ++i) {
7998 // Each element of the unpack contains Scale elements from this mask.
7999 int UnpackIdx = i / Scale;
8001 // We only handle the case where V1 feeds the first slots of the unpack.
8002 // We rely on canonicalization to ensure this is the case.
8003 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8006 // Setup the mask for this input. The indexing is tricky as we have to
8007 // handle the unpack stride.
8008 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8009 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8013 // If we will have to shuffle both inputs to use the unpack, check whether
8014 // we can just unpack first and shuffle the result. If so, skip this unpack.
8015 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8016 !isNoopShuffleMask(V2Mask))
8019 // Shuffle the inputs into place.
8020 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8021 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8023 // Cast the inputs to the type we will use to unpack them.
8024 V1 = DAG.getBitcast(UnpackVT, V1);
8025 V2 = DAG.getBitcast(UnpackVT, V2);
8027 // Unpack the inputs and cast the result back to the desired type.
8028 return DAG.getBitcast(
8029 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8033 // We try each unpack from the largest to the smallest to try and find one
8034 // that fits this mask.
8035 int OrigNumElements = VT.getVectorNumElements();
8036 int OrigScalarSize = VT.getScalarSizeInBits();
8037 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8038 int Scale = ScalarSize / OrigScalarSize;
8039 int NumElements = OrigNumElements / Scale;
8040 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8041 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8045 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8047 if (NumLoInputs == 0 || NumHiInputs == 0) {
8048 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8049 "We have to have *some* inputs!");
8050 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8052 // FIXME: We could consider the total complexity of the permute of each
8053 // possible unpacking. Or at the least we should consider how many
8054 // half-crossings are created.
8055 // FIXME: We could consider commuting the unpacks.
8057 SmallVector<int, 32> PermMask;
8058 PermMask.assign(Size, -1);
8059 for (int i = 0; i < Size; ++i) {
8063 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8066 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8068 return DAG.getVectorShuffle(
8069 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8071 DAG.getUNDEF(VT), PermMask);
8077 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8079 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8080 /// support for floating point shuffles but not integer shuffles. These
8081 /// instructions will incur a domain crossing penalty on some chips though so
8082 /// it is better to avoid lowering through this for integer vectors where
8084 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8085 const X86Subtarget *Subtarget,
8086 SelectionDAG &DAG) {
8088 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8089 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8090 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8092 ArrayRef<int> Mask = SVOp->getMask();
8093 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8095 if (isSingleInputShuffleMask(Mask)) {
8096 // Use low duplicate instructions for masks that match their pattern.
8097 if (Subtarget->hasSSE3())
8098 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8099 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8101 // Straight shuffle of a single input vector. Simulate this by using the
8102 // single input as both of the "inputs" to this instruction..
8103 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8105 if (Subtarget->hasAVX()) {
8106 // If we have AVX, we can use VPERMILPS which will allow folding a load
8107 // into the shuffle.
8108 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8109 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8112 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8113 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8115 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8116 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8118 // If we have a single input, insert that into V1 if we can do so cheaply.
8119 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8120 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8121 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8123 // Try inverting the insertion since for v2 masks it is easy to do and we
8124 // can't reliably sort the mask one way or the other.
8125 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8126 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8127 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8128 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8132 // Try to use one of the special instruction patterns to handle two common
8133 // blend patterns if a zero-blend above didn't work.
8134 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8135 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8136 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8137 // We can either use a special instruction to load over the low double or
8138 // to move just the low double.
8140 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8142 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8144 if (Subtarget->hasSSE41())
8145 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8149 // Use dedicated unpack instructions for masks that match their pattern.
8150 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8151 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8152 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8153 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8155 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8156 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8157 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8160 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8162 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8163 /// the integer unit to minimize domain crossing penalties. However, for blends
8164 /// it falls back to the floating point shuffle operation with appropriate bit
8166 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8167 const X86Subtarget *Subtarget,
8168 SelectionDAG &DAG) {
8170 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8171 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8172 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8173 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8174 ArrayRef<int> Mask = SVOp->getMask();
8175 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8177 if (isSingleInputShuffleMask(Mask)) {
8178 // Check for being able to broadcast a single element.
8179 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8180 Mask, Subtarget, DAG))
8183 // Straight shuffle of a single input vector. For everything from SSE2
8184 // onward this has a single fast instruction with no scary immediates.
8185 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8186 V1 = DAG.getBitcast(MVT::v4i32, V1);
8187 int WidenedMask[4] = {
8188 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8189 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8190 return DAG.getBitcast(
8192 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8193 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8195 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8196 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8197 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8198 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8200 // If we have a blend of two PACKUS operations an the blend aligns with the
8201 // low and half halves, we can just merge the PACKUS operations. This is
8202 // particularly important as it lets us merge shuffles that this routine itself
8204 auto GetPackNode = [](SDValue V) {
8205 while (V.getOpcode() == ISD::BITCAST)
8206 V = V.getOperand(0);
8208 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8210 if (SDValue V1Pack = GetPackNode(V1))
8211 if (SDValue V2Pack = GetPackNode(V2))
8212 return DAG.getBitcast(MVT::v2i64,
8213 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8214 Mask[0] == 0 ? V1Pack.getOperand(0)
8215 : V1Pack.getOperand(1),
8216 Mask[1] == 2 ? V2Pack.getOperand(0)
8217 : V2Pack.getOperand(1)));
8219 // Try to use shift instructions.
8221 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8224 // When loading a scalar and then shuffling it into a vector we can often do
8225 // the insertion cheaply.
8226 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8227 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8229 // Try inverting the insertion since for v2 masks it is easy to do and we
8230 // can't reliably sort the mask one way or the other.
8231 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8232 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8233 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8236 // We have different paths for blend lowering, but they all must use the
8237 // *exact* same predicate.
8238 bool IsBlendSupported = Subtarget->hasSSE41();
8239 if (IsBlendSupported)
8240 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8244 // Use dedicated unpack instructions for masks that match their pattern.
8245 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8246 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8247 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8248 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8250 // Try to use byte rotation instructions.
8251 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8252 if (Subtarget->hasSSSE3())
8253 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8254 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8257 // If we have direct support for blends, we should lower by decomposing into
8258 // a permute. That will be faster than the domain cross.
8259 if (IsBlendSupported)
8260 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8263 // We implement this with SHUFPD which is pretty lame because it will likely
8264 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8265 // However, all the alternatives are still more cycles and newer chips don't
8266 // have this problem. It would be really nice if x86 had better shuffles here.
8267 V1 = DAG.getBitcast(MVT::v2f64, V1);
8268 V2 = DAG.getBitcast(MVT::v2f64, V2);
8269 return DAG.getBitcast(MVT::v2i64,
8270 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8273 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8275 /// This is used to disable more specialized lowerings when the shufps lowering
8276 /// will happen to be efficient.
8277 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8278 // This routine only handles 128-bit shufps.
8279 assert(Mask.size() == 4 && "Unsupported mask size!");
8281 // To lower with a single SHUFPS we need to have the low half and high half
8282 // each requiring a single input.
8283 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8285 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8291 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8293 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8294 /// It makes no assumptions about whether this is the *best* lowering, it simply
8296 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8297 ArrayRef<int> Mask, SDValue V1,
8298 SDValue V2, SelectionDAG &DAG) {
8299 SDValue LowV = V1, HighV = V2;
8300 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8303 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8305 if (NumV2Elements == 1) {
8307 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8310 // Compute the index adjacent to V2Index and in the same half by toggling
8312 int V2AdjIndex = V2Index ^ 1;
8314 if (Mask[V2AdjIndex] == -1) {
8315 // Handles all the cases where we have a single V2 element and an undef.
8316 // This will only ever happen in the high lanes because we commute the
8317 // vector otherwise.
8319 std::swap(LowV, HighV);
8320 NewMask[V2Index] -= 4;
8322 // Handle the case where the V2 element ends up adjacent to a V1 element.
8323 // To make this work, blend them together as the first step.
8324 int V1Index = V2AdjIndex;
8325 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8326 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8327 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8329 // Now proceed to reconstruct the final blend as we have the necessary
8330 // high or low half formed.
8337 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8338 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8340 } else if (NumV2Elements == 2) {
8341 if (Mask[0] < 4 && Mask[1] < 4) {
8342 // Handle the easy case where we have V1 in the low lanes and V2 in the
8346 } else if (Mask[2] < 4 && Mask[3] < 4) {
8347 // We also handle the reversed case because this utility may get called
8348 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8349 // arrange things in the right direction.
8355 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8356 // trying to place elements directly, just blend them and set up the final
8357 // shuffle to place them.
8359 // The first two blend mask elements are for V1, the second two are for
8361 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8362 Mask[2] < 4 ? Mask[2] : Mask[3],
8363 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8364 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8365 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8366 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8368 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8371 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8372 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8373 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8374 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8377 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8378 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8381 /// \brief Lower 4-lane 32-bit floating point shuffles.
8383 /// Uses instructions exclusively from the floating point unit to minimize
8384 /// domain crossing penalties, as these are sufficient to implement all v4f32
8386 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8387 const X86Subtarget *Subtarget,
8388 SelectionDAG &DAG) {
8390 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8391 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8392 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8393 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8394 ArrayRef<int> Mask = SVOp->getMask();
8395 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8398 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8400 if (NumV2Elements == 0) {
8401 // Check for being able to broadcast a single element.
8402 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8403 Mask, Subtarget, DAG))
8406 // Use even/odd duplicate instructions for masks that match their pattern.
8407 if (Subtarget->hasSSE3()) {
8408 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8409 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8410 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8411 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8414 if (Subtarget->hasAVX()) {
8415 // If we have AVX, we can use VPERMILPS which will allow folding a load
8416 // into the shuffle.
8417 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8418 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8421 // Otherwise, use a straight shuffle of a single input vector. We pass the
8422 // input vector to both operands to simulate this with a SHUFPS.
8423 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8424 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8427 // There are special ways we can lower some single-element blends. However, we
8428 // have custom ways we can lower more complex single-element blends below that
8429 // we defer to if both this and BLENDPS fail to match, so restrict this to
8430 // when the V2 input is targeting element 0 of the mask -- that is the fast
8432 if (NumV2Elements == 1 && Mask[0] >= 4)
8433 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8434 Mask, Subtarget, DAG))
8437 if (Subtarget->hasSSE41()) {
8438 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8442 // Use INSERTPS if we can complete the shuffle efficiently.
8443 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8446 if (!isSingleSHUFPSMask(Mask))
8447 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8448 DL, MVT::v4f32, V1, V2, Mask, DAG))
8452 // Use dedicated unpack instructions for masks that match their pattern.
8453 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8454 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8455 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8456 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8457 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8458 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8459 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8460 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8462 // Otherwise fall back to a SHUFPS lowering strategy.
8463 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8466 /// \brief Lower 4-lane i32 vector shuffles.
8468 /// We try to handle these with integer-domain shuffles where we can, but for
8469 /// blends we use the floating point domain blend instructions.
8470 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8471 const X86Subtarget *Subtarget,
8472 SelectionDAG &DAG) {
8474 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8475 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8476 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8478 ArrayRef<int> Mask = SVOp->getMask();
8479 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8481 // Whenever we can lower this as a zext, that instruction is strictly faster
8482 // than any alternative. It also allows us to fold memory operands into the
8483 // shuffle in many cases.
8484 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8485 Mask, Subtarget, DAG))
8489 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8491 if (NumV2Elements == 0) {
8492 // Check for being able to broadcast a single element.
8493 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8494 Mask, Subtarget, DAG))
8497 // Straight shuffle of a single input vector. For everything from SSE2
8498 // onward this has a single fast instruction with no scary immediates.
8499 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8500 // but we aren't actually going to use the UNPCK instruction because doing
8501 // so prevents folding a load into this instruction or making a copy.
8502 const int UnpackLoMask[] = {0, 0, 1, 1};
8503 const int UnpackHiMask[] = {2, 2, 3, 3};
8504 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8505 Mask = UnpackLoMask;
8506 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8507 Mask = UnpackHiMask;
8509 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8510 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8513 // Try to use shift instructions.
8515 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8518 // There are special ways we can lower some single-element blends.
8519 if (NumV2Elements == 1)
8520 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8521 Mask, Subtarget, DAG))
8524 // We have different paths for blend lowering, but they all must use the
8525 // *exact* same predicate.
8526 bool IsBlendSupported = Subtarget->hasSSE41();
8527 if (IsBlendSupported)
8528 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8532 if (SDValue Masked =
8533 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8536 // Use dedicated unpack instructions for masks that match their pattern.
8537 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8538 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8539 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8540 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8541 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8542 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8543 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8544 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8546 // Try to use byte rotation instructions.
8547 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8548 if (Subtarget->hasSSSE3())
8549 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8550 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8553 // If we have direct support for blends, we should lower by decomposing into
8554 // a permute. That will be faster than the domain cross.
8555 if (IsBlendSupported)
8556 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8559 // Try to lower by permuting the inputs into an unpack instruction.
8560 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8564 // We implement this with SHUFPS because it can blend from two vectors.
8565 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8566 // up the inputs, bypassing domain shift penalties that we would encur if we
8567 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8569 return DAG.getBitcast(
8571 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8572 DAG.getBitcast(MVT::v4f32, V2), Mask));
8575 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8576 /// shuffle lowering, and the most complex part.
8578 /// The lowering strategy is to try to form pairs of input lanes which are
8579 /// targeted at the same half of the final vector, and then use a dword shuffle
8580 /// to place them onto the right half, and finally unpack the paired lanes into
8581 /// their final position.
8583 /// The exact breakdown of how to form these dword pairs and align them on the
8584 /// correct sides is really tricky. See the comments within the function for
8585 /// more of the details.
8587 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8588 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8589 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8590 /// vector, form the analogous 128-bit 8-element Mask.
8591 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8592 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8593 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8594 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8595 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8597 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8598 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8599 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8601 SmallVector<int, 4> LoInputs;
8602 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8603 [](int M) { return M >= 0; });
8604 std::sort(LoInputs.begin(), LoInputs.end());
8605 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8606 SmallVector<int, 4> HiInputs;
8607 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8608 [](int M) { return M >= 0; });
8609 std::sort(HiInputs.begin(), HiInputs.end());
8610 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8612 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8613 int NumHToL = LoInputs.size() - NumLToL;
8615 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8616 int NumHToH = HiInputs.size() - NumLToH;
8617 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8618 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8619 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8620 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8622 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8623 // such inputs we can swap two of the dwords across the half mark and end up
8624 // with <=2 inputs to each half in each half. Once there, we can fall through
8625 // to the generic code below. For example:
8627 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8628 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8630 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8631 // and an existing 2-into-2 on the other half. In this case we may have to
8632 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8633 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8634 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8635 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8636 // half than the one we target for fixing) will be fixed when we re-enter this
8637 // path. We will also combine away any sequence of PSHUFD instructions that
8638 // result into a single instruction. Here is an example of the tricky case:
8640 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8641 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8643 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8645 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8646 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8648 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8649 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8651 // The result is fine to be handled by the generic logic.
8652 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8653 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8654 int AOffset, int BOffset) {
8655 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8656 "Must call this with A having 3 or 1 inputs from the A half.");
8657 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8658 "Must call this with B having 1 or 3 inputs from the B half.");
8659 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8660 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8662 bool ThreeAInputs = AToAInputs.size() == 3;
8664 // Compute the index of dword with only one word among the three inputs in
8665 // a half by taking the sum of the half with three inputs and subtracting
8666 // the sum of the actual three inputs. The difference is the remaining
8669 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8670 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8671 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8672 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8673 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8674 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8675 int TripleNonInputIdx =
8676 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8677 TripleDWord = TripleNonInputIdx / 2;
8679 // We use xor with one to compute the adjacent DWord to whichever one the
8681 OneInputDWord = (OneInput / 2) ^ 1;
8683 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8684 // and BToA inputs. If there is also such a problem with the BToB and AToB
8685 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8686 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8687 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8688 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8689 // Compute how many inputs will be flipped by swapping these DWords. We
8691 // to balance this to ensure we don't form a 3-1 shuffle in the other
8693 int NumFlippedAToBInputs =
8694 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8695 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8696 int NumFlippedBToBInputs =
8697 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8698 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8699 if ((NumFlippedAToBInputs == 1 &&
8700 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8701 (NumFlippedBToBInputs == 1 &&
8702 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8703 // We choose whether to fix the A half or B half based on whether that
8704 // half has zero flipped inputs. At zero, we may not be able to fix it
8705 // with that half. We also bias towards fixing the B half because that
8706 // will more commonly be the high half, and we have to bias one way.
8707 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8708 ArrayRef<int> Inputs) {
8709 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8710 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8711 PinnedIdx ^ 1) != Inputs.end();
8712 // Determine whether the free index is in the flipped dword or the
8713 // unflipped dword based on where the pinned index is. We use this bit
8714 // in an xor to conditionally select the adjacent dword.
8715 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8716 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8717 FixFreeIdx) != Inputs.end();
8718 if (IsFixIdxInput == IsFixFreeIdxInput)
8720 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8721 FixFreeIdx) != Inputs.end();
8722 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8723 "We need to be changing the number of flipped inputs!");
8724 int PSHUFHalfMask[] = {0, 1, 2, 3};
8725 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8726 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8728 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8731 if (M != -1 && M == FixIdx)
8733 else if (M != -1 && M == FixFreeIdx)
8736 if (NumFlippedBToBInputs != 0) {
8738 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8739 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8741 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8742 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8743 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8748 int PSHUFDMask[] = {0, 1, 2, 3};
8749 PSHUFDMask[ADWord] = BDWord;
8750 PSHUFDMask[BDWord] = ADWord;
8753 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8754 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8756 // Adjust the mask to match the new locations of A and B.
8758 if (M != -1 && M/2 == ADWord)
8759 M = 2 * BDWord + M % 2;
8760 else if (M != -1 && M/2 == BDWord)
8761 M = 2 * ADWord + M % 2;
8763 // Recurse back into this routine to re-compute state now that this isn't
8764 // a 3 and 1 problem.
8765 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8768 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8769 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8770 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8771 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8773 // At this point there are at most two inputs to the low and high halves from
8774 // each half. That means the inputs can always be grouped into dwords and
8775 // those dwords can then be moved to the correct half with a dword shuffle.
8776 // We use at most one low and one high word shuffle to collect these paired
8777 // inputs into dwords, and finally a dword shuffle to place them.
8778 int PSHUFLMask[4] = {-1, -1, -1, -1};
8779 int PSHUFHMask[4] = {-1, -1, -1, -1};
8780 int PSHUFDMask[4] = {-1, -1, -1, -1};
8782 // First fix the masks for all the inputs that are staying in their
8783 // original halves. This will then dictate the targets of the cross-half
8785 auto fixInPlaceInputs =
8786 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8787 MutableArrayRef<int> SourceHalfMask,
8788 MutableArrayRef<int> HalfMask, int HalfOffset) {
8789 if (InPlaceInputs.empty())
8791 if (InPlaceInputs.size() == 1) {
8792 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8793 InPlaceInputs[0] - HalfOffset;
8794 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8797 if (IncomingInputs.empty()) {
8798 // Just fix all of the in place inputs.
8799 for (int Input : InPlaceInputs) {
8800 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8801 PSHUFDMask[Input / 2] = Input / 2;
8806 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8807 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8808 InPlaceInputs[0] - HalfOffset;
8809 // Put the second input next to the first so that they are packed into
8810 // a dword. We find the adjacent index by toggling the low bit.
8811 int AdjIndex = InPlaceInputs[0] ^ 1;
8812 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8813 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8814 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8816 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8817 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8819 // Now gather the cross-half inputs and place them into a free dword of
8820 // their target half.
8821 // FIXME: This operation could almost certainly be simplified dramatically to
8822 // look more like the 3-1 fixing operation.
8823 auto moveInputsToRightHalf = [&PSHUFDMask](
8824 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8825 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8826 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8828 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8829 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8831 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8833 int LowWord = Word & ~1;
8834 int HighWord = Word | 1;
8835 return isWordClobbered(SourceHalfMask, LowWord) ||
8836 isWordClobbered(SourceHalfMask, HighWord);
8839 if (IncomingInputs.empty())
8842 if (ExistingInputs.empty()) {
8843 // Map any dwords with inputs from them into the right half.
8844 for (int Input : IncomingInputs) {
8845 // If the source half mask maps over the inputs, turn those into
8846 // swaps and use the swapped lane.
8847 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8848 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8849 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8850 Input - SourceOffset;
8851 // We have to swap the uses in our half mask in one sweep.
8852 for (int &M : HalfMask)
8853 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8855 else if (M == Input)
8856 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8858 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8859 Input - SourceOffset &&
8860 "Previous placement doesn't match!");
8862 // Note that this correctly re-maps both when we do a swap and when
8863 // we observe the other side of the swap above. We rely on that to
8864 // avoid swapping the members of the input list directly.
8865 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8868 // Map the input's dword into the correct half.
8869 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8870 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8872 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8874 "Previous placement doesn't match!");
8877 // And just directly shift any other-half mask elements to be same-half
8878 // as we will have mirrored the dword containing the element into the
8879 // same position within that half.
8880 for (int &M : HalfMask)
8881 if (M >= SourceOffset && M < SourceOffset + 4) {
8882 M = M - SourceOffset + DestOffset;
8883 assert(M >= 0 && "This should never wrap below zero!");
8888 // Ensure we have the input in a viable dword of its current half. This
8889 // is particularly tricky because the original position may be clobbered
8890 // by inputs being moved and *staying* in that half.
8891 if (IncomingInputs.size() == 1) {
8892 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8893 int InputFixed = std::find(std::begin(SourceHalfMask),
8894 std::end(SourceHalfMask), -1) -
8895 std::begin(SourceHalfMask) + SourceOffset;
8896 SourceHalfMask[InputFixed - SourceOffset] =
8897 IncomingInputs[0] - SourceOffset;
8898 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8900 IncomingInputs[0] = InputFixed;
8902 } else if (IncomingInputs.size() == 2) {
8903 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8904 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8905 // We have two non-adjacent or clobbered inputs we need to extract from
8906 // the source half. To do this, we need to map them into some adjacent
8907 // dword slot in the source mask.
8908 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8909 IncomingInputs[1] - SourceOffset};
8911 // If there is a free slot in the source half mask adjacent to one of
8912 // the inputs, place the other input in it. We use (Index XOR 1) to
8913 // compute an adjacent index.
8914 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8915 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8916 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8917 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8918 InputsFixed[1] = InputsFixed[0] ^ 1;
8919 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8920 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8921 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8922 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8923 InputsFixed[0] = InputsFixed[1] ^ 1;
8924 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8925 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8926 // The two inputs are in the same DWord but it is clobbered and the
8927 // adjacent DWord isn't used at all. Move both inputs to the free
8929 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8930 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8931 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8932 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8934 // The only way we hit this point is if there is no clobbering
8935 // (because there are no off-half inputs to this half) and there is no
8936 // free slot adjacent to one of the inputs. In this case, we have to
8937 // swap an input with a non-input.
8938 for (int i = 0; i < 4; ++i)
8939 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8940 "We can't handle any clobbers here!");
8941 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8942 "Cannot have adjacent inputs here!");
8944 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8945 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8947 // We also have to update the final source mask in this case because
8948 // it may need to undo the above swap.
8949 for (int &M : FinalSourceHalfMask)
8950 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8951 M = InputsFixed[1] + SourceOffset;
8952 else if (M == InputsFixed[1] + SourceOffset)
8953 M = (InputsFixed[0] ^ 1) + SourceOffset;
8955 InputsFixed[1] = InputsFixed[0] ^ 1;
8958 // Point everything at the fixed inputs.
8959 for (int &M : HalfMask)
8960 if (M == IncomingInputs[0])
8961 M = InputsFixed[0] + SourceOffset;
8962 else if (M == IncomingInputs[1])
8963 M = InputsFixed[1] + SourceOffset;
8965 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8966 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8969 llvm_unreachable("Unhandled input size!");
8972 // Now hoist the DWord down to the right half.
8973 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8974 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8975 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8976 for (int &M : HalfMask)
8977 for (int Input : IncomingInputs)
8979 M = FreeDWord * 2 + Input % 2;
8981 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8982 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8983 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8984 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8986 // Now enact all the shuffles we've computed to move the inputs into their
8988 if (!isNoopShuffleMask(PSHUFLMask))
8989 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8990 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8991 if (!isNoopShuffleMask(PSHUFHMask))
8992 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8993 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8994 if (!isNoopShuffleMask(PSHUFDMask))
8997 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8998 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9000 // At this point, each half should contain all its inputs, and we can then
9001 // just shuffle them into their final position.
9002 assert(std::count_if(LoMask.begin(), LoMask.end(),
9003 [](int M) { return M >= 4; }) == 0 &&
9004 "Failed to lift all the high half inputs to the low mask!");
9005 assert(std::count_if(HiMask.begin(), HiMask.end(),
9006 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9007 "Failed to lift all the low half inputs to the high mask!");
9009 // Do a half shuffle for the low mask.
9010 if (!isNoopShuffleMask(LoMask))
9011 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9012 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9014 // Do a half shuffle with the high mask after shifting its values down.
9015 for (int &M : HiMask)
9018 if (!isNoopShuffleMask(HiMask))
9019 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9020 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9025 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9026 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9027 SDValue V2, ArrayRef<int> Mask,
9028 SelectionDAG &DAG, bool &V1InUse,
9030 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9036 int Size = Mask.size();
9037 int Scale = 16 / Size;
9038 for (int i = 0; i < 16; ++i) {
9039 if (Mask[i / Scale] == -1) {
9040 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9042 const int ZeroMask = 0x80;
9043 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9045 int V2Idx = Mask[i / Scale] < Size
9047 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9048 if (Zeroable[i / Scale])
9049 V1Idx = V2Idx = ZeroMask;
9050 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9051 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9052 V1InUse |= (ZeroMask != V1Idx);
9053 V2InUse |= (ZeroMask != V2Idx);
9058 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9059 DAG.getBitcast(MVT::v16i8, V1),
9060 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9062 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9063 DAG.getBitcast(MVT::v16i8, V2),
9064 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9066 // If we need shuffled inputs from both, blend the two.
9068 if (V1InUse && V2InUse)
9069 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9071 V = V1InUse ? V1 : V2;
9073 // Cast the result back to the correct type.
9074 return DAG.getBitcast(VT, V);
9077 /// \brief Generic lowering of 8-lane i16 shuffles.
9079 /// This handles both single-input shuffles and combined shuffle/blends with
9080 /// two inputs. The single input shuffles are immediately delegated to
9081 /// a dedicated lowering routine.
9083 /// The blends are lowered in one of three fundamental ways. If there are few
9084 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9085 /// of the input is significantly cheaper when lowered as an interleaving of
9086 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9087 /// halves of the inputs separately (making them have relatively few inputs)
9088 /// and then concatenate them.
9089 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9090 const X86Subtarget *Subtarget,
9091 SelectionDAG &DAG) {
9093 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9094 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9095 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9097 ArrayRef<int> OrigMask = SVOp->getMask();
9098 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9099 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9100 MutableArrayRef<int> Mask(MaskStorage);
9102 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9104 // Whenever we can lower this as a zext, that instruction is strictly faster
9105 // than any alternative.
9106 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9107 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9110 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9112 auto isV2 = [](int M) { return M >= 8; };
9114 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9116 if (NumV2Inputs == 0) {
9117 // Check for being able to broadcast a single element.
9118 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9119 Mask, Subtarget, DAG))
9122 // Try to use shift instructions.
9124 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9127 // Use dedicated unpack instructions for masks that match their pattern.
9128 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9129 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9130 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9131 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9133 // Try to use byte rotation instructions.
9134 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9135 Mask, Subtarget, DAG))
9138 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9142 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9143 "All single-input shuffles should be canonicalized to be V1-input "
9146 // Try to use shift instructions.
9148 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9151 // See if we can use SSE4A Extraction / Insertion.
9152 if (Subtarget->hasSSE4A())
9153 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9156 // There are special ways we can lower some single-element blends.
9157 if (NumV2Inputs == 1)
9158 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9159 Mask, Subtarget, DAG))
9162 // We have different paths for blend lowering, but they all must use the
9163 // *exact* same predicate.
9164 bool IsBlendSupported = Subtarget->hasSSE41();
9165 if (IsBlendSupported)
9166 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9170 if (SDValue Masked =
9171 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9174 // Use dedicated unpack instructions for masks that match their pattern.
9175 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9176 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9177 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9178 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9180 // Try to use byte rotation instructions.
9181 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9182 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9185 if (SDValue BitBlend =
9186 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9189 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9193 // If we can't directly blend but can use PSHUFB, that will be better as it
9194 // can both shuffle and set up the inefficient blend.
9195 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9196 bool V1InUse, V2InUse;
9197 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9201 // We can always bit-blend if we have to so the fallback strategy is to
9202 // decompose into single-input permutes and blends.
9203 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9207 /// \brief Check whether a compaction lowering can be done by dropping even
9208 /// elements and compute how many times even elements must be dropped.
9210 /// This handles shuffles which take every Nth element where N is a power of
9211 /// two. Example shuffle masks:
9213 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9214 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9215 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9216 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9217 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9218 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9220 /// Any of these lanes can of course be undef.
9222 /// This routine only supports N <= 3.
9223 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9226 /// \returns N above, or the number of times even elements must be dropped if
9227 /// there is such a number. Otherwise returns zero.
9228 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9229 // Figure out whether we're looping over two inputs or just one.
9230 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9232 // The modulus for the shuffle vector entries is based on whether this is
9233 // a single input or not.
9234 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9235 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9236 "We should only be called with masks with a power-of-2 size!");
9238 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9240 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9241 // and 2^3 simultaneously. This is because we may have ambiguity with
9242 // partially undef inputs.
9243 bool ViableForN[3] = {true, true, true};
9245 for (int i = 0, e = Mask.size(); i < e; ++i) {
9246 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9251 bool IsAnyViable = false;
9252 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9253 if (ViableForN[j]) {
9256 // The shuffle mask must be equal to (i * 2^N) % M.
9257 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9260 ViableForN[j] = false;
9262 // Early exit if we exhaust the possible powers of two.
9267 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9271 // Return 0 as there is no viable power of two.
9275 /// \brief Generic lowering of v16i8 shuffles.
9277 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9278 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9279 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9280 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9282 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9283 const X86Subtarget *Subtarget,
9284 SelectionDAG &DAG) {
9286 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9287 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9288 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9289 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9290 ArrayRef<int> Mask = SVOp->getMask();
9291 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9293 // Try to use shift instructions.
9295 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9298 // Try to use byte rotation instructions.
9299 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9300 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9303 // Try to use a zext lowering.
9304 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9305 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9308 // See if we can use SSE4A Extraction / Insertion.
9309 if (Subtarget->hasSSE4A())
9310 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9314 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9316 // For single-input shuffles, there are some nicer lowering tricks we can use.
9317 if (NumV2Elements == 0) {
9318 // Check for being able to broadcast a single element.
9319 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9320 Mask, Subtarget, DAG))
9323 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9324 // Notably, this handles splat and partial-splat shuffles more efficiently.
9325 // However, it only makes sense if the pre-duplication shuffle simplifies
9326 // things significantly. Currently, this means we need to be able to
9327 // express the pre-duplication shuffle as an i16 shuffle.
9329 // FIXME: We should check for other patterns which can be widened into an
9330 // i16 shuffle as well.
9331 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9332 for (int i = 0; i < 16; i += 2)
9333 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9338 auto tryToWidenViaDuplication = [&]() -> SDValue {
9339 if (!canWidenViaDuplication(Mask))
9341 SmallVector<int, 4> LoInputs;
9342 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9343 [](int M) { return M >= 0 && M < 8; });
9344 std::sort(LoInputs.begin(), LoInputs.end());
9345 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9347 SmallVector<int, 4> HiInputs;
9348 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9349 [](int M) { return M >= 8; });
9350 std::sort(HiInputs.begin(), HiInputs.end());
9351 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9354 bool TargetLo = LoInputs.size() >= HiInputs.size();
9355 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9356 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9358 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9359 SmallDenseMap<int, int, 8> LaneMap;
9360 for (int I : InPlaceInputs) {
9361 PreDupI16Shuffle[I/2] = I/2;
9364 int j = TargetLo ? 0 : 4, je = j + 4;
9365 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9366 // Check if j is already a shuffle of this input. This happens when
9367 // there are two adjacent bytes after we move the low one.
9368 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9369 // If we haven't yet mapped the input, search for a slot into which
9371 while (j < je && PreDupI16Shuffle[j] != -1)
9375 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9378 // Map this input with the i16 shuffle.
9379 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9382 // Update the lane map based on the mapping we ended up with.
9383 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9385 V1 = DAG.getBitcast(
9387 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9388 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9390 // Unpack the bytes to form the i16s that will be shuffled into place.
9391 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9392 MVT::v16i8, V1, V1);
9394 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9395 for (int i = 0; i < 16; ++i)
9396 if (Mask[i] != -1) {
9397 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9398 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9399 if (PostDupI16Shuffle[i / 2] == -1)
9400 PostDupI16Shuffle[i / 2] = MappedMask;
9402 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9403 "Conflicting entrties in the original shuffle!");
9405 return DAG.getBitcast(
9407 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9408 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9410 if (SDValue V = tryToWidenViaDuplication())
9414 if (SDValue Masked =
9415 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9418 // Use dedicated unpack instructions for masks that match their pattern.
9419 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9420 0, 16, 1, 17, 2, 18, 3, 19,
9422 4, 20, 5, 21, 6, 22, 7, 23}))
9423 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9424 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9425 8, 24, 9, 25, 10, 26, 11, 27,
9427 12, 28, 13, 29, 14, 30, 15, 31}))
9428 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9430 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9431 // with PSHUFB. It is important to do this before we attempt to generate any
9432 // blends but after all of the single-input lowerings. If the single input
9433 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9434 // want to preserve that and we can DAG combine any longer sequences into
9435 // a PSHUFB in the end. But once we start blending from multiple inputs,
9436 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9437 // and there are *very* few patterns that would actually be faster than the
9438 // PSHUFB approach because of its ability to zero lanes.
9440 // FIXME: The only exceptions to the above are blends which are exact
9441 // interleavings with direct instructions supporting them. We currently don't
9442 // handle those well here.
9443 if (Subtarget->hasSSSE3()) {
9444 bool V1InUse = false;
9445 bool V2InUse = false;
9447 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9448 DAG, V1InUse, V2InUse);
9450 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9451 // do so. This avoids using them to handle blends-with-zero which is
9452 // important as a single pshufb is significantly faster for that.
9453 if (V1InUse && V2InUse) {
9454 if (Subtarget->hasSSE41())
9455 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9456 Mask, Subtarget, DAG))
9459 // We can use an unpack to do the blending rather than an or in some
9460 // cases. Even though the or may be (very minorly) more efficient, we
9461 // preference this lowering because there are common cases where part of
9462 // the complexity of the shuffles goes away when we do the final blend as
9464 // FIXME: It might be worth trying to detect if the unpack-feeding
9465 // shuffles will both be pshufb, in which case we shouldn't bother with
9467 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9468 DL, MVT::v16i8, V1, V2, Mask, DAG))
9475 // There are special ways we can lower some single-element blends.
9476 if (NumV2Elements == 1)
9477 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9478 Mask, Subtarget, DAG))
9481 if (SDValue BitBlend =
9482 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9485 // Check whether a compaction lowering can be done. This handles shuffles
9486 // which take every Nth element for some even N. See the helper function for
9489 // We special case these as they can be particularly efficiently handled with
9490 // the PACKUSB instruction on x86 and they show up in common patterns of
9491 // rearranging bytes to truncate wide elements.
9492 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9493 // NumEvenDrops is the power of two stride of the elements. Another way of
9494 // thinking about it is that we need to drop the even elements this many
9495 // times to get the original input.
9496 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9498 // First we need to zero all the dropped bytes.
9499 assert(NumEvenDrops <= 3 &&
9500 "No support for dropping even elements more than 3 times.");
9501 // We use the mask type to pick which bytes are preserved based on how many
9502 // elements are dropped.
9503 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9504 SDValue ByteClearMask = DAG.getBitcast(
9505 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9506 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9508 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9510 // Now pack things back together.
9511 V1 = DAG.getBitcast(MVT::v8i16, V1);
9512 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9513 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9514 for (int i = 1; i < NumEvenDrops; ++i) {
9515 Result = DAG.getBitcast(MVT::v8i16, Result);
9516 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9522 // Handle multi-input cases by blending single-input shuffles.
9523 if (NumV2Elements > 0)
9524 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9527 // The fallback path for single-input shuffles widens this into two v8i16
9528 // vectors with unpacks, shuffles those, and then pulls them back together
9532 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9533 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9534 for (int i = 0; i < 16; ++i)
9536 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9538 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9540 SDValue VLoHalf, VHiHalf;
9541 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9542 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9544 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9545 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9546 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9547 [](int M) { return M >= 0 && M % 2 == 1; })) {
9548 // Use a mask to drop the high bytes.
9549 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9550 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9551 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9553 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9554 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9556 // Squash the masks to point directly into VLoHalf.
9557 for (int &M : LoBlendMask)
9560 for (int &M : HiBlendMask)
9564 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9565 // VHiHalf so that we can blend them as i16s.
9566 VLoHalf = DAG.getBitcast(
9567 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9568 VHiHalf = DAG.getBitcast(
9569 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9572 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9573 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9575 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9578 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9580 /// This routine breaks down the specific type of 128-bit shuffle and
9581 /// dispatches to the lowering routines accordingly.
9582 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9583 MVT VT, const X86Subtarget *Subtarget,
9584 SelectionDAG &DAG) {
9585 switch (VT.SimpleTy) {
9587 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9589 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9591 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9593 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9595 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9597 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9600 llvm_unreachable("Unimplemented!");
9604 /// \brief Helper function to test whether a shuffle mask could be
9605 /// simplified by widening the elements being shuffled.
9607 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9608 /// leaves it in an unspecified state.
9610 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9611 /// shuffle masks. The latter have the special property of a '-2' representing
9612 /// a zero-ed lane of a vector.
9613 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9614 SmallVectorImpl<int> &WidenedMask) {
9615 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9616 // If both elements are undef, its trivial.
9617 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9618 WidenedMask.push_back(SM_SentinelUndef);
9622 // Check for an undef mask and a mask value properly aligned to fit with
9623 // a pair of values. If we find such a case, use the non-undef mask's value.
9624 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9625 WidenedMask.push_back(Mask[i + 1] / 2);
9628 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9629 WidenedMask.push_back(Mask[i] / 2);
9633 // When zeroing, we need to spread the zeroing across both lanes to widen.
9634 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9635 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9636 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9637 WidenedMask.push_back(SM_SentinelZero);
9643 // Finally check if the two mask values are adjacent and aligned with
9645 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9646 WidenedMask.push_back(Mask[i] / 2);
9650 // Otherwise we can't safely widen the elements used in this shuffle.
9653 assert(WidenedMask.size() == Mask.size() / 2 &&
9654 "Incorrect size of mask after widening the elements!");
9659 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9661 /// This routine just extracts two subvectors, shuffles them independently, and
9662 /// then concatenates them back together. This should work effectively with all
9663 /// AVX vector shuffle types.
9664 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9665 SDValue V2, ArrayRef<int> Mask,
9666 SelectionDAG &DAG) {
9667 assert(VT.getSizeInBits() >= 256 &&
9668 "Only for 256-bit or wider vector shuffles!");
9669 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9670 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9672 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9673 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9675 int NumElements = VT.getVectorNumElements();
9676 int SplitNumElements = NumElements / 2;
9677 MVT ScalarVT = VT.getScalarType();
9678 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9680 // Rather than splitting build-vectors, just build two narrower build
9681 // vectors. This helps shuffling with splats and zeros.
9682 auto SplitVector = [&](SDValue V) {
9683 while (V.getOpcode() == ISD::BITCAST)
9684 V = V->getOperand(0);
9686 MVT OrigVT = V.getSimpleValueType();
9687 int OrigNumElements = OrigVT.getVectorNumElements();
9688 int OrigSplitNumElements = OrigNumElements / 2;
9689 MVT OrigScalarVT = OrigVT.getScalarType();
9690 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9694 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9696 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9697 DAG.getIntPtrConstant(0, DL));
9698 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9699 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9702 SmallVector<SDValue, 16> LoOps, HiOps;
9703 for (int i = 0; i < OrigSplitNumElements; ++i) {
9704 LoOps.push_back(BV->getOperand(i));
9705 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9707 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9708 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9710 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9711 DAG.getBitcast(SplitVT, HiV));
9714 SDValue LoV1, HiV1, LoV2, HiV2;
9715 std::tie(LoV1, HiV1) = SplitVector(V1);
9716 std::tie(LoV2, HiV2) = SplitVector(V2);
9718 // Now create two 4-way blends of these half-width vectors.
9719 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9720 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9721 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9722 for (int i = 0; i < SplitNumElements; ++i) {
9723 int M = HalfMask[i];
9724 if (M >= NumElements) {
9725 if (M >= NumElements + SplitNumElements)
9729 V2BlendMask.push_back(M - NumElements);
9730 V1BlendMask.push_back(-1);
9731 BlendMask.push_back(SplitNumElements + i);
9732 } else if (M >= 0) {
9733 if (M >= SplitNumElements)
9737 V2BlendMask.push_back(-1);
9738 V1BlendMask.push_back(M);
9739 BlendMask.push_back(i);
9741 V2BlendMask.push_back(-1);
9742 V1BlendMask.push_back(-1);
9743 BlendMask.push_back(-1);
9747 // Because the lowering happens after all combining takes place, we need to
9748 // manually combine these blend masks as much as possible so that we create
9749 // a minimal number of high-level vector shuffle nodes.
9751 // First try just blending the halves of V1 or V2.
9752 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9753 return DAG.getUNDEF(SplitVT);
9754 if (!UseLoV2 && !UseHiV2)
9755 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9756 if (!UseLoV1 && !UseHiV1)
9757 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9759 SDValue V1Blend, V2Blend;
9760 if (UseLoV1 && UseHiV1) {
9762 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9764 // We only use half of V1 so map the usage down into the final blend mask.
9765 V1Blend = UseLoV1 ? LoV1 : HiV1;
9766 for (int i = 0; i < SplitNumElements; ++i)
9767 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9768 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9770 if (UseLoV2 && UseHiV2) {
9772 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9774 // We only use half of V2 so map the usage down into the final blend mask.
9775 V2Blend = UseLoV2 ? LoV2 : HiV2;
9776 for (int i = 0; i < SplitNumElements; ++i)
9777 if (BlendMask[i] >= SplitNumElements)
9778 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9780 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9782 SDValue Lo = HalfBlend(LoMask);
9783 SDValue Hi = HalfBlend(HiMask);
9784 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9787 /// \brief Either split a vector in halves or decompose the shuffles and the
9790 /// This is provided as a good fallback for many lowerings of non-single-input
9791 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9792 /// between splitting the shuffle into 128-bit components and stitching those
9793 /// back together vs. extracting the single-input shuffles and blending those
9795 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9796 SDValue V2, ArrayRef<int> Mask,
9797 SelectionDAG &DAG) {
9798 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9799 "lower single-input shuffles as it "
9800 "could then recurse on itself.");
9801 int Size = Mask.size();
9803 // If this can be modeled as a broadcast of two elements followed by a blend,
9804 // prefer that lowering. This is especially important because broadcasts can
9805 // often fold with memory operands.
9806 auto DoBothBroadcast = [&] {
9807 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9810 if (V2BroadcastIdx == -1)
9811 V2BroadcastIdx = M - Size;
9812 else if (M - Size != V2BroadcastIdx)
9814 } else if (M >= 0) {
9815 if (V1BroadcastIdx == -1)
9817 else if (M != V1BroadcastIdx)
9822 if (DoBothBroadcast())
9823 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9826 // If the inputs all stem from a single 128-bit lane of each input, then we
9827 // split them rather than blending because the split will decompose to
9828 // unusually few instructions.
9829 int LaneCount = VT.getSizeInBits() / 128;
9830 int LaneSize = Size / LaneCount;
9831 SmallBitVector LaneInputs[2];
9832 LaneInputs[0].resize(LaneCount, false);
9833 LaneInputs[1].resize(LaneCount, false);
9834 for (int i = 0; i < Size; ++i)
9836 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9837 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9838 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9840 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9841 // that the decomposed single-input shuffles don't end up here.
9842 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9845 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9846 /// a permutation and blend of those lanes.
9848 /// This essentially blends the out-of-lane inputs to each lane into the lane
9849 /// from a permuted copy of the vector. This lowering strategy results in four
9850 /// instructions in the worst case for a single-input cross lane shuffle which
9851 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9852 /// of. Special cases for each particular shuffle pattern should be handled
9853 /// prior to trying this lowering.
9854 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9855 SDValue V1, SDValue V2,
9857 SelectionDAG &DAG) {
9858 // FIXME: This should probably be generalized for 512-bit vectors as well.
9859 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9860 int LaneSize = Mask.size() / 2;
9862 // If there are only inputs from one 128-bit lane, splitting will in fact be
9863 // less expensive. The flags track whether the given lane contains an element
9864 // that crosses to another lane.
9865 bool LaneCrossing[2] = {false, false};
9866 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9867 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9868 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9869 if (!LaneCrossing[0] || !LaneCrossing[1])
9870 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9872 if (isSingleInputShuffleMask(Mask)) {
9873 SmallVector<int, 32> FlippedBlendMask;
9874 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9875 FlippedBlendMask.push_back(
9876 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9878 : Mask[i] % LaneSize +
9879 (i / LaneSize) * LaneSize + Size));
9881 // Flip the vector, and blend the results which should now be in-lane. The
9882 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9883 // 5 for the high source. The value 3 selects the high half of source 2 and
9884 // the value 2 selects the low half of source 2. We only use source 2 to
9885 // allow folding it into a memory operand.
9886 unsigned PERMMask = 3 | 2 << 4;
9887 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9888 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9889 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9892 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9893 // will be handled by the above logic and a blend of the results, much like
9894 // other patterns in AVX.
9895 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9898 /// \brief Handle lowering 2-lane 128-bit shuffles.
9899 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9900 SDValue V2, ArrayRef<int> Mask,
9901 const X86Subtarget *Subtarget,
9902 SelectionDAG &DAG) {
9903 // TODO: If minimizing size and one of the inputs is a zero vector and the
9904 // the zero vector has only one use, we could use a VPERM2X128 to save the
9905 // instruction bytes needed to explicitly generate the zero vector.
9907 // Blends are faster and handle all the non-lane-crossing cases.
9908 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9912 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9913 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9915 // If either input operand is a zero vector, use VPERM2X128 because its mask
9916 // allows us to replace the zero input with an implicit zero.
9917 if (!IsV1Zero && !IsV2Zero) {
9918 // Check for patterns which can be matched with a single insert of a 128-bit
9920 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9921 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9922 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9923 VT.getVectorNumElements() / 2);
9924 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9925 DAG.getIntPtrConstant(0, DL));
9926 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9927 OnlyUsesV1 ? V1 : V2,
9928 DAG.getIntPtrConstant(0, DL));
9929 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9933 // Otherwise form a 128-bit permutation. After accounting for undefs,
9934 // convert the 64-bit shuffle mask selection values into 128-bit
9935 // selection bits by dividing the indexes by 2 and shifting into positions
9936 // defined by a vperm2*128 instruction's immediate control byte.
9938 // The immediate permute control byte looks like this:
9939 // [1:0] - select 128 bits from sources for low half of destination
9941 // [3] - zero low half of destination
9942 // [5:4] - select 128 bits from sources for high half of destination
9944 // [7] - zero high half of destination
9946 int MaskLO = Mask[0];
9947 if (MaskLO == SM_SentinelUndef)
9948 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9950 int MaskHI = Mask[2];
9951 if (MaskHI == SM_SentinelUndef)
9952 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9954 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9956 // If either input is a zero vector, replace it with an undef input.
9957 // Shuffle mask values < 4 are selecting elements of V1.
9958 // Shuffle mask values >= 4 are selecting elements of V2.
9959 // Adjust each half of the permute mask by clearing the half that was
9960 // selecting the zero vector and setting the zero mask bit.
9962 V1 = DAG.getUNDEF(VT);
9964 PermMask = (PermMask & 0xf0) | 0x08;
9966 PermMask = (PermMask & 0x0f) | 0x80;
9969 V2 = DAG.getUNDEF(VT);
9971 PermMask = (PermMask & 0xf0) | 0x08;
9973 PermMask = (PermMask & 0x0f) | 0x80;
9976 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9977 DAG.getConstant(PermMask, DL, MVT::i8));
9980 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9981 /// shuffling each lane.
9983 /// This will only succeed when the result of fixing the 128-bit lanes results
9984 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9985 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9986 /// the lane crosses early and then use simpler shuffles within each lane.
9988 /// FIXME: It might be worthwhile at some point to support this without
9989 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9990 /// in x86 only floating point has interesting non-repeating shuffles, and even
9991 /// those are still *marginally* more expensive.
9992 static SDValue lowerVectorShuffleByMerging128BitLanes(
9993 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9994 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9995 assert(!isSingleInputShuffleMask(Mask) &&
9996 "This is only useful with multiple inputs.");
9998 int Size = Mask.size();
9999 int LaneSize = 128 / VT.getScalarSizeInBits();
10000 int NumLanes = Size / LaneSize;
10001 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10003 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10004 // check whether the in-128-bit lane shuffles share a repeating pattern.
10005 SmallVector<int, 4> Lanes;
10006 Lanes.resize(NumLanes, -1);
10007 SmallVector<int, 4> InLaneMask;
10008 InLaneMask.resize(LaneSize, -1);
10009 for (int i = 0; i < Size; ++i) {
10013 int j = i / LaneSize;
10015 if (Lanes[j] < 0) {
10016 // First entry we've seen for this lane.
10017 Lanes[j] = Mask[i] / LaneSize;
10018 } else if (Lanes[j] != Mask[i] / LaneSize) {
10019 // This doesn't match the lane selected previously!
10023 // Check that within each lane we have a consistent shuffle mask.
10024 int k = i % LaneSize;
10025 if (InLaneMask[k] < 0) {
10026 InLaneMask[k] = Mask[i] % LaneSize;
10027 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10028 // This doesn't fit a repeating in-lane mask.
10033 // First shuffle the lanes into place.
10034 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10035 VT.getSizeInBits() / 64);
10036 SmallVector<int, 8> LaneMask;
10037 LaneMask.resize(NumLanes * 2, -1);
10038 for (int i = 0; i < NumLanes; ++i)
10039 if (Lanes[i] >= 0) {
10040 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10041 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10044 V1 = DAG.getBitcast(LaneVT, V1);
10045 V2 = DAG.getBitcast(LaneVT, V2);
10046 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10048 // Cast it back to the type we actually want.
10049 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10051 // Now do a simple shuffle that isn't lane crossing.
10052 SmallVector<int, 8> NewMask;
10053 NewMask.resize(Size, -1);
10054 for (int i = 0; i < Size; ++i)
10056 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10057 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10058 "Must not introduce lane crosses at this point!");
10060 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10063 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10066 /// This returns true if the elements from a particular input are already in the
10067 /// slot required by the given mask and require no permutation.
10068 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10069 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10070 int Size = Mask.size();
10071 for (int i = 0; i < Size; ++i)
10072 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10078 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10079 ArrayRef<int> Mask, SDValue V1,
10080 SDValue V2, SelectionDAG &DAG) {
10082 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10083 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10084 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10085 int NumElts = VT.getVectorNumElements();
10086 bool ShufpdMask = true;
10087 bool CommutableMask = true;
10088 unsigned Immediate = 0;
10089 for (int i = 0; i < NumElts; ++i) {
10092 int Val = (i & 6) + NumElts * (i & 1);
10093 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10094 if (Mask[i] < Val || Mask[i] > Val + 1)
10095 ShufpdMask = false;
10096 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10097 CommutableMask = false;
10098 Immediate |= (Mask[i] % 2) << i;
10101 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10102 DAG.getConstant(Immediate, DL, MVT::i8));
10103 if (CommutableMask)
10104 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10105 DAG.getConstant(Immediate, DL, MVT::i8));
10109 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10111 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10112 /// isn't available.
10113 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10114 const X86Subtarget *Subtarget,
10115 SelectionDAG &DAG) {
10117 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10118 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10119 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10120 ArrayRef<int> Mask = SVOp->getMask();
10121 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10123 SmallVector<int, 4> WidenedMask;
10124 if (canWidenShuffleElements(Mask, WidenedMask))
10125 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10128 if (isSingleInputShuffleMask(Mask)) {
10129 // Check for being able to broadcast a single element.
10130 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10131 Mask, Subtarget, DAG))
10134 // Use low duplicate instructions for masks that match their pattern.
10135 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10136 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10138 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10139 // Non-half-crossing single input shuffles can be lowerid with an
10140 // interleaved permutation.
10141 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10142 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10143 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10144 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10147 // With AVX2 we have direct support for this permutation.
10148 if (Subtarget->hasAVX2())
10149 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10150 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10152 // Otherwise, fall back.
10153 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10157 // X86 has dedicated unpack instructions that can handle specific blend
10158 // operations: UNPCKH and UNPCKL.
10159 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10160 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10161 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10162 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10163 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10164 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10165 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10166 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10168 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10172 // Check if the blend happens to exactly fit that of SHUFPD.
10174 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10177 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10178 // shuffle. However, if we have AVX2 and either inputs are already in place,
10179 // we will be able to shuffle even across lanes the other input in a single
10180 // instruction so skip this pattern.
10181 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10182 isShuffleMaskInputInPlace(1, Mask))))
10183 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10184 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10187 // If we have AVX2 then we always want to lower with a blend because an v4 we
10188 // can fully permute the elements.
10189 if (Subtarget->hasAVX2())
10190 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10193 // Otherwise fall back on generic lowering.
10194 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10197 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10199 /// This routine is only called when we have AVX2 and thus a reasonable
10200 /// instruction set for v4i64 shuffling..
10201 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10202 const X86Subtarget *Subtarget,
10203 SelectionDAG &DAG) {
10205 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10206 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10207 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10208 ArrayRef<int> Mask = SVOp->getMask();
10209 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10210 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10212 SmallVector<int, 4> WidenedMask;
10213 if (canWidenShuffleElements(Mask, WidenedMask))
10214 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10217 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10221 // Check for being able to broadcast a single element.
10222 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10223 Mask, Subtarget, DAG))
10226 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10227 // use lower latency instructions that will operate on both 128-bit lanes.
10228 SmallVector<int, 2> RepeatedMask;
10229 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10230 if (isSingleInputShuffleMask(Mask)) {
10231 int PSHUFDMask[] = {-1, -1, -1, -1};
10232 for (int i = 0; i < 2; ++i)
10233 if (RepeatedMask[i] >= 0) {
10234 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10235 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10237 return DAG.getBitcast(
10239 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10240 DAG.getBitcast(MVT::v8i32, V1),
10241 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10245 // AVX2 provides a direct instruction for permuting a single input across
10247 if (isSingleInputShuffleMask(Mask))
10248 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10249 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10251 // Try to use shift instructions.
10252 if (SDValue Shift =
10253 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10256 // Use dedicated unpack instructions for masks that match their pattern.
10257 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10258 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10259 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10260 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10261 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10262 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10263 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10264 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10266 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10267 // shuffle. However, if we have AVX2 and either inputs are already in place,
10268 // we will be able to shuffle even across lanes the other input in a single
10269 // instruction so skip this pattern.
10270 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10271 isShuffleMaskInputInPlace(1, Mask))))
10272 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10273 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10276 // Otherwise fall back on generic blend lowering.
10277 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10281 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10283 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10284 /// isn't available.
10285 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10286 const X86Subtarget *Subtarget,
10287 SelectionDAG &DAG) {
10289 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10290 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10291 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10292 ArrayRef<int> Mask = SVOp->getMask();
10293 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10295 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10299 // Check for being able to broadcast a single element.
10300 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10301 Mask, Subtarget, DAG))
10304 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10305 // options to efficiently lower the shuffle.
10306 SmallVector<int, 4> RepeatedMask;
10307 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10308 assert(RepeatedMask.size() == 4 &&
10309 "Repeated masks must be half the mask width!");
10311 // Use even/odd duplicate instructions for masks that match their pattern.
10312 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10313 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10314 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10315 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10317 if (isSingleInputShuffleMask(Mask))
10318 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10319 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10321 // Use dedicated unpack instructions for masks that match their pattern.
10322 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10323 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10324 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10325 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10326 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10327 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10328 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10329 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10331 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10332 // have already handled any direct blends. We also need to squash the
10333 // repeated mask into a simulated v4f32 mask.
10334 for (int i = 0; i < 4; ++i)
10335 if (RepeatedMask[i] >= 8)
10336 RepeatedMask[i] -= 4;
10337 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10340 // If we have a single input shuffle with different shuffle patterns in the
10341 // two 128-bit lanes use the variable mask to VPERMILPS.
10342 if (isSingleInputShuffleMask(Mask)) {
10343 SDValue VPermMask[8];
10344 for (int i = 0; i < 8; ++i)
10345 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10346 : DAG.getConstant(Mask[i], DL, MVT::i32);
10347 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10348 return DAG.getNode(
10349 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10350 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10352 if (Subtarget->hasAVX2())
10353 return DAG.getNode(
10354 X86ISD::VPERMV, DL, MVT::v8f32,
10355 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10356 MVT::v8i32, VPermMask)),
10359 // Otherwise, fall back.
10360 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10364 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10366 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10367 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10370 // If we have AVX2 then we always want to lower with a blend because at v8 we
10371 // can fully permute the elements.
10372 if (Subtarget->hasAVX2())
10373 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10376 // Otherwise fall back on generic lowering.
10377 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10380 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10382 /// This routine is only called when we have AVX2 and thus a reasonable
10383 /// instruction set for v8i32 shuffling..
10384 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10385 const X86Subtarget *Subtarget,
10386 SelectionDAG &DAG) {
10388 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10389 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10391 ArrayRef<int> Mask = SVOp->getMask();
10392 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10393 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10395 // Whenever we can lower this as a zext, that instruction is strictly faster
10396 // than any alternative. It also allows us to fold memory operands into the
10397 // shuffle in many cases.
10398 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10399 Mask, Subtarget, DAG))
10402 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10406 // Check for being able to broadcast a single element.
10407 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10408 Mask, Subtarget, DAG))
10411 // If the shuffle mask is repeated in each 128-bit lane we can use more
10412 // efficient instructions that mirror the shuffles across the two 128-bit
10414 SmallVector<int, 4> RepeatedMask;
10415 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10416 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10417 if (isSingleInputShuffleMask(Mask))
10418 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10419 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10421 // Use dedicated unpack instructions for masks that match their pattern.
10422 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10423 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10424 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10425 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10426 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10427 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10428 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10429 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10432 // Try to use shift instructions.
10433 if (SDValue Shift =
10434 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10437 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10438 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10441 // If the shuffle patterns aren't repeated but it is a single input, directly
10442 // generate a cross-lane VPERMD instruction.
10443 if (isSingleInputShuffleMask(Mask)) {
10444 SDValue VPermMask[8];
10445 for (int i = 0; i < 8; ++i)
10446 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10447 : DAG.getConstant(Mask[i], DL, MVT::i32);
10448 return DAG.getNode(
10449 X86ISD::VPERMV, DL, MVT::v8i32,
10450 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10453 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10455 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10456 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10459 // Otherwise fall back on generic blend lowering.
10460 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10464 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10466 /// This routine is only called when we have AVX2 and thus a reasonable
10467 /// instruction set for v16i16 shuffling..
10468 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10469 const X86Subtarget *Subtarget,
10470 SelectionDAG &DAG) {
10472 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10473 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10474 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10475 ArrayRef<int> Mask = SVOp->getMask();
10476 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10477 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10479 // Whenever we can lower this as a zext, that instruction is strictly faster
10480 // than any alternative. It also allows us to fold memory operands into the
10481 // shuffle in many cases.
10482 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10483 Mask, Subtarget, DAG))
10486 // Check for being able to broadcast a single element.
10487 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10488 Mask, Subtarget, DAG))
10491 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10495 // Use dedicated unpack instructions for masks that match their pattern.
10496 if (isShuffleEquivalent(V1, V2, Mask,
10497 {// First 128-bit lane:
10498 0, 16, 1, 17, 2, 18, 3, 19,
10499 // Second 128-bit lane:
10500 8, 24, 9, 25, 10, 26, 11, 27}))
10501 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10502 if (isShuffleEquivalent(V1, V2, Mask,
10503 {// First 128-bit lane:
10504 4, 20, 5, 21, 6, 22, 7, 23,
10505 // Second 128-bit lane:
10506 12, 28, 13, 29, 14, 30, 15, 31}))
10507 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10509 // Try to use shift instructions.
10510 if (SDValue Shift =
10511 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10514 // Try to use byte rotation instructions.
10515 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10516 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10519 if (isSingleInputShuffleMask(Mask)) {
10520 // There are no generalized cross-lane shuffle operations available on i16
10522 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10523 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10526 SmallVector<int, 8> RepeatedMask;
10527 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10528 // As this is a single-input shuffle, the repeated mask should be
10529 // a strictly valid v8i16 mask that we can pass through to the v8i16
10530 // lowering to handle even the v16 case.
10531 return lowerV8I16GeneralSingleInputVectorShuffle(
10532 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10535 SDValue PSHUFBMask[32];
10536 for (int i = 0; i < 16; ++i) {
10537 if (Mask[i] == -1) {
10538 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10542 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10543 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10544 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10545 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10547 return DAG.getBitcast(MVT::v16i16,
10548 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10549 DAG.getBitcast(MVT::v32i8, V1),
10550 DAG.getNode(ISD::BUILD_VECTOR, DL,
10551 MVT::v32i8, PSHUFBMask)));
10554 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10556 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10557 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10560 // Otherwise fall back on generic lowering.
10561 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10564 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10566 /// This routine is only called when we have AVX2 and thus a reasonable
10567 /// instruction set for v32i8 shuffling..
10568 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10569 const X86Subtarget *Subtarget,
10570 SelectionDAG &DAG) {
10572 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10573 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10574 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10575 ArrayRef<int> Mask = SVOp->getMask();
10576 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10577 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10579 // Whenever we can lower this as a zext, that instruction is strictly faster
10580 // than any alternative. It also allows us to fold memory operands into the
10581 // shuffle in many cases.
10582 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10583 Mask, Subtarget, DAG))
10586 // Check for being able to broadcast a single element.
10587 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10588 Mask, Subtarget, DAG))
10591 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10595 // Use dedicated unpack instructions for masks that match their pattern.
10596 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10598 if (isShuffleEquivalent(
10600 {// First 128-bit lane:
10601 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10602 // Second 128-bit lane:
10603 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10604 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10605 if (isShuffleEquivalent(
10607 {// First 128-bit lane:
10608 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10609 // Second 128-bit lane:
10610 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10611 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10613 // Try to use shift instructions.
10614 if (SDValue Shift =
10615 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10618 // Try to use byte rotation instructions.
10619 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10620 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10623 if (isSingleInputShuffleMask(Mask)) {
10624 // There are no generalized cross-lane shuffle operations available on i8
10626 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10627 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10630 SDValue PSHUFBMask[32];
10631 for (int i = 0; i < 32; ++i)
10634 ? DAG.getUNDEF(MVT::i8)
10635 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10638 return DAG.getNode(
10639 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10640 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10643 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10645 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10646 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10649 // Otherwise fall back on generic lowering.
10650 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10653 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10655 /// This routine either breaks down the specific type of a 256-bit x86 vector
10656 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10657 /// together based on the available instructions.
10658 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10659 MVT VT, const X86Subtarget *Subtarget,
10660 SelectionDAG &DAG) {
10662 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10663 ArrayRef<int> Mask = SVOp->getMask();
10665 // If we have a single input to the zero element, insert that into V1 if we
10666 // can do so cheaply.
10667 int NumElts = VT.getVectorNumElements();
10668 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10669 return M >= NumElts;
10672 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10673 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10674 DL, VT, V1, V2, Mask, Subtarget, DAG))
10677 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10678 // can check for those subtargets here and avoid much of the subtarget
10679 // querying in the per-vector-type lowering routines. With AVX1 we have
10680 // essentially *zero* ability to manipulate a 256-bit vector with integer
10681 // types. Since we'll use floating point types there eventually, just
10682 // immediately cast everything to a float and operate entirely in that domain.
10683 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10684 int ElementBits = VT.getScalarSizeInBits();
10685 if (ElementBits < 32)
10686 // No floating point type available, decompose into 128-bit vectors.
10687 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10689 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10690 VT.getVectorNumElements());
10691 V1 = DAG.getBitcast(FpVT, V1);
10692 V2 = DAG.getBitcast(FpVT, V2);
10693 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10696 switch (VT.SimpleTy) {
10698 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10700 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10702 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10704 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10706 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10708 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10711 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10715 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10716 ArrayRef<int> Mask, SDValue V1,
10717 SDValue V2, SelectionDAG &DAG) {
10719 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10721 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10722 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10724 SmallVector<SDValue, 32> VPermMask;
10725 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10726 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10727 DAG.getConstant(Mask[i], DL, MaskEltVT));
10728 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10730 if (isSingleInputShuffleMask(Mask))
10731 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10733 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10736 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10737 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10738 const X86Subtarget *Subtarget,
10739 SelectionDAG &DAG) {
10741 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10742 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10743 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10744 ArrayRef<int> Mask = SVOp->getMask();
10745 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10747 if (SDValue Unpck =
10748 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10751 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10754 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10755 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10756 const X86Subtarget *Subtarget,
10757 SelectionDAG &DAG) {
10759 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10760 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10761 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10762 ArrayRef<int> Mask = SVOp->getMask();
10763 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10765 if (SDValue Unpck =
10766 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10769 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10772 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10773 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10774 const X86Subtarget *Subtarget,
10775 SelectionDAG &DAG) {
10777 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10778 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10779 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10780 ArrayRef<int> Mask = SVOp->getMask();
10781 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10783 if (SDValue Unpck =
10784 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10787 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10790 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10791 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10792 const X86Subtarget *Subtarget,
10793 SelectionDAG &DAG) {
10795 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10796 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10797 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10798 ArrayRef<int> Mask = SVOp->getMask();
10799 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10801 if (SDValue Unpck =
10802 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10805 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10808 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10809 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10810 const X86Subtarget *Subtarget,
10811 SelectionDAG &DAG) {
10813 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10814 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10815 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10816 ArrayRef<int> Mask = SVOp->getMask();
10817 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10818 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10820 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10823 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10824 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10825 const X86Subtarget *Subtarget,
10826 SelectionDAG &DAG) {
10828 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10829 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10830 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10831 ArrayRef<int> Mask = SVOp->getMask();
10832 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10833 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10835 // FIXME: Implement direct support for this type!
10836 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10839 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10841 /// This routine either breaks down the specific type of a 512-bit x86 vector
10842 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10843 /// together based on the available instructions.
10844 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10845 MVT VT, const X86Subtarget *Subtarget,
10846 SelectionDAG &DAG) {
10848 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10849 ArrayRef<int> Mask = SVOp->getMask();
10850 assert(Subtarget->hasAVX512() &&
10851 "Cannot lower 512-bit vectors w/ basic ISA!");
10853 // Check for being able to broadcast a single element.
10854 if (SDValue Broadcast =
10855 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10858 // Dispatch to each element type for lowering. If we don't have supprot for
10859 // specific element type shuffles at 512 bits, immediately split them and
10860 // lower them. Each lowering routine of a given type is allowed to assume that
10861 // the requisite ISA extensions for that element type are available.
10862 switch (VT.SimpleTy) {
10864 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10866 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10868 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10870 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10872 if (Subtarget->hasBWI())
10873 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10876 if (Subtarget->hasBWI())
10877 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10881 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10884 // Otherwise fall back on splitting.
10885 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10888 // Lower vXi1 vector shuffles.
10889 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10890 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10891 // vector, shuffle and then truncate it back.
10892 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10893 MVT VT, const X86Subtarget *Subtarget,
10894 SelectionDAG &DAG) {
10896 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10897 ArrayRef<int> Mask = SVOp->getMask();
10898 assert(Subtarget->hasAVX512() &&
10899 "Cannot lower 512-bit vectors w/o basic ISA!");
10901 switch (VT.SimpleTy) {
10903 assert(false && "Expected a vector of i1 elements");
10906 ExtVT = MVT::v2i64;
10909 ExtVT = MVT::v4i32;
10912 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10915 ExtVT = MVT::v16i32;
10918 ExtVT = MVT::v32i16;
10921 ExtVT = MVT::v64i8;
10925 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10926 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10927 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10928 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10930 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10933 V2 = DAG.getUNDEF(ExtVT);
10934 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10935 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10936 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10937 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10939 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10940 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10941 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10943 /// \brief Top-level lowering for x86 vector shuffles.
10945 /// This handles decomposition, canonicalization, and lowering of all x86
10946 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10947 /// above in helper routines. The canonicalization attempts to widen shuffles
10948 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10949 /// s.t. only one of the two inputs needs to be tested, etc.
10950 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10951 SelectionDAG &DAG) {
10952 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10953 ArrayRef<int> Mask = SVOp->getMask();
10954 SDValue V1 = Op.getOperand(0);
10955 SDValue V2 = Op.getOperand(1);
10956 MVT VT = Op.getSimpleValueType();
10957 int NumElements = VT.getVectorNumElements();
10959 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
10961 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
10962 "Can't lower MMX shuffles");
10964 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10965 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10966 if (V1IsUndef && V2IsUndef)
10967 return DAG.getUNDEF(VT);
10969 // When we create a shuffle node we put the UNDEF node to second operand,
10970 // but in some cases the first operand may be transformed to UNDEF.
10971 // In this case we should just commute the node.
10973 return DAG.getCommutedVectorShuffle(*SVOp);
10975 // Check for non-undef masks pointing at an undef vector and make the masks
10976 // undef as well. This makes it easier to match the shuffle based solely on
10980 if (M >= NumElements) {
10981 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10982 for (int &M : NewMask)
10983 if (M >= NumElements)
10985 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10988 // We actually see shuffles that are entirely re-arrangements of a set of
10989 // zero inputs. This mostly happens while decomposing complex shuffles into
10990 // simple ones. Directly lower these as a buildvector of zeros.
10991 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10992 if (Zeroable.all())
10993 return getZeroVector(VT, Subtarget, DAG, dl);
10995 // Try to collapse shuffles into using a vector type with fewer elements but
10996 // wider element types. We cap this to not form integers or floating point
10997 // elements wider than 64 bits, but it might be interesting to form i128
10998 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10999 SmallVector<int, 16> WidenedMask;
11000 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11001 canWidenShuffleElements(Mask, WidenedMask)) {
11002 MVT NewEltVT = VT.isFloatingPoint()
11003 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11004 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11005 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11006 // Make sure that the new vector type is legal. For example, v2f64 isn't
11008 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11009 V1 = DAG.getBitcast(NewVT, V1);
11010 V2 = DAG.getBitcast(NewVT, V2);
11011 return DAG.getBitcast(
11012 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11016 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11017 for (int M : SVOp->getMask())
11019 ++NumUndefElements;
11020 else if (M < NumElements)
11025 // Commute the shuffle as needed such that more elements come from V1 than
11026 // V2. This allows us to match the shuffle pattern strictly on how many
11027 // elements come from V1 without handling the symmetric cases.
11028 if (NumV2Elements > NumV1Elements)
11029 return DAG.getCommutedVectorShuffle(*SVOp);
11031 // When the number of V1 and V2 elements are the same, try to minimize the
11032 // number of uses of V2 in the low half of the vector. When that is tied,
11033 // ensure that the sum of indices for V1 is equal to or lower than the sum
11034 // indices for V2. When those are equal, try to ensure that the number of odd
11035 // indices for V1 is lower than the number of odd indices for V2.
11036 if (NumV1Elements == NumV2Elements) {
11037 int LowV1Elements = 0, LowV2Elements = 0;
11038 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11039 if (M >= NumElements)
11043 if (LowV2Elements > LowV1Elements) {
11044 return DAG.getCommutedVectorShuffle(*SVOp);
11045 } else if (LowV2Elements == LowV1Elements) {
11046 int SumV1Indices = 0, SumV2Indices = 0;
11047 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11048 if (SVOp->getMask()[i] >= NumElements)
11050 else if (SVOp->getMask()[i] >= 0)
11052 if (SumV2Indices < SumV1Indices) {
11053 return DAG.getCommutedVectorShuffle(*SVOp);
11054 } else if (SumV2Indices == SumV1Indices) {
11055 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11056 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11057 if (SVOp->getMask()[i] >= NumElements)
11058 NumV2OddIndices += i % 2;
11059 else if (SVOp->getMask()[i] >= 0)
11060 NumV1OddIndices += i % 2;
11061 if (NumV2OddIndices < NumV1OddIndices)
11062 return DAG.getCommutedVectorShuffle(*SVOp);
11067 // For each vector width, delegate to a specialized lowering routine.
11068 if (VT.getSizeInBits() == 128)
11069 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11071 if (VT.getSizeInBits() == 256)
11072 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11074 if (VT.getSizeInBits() == 512)
11075 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11078 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11079 llvm_unreachable("Unimplemented!");
11082 // This function assumes its argument is a BUILD_VECTOR of constants or
11083 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11085 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11086 unsigned &MaskValue) {
11088 unsigned NumElems = BuildVector->getNumOperands();
11089 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11090 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11091 unsigned NumElemsInLane = NumElems / NumLanes;
11093 // Blend for v16i16 should be symmetric for the both lanes.
11094 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11095 SDValue EltCond = BuildVector->getOperand(i);
11096 SDValue SndLaneEltCond =
11097 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11099 int Lane1Cond = -1, Lane2Cond = -1;
11100 if (isa<ConstantSDNode>(EltCond))
11101 Lane1Cond = !isZero(EltCond);
11102 if (isa<ConstantSDNode>(SndLaneEltCond))
11103 Lane2Cond = !isZero(SndLaneEltCond);
11105 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11106 // Lane1Cond != 0, means we want the first argument.
11107 // Lane1Cond == 0, means we want the second argument.
11108 // The encoding of this argument is 0 for the first argument, 1
11109 // for the second. Therefore, invert the condition.
11110 MaskValue |= !Lane1Cond << i;
11111 else if (Lane1Cond < 0)
11112 MaskValue |= !Lane2Cond << i;
11119 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11120 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11121 const X86Subtarget *Subtarget,
11122 SelectionDAG &DAG) {
11123 SDValue Cond = Op.getOperand(0);
11124 SDValue LHS = Op.getOperand(1);
11125 SDValue RHS = Op.getOperand(2);
11127 MVT VT = Op.getSimpleValueType();
11129 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11131 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11133 // Only non-legal VSELECTs reach this lowering, convert those into generic
11134 // shuffles and re-use the shuffle lowering path for blends.
11135 SmallVector<int, 32> Mask;
11136 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11137 SDValue CondElt = CondBV->getOperand(i);
11139 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11141 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11144 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11145 // A vselect where all conditions and data are constants can be optimized into
11146 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11147 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11148 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11149 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11152 // Try to lower this to a blend-style vector shuffle. This can handle all
11153 // constant condition cases.
11154 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11157 // Variable blends are only legal from SSE4.1 onward.
11158 if (!Subtarget->hasSSE41())
11161 // Only some types will be legal on some subtargets. If we can emit a legal
11162 // VSELECT-matching blend, return Op, and but if we need to expand, return
11164 switch (Op.getSimpleValueType().SimpleTy) {
11166 // Most of the vector types have blends past SSE4.1.
11170 // The byte blends for AVX vectors were introduced only in AVX2.
11171 if (Subtarget->hasAVX2())
11178 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11179 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11182 // FIXME: We should custom lower this by fixing the condition and using i8
11188 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11189 MVT VT = Op.getSimpleValueType();
11192 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11195 if (VT.getSizeInBits() == 8) {
11196 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11197 Op.getOperand(0), Op.getOperand(1));
11198 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11199 DAG.getValueType(VT));
11200 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11203 if (VT.getSizeInBits() == 16) {
11204 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11205 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11207 return DAG.getNode(
11208 ISD::TRUNCATE, dl, MVT::i16,
11209 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11210 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11211 Op.getOperand(1)));
11212 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11213 Op.getOperand(0), Op.getOperand(1));
11214 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11215 DAG.getValueType(VT));
11216 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11219 if (VT == MVT::f32) {
11220 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11221 // the result back to FR32 register. It's only worth matching if the
11222 // result has a single use which is a store or a bitcast to i32. And in
11223 // the case of a store, it's not worth it if the index is a constant 0,
11224 // because a MOVSSmr can be used instead, which is smaller and faster.
11225 if (!Op.hasOneUse())
11227 SDNode *User = *Op.getNode()->use_begin();
11228 if ((User->getOpcode() != ISD::STORE ||
11229 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11230 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11231 (User->getOpcode() != ISD::BITCAST ||
11232 User->getValueType(0) != MVT::i32))
11234 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11235 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11237 return DAG.getBitcast(MVT::f32, Extract);
11240 if (VT == MVT::i32 || VT == MVT::i64) {
11241 // ExtractPS/pextrq works with constant index.
11242 if (isa<ConstantSDNode>(Op.getOperand(1)))
11248 /// Extract one bit from mask vector, like v16i1 or v8i1.
11249 /// AVX-512 feature.
11251 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11252 SDValue Vec = Op.getOperand(0);
11254 MVT VecVT = Vec.getSimpleValueType();
11255 SDValue Idx = Op.getOperand(1);
11256 MVT EltVT = Op.getSimpleValueType();
11258 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11259 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11260 "Unexpected vector type in ExtractBitFromMaskVector");
11262 // variable index can't be handled in mask registers,
11263 // extend vector to VR512
11264 if (!isa<ConstantSDNode>(Idx)) {
11265 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11266 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11267 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11268 ExtVT.getVectorElementType(), Ext, Idx);
11269 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11272 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11273 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11274 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11275 rc = getRegClassFor(MVT::v16i1);
11276 unsigned MaxSift = rc->getSize()*8 - 1;
11277 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11278 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11279 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11280 DAG.getConstant(MaxSift, dl, MVT::i8));
11281 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11282 DAG.getIntPtrConstant(0, dl));
11286 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11287 SelectionDAG &DAG) const {
11289 SDValue Vec = Op.getOperand(0);
11290 MVT VecVT = Vec.getSimpleValueType();
11291 SDValue Idx = Op.getOperand(1);
11293 if (Op.getSimpleValueType() == MVT::i1)
11294 return ExtractBitFromMaskVector(Op, DAG);
11296 if (!isa<ConstantSDNode>(Idx)) {
11297 if (VecVT.is512BitVector() ||
11298 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11299 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11302 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11303 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11304 MaskEltVT.getSizeInBits());
11306 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11307 auto PtrVT = getPointerTy(DAG.getDataLayout());
11308 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11309 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11310 DAG.getConstant(0, dl, PtrVT));
11311 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11312 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11313 DAG.getConstant(0, dl, PtrVT));
11318 // If this is a 256-bit vector result, first extract the 128-bit vector and
11319 // then extract the element from the 128-bit vector.
11320 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11322 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11323 // Get the 128-bit vector.
11324 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11325 MVT EltVT = VecVT.getVectorElementType();
11327 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11329 //if (IdxVal >= NumElems/2)
11330 // IdxVal -= NumElems/2;
11331 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11332 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11333 DAG.getConstant(IdxVal, dl, MVT::i32));
11336 assert(VecVT.is128BitVector() && "Unexpected vector length");
11338 if (Subtarget->hasSSE41())
11339 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11342 MVT VT = Op.getSimpleValueType();
11343 // TODO: handle v16i8.
11344 if (VT.getSizeInBits() == 16) {
11345 SDValue Vec = Op.getOperand(0);
11346 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11348 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11349 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11350 DAG.getBitcast(MVT::v4i32, Vec),
11351 Op.getOperand(1)));
11352 // Transform it so it match pextrw which produces a 32-bit result.
11353 MVT EltVT = MVT::i32;
11354 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11355 Op.getOperand(0), Op.getOperand(1));
11356 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11357 DAG.getValueType(VT));
11358 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11361 if (VT.getSizeInBits() == 32) {
11362 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11366 // SHUFPS the element to the lowest double word, then movss.
11367 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11368 MVT VVT = Op.getOperand(0).getSimpleValueType();
11369 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11370 DAG.getUNDEF(VVT), Mask);
11371 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11372 DAG.getIntPtrConstant(0, dl));
11375 if (VT.getSizeInBits() == 64) {
11376 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11377 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11378 // to match extract_elt for f64.
11379 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11383 // UNPCKHPD the element to the lowest double word, then movsd.
11384 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11385 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11386 int Mask[2] = { 1, -1 };
11387 MVT VVT = Op.getOperand(0).getSimpleValueType();
11388 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11389 DAG.getUNDEF(VVT), Mask);
11390 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11391 DAG.getIntPtrConstant(0, dl));
11397 /// Insert one bit to mask vector, like v16i1 or v8i1.
11398 /// AVX-512 feature.
11400 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11402 SDValue Vec = Op.getOperand(0);
11403 SDValue Elt = Op.getOperand(1);
11404 SDValue Idx = Op.getOperand(2);
11405 MVT VecVT = Vec.getSimpleValueType();
11407 if (!isa<ConstantSDNode>(Idx)) {
11408 // Non constant index. Extend source and destination,
11409 // insert element and then truncate the result.
11410 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11411 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11412 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11413 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11414 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11415 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11418 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11419 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11421 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11422 DAG.getConstant(IdxVal, dl, MVT::i8));
11423 if (Vec.getOpcode() == ISD::UNDEF)
11425 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11428 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11429 SelectionDAG &DAG) const {
11430 MVT VT = Op.getSimpleValueType();
11431 MVT EltVT = VT.getVectorElementType();
11433 if (EltVT == MVT::i1)
11434 return InsertBitToMaskVector(Op, DAG);
11437 SDValue N0 = Op.getOperand(0);
11438 SDValue N1 = Op.getOperand(1);
11439 SDValue N2 = Op.getOperand(2);
11440 if (!isa<ConstantSDNode>(N2))
11442 auto *N2C = cast<ConstantSDNode>(N2);
11443 unsigned IdxVal = N2C->getZExtValue();
11445 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11446 // into that, and then insert the subvector back into the result.
11447 if (VT.is256BitVector() || VT.is512BitVector()) {
11448 // With a 256-bit vector, we can insert into the zero element efficiently
11449 // using a blend if we have AVX or AVX2 and the right data type.
11450 if (VT.is256BitVector() && IdxVal == 0) {
11451 // TODO: It is worthwhile to cast integer to floating point and back
11452 // and incur a domain crossing penalty if that's what we'll end up
11453 // doing anyway after extracting to a 128-bit vector.
11454 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11455 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11456 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11457 N2 = DAG.getIntPtrConstant(1, dl);
11458 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11462 // Get the desired 128-bit vector chunk.
11463 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11465 // Insert the element into the desired chunk.
11466 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11467 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11469 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11470 DAG.getConstant(IdxIn128, dl, MVT::i32));
11472 // Insert the changed part back into the bigger vector
11473 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11475 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11477 if (Subtarget->hasSSE41()) {
11478 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11480 if (VT == MVT::v8i16) {
11481 Opc = X86ISD::PINSRW;
11483 assert(VT == MVT::v16i8);
11484 Opc = X86ISD::PINSRB;
11487 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11489 if (N1.getValueType() != MVT::i32)
11490 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11491 if (N2.getValueType() != MVT::i32)
11492 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11493 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11496 if (EltVT == MVT::f32) {
11497 // Bits [7:6] of the constant are the source select. This will always be
11498 // zero here. The DAG Combiner may combine an extract_elt index into
11499 // these bits. For example (insert (extract, 3), 2) could be matched by
11500 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11501 // Bits [5:4] of the constant are the destination select. This is the
11502 // value of the incoming immediate.
11503 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11504 // combine either bitwise AND or insert of float 0.0 to set these bits.
11506 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11507 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11508 // If this is an insertion of 32-bits into the low 32-bits of
11509 // a vector, we prefer to generate a blend with immediate rather
11510 // than an insertps. Blends are simpler operations in hardware and so
11511 // will always have equal or better performance than insertps.
11512 // But if optimizing for size and there's a load folding opportunity,
11513 // generate insertps because blendps does not have a 32-bit memory
11515 N2 = DAG.getIntPtrConstant(1, dl);
11516 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11517 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11519 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11520 // Create this as a scalar to vector..
11521 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11522 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11525 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11526 // PINSR* works with constant index.
11531 if (EltVT == MVT::i8)
11534 if (EltVT.getSizeInBits() == 16) {
11535 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11536 // as its second argument.
11537 if (N1.getValueType() != MVT::i32)
11538 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11539 if (N2.getValueType() != MVT::i32)
11540 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11541 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11546 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11548 MVT OpVT = Op.getSimpleValueType();
11550 // If this is a 256-bit vector result, first insert into a 128-bit
11551 // vector and then insert into the 256-bit vector.
11552 if (!OpVT.is128BitVector()) {
11553 // Insert into a 128-bit vector.
11554 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11555 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11556 OpVT.getVectorNumElements() / SizeFactor);
11558 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11560 // Insert the 128-bit vector.
11561 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11564 if (OpVT == MVT::v1i64 &&
11565 Op.getOperand(0).getValueType() == MVT::i64)
11566 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11568 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11569 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11570 return DAG.getBitcast(
11571 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11574 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11575 // a simple subregister reference or explicit instructions to grab
11576 // upper bits of a vector.
11577 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11578 SelectionDAG &DAG) {
11580 SDValue In = Op.getOperand(0);
11581 SDValue Idx = Op.getOperand(1);
11582 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11583 MVT ResVT = Op.getSimpleValueType();
11584 MVT InVT = In.getSimpleValueType();
11586 if (Subtarget->hasFp256()) {
11587 if (ResVT.is128BitVector() &&
11588 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11589 isa<ConstantSDNode>(Idx)) {
11590 return Extract128BitVector(In, IdxVal, DAG, dl);
11592 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11593 isa<ConstantSDNode>(Idx)) {
11594 return Extract256BitVector(In, IdxVal, DAG, dl);
11600 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11601 // simple superregister reference or explicit instructions to insert
11602 // the upper bits of a vector.
11603 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11604 SelectionDAG &DAG) {
11605 if (!Subtarget->hasAVX())
11609 SDValue Vec = Op.getOperand(0);
11610 SDValue SubVec = Op.getOperand(1);
11611 SDValue Idx = Op.getOperand(2);
11613 if (!isa<ConstantSDNode>(Idx))
11616 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11617 MVT OpVT = Op.getSimpleValueType();
11618 MVT SubVecVT = SubVec.getSimpleValueType();
11620 // Fold two 16-byte subvector loads into one 32-byte load:
11621 // (insert_subvector (insert_subvector undef, (load addr), 0),
11622 // (load addr + 16), Elts/2)
11624 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11625 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11626 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11627 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11628 if (Idx2 && Idx2->getZExtValue() == 0) {
11629 SDValue SubVec2 = Vec.getOperand(1);
11630 // If needed, look through a bitcast to get to the load.
11631 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11632 SubVec2 = SubVec2.getOperand(0);
11634 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11636 unsigned Alignment = FirstLd->getAlignment();
11637 unsigned AS = FirstLd->getAddressSpace();
11638 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11639 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11640 OpVT, AS, Alignment, &Fast) && Fast) {
11641 SDValue Ops[] = { SubVec2, SubVec };
11642 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11649 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11650 SubVecVT.is128BitVector())
11651 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11653 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11654 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11656 if (OpVT.getVectorElementType() == MVT::i1) {
11657 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11659 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11660 SDValue Undef = DAG.getUNDEF(OpVT);
11661 unsigned NumElems = OpVT.getVectorNumElements();
11662 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11664 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11665 // Zero upper bits of the Vec
11666 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11667 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11669 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11671 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11672 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11675 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11677 // Zero upper bits of the Vec2
11678 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11679 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11680 // Zero lower bits of the Vec
11681 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11682 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11683 // Merge them together
11684 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11690 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11691 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11692 // one of the above mentioned nodes. It has to be wrapped because otherwise
11693 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11694 // be used to form addressing mode. These wrapped nodes will be selected
11697 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11698 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11700 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11701 // global base reg.
11702 unsigned char OpFlag = 0;
11703 unsigned WrapperKind = X86ISD::Wrapper;
11704 CodeModel::Model M = DAG.getTarget().getCodeModel();
11706 if (Subtarget->isPICStyleRIPRel() &&
11707 (M == CodeModel::Small || M == CodeModel::Kernel))
11708 WrapperKind = X86ISD::WrapperRIP;
11709 else if (Subtarget->isPICStyleGOT())
11710 OpFlag = X86II::MO_GOTOFF;
11711 else if (Subtarget->isPICStyleStubPIC())
11712 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11714 auto PtrVT = getPointerTy(DAG.getDataLayout());
11715 SDValue Result = DAG.getTargetConstantPool(
11716 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11718 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11719 // With PIC, the address is actually $g + Offset.
11722 DAG.getNode(ISD::ADD, DL, PtrVT,
11723 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11729 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11730 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11732 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11733 // global base reg.
11734 unsigned char OpFlag = 0;
11735 unsigned WrapperKind = X86ISD::Wrapper;
11736 CodeModel::Model M = DAG.getTarget().getCodeModel();
11738 if (Subtarget->isPICStyleRIPRel() &&
11739 (M == CodeModel::Small || M == CodeModel::Kernel))
11740 WrapperKind = X86ISD::WrapperRIP;
11741 else if (Subtarget->isPICStyleGOT())
11742 OpFlag = X86II::MO_GOTOFF;
11743 else if (Subtarget->isPICStyleStubPIC())
11744 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11746 auto PtrVT = getPointerTy(DAG.getDataLayout());
11747 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11749 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11751 // With PIC, the address is actually $g + Offset.
11754 DAG.getNode(ISD::ADD, DL, PtrVT,
11755 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11761 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11762 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11764 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11765 // global base reg.
11766 unsigned char OpFlag = 0;
11767 unsigned WrapperKind = X86ISD::Wrapper;
11768 CodeModel::Model M = DAG.getTarget().getCodeModel();
11770 if (Subtarget->isPICStyleRIPRel() &&
11771 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11772 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11773 OpFlag = X86II::MO_GOTPCREL;
11774 WrapperKind = X86ISD::WrapperRIP;
11775 } else if (Subtarget->isPICStyleGOT()) {
11776 OpFlag = X86II::MO_GOT;
11777 } else if (Subtarget->isPICStyleStubPIC()) {
11778 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11779 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11780 OpFlag = X86II::MO_DARWIN_NONLAZY;
11783 auto PtrVT = getPointerTy(DAG.getDataLayout());
11784 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11787 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11789 // With PIC, the address is actually $g + Offset.
11790 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11791 !Subtarget->is64Bit()) {
11793 DAG.getNode(ISD::ADD, DL, PtrVT,
11794 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11797 // For symbols that require a load from a stub to get the address, emit the
11799 if (isGlobalStubReference(OpFlag))
11800 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11801 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11802 false, false, false, 0);
11808 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11809 // Create the TargetBlockAddressAddress node.
11810 unsigned char OpFlags =
11811 Subtarget->ClassifyBlockAddressReference();
11812 CodeModel::Model M = DAG.getTarget().getCodeModel();
11813 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11814 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11816 auto PtrVT = getPointerTy(DAG.getDataLayout());
11817 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11819 if (Subtarget->isPICStyleRIPRel() &&
11820 (M == CodeModel::Small || M == CodeModel::Kernel))
11821 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11823 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11825 // With PIC, the address is actually $g + Offset.
11826 if (isGlobalRelativeToPICBase(OpFlags)) {
11827 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11828 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11835 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11836 int64_t Offset, SelectionDAG &DAG) const {
11837 // Create the TargetGlobalAddress node, folding in the constant
11838 // offset if it is legal.
11839 unsigned char OpFlags =
11840 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11841 CodeModel::Model M = DAG.getTarget().getCodeModel();
11842 auto PtrVT = getPointerTy(DAG.getDataLayout());
11844 if (OpFlags == X86II::MO_NO_FLAG &&
11845 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11846 // A direct static reference to a global.
11847 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11850 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11853 if (Subtarget->isPICStyleRIPRel() &&
11854 (M == CodeModel::Small || M == CodeModel::Kernel))
11855 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11857 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11859 // With PIC, the address is actually $g + Offset.
11860 if (isGlobalRelativeToPICBase(OpFlags)) {
11861 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11862 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11865 // For globals that require a load from a stub to get the address, emit the
11867 if (isGlobalStubReference(OpFlags))
11868 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11869 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11870 false, false, false, 0);
11872 // If there was a non-zero offset that we didn't fold, create an explicit
11873 // addition for it.
11875 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11876 DAG.getConstant(Offset, dl, PtrVT));
11882 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11883 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11884 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11885 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11889 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11890 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11891 unsigned char OperandFlags, bool LocalDynamic = false) {
11892 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11893 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11895 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11896 GA->getValueType(0),
11900 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11904 SDValue Ops[] = { Chain, TGA, *InFlag };
11905 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11907 SDValue Ops[] = { Chain, TGA };
11908 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11911 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11912 MFI->setAdjustsStack(true);
11913 MFI->setHasCalls(true);
11915 SDValue Flag = Chain.getValue(1);
11916 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11919 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11921 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11924 SDLoc dl(GA); // ? function entry point might be better
11925 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11926 DAG.getNode(X86ISD::GlobalBaseReg,
11927 SDLoc(), PtrVT), InFlag);
11928 InFlag = Chain.getValue(1);
11930 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11933 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11935 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11937 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11938 X86::RAX, X86II::MO_TLSGD);
11941 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11947 // Get the start address of the TLS block for this module.
11948 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11949 .getInfo<X86MachineFunctionInfo>();
11950 MFI->incNumLocalDynamicTLSAccesses();
11954 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11955 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11958 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11959 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11960 InFlag = Chain.getValue(1);
11961 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11962 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11965 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11969 unsigned char OperandFlags = X86II::MO_DTPOFF;
11970 unsigned WrapperKind = X86ISD::Wrapper;
11971 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11972 GA->getValueType(0),
11973 GA->getOffset(), OperandFlags);
11974 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11976 // Add x@dtpoff with the base.
11977 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11980 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11981 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11982 const EVT PtrVT, TLSModel::Model model,
11983 bool is64Bit, bool isPIC) {
11986 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11987 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11988 is64Bit ? 257 : 256));
11990 SDValue ThreadPointer =
11991 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11992 MachinePointerInfo(Ptr), false, false, false, 0);
11994 unsigned char OperandFlags = 0;
11995 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11997 unsigned WrapperKind = X86ISD::Wrapper;
11998 if (model == TLSModel::LocalExec) {
11999 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12000 } else if (model == TLSModel::InitialExec) {
12002 OperandFlags = X86II::MO_GOTTPOFF;
12003 WrapperKind = X86ISD::WrapperRIP;
12005 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12008 llvm_unreachable("Unexpected model");
12011 // emit "addl x@ntpoff,%eax" (local exec)
12012 // or "addl x@indntpoff,%eax" (initial exec)
12013 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12015 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12016 GA->getOffset(), OperandFlags);
12017 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12019 if (model == TLSModel::InitialExec) {
12020 if (isPIC && !is64Bit) {
12021 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12022 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12026 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12027 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12028 false, false, false, 0);
12031 // The address of the thread local variable is the add of the thread
12032 // pointer with the offset of the variable.
12033 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12037 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12039 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12040 const GlobalValue *GV = GA->getGlobal();
12041 auto PtrVT = getPointerTy(DAG.getDataLayout());
12043 if (Subtarget->isTargetELF()) {
12044 if (DAG.getTarget().Options.EmulatedTLS)
12045 return LowerToTLSEmulatedModel(GA, DAG);
12046 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12048 case TLSModel::GeneralDynamic:
12049 if (Subtarget->is64Bit())
12050 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12051 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12052 case TLSModel::LocalDynamic:
12053 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12054 Subtarget->is64Bit());
12055 case TLSModel::InitialExec:
12056 case TLSModel::LocalExec:
12057 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12058 DAG.getTarget().getRelocationModel() ==
12061 llvm_unreachable("Unknown TLS model.");
12064 if (Subtarget->isTargetDarwin()) {
12065 // Darwin only has one model of TLS. Lower to that.
12066 unsigned char OpFlag = 0;
12067 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12068 X86ISD::WrapperRIP : X86ISD::Wrapper;
12070 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12071 // global base reg.
12072 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12073 !Subtarget->is64Bit();
12075 OpFlag = X86II::MO_TLVP_PIC_BASE;
12077 OpFlag = X86II::MO_TLVP;
12079 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12080 GA->getValueType(0),
12081 GA->getOffset(), OpFlag);
12082 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12084 // With PIC32, the address is actually $g + Offset.
12086 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12087 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12090 // Lowering the machine isd will make sure everything is in the right
12092 SDValue Chain = DAG.getEntryNode();
12093 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12094 SDValue Args[] = { Chain, Offset };
12095 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12097 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12098 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12099 MFI->setAdjustsStack(true);
12101 // And our return value (tls address) is in the standard call return value
12103 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12104 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12107 if (Subtarget->isTargetKnownWindowsMSVC() ||
12108 Subtarget->isTargetWindowsGNU()) {
12109 // Just use the implicit TLS architecture
12110 // Need to generate someting similar to:
12111 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12113 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12114 // mov rcx, qword [rdx+rcx*8]
12115 // mov eax, .tls$:tlsvar
12116 // [rax+rcx] contains the address
12117 // Windows 64bit: gs:0x58
12118 // Windows 32bit: fs:__tls_array
12121 SDValue Chain = DAG.getEntryNode();
12123 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12124 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12125 // use its literal value of 0x2C.
12126 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12127 ? Type::getInt8PtrTy(*DAG.getContext(),
12129 : Type::getInt32PtrTy(*DAG.getContext(),
12132 SDValue TlsArray = Subtarget->is64Bit()
12133 ? DAG.getIntPtrConstant(0x58, dl)
12134 : (Subtarget->isTargetWindowsGNU()
12135 ? DAG.getIntPtrConstant(0x2C, dl)
12136 : DAG.getExternalSymbol("_tls_array", PtrVT));
12138 SDValue ThreadPointer =
12139 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12143 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12144 res = ThreadPointer;
12146 // Load the _tls_index variable
12147 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12148 if (Subtarget->is64Bit())
12149 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12150 MachinePointerInfo(), MVT::i32, false, false,
12153 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12156 auto &DL = DAG.getDataLayout();
12158 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12159 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12161 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12164 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12167 // Get the offset of start of .tls section
12168 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12169 GA->getValueType(0),
12170 GA->getOffset(), X86II::MO_SECREL);
12171 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12173 // The address of the thread local variable is the add of the thread
12174 // pointer with the offset of the variable.
12175 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12178 llvm_unreachable("TLS not implemented for this target.");
12181 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12182 /// and take a 2 x i32 value to shift plus a shift amount.
12183 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12184 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12185 MVT VT = Op.getSimpleValueType();
12186 unsigned VTBits = VT.getSizeInBits();
12188 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12189 SDValue ShOpLo = Op.getOperand(0);
12190 SDValue ShOpHi = Op.getOperand(1);
12191 SDValue ShAmt = Op.getOperand(2);
12192 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12193 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12195 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12196 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12197 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12198 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12199 : DAG.getConstant(0, dl, VT);
12201 SDValue Tmp2, Tmp3;
12202 if (Op.getOpcode() == ISD::SHL_PARTS) {
12203 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12204 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12206 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12207 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12210 // If the shift amount is larger or equal than the width of a part we can't
12211 // rely on the results of shld/shrd. Insert a test and select the appropriate
12212 // values for large shift amounts.
12213 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12214 DAG.getConstant(VTBits, dl, MVT::i8));
12215 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12216 AndNode, DAG.getConstant(0, dl, MVT::i8));
12219 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12220 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12221 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12223 if (Op.getOpcode() == ISD::SHL_PARTS) {
12224 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12225 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12227 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12228 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12231 SDValue Ops[2] = { Lo, Hi };
12232 return DAG.getMergeValues(Ops, dl);
12235 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12236 SelectionDAG &DAG) const {
12237 SDValue Src = Op.getOperand(0);
12238 MVT SrcVT = Src.getSimpleValueType();
12239 MVT VT = Op.getSimpleValueType();
12242 if (SrcVT.isVector()) {
12243 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12244 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12245 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12246 DAG.getUNDEF(SrcVT)));
12248 if (SrcVT.getVectorElementType() == MVT::i1) {
12249 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12250 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12251 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12256 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12257 "Unknown SINT_TO_FP to lower!");
12259 // These are really Legal; return the operand so the caller accepts it as
12261 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12263 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12264 Subtarget->is64Bit()) {
12268 unsigned Size = SrcVT.getSizeInBits()/8;
12269 MachineFunction &MF = DAG.getMachineFunction();
12270 auto PtrVT = getPointerTy(MF.getDataLayout());
12271 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12272 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12273 SDValue Chain = DAG.getStore(
12274 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12275 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12277 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12280 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12282 SelectionDAG &DAG) const {
12286 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12288 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12290 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12292 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12294 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12295 MachineMemOperand *MMO;
12297 int SSFI = FI->getIndex();
12298 MMO = DAG.getMachineFunction().getMachineMemOperand(
12299 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12300 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12302 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12303 StackSlot = StackSlot.getOperand(1);
12305 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12306 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12308 Tys, Ops, SrcVT, MMO);
12311 Chain = Result.getValue(1);
12312 SDValue InFlag = Result.getValue(2);
12314 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12315 // shouldn't be necessary except that RFP cannot be live across
12316 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12317 MachineFunction &MF = DAG.getMachineFunction();
12318 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12319 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12320 auto PtrVT = getPointerTy(MF.getDataLayout());
12321 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12322 Tys = DAG.getVTList(MVT::Other);
12324 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12326 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12327 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12328 MachineMemOperand::MOStore, SSFISize, SSFISize);
12330 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12331 Ops, Op.getValueType(), MMO);
12332 Result = DAG.getLoad(
12333 Op.getValueType(), DL, Chain, StackSlot,
12334 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12335 false, false, false, 0);
12341 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12342 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12343 SelectionDAG &DAG) const {
12344 // This algorithm is not obvious. Here it is what we're trying to output:
12347 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12348 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12350 haddpd %xmm0, %xmm0
12352 pshufd $0x4e, %xmm0, %xmm1
12358 LLVMContext *Context = DAG.getContext();
12360 // Build some magic constants.
12361 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12362 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12363 auto PtrVT = getPointerTy(DAG.getDataLayout());
12364 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12366 SmallVector<Constant*,2> CV1;
12368 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12369 APInt(64, 0x4330000000000000ULL))));
12371 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12372 APInt(64, 0x4530000000000000ULL))));
12373 Constant *C1 = ConstantVector::get(CV1);
12374 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12376 // Load the 64-bit value into an XMM register.
12377 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12380 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12381 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12382 false, false, false, 16);
12384 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12387 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12388 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12389 false, false, false, 16);
12390 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12391 // TODO: Are there any fast-math-flags to propagate here?
12392 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12395 if (Subtarget->hasSSE3()) {
12396 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12397 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12399 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12400 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12402 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12403 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12406 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12407 DAG.getIntPtrConstant(0, dl));
12410 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12411 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12412 SelectionDAG &DAG) const {
12414 // FP constant to bias correct the final result.
12415 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12418 // Load the 32-bit value into an XMM register.
12419 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12422 // Zero out the upper parts of the register.
12423 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12425 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12426 DAG.getBitcast(MVT::v2f64, Load),
12427 DAG.getIntPtrConstant(0, dl));
12429 // Or the load with the bias.
12430 SDValue Or = DAG.getNode(
12431 ISD::OR, dl, MVT::v2i64,
12432 DAG.getBitcast(MVT::v2i64,
12433 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12434 DAG.getBitcast(MVT::v2i64,
12435 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12437 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12438 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12440 // Subtract the bias.
12441 // TODO: Are there any fast-math-flags to propagate here?
12442 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12444 // Handle final rounding.
12445 EVT DestVT = Op.getValueType();
12447 if (DestVT.bitsLT(MVT::f64))
12448 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12449 DAG.getIntPtrConstant(0, dl));
12450 if (DestVT.bitsGT(MVT::f64))
12451 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12453 // Handle final rounding.
12457 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12458 const X86Subtarget &Subtarget) {
12459 // The algorithm is the following:
12460 // #ifdef __SSE4_1__
12461 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12462 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12463 // (uint4) 0x53000000, 0xaa);
12465 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12466 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12468 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12469 // return (float4) lo + fhi;
12472 SDValue V = Op->getOperand(0);
12473 EVT VecIntVT = V.getValueType();
12474 bool Is128 = VecIntVT == MVT::v4i32;
12475 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12476 // If we convert to something else than the supported type, e.g., to v4f64,
12478 if (VecFloatVT != Op->getValueType(0))
12481 unsigned NumElts = VecIntVT.getVectorNumElements();
12482 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12483 "Unsupported custom type");
12484 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12486 // In the #idef/#else code, we have in common:
12487 // - The vector of constants:
12493 // Create the splat vector for 0x4b000000.
12494 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12495 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12496 CstLow, CstLow, CstLow, CstLow};
12497 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12498 makeArrayRef(&CstLowArray[0], NumElts));
12499 // Create the splat vector for 0x53000000.
12500 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12501 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12502 CstHigh, CstHigh, CstHigh, CstHigh};
12503 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12504 makeArrayRef(&CstHighArray[0], NumElts));
12506 // Create the right shift.
12507 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12508 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12509 CstShift, CstShift, CstShift, CstShift};
12510 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12511 makeArrayRef(&CstShiftArray[0], NumElts));
12512 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12515 if (Subtarget.hasSSE41()) {
12516 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12517 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12518 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12519 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12520 // Low will be bitcasted right away, so do not bother bitcasting back to its
12522 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12523 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12524 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12525 // (uint4) 0x53000000, 0xaa);
12526 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12527 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12528 // High will be bitcasted right away, so do not bother bitcasting back to
12529 // its original type.
12530 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12531 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12533 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12534 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12535 CstMask, CstMask, CstMask);
12536 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12537 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12538 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12540 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12541 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12544 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12545 SDValue CstFAdd = DAG.getConstantFP(
12546 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12547 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12548 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12549 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12550 makeArrayRef(&CstFAddArray[0], NumElts));
12552 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12553 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12554 // TODO: Are there any fast-math-flags to propagate here?
12556 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12557 // return (float4) lo + fhi;
12558 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12559 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12562 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12563 SelectionDAG &DAG) const {
12564 SDValue N0 = Op.getOperand(0);
12565 MVT SVT = N0.getSimpleValueType();
12568 switch (SVT.SimpleTy) {
12570 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12575 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12576 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12577 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12581 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12584 if (Subtarget->hasAVX512())
12585 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12586 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12588 llvm_unreachable(nullptr);
12591 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12592 SelectionDAG &DAG) const {
12593 SDValue N0 = Op.getOperand(0);
12595 auto PtrVT = getPointerTy(DAG.getDataLayout());
12597 if (Op.getValueType().isVector())
12598 return lowerUINT_TO_FP_vec(Op, DAG);
12600 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12601 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12602 // the optimization here.
12603 if (DAG.SignBitIsZero(N0))
12604 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12606 MVT SrcVT = N0.getSimpleValueType();
12607 MVT DstVT = Op.getSimpleValueType();
12609 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12610 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12611 // Conversions from unsigned i32 to f32/f64 are legal,
12612 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12616 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12617 return LowerUINT_TO_FP_i64(Op, DAG);
12618 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12619 return LowerUINT_TO_FP_i32(Op, DAG);
12620 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12623 // Make a 64-bit buffer, and use it to build an FILD.
12624 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12625 if (SrcVT == MVT::i32) {
12626 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12627 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12628 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12629 StackSlot, MachinePointerInfo(),
12631 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12632 OffsetSlot, MachinePointerInfo(),
12634 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12638 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12639 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12640 StackSlot, MachinePointerInfo(),
12642 // For i64 source, we need to add the appropriate power of 2 if the input
12643 // was negative. This is the same as the optimization in
12644 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12645 // we must be careful to do the computation in x87 extended precision, not
12646 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12647 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12648 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12649 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12650 MachineMemOperand::MOLoad, 8, 8);
12652 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12653 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12654 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12657 APInt FF(32, 0x5F800000ULL);
12659 // Check whether the sign bit is set.
12660 SDValue SignSet = DAG.getSetCC(
12661 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12662 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12664 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12665 SDValue FudgePtr = DAG.getConstantPool(
12666 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12668 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12669 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12670 SDValue Four = DAG.getIntPtrConstant(4, dl);
12671 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12673 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12675 // Load the value out, extending it from f32 to f80.
12676 // FIXME: Avoid the extend by constructing the right constant pool?
12677 SDValue Fudge = DAG.getExtLoad(
12678 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12679 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12680 false, false, false, 4);
12681 // Extend everything to 80 bits to force it to be done on x87.
12682 // TODO: Are there any fast-math-flags to propagate here?
12683 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12684 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12685 DAG.getIntPtrConstant(0, dl));
12688 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12689 // is legal, or has an f16 source (which needs to be promoted to f32),
12690 // just return an <SDValue(), SDValue()> pair.
12691 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12692 // to i16, i32 or i64, and we lower it to a legal sequence.
12693 // If lowered to the final integer result we return a <result, SDValue()> pair.
12694 // Otherwise we lower it to a sequence ending with a FIST, return a
12695 // <FIST, StackSlot> pair, and the caller is responsible for loading
12696 // the final integer result from StackSlot.
12697 std::pair<SDValue,SDValue>
12698 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12699 bool IsSigned, bool IsReplace) const {
12702 EVT DstTy = Op.getValueType();
12703 EVT TheVT = Op.getOperand(0).getValueType();
12704 auto PtrVT = getPointerTy(DAG.getDataLayout());
12706 if (TheVT == MVT::f16)
12707 // We need to promote the f16 to f32 before using the lowering
12708 // in this routine.
12709 return std::make_pair(SDValue(), SDValue());
12711 assert((TheVT == MVT::f32 ||
12712 TheVT == MVT::f64 ||
12713 TheVT == MVT::f80) &&
12714 "Unexpected FP operand type in FP_TO_INTHelper");
12716 // If using FIST to compute an unsigned i64, we'll need some fixup
12717 // to handle values above the maximum signed i64. A FIST is always
12718 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12719 bool UnsignedFixup = !IsSigned &&
12720 DstTy == MVT::i64 &&
12721 (!Subtarget->is64Bit() ||
12722 !isScalarFPTypeInSSEReg(TheVT));
12724 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12725 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12726 // The low 32 bits of the fist result will have the correct uint32 result.
12727 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12731 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12732 DstTy.getSimpleVT() >= MVT::i16 &&
12733 "Unknown FP_TO_INT to lower!");
12735 // These are really Legal.
12736 if (DstTy == MVT::i32 &&
12737 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12738 return std::make_pair(SDValue(), SDValue());
12739 if (Subtarget->is64Bit() &&
12740 DstTy == MVT::i64 &&
12741 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12742 return std::make_pair(SDValue(), SDValue());
12744 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12746 MachineFunction &MF = DAG.getMachineFunction();
12747 unsigned MemSize = DstTy.getSizeInBits()/8;
12748 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12749 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12752 switch (DstTy.getSimpleVT().SimpleTy) {
12753 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12754 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12755 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12756 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12759 SDValue Chain = DAG.getEntryNode();
12760 SDValue Value = Op.getOperand(0);
12761 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12763 if (UnsignedFixup) {
12765 // Conversion to unsigned i64 is implemented with a select,
12766 // depending on whether the source value fits in the range
12767 // of a signed i64. Let Thresh be the FP equivalent of
12768 // 0x8000000000000000ULL.
12770 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12771 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12772 // Fist-to-mem64 FistSrc
12773 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12774 // to XOR'ing the high 32 bits with Adjust.
12776 // Being a power of 2, Thresh is exactly representable in all FP formats.
12777 // For X87 we'd like to use the smallest FP type for this constant, but
12778 // for DAG type consistency we have to match the FP operand type.
12780 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12781 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12782 bool LosesInfo = false;
12783 if (TheVT == MVT::f64)
12784 // The rounding mode is irrelevant as the conversion should be exact.
12785 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12787 else if (TheVT == MVT::f80)
12788 Status = Thresh.convert(APFloat::x87DoubleExtended,
12789 APFloat::rmNearestTiesToEven, &LosesInfo);
12791 assert(Status == APFloat::opOK && !LosesInfo &&
12792 "FP conversion should have been exact");
12794 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12796 SDValue Cmp = DAG.getSetCC(DL,
12797 getSetCCResultType(DAG.getDataLayout(),
12798 *DAG.getContext(), TheVT),
12799 Value, ThreshVal, ISD::SETLT);
12800 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12801 DAG.getConstant(0, DL, MVT::i32),
12802 DAG.getConstant(0x80000000, DL, MVT::i32));
12803 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12804 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12805 *DAG.getContext(), TheVT),
12806 Value, ThreshVal, ISD::SETLT);
12807 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12810 // FIXME This causes a redundant load/store if the SSE-class value is already
12811 // in memory, such as if it is on the callstack.
12812 if (isScalarFPTypeInSSEReg(TheVT)) {
12813 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12814 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12815 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12817 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12819 Chain, StackSlot, DAG.getValueType(TheVT)
12822 MachineMemOperand *MMO =
12823 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12824 MachineMemOperand::MOLoad, MemSize, MemSize);
12825 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12826 Chain = Value.getValue(1);
12827 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12828 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12831 MachineMemOperand *MMO =
12832 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12833 MachineMemOperand::MOStore, MemSize, MemSize);
12835 if (UnsignedFixup) {
12837 // Insert the FIST, load its result as two i32's,
12838 // and XOR the high i32 with Adjust.
12840 SDValue FistOps[] = { Chain, Value, StackSlot };
12841 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12842 FistOps, DstTy, MMO);
12844 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12845 MachinePointerInfo(),
12846 false, false, false, 0);
12847 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12848 DAG.getConstant(4, DL, PtrVT));
12850 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12851 MachinePointerInfo(),
12852 false, false, false, 0);
12853 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12855 if (Subtarget->is64Bit()) {
12856 // Join High32 and Low32 into a 64-bit result.
12857 // (High32 << 32) | Low32
12858 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12859 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12860 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12861 DAG.getConstant(32, DL, MVT::i8));
12862 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12863 return std::make_pair(Result, SDValue());
12866 SDValue ResultOps[] = { Low32, High32 };
12868 SDValue pair = IsReplace
12869 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12870 : DAG.getMergeValues(ResultOps, DL);
12871 return std::make_pair(pair, SDValue());
12873 // Build the FP_TO_INT*_IN_MEM
12874 SDValue Ops[] = { Chain, Value, StackSlot };
12875 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12877 return std::make_pair(FIST, StackSlot);
12881 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12882 const X86Subtarget *Subtarget) {
12883 MVT VT = Op->getSimpleValueType(0);
12884 SDValue In = Op->getOperand(0);
12885 MVT InVT = In.getSimpleValueType();
12888 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12889 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12891 // Optimize vectors in AVX mode:
12894 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12895 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12896 // Concat upper and lower parts.
12899 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12900 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12901 // Concat upper and lower parts.
12904 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12905 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12906 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12909 if (Subtarget->hasInt256())
12910 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12912 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12913 SDValue Undef = DAG.getUNDEF(InVT);
12914 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12915 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12916 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12918 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12919 VT.getVectorNumElements()/2);
12921 OpLo = DAG.getBitcast(HVT, OpLo);
12922 OpHi = DAG.getBitcast(HVT, OpHi);
12924 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12927 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12928 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12929 MVT VT = Op->getSimpleValueType(0);
12930 SDValue In = Op->getOperand(0);
12931 MVT InVT = In.getSimpleValueType();
12933 unsigned int NumElts = VT.getVectorNumElements();
12934 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12937 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12938 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12940 assert(InVT.getVectorElementType() == MVT::i1);
12941 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12943 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12945 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12947 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12948 if (VT.is512BitVector())
12950 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12953 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12954 SelectionDAG &DAG) {
12955 if (Subtarget->hasFp256())
12956 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12962 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12963 SelectionDAG &DAG) {
12965 MVT VT = Op.getSimpleValueType();
12966 SDValue In = Op.getOperand(0);
12967 MVT SVT = In.getSimpleValueType();
12969 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12970 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12972 if (Subtarget->hasFp256())
12973 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12976 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12977 VT.getVectorNumElements() != SVT.getVectorNumElements());
12981 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12983 MVT VT = Op.getSimpleValueType();
12984 SDValue In = Op.getOperand(0);
12985 MVT InVT = In.getSimpleValueType();
12987 if (VT == MVT::i1) {
12988 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12989 "Invalid scalar TRUNCATE operation");
12990 if (InVT.getSizeInBits() >= 32)
12992 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12993 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12995 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12996 "Invalid TRUNCATE operation");
12998 // move vector to mask - truncate solution for SKX
12999 if (VT.getVectorElementType() == MVT::i1) {
13000 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13001 Subtarget->hasBWI())
13002 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13003 if ((InVT.is256BitVector() || InVT.is128BitVector())
13004 && InVT.getScalarSizeInBits() <= 16 &&
13005 Subtarget->hasBWI() && Subtarget->hasVLX())
13006 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13007 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13008 Subtarget->hasDQI())
13009 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13010 if ((InVT.is256BitVector() || InVT.is128BitVector())
13011 && InVT.getScalarSizeInBits() >= 32 &&
13012 Subtarget->hasDQI() && Subtarget->hasVLX())
13013 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13016 if (VT.getVectorElementType() == MVT::i1) {
13017 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13018 unsigned NumElts = InVT.getVectorNumElements();
13019 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13020 if (InVT.getSizeInBits() < 512) {
13021 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13022 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13027 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13028 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13029 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13032 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13033 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13034 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13035 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13037 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13038 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13039 if (Subtarget->hasInt256()) {
13040 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13041 In = DAG.getBitcast(MVT::v8i32, In);
13042 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13044 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13045 DAG.getIntPtrConstant(0, DL));
13048 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13049 DAG.getIntPtrConstant(0, DL));
13050 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13051 DAG.getIntPtrConstant(2, DL));
13052 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13053 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13054 static const int ShufMask[] = {0, 2, 4, 6};
13055 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13058 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13059 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13060 if (Subtarget->hasInt256()) {
13061 In = DAG.getBitcast(MVT::v32i8, In);
13063 SmallVector<SDValue,32> pshufbMask;
13064 for (unsigned i = 0; i < 2; ++i) {
13065 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13066 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13067 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13068 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13069 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13070 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13071 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13072 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13073 for (unsigned j = 0; j < 8; ++j)
13074 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13076 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13077 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13078 In = DAG.getBitcast(MVT::v4i64, In);
13080 static const int ShufMask[] = {0, 2, -1, -1};
13081 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13083 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13084 DAG.getIntPtrConstant(0, DL));
13085 return DAG.getBitcast(VT, In);
13088 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13089 DAG.getIntPtrConstant(0, DL));
13091 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13092 DAG.getIntPtrConstant(4, DL));
13094 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13095 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13097 // The PSHUFB mask:
13098 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13099 -1, -1, -1, -1, -1, -1, -1, -1};
13101 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13102 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13103 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13105 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13106 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13108 // The MOVLHPS Mask:
13109 static const int ShufMask2[] = {0, 1, 4, 5};
13110 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13111 return DAG.getBitcast(MVT::v8i16, res);
13114 // Handle truncation of V256 to V128 using shuffles.
13115 if (!VT.is128BitVector() || !InVT.is256BitVector())
13118 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13120 unsigned NumElems = VT.getVectorNumElements();
13121 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13123 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13124 // Prepare truncation shuffle mask
13125 for (unsigned i = 0; i != NumElems; ++i)
13126 MaskVec[i] = i * 2;
13127 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13128 DAG.getUNDEF(NVT), &MaskVec[0]);
13129 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13130 DAG.getIntPtrConstant(0, DL));
13133 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13134 SelectionDAG &DAG) const {
13135 assert(!Op.getSimpleValueType().isVector());
13137 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13138 /*IsSigned=*/ true, /*IsReplace=*/ false);
13139 SDValue FIST = Vals.first, StackSlot = Vals.second;
13140 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13141 if (!FIST.getNode())
13144 if (StackSlot.getNode())
13145 // Load the result.
13146 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13147 FIST, StackSlot, MachinePointerInfo(),
13148 false, false, false, 0);
13150 // The node is the result.
13154 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13155 SelectionDAG &DAG) const {
13156 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13157 /*IsSigned=*/ false, /*IsReplace=*/ false);
13158 SDValue FIST = Vals.first, StackSlot = Vals.second;
13159 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13160 if (!FIST.getNode())
13163 if (StackSlot.getNode())
13164 // Load the result.
13165 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13166 FIST, StackSlot, MachinePointerInfo(),
13167 false, false, false, 0);
13169 // The node is the result.
13173 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13175 MVT VT = Op.getSimpleValueType();
13176 SDValue In = Op.getOperand(0);
13177 MVT SVT = In.getSimpleValueType();
13179 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13181 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13182 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13183 In, DAG.getUNDEF(SVT)));
13186 /// The only differences between FABS and FNEG are the mask and the logic op.
13187 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13188 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13189 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13190 "Wrong opcode for lowering FABS or FNEG.");
13192 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13194 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13195 // into an FNABS. We'll lower the FABS after that if it is still in use.
13197 for (SDNode *User : Op->uses())
13198 if (User->getOpcode() == ISD::FNEG)
13202 MVT VT = Op.getSimpleValueType();
13204 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13205 // decide if we should generate a 16-byte constant mask when we only need 4 or
13206 // 8 bytes for the scalar case.
13212 if (VT.isVector()) {
13214 EltVT = VT.getVectorElementType();
13215 NumElts = VT.getVectorNumElements();
13217 // There are no scalar bitwise logical SSE/AVX instructions, so we
13218 // generate a 16-byte vector constant and logic op even for the scalar case.
13219 // Using a 16-byte mask allows folding the load of the mask with
13220 // the logic op, so it can save (~4 bytes) on code size.
13221 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13223 NumElts = (VT == MVT::f64) ? 2 : 4;
13226 unsigned EltBits = EltVT.getSizeInBits();
13227 LLVMContext *Context = DAG.getContext();
13228 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13230 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13231 Constant *C = ConstantInt::get(*Context, MaskElt);
13232 C = ConstantVector::getSplat(NumElts, C);
13233 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13234 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13235 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13237 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13238 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13239 false, false, false, Alignment);
13241 SDValue Op0 = Op.getOperand(0);
13242 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13244 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13245 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13248 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13250 // For the scalar case extend to a 128-bit vector, perform the logic op,
13251 // and extract the scalar result back out.
13252 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13253 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13254 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13255 DAG.getIntPtrConstant(0, dl));
13258 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13259 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13260 LLVMContext *Context = DAG.getContext();
13261 SDValue Op0 = Op.getOperand(0);
13262 SDValue Op1 = Op.getOperand(1);
13264 MVT VT = Op.getSimpleValueType();
13265 MVT SrcVT = Op1.getSimpleValueType();
13267 // If second operand is smaller, extend it first.
13268 if (SrcVT.bitsLT(VT)) {
13269 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13272 // And if it is bigger, shrink it first.
13273 if (SrcVT.bitsGT(VT)) {
13274 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13278 // At this point the operands and the result should have the same
13279 // type, and that won't be f80 since that is not custom lowered.
13281 const fltSemantics &Sem =
13282 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13283 const unsigned SizeInBits = VT.getSizeInBits();
13285 SmallVector<Constant *, 4> CV(
13286 VT == MVT::f64 ? 2 : 4,
13287 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13289 // First, clear all bits but the sign bit from the second operand (sign).
13290 CV[0] = ConstantFP::get(*Context,
13291 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13292 Constant *C = ConstantVector::get(CV);
13293 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13294 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13296 // Perform all logic operations as 16-byte vectors because there are no
13297 // scalar FP logic instructions in SSE. This allows load folding of the
13298 // constants into the logic instructions.
13299 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13301 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13302 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13303 false, false, false, 16);
13304 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13305 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13307 // Next, clear the sign bit from the first operand (magnitude).
13308 // If it's a constant, we can clear it here.
13309 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13310 APFloat APF = Op0CN->getValueAPF();
13311 // If the magnitude is a positive zero, the sign bit alone is enough.
13312 if (APF.isPosZero())
13313 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13314 DAG.getIntPtrConstant(0, dl));
13316 CV[0] = ConstantFP::get(*Context, APF);
13318 CV[0] = ConstantFP::get(
13320 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13322 C = ConstantVector::get(CV);
13323 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13325 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13326 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13327 false, false, false, 16);
13328 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13329 if (!isa<ConstantFPSDNode>(Op0)) {
13330 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13331 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13333 // OR the magnitude value with the sign bit.
13334 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13335 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13336 DAG.getIntPtrConstant(0, dl));
13339 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13340 SDValue N0 = Op.getOperand(0);
13342 MVT VT = Op.getSimpleValueType();
13344 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13345 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13346 DAG.getConstant(1, dl, VT));
13347 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13350 // Check whether an OR'd tree is PTEST-able.
13351 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13352 SelectionDAG &DAG) {
13353 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13355 if (!Subtarget->hasSSE41())
13358 if (!Op->hasOneUse())
13361 SDNode *N = Op.getNode();
13364 SmallVector<SDValue, 8> Opnds;
13365 DenseMap<SDValue, unsigned> VecInMap;
13366 SmallVector<SDValue, 8> VecIns;
13367 EVT VT = MVT::Other;
13369 // Recognize a special case where a vector is casted into wide integer to
13371 Opnds.push_back(N->getOperand(0));
13372 Opnds.push_back(N->getOperand(1));
13374 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13375 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13376 // BFS traverse all OR'd operands.
13377 if (I->getOpcode() == ISD::OR) {
13378 Opnds.push_back(I->getOperand(0));
13379 Opnds.push_back(I->getOperand(1));
13380 // Re-evaluate the number of nodes to be traversed.
13381 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13385 // Quit if a non-EXTRACT_VECTOR_ELT
13386 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13389 // Quit if without a constant index.
13390 SDValue Idx = I->getOperand(1);
13391 if (!isa<ConstantSDNode>(Idx))
13394 SDValue ExtractedFromVec = I->getOperand(0);
13395 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13396 if (M == VecInMap.end()) {
13397 VT = ExtractedFromVec.getValueType();
13398 // Quit if not 128/256-bit vector.
13399 if (!VT.is128BitVector() && !VT.is256BitVector())
13401 // Quit if not the same type.
13402 if (VecInMap.begin() != VecInMap.end() &&
13403 VT != VecInMap.begin()->first.getValueType())
13405 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13406 VecIns.push_back(ExtractedFromVec);
13408 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13411 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13412 "Not extracted from 128-/256-bit vector.");
13414 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13416 for (DenseMap<SDValue, unsigned>::const_iterator
13417 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13418 // Quit if not all elements are used.
13419 if (I->second != FullMask)
13423 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13425 // Cast all vectors into TestVT for PTEST.
13426 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13427 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13429 // If more than one full vectors are evaluated, OR them first before PTEST.
13430 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13431 // Each iteration will OR 2 nodes and append the result until there is only
13432 // 1 node left, i.e. the final OR'd value of all vectors.
13433 SDValue LHS = VecIns[Slot];
13434 SDValue RHS = VecIns[Slot + 1];
13435 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13438 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13439 VecIns.back(), VecIns.back());
13442 /// \brief return true if \c Op has a use that doesn't just read flags.
13443 static bool hasNonFlagsUse(SDValue Op) {
13444 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13446 SDNode *User = *UI;
13447 unsigned UOpNo = UI.getOperandNo();
13448 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13449 // Look pass truncate.
13450 UOpNo = User->use_begin().getOperandNo();
13451 User = *User->use_begin();
13454 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13455 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13461 /// Emit nodes that will be selected as "test Op0,Op0", or something
13463 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13464 SelectionDAG &DAG) const {
13465 if (Op.getValueType() == MVT::i1) {
13466 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13467 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13468 DAG.getConstant(0, dl, MVT::i8));
13470 // CF and OF aren't always set the way we want. Determine which
13471 // of these we need.
13472 bool NeedCF = false;
13473 bool NeedOF = false;
13476 case X86::COND_A: case X86::COND_AE:
13477 case X86::COND_B: case X86::COND_BE:
13480 case X86::COND_G: case X86::COND_GE:
13481 case X86::COND_L: case X86::COND_LE:
13482 case X86::COND_O: case X86::COND_NO: {
13483 // Check if we really need to set the
13484 // Overflow flag. If NoSignedWrap is present
13485 // that is not actually needed.
13486 switch (Op->getOpcode()) {
13491 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13492 if (BinNode->Flags.hasNoSignedWrap())
13502 // See if we can use the EFLAGS value from the operand instead of
13503 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13504 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13505 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13506 // Emit a CMP with 0, which is the TEST pattern.
13507 //if (Op.getValueType() == MVT::i1)
13508 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13509 // DAG.getConstant(0, MVT::i1));
13510 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13511 DAG.getConstant(0, dl, Op.getValueType()));
13513 unsigned Opcode = 0;
13514 unsigned NumOperands = 0;
13516 // Truncate operations may prevent the merge of the SETCC instruction
13517 // and the arithmetic instruction before it. Attempt to truncate the operands
13518 // of the arithmetic instruction and use a reduced bit-width instruction.
13519 bool NeedTruncation = false;
13520 SDValue ArithOp = Op;
13521 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13522 SDValue Arith = Op->getOperand(0);
13523 // Both the trunc and the arithmetic op need to have one user each.
13524 if (Arith->hasOneUse())
13525 switch (Arith.getOpcode()) {
13532 NeedTruncation = true;
13538 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13539 // which may be the result of a CAST. We use the variable 'Op', which is the
13540 // non-casted variable when we check for possible users.
13541 switch (ArithOp.getOpcode()) {
13543 // Due to an isel shortcoming, be conservative if this add is likely to be
13544 // selected as part of a load-modify-store instruction. When the root node
13545 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13546 // uses of other nodes in the match, such as the ADD in this case. This
13547 // leads to the ADD being left around and reselected, with the result being
13548 // two adds in the output. Alas, even if none our users are stores, that
13549 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13550 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13551 // climbing the DAG back to the root, and it doesn't seem to be worth the
13553 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13554 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13555 if (UI->getOpcode() != ISD::CopyToReg &&
13556 UI->getOpcode() != ISD::SETCC &&
13557 UI->getOpcode() != ISD::STORE)
13560 if (ConstantSDNode *C =
13561 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13562 // An add of one will be selected as an INC.
13563 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13564 Opcode = X86ISD::INC;
13569 // An add of negative one (subtract of one) will be selected as a DEC.
13570 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13571 Opcode = X86ISD::DEC;
13577 // Otherwise use a regular EFLAGS-setting add.
13578 Opcode = X86ISD::ADD;
13583 // If we have a constant logical shift that's only used in a comparison
13584 // against zero turn it into an equivalent AND. This allows turning it into
13585 // a TEST instruction later.
13586 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13587 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13588 EVT VT = Op.getValueType();
13589 unsigned BitWidth = VT.getSizeInBits();
13590 unsigned ShAmt = Op->getConstantOperandVal(1);
13591 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13593 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13594 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13595 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13596 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13598 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13599 DAG.getConstant(Mask, dl, VT));
13600 DAG.ReplaceAllUsesWith(Op, New);
13606 // If the primary and result isn't used, don't bother using X86ISD::AND,
13607 // because a TEST instruction will be better.
13608 if (!hasNonFlagsUse(Op))
13614 // Due to the ISEL shortcoming noted above, be conservative if this op is
13615 // likely to be selected as part of a load-modify-store instruction.
13616 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13617 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13618 if (UI->getOpcode() == ISD::STORE)
13621 // Otherwise use a regular EFLAGS-setting instruction.
13622 switch (ArithOp.getOpcode()) {
13623 default: llvm_unreachable("unexpected operator!");
13624 case ISD::SUB: Opcode = X86ISD::SUB; break;
13625 case ISD::XOR: Opcode = X86ISD::XOR; break;
13626 case ISD::AND: Opcode = X86ISD::AND; break;
13628 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13629 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13630 if (EFLAGS.getNode())
13633 Opcode = X86ISD::OR;
13647 return SDValue(Op.getNode(), 1);
13653 // If we found that truncation is beneficial, perform the truncation and
13655 if (NeedTruncation) {
13656 EVT VT = Op.getValueType();
13657 SDValue WideVal = Op->getOperand(0);
13658 EVT WideVT = WideVal.getValueType();
13659 unsigned ConvertedOp = 0;
13660 // Use a target machine opcode to prevent further DAGCombine
13661 // optimizations that may separate the arithmetic operations
13662 // from the setcc node.
13663 switch (WideVal.getOpcode()) {
13665 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13666 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13667 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13668 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13669 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13674 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13675 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13676 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13677 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13683 // Emit a CMP with 0, which is the TEST pattern.
13684 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13685 DAG.getConstant(0, dl, Op.getValueType()));
13687 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13688 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13690 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13691 DAG.ReplaceAllUsesWith(Op, New);
13692 return SDValue(New.getNode(), 1);
13695 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13697 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13698 SDLoc dl, SelectionDAG &DAG) const {
13699 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13700 if (C->getAPIntValue() == 0)
13701 return EmitTest(Op0, X86CC, dl, DAG);
13703 if (Op0.getValueType() == MVT::i1)
13704 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13707 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13708 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13709 // Do the comparison at i32 if it's smaller, besides the Atom case.
13710 // This avoids subregister aliasing issues. Keep the smaller reference
13711 // if we're optimizing for size, however, as that'll allow better folding
13712 // of memory operations.
13713 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13714 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13715 !Subtarget->isAtom()) {
13716 unsigned ExtendOp =
13717 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13718 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13719 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13721 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13722 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13723 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13725 return SDValue(Sub.getNode(), 1);
13727 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13730 /// Convert a comparison if required by the subtarget.
13731 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13732 SelectionDAG &DAG) const {
13733 // If the subtarget does not support the FUCOMI instruction, floating-point
13734 // comparisons have to be converted.
13735 if (Subtarget->hasCMov() ||
13736 Cmp.getOpcode() != X86ISD::CMP ||
13737 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13738 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13741 // The instruction selector will select an FUCOM instruction instead of
13742 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13743 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13744 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13746 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13747 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13748 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13749 DAG.getConstant(8, dl, MVT::i8));
13750 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13751 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13754 /// The minimum architected relative accuracy is 2^-12. We need one
13755 /// Newton-Raphson step to have a good float result (24 bits of precision).
13756 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13757 DAGCombinerInfo &DCI,
13758 unsigned &RefinementSteps,
13759 bool &UseOneConstNR) const {
13760 EVT VT = Op.getValueType();
13761 const char *RecipOp;
13763 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13764 // TODO: Add support for AVX512 (v16f32).
13765 // It is likely not profitable to do this for f64 because a double-precision
13766 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13767 // instructions: convert to single, rsqrtss, convert back to double, refine
13768 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13769 // along with FMA, this could be a throughput win.
13770 if (VT == MVT::f32 && Subtarget->hasSSE1())
13772 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13773 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13774 RecipOp = "vec-sqrtf";
13778 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13779 if (!Recips.isEnabled(RecipOp))
13782 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13783 UseOneConstNR = false;
13784 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13787 /// The minimum architected relative accuracy is 2^-12. We need one
13788 /// Newton-Raphson step to have a good float result (24 bits of precision).
13789 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13790 DAGCombinerInfo &DCI,
13791 unsigned &RefinementSteps) const {
13792 EVT VT = Op.getValueType();
13793 const char *RecipOp;
13795 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13796 // TODO: Add support for AVX512 (v16f32).
13797 // It is likely not profitable to do this for f64 because a double-precision
13798 // reciprocal estimate with refinement on x86 prior to FMA requires
13799 // 15 instructions: convert to single, rcpss, convert back to double, refine
13800 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13801 // along with FMA, this could be a throughput win.
13802 if (VT == MVT::f32 && Subtarget->hasSSE1())
13804 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13805 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13806 RecipOp = "vec-divf";
13810 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13811 if (!Recips.isEnabled(RecipOp))
13814 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13815 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13818 /// If we have at least two divisions that use the same divisor, convert to
13819 /// multplication by a reciprocal. This may need to be adjusted for a given
13820 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13821 /// This is because we still need one division to calculate the reciprocal and
13822 /// then we need two multiplies by that reciprocal as replacements for the
13823 /// original divisions.
13824 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13828 static bool isAllOnes(SDValue V) {
13829 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13830 return C && C->isAllOnesValue();
13833 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13834 /// if it's possible.
13835 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13836 SDLoc dl, SelectionDAG &DAG) const {
13837 SDValue Op0 = And.getOperand(0);
13838 SDValue Op1 = And.getOperand(1);
13839 if (Op0.getOpcode() == ISD::TRUNCATE)
13840 Op0 = Op0.getOperand(0);
13841 if (Op1.getOpcode() == ISD::TRUNCATE)
13842 Op1 = Op1.getOperand(0);
13845 if (Op1.getOpcode() == ISD::SHL)
13846 std::swap(Op0, Op1);
13847 if (Op0.getOpcode() == ISD::SHL) {
13848 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13849 if (And00C->getZExtValue() == 1) {
13850 // If we looked past a truncate, check that it's only truncating away
13852 unsigned BitWidth = Op0.getValueSizeInBits();
13853 unsigned AndBitWidth = And.getValueSizeInBits();
13854 if (BitWidth > AndBitWidth) {
13856 DAG.computeKnownBits(Op0, Zeros, Ones);
13857 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13861 RHS = Op0.getOperand(1);
13863 } else if (Op1.getOpcode() == ISD::Constant) {
13864 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13865 uint64_t AndRHSVal = AndRHS->getZExtValue();
13866 SDValue AndLHS = Op0;
13868 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13869 LHS = AndLHS.getOperand(0);
13870 RHS = AndLHS.getOperand(1);
13873 // Use BT if the immediate can't be encoded in a TEST instruction.
13874 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13876 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13880 if (LHS.getNode()) {
13881 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13882 // instruction. Since the shift amount is in-range-or-undefined, we know
13883 // that doing a bittest on the i32 value is ok. We extend to i32 because
13884 // the encoding for the i16 version is larger than the i32 version.
13885 // Also promote i16 to i32 for performance / code size reason.
13886 if (LHS.getValueType() == MVT::i8 ||
13887 LHS.getValueType() == MVT::i16)
13888 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13890 // If the operand types disagree, extend the shift amount to match. Since
13891 // BT ignores high bits (like shifts) we can use anyextend.
13892 if (LHS.getValueType() != RHS.getValueType())
13893 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13895 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13896 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13897 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13898 DAG.getConstant(Cond, dl, MVT::i8), BT);
13904 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13906 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13911 // SSE Condition code mapping:
13920 switch (SetCCOpcode) {
13921 default: llvm_unreachable("Unexpected SETCC condition");
13923 case ISD::SETEQ: SSECC = 0; break;
13925 case ISD::SETGT: Swap = true; // Fallthrough
13927 case ISD::SETOLT: SSECC = 1; break;
13929 case ISD::SETGE: Swap = true; // Fallthrough
13931 case ISD::SETOLE: SSECC = 2; break;
13932 case ISD::SETUO: SSECC = 3; break;
13934 case ISD::SETNE: SSECC = 4; break;
13935 case ISD::SETULE: Swap = true; // Fallthrough
13936 case ISD::SETUGE: SSECC = 5; break;
13937 case ISD::SETULT: Swap = true; // Fallthrough
13938 case ISD::SETUGT: SSECC = 6; break;
13939 case ISD::SETO: SSECC = 7; break;
13941 case ISD::SETONE: SSECC = 8; break;
13944 std::swap(Op0, Op1);
13949 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13950 // ones, and then concatenate the result back.
13951 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13952 MVT VT = Op.getSimpleValueType();
13954 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13955 "Unsupported value type for operation");
13957 unsigned NumElems = VT.getVectorNumElements();
13959 SDValue CC = Op.getOperand(2);
13961 // Extract the LHS vectors
13962 SDValue LHS = Op.getOperand(0);
13963 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13964 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13966 // Extract the RHS vectors
13967 SDValue RHS = Op.getOperand(1);
13968 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13969 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13971 // Issue the operation on the smaller types and concatenate the result back
13972 MVT EltVT = VT.getVectorElementType();
13973 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13974 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13975 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13976 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13979 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13980 SDValue Op0 = Op.getOperand(0);
13981 SDValue Op1 = Op.getOperand(1);
13982 SDValue CC = Op.getOperand(2);
13983 MVT VT = Op.getSimpleValueType();
13986 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13987 "Unexpected type for boolean compare operation");
13988 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13989 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13990 DAG.getConstant(-1, dl, VT));
13991 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13992 DAG.getConstant(-1, dl, VT));
13993 switch (SetCCOpcode) {
13994 default: llvm_unreachable("Unexpected SETCC condition");
13996 // (x == y) -> ~(x ^ y)
13997 return DAG.getNode(ISD::XOR, dl, VT,
13998 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13999 DAG.getConstant(-1, dl, VT));
14001 // (x != y) -> (x ^ y)
14002 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14005 // (x > y) -> (x & ~y)
14006 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14009 // (x < y) -> (~x & y)
14010 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14013 // (x <= y) -> (~x | y)
14014 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14017 // (x >=y) -> (x | ~y)
14018 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14022 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14023 const X86Subtarget *Subtarget) {
14024 SDValue Op0 = Op.getOperand(0);
14025 SDValue Op1 = Op.getOperand(1);
14026 SDValue CC = Op.getOperand(2);
14027 MVT VT = Op.getSimpleValueType();
14030 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14031 Op.getValueType().getScalarType() == MVT::i1 &&
14032 "Cannot set masked compare for this operation");
14034 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14036 bool Unsigned = false;
14039 switch (SetCCOpcode) {
14040 default: llvm_unreachable("Unexpected SETCC condition");
14041 case ISD::SETNE: SSECC = 4; break;
14042 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14043 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14044 case ISD::SETLT: Swap = true; //fall-through
14045 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14046 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14047 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14048 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14049 case ISD::SETULE: Unsigned = true; //fall-through
14050 case ISD::SETLE: SSECC = 2; break;
14054 std::swap(Op0, Op1);
14056 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14057 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14058 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14059 DAG.getConstant(SSECC, dl, MVT::i8));
14062 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14063 /// operand \p Op1. If non-trivial (for example because it's not constant)
14064 /// return an empty value.
14065 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14067 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14071 MVT VT = Op1.getSimpleValueType();
14072 MVT EVT = VT.getVectorElementType();
14073 unsigned n = VT.getVectorNumElements();
14074 SmallVector<SDValue, 8> ULTOp1;
14076 for (unsigned i = 0; i < n; ++i) {
14077 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14078 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14081 // Avoid underflow.
14082 APInt Val = Elt->getAPIntValue();
14086 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14089 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14092 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14093 SelectionDAG &DAG) {
14094 SDValue Op0 = Op.getOperand(0);
14095 SDValue Op1 = Op.getOperand(1);
14096 SDValue CC = Op.getOperand(2);
14097 MVT VT = Op.getSimpleValueType();
14098 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14099 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14104 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14105 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14108 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14109 unsigned Opc = X86ISD::CMPP;
14110 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14111 assert(VT.getVectorNumElements() <= 16);
14112 Opc = X86ISD::CMPM;
14114 // In the two special cases we can't handle, emit two comparisons.
14117 unsigned CombineOpc;
14118 if (SetCCOpcode == ISD::SETUEQ) {
14119 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14121 assert(SetCCOpcode == ISD::SETONE);
14122 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14125 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14126 DAG.getConstant(CC0, dl, MVT::i8));
14127 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14128 DAG.getConstant(CC1, dl, MVT::i8));
14129 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14131 // Handle all other FP comparisons here.
14132 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14133 DAG.getConstant(SSECC, dl, MVT::i8));
14136 // Break 256-bit integer vector compare into smaller ones.
14137 if (VT.is256BitVector() && !Subtarget->hasInt256())
14138 return Lower256IntVSETCC(Op, DAG);
14140 EVT OpVT = Op1.getValueType();
14141 if (OpVT.getVectorElementType() == MVT::i1)
14142 return LowerBoolVSETCC_AVX512(Op, DAG);
14144 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14145 if (Subtarget->hasAVX512()) {
14146 if (Op1.getValueType().is512BitVector() ||
14147 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14148 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14149 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14151 // In AVX-512 architecture setcc returns mask with i1 elements,
14152 // But there is no compare instruction for i8 and i16 elements in KNL.
14153 // We are not talking about 512-bit operands in this case, these
14154 // types are illegal.
14156 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14157 OpVT.getVectorElementType().getSizeInBits() >= 8))
14158 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14159 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14162 // We are handling one of the integer comparisons here. Since SSE only has
14163 // GT and EQ comparisons for integer, swapping operands and multiple
14164 // operations may be required for some comparisons.
14166 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14167 bool Subus = false;
14169 switch (SetCCOpcode) {
14170 default: llvm_unreachable("Unexpected SETCC condition");
14171 case ISD::SETNE: Invert = true;
14172 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14173 case ISD::SETLT: Swap = true;
14174 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14175 case ISD::SETGE: Swap = true;
14176 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14177 Invert = true; break;
14178 case ISD::SETULT: Swap = true;
14179 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14180 FlipSigns = true; break;
14181 case ISD::SETUGE: Swap = true;
14182 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14183 FlipSigns = true; Invert = true; break;
14186 // Special case: Use min/max operations for SETULE/SETUGE
14187 MVT VET = VT.getVectorElementType();
14189 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14190 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14193 switch (SetCCOpcode) {
14195 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14196 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14199 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14202 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14203 if (!MinMax && hasSubus) {
14204 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14206 // t = psubus Op0, Op1
14207 // pcmpeq t, <0..0>
14208 switch (SetCCOpcode) {
14210 case ISD::SETULT: {
14211 // If the comparison is against a constant we can turn this into a
14212 // setule. With psubus, setule does not require a swap. This is
14213 // beneficial because the constant in the register is no longer
14214 // destructed as the destination so it can be hoisted out of a loop.
14215 // Only do this pre-AVX since vpcmp* is no longer destructive.
14216 if (Subtarget->hasAVX())
14218 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14219 if (ULEOp1.getNode()) {
14221 Subus = true; Invert = false; Swap = false;
14225 // Psubus is better than flip-sign because it requires no inversion.
14226 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14227 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14231 Opc = X86ISD::SUBUS;
14237 std::swap(Op0, Op1);
14239 // Check that the operation in question is available (most are plain SSE2,
14240 // but PCMPGTQ and PCMPEQQ have different requirements).
14241 if (VT == MVT::v2i64) {
14242 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14243 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14245 // First cast everything to the right type.
14246 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14247 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14249 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14250 // bits of the inputs before performing those operations. The lower
14251 // compare is always unsigned.
14254 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14256 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14257 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14258 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14259 Sign, Zero, Sign, Zero);
14261 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14262 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14264 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14265 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14266 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14268 // Create masks for only the low parts/high parts of the 64 bit integers.
14269 static const int MaskHi[] = { 1, 1, 3, 3 };
14270 static const int MaskLo[] = { 0, 0, 2, 2 };
14271 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14272 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14273 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14275 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14276 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14279 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14281 return DAG.getBitcast(VT, Result);
14284 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14285 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14286 // pcmpeqd + pshufd + pand.
14287 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14289 // First cast everything to the right type.
14290 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14291 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14294 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14296 // Make sure the lower and upper halves are both all-ones.
14297 static const int Mask[] = { 1, 0, 3, 2 };
14298 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14299 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14302 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14304 return DAG.getBitcast(VT, Result);
14308 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14309 // bits of the inputs before performing those operations.
14311 EVT EltVT = VT.getVectorElementType();
14312 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14314 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14315 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14318 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14320 // If the logical-not of the result is required, perform that now.
14322 Result = DAG.getNOT(dl, Result, VT);
14325 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14328 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14329 getZeroVector(VT, Subtarget, DAG, dl));
14334 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14336 MVT VT = Op.getSimpleValueType();
14338 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14340 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14341 && "SetCC type must be 8-bit or 1-bit integer");
14342 SDValue Op0 = Op.getOperand(0);
14343 SDValue Op1 = Op.getOperand(1);
14345 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14347 // Optimize to BT if possible.
14348 // Lower (X & (1 << N)) == 0 to BT(X, N).
14349 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14350 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14351 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14352 Op1.getOpcode() == ISD::Constant &&
14353 cast<ConstantSDNode>(Op1)->isNullValue() &&
14354 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14355 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14356 if (NewSetCC.getNode()) {
14358 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14363 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14365 if (Op1.getOpcode() == ISD::Constant &&
14366 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14367 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14368 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14370 // If the input is a setcc, then reuse the input setcc or use a new one with
14371 // the inverted condition.
14372 if (Op0.getOpcode() == X86ISD::SETCC) {
14373 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14374 bool Invert = (CC == ISD::SETNE) ^
14375 cast<ConstantSDNode>(Op1)->isNullValue();
14379 CCode = X86::GetOppositeBranchCondition(CCode);
14380 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14381 DAG.getConstant(CCode, dl, MVT::i8),
14382 Op0.getOperand(1));
14384 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14388 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14389 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14390 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14392 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14393 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14396 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14397 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14398 if (X86CC == X86::COND_INVALID)
14401 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14402 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14403 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14404 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14406 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14410 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14411 static bool isX86LogicalCmp(SDValue Op) {
14412 unsigned Opc = Op.getNode()->getOpcode();
14413 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14414 Opc == X86ISD::SAHF)
14416 if (Op.getResNo() == 1 &&
14417 (Opc == X86ISD::ADD ||
14418 Opc == X86ISD::SUB ||
14419 Opc == X86ISD::ADC ||
14420 Opc == X86ISD::SBB ||
14421 Opc == X86ISD::SMUL ||
14422 Opc == X86ISD::UMUL ||
14423 Opc == X86ISD::INC ||
14424 Opc == X86ISD::DEC ||
14425 Opc == X86ISD::OR ||
14426 Opc == X86ISD::XOR ||
14427 Opc == X86ISD::AND))
14430 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14436 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14437 if (V.getOpcode() != ISD::TRUNCATE)
14440 SDValue VOp0 = V.getOperand(0);
14441 unsigned InBits = VOp0.getValueSizeInBits();
14442 unsigned Bits = V.getValueSizeInBits();
14443 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14446 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14447 bool addTest = true;
14448 SDValue Cond = Op.getOperand(0);
14449 SDValue Op1 = Op.getOperand(1);
14450 SDValue Op2 = Op.getOperand(2);
14452 EVT VT = Op1.getValueType();
14455 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14456 // are available or VBLENDV if AVX is available.
14457 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14458 if (Cond.getOpcode() == ISD::SETCC &&
14459 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14460 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14461 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14462 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14463 int SSECC = translateX86FSETCC(
14464 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14467 if (Subtarget->hasAVX512()) {
14468 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14469 DAG.getConstant(SSECC, DL, MVT::i8));
14470 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14473 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14474 DAG.getConstant(SSECC, DL, MVT::i8));
14476 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14477 // of 3 logic instructions for size savings and potentially speed.
14478 // Unfortunately, there is no scalar form of VBLENDV.
14480 // If either operand is a constant, don't try this. We can expect to
14481 // optimize away at least one of the logic instructions later in that
14482 // case, so that sequence would be faster than a variable blend.
14484 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14485 // uses XMM0 as the selection register. That may need just as many
14486 // instructions as the AND/ANDN/OR sequence due to register moves, so
14489 if (Subtarget->hasAVX() &&
14490 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14492 // Convert to vectors, do a VSELECT, and convert back to scalar.
14493 // All of the conversions should be optimized away.
14495 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14496 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14497 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14498 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14500 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14501 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14503 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14505 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14506 VSel, DAG.getIntPtrConstant(0, DL));
14508 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14509 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14510 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14514 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14516 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14517 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14518 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14519 Op1Scalar = Op1.getOperand(0);
14521 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14522 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14523 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14524 Op2Scalar = Op2.getOperand(0);
14525 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14526 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14527 Op1Scalar.getValueType(),
14528 Cond, Op1Scalar, Op2Scalar);
14529 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14530 return DAG.getBitcast(VT, newSelect);
14531 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14532 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14533 DAG.getIntPtrConstant(0, DL));
14537 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14538 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14539 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14540 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14541 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14542 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14543 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14545 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14548 if (Cond.getOpcode() == ISD::SETCC) {
14549 SDValue NewCond = LowerSETCC(Cond, DAG);
14550 if (NewCond.getNode())
14554 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14555 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14556 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14557 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14558 if (Cond.getOpcode() == X86ISD::SETCC &&
14559 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14560 isZero(Cond.getOperand(1).getOperand(1))) {
14561 SDValue Cmp = Cond.getOperand(1);
14563 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14565 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14566 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14567 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14569 SDValue CmpOp0 = Cmp.getOperand(0);
14570 // Apply further optimizations for special cases
14571 // (select (x != 0), -1, 0) -> neg & sbb
14572 // (select (x == 0), 0, -1) -> neg & sbb
14573 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14574 if (YC->isNullValue() &&
14575 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14576 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14577 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14578 DAG.getConstant(0, DL,
14579 CmpOp0.getValueType()),
14581 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14582 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14583 SDValue(Neg.getNode(), 1));
14587 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14588 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14589 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14591 SDValue Res = // Res = 0 or -1.
14592 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14593 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14595 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14596 Res = DAG.getNOT(DL, Res, Res.getValueType());
14598 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14599 if (!N2C || !N2C->isNullValue())
14600 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14605 // Look past (and (setcc_carry (cmp ...)), 1).
14606 if (Cond.getOpcode() == ISD::AND &&
14607 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14608 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14609 if (C && C->getAPIntValue() == 1)
14610 Cond = Cond.getOperand(0);
14613 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14614 // setting operand in place of the X86ISD::SETCC.
14615 unsigned CondOpcode = Cond.getOpcode();
14616 if (CondOpcode == X86ISD::SETCC ||
14617 CondOpcode == X86ISD::SETCC_CARRY) {
14618 CC = Cond.getOperand(0);
14620 SDValue Cmp = Cond.getOperand(1);
14621 unsigned Opc = Cmp.getOpcode();
14622 MVT VT = Op.getSimpleValueType();
14624 bool IllegalFPCMov = false;
14625 if (VT.isFloatingPoint() && !VT.isVector() &&
14626 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14627 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14629 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14630 Opc == X86ISD::BT) { // FIXME
14634 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14635 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14636 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14637 Cond.getOperand(0).getValueType() != MVT::i8)) {
14638 SDValue LHS = Cond.getOperand(0);
14639 SDValue RHS = Cond.getOperand(1);
14640 unsigned X86Opcode;
14643 switch (CondOpcode) {
14644 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14645 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14646 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14647 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14648 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14649 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14650 default: llvm_unreachable("unexpected overflowing operator");
14652 if (CondOpcode == ISD::UMULO)
14653 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14656 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14658 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14660 if (CondOpcode == ISD::UMULO)
14661 Cond = X86Op.getValue(2);
14663 Cond = X86Op.getValue(1);
14665 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14670 // Look past the truncate if the high bits are known zero.
14671 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14672 Cond = Cond.getOperand(0);
14674 // We know the result of AND is compared against zero. Try to match
14676 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14677 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14678 if (NewSetCC.getNode()) {
14679 CC = NewSetCC.getOperand(0);
14680 Cond = NewSetCC.getOperand(1);
14687 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14688 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14691 // a < b ? -1 : 0 -> RES = ~setcc_carry
14692 // a < b ? 0 : -1 -> RES = setcc_carry
14693 // a >= b ? -1 : 0 -> RES = setcc_carry
14694 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14695 if (Cond.getOpcode() == X86ISD::SUB) {
14696 Cond = ConvertCmpIfNecessary(Cond, DAG);
14697 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14699 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14700 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14701 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14702 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14704 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14705 return DAG.getNOT(DL, Res, Res.getValueType());
14710 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14711 // widen the cmov and push the truncate through. This avoids introducing a new
14712 // branch during isel and doesn't add any extensions.
14713 if (Op.getValueType() == MVT::i8 &&
14714 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14715 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14716 if (T1.getValueType() == T2.getValueType() &&
14717 // Blacklist CopyFromReg to avoid partial register stalls.
14718 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14719 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14720 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14721 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14725 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14726 // condition is true.
14727 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14728 SDValue Ops[] = { Op2, Op1, CC, Cond };
14729 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14732 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14733 const X86Subtarget *Subtarget,
14734 SelectionDAG &DAG) {
14735 MVT VT = Op->getSimpleValueType(0);
14736 SDValue In = Op->getOperand(0);
14737 MVT InVT = In.getSimpleValueType();
14738 MVT VTElt = VT.getVectorElementType();
14739 MVT InVTElt = InVT.getVectorElementType();
14743 if ((InVTElt == MVT::i1) &&
14744 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14745 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14747 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14748 VTElt.getSizeInBits() <= 16)) ||
14750 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14751 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14753 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14754 VTElt.getSizeInBits() >= 32))))
14755 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14757 unsigned int NumElts = VT.getVectorNumElements();
14759 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14762 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14763 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14764 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14765 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14768 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14769 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14771 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14774 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14776 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14777 if (VT.is512BitVector())
14779 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14782 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14783 const X86Subtarget *Subtarget,
14784 SelectionDAG &DAG) {
14785 SDValue In = Op->getOperand(0);
14786 MVT VT = Op->getSimpleValueType(0);
14787 MVT InVT = In.getSimpleValueType();
14788 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14790 MVT InSVT = InVT.getScalarType();
14791 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14793 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14795 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14800 // SSE41 targets can use the pmovsx* instructions directly.
14801 if (Subtarget->hasSSE41())
14802 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14804 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14808 // As SRAI is only available on i16/i32 types, we expand only up to i32
14809 // and handle i64 separately.
14810 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14811 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14812 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14813 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14814 Curr = DAG.getBitcast(CurrVT, Curr);
14817 SDValue SignExt = Curr;
14818 if (CurrVT != InVT) {
14819 unsigned SignExtShift =
14820 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14821 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14822 DAG.getConstant(SignExtShift, dl, MVT::i8));
14828 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14829 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14830 DAG.getConstant(31, dl, MVT::i8));
14831 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14832 return DAG.getBitcast(VT, Ext);
14838 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14839 SelectionDAG &DAG) {
14840 MVT VT = Op->getSimpleValueType(0);
14841 SDValue In = Op->getOperand(0);
14842 MVT InVT = In.getSimpleValueType();
14845 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14846 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14848 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14849 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14850 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14853 if (Subtarget->hasInt256())
14854 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14856 // Optimize vectors in AVX mode
14857 // Sign extend v8i16 to v8i32 and
14860 // Divide input vector into two parts
14861 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14862 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14863 // concat the vectors to original VT
14865 unsigned NumElems = InVT.getVectorNumElements();
14866 SDValue Undef = DAG.getUNDEF(InVT);
14868 SmallVector<int,8> ShufMask1(NumElems, -1);
14869 for (unsigned i = 0; i != NumElems/2; ++i)
14872 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14874 SmallVector<int,8> ShufMask2(NumElems, -1);
14875 for (unsigned i = 0; i != NumElems/2; ++i)
14876 ShufMask2[i] = i + NumElems/2;
14878 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14880 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14881 VT.getVectorNumElements()/2);
14883 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14884 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14886 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14889 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14890 // may emit an illegal shuffle but the expansion is still better than scalar
14891 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14892 // we'll emit a shuffle and a arithmetic shift.
14893 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14894 // TODO: It is possible to support ZExt by zeroing the undef values during
14895 // the shuffle phase or after the shuffle.
14896 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14897 SelectionDAG &DAG) {
14898 MVT RegVT = Op.getSimpleValueType();
14899 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14900 assert(RegVT.isInteger() &&
14901 "We only custom lower integer vector sext loads.");
14903 // Nothing useful we can do without SSE2 shuffles.
14904 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14906 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14908 EVT MemVT = Ld->getMemoryVT();
14909 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14910 unsigned RegSz = RegVT.getSizeInBits();
14912 ISD::LoadExtType Ext = Ld->getExtensionType();
14914 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14915 && "Only anyext and sext are currently implemented.");
14916 assert(MemVT != RegVT && "Cannot extend to the same type");
14917 assert(MemVT.isVector() && "Must load a vector from memory");
14919 unsigned NumElems = RegVT.getVectorNumElements();
14920 unsigned MemSz = MemVT.getSizeInBits();
14921 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14923 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14924 // The only way in which we have a legal 256-bit vector result but not the
14925 // integer 256-bit operations needed to directly lower a sextload is if we
14926 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14927 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14928 // correctly legalized. We do this late to allow the canonical form of
14929 // sextload to persist throughout the rest of the DAG combiner -- it wants
14930 // to fold together any extensions it can, and so will fuse a sign_extend
14931 // of an sextload into a sextload targeting a wider value.
14933 if (MemSz == 128) {
14934 // Just switch this to a normal load.
14935 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14936 "it must be a legal 128-bit vector "
14938 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14939 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14940 Ld->isInvariant(), Ld->getAlignment());
14942 assert(MemSz < 128 &&
14943 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14944 // Do an sext load to a 128-bit vector type. We want to use the same
14945 // number of elements, but elements half as wide. This will end up being
14946 // recursively lowered by this routine, but will succeed as we definitely
14947 // have all the necessary features if we're using AVX1.
14949 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14950 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14952 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14953 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14954 Ld->isNonTemporal(), Ld->isInvariant(),
14955 Ld->getAlignment());
14958 // Replace chain users with the new chain.
14959 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14960 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14962 // Finally, do a normal sign-extend to the desired register.
14963 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14966 // All sizes must be a power of two.
14967 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14968 "Non-power-of-two elements are not custom lowered!");
14970 // Attempt to load the original value using scalar loads.
14971 // Find the largest scalar type that divides the total loaded size.
14972 MVT SclrLoadTy = MVT::i8;
14973 for (MVT Tp : MVT::integer_valuetypes()) {
14974 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14979 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14980 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14982 SclrLoadTy = MVT::f64;
14984 // Calculate the number of scalar loads that we need to perform
14985 // in order to load our vector from memory.
14986 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14988 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14989 "Can only lower sext loads with a single scalar load!");
14991 unsigned loadRegZize = RegSz;
14992 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14995 // Represent our vector as a sequence of elements which are the
14996 // largest scalar that we can load.
14997 EVT LoadUnitVecVT = EVT::getVectorVT(
14998 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15000 // Represent the data using the same element type that is stored in
15001 // memory. In practice, we ''widen'' MemVT.
15003 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15004 loadRegZize / MemVT.getScalarType().getSizeInBits());
15006 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15007 "Invalid vector type");
15009 // We can't shuffle using an illegal type.
15010 assert(TLI.isTypeLegal(WideVecVT) &&
15011 "We only lower types that form legal widened vector types");
15013 SmallVector<SDValue, 8> Chains;
15014 SDValue Ptr = Ld->getBasePtr();
15015 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15016 TLI.getPointerTy(DAG.getDataLayout()));
15017 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15019 for (unsigned i = 0; i < NumLoads; ++i) {
15020 // Perform a single load.
15021 SDValue ScalarLoad =
15022 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15023 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15024 Ld->getAlignment());
15025 Chains.push_back(ScalarLoad.getValue(1));
15026 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15027 // another round of DAGCombining.
15029 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15031 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15032 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15034 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15037 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15039 // Bitcast the loaded value to a vector of the original element type, in
15040 // the size of the target vector type.
15041 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15042 unsigned SizeRatio = RegSz / MemSz;
15044 if (Ext == ISD::SEXTLOAD) {
15045 // If we have SSE4.1, we can directly emit a VSEXT node.
15046 if (Subtarget->hasSSE41()) {
15047 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15048 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15052 // Otherwise we'll shuffle the small elements in the high bits of the
15053 // larger type and perform an arithmetic shift. If the shift is not legal
15054 // it's better to scalarize.
15055 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15056 "We can't implement a sext load without an arithmetic right shift!");
15058 // Redistribute the loaded elements into the different locations.
15059 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15060 for (unsigned i = 0; i != NumElems; ++i)
15061 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15063 SDValue Shuff = DAG.getVectorShuffle(
15064 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15066 Shuff = DAG.getBitcast(RegVT, Shuff);
15068 // Build the arithmetic shift.
15069 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15070 MemVT.getVectorElementType().getSizeInBits();
15072 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
15073 DAG.getConstant(Amt, dl, RegVT));
15075 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15079 // Redistribute the loaded elements into the different locations.
15080 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15081 for (unsigned i = 0; i != NumElems; ++i)
15082 ShuffleVec[i * SizeRatio] = i;
15084 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15085 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15087 // Bitcast to the requested type.
15088 Shuff = DAG.getBitcast(RegVT, Shuff);
15089 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15093 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15094 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15095 // from the AND / OR.
15096 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15097 Opc = Op.getOpcode();
15098 if (Opc != ISD::OR && Opc != ISD::AND)
15100 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15101 Op.getOperand(0).hasOneUse() &&
15102 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15103 Op.getOperand(1).hasOneUse());
15106 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15107 // 1 and that the SETCC node has a single use.
15108 static bool isXor1OfSetCC(SDValue Op) {
15109 if (Op.getOpcode() != ISD::XOR)
15111 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15112 if (N1C && N1C->getAPIntValue() == 1) {
15113 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15114 Op.getOperand(0).hasOneUse();
15119 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15120 bool addTest = true;
15121 SDValue Chain = Op.getOperand(0);
15122 SDValue Cond = Op.getOperand(1);
15123 SDValue Dest = Op.getOperand(2);
15126 bool Inverted = false;
15128 if (Cond.getOpcode() == ISD::SETCC) {
15129 // Check for setcc([su]{add,sub,mul}o == 0).
15130 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15131 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15132 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15133 Cond.getOperand(0).getResNo() == 1 &&
15134 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15135 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15136 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15137 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15138 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15139 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15141 Cond = Cond.getOperand(0);
15143 SDValue NewCond = LowerSETCC(Cond, DAG);
15144 if (NewCond.getNode())
15149 // FIXME: LowerXALUO doesn't handle these!!
15150 else if (Cond.getOpcode() == X86ISD::ADD ||
15151 Cond.getOpcode() == X86ISD::SUB ||
15152 Cond.getOpcode() == X86ISD::SMUL ||
15153 Cond.getOpcode() == X86ISD::UMUL)
15154 Cond = LowerXALUO(Cond, DAG);
15157 // Look pass (and (setcc_carry (cmp ...)), 1).
15158 if (Cond.getOpcode() == ISD::AND &&
15159 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15160 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15161 if (C && C->getAPIntValue() == 1)
15162 Cond = Cond.getOperand(0);
15165 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15166 // setting operand in place of the X86ISD::SETCC.
15167 unsigned CondOpcode = Cond.getOpcode();
15168 if (CondOpcode == X86ISD::SETCC ||
15169 CondOpcode == X86ISD::SETCC_CARRY) {
15170 CC = Cond.getOperand(0);
15172 SDValue Cmp = Cond.getOperand(1);
15173 unsigned Opc = Cmp.getOpcode();
15174 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15175 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15179 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15183 // These can only come from an arithmetic instruction with overflow,
15184 // e.g. SADDO, UADDO.
15185 Cond = Cond.getNode()->getOperand(1);
15191 CondOpcode = Cond.getOpcode();
15192 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15193 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15194 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15195 Cond.getOperand(0).getValueType() != MVT::i8)) {
15196 SDValue LHS = Cond.getOperand(0);
15197 SDValue RHS = Cond.getOperand(1);
15198 unsigned X86Opcode;
15201 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15202 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15204 switch (CondOpcode) {
15205 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15207 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15209 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15212 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15213 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15215 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15217 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15220 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15221 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15222 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15223 default: llvm_unreachable("unexpected overflowing operator");
15226 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15227 if (CondOpcode == ISD::UMULO)
15228 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15231 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15233 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15235 if (CondOpcode == ISD::UMULO)
15236 Cond = X86Op.getValue(2);
15238 Cond = X86Op.getValue(1);
15240 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15244 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15245 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15246 if (CondOpc == ISD::OR) {
15247 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15248 // two branches instead of an explicit OR instruction with a
15250 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15251 isX86LogicalCmp(Cmp)) {
15252 CC = Cond.getOperand(0).getOperand(0);
15253 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15254 Chain, Dest, CC, Cmp);
15255 CC = Cond.getOperand(1).getOperand(0);
15259 } else { // ISD::AND
15260 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15261 // two branches instead of an explicit AND instruction with a
15262 // separate test. However, we only do this if this block doesn't
15263 // have a fall-through edge, because this requires an explicit
15264 // jmp when the condition is false.
15265 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15266 isX86LogicalCmp(Cmp) &&
15267 Op.getNode()->hasOneUse()) {
15268 X86::CondCode CCode =
15269 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15270 CCode = X86::GetOppositeBranchCondition(CCode);
15271 CC = DAG.getConstant(CCode, dl, MVT::i8);
15272 SDNode *User = *Op.getNode()->use_begin();
15273 // Look for an unconditional branch following this conditional branch.
15274 // We need this because we need to reverse the successors in order
15275 // to implement FCMP_OEQ.
15276 if (User->getOpcode() == ISD::BR) {
15277 SDValue FalseBB = User->getOperand(1);
15279 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15280 assert(NewBR == User);
15284 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15285 Chain, Dest, CC, Cmp);
15286 X86::CondCode CCode =
15287 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15288 CCode = X86::GetOppositeBranchCondition(CCode);
15289 CC = DAG.getConstant(CCode, dl, MVT::i8);
15295 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15296 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15297 // It should be transformed during dag combiner except when the condition
15298 // is set by a arithmetics with overflow node.
15299 X86::CondCode CCode =
15300 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15301 CCode = X86::GetOppositeBranchCondition(CCode);
15302 CC = DAG.getConstant(CCode, dl, MVT::i8);
15303 Cond = Cond.getOperand(0).getOperand(1);
15305 } else if (Cond.getOpcode() == ISD::SETCC &&
15306 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15307 // For FCMP_OEQ, we can emit
15308 // two branches instead of an explicit AND instruction with a
15309 // separate test. However, we only do this if this block doesn't
15310 // have a fall-through edge, because this requires an explicit
15311 // jmp when the condition is false.
15312 if (Op.getNode()->hasOneUse()) {
15313 SDNode *User = *Op.getNode()->use_begin();
15314 // Look for an unconditional branch following this conditional branch.
15315 // We need this because we need to reverse the successors in order
15316 // to implement FCMP_OEQ.
15317 if (User->getOpcode() == ISD::BR) {
15318 SDValue FalseBB = User->getOperand(1);
15320 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15321 assert(NewBR == User);
15325 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15326 Cond.getOperand(0), Cond.getOperand(1));
15327 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15328 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15329 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15330 Chain, Dest, CC, Cmp);
15331 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15336 } else if (Cond.getOpcode() == ISD::SETCC &&
15337 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15338 // For FCMP_UNE, we can emit
15339 // two branches instead of an explicit AND instruction with a
15340 // separate test. However, we only do this if this block doesn't
15341 // have a fall-through edge, because this requires an explicit
15342 // jmp when the condition is false.
15343 if (Op.getNode()->hasOneUse()) {
15344 SDNode *User = *Op.getNode()->use_begin();
15345 // Look for an unconditional branch following this conditional branch.
15346 // We need this because we need to reverse the successors in order
15347 // to implement FCMP_UNE.
15348 if (User->getOpcode() == ISD::BR) {
15349 SDValue FalseBB = User->getOperand(1);
15351 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15352 assert(NewBR == User);
15355 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15356 Cond.getOperand(0), Cond.getOperand(1));
15357 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15358 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15359 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15360 Chain, Dest, CC, Cmp);
15361 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15371 // Look pass the truncate if the high bits are known zero.
15372 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15373 Cond = Cond.getOperand(0);
15375 // We know the result of AND is compared against zero. Try to match
15377 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15378 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15379 if (NewSetCC.getNode()) {
15380 CC = NewSetCC.getOperand(0);
15381 Cond = NewSetCC.getOperand(1);
15388 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15389 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15390 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15392 Cond = ConvertCmpIfNecessary(Cond, DAG);
15393 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15394 Chain, Dest, CC, Cond);
15397 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15398 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15399 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15400 // that the guard pages used by the OS virtual memory manager are allocated in
15401 // correct sequence.
15403 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15404 SelectionDAG &DAG) const {
15405 MachineFunction &MF = DAG.getMachineFunction();
15406 bool SplitStack = MF.shouldSplitStack();
15407 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15413 SDNode* Node = Op.getNode();
15415 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15416 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15417 " not tell us which reg is the stack pointer!");
15418 EVT VT = Node->getValueType(0);
15419 SDValue Tmp1 = SDValue(Node, 0);
15420 SDValue Tmp2 = SDValue(Node, 1);
15421 SDValue Tmp3 = Node->getOperand(2);
15422 SDValue Chain = Tmp1.getOperand(0);
15424 // Chain the dynamic stack allocation so that it doesn't modify the stack
15425 // pointer when other instructions are using the stack.
15426 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15429 SDValue Size = Tmp2.getOperand(1);
15430 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15431 Chain = SP.getValue(1);
15432 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15433 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15434 unsigned StackAlign = TFI.getStackAlignment();
15435 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15436 if (Align > StackAlign)
15437 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15438 DAG.getConstant(-(uint64_t)Align, dl, VT));
15439 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15441 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15442 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15445 SDValue Ops[2] = { Tmp1, Tmp2 };
15446 return DAG.getMergeValues(Ops, dl);
15450 SDValue Chain = Op.getOperand(0);
15451 SDValue Size = Op.getOperand(1);
15452 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15453 EVT VT = Op.getNode()->getValueType(0);
15455 bool Is64Bit = Subtarget->is64Bit();
15456 MVT SPTy = getPointerTy(DAG.getDataLayout());
15459 MachineRegisterInfo &MRI = MF.getRegInfo();
15462 // The 64 bit implementation of segmented stacks needs to clobber both r10
15463 // r11. This makes it impossible to use it along with nested parameters.
15464 const Function *F = MF.getFunction();
15466 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15468 if (I->hasNestAttr())
15469 report_fatal_error("Cannot use segmented stacks with functions that "
15470 "have nested arguments.");
15473 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15474 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15475 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15476 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15477 DAG.getRegister(Vreg, SPTy));
15478 SDValue Ops1[2] = { Value, Chain };
15479 return DAG.getMergeValues(Ops1, dl);
15482 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15484 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15485 Flag = Chain.getValue(1);
15486 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15488 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15490 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15491 unsigned SPReg = RegInfo->getStackRegister();
15492 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15493 Chain = SP.getValue(1);
15496 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15497 DAG.getConstant(-(uint64_t)Align, dl, VT));
15498 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15501 SDValue Ops1[2] = { SP, Chain };
15502 return DAG.getMergeValues(Ops1, dl);
15506 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15507 MachineFunction &MF = DAG.getMachineFunction();
15508 auto PtrVT = getPointerTy(MF.getDataLayout());
15509 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15511 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15514 if (!Subtarget->is64Bit() ||
15515 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15516 // vastart just stores the address of the VarArgsFrameIndex slot into the
15517 // memory location argument.
15518 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15519 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15520 MachinePointerInfo(SV), false, false, 0);
15524 // gp_offset (0 - 6 * 8)
15525 // fp_offset (48 - 48 + 8 * 16)
15526 // overflow_arg_area (point to parameters coming in memory).
15528 SmallVector<SDValue, 8> MemOps;
15529 SDValue FIN = Op.getOperand(1);
15531 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15532 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15534 FIN, MachinePointerInfo(SV), false, false, 0);
15535 MemOps.push_back(Store);
15538 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15539 Store = DAG.getStore(Op.getOperand(0), DL,
15540 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15542 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15543 MemOps.push_back(Store);
15545 // Store ptr to overflow_arg_area
15546 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15547 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15548 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15549 MachinePointerInfo(SV, 8),
15551 MemOps.push_back(Store);
15553 // Store ptr to reg_save_area.
15554 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15555 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15556 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15557 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15558 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15559 MemOps.push_back(Store);
15560 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15563 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15564 assert(Subtarget->is64Bit() &&
15565 "LowerVAARG only handles 64-bit va_arg!");
15566 assert(Op.getNode()->getNumOperands() == 4);
15568 MachineFunction &MF = DAG.getMachineFunction();
15569 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15570 // The Win64 ABI uses char* instead of a structure.
15571 return DAG.expandVAArg(Op.getNode());
15573 SDValue Chain = Op.getOperand(0);
15574 SDValue SrcPtr = Op.getOperand(1);
15575 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15576 unsigned Align = Op.getConstantOperandVal(3);
15579 EVT ArgVT = Op.getNode()->getValueType(0);
15580 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15581 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15584 // Decide which area this value should be read from.
15585 // TODO: Implement the AMD64 ABI in its entirety. This simple
15586 // selection mechanism works only for the basic types.
15587 if (ArgVT == MVT::f80) {
15588 llvm_unreachable("va_arg for f80 not yet implemented");
15589 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15590 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15591 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15592 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15594 llvm_unreachable("Unhandled argument type in LowerVAARG");
15597 if (ArgMode == 2) {
15598 // Sanity Check: Make sure using fp_offset makes sense.
15599 assert(!Subtarget->useSoftFloat() &&
15600 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15601 Subtarget->hasSSE1());
15604 // Insert VAARG_64 node into the DAG
15605 // VAARG_64 returns two values: Variable Argument Address, Chain
15606 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15607 DAG.getConstant(ArgMode, dl, MVT::i8),
15608 DAG.getConstant(Align, dl, MVT::i32)};
15609 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15610 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15611 VTs, InstOps, MVT::i64,
15612 MachinePointerInfo(SV),
15614 /*Volatile=*/false,
15616 /*WriteMem=*/true);
15617 Chain = VAARG.getValue(1);
15619 // Load the next argument and return it
15620 return DAG.getLoad(ArgVT, dl,
15623 MachinePointerInfo(),
15624 false, false, false, 0);
15627 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15628 SelectionDAG &DAG) {
15629 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15630 // where a va_list is still an i8*.
15631 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15632 if (Subtarget->isCallingConvWin64(
15633 DAG.getMachineFunction().getFunction()->getCallingConv()))
15634 // Probably a Win64 va_copy.
15635 return DAG.expandVACopy(Op.getNode());
15637 SDValue Chain = Op.getOperand(0);
15638 SDValue DstPtr = Op.getOperand(1);
15639 SDValue SrcPtr = Op.getOperand(2);
15640 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15641 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15644 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15645 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15647 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15650 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15651 // amount is a constant. Takes immediate version of shift as input.
15652 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15653 SDValue SrcOp, uint64_t ShiftAmt,
15654 SelectionDAG &DAG) {
15655 MVT ElementType = VT.getVectorElementType();
15657 // Fold this packed shift into its first operand if ShiftAmt is 0.
15661 // Check for ShiftAmt >= element width
15662 if (ShiftAmt >= ElementType.getSizeInBits()) {
15663 if (Opc == X86ISD::VSRAI)
15664 ShiftAmt = ElementType.getSizeInBits() - 1;
15666 return DAG.getConstant(0, dl, VT);
15669 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15670 && "Unknown target vector shift-by-constant node");
15672 // Fold this packed vector shift into a build vector if SrcOp is a
15673 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15674 if (VT == SrcOp.getSimpleValueType() &&
15675 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15676 SmallVector<SDValue, 8> Elts;
15677 unsigned NumElts = SrcOp->getNumOperands();
15678 ConstantSDNode *ND;
15681 default: llvm_unreachable(nullptr);
15682 case X86ISD::VSHLI:
15683 for (unsigned i=0; i!=NumElts; ++i) {
15684 SDValue CurrentOp = SrcOp->getOperand(i);
15685 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15686 Elts.push_back(CurrentOp);
15689 ND = cast<ConstantSDNode>(CurrentOp);
15690 const APInt &C = ND->getAPIntValue();
15691 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15694 case X86ISD::VSRLI:
15695 for (unsigned i=0; i!=NumElts; ++i) {
15696 SDValue CurrentOp = SrcOp->getOperand(i);
15697 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15698 Elts.push_back(CurrentOp);
15701 ND = cast<ConstantSDNode>(CurrentOp);
15702 const APInt &C = ND->getAPIntValue();
15703 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15706 case X86ISD::VSRAI:
15707 for (unsigned i=0; i!=NumElts; ++i) {
15708 SDValue CurrentOp = SrcOp->getOperand(i);
15709 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15710 Elts.push_back(CurrentOp);
15713 ND = cast<ConstantSDNode>(CurrentOp);
15714 const APInt &C = ND->getAPIntValue();
15715 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15720 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15723 return DAG.getNode(Opc, dl, VT, SrcOp,
15724 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15727 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15728 // may or may not be a constant. Takes immediate version of shift as input.
15729 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15730 SDValue SrcOp, SDValue ShAmt,
15731 SelectionDAG &DAG) {
15732 MVT SVT = ShAmt.getSimpleValueType();
15733 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15735 // Catch shift-by-constant.
15736 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15737 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15738 CShAmt->getZExtValue(), DAG);
15740 // Change opcode to non-immediate version
15742 default: llvm_unreachable("Unknown target vector shift node");
15743 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15744 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15745 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15748 const X86Subtarget &Subtarget =
15749 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15750 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15751 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15752 // Let the shuffle legalizer expand this shift amount node.
15753 SDValue Op0 = ShAmt.getOperand(0);
15754 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15755 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15757 // Need to build a vector containing shift amount.
15758 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15759 SmallVector<SDValue, 4> ShOps;
15760 ShOps.push_back(ShAmt);
15761 if (SVT == MVT::i32) {
15762 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15763 ShOps.push_back(DAG.getUNDEF(SVT));
15765 ShOps.push_back(DAG.getUNDEF(SVT));
15767 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15768 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15771 // The return type has to be a 128-bit type with the same element
15772 // type as the input type.
15773 MVT EltVT = VT.getVectorElementType();
15774 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15776 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15777 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15780 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15781 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15782 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15783 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15784 SDValue PreservedSrc,
15785 const X86Subtarget *Subtarget,
15786 SelectionDAG &DAG) {
15787 EVT VT = Op.getValueType();
15788 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15789 MVT::i1, VT.getVectorNumElements());
15790 SDValue VMask = SDValue();
15791 unsigned OpcodeSelect = ISD::VSELECT;
15794 assert(MaskVT.isSimple() && "invalid mask type");
15796 if (isAllOnes(Mask))
15799 if (MaskVT.bitsGT(Mask.getValueType())) {
15800 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15801 MaskVT.getSizeInBits());
15802 VMask = DAG.getBitcast(MaskVT,
15803 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15805 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15806 Mask.getValueType().getSizeInBits());
15807 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15808 // are extracted by EXTRACT_SUBVECTOR.
15809 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15810 DAG.getBitcast(BitcastVT, Mask),
15811 DAG.getIntPtrConstant(0, dl));
15814 switch (Op.getOpcode()) {
15816 case X86ISD::PCMPEQM:
15817 case X86ISD::PCMPGTM:
15819 case X86ISD::CMPMU:
15820 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15821 case X86ISD::VFPCLASS:
15822 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15823 case X86ISD::VTRUNC:
15824 case X86ISD::VTRUNCS:
15825 case X86ISD::VTRUNCUS:
15826 // We can't use ISD::VSELECT here because it is not always "Legal"
15827 // for the destination type. For example vpmovqb require only AVX512
15828 // and vselect that can operate on byte element type require BWI
15829 OpcodeSelect = X86ISD::SELECT;
15832 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15833 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15834 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15837 /// \brief Creates an SDNode for a predicated scalar operation.
15838 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15839 /// The mask is coming as MVT::i8 and it should be truncated
15840 /// to MVT::i1 while lowering masking intrinsics.
15841 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15842 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15843 /// for a scalar instruction.
15844 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15845 SDValue PreservedSrc,
15846 const X86Subtarget *Subtarget,
15847 SelectionDAG &DAG) {
15848 if (isAllOnes(Mask))
15851 EVT VT = Op.getValueType();
15853 // The mask should be of type MVT::i1
15854 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15856 if (Op.getOpcode() == X86ISD::FSETCC)
15857 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15859 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15860 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15861 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15864 static int getSEHRegistrationNodeSize(const Function *Fn) {
15865 if (!Fn->hasPersonalityFn())
15866 report_fatal_error(
15867 "querying registration node size for function without personality");
15868 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15869 // WinEHStatePass for the full struct definition.
15870 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15871 case EHPersonality::MSVC_X86SEH: return 24;
15872 case EHPersonality::MSVC_CXX: return 16;
15875 report_fatal_error("can only recover FP for MSVC EH personality functions");
15878 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15879 /// function or when returning to a parent frame after catching an exception, we
15880 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15881 /// Here's the math:
15882 /// RegNodeBase = EntryEBP - RegNodeSize
15883 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15884 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15885 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15886 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15887 SDValue EntryEBP) {
15888 MachineFunction &MF = DAG.getMachineFunction();
15891 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15892 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15894 // It's possible that the parent function no longer has a personality function
15895 // if the exceptional code was optimized away, in which case we just return
15896 // the incoming EBP.
15897 if (!Fn->hasPersonalityFn())
15900 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15902 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15904 MCSymbol *OffsetSym =
15905 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15906 GlobalValue::getRealLinkageName(Fn->getName()));
15907 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15908 SDValue RegNodeFrameOffset =
15909 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15911 // RegNodeBase = EntryEBP - RegNodeSize
15912 // ParentFP = RegNodeBase - RegNodeFrameOffset
15913 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15914 DAG.getConstant(RegNodeSize, dl, PtrVT));
15915 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15918 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15919 SelectionDAG &DAG) {
15921 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15922 EVT VT = Op.getValueType();
15923 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15925 switch(IntrData->Type) {
15926 case INTR_TYPE_1OP:
15927 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15928 case INTR_TYPE_2OP:
15929 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15931 case INTR_TYPE_2OP_IMM8:
15932 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15933 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15934 case INTR_TYPE_3OP:
15935 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15936 Op.getOperand(2), Op.getOperand(3));
15937 case INTR_TYPE_4OP:
15938 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15939 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15940 case INTR_TYPE_1OP_MASK_RM: {
15941 SDValue Src = Op.getOperand(1);
15942 SDValue PassThru = Op.getOperand(2);
15943 SDValue Mask = Op.getOperand(3);
15944 SDValue RoundingMode;
15945 // We allways add rounding mode to the Node.
15946 // If the rounding mode is not specified, we add the
15947 // "current direction" mode.
15948 if (Op.getNumOperands() == 4)
15950 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15952 RoundingMode = Op.getOperand(4);
15953 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15954 if (IntrWithRoundingModeOpcode != 0)
15955 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
15956 X86::STATIC_ROUNDING::CUR_DIRECTION)
15957 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15958 dl, Op.getValueType(), Src, RoundingMode),
15959 Mask, PassThru, Subtarget, DAG);
15960 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15962 Mask, PassThru, Subtarget, DAG);
15964 case INTR_TYPE_1OP_MASK: {
15965 SDValue Src = Op.getOperand(1);
15966 SDValue PassThru = Op.getOperand(2);
15967 SDValue Mask = Op.getOperand(3);
15968 // We add rounding mode to the Node when
15969 // - RM Opcode is specified and
15970 // - RM is not "current direction".
15971 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15972 if (IntrWithRoundingModeOpcode != 0) {
15973 SDValue Rnd = Op.getOperand(4);
15974 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15975 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15976 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15977 dl, Op.getValueType(),
15979 Mask, PassThru, Subtarget, DAG);
15982 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15983 Mask, PassThru, Subtarget, DAG);
15985 case INTR_TYPE_SCALAR_MASK: {
15986 SDValue Src1 = Op.getOperand(1);
15987 SDValue Src2 = Op.getOperand(2);
15988 SDValue passThru = Op.getOperand(3);
15989 SDValue Mask = Op.getOperand(4);
15990 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
15991 Mask, passThru, Subtarget, DAG);
15993 case INTR_TYPE_SCALAR_MASK_RM: {
15994 SDValue Src1 = Op.getOperand(1);
15995 SDValue Src2 = Op.getOperand(2);
15996 SDValue Src0 = Op.getOperand(3);
15997 SDValue Mask = Op.getOperand(4);
15998 // There are 2 kinds of intrinsics in this group:
15999 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16000 // (2) With rounding mode and sae - 7 operands.
16001 if (Op.getNumOperands() == 6) {
16002 SDValue Sae = Op.getOperand(5);
16003 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16004 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16006 Mask, Src0, Subtarget, DAG);
16008 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16009 SDValue RoundingMode = Op.getOperand(5);
16010 SDValue Sae = Op.getOperand(6);
16011 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16012 RoundingMode, Sae),
16013 Mask, Src0, Subtarget, DAG);
16015 case INTR_TYPE_2OP_MASK: {
16016 SDValue Src1 = Op.getOperand(1);
16017 SDValue Src2 = Op.getOperand(2);
16018 SDValue PassThru = Op.getOperand(3);
16019 SDValue Mask = Op.getOperand(4);
16020 // We specify 2 possible opcodes for intrinsics with rounding modes.
16021 // First, we check if the intrinsic may have non-default rounding mode,
16022 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16023 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16024 if (IntrWithRoundingModeOpcode != 0) {
16025 SDValue Rnd = Op.getOperand(5);
16026 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16027 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16028 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16029 dl, Op.getValueType(),
16031 Mask, PassThru, Subtarget, DAG);
16034 // TODO: Intrinsics should have fast-math-flags to propagate.
16035 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16036 Mask, PassThru, Subtarget, DAG);
16038 case INTR_TYPE_2OP_MASK_RM: {
16039 SDValue Src1 = Op.getOperand(1);
16040 SDValue Src2 = Op.getOperand(2);
16041 SDValue PassThru = Op.getOperand(3);
16042 SDValue Mask = Op.getOperand(4);
16043 // We specify 2 possible modes for intrinsics, with/without rounding
16045 // First, we check if the intrinsic have rounding mode (6 operands),
16046 // if not, we set rounding mode to "current".
16048 if (Op.getNumOperands() == 6)
16049 Rnd = Op.getOperand(5);
16051 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16052 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16054 Mask, PassThru, Subtarget, DAG);
16056 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16057 SDValue Src1 = Op.getOperand(1);
16058 SDValue Src2 = Op.getOperand(2);
16059 SDValue Src3 = Op.getOperand(3);
16060 SDValue PassThru = Op.getOperand(4);
16061 SDValue Mask = Op.getOperand(5);
16062 SDValue Sae = Op.getOperand(6);
16064 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16066 Mask, PassThru, Subtarget, DAG);
16068 case INTR_TYPE_3OP_MASK_RM: {
16069 SDValue Src1 = Op.getOperand(1);
16070 SDValue Src2 = Op.getOperand(2);
16071 SDValue Imm = Op.getOperand(3);
16072 SDValue PassThru = Op.getOperand(4);
16073 SDValue Mask = Op.getOperand(5);
16074 // We specify 2 possible modes for intrinsics, with/without rounding
16076 // First, we check if the intrinsic have rounding mode (7 operands),
16077 // if not, we set rounding mode to "current".
16079 if (Op.getNumOperands() == 7)
16080 Rnd = Op.getOperand(6);
16082 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16083 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16084 Src1, Src2, Imm, Rnd),
16085 Mask, PassThru, Subtarget, DAG);
16087 case INTR_TYPE_3OP_IMM8_MASK:
16088 case INTR_TYPE_3OP_MASK:
16089 case INSERT_SUBVEC: {
16090 SDValue Src1 = Op.getOperand(1);
16091 SDValue Src2 = Op.getOperand(2);
16092 SDValue Src3 = Op.getOperand(3);
16093 SDValue PassThru = Op.getOperand(4);
16094 SDValue Mask = Op.getOperand(5);
16096 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16097 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16098 else if (IntrData->Type == INSERT_SUBVEC) {
16099 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16100 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16101 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16102 Imm *= Src2.getValueType().getVectorNumElements();
16103 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16106 // We specify 2 possible opcodes for intrinsics with rounding modes.
16107 // First, we check if the intrinsic may have non-default rounding mode,
16108 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16109 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16110 if (IntrWithRoundingModeOpcode != 0) {
16111 SDValue Rnd = Op.getOperand(6);
16112 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16113 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16114 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16115 dl, Op.getValueType(),
16116 Src1, Src2, Src3, Rnd),
16117 Mask, PassThru, Subtarget, DAG);
16120 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16122 Mask, PassThru, Subtarget, DAG);
16124 case VPERM_3OP_MASKZ:
16125 case VPERM_3OP_MASK:
16128 case FMA_OP_MASK: {
16129 SDValue Src1 = Op.getOperand(1);
16130 SDValue Src2 = Op.getOperand(2);
16131 SDValue Src3 = Op.getOperand(3);
16132 SDValue Mask = Op.getOperand(4);
16133 EVT VT = Op.getValueType();
16134 SDValue PassThru = SDValue();
16136 // set PassThru element
16137 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16138 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16139 else if (IntrData->Type == FMA_OP_MASK3)
16144 // We specify 2 possible opcodes for intrinsics with rounding modes.
16145 // First, we check if the intrinsic may have non-default rounding mode,
16146 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16147 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16148 if (IntrWithRoundingModeOpcode != 0) {
16149 SDValue Rnd = Op.getOperand(5);
16150 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16151 X86::STATIC_ROUNDING::CUR_DIRECTION)
16152 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16153 dl, Op.getValueType(),
16154 Src1, Src2, Src3, Rnd),
16155 Mask, PassThru, Subtarget, DAG);
16157 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16158 dl, Op.getValueType(),
16160 Mask, PassThru, Subtarget, DAG);
16163 // FPclass intrinsics with mask
16164 SDValue Src1 = Op.getOperand(1);
16165 EVT VT = Src1.getValueType();
16166 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16167 VT.getVectorNumElements());
16168 SDValue Imm = Op.getOperand(2);
16169 SDValue Mask = Op.getOperand(3);
16170 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16171 Mask.getValueType().getSizeInBits());
16172 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16173 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16174 DAG.getTargetConstant(0, dl, MaskVT),
16176 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16177 DAG.getUNDEF(BitcastVT), FPclassMask,
16178 DAG.getIntPtrConstant(0, dl));
16179 return DAG.getBitcast(Op.getValueType(), Res);
16182 case CMP_MASK_CC: {
16183 // Comparison intrinsics with masks.
16184 // Example of transformation:
16185 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16186 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16188 // (v8i1 (insert_subvector undef,
16189 // (v2i1 (and (PCMPEQM %a, %b),
16190 // (extract_subvector
16191 // (v8i1 (bitcast %mask)), 0))), 0))))
16192 EVT VT = Op.getOperand(1).getValueType();
16193 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16194 VT.getVectorNumElements());
16195 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16196 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16197 Mask.getValueType().getSizeInBits());
16199 if (IntrData->Type == CMP_MASK_CC) {
16200 SDValue CC = Op.getOperand(3);
16201 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16202 // We specify 2 possible opcodes for intrinsics with rounding modes.
16203 // First, we check if the intrinsic may have non-default rounding mode,
16204 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16205 if (IntrData->Opc1 != 0) {
16206 SDValue Rnd = Op.getOperand(5);
16207 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16208 X86::STATIC_ROUNDING::CUR_DIRECTION)
16209 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16210 Op.getOperand(2), CC, Rnd);
16212 //default rounding mode
16214 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16215 Op.getOperand(2), CC);
16218 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16219 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16222 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16223 DAG.getTargetConstant(0, dl,
16226 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16227 DAG.getUNDEF(BitcastVT), CmpMask,
16228 DAG.getIntPtrConstant(0, dl));
16229 return DAG.getBitcast(Op.getValueType(), Res);
16231 case CMP_MASK_SCALAR_CC: {
16232 SDValue Src1 = Op.getOperand(1);
16233 SDValue Src2 = Op.getOperand(2);
16234 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16235 SDValue Mask = Op.getOperand(4);
16238 if (IntrData->Opc1 != 0) {
16239 SDValue Rnd = Op.getOperand(5);
16240 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16241 X86::STATIC_ROUNDING::CUR_DIRECTION)
16242 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16244 //default rounding mode
16246 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16248 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16249 DAG.getTargetConstant(0, dl,
16253 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16254 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16255 DAG.getValueType(MVT::i1));
16257 case COMI: { // Comparison intrinsics
16258 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16259 SDValue LHS = Op.getOperand(1);
16260 SDValue RHS = Op.getOperand(2);
16261 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16262 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16263 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16264 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16265 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16266 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16269 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16270 Op.getOperand(1), Op.getOperand(2), DAG);
16272 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16273 Op.getSimpleValueType(),
16275 Op.getOperand(2), DAG),
16276 Op.getOperand(4), Op.getOperand(3), Subtarget,
16278 case COMPRESS_EXPAND_IN_REG: {
16279 SDValue Mask = Op.getOperand(3);
16280 SDValue DataToCompress = Op.getOperand(1);
16281 SDValue PassThru = Op.getOperand(2);
16282 if (isAllOnes(Mask)) // return data as is
16283 return Op.getOperand(1);
16285 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16287 Mask, PassThru, Subtarget, DAG);
16290 SDValue Mask = Op.getOperand(3);
16291 EVT VT = Op.getValueType();
16292 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16293 VT.getVectorNumElements());
16294 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16295 Mask.getValueType().getSizeInBits());
16297 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16298 DAG.getBitcast(BitcastVT, Mask),
16299 DAG.getIntPtrConstant(0, dl));
16300 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16309 default: return SDValue(); // Don't custom lower most intrinsics.
16311 case Intrinsic::x86_avx2_permd:
16312 case Intrinsic::x86_avx2_permps:
16313 // Operands intentionally swapped. Mask is last operand to intrinsic,
16314 // but second operand for node/instruction.
16315 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16316 Op.getOperand(2), Op.getOperand(1));
16318 // ptest and testp intrinsics. The intrinsic these come from are designed to
16319 // return an integer value, not just an instruction so lower it to the ptest
16320 // or testp pattern and a setcc for the result.
16321 case Intrinsic::x86_sse41_ptestz:
16322 case Intrinsic::x86_sse41_ptestc:
16323 case Intrinsic::x86_sse41_ptestnzc:
16324 case Intrinsic::x86_avx_ptestz_256:
16325 case Intrinsic::x86_avx_ptestc_256:
16326 case Intrinsic::x86_avx_ptestnzc_256:
16327 case Intrinsic::x86_avx_vtestz_ps:
16328 case Intrinsic::x86_avx_vtestc_ps:
16329 case Intrinsic::x86_avx_vtestnzc_ps:
16330 case Intrinsic::x86_avx_vtestz_pd:
16331 case Intrinsic::x86_avx_vtestc_pd:
16332 case Intrinsic::x86_avx_vtestnzc_pd:
16333 case Intrinsic::x86_avx_vtestz_ps_256:
16334 case Intrinsic::x86_avx_vtestc_ps_256:
16335 case Intrinsic::x86_avx_vtestnzc_ps_256:
16336 case Intrinsic::x86_avx_vtestz_pd_256:
16337 case Intrinsic::x86_avx_vtestc_pd_256:
16338 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16339 bool IsTestPacked = false;
16342 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16343 case Intrinsic::x86_avx_vtestz_ps:
16344 case Intrinsic::x86_avx_vtestz_pd:
16345 case Intrinsic::x86_avx_vtestz_ps_256:
16346 case Intrinsic::x86_avx_vtestz_pd_256:
16347 IsTestPacked = true; // Fallthrough
16348 case Intrinsic::x86_sse41_ptestz:
16349 case Intrinsic::x86_avx_ptestz_256:
16351 X86CC = X86::COND_E;
16353 case Intrinsic::x86_avx_vtestc_ps:
16354 case Intrinsic::x86_avx_vtestc_pd:
16355 case Intrinsic::x86_avx_vtestc_ps_256:
16356 case Intrinsic::x86_avx_vtestc_pd_256:
16357 IsTestPacked = true; // Fallthrough
16358 case Intrinsic::x86_sse41_ptestc:
16359 case Intrinsic::x86_avx_ptestc_256:
16361 X86CC = X86::COND_B;
16363 case Intrinsic::x86_avx_vtestnzc_ps:
16364 case Intrinsic::x86_avx_vtestnzc_pd:
16365 case Intrinsic::x86_avx_vtestnzc_ps_256:
16366 case Intrinsic::x86_avx_vtestnzc_pd_256:
16367 IsTestPacked = true; // Fallthrough
16368 case Intrinsic::x86_sse41_ptestnzc:
16369 case Intrinsic::x86_avx_ptestnzc_256:
16371 X86CC = X86::COND_A;
16375 SDValue LHS = Op.getOperand(1);
16376 SDValue RHS = Op.getOperand(2);
16377 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16378 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16379 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16380 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16381 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16383 case Intrinsic::x86_avx512_kortestz_w:
16384 case Intrinsic::x86_avx512_kortestc_w: {
16385 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16386 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16387 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16388 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16389 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16390 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16391 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16394 case Intrinsic::x86_sse42_pcmpistria128:
16395 case Intrinsic::x86_sse42_pcmpestria128:
16396 case Intrinsic::x86_sse42_pcmpistric128:
16397 case Intrinsic::x86_sse42_pcmpestric128:
16398 case Intrinsic::x86_sse42_pcmpistrio128:
16399 case Intrinsic::x86_sse42_pcmpestrio128:
16400 case Intrinsic::x86_sse42_pcmpistris128:
16401 case Intrinsic::x86_sse42_pcmpestris128:
16402 case Intrinsic::x86_sse42_pcmpistriz128:
16403 case Intrinsic::x86_sse42_pcmpestriz128: {
16407 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16408 case Intrinsic::x86_sse42_pcmpistria128:
16409 Opcode = X86ISD::PCMPISTRI;
16410 X86CC = X86::COND_A;
16412 case Intrinsic::x86_sse42_pcmpestria128:
16413 Opcode = X86ISD::PCMPESTRI;
16414 X86CC = X86::COND_A;
16416 case Intrinsic::x86_sse42_pcmpistric128:
16417 Opcode = X86ISD::PCMPISTRI;
16418 X86CC = X86::COND_B;
16420 case Intrinsic::x86_sse42_pcmpestric128:
16421 Opcode = X86ISD::PCMPESTRI;
16422 X86CC = X86::COND_B;
16424 case Intrinsic::x86_sse42_pcmpistrio128:
16425 Opcode = X86ISD::PCMPISTRI;
16426 X86CC = X86::COND_O;
16428 case Intrinsic::x86_sse42_pcmpestrio128:
16429 Opcode = X86ISD::PCMPESTRI;
16430 X86CC = X86::COND_O;
16432 case Intrinsic::x86_sse42_pcmpistris128:
16433 Opcode = X86ISD::PCMPISTRI;
16434 X86CC = X86::COND_S;
16436 case Intrinsic::x86_sse42_pcmpestris128:
16437 Opcode = X86ISD::PCMPESTRI;
16438 X86CC = X86::COND_S;
16440 case Intrinsic::x86_sse42_pcmpistriz128:
16441 Opcode = X86ISD::PCMPISTRI;
16442 X86CC = X86::COND_E;
16444 case Intrinsic::x86_sse42_pcmpestriz128:
16445 Opcode = X86ISD::PCMPESTRI;
16446 X86CC = X86::COND_E;
16449 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16450 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16451 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16452 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16453 DAG.getConstant(X86CC, dl, MVT::i8),
16454 SDValue(PCMP.getNode(), 1));
16455 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16458 case Intrinsic::x86_sse42_pcmpistri128:
16459 case Intrinsic::x86_sse42_pcmpestri128: {
16461 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16462 Opcode = X86ISD::PCMPISTRI;
16464 Opcode = X86ISD::PCMPESTRI;
16466 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16467 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16468 return DAG.getNode(Opcode, dl, VTs, NewOps);
16471 case Intrinsic::x86_seh_lsda: {
16472 // Compute the symbol for the LSDA. We know it'll get emitted later.
16473 MachineFunction &MF = DAG.getMachineFunction();
16474 SDValue Op1 = Op.getOperand(1);
16475 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16476 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16477 GlobalValue::getRealLinkageName(Fn->getName()));
16479 // Generate a simple absolute symbol reference. This intrinsic is only
16480 // supported on 32-bit Windows, which isn't PIC.
16481 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16482 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16485 case Intrinsic::x86_seh_recoverfp: {
16486 SDValue FnOp = Op.getOperand(1);
16487 SDValue IncomingFPOp = Op.getOperand(2);
16488 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16489 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16491 report_fatal_error(
16492 "llvm.x86.seh.recoverfp must take a function as the first argument");
16493 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16496 case Intrinsic::localaddress: {
16497 // Returns one of the stack, base, or frame pointer registers, depending on
16498 // which is used to reference local variables.
16499 MachineFunction &MF = DAG.getMachineFunction();
16500 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16502 if (RegInfo->hasBasePointer(MF))
16503 Reg = RegInfo->getBaseRegister();
16504 else // This function handles the SP or FP case.
16505 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16506 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16511 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16512 SDValue Src, SDValue Mask, SDValue Base,
16513 SDValue Index, SDValue ScaleOp, SDValue Chain,
16514 const X86Subtarget * Subtarget) {
16516 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16518 llvm_unreachable("Invalid scale type");
16519 unsigned ScaleVal = C->getZExtValue();
16520 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16521 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16523 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16524 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16525 Index.getSimpleValueType().getVectorNumElements());
16527 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16529 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16531 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16532 Mask.getValueType().getSizeInBits());
16534 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16535 // are extracted by EXTRACT_SUBVECTOR.
16536 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16537 DAG.getBitcast(BitcastVT, Mask),
16538 DAG.getIntPtrConstant(0, dl));
16540 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16541 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16542 SDValue Segment = DAG.getRegister(0, MVT::i32);
16543 if (Src.getOpcode() == ISD::UNDEF)
16544 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16545 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16546 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16547 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16548 return DAG.getMergeValues(RetOps, dl);
16551 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16552 SDValue Src, SDValue Mask, SDValue Base,
16553 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16555 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16557 llvm_unreachable("Invalid scale type");
16558 unsigned ScaleVal = C->getZExtValue();
16559 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16560 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16562 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16563 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16564 SDValue Segment = DAG.getRegister(0, MVT::i32);
16565 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16566 Index.getSimpleValueType().getVectorNumElements());
16568 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16570 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16572 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16573 Mask.getValueType().getSizeInBits());
16575 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16576 // are extracted by EXTRACT_SUBVECTOR.
16577 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16578 DAG.getBitcast(BitcastVT, Mask),
16579 DAG.getIntPtrConstant(0, dl));
16581 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16582 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16583 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16584 return SDValue(Res, 1);
16587 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16588 SDValue Mask, SDValue Base, SDValue Index,
16589 SDValue ScaleOp, SDValue Chain) {
16591 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16592 assert(C && "Invalid scale type");
16593 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16594 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16595 SDValue Segment = DAG.getRegister(0, MVT::i32);
16597 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16599 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16601 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16603 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16604 //SDVTList VTs = DAG.getVTList(MVT::Other);
16605 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16606 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16607 return SDValue(Res, 0);
16610 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16611 // read performance monitor counters (x86_rdpmc).
16612 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16613 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16614 SmallVectorImpl<SDValue> &Results) {
16615 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16616 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16619 // The ECX register is used to select the index of the performance counter
16621 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16623 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16625 // Reads the content of a 64-bit performance counter and returns it in the
16626 // registers EDX:EAX.
16627 if (Subtarget->is64Bit()) {
16628 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16629 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16632 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16633 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16636 Chain = HI.getValue(1);
16638 if (Subtarget->is64Bit()) {
16639 // The EAX register is loaded with the low-order 32 bits. The EDX register
16640 // is loaded with the supported high-order bits of the counter.
16641 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16642 DAG.getConstant(32, DL, MVT::i8));
16643 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16644 Results.push_back(Chain);
16648 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16649 SDValue Ops[] = { LO, HI };
16650 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16651 Results.push_back(Pair);
16652 Results.push_back(Chain);
16655 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16656 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16657 // also used to custom lower READCYCLECOUNTER nodes.
16658 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16659 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16660 SmallVectorImpl<SDValue> &Results) {
16661 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16662 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16665 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16666 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16667 // and the EAX register is loaded with the low-order 32 bits.
16668 if (Subtarget->is64Bit()) {
16669 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16670 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16673 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16674 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16677 SDValue Chain = HI.getValue(1);
16679 if (Opcode == X86ISD::RDTSCP_DAG) {
16680 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16682 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16683 // the ECX register. Add 'ecx' explicitly to the chain.
16684 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16686 // Explicitly store the content of ECX at the location passed in input
16687 // to the 'rdtscp' intrinsic.
16688 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16689 MachinePointerInfo(), false, false, 0);
16692 if (Subtarget->is64Bit()) {
16693 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16694 // the EAX register is loaded with the low-order 32 bits.
16695 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16696 DAG.getConstant(32, DL, MVT::i8));
16697 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16698 Results.push_back(Chain);
16702 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16703 SDValue Ops[] = { LO, HI };
16704 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16705 Results.push_back(Pair);
16706 Results.push_back(Chain);
16709 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16710 SelectionDAG &DAG) {
16711 SmallVector<SDValue, 2> Results;
16713 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16715 return DAG.getMergeValues(Results, DL);
16718 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16719 SelectionDAG &DAG) {
16720 MachineFunction &MF = DAG.getMachineFunction();
16721 const Function *Fn = MF.getFunction();
16723 SDValue Chain = Op.getOperand(0);
16725 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16726 "using llvm.x86.seh.restoreframe requires a frame pointer");
16728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16729 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16731 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16732 unsigned FrameReg =
16733 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16734 unsigned SPReg = RegInfo->getStackRegister();
16735 unsigned SlotSize = RegInfo->getSlotSize();
16737 // Get incoming EBP.
16738 SDValue IncomingEBP =
16739 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16741 // SP is saved in the first field of every registration node, so load
16742 // [EBP-RegNodeSize] into SP.
16743 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16744 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16745 DAG.getConstant(-RegNodeSize, dl, VT));
16747 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16748 false, VT.getScalarSizeInBits() / 8);
16749 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16751 if (!RegInfo->needsStackRealignment(MF)) {
16752 // Adjust EBP to point back to the original frame position.
16753 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16754 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16756 assert(RegInfo->hasBasePointer(MF) &&
16757 "functions with Win32 EH must use frame or base pointer register");
16759 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16760 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16761 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16763 // Reload the spilled EBP value, now that the stack and base pointers are
16765 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16766 X86FI->setHasSEHFramePtrSave(true);
16767 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16768 X86FI->setSEHFramePtrSaveIndex(FI);
16769 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16770 MachinePointerInfo(), false, false, false,
16771 VT.getScalarSizeInBits() / 8);
16772 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16778 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16779 /// return truncate Store/MaskedStore Node
16780 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16784 SDValue Mask = Op.getOperand(4);
16785 SDValue DataToTruncate = Op.getOperand(3);
16786 SDValue Addr = Op.getOperand(2);
16787 SDValue Chain = Op.getOperand(0);
16789 EVT VT = DataToTruncate.getValueType();
16790 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16791 ElementType, VT.getVectorNumElements());
16793 if (isAllOnes(Mask)) // return just a truncate store
16794 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16795 MachinePointerInfo(), SVT, false, false,
16796 SVT.getScalarSizeInBits()/8);
16798 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16799 MVT::i1, VT.getVectorNumElements());
16800 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16801 Mask.getValueType().getSizeInBits());
16802 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16803 // are extracted by EXTRACT_SUBVECTOR.
16804 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16805 DAG.getBitcast(BitcastVT, Mask),
16806 DAG.getIntPtrConstant(0, dl));
16808 MachineMemOperand *MMO = DAG.getMachineFunction().
16809 getMachineMemOperand(MachinePointerInfo(),
16810 MachineMemOperand::MOStore, SVT.getStoreSize(),
16811 SVT.getScalarSizeInBits()/8);
16813 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16814 VMask, SVT, MMO, true);
16817 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16818 SelectionDAG &DAG) {
16819 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16821 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16823 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16824 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16829 switch(IntrData->Type) {
16831 llvm_unreachable("Unknown Intrinsic Type");
16835 // Emit the node with the right value type.
16836 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16837 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16839 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16840 // Otherwise return the value from Rand, which is always 0, casted to i32.
16841 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16842 DAG.getConstant(1, dl, Op->getValueType(1)),
16843 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16844 SDValue(Result.getNode(), 1) };
16845 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16846 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16849 // Return { result, isValid, chain }.
16850 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16851 SDValue(Result.getNode(), 2));
16854 //gather(v1, mask, index, base, scale);
16855 SDValue Chain = Op.getOperand(0);
16856 SDValue Src = Op.getOperand(2);
16857 SDValue Base = Op.getOperand(3);
16858 SDValue Index = Op.getOperand(4);
16859 SDValue Mask = Op.getOperand(5);
16860 SDValue Scale = Op.getOperand(6);
16861 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16865 //scatter(base, mask, index, v1, scale);
16866 SDValue Chain = Op.getOperand(0);
16867 SDValue Base = Op.getOperand(2);
16868 SDValue Mask = Op.getOperand(3);
16869 SDValue Index = Op.getOperand(4);
16870 SDValue Src = Op.getOperand(5);
16871 SDValue Scale = Op.getOperand(6);
16872 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16876 SDValue Hint = Op.getOperand(6);
16877 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16878 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16879 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16880 SDValue Chain = Op.getOperand(0);
16881 SDValue Mask = Op.getOperand(2);
16882 SDValue Index = Op.getOperand(3);
16883 SDValue Base = Op.getOperand(4);
16884 SDValue Scale = Op.getOperand(5);
16885 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16887 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16889 SmallVector<SDValue, 2> Results;
16890 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16892 return DAG.getMergeValues(Results, dl);
16894 // Read Performance Monitoring Counters.
16896 SmallVector<SDValue, 2> Results;
16897 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16898 return DAG.getMergeValues(Results, dl);
16900 // XTEST intrinsics.
16902 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16903 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16904 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16905 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16907 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16908 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16909 Ret, SDValue(InTrans.getNode(), 1));
16913 SmallVector<SDValue, 2> Results;
16914 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16915 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16916 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16917 DAG.getConstant(-1, dl, MVT::i8));
16918 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16919 Op.getOperand(4), GenCF.getValue(1));
16920 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16921 Op.getOperand(5), MachinePointerInfo(),
16923 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16924 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16926 Results.push_back(SetCC);
16927 Results.push_back(Store);
16928 return DAG.getMergeValues(Results, dl);
16930 case COMPRESS_TO_MEM: {
16932 SDValue Mask = Op.getOperand(4);
16933 SDValue DataToCompress = Op.getOperand(3);
16934 SDValue Addr = Op.getOperand(2);
16935 SDValue Chain = Op.getOperand(0);
16937 EVT VT = DataToCompress.getValueType();
16938 if (isAllOnes(Mask)) // return just a store
16939 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16940 MachinePointerInfo(), false, false,
16941 VT.getScalarSizeInBits()/8);
16943 SDValue Compressed =
16944 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16945 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16946 return DAG.getStore(Chain, dl, Compressed, Addr,
16947 MachinePointerInfo(), false, false,
16948 VT.getScalarSizeInBits()/8);
16950 case TRUNCATE_TO_MEM_VI8:
16951 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
16952 case TRUNCATE_TO_MEM_VI16:
16953 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
16954 case TRUNCATE_TO_MEM_VI32:
16955 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
16956 case EXPAND_FROM_MEM: {
16958 SDValue Mask = Op.getOperand(4);
16959 SDValue PassThru = Op.getOperand(3);
16960 SDValue Addr = Op.getOperand(2);
16961 SDValue Chain = Op.getOperand(0);
16962 EVT VT = Op.getValueType();
16964 if (isAllOnes(Mask)) // return just a load
16965 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16966 false, VT.getScalarSizeInBits()/8);
16968 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16969 false, false, false,
16970 VT.getScalarSizeInBits()/8);
16972 SDValue Results[] = {
16973 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16974 Mask, PassThru, Subtarget, DAG), Chain};
16975 return DAG.getMergeValues(Results, dl);
16980 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16981 SelectionDAG &DAG) const {
16982 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16983 MFI->setReturnAddressIsTaken(true);
16985 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16988 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16990 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16993 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16994 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16995 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16996 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16997 DAG.getNode(ISD::ADD, dl, PtrVT,
16998 FrameAddr, Offset),
16999 MachinePointerInfo(), false, false, false, 0);
17002 // Just load the return address.
17003 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17004 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17005 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17008 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17009 MachineFunction &MF = DAG.getMachineFunction();
17010 MachineFrameInfo *MFI = MF.getFrameInfo();
17011 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17012 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17013 EVT VT = Op.getValueType();
17015 MFI->setFrameAddressIsTaken(true);
17017 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17018 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17019 // is not possible to crawl up the stack without looking at the unwind codes
17021 int FrameAddrIndex = FuncInfo->getFAIndex();
17022 if (!FrameAddrIndex) {
17023 // Set up a frame object for the return address.
17024 unsigned SlotSize = RegInfo->getSlotSize();
17025 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17026 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17027 FuncInfo->setFAIndex(FrameAddrIndex);
17029 return DAG.getFrameIndex(FrameAddrIndex, VT);
17032 unsigned FrameReg =
17033 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17034 SDLoc dl(Op); // FIXME probably not meaningful
17035 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17036 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17037 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17038 "Invalid Frame Register!");
17039 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17041 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17042 MachinePointerInfo(),
17043 false, false, false, 0);
17047 // FIXME? Maybe this could be a TableGen attribute on some registers and
17048 // this table could be generated automatically from RegInfo.
17049 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17050 SelectionDAG &DAG) const {
17051 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17052 const MachineFunction &MF = DAG.getMachineFunction();
17054 unsigned Reg = StringSwitch<unsigned>(RegName)
17055 .Case("esp", X86::ESP)
17056 .Case("rsp", X86::RSP)
17057 .Case("ebp", X86::EBP)
17058 .Case("rbp", X86::RBP)
17061 if (Reg == X86::EBP || Reg == X86::RBP) {
17062 if (!TFI.hasFP(MF))
17063 report_fatal_error("register " + StringRef(RegName) +
17064 " is allocatable: function has no frame pointer");
17067 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17068 unsigned FrameReg =
17069 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17070 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17071 "Invalid Frame Register!");
17079 report_fatal_error("Invalid register name global variable");
17082 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17083 SelectionDAG &DAG) const {
17084 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17085 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17088 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17089 SDValue Chain = Op.getOperand(0);
17090 SDValue Offset = Op.getOperand(1);
17091 SDValue Handler = Op.getOperand(2);
17094 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17095 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17096 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17097 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17098 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17099 "Invalid Frame Register!");
17100 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17101 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17103 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17104 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17106 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17107 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17109 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17111 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17112 DAG.getRegister(StoreAddrReg, PtrVT));
17115 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17116 SelectionDAG &DAG) const {
17118 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17119 DAG.getVTList(MVT::i32, MVT::Other),
17120 Op.getOperand(0), Op.getOperand(1));
17123 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17124 SelectionDAG &DAG) const {
17126 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17127 Op.getOperand(0), Op.getOperand(1));
17130 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17131 return Op.getOperand(0);
17134 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17135 SelectionDAG &DAG) const {
17136 SDValue Root = Op.getOperand(0);
17137 SDValue Trmp = Op.getOperand(1); // trampoline
17138 SDValue FPtr = Op.getOperand(2); // nested function
17139 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17142 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17143 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17145 if (Subtarget->is64Bit()) {
17146 SDValue OutChains[6];
17148 // Large code-model.
17149 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17150 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17152 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17153 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17155 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17157 // Load the pointer to the nested function into R11.
17158 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17159 SDValue Addr = Trmp;
17160 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17161 Addr, MachinePointerInfo(TrmpAddr),
17164 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17165 DAG.getConstant(2, dl, MVT::i64));
17166 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17167 MachinePointerInfo(TrmpAddr, 2),
17170 // Load the 'nest' parameter value into R10.
17171 // R10 is specified in X86CallingConv.td
17172 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17173 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17174 DAG.getConstant(10, dl, MVT::i64));
17175 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17176 Addr, MachinePointerInfo(TrmpAddr, 10),
17179 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17180 DAG.getConstant(12, dl, MVT::i64));
17181 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17182 MachinePointerInfo(TrmpAddr, 12),
17185 // Jump to the nested function.
17186 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17187 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17188 DAG.getConstant(20, dl, MVT::i64));
17189 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17190 Addr, MachinePointerInfo(TrmpAddr, 20),
17193 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17194 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17195 DAG.getConstant(22, dl, MVT::i64));
17196 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17197 Addr, MachinePointerInfo(TrmpAddr, 22),
17200 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17202 const Function *Func =
17203 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17204 CallingConv::ID CC = Func->getCallingConv();
17209 llvm_unreachable("Unsupported calling convention");
17210 case CallingConv::C:
17211 case CallingConv::X86_StdCall: {
17212 // Pass 'nest' parameter in ECX.
17213 // Must be kept in sync with X86CallingConv.td
17214 NestReg = X86::ECX;
17216 // Check that ECX wasn't needed by an 'inreg' parameter.
17217 FunctionType *FTy = Func->getFunctionType();
17218 const AttributeSet &Attrs = Func->getAttributes();
17220 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17221 unsigned InRegCount = 0;
17224 for (FunctionType::param_iterator I = FTy->param_begin(),
17225 E = FTy->param_end(); I != E; ++I, ++Idx)
17226 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17227 auto &DL = DAG.getDataLayout();
17228 // FIXME: should only count parameters that are lowered to integers.
17229 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17232 if (InRegCount > 2) {
17233 report_fatal_error("Nest register in use - reduce number of inreg"
17239 case CallingConv::X86_FastCall:
17240 case CallingConv::X86_ThisCall:
17241 case CallingConv::Fast:
17242 // Pass 'nest' parameter in EAX.
17243 // Must be kept in sync with X86CallingConv.td
17244 NestReg = X86::EAX;
17248 SDValue OutChains[4];
17249 SDValue Addr, Disp;
17251 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17252 DAG.getConstant(10, dl, MVT::i32));
17253 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17255 // This is storing the opcode for MOV32ri.
17256 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17257 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17258 OutChains[0] = DAG.getStore(Root, dl,
17259 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17260 Trmp, MachinePointerInfo(TrmpAddr),
17263 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17264 DAG.getConstant(1, dl, MVT::i32));
17265 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17266 MachinePointerInfo(TrmpAddr, 1),
17269 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17270 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17271 DAG.getConstant(5, dl, MVT::i32));
17272 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17273 Addr, MachinePointerInfo(TrmpAddr, 5),
17276 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17277 DAG.getConstant(6, dl, MVT::i32));
17278 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17279 MachinePointerInfo(TrmpAddr, 6),
17282 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17286 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17287 SelectionDAG &DAG) const {
17289 The rounding mode is in bits 11:10 of FPSR, and has the following
17291 00 Round to nearest
17296 FLT_ROUNDS, on the other hand, expects the following:
17303 To perform the conversion, we do:
17304 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17307 MachineFunction &MF = DAG.getMachineFunction();
17308 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17309 unsigned StackAlignment = TFI.getStackAlignment();
17310 MVT VT = Op.getSimpleValueType();
17313 // Save FP Control Word to stack slot
17314 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17315 SDValue StackSlot =
17316 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17318 MachineMemOperand *MMO =
17319 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17320 MachineMemOperand::MOStore, 2, 2);
17322 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17323 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17324 DAG.getVTList(MVT::Other),
17325 Ops, MVT::i16, MMO);
17327 // Load FP Control Word from stack slot
17328 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17329 MachinePointerInfo(), false, false, false, 0);
17331 // Transform as necessary
17333 DAG.getNode(ISD::SRL, DL, MVT::i16,
17334 DAG.getNode(ISD::AND, DL, MVT::i16,
17335 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17336 DAG.getConstant(11, DL, MVT::i8));
17338 DAG.getNode(ISD::SRL, DL, MVT::i16,
17339 DAG.getNode(ISD::AND, DL, MVT::i16,
17340 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17341 DAG.getConstant(9, DL, MVT::i8));
17344 DAG.getNode(ISD::AND, DL, MVT::i16,
17345 DAG.getNode(ISD::ADD, DL, MVT::i16,
17346 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17347 DAG.getConstant(1, DL, MVT::i16)),
17348 DAG.getConstant(3, DL, MVT::i16));
17350 return DAG.getNode((VT.getSizeInBits() < 16 ?
17351 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17354 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17355 MVT VT = Op.getSimpleValueType();
17357 unsigned NumBits = VT.getSizeInBits();
17360 Op = Op.getOperand(0);
17361 if (VT == MVT::i8) {
17362 // Zero extend to i32 since there is not an i8 bsr.
17364 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17367 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17368 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17369 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17371 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17374 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17375 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17378 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17380 // Finally xor with NumBits-1.
17381 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17382 DAG.getConstant(NumBits - 1, dl, OpVT));
17385 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17389 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17390 MVT VT = Op.getSimpleValueType();
17392 unsigned NumBits = VT.getSizeInBits();
17395 Op = Op.getOperand(0);
17396 if (VT == MVT::i8) {
17397 // Zero extend to i32 since there is not an i8 bsr.
17399 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17402 // Issue a bsr (scan bits in reverse).
17403 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17404 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17406 // And xor with NumBits-1.
17407 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17408 DAG.getConstant(NumBits - 1, dl, OpVT));
17411 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17415 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17416 MVT VT = Op.getSimpleValueType();
17417 unsigned NumBits = VT.getScalarSizeInBits();
17420 if (VT.isVector()) {
17421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17423 SDValue N0 = Op.getOperand(0);
17424 SDValue Zero = DAG.getConstant(0, dl, VT);
17426 // lsb(x) = (x & -x)
17427 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17428 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17430 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17431 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17432 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17433 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17434 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17435 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17438 // cttz(x) = ctpop(lsb - 1)
17439 SDValue One = DAG.getConstant(1, dl, VT);
17440 return DAG.getNode(ISD::CTPOP, dl, VT,
17441 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17444 assert(Op.getOpcode() == ISD::CTTZ &&
17445 "Only scalar CTTZ requires custom lowering");
17447 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17448 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17449 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17451 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17454 DAG.getConstant(NumBits, dl, VT),
17455 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17458 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17461 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17462 // ones, and then concatenate the result back.
17463 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17464 MVT VT = Op.getSimpleValueType();
17466 assert(VT.is256BitVector() && VT.isInteger() &&
17467 "Unsupported value type for operation");
17469 unsigned NumElems = VT.getVectorNumElements();
17472 // Extract the LHS vectors
17473 SDValue LHS = Op.getOperand(0);
17474 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17475 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17477 // Extract the RHS vectors
17478 SDValue RHS = Op.getOperand(1);
17479 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17480 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17482 MVT EltVT = VT.getVectorElementType();
17483 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17485 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17486 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17487 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17490 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17491 if (Op.getValueType() == MVT::i1)
17492 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17493 Op.getOperand(0), Op.getOperand(1));
17494 assert(Op.getSimpleValueType().is256BitVector() &&
17495 Op.getSimpleValueType().isInteger() &&
17496 "Only handle AVX 256-bit vector integer operation");
17497 return Lower256IntArith(Op, DAG);
17500 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17501 if (Op.getValueType() == MVT::i1)
17502 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17503 Op.getOperand(0), Op.getOperand(1));
17504 assert(Op.getSimpleValueType().is256BitVector() &&
17505 Op.getSimpleValueType().isInteger() &&
17506 "Only handle AVX 256-bit vector integer operation");
17507 return Lower256IntArith(Op, DAG);
17510 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17511 assert(Op.getSimpleValueType().is256BitVector() &&
17512 Op.getSimpleValueType().isInteger() &&
17513 "Only handle AVX 256-bit vector integer operation");
17514 return Lower256IntArith(Op, DAG);
17517 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17518 SelectionDAG &DAG) {
17520 MVT VT = Op.getSimpleValueType();
17523 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17525 // Decompose 256-bit ops into smaller 128-bit ops.
17526 if (VT.is256BitVector() && !Subtarget->hasInt256())
17527 return Lower256IntArith(Op, DAG);
17529 SDValue A = Op.getOperand(0);
17530 SDValue B = Op.getOperand(1);
17532 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17533 // pairs, multiply and truncate.
17534 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17535 if (Subtarget->hasInt256()) {
17536 if (VT == MVT::v32i8) {
17537 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17538 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17539 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17540 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17541 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17542 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17543 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17544 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17545 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17546 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17549 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17550 return DAG.getNode(
17551 ISD::TRUNCATE, dl, VT,
17552 DAG.getNode(ISD::MUL, dl, ExVT,
17553 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17554 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17557 assert(VT == MVT::v16i8 &&
17558 "Pre-AVX2 support only supports v16i8 multiplication");
17559 MVT ExVT = MVT::v8i16;
17561 // Extract the lo parts and sign extend to i16
17563 if (Subtarget->hasSSE41()) {
17564 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17565 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17567 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17568 -1, 4, -1, 5, -1, 6, -1, 7};
17569 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17570 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17571 ALo = DAG.getBitcast(ExVT, ALo);
17572 BLo = DAG.getBitcast(ExVT, BLo);
17573 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17574 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17577 // Extract the hi parts and sign extend to i16
17579 if (Subtarget->hasSSE41()) {
17580 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17581 -1, -1, -1, -1, -1, -1, -1, -1};
17582 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17583 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17584 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17585 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17587 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17588 -1, 12, -1, 13, -1, 14, -1, 15};
17589 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17590 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17591 AHi = DAG.getBitcast(ExVT, AHi);
17592 BHi = DAG.getBitcast(ExVT, BHi);
17593 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17594 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17597 // Multiply, mask the lower 8bits of the lo/hi results and pack
17598 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17599 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17600 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17601 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17602 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17605 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17606 if (VT == MVT::v4i32) {
17607 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17608 "Should not custom lower when pmuldq is available!");
17610 // Extract the odd parts.
17611 static const int UnpackMask[] = { 1, -1, 3, -1 };
17612 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17613 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17615 // Multiply the even parts.
17616 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17617 // Now multiply odd parts.
17618 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17620 Evens = DAG.getBitcast(VT, Evens);
17621 Odds = DAG.getBitcast(VT, Odds);
17623 // Merge the two vectors back together with a shuffle. This expands into 2
17625 static const int ShufMask[] = { 0, 4, 2, 6 };
17626 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17629 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17630 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17632 // Ahi = psrlqi(a, 32);
17633 // Bhi = psrlqi(b, 32);
17635 // AloBlo = pmuludq(a, b);
17636 // AloBhi = pmuludq(a, Bhi);
17637 // AhiBlo = pmuludq(Ahi, b);
17639 // AloBhi = psllqi(AloBhi, 32);
17640 // AhiBlo = psllqi(AhiBlo, 32);
17641 // return AloBlo + AloBhi + AhiBlo;
17643 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17644 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17646 SDValue AhiBlo = Ahi;
17647 SDValue AloBhi = Bhi;
17648 // Bit cast to 32-bit vectors for MULUDQ
17649 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17650 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17651 A = DAG.getBitcast(MulVT, A);
17652 B = DAG.getBitcast(MulVT, B);
17653 Ahi = DAG.getBitcast(MulVT, Ahi);
17654 Bhi = DAG.getBitcast(MulVT, Bhi);
17656 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17657 // After shifting right const values the result may be all-zero.
17658 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17659 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17660 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17662 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17663 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17664 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17667 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17668 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17671 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17672 assert(Subtarget->isTargetWin64() && "Unexpected target");
17673 EVT VT = Op.getValueType();
17674 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17675 "Unexpected return type for lowering");
17679 switch (Op->getOpcode()) {
17680 default: llvm_unreachable("Unexpected request for libcall!");
17681 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17682 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17683 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17684 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17685 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17686 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17690 SDValue InChain = DAG.getEntryNode();
17692 TargetLowering::ArgListTy Args;
17693 TargetLowering::ArgListEntry Entry;
17694 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17695 EVT ArgVT = Op->getOperand(i).getValueType();
17696 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17697 "Unexpected argument type for lowering");
17698 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17699 Entry.Node = StackPtr;
17700 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17702 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17703 Entry.Ty = PointerType::get(ArgTy,0);
17704 Entry.isSExt = false;
17705 Entry.isZExt = false;
17706 Args.push_back(Entry);
17709 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17710 getPointerTy(DAG.getDataLayout()));
17712 TargetLowering::CallLoweringInfo CLI(DAG);
17713 CLI.setDebugLoc(dl).setChain(InChain)
17714 .setCallee(getLibcallCallingConv(LC),
17715 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17716 Callee, std::move(Args), 0)
17717 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17719 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17720 return DAG.getBitcast(VT, CallInfo.first);
17723 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17724 SelectionDAG &DAG) {
17725 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17726 EVT VT = Op0.getValueType();
17729 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17730 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17732 // PMULxD operations multiply each even value (starting at 0) of LHS with
17733 // the related value of RHS and produce a widen result.
17734 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17735 // => <2 x i64> <ae|cg>
17737 // In other word, to have all the results, we need to perform two PMULxD:
17738 // 1. one with the even values.
17739 // 2. one with the odd values.
17740 // To achieve #2, with need to place the odd values at an even position.
17742 // Place the odd value at an even position (basically, shift all values 1
17743 // step to the left):
17744 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17745 // <a|b|c|d> => <b|undef|d|undef>
17746 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17747 // <e|f|g|h> => <f|undef|h|undef>
17748 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17750 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17752 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17753 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17755 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17756 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17757 // => <2 x i64> <ae|cg>
17758 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17759 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17760 // => <2 x i64> <bf|dh>
17761 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17763 // Shuffle it back into the right order.
17764 SDValue Highs, Lows;
17765 if (VT == MVT::v8i32) {
17766 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17767 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17768 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17769 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17771 const int HighMask[] = {1, 5, 3, 7};
17772 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17773 const int LowMask[] = {0, 4, 2, 6};
17774 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17777 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17778 // unsigned multiply.
17779 if (IsSigned && !Subtarget->hasSSE41()) {
17780 SDValue ShAmt = DAG.getConstant(
17782 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17783 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17784 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17785 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17786 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17788 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17789 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17792 // The first result of MUL_LOHI is actually the low value, followed by the
17794 SDValue Ops[] = {Lows, Highs};
17795 return DAG.getMergeValues(Ops, dl);
17798 // Return true if the required (according to Opcode) shift-imm form is natively
17799 // supported by the Subtarget
17800 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17802 if (VT.getScalarSizeInBits() < 16)
17805 if (VT.is512BitVector() &&
17806 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17809 bool LShift = VT.is128BitVector() ||
17810 (VT.is256BitVector() && Subtarget->hasInt256());
17812 bool AShift = LShift && (Subtarget->hasVLX() ||
17813 (VT != MVT::v2i64 && VT != MVT::v4i64));
17814 return (Opcode == ISD::SRA) ? AShift : LShift;
17817 // The shift amount is a variable, but it is the same for all vector lanes.
17818 // These instructions are defined together with shift-immediate.
17820 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17822 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17825 // Return true if the required (according to Opcode) variable-shift form is
17826 // natively supported by the Subtarget
17827 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17830 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17833 // vXi16 supported only on AVX-512, BWI
17834 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17837 if (VT.is512BitVector() || Subtarget->hasVLX())
17840 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17841 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17842 return (Opcode == ISD::SRA) ? AShift : LShift;
17845 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17846 const X86Subtarget *Subtarget) {
17847 MVT VT = Op.getSimpleValueType();
17849 SDValue R = Op.getOperand(0);
17850 SDValue Amt = Op.getOperand(1);
17852 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17853 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17855 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17856 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17857 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17858 SDValue Ex = DAG.getBitcast(ExVT, R);
17860 if (ShiftAmt >= 32) {
17861 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17863 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17864 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17865 ShiftAmt - 32, DAG);
17866 if (VT == MVT::v2i64)
17867 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17868 if (VT == MVT::v4i64)
17869 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17870 {9, 1, 11, 3, 13, 5, 15, 7});
17872 // SRA upper i32, SHL whole i64 and select lower i32.
17873 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17876 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17877 Lower = DAG.getBitcast(ExVT, Lower);
17878 if (VT == MVT::v2i64)
17879 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17880 if (VT == MVT::v4i64)
17881 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17882 {8, 1, 10, 3, 12, 5, 14, 7});
17884 return DAG.getBitcast(VT, Ex);
17887 // Optimize shl/srl/sra with constant shift amount.
17888 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17889 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17890 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17892 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17893 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17895 // i64 SRA needs to be performed as partial shifts.
17896 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17897 Op.getOpcode() == ISD::SRA)
17898 return ArithmeticShiftRight64(ShiftAmt);
17900 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17901 unsigned NumElts = VT.getVectorNumElements();
17902 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17904 if (Op.getOpcode() == ISD::SHL) {
17905 // Simple i8 add case
17907 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17909 // Make a large shift.
17910 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17912 SHL = DAG.getBitcast(VT, SHL);
17913 // Zero out the rightmost bits.
17914 SmallVector<SDValue, 32> V(
17915 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17916 return DAG.getNode(ISD::AND, dl, VT, SHL,
17917 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17919 if (Op.getOpcode() == ISD::SRL) {
17920 // Make a large shift.
17921 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17923 SRL = DAG.getBitcast(VT, SRL);
17924 // Zero out the leftmost bits.
17925 SmallVector<SDValue, 32> V(
17926 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17927 return DAG.getNode(ISD::AND, dl, VT, SRL,
17928 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17930 if (Op.getOpcode() == ISD::SRA) {
17931 if (ShiftAmt == 7) {
17932 // ashr(R, 7) === cmp_slt(R, 0)
17933 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17934 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17937 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
17938 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17939 SmallVector<SDValue, 32> V(NumElts,
17940 DAG.getConstant(128 >> ShiftAmt, dl,
17942 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17943 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17944 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17947 llvm_unreachable("Unknown shift opcode.");
17952 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17953 if (!Subtarget->is64Bit() &&
17954 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
17956 // Peek through any splat that was introduced for i64 shift vectorization.
17957 int SplatIndex = -1;
17958 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
17959 if (SVN->isSplat()) {
17960 SplatIndex = SVN->getSplatIndex();
17961 Amt = Amt.getOperand(0);
17962 assert(SplatIndex < (int)VT.getVectorNumElements() &&
17963 "Splat shuffle referencing second operand");
17966 if (Amt.getOpcode() != ISD::BITCAST ||
17967 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
17970 Amt = Amt.getOperand(0);
17971 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17972 VT.getVectorNumElements();
17973 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17974 uint64_t ShiftAmt = 0;
17975 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
17976 for (unsigned i = 0; i != Ratio; ++i) {
17977 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
17981 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17984 // Check remaining shift amounts (if not a splat).
17985 if (SplatIndex < 0) {
17986 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17987 uint64_t ShAmt = 0;
17988 for (unsigned j = 0; j != Ratio; ++j) {
17989 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17993 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17995 if (ShAmt != ShiftAmt)
18000 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18001 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18003 if (Op.getOpcode() == ISD::SRA)
18004 return ArithmeticShiftRight64(ShiftAmt);
18010 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18011 const X86Subtarget* Subtarget) {
18012 MVT VT = Op.getSimpleValueType();
18014 SDValue R = Op.getOperand(0);
18015 SDValue Amt = Op.getOperand(1);
18017 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18018 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18020 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18021 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18023 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18025 EVT EltVT = VT.getVectorElementType();
18027 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18028 // Check if this build_vector node is doing a splat.
18029 // If so, then set BaseShAmt equal to the splat value.
18030 BaseShAmt = BV->getSplatValue();
18031 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18032 BaseShAmt = SDValue();
18034 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18035 Amt = Amt.getOperand(0);
18037 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18038 if (SVN && SVN->isSplat()) {
18039 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18040 SDValue InVec = Amt.getOperand(0);
18041 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18042 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18043 "Unexpected shuffle index found!");
18044 BaseShAmt = InVec.getOperand(SplatIdx);
18045 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18046 if (ConstantSDNode *C =
18047 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18048 if (C->getZExtValue() == SplatIdx)
18049 BaseShAmt = InVec.getOperand(1);
18054 // Avoid introducing an extract element from a shuffle.
18055 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18056 DAG.getIntPtrConstant(SplatIdx, dl));
18060 if (BaseShAmt.getNode()) {
18061 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18062 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18063 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18064 else if (EltVT.bitsLT(MVT::i32))
18065 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18067 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18071 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18072 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18073 Amt.getOpcode() == ISD::BITCAST &&
18074 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18075 Amt = Amt.getOperand(0);
18076 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18077 VT.getVectorNumElements();
18078 std::vector<SDValue> Vals(Ratio);
18079 for (unsigned i = 0; i != Ratio; ++i)
18080 Vals[i] = Amt.getOperand(i);
18081 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18082 for (unsigned j = 0; j != Ratio; ++j)
18083 if (Vals[j] != Amt.getOperand(i + j))
18087 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18088 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18093 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18094 SelectionDAG &DAG) {
18095 MVT VT = Op.getSimpleValueType();
18097 SDValue R = Op.getOperand(0);
18098 SDValue Amt = Op.getOperand(1);
18100 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18101 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18103 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18106 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18109 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18112 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18113 // shifts per-lane and then shuffle the partial results back together.
18114 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18115 // Splat the shift amounts so the scalar shifts above will catch it.
18116 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18117 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18118 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18119 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18120 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18123 // i64 vector arithmetic shift can be emulated with the transform:
18124 // M = lshr(SIGN_BIT, Amt)
18125 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18126 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18127 Op.getOpcode() == ISD::SRA) {
18128 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18129 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18130 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18131 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18132 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18136 // If possible, lower this packed shift into a vector multiply instead of
18137 // expanding it into a sequence of scalar shifts.
18138 // Do this only if the vector shift count is a constant build_vector.
18139 if (Op.getOpcode() == ISD::SHL &&
18140 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18141 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18142 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18143 SmallVector<SDValue, 8> Elts;
18144 EVT SVT = VT.getScalarType();
18145 unsigned SVTBits = SVT.getSizeInBits();
18146 const APInt &One = APInt(SVTBits, 1);
18147 unsigned NumElems = VT.getVectorNumElements();
18149 for (unsigned i=0; i !=NumElems; ++i) {
18150 SDValue Op = Amt->getOperand(i);
18151 if (Op->getOpcode() == ISD::UNDEF) {
18152 Elts.push_back(Op);
18156 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18157 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18158 uint64_t ShAmt = C.getZExtValue();
18159 if (ShAmt >= SVTBits) {
18160 Elts.push_back(DAG.getUNDEF(SVT));
18163 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18165 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18166 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18169 // Lower SHL with variable shift amount.
18170 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18171 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18173 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18174 DAG.getConstant(0x3f800000U, dl, VT));
18175 Op = DAG.getBitcast(MVT::v4f32, Op);
18176 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18177 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18180 // If possible, lower this shift as a sequence of two shifts by
18181 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18183 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18185 // Could be rewritten as:
18186 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18188 // The advantage is that the two shifts from the example would be
18189 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18190 // the vector shift into four scalar shifts plus four pairs of vector
18192 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18193 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18194 unsigned TargetOpcode = X86ISD::MOVSS;
18195 bool CanBeSimplified;
18196 // The splat value for the first packed shift (the 'X' from the example).
18197 SDValue Amt1 = Amt->getOperand(0);
18198 // The splat value for the second packed shift (the 'Y' from the example).
18199 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18200 Amt->getOperand(2);
18202 // See if it is possible to replace this node with a sequence of
18203 // two shifts followed by a MOVSS/MOVSD
18204 if (VT == MVT::v4i32) {
18205 // Check if it is legal to use a MOVSS.
18206 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18207 Amt2 == Amt->getOperand(3);
18208 if (!CanBeSimplified) {
18209 // Otherwise, check if we can still simplify this node using a MOVSD.
18210 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18211 Amt->getOperand(2) == Amt->getOperand(3);
18212 TargetOpcode = X86ISD::MOVSD;
18213 Amt2 = Amt->getOperand(2);
18216 // Do similar checks for the case where the machine value type
18218 CanBeSimplified = Amt1 == Amt->getOperand(1);
18219 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18220 CanBeSimplified = Amt2 == Amt->getOperand(i);
18222 if (!CanBeSimplified) {
18223 TargetOpcode = X86ISD::MOVSD;
18224 CanBeSimplified = true;
18225 Amt2 = Amt->getOperand(4);
18226 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18227 CanBeSimplified = Amt1 == Amt->getOperand(i);
18228 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18229 CanBeSimplified = Amt2 == Amt->getOperand(j);
18233 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18234 isa<ConstantSDNode>(Amt2)) {
18235 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18236 EVT CastVT = MVT::v4i32;
18238 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18239 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18241 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18242 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18243 if (TargetOpcode == X86ISD::MOVSD)
18244 CastVT = MVT::v2i64;
18245 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18246 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18247 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18249 return DAG.getBitcast(VT, Result);
18253 // v4i32 Non Uniform Shifts.
18254 // If the shift amount is constant we can shift each lane using the SSE2
18255 // immediate shifts, else we need to zero-extend each lane to the lower i64
18256 // and shift using the SSE2 variable shifts.
18257 // The separate results can then be blended together.
18258 if (VT == MVT::v4i32) {
18259 unsigned Opc = Op.getOpcode();
18260 SDValue Amt0, Amt1, Amt2, Amt3;
18261 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18262 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18263 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18264 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18265 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18267 // ISD::SHL is handled above but we include it here for completeness.
18270 llvm_unreachable("Unknown target vector shift node");
18272 Opc = X86ISD::VSHL;
18275 Opc = X86ISD::VSRL;
18278 Opc = X86ISD::VSRA;
18281 // The SSE2 shifts use the lower i64 as the same shift amount for
18282 // all lanes and the upper i64 is ignored. These shuffle masks
18283 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18284 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18285 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18286 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18287 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18288 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18291 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18292 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18293 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18294 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18295 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18296 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18297 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18300 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
18301 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18302 unsigned ShiftOpcode = Op->getOpcode();
18304 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18305 // On SSE41 targets we make use of the fact that VSELECT lowers
18306 // to PBLENDVB which selects bytes based just on the sign bit.
18307 if (Subtarget->hasSSE41()) {
18308 V0 = DAG.getBitcast(VT, V0);
18309 V1 = DAG.getBitcast(VT, V1);
18310 Sel = DAG.getBitcast(VT, Sel);
18311 return DAG.getBitcast(SelVT,
18312 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18314 // On pre-SSE41 targets we test for the sign bit by comparing to
18315 // zero - a negative value will set all bits of the lanes to true
18316 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18317 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18318 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18319 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18322 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18323 // We can safely do this using i16 shifts as we're only interested in
18324 // the 3 lower bits of each byte.
18325 Amt = DAG.getBitcast(ExtVT, Amt);
18326 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18327 Amt = DAG.getBitcast(VT, Amt);
18329 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18330 // r = VSELECT(r, shift(r, 4), a);
18332 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18333 R = SignBitSelect(VT, Amt, M, R);
18336 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18338 // r = VSELECT(r, shift(r, 2), a);
18339 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18340 R = SignBitSelect(VT, Amt, M, R);
18343 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18345 // return VSELECT(r, shift(r, 1), a);
18346 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18347 R = SignBitSelect(VT, Amt, M, R);
18351 if (Op->getOpcode() == ISD::SRA) {
18352 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18353 // so we can correctly sign extend. We don't care what happens to the
18355 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18356 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18357 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18358 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18359 ALo = DAG.getBitcast(ExtVT, ALo);
18360 AHi = DAG.getBitcast(ExtVT, AHi);
18361 RLo = DAG.getBitcast(ExtVT, RLo);
18362 RHi = DAG.getBitcast(ExtVT, RHi);
18364 // r = VSELECT(r, shift(r, 4), a);
18365 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18366 DAG.getConstant(4, dl, ExtVT));
18367 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18368 DAG.getConstant(4, dl, ExtVT));
18369 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18370 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18373 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18374 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18376 // r = VSELECT(r, shift(r, 2), a);
18377 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18378 DAG.getConstant(2, dl, ExtVT));
18379 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18380 DAG.getConstant(2, dl, ExtVT));
18381 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18382 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18385 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18386 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18388 // r = VSELECT(r, shift(r, 1), a);
18389 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18390 DAG.getConstant(1, dl, ExtVT));
18391 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18392 DAG.getConstant(1, dl, ExtVT));
18393 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18394 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18396 // Logical shift the result back to the lower byte, leaving a zero upper
18398 // meaning that we can safely pack with PACKUSWB.
18400 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18402 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18403 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18407 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18408 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18409 // solution better.
18410 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18411 MVT ExtVT = MVT::v8i32;
18413 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18414 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18415 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18416 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18417 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18420 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
18421 MVT ExtVT = MVT::v8i32;
18422 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18423 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18424 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18425 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18426 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18427 ALo = DAG.getBitcast(ExtVT, ALo);
18428 AHi = DAG.getBitcast(ExtVT, AHi);
18429 RLo = DAG.getBitcast(ExtVT, RLo);
18430 RHi = DAG.getBitcast(ExtVT, RHi);
18431 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18432 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18433 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18434 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18435 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18438 if (VT == MVT::v8i16) {
18439 unsigned ShiftOpcode = Op->getOpcode();
18441 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18442 // On SSE41 targets we make use of the fact that VSELECT lowers
18443 // to PBLENDVB which selects bytes based just on the sign bit.
18444 if (Subtarget->hasSSE41()) {
18445 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18446 V0 = DAG.getBitcast(ExtVT, V0);
18447 V1 = DAG.getBitcast(ExtVT, V1);
18448 Sel = DAG.getBitcast(ExtVT, Sel);
18449 return DAG.getBitcast(
18450 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18452 // On pre-SSE41 targets we splat the sign bit - a negative value will
18453 // set all bits of the lanes to true and VSELECT uses that in
18454 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18456 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18457 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18460 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18461 if (Subtarget->hasSSE41()) {
18462 // On SSE41 targets we need to replicate the shift mask in both
18463 // bytes for PBLENDVB.
18466 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18467 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18469 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18472 // r = VSELECT(r, shift(r, 8), a);
18473 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18474 R = SignBitSelect(Amt, M, R);
18477 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18479 // r = VSELECT(r, shift(r, 4), a);
18480 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18481 R = SignBitSelect(Amt, M, R);
18484 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18486 // r = VSELECT(r, shift(r, 2), a);
18487 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18488 R = SignBitSelect(Amt, M, R);
18491 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18493 // return VSELECT(r, shift(r, 1), a);
18494 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18495 R = SignBitSelect(Amt, M, R);
18499 // Decompose 256-bit shifts into smaller 128-bit shifts.
18500 if (VT.is256BitVector()) {
18501 unsigned NumElems = VT.getVectorNumElements();
18502 MVT EltVT = VT.getVectorElementType();
18503 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18505 // Extract the two vectors
18506 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18507 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18509 // Recreate the shift amount vectors
18510 SDValue Amt1, Amt2;
18511 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18512 // Constant shift amount
18513 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18514 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18515 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18517 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18518 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18520 // Variable shift amount
18521 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18522 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18525 // Issue new vector shifts for the smaller types
18526 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18527 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18529 // Concatenate the result back
18530 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18536 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18537 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18538 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18539 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18540 // has only one use.
18541 SDNode *N = Op.getNode();
18542 SDValue LHS = N->getOperand(0);
18543 SDValue RHS = N->getOperand(1);
18544 unsigned BaseOp = 0;
18547 switch (Op.getOpcode()) {
18548 default: llvm_unreachable("Unknown ovf instruction!");
18550 // A subtract of one will be selected as a INC. Note that INC doesn't
18551 // set CF, so we can't do this for UADDO.
18552 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18554 BaseOp = X86ISD::INC;
18555 Cond = X86::COND_O;
18558 BaseOp = X86ISD::ADD;
18559 Cond = X86::COND_O;
18562 BaseOp = X86ISD::ADD;
18563 Cond = X86::COND_B;
18566 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18567 // set CF, so we can't do this for USUBO.
18568 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18570 BaseOp = X86ISD::DEC;
18571 Cond = X86::COND_O;
18574 BaseOp = X86ISD::SUB;
18575 Cond = X86::COND_O;
18578 BaseOp = X86ISD::SUB;
18579 Cond = X86::COND_B;
18582 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18583 Cond = X86::COND_O;
18585 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18586 if (N->getValueType(0) == MVT::i8) {
18587 BaseOp = X86ISD::UMUL8;
18588 Cond = X86::COND_O;
18591 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18593 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18596 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18597 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18598 SDValue(Sum.getNode(), 2));
18600 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18604 // Also sets EFLAGS.
18605 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18606 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18609 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18610 DAG.getConstant(Cond, DL, MVT::i32),
18611 SDValue(Sum.getNode(), 1));
18613 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18616 /// Returns true if the operand type is exactly twice the native width, and
18617 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18618 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18619 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18620 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18621 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18624 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18625 else if (OpWidth == 128)
18626 return Subtarget->hasCmpxchg16b();
18631 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18632 return needsCmpXchgNb(SI->getValueOperand()->getType());
18635 // Note: this turns large loads into lock cmpxchg8b/16b.
18636 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18637 TargetLowering::AtomicExpansionKind
18638 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18639 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18640 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18641 : AtomicExpansionKind::None;
18644 TargetLowering::AtomicExpansionKind
18645 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18646 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18647 Type *MemType = AI->getType();
18649 // If the operand is too big, we must see if cmpxchg8/16b is available
18650 // and default to library calls otherwise.
18651 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18652 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18653 : AtomicExpansionKind::None;
18656 AtomicRMWInst::BinOp Op = AI->getOperation();
18659 llvm_unreachable("Unknown atomic operation");
18660 case AtomicRMWInst::Xchg:
18661 case AtomicRMWInst::Add:
18662 case AtomicRMWInst::Sub:
18663 // It's better to use xadd, xsub or xchg for these in all cases.
18664 return AtomicExpansionKind::None;
18665 case AtomicRMWInst::Or:
18666 case AtomicRMWInst::And:
18667 case AtomicRMWInst::Xor:
18668 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18669 // prefix to a normal instruction for these operations.
18670 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18671 : AtomicExpansionKind::None;
18672 case AtomicRMWInst::Nand:
18673 case AtomicRMWInst::Max:
18674 case AtomicRMWInst::Min:
18675 case AtomicRMWInst::UMax:
18676 case AtomicRMWInst::UMin:
18677 // These always require a non-trivial set of data operations on x86. We must
18678 // use a cmpxchg loop.
18679 return AtomicExpansionKind::CmpXChg;
18683 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18684 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18685 // no-sse2). There isn't any reason to disable it if the target processor
18687 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18691 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18692 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18693 Type *MemType = AI->getType();
18694 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18695 // there is no benefit in turning such RMWs into loads, and it is actually
18696 // harmful as it introduces a mfence.
18697 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18700 auto Builder = IRBuilder<>(AI);
18701 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18702 auto SynchScope = AI->getSynchScope();
18703 // We must restrict the ordering to avoid generating loads with Release or
18704 // ReleaseAcquire orderings.
18705 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18706 auto Ptr = AI->getPointerOperand();
18708 // Before the load we need a fence. Here is an example lifted from
18709 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18712 // x.store(1, relaxed);
18713 // r1 = y.fetch_add(0, release);
18715 // y.fetch_add(42, acquire);
18716 // r2 = x.load(relaxed);
18717 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18718 // lowered to just a load without a fence. A mfence flushes the store buffer,
18719 // making the optimization clearly correct.
18720 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18721 // otherwise, we might be able to be more aggressive on relaxed idempotent
18722 // rmw. In practice, they do not look useful, so we don't try to be
18723 // especially clever.
18724 if (SynchScope == SingleThread)
18725 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18726 // the IR level, so we must wrap it in an intrinsic.
18729 if (!hasMFENCE(*Subtarget))
18730 // FIXME: it might make sense to use a locked operation here but on a
18731 // different cache-line to prevent cache-line bouncing. In practice it
18732 // is probably a small win, and x86 processors without mfence are rare
18733 // enough that we do not bother.
18737 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18738 Builder.CreateCall(MFence, {});
18740 // Finally we can emit the atomic load.
18741 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18742 AI->getType()->getPrimitiveSizeInBits());
18743 Loaded->setAtomic(Order, SynchScope);
18744 AI->replaceAllUsesWith(Loaded);
18745 AI->eraseFromParent();
18749 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18750 SelectionDAG &DAG) {
18752 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18753 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18754 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18755 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18757 // The only fence that needs an instruction is a sequentially-consistent
18758 // cross-thread fence.
18759 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18760 if (hasMFENCE(*Subtarget))
18761 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18763 SDValue Chain = Op.getOperand(0);
18764 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18766 DAG.getRegister(X86::ESP, MVT::i32), // Base
18767 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18768 DAG.getRegister(0, MVT::i32), // Index
18769 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18770 DAG.getRegister(0, MVT::i32), // Segment.
18774 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18775 return SDValue(Res, 0);
18778 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18779 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18782 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18783 SelectionDAG &DAG) {
18784 MVT T = Op.getSimpleValueType();
18788 switch(T.SimpleTy) {
18789 default: llvm_unreachable("Invalid value type!");
18790 case MVT::i8: Reg = X86::AL; size = 1; break;
18791 case MVT::i16: Reg = X86::AX; size = 2; break;
18792 case MVT::i32: Reg = X86::EAX; size = 4; break;
18794 assert(Subtarget->is64Bit() && "Node not type legal!");
18795 Reg = X86::RAX; size = 8;
18798 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18799 Op.getOperand(2), SDValue());
18800 SDValue Ops[] = { cpIn.getValue(0),
18803 DAG.getTargetConstant(size, DL, MVT::i8),
18804 cpIn.getValue(1) };
18805 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18806 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18807 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18811 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18812 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18813 MVT::i32, cpOut.getValue(2));
18814 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18815 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18818 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18819 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18820 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18824 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18825 SelectionDAG &DAG) {
18826 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18827 MVT DstVT = Op.getSimpleValueType();
18829 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18830 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18831 if (DstVT != MVT::f64)
18832 // This conversion needs to be expanded.
18835 SDValue InVec = Op->getOperand(0);
18837 unsigned NumElts = SrcVT.getVectorNumElements();
18838 EVT SVT = SrcVT.getVectorElementType();
18840 // Widen the vector in input in the case of MVT::v2i32.
18841 // Example: from MVT::v2i32 to MVT::v4i32.
18842 SmallVector<SDValue, 16> Elts;
18843 for (unsigned i = 0, e = NumElts; i != e; ++i)
18844 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18845 DAG.getIntPtrConstant(i, dl)));
18847 // Explicitly mark the extra elements as Undef.
18848 Elts.append(NumElts, DAG.getUNDEF(SVT));
18850 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18851 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18852 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18853 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18854 DAG.getIntPtrConstant(0, dl));
18857 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18858 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18859 assert((DstVT == MVT::i64 ||
18860 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18861 "Unexpected custom BITCAST");
18862 // i64 <=> MMX conversions are Legal.
18863 if (SrcVT==MVT::i64 && DstVT.isVector())
18865 if (DstVT==MVT::i64 && SrcVT.isVector())
18867 // MMX <=> MMX conversions are Legal.
18868 if (SrcVT.isVector() && DstVT.isVector())
18870 // All other conversions need to be expanded.
18874 /// Compute the horizontal sum of bytes in V for the elements of VT.
18876 /// Requires V to be a byte vector and VT to be an integer vector type with
18877 /// wider elements than V's type. The width of the elements of VT determines
18878 /// how many bytes of V are summed horizontally to produce each element of the
18880 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18881 const X86Subtarget *Subtarget,
18882 SelectionDAG &DAG) {
18884 MVT ByteVecVT = V.getSimpleValueType();
18885 MVT EltVT = VT.getVectorElementType();
18886 int NumElts = VT.getVectorNumElements();
18887 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18888 "Expected value to have byte element type.");
18889 assert(EltVT != MVT::i8 &&
18890 "Horizontal byte sum only makes sense for wider elements!");
18891 unsigned VecSize = VT.getSizeInBits();
18892 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18894 // PSADBW instruction horizontally add all bytes and leave the result in i64
18895 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18896 if (EltVT == MVT::i64) {
18897 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18898 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18899 return DAG.getBitcast(VT, V);
18902 if (EltVT == MVT::i32) {
18903 // We unpack the low half and high half into i32s interleaved with zeros so
18904 // that we can use PSADBW to horizontally sum them. The most useful part of
18905 // this is that it lines up the results of two PSADBW instructions to be
18906 // two v2i64 vectors which concatenated are the 4 population counts. We can
18907 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18908 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18909 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18910 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18912 // Do the horizontal sums into two v2i64s.
18913 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18914 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18915 DAG.getBitcast(ByteVecVT, Low), Zeros);
18916 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18917 DAG.getBitcast(ByteVecVT, High), Zeros);
18919 // Merge them together.
18920 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18921 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18922 DAG.getBitcast(ShortVecVT, Low),
18923 DAG.getBitcast(ShortVecVT, High));
18925 return DAG.getBitcast(VT, V);
18928 // The only element type left is i16.
18929 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18931 // To obtain pop count for each i16 element starting from the pop count for
18932 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18933 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18934 // directly supported.
18935 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18936 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18937 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18938 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18939 DAG.getBitcast(ByteVecVT, V));
18940 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18943 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18944 const X86Subtarget *Subtarget,
18945 SelectionDAG &DAG) {
18946 MVT VT = Op.getSimpleValueType();
18947 MVT EltVT = VT.getVectorElementType();
18948 unsigned VecSize = VT.getSizeInBits();
18950 // Implement a lookup table in register by using an algorithm based on:
18951 // http://wm.ite.pl/articles/sse-popcount.html
18953 // The general idea is that every lower byte nibble in the input vector is an
18954 // index into a in-register pre-computed pop count table. We then split up the
18955 // input vector in two new ones: (1) a vector with only the shifted-right
18956 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18957 // masked out higher ones) for each byte. PSHUB is used separately with both
18958 // to index the in-register table. Next, both are added and the result is a
18959 // i8 vector where each element contains the pop count for input byte.
18961 // To obtain the pop count for elements != i8, we follow up with the same
18962 // approach and use additional tricks as described below.
18964 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18965 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18966 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18967 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18969 int NumByteElts = VecSize / 8;
18970 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18971 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18972 SmallVector<SDValue, 16> LUTVec;
18973 for (int i = 0; i < NumByteElts; ++i)
18974 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18975 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18976 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18977 DAG.getConstant(0x0F, DL, MVT::i8));
18978 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18981 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18982 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18983 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18986 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18988 // The input vector is used as the shuffle mask that index elements into the
18989 // LUT. After counting low and high nibbles, add the vector to obtain the
18990 // final pop count per i8 element.
18991 SDValue HighPopCnt =
18992 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18993 SDValue LowPopCnt =
18994 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18995 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18997 if (EltVT == MVT::i8)
19000 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19003 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19004 const X86Subtarget *Subtarget,
19005 SelectionDAG &DAG) {
19006 MVT VT = Op.getSimpleValueType();
19007 assert(VT.is128BitVector() &&
19008 "Only 128-bit vector bitmath lowering supported.");
19010 int VecSize = VT.getSizeInBits();
19011 MVT EltVT = VT.getVectorElementType();
19012 int Len = EltVT.getSizeInBits();
19014 // This is the vectorized version of the "best" algorithm from
19015 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19016 // with a minor tweak to use a series of adds + shifts instead of vector
19017 // multiplications. Implemented for all integer vector types. We only use
19018 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19019 // much faster, even faster than using native popcnt instructions.
19021 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19022 MVT VT = V.getSimpleValueType();
19023 SmallVector<SDValue, 32> Shifters(
19024 VT.getVectorNumElements(),
19025 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19026 return DAG.getNode(OpCode, DL, VT, V,
19027 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19029 auto GetMask = [&](SDValue V, APInt Mask) {
19030 MVT VT = V.getSimpleValueType();
19031 SmallVector<SDValue, 32> Masks(
19032 VT.getVectorNumElements(),
19033 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19034 return DAG.getNode(ISD::AND, DL, VT, V,
19035 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19038 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19039 // x86, so set the SRL type to have elements at least i16 wide. This is
19040 // correct because all of our SRLs are followed immediately by a mask anyways
19041 // that handles any bits that sneak into the high bits of the byte elements.
19042 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19046 // v = v - ((v >> 1) & 0x55555555...)
19048 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19049 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19050 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19052 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19053 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19054 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19055 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19056 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19058 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19059 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19060 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19061 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19063 // At this point, V contains the byte-wise population count, and we are
19064 // merely doing a horizontal sum if necessary to get the wider element
19066 if (EltVT == MVT::i8)
19069 return LowerHorizontalByteSum(
19070 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19074 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19075 SelectionDAG &DAG) {
19076 MVT VT = Op.getSimpleValueType();
19077 // FIXME: Need to add AVX-512 support here!
19078 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19079 "Unknown CTPOP type to handle");
19080 SDLoc DL(Op.getNode());
19081 SDValue Op0 = Op.getOperand(0);
19083 if (!Subtarget->hasSSSE3()) {
19084 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19085 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19086 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19089 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19090 unsigned NumElems = VT.getVectorNumElements();
19092 // Extract each 128-bit vector, compute pop count and concat the result.
19093 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19094 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19096 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19097 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19098 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19101 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19104 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19105 SelectionDAG &DAG) {
19106 assert(Op.getValueType().isVector() &&
19107 "We only do custom lowering for vector population count.");
19108 return LowerVectorCTPOP(Op, Subtarget, DAG);
19111 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19112 SDNode *Node = Op.getNode();
19114 EVT T = Node->getValueType(0);
19115 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19116 DAG.getConstant(0, dl, T), Node->getOperand(2));
19117 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19118 cast<AtomicSDNode>(Node)->getMemoryVT(),
19119 Node->getOperand(0),
19120 Node->getOperand(1), negOp,
19121 cast<AtomicSDNode>(Node)->getMemOperand(),
19122 cast<AtomicSDNode>(Node)->getOrdering(),
19123 cast<AtomicSDNode>(Node)->getSynchScope());
19126 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19127 SDNode *Node = Op.getNode();
19129 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19131 // Convert seq_cst store -> xchg
19132 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19133 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19134 // (The only way to get a 16-byte store is cmpxchg16b)
19135 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19136 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19137 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19138 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19139 cast<AtomicSDNode>(Node)->getMemoryVT(),
19140 Node->getOperand(0),
19141 Node->getOperand(1), Node->getOperand(2),
19142 cast<AtomicSDNode>(Node)->getMemOperand(),
19143 cast<AtomicSDNode>(Node)->getOrdering(),
19144 cast<AtomicSDNode>(Node)->getSynchScope());
19145 return Swap.getValue(1);
19147 // Other atomic stores have a simple pattern.
19151 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19152 EVT VT = Op.getNode()->getSimpleValueType(0);
19154 // Let legalize expand this if it isn't a legal type yet.
19155 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19158 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19161 bool ExtraOp = false;
19162 switch (Op.getOpcode()) {
19163 default: llvm_unreachable("Invalid code");
19164 case ISD::ADDC: Opc = X86ISD::ADD; break;
19165 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19166 case ISD::SUBC: Opc = X86ISD::SUB; break;
19167 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19171 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19173 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19174 Op.getOperand(1), Op.getOperand(2));
19177 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19178 SelectionDAG &DAG) {
19179 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19181 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19182 // which returns the values as { float, float } (in XMM0) or
19183 // { double, double } (which is returned in XMM0, XMM1).
19185 SDValue Arg = Op.getOperand(0);
19186 EVT ArgVT = Arg.getValueType();
19187 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19189 TargetLowering::ArgListTy Args;
19190 TargetLowering::ArgListEntry Entry;
19194 Entry.isSExt = false;
19195 Entry.isZExt = false;
19196 Args.push_back(Entry);
19198 bool isF64 = ArgVT == MVT::f64;
19199 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19200 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19201 // the results are returned via SRet in memory.
19202 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19203 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19205 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19207 Type *RetTy = isF64
19208 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19209 : (Type*)VectorType::get(ArgTy, 4);
19211 TargetLowering::CallLoweringInfo CLI(DAG);
19212 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19213 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19215 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19218 // Returned in xmm0 and xmm1.
19219 return CallResult.first;
19221 // Returned in bits 0:31 and 32:64 xmm0.
19222 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19223 CallResult.first, DAG.getIntPtrConstant(0, dl));
19224 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19225 CallResult.first, DAG.getIntPtrConstant(1, dl));
19226 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19227 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19230 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19231 SelectionDAG &DAG) {
19232 assert(Subtarget->hasAVX512() &&
19233 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19235 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19236 EVT VT = N->getValue().getValueType();
19237 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19240 // X86 scatter kills mask register, so its type should be added to
19241 // the list of return values
19242 if (N->getNumValues() == 1) {
19243 SDValue Index = N->getIndex();
19244 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19245 !Index.getValueType().is512BitVector())
19246 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19248 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19249 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19250 N->getOperand(3), Index };
19252 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19253 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19254 return SDValue(NewScatter.getNode(), 0);
19259 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19260 SelectionDAG &DAG) {
19261 assert(Subtarget->hasAVX512() &&
19262 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19264 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19265 EVT VT = Op.getValueType();
19266 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19269 SDValue Index = N->getIndex();
19270 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19271 !Index.getValueType().is512BitVector()) {
19272 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19273 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19274 N->getOperand(3), Index };
19275 DAG.UpdateNodeOperands(N, Ops);
19280 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19281 SelectionDAG &DAG) const {
19282 // TODO: Eventually, the lowering of these nodes should be informed by or
19283 // deferred to the GC strategy for the function in which they appear. For
19284 // now, however, they must be lowered to something. Since they are logically
19285 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19286 // require special handling for these nodes), lower them as literal NOOPs for
19288 SmallVector<SDValue, 2> Ops;
19290 Ops.push_back(Op.getOperand(0));
19291 if (Op->getGluedNode())
19292 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19295 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19296 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19301 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19302 SelectionDAG &DAG) const {
19303 // TODO: Eventually, the lowering of these nodes should be informed by or
19304 // deferred to the GC strategy for the function in which they appear. For
19305 // now, however, they must be lowered to something. Since they are logically
19306 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19307 // require special handling for these nodes), lower them as literal NOOPs for
19309 SmallVector<SDValue, 2> Ops;
19311 Ops.push_back(Op.getOperand(0));
19312 if (Op->getGluedNode())
19313 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19316 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19317 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19322 /// LowerOperation - Provide custom lowering hooks for some operations.
19324 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19325 switch (Op.getOpcode()) {
19326 default: llvm_unreachable("Should not custom lower this!");
19327 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19328 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19329 return LowerCMP_SWAP(Op, Subtarget, DAG);
19330 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19331 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19332 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19333 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19334 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19335 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19336 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19337 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19338 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19339 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19340 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19341 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19342 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19343 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19344 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19345 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19346 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19347 case ISD::SHL_PARTS:
19348 case ISD::SRA_PARTS:
19349 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19350 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19351 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19352 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19353 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19354 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19355 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19356 case ISD::SIGN_EXTEND_VECTOR_INREG:
19357 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19358 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19359 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19360 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19361 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19363 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19364 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19365 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19366 case ISD::SETCC: return LowerSETCC(Op, DAG);
19367 case ISD::SELECT: return LowerSELECT(Op, DAG);
19368 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19369 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19370 case ISD::VASTART: return LowerVASTART(Op, DAG);
19371 case ISD::VAARG: return LowerVAARG(Op, DAG);
19372 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19373 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19374 case ISD::INTRINSIC_VOID:
19375 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19376 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19377 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19378 case ISD::FRAME_TO_ARGS_OFFSET:
19379 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19380 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19381 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19382 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19383 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19384 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19385 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19386 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19387 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19388 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19390 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19391 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19392 case ISD::UMUL_LOHI:
19393 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19396 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19402 case ISD::UMULO: return LowerXALUO(Op, DAG);
19403 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19404 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19408 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19409 case ISD::ADD: return LowerADD(Op, DAG);
19410 case ISD::SUB: return LowerSUB(Op, DAG);
19414 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19415 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19416 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19417 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19418 case ISD::GC_TRANSITION_START:
19419 return LowerGC_TRANSITION_START(Op, DAG);
19420 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19424 /// ReplaceNodeResults - Replace a node with an illegal result type
19425 /// with a new node built out of custom code.
19426 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19427 SmallVectorImpl<SDValue>&Results,
19428 SelectionDAG &DAG) const {
19430 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19431 switch (N->getOpcode()) {
19433 llvm_unreachable("Do not know how to custom type legalize this operation!");
19434 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19435 case X86ISD::FMINC:
19437 case X86ISD::FMAXC:
19438 case X86ISD::FMAX: {
19439 EVT VT = N->getValueType(0);
19440 if (VT != MVT::v2f32)
19441 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19442 SDValue UNDEF = DAG.getUNDEF(VT);
19443 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19444 N->getOperand(0), UNDEF);
19445 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19446 N->getOperand(1), UNDEF);
19447 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19450 case ISD::SIGN_EXTEND_INREG:
19455 // We don't want to expand or promote these.
19462 case ISD::UDIVREM: {
19463 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19464 Results.push_back(V);
19467 case ISD::FP_TO_SINT:
19468 case ISD::FP_TO_UINT: {
19469 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19471 std::pair<SDValue,SDValue> Vals =
19472 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19473 SDValue FIST = Vals.first, StackSlot = Vals.second;
19474 if (FIST.getNode()) {
19475 EVT VT = N->getValueType(0);
19476 // Return a load from the stack slot.
19477 if (StackSlot.getNode())
19478 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19479 MachinePointerInfo(),
19480 false, false, false, 0));
19482 Results.push_back(FIST);
19486 case ISD::UINT_TO_FP: {
19487 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19488 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19489 N->getValueType(0) != MVT::v2f32)
19491 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19493 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19495 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19496 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19497 DAG.getBitcast(MVT::v2i64, VBias));
19498 Or = DAG.getBitcast(MVT::v2f64, Or);
19499 // TODO: Are there any fast-math-flags to propagate here?
19500 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19501 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19504 case ISD::FP_ROUND: {
19505 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19507 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19508 Results.push_back(V);
19511 case ISD::FP_EXTEND: {
19512 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19513 // No other ValueType for FP_EXTEND should reach this point.
19514 assert(N->getValueType(0) == MVT::v2f32 &&
19515 "Do not know how to legalize this Node");
19518 case ISD::INTRINSIC_W_CHAIN: {
19519 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19521 default : llvm_unreachable("Do not know how to custom type "
19522 "legalize this intrinsic operation!");
19523 case Intrinsic::x86_rdtsc:
19524 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19526 case Intrinsic::x86_rdtscp:
19527 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19529 case Intrinsic::x86_rdpmc:
19530 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19533 case ISD::READCYCLECOUNTER: {
19534 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19537 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19538 EVT T = N->getValueType(0);
19539 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19540 bool Regs64bit = T == MVT::i128;
19541 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19542 SDValue cpInL, cpInH;
19543 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19544 DAG.getConstant(0, dl, HalfT));
19545 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19546 DAG.getConstant(1, dl, HalfT));
19547 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19548 Regs64bit ? X86::RAX : X86::EAX,
19550 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19551 Regs64bit ? X86::RDX : X86::EDX,
19552 cpInH, cpInL.getValue(1));
19553 SDValue swapInL, swapInH;
19554 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19555 DAG.getConstant(0, dl, HalfT));
19556 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19557 DAG.getConstant(1, dl, HalfT));
19558 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19559 Regs64bit ? X86::RBX : X86::EBX,
19560 swapInL, cpInH.getValue(1));
19561 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19562 Regs64bit ? X86::RCX : X86::ECX,
19563 swapInH, swapInL.getValue(1));
19564 SDValue Ops[] = { swapInH.getValue(0),
19566 swapInH.getValue(1) };
19567 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19568 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19569 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19570 X86ISD::LCMPXCHG8_DAG;
19571 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19572 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19573 Regs64bit ? X86::RAX : X86::EAX,
19574 HalfT, Result.getValue(1));
19575 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19576 Regs64bit ? X86::RDX : X86::EDX,
19577 HalfT, cpOutL.getValue(2));
19578 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19580 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19581 MVT::i32, cpOutH.getValue(2));
19583 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19584 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19585 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19587 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19588 Results.push_back(Success);
19589 Results.push_back(EFLAGS.getValue(1));
19592 case ISD::ATOMIC_SWAP:
19593 case ISD::ATOMIC_LOAD_ADD:
19594 case ISD::ATOMIC_LOAD_SUB:
19595 case ISD::ATOMIC_LOAD_AND:
19596 case ISD::ATOMIC_LOAD_OR:
19597 case ISD::ATOMIC_LOAD_XOR:
19598 case ISD::ATOMIC_LOAD_NAND:
19599 case ISD::ATOMIC_LOAD_MIN:
19600 case ISD::ATOMIC_LOAD_MAX:
19601 case ISD::ATOMIC_LOAD_UMIN:
19602 case ISD::ATOMIC_LOAD_UMAX:
19603 case ISD::ATOMIC_LOAD: {
19604 // Delegate to generic TypeLegalization. Situations we can really handle
19605 // should have already been dealt with by AtomicExpandPass.cpp.
19608 case ISD::BITCAST: {
19609 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19610 EVT DstVT = N->getValueType(0);
19611 EVT SrcVT = N->getOperand(0)->getValueType(0);
19613 if (SrcVT != MVT::f64 ||
19614 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19617 unsigned NumElts = DstVT.getVectorNumElements();
19618 EVT SVT = DstVT.getVectorElementType();
19619 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19620 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19621 MVT::v2f64, N->getOperand(0));
19622 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19624 if (ExperimentalVectorWideningLegalization) {
19625 // If we are legalizing vectors by widening, we already have the desired
19626 // legal vector type, just return it.
19627 Results.push_back(ToVecInt);
19631 SmallVector<SDValue, 8> Elts;
19632 for (unsigned i = 0, e = NumElts; i != e; ++i)
19633 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19634 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19636 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19641 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19642 switch ((X86ISD::NodeType)Opcode) {
19643 case X86ISD::FIRST_NUMBER: break;
19644 case X86ISD::BSF: return "X86ISD::BSF";
19645 case X86ISD::BSR: return "X86ISD::BSR";
19646 case X86ISD::SHLD: return "X86ISD::SHLD";
19647 case X86ISD::SHRD: return "X86ISD::SHRD";
19648 case X86ISD::FAND: return "X86ISD::FAND";
19649 case X86ISD::FANDN: return "X86ISD::FANDN";
19650 case X86ISD::FOR: return "X86ISD::FOR";
19651 case X86ISD::FXOR: return "X86ISD::FXOR";
19652 case X86ISD::FILD: return "X86ISD::FILD";
19653 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19654 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19655 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19656 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19657 case X86ISD::FLD: return "X86ISD::FLD";
19658 case X86ISD::FST: return "X86ISD::FST";
19659 case X86ISD::CALL: return "X86ISD::CALL";
19660 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19661 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19662 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19663 case X86ISD::BT: return "X86ISD::BT";
19664 case X86ISD::CMP: return "X86ISD::CMP";
19665 case X86ISD::COMI: return "X86ISD::COMI";
19666 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19667 case X86ISD::CMPM: return "X86ISD::CMPM";
19668 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19669 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19670 case X86ISD::SETCC: return "X86ISD::SETCC";
19671 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19672 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19673 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19674 case X86ISD::CMOV: return "X86ISD::CMOV";
19675 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19676 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19677 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19678 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19679 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19680 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19681 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19682 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19683 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19684 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19685 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19686 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19687 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19688 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19689 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19690 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19691 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19692 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19693 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19694 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19695 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19696 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19697 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19698 case X86ISD::HADD: return "X86ISD::HADD";
19699 case X86ISD::HSUB: return "X86ISD::HSUB";
19700 case X86ISD::FHADD: return "X86ISD::FHADD";
19701 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19702 case X86ISD::ABS: return "X86ISD::ABS";
19703 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19704 case X86ISD::FMAX: return "X86ISD::FMAX";
19705 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19706 case X86ISD::FMIN: return "X86ISD::FMIN";
19707 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19708 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19709 case X86ISD::FMINC: return "X86ISD::FMINC";
19710 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19711 case X86ISD::FRCP: return "X86ISD::FRCP";
19712 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19713 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19714 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19715 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19716 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19717 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19718 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19719 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19720 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19721 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19722 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19723 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19724 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19725 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19726 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19727 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19728 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19729 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19730 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19731 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19732 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19733 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19734 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19735 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19736 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19737 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19738 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19739 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19740 case X86ISD::VSHL: return "X86ISD::VSHL";
19741 case X86ISD::VSRL: return "X86ISD::VSRL";
19742 case X86ISD::VSRA: return "X86ISD::VSRA";
19743 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19744 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19745 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19746 case X86ISD::CMPP: return "X86ISD::CMPP";
19747 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19748 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19749 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19750 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19751 case X86ISD::ADD: return "X86ISD::ADD";
19752 case X86ISD::SUB: return "X86ISD::SUB";
19753 case X86ISD::ADC: return "X86ISD::ADC";
19754 case X86ISD::SBB: return "X86ISD::SBB";
19755 case X86ISD::SMUL: return "X86ISD::SMUL";
19756 case X86ISD::UMUL: return "X86ISD::UMUL";
19757 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19758 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19759 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19760 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19761 case X86ISD::INC: return "X86ISD::INC";
19762 case X86ISD::DEC: return "X86ISD::DEC";
19763 case X86ISD::OR: return "X86ISD::OR";
19764 case X86ISD::XOR: return "X86ISD::XOR";
19765 case X86ISD::AND: return "X86ISD::AND";
19766 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19767 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19768 case X86ISD::PTEST: return "X86ISD::PTEST";
19769 case X86ISD::TESTP: return "X86ISD::TESTP";
19770 case X86ISD::TESTM: return "X86ISD::TESTM";
19771 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19772 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19773 case X86ISD::KTEST: return "X86ISD::KTEST";
19774 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19775 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19776 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19777 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19778 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19779 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19780 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19781 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19782 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19783 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19784 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19785 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19786 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19787 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19788 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19789 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19790 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19791 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19792 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19793 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19794 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19795 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19796 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19797 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19798 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19799 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19800 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19801 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19802 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19803 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19804 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19805 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19806 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19807 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19808 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19809 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19810 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19811 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19812 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19813 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19814 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19815 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19816 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19817 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19818 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19819 case X86ISD::SAHF: return "X86ISD::SAHF";
19820 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19821 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19822 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19823 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19824 case X86ISD::FMADD: return "X86ISD::FMADD";
19825 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19826 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19827 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19828 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19829 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19830 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19831 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19832 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19833 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19834 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19835 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19836 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19837 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19838 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19839 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19840 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19841 case X86ISD::XTEST: return "X86ISD::XTEST";
19842 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19843 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19844 case X86ISD::SELECT: return "X86ISD::SELECT";
19845 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19846 case X86ISD::RCP28: return "X86ISD::RCP28";
19847 case X86ISD::EXP2: return "X86ISD::EXP2";
19848 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19849 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19850 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19851 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19852 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19853 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19854 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19855 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19856 case X86ISD::ADDS: return "X86ISD::ADDS";
19857 case X86ISD::SUBS: return "X86ISD::SUBS";
19858 case X86ISD::AVG: return "X86ISD::AVG";
19859 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19860 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19861 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19862 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19863 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19864 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
19869 // isLegalAddressingMode - Return true if the addressing mode represented
19870 // by AM is legal for this target, for a load/store of the specified type.
19871 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19872 const AddrMode &AM, Type *Ty,
19873 unsigned AS) const {
19874 // X86 supports extremely general addressing modes.
19875 CodeModel::Model M = getTargetMachine().getCodeModel();
19876 Reloc::Model R = getTargetMachine().getRelocationModel();
19878 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19879 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19884 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19886 // If a reference to this global requires an extra load, we can't fold it.
19887 if (isGlobalStubReference(GVFlags))
19890 // If BaseGV requires a register for the PIC base, we cannot also have a
19891 // BaseReg specified.
19892 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19895 // If lower 4G is not available, then we must use rip-relative addressing.
19896 if ((M != CodeModel::Small || R != Reloc::Static) &&
19897 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19901 switch (AM.Scale) {
19907 // These scales always work.
19912 // These scales are formed with basereg+scalereg. Only accept if there is
19917 default: // Other stuff never works.
19924 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19925 unsigned Bits = Ty->getScalarSizeInBits();
19927 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19928 // particularly cheaper than those without.
19932 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19933 // variable shifts just as cheap as scalar ones.
19934 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19937 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19938 // fully general vector.
19942 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19943 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19945 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19946 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19947 return NumBits1 > NumBits2;
19950 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19951 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19954 if (!isTypeLegal(EVT::getEVT(Ty1)))
19957 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19959 // Assuming the caller doesn't have a zeroext or signext return parameter,
19960 // truncation all the way down to i1 is valid.
19964 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19965 return isInt<32>(Imm);
19968 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19969 // Can also use sub to handle negated immediates.
19970 return isInt<32>(Imm);
19973 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19974 if (!VT1.isInteger() || !VT2.isInteger())
19976 unsigned NumBits1 = VT1.getSizeInBits();
19977 unsigned NumBits2 = VT2.getSizeInBits();
19978 return NumBits1 > NumBits2;
19981 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19982 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19983 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19986 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19987 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19988 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19991 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19992 EVT VT1 = Val.getValueType();
19993 if (isZExtFree(VT1, VT2))
19996 if (Val.getOpcode() != ISD::LOAD)
19999 if (!VT1.isSimple() || !VT1.isInteger() ||
20000 !VT2.isSimple() || !VT2.isInteger())
20003 switch (VT1.getSimpleVT().SimpleTy) {
20008 // X86 has 8, 16, and 32-bit zero-extending loads.
20015 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20018 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20019 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20022 VT = VT.getScalarType();
20024 if (!VT.isSimple())
20027 switch (VT.getSimpleVT().SimpleTy) {
20038 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20039 // i16 instructions are longer (0x66 prefix) and potentially slower.
20040 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20043 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20044 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20045 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20046 /// are assumed to be legal.
20048 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20050 if (!VT.isSimple())
20053 // Not for i1 vectors
20054 if (VT.getScalarType() == MVT::i1)
20057 // Very little shuffling can be done for 64-bit vectors right now.
20058 if (VT.getSizeInBits() == 64)
20061 // We only care that the types being shuffled are legal. The lowering can
20062 // handle any possible shuffle mask that results.
20063 return isTypeLegal(VT.getSimpleVT());
20067 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20069 // Just delegate to the generic legality, clear masks aren't special.
20070 return isShuffleMaskLegal(Mask, VT);
20073 //===----------------------------------------------------------------------===//
20074 // X86 Scheduler Hooks
20075 //===----------------------------------------------------------------------===//
20077 /// Utility function to emit xbegin specifying the start of an RTM region.
20078 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20079 const TargetInstrInfo *TII) {
20080 DebugLoc DL = MI->getDebugLoc();
20082 const BasicBlock *BB = MBB->getBasicBlock();
20083 MachineFunction::iterator I = MBB;
20086 // For the v = xbegin(), we generate
20097 MachineBasicBlock *thisMBB = MBB;
20098 MachineFunction *MF = MBB->getParent();
20099 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20100 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20101 MF->insert(I, mainMBB);
20102 MF->insert(I, sinkMBB);
20104 // Transfer the remainder of BB and its successor edges to sinkMBB.
20105 sinkMBB->splice(sinkMBB->begin(), MBB,
20106 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20107 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20111 // # fallthrough to mainMBB
20112 // # abortion to sinkMBB
20113 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20114 thisMBB->addSuccessor(mainMBB);
20115 thisMBB->addSuccessor(sinkMBB);
20119 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20120 mainMBB->addSuccessor(sinkMBB);
20123 // EAX is live into the sinkMBB
20124 sinkMBB->addLiveIn(X86::EAX);
20125 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20126 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20129 MI->eraseFromParent();
20133 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20134 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20135 // in the .td file.
20136 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20137 const TargetInstrInfo *TII) {
20139 switch (MI->getOpcode()) {
20140 default: llvm_unreachable("illegal opcode!");
20141 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20142 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20143 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20144 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20145 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20146 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20147 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20148 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20151 DebugLoc dl = MI->getDebugLoc();
20152 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20154 unsigned NumArgs = MI->getNumOperands();
20155 for (unsigned i = 1; i < NumArgs; ++i) {
20156 MachineOperand &Op = MI->getOperand(i);
20157 if (!(Op.isReg() && Op.isImplicit()))
20158 MIB.addOperand(Op);
20160 if (MI->hasOneMemOperand())
20161 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20163 BuildMI(*BB, MI, dl,
20164 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20165 .addReg(X86::XMM0);
20167 MI->eraseFromParent();
20171 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20172 // defs in an instruction pattern
20173 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20174 const TargetInstrInfo *TII) {
20176 switch (MI->getOpcode()) {
20177 default: llvm_unreachable("illegal opcode!");
20178 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20179 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20180 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20181 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20182 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20183 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20184 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20185 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20188 DebugLoc dl = MI->getDebugLoc();
20189 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20191 unsigned NumArgs = MI->getNumOperands(); // remove the results
20192 for (unsigned i = 1; i < NumArgs; ++i) {
20193 MachineOperand &Op = MI->getOperand(i);
20194 if (!(Op.isReg() && Op.isImplicit()))
20195 MIB.addOperand(Op);
20197 if (MI->hasOneMemOperand())
20198 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20200 BuildMI(*BB, MI, dl,
20201 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20204 MI->eraseFromParent();
20208 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20209 const X86Subtarget *Subtarget) {
20210 DebugLoc dl = MI->getDebugLoc();
20211 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20212 // Address into RAX/EAX, other two args into ECX, EDX.
20213 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20214 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20215 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20216 for (int i = 0; i < X86::AddrNumOperands; ++i)
20217 MIB.addOperand(MI->getOperand(i));
20219 unsigned ValOps = X86::AddrNumOperands;
20220 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20221 .addReg(MI->getOperand(ValOps).getReg());
20222 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20223 .addReg(MI->getOperand(ValOps+1).getReg());
20225 // The instruction doesn't actually take any operands though.
20226 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20228 MI->eraseFromParent(); // The pseudo is gone now.
20232 MachineBasicBlock *
20233 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20234 MachineBasicBlock *MBB) const {
20235 // Emit va_arg instruction on X86-64.
20237 // Operands to this pseudo-instruction:
20238 // 0 ) Output : destination address (reg)
20239 // 1-5) Input : va_list address (addr, i64mem)
20240 // 6 ) ArgSize : Size (in bytes) of vararg type
20241 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20242 // 8 ) Align : Alignment of type
20243 // 9 ) EFLAGS (implicit-def)
20245 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20246 static_assert(X86::AddrNumOperands == 5,
20247 "VAARG_64 assumes 5 address operands");
20249 unsigned DestReg = MI->getOperand(0).getReg();
20250 MachineOperand &Base = MI->getOperand(1);
20251 MachineOperand &Scale = MI->getOperand(2);
20252 MachineOperand &Index = MI->getOperand(3);
20253 MachineOperand &Disp = MI->getOperand(4);
20254 MachineOperand &Segment = MI->getOperand(5);
20255 unsigned ArgSize = MI->getOperand(6).getImm();
20256 unsigned ArgMode = MI->getOperand(7).getImm();
20257 unsigned Align = MI->getOperand(8).getImm();
20259 // Memory Reference
20260 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20261 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20262 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20264 // Machine Information
20265 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20266 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20267 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20268 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20269 DebugLoc DL = MI->getDebugLoc();
20271 // struct va_list {
20274 // i64 overflow_area (address)
20275 // i64 reg_save_area (address)
20277 // sizeof(va_list) = 24
20278 // alignment(va_list) = 8
20280 unsigned TotalNumIntRegs = 6;
20281 unsigned TotalNumXMMRegs = 8;
20282 bool UseGPOffset = (ArgMode == 1);
20283 bool UseFPOffset = (ArgMode == 2);
20284 unsigned MaxOffset = TotalNumIntRegs * 8 +
20285 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20287 /* Align ArgSize to a multiple of 8 */
20288 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20289 bool NeedsAlign = (Align > 8);
20291 MachineBasicBlock *thisMBB = MBB;
20292 MachineBasicBlock *overflowMBB;
20293 MachineBasicBlock *offsetMBB;
20294 MachineBasicBlock *endMBB;
20296 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20297 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20298 unsigned OffsetReg = 0;
20300 if (!UseGPOffset && !UseFPOffset) {
20301 // If we only pull from the overflow region, we don't create a branch.
20302 // We don't need to alter control flow.
20303 OffsetDestReg = 0; // unused
20304 OverflowDestReg = DestReg;
20306 offsetMBB = nullptr;
20307 overflowMBB = thisMBB;
20310 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20311 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20312 // If not, pull from overflow_area. (branch to overflowMBB)
20317 // offsetMBB overflowMBB
20322 // Registers for the PHI in endMBB
20323 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20324 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20326 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20327 MachineFunction *MF = MBB->getParent();
20328 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20329 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20330 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20332 MachineFunction::iterator MBBIter = MBB;
20335 // Insert the new basic blocks
20336 MF->insert(MBBIter, offsetMBB);
20337 MF->insert(MBBIter, overflowMBB);
20338 MF->insert(MBBIter, endMBB);
20340 // Transfer the remainder of MBB and its successor edges to endMBB.
20341 endMBB->splice(endMBB->begin(), thisMBB,
20342 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20343 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20345 // Make offsetMBB and overflowMBB successors of thisMBB
20346 thisMBB->addSuccessor(offsetMBB);
20347 thisMBB->addSuccessor(overflowMBB);
20349 // endMBB is a successor of both offsetMBB and overflowMBB
20350 offsetMBB->addSuccessor(endMBB);
20351 overflowMBB->addSuccessor(endMBB);
20353 // Load the offset value into a register
20354 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20355 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20359 .addDisp(Disp, UseFPOffset ? 4 : 0)
20360 .addOperand(Segment)
20361 .setMemRefs(MMOBegin, MMOEnd);
20363 // Check if there is enough room left to pull this argument.
20364 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20366 .addImm(MaxOffset + 8 - ArgSizeA8);
20368 // Branch to "overflowMBB" if offset >= max
20369 // Fall through to "offsetMBB" otherwise
20370 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20371 .addMBB(overflowMBB);
20374 // In offsetMBB, emit code to use the reg_save_area.
20376 assert(OffsetReg != 0);
20378 // Read the reg_save_area address.
20379 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20380 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20385 .addOperand(Segment)
20386 .setMemRefs(MMOBegin, MMOEnd);
20388 // Zero-extend the offset
20389 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20390 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20393 .addImm(X86::sub_32bit);
20395 // Add the offset to the reg_save_area to get the final address.
20396 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20397 .addReg(OffsetReg64)
20398 .addReg(RegSaveReg);
20400 // Compute the offset for the next argument
20401 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20402 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20404 .addImm(UseFPOffset ? 16 : 8);
20406 // Store it back into the va_list.
20407 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20411 .addDisp(Disp, UseFPOffset ? 4 : 0)
20412 .addOperand(Segment)
20413 .addReg(NextOffsetReg)
20414 .setMemRefs(MMOBegin, MMOEnd);
20417 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20422 // Emit code to use overflow area
20425 // Load the overflow_area address into a register.
20426 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20427 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20432 .addOperand(Segment)
20433 .setMemRefs(MMOBegin, MMOEnd);
20435 // If we need to align it, do so. Otherwise, just copy the address
20436 // to OverflowDestReg.
20438 // Align the overflow address
20439 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20440 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20442 // aligned_addr = (addr + (align-1)) & ~(align-1)
20443 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20444 .addReg(OverflowAddrReg)
20447 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20449 .addImm(~(uint64_t)(Align-1));
20451 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20452 .addReg(OverflowAddrReg);
20455 // Compute the next overflow address after this argument.
20456 // (the overflow address should be kept 8-byte aligned)
20457 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20458 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20459 .addReg(OverflowDestReg)
20460 .addImm(ArgSizeA8);
20462 // Store the new overflow address.
20463 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20468 .addOperand(Segment)
20469 .addReg(NextAddrReg)
20470 .setMemRefs(MMOBegin, MMOEnd);
20472 // If we branched, emit the PHI to the front of endMBB.
20474 BuildMI(*endMBB, endMBB->begin(), DL,
20475 TII->get(X86::PHI), DestReg)
20476 .addReg(OffsetDestReg).addMBB(offsetMBB)
20477 .addReg(OverflowDestReg).addMBB(overflowMBB);
20480 // Erase the pseudo instruction
20481 MI->eraseFromParent();
20486 MachineBasicBlock *
20487 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20489 MachineBasicBlock *MBB) const {
20490 // Emit code to save XMM registers to the stack. The ABI says that the
20491 // number of registers to save is given in %al, so it's theoretically
20492 // possible to do an indirect jump trick to avoid saving all of them,
20493 // however this code takes a simpler approach and just executes all
20494 // of the stores if %al is non-zero. It's less code, and it's probably
20495 // easier on the hardware branch predictor, and stores aren't all that
20496 // expensive anyway.
20498 // Create the new basic blocks. One block contains all the XMM stores,
20499 // and one block is the final destination regardless of whether any
20500 // stores were performed.
20501 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20502 MachineFunction *F = MBB->getParent();
20503 MachineFunction::iterator MBBIter = MBB;
20505 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20506 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20507 F->insert(MBBIter, XMMSaveMBB);
20508 F->insert(MBBIter, EndMBB);
20510 // Transfer the remainder of MBB and its successor edges to EndMBB.
20511 EndMBB->splice(EndMBB->begin(), MBB,
20512 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20513 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20515 // The original block will now fall through to the XMM save block.
20516 MBB->addSuccessor(XMMSaveMBB);
20517 // The XMMSaveMBB will fall through to the end block.
20518 XMMSaveMBB->addSuccessor(EndMBB);
20520 // Now add the instructions.
20521 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20522 DebugLoc DL = MI->getDebugLoc();
20524 unsigned CountReg = MI->getOperand(0).getReg();
20525 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20526 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20528 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20529 // If %al is 0, branch around the XMM save block.
20530 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20531 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20532 MBB->addSuccessor(EndMBB);
20535 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20536 // that was just emitted, but clearly shouldn't be "saved".
20537 assert((MI->getNumOperands() <= 3 ||
20538 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20539 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20540 && "Expected last argument to be EFLAGS");
20541 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20542 // In the XMM save block, save all the XMM argument registers.
20543 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20544 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20545 MachineMemOperand *MMO = F->getMachineMemOperand(
20546 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20547 MachineMemOperand::MOStore,
20548 /*Size=*/16, /*Align=*/16);
20549 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20550 .addFrameIndex(RegSaveFrameIndex)
20551 .addImm(/*Scale=*/1)
20552 .addReg(/*IndexReg=*/0)
20553 .addImm(/*Disp=*/Offset)
20554 .addReg(/*Segment=*/0)
20555 .addReg(MI->getOperand(i).getReg())
20556 .addMemOperand(MMO);
20559 MI->eraseFromParent(); // The pseudo instruction is gone now.
20564 // The EFLAGS operand of SelectItr might be missing a kill marker
20565 // because there were multiple uses of EFLAGS, and ISel didn't know
20566 // which to mark. Figure out whether SelectItr should have had a
20567 // kill marker, and set it if it should. Returns the correct kill
20569 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20570 MachineBasicBlock* BB,
20571 const TargetRegisterInfo* TRI) {
20572 // Scan forward through BB for a use/def of EFLAGS.
20573 MachineBasicBlock::iterator miI(std::next(SelectItr));
20574 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20575 const MachineInstr& mi = *miI;
20576 if (mi.readsRegister(X86::EFLAGS))
20578 if (mi.definesRegister(X86::EFLAGS))
20579 break; // Should have kill-flag - update below.
20582 // If we hit the end of the block, check whether EFLAGS is live into a
20584 if (miI == BB->end()) {
20585 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20586 sEnd = BB->succ_end();
20587 sItr != sEnd; ++sItr) {
20588 MachineBasicBlock* succ = *sItr;
20589 if (succ->isLiveIn(X86::EFLAGS))
20594 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20595 // out. SelectMI should have a kill flag on EFLAGS.
20596 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20600 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20601 // together with other CMOV pseudo-opcodes into a single basic-block with
20602 // conditional jump around it.
20603 static bool isCMOVPseudo(MachineInstr *MI) {
20604 switch (MI->getOpcode()) {
20605 case X86::CMOV_FR32:
20606 case X86::CMOV_FR64:
20607 case X86::CMOV_GR8:
20608 case X86::CMOV_GR16:
20609 case X86::CMOV_GR32:
20610 case X86::CMOV_RFP32:
20611 case X86::CMOV_RFP64:
20612 case X86::CMOV_RFP80:
20613 case X86::CMOV_V2F64:
20614 case X86::CMOV_V2I64:
20615 case X86::CMOV_V4F32:
20616 case X86::CMOV_V4F64:
20617 case X86::CMOV_V4I64:
20618 case X86::CMOV_V16F32:
20619 case X86::CMOV_V8F32:
20620 case X86::CMOV_V8F64:
20621 case X86::CMOV_V8I64:
20622 case X86::CMOV_V8I1:
20623 case X86::CMOV_V16I1:
20624 case X86::CMOV_V32I1:
20625 case X86::CMOV_V64I1:
20633 MachineBasicBlock *
20634 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20635 MachineBasicBlock *BB) const {
20636 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20637 DebugLoc DL = MI->getDebugLoc();
20639 // To "insert" a SELECT_CC instruction, we actually have to insert the
20640 // diamond control-flow pattern. The incoming instruction knows the
20641 // destination vreg to set, the condition code register to branch on, the
20642 // true/false values to select between, and a branch opcode to use.
20643 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20644 MachineFunction::iterator It = BB;
20650 // cmpTY ccX, r1, r2
20652 // fallthrough --> copy0MBB
20653 MachineBasicBlock *thisMBB = BB;
20654 MachineFunction *F = BB->getParent();
20656 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20657 // as described above, by inserting a BB, and then making a PHI at the join
20658 // point to select the true and false operands of the CMOV in the PHI.
20660 // The code also handles two different cases of multiple CMOV opcodes
20664 // In this case, there are multiple CMOVs in a row, all which are based on
20665 // the same condition setting (or the exact opposite condition setting).
20666 // In this case we can lower all the CMOVs using a single inserted BB, and
20667 // then make a number of PHIs at the join point to model the CMOVs. The only
20668 // trickiness here, is that in a case like:
20670 // t2 = CMOV cond1 t1, f1
20671 // t3 = CMOV cond1 t2, f2
20673 // when rewriting this into PHIs, we have to perform some renaming on the
20674 // temps since you cannot have a PHI operand refer to a PHI result earlier
20675 // in the same block. The "simple" but wrong lowering would be:
20677 // t2 = PHI t1(BB1), f1(BB2)
20678 // t3 = PHI t2(BB1), f2(BB2)
20680 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20681 // renaming is to note that on the path through BB1, t2 is really just a
20682 // copy of t1, and do that renaming, properly generating:
20684 // t2 = PHI t1(BB1), f1(BB2)
20685 // t3 = PHI t1(BB1), f2(BB2)
20687 // Case 2, we lower cascaded CMOVs such as
20689 // (CMOV (CMOV F, T, cc1), T, cc2)
20691 // to two successives branches. For that, we look for another CMOV as the
20692 // following instruction.
20694 // Without this, we would add a PHI between the two jumps, which ends up
20695 // creating a few copies all around. For instance, for
20697 // (sitofp (zext (fcmp une)))
20699 // we would generate:
20701 // ucomiss %xmm1, %xmm0
20702 // movss <1.0f>, %xmm0
20703 // movaps %xmm0, %xmm1
20705 // xorps %xmm1, %xmm1
20708 // movaps %xmm1, %xmm0
20712 // because this custom-inserter would have generated:
20724 // A: X = ...; Y = ...
20726 // C: Z = PHI [X, A], [Y, B]
20728 // E: PHI [X, C], [Z, D]
20730 // If we lower both CMOVs in a single step, we can instead generate:
20742 // A: X = ...; Y = ...
20744 // E: PHI [X, A], [X, C], [Y, D]
20746 // Which, in our sitofp/fcmp example, gives us something like:
20748 // ucomiss %xmm1, %xmm0
20749 // movss <1.0f>, %xmm0
20752 // xorps %xmm0, %xmm0
20756 MachineInstr *CascadedCMOV = nullptr;
20757 MachineInstr *LastCMOV = MI;
20758 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20759 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20760 MachineBasicBlock::iterator NextMIIt =
20761 std::next(MachineBasicBlock::iterator(MI));
20763 // Check for case 1, where there are multiple CMOVs with the same condition
20764 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20765 // number of jumps the most.
20767 if (isCMOVPseudo(MI)) {
20768 // See if we have a string of CMOVS with the same condition.
20769 while (NextMIIt != BB->end() &&
20770 isCMOVPseudo(NextMIIt) &&
20771 (NextMIIt->getOperand(3).getImm() == CC ||
20772 NextMIIt->getOperand(3).getImm() == OppCC)) {
20773 LastCMOV = &*NextMIIt;
20778 // This checks for case 2, but only do this if we didn't already find
20779 // case 1, as indicated by LastCMOV == MI.
20780 if (LastCMOV == MI &&
20781 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20782 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20783 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20784 CascadedCMOV = &*NextMIIt;
20787 MachineBasicBlock *jcc1MBB = nullptr;
20789 // If we have a cascaded CMOV, we lower it to two successive branches to
20790 // the same block. EFLAGS is used by both, so mark it as live in the second.
20791 if (CascadedCMOV) {
20792 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20793 F->insert(It, jcc1MBB);
20794 jcc1MBB->addLiveIn(X86::EFLAGS);
20797 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20798 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20799 F->insert(It, copy0MBB);
20800 F->insert(It, sinkMBB);
20802 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20803 // live into the sink and copy blocks.
20804 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20806 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20807 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20808 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20809 copy0MBB->addLiveIn(X86::EFLAGS);
20810 sinkMBB->addLiveIn(X86::EFLAGS);
20813 // Transfer the remainder of BB and its successor edges to sinkMBB.
20814 sinkMBB->splice(sinkMBB->begin(), BB,
20815 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20816 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20818 // Add the true and fallthrough blocks as its successors.
20819 if (CascadedCMOV) {
20820 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20821 BB->addSuccessor(jcc1MBB);
20823 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20824 // jump to the sinkMBB.
20825 jcc1MBB->addSuccessor(copy0MBB);
20826 jcc1MBB->addSuccessor(sinkMBB);
20828 BB->addSuccessor(copy0MBB);
20831 // The true block target of the first (or only) branch is always sinkMBB.
20832 BB->addSuccessor(sinkMBB);
20834 // Create the conditional branch instruction.
20835 unsigned Opc = X86::GetCondBranchFromCond(CC);
20836 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20838 if (CascadedCMOV) {
20839 unsigned Opc2 = X86::GetCondBranchFromCond(
20840 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20841 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20845 // %FalseValue = ...
20846 // # fallthrough to sinkMBB
20847 copy0MBB->addSuccessor(sinkMBB);
20850 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20852 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20853 MachineBasicBlock::iterator MIItEnd =
20854 std::next(MachineBasicBlock::iterator(LastCMOV));
20855 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20856 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20857 MachineInstrBuilder MIB;
20859 // As we are creating the PHIs, we have to be careful if there is more than
20860 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20861 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20862 // That also means that PHI construction must work forward from earlier to
20863 // later, and that the code must maintain a mapping from earlier PHI's
20864 // destination registers, and the registers that went into the PHI.
20866 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20867 unsigned DestReg = MIIt->getOperand(0).getReg();
20868 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20869 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20871 // If this CMOV we are generating is the opposite condition from
20872 // the jump we generated, then we have to swap the operands for the
20873 // PHI that is going to be generated.
20874 if (MIIt->getOperand(3).getImm() == OppCC)
20875 std::swap(Op1Reg, Op2Reg);
20877 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20878 Op1Reg = RegRewriteTable[Op1Reg].first;
20880 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20881 Op2Reg = RegRewriteTable[Op2Reg].second;
20883 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20884 TII->get(X86::PHI), DestReg)
20885 .addReg(Op1Reg).addMBB(copy0MBB)
20886 .addReg(Op2Reg).addMBB(thisMBB);
20888 // Add this PHI to the rewrite table.
20889 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20892 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20893 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20894 if (CascadedCMOV) {
20895 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20896 // Copy the PHI result to the register defined by the second CMOV.
20897 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20898 DL, TII->get(TargetOpcode::COPY),
20899 CascadedCMOV->getOperand(0).getReg())
20900 .addReg(MI->getOperand(0).getReg());
20901 CascadedCMOV->eraseFromParent();
20904 // Now remove the CMOV(s).
20905 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20906 (MIIt++)->eraseFromParent();
20911 MachineBasicBlock *
20912 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
20913 MachineBasicBlock *BB) const {
20914 // Combine the following atomic floating-point modification pattern:
20915 // a.store(reg OP a.load(acquire), release)
20916 // Transform them into:
20917 // OPss (%gpr), %xmm
20918 // movss %xmm, (%gpr)
20919 // Or sd equivalent for 64-bit operations.
20921 switch (MI->getOpcode()) {
20922 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
20923 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
20924 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
20926 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20927 DebugLoc DL = MI->getDebugLoc();
20928 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
20929 unsigned MSrc = MI->getOperand(0).getReg();
20930 unsigned VSrc = MI->getOperand(5).getReg();
20931 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
20932 .addReg(/*Base=*/MSrc)
20933 .addImm(/*Scale=*/1)
20934 .addReg(/*Index=*/0)
20937 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
20938 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
20940 .addReg(/*Base=*/MSrc)
20941 .addImm(/*Scale=*/1)
20942 .addReg(/*Index=*/0)
20943 .addImm(/*Disp=*/0)
20944 .addReg(/*Segment=*/0);
20945 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
20946 MI->eraseFromParent(); // The pseudo instruction is gone now.
20950 MachineBasicBlock *
20951 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20952 MachineBasicBlock *BB) const {
20953 MachineFunction *MF = BB->getParent();
20954 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20955 DebugLoc DL = MI->getDebugLoc();
20956 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20958 assert(MF->shouldSplitStack());
20960 const bool Is64Bit = Subtarget->is64Bit();
20961 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20963 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20964 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20967 // ... [Till the alloca]
20968 // If stacklet is not large enough, jump to mallocMBB
20971 // Allocate by subtracting from RSP
20972 // Jump to continueMBB
20975 // Allocate by call to runtime
20979 // [rest of original BB]
20982 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20983 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20984 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20986 MachineRegisterInfo &MRI = MF->getRegInfo();
20987 const TargetRegisterClass *AddrRegClass =
20988 getRegClassFor(getPointerTy(MF->getDataLayout()));
20990 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20991 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20992 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20993 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20994 sizeVReg = MI->getOperand(1).getReg(),
20995 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20997 MachineFunction::iterator MBBIter = BB;
21000 MF->insert(MBBIter, bumpMBB);
21001 MF->insert(MBBIter, mallocMBB);
21002 MF->insert(MBBIter, continueMBB);
21004 continueMBB->splice(continueMBB->begin(), BB,
21005 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21006 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21008 // Add code to the main basic block to check if the stack limit has been hit,
21009 // and if so, jump to mallocMBB otherwise to bumpMBB.
21010 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21011 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21012 .addReg(tmpSPVReg).addReg(sizeVReg);
21013 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21014 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21015 .addReg(SPLimitVReg);
21016 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21018 // bumpMBB simply decreases the stack pointer, since we know the current
21019 // stacklet has enough space.
21020 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21021 .addReg(SPLimitVReg);
21022 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21023 .addReg(SPLimitVReg);
21024 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21026 // Calls into a routine in libgcc to allocate more space from the heap.
21027 const uint32_t *RegMask =
21028 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21030 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21032 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21033 .addExternalSymbol("__morestack_allocate_stack_space")
21034 .addRegMask(RegMask)
21035 .addReg(X86::RDI, RegState::Implicit)
21036 .addReg(X86::RAX, RegState::ImplicitDefine);
21037 } else if (Is64Bit) {
21038 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21040 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21041 .addExternalSymbol("__morestack_allocate_stack_space")
21042 .addRegMask(RegMask)
21043 .addReg(X86::EDI, RegState::Implicit)
21044 .addReg(X86::EAX, RegState::ImplicitDefine);
21046 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21048 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21049 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21050 .addExternalSymbol("__morestack_allocate_stack_space")
21051 .addRegMask(RegMask)
21052 .addReg(X86::EAX, RegState::ImplicitDefine);
21056 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21059 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21060 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21061 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21063 // Set up the CFG correctly.
21064 BB->addSuccessor(bumpMBB);
21065 BB->addSuccessor(mallocMBB);
21066 mallocMBB->addSuccessor(continueMBB);
21067 bumpMBB->addSuccessor(continueMBB);
21069 // Take care of the PHI nodes.
21070 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21071 MI->getOperand(0).getReg())
21072 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21073 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21075 // Delete the original pseudo instruction.
21076 MI->eraseFromParent();
21079 return continueMBB;
21082 MachineBasicBlock *
21083 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21084 MachineBasicBlock *BB) const {
21085 DebugLoc DL = MI->getDebugLoc();
21087 assert(!Subtarget->isTargetMachO());
21089 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21092 MI->eraseFromParent(); // The pseudo instruction is gone now.
21096 MachineBasicBlock *
21097 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21098 MachineBasicBlock *BB) const {
21099 // This is pretty easy. We're taking the value that we received from
21100 // our load from the relocation, sticking it in either RDI (x86-64)
21101 // or EAX and doing an indirect call. The return value will then
21102 // be in the normal return register.
21103 MachineFunction *F = BB->getParent();
21104 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21105 DebugLoc DL = MI->getDebugLoc();
21107 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21108 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21110 // Get a register mask for the lowered call.
21111 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21112 // proper register mask.
21113 const uint32_t *RegMask =
21114 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21115 if (Subtarget->is64Bit()) {
21116 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21117 TII->get(X86::MOV64rm), X86::RDI)
21119 .addImm(0).addReg(0)
21120 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21121 MI->getOperand(3).getTargetFlags())
21123 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21124 addDirectMem(MIB, X86::RDI);
21125 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21126 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21127 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21128 TII->get(X86::MOV32rm), X86::EAX)
21130 .addImm(0).addReg(0)
21131 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21132 MI->getOperand(3).getTargetFlags())
21134 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21135 addDirectMem(MIB, X86::EAX);
21136 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21138 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21139 TII->get(X86::MOV32rm), X86::EAX)
21140 .addReg(TII->getGlobalBaseReg(F))
21141 .addImm(0).addReg(0)
21142 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21143 MI->getOperand(3).getTargetFlags())
21145 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21146 addDirectMem(MIB, X86::EAX);
21147 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21150 MI->eraseFromParent(); // The pseudo instruction is gone now.
21154 MachineBasicBlock *
21155 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21156 MachineBasicBlock *MBB) const {
21157 DebugLoc DL = MI->getDebugLoc();
21158 MachineFunction *MF = MBB->getParent();
21159 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21160 MachineRegisterInfo &MRI = MF->getRegInfo();
21162 const BasicBlock *BB = MBB->getBasicBlock();
21163 MachineFunction::iterator I = MBB;
21166 // Memory Reference
21167 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21168 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21171 unsigned MemOpndSlot = 0;
21173 unsigned CurOp = 0;
21175 DstReg = MI->getOperand(CurOp++).getReg();
21176 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21177 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21178 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21179 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21181 MemOpndSlot = CurOp;
21183 MVT PVT = getPointerTy(MF->getDataLayout());
21184 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21185 "Invalid Pointer Size!");
21187 // For v = setjmp(buf), we generate
21190 // buf[LabelOffset] = restoreMBB
21191 // SjLjSetup restoreMBB
21197 // v = phi(main, restore)
21200 // if base pointer being used, load it from frame
21203 MachineBasicBlock *thisMBB = MBB;
21204 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21205 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21206 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21207 MF->insert(I, mainMBB);
21208 MF->insert(I, sinkMBB);
21209 MF->push_back(restoreMBB);
21211 MachineInstrBuilder MIB;
21213 // Transfer the remainder of BB and its successor edges to sinkMBB.
21214 sinkMBB->splice(sinkMBB->begin(), MBB,
21215 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21216 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21219 unsigned PtrStoreOpc = 0;
21220 unsigned LabelReg = 0;
21221 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21222 Reloc::Model RM = MF->getTarget().getRelocationModel();
21223 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21224 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21226 // Prepare IP either in reg or imm.
21227 if (!UseImmLabel) {
21228 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21229 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21230 LabelReg = MRI.createVirtualRegister(PtrRC);
21231 if (Subtarget->is64Bit()) {
21232 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21236 .addMBB(restoreMBB)
21239 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21240 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21241 .addReg(XII->getGlobalBaseReg(MF))
21244 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21248 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21250 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21251 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21252 if (i == X86::AddrDisp)
21253 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21255 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21258 MIB.addReg(LabelReg);
21260 MIB.addMBB(restoreMBB);
21261 MIB.setMemRefs(MMOBegin, MMOEnd);
21263 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21264 .addMBB(restoreMBB);
21266 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21267 MIB.addRegMask(RegInfo->getNoPreservedMask());
21268 thisMBB->addSuccessor(mainMBB);
21269 thisMBB->addSuccessor(restoreMBB);
21273 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21274 mainMBB->addSuccessor(sinkMBB);
21277 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21278 TII->get(X86::PHI), DstReg)
21279 .addReg(mainDstReg).addMBB(mainMBB)
21280 .addReg(restoreDstReg).addMBB(restoreMBB);
21283 if (RegInfo->hasBasePointer(*MF)) {
21284 const bool Uses64BitFramePtr =
21285 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21286 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21287 X86FI->setRestoreBasePointer(MF);
21288 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21289 unsigned BasePtr = RegInfo->getBaseRegister();
21290 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21291 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21292 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21293 .setMIFlag(MachineInstr::FrameSetup);
21295 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21296 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21297 restoreMBB->addSuccessor(sinkMBB);
21299 MI->eraseFromParent();
21303 MachineBasicBlock *
21304 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21305 MachineBasicBlock *MBB) const {
21306 DebugLoc DL = MI->getDebugLoc();
21307 MachineFunction *MF = MBB->getParent();
21308 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21309 MachineRegisterInfo &MRI = MF->getRegInfo();
21311 // Memory Reference
21312 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21313 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21315 MVT PVT = getPointerTy(MF->getDataLayout());
21316 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21317 "Invalid Pointer Size!");
21319 const TargetRegisterClass *RC =
21320 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21321 unsigned Tmp = MRI.createVirtualRegister(RC);
21322 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21323 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21324 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21325 unsigned SP = RegInfo->getStackRegister();
21327 MachineInstrBuilder MIB;
21329 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21330 const int64_t SPOffset = 2 * PVT.getStoreSize();
21332 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21333 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21336 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21337 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21338 MIB.addOperand(MI->getOperand(i));
21339 MIB.setMemRefs(MMOBegin, MMOEnd);
21341 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21342 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21343 if (i == X86::AddrDisp)
21344 MIB.addDisp(MI->getOperand(i), LabelOffset);
21346 MIB.addOperand(MI->getOperand(i));
21348 MIB.setMemRefs(MMOBegin, MMOEnd);
21350 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21351 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21352 if (i == X86::AddrDisp)
21353 MIB.addDisp(MI->getOperand(i), SPOffset);
21355 MIB.addOperand(MI->getOperand(i));
21357 MIB.setMemRefs(MMOBegin, MMOEnd);
21359 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21361 MI->eraseFromParent();
21365 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21366 // accumulator loops. Writing back to the accumulator allows the coalescer
21367 // to remove extra copies in the loop.
21368 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21369 MachineBasicBlock *
21370 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21371 MachineBasicBlock *MBB) const {
21372 MachineOperand &AddendOp = MI->getOperand(3);
21374 // Bail out early if the addend isn't a register - we can't switch these.
21375 if (!AddendOp.isReg())
21378 MachineFunction &MF = *MBB->getParent();
21379 MachineRegisterInfo &MRI = MF.getRegInfo();
21381 // Check whether the addend is defined by a PHI:
21382 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21383 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21384 if (!AddendDef.isPHI())
21387 // Look for the following pattern:
21389 // %addend = phi [%entry, 0], [%loop, %result]
21391 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21395 // %addend = phi [%entry, 0], [%loop, %result]
21397 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21399 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21400 assert(AddendDef.getOperand(i).isReg());
21401 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21402 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21403 if (&PHISrcInst == MI) {
21404 // Found a matching instruction.
21405 unsigned NewFMAOpc = 0;
21406 switch (MI->getOpcode()) {
21407 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21408 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21409 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21410 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21411 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21412 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21413 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21414 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21415 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21416 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21417 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21418 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21419 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21420 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21421 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21422 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21423 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21424 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21425 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21426 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21428 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21429 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21430 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21431 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21432 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21433 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21434 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21435 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21436 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21437 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21438 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21439 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21440 default: llvm_unreachable("Unrecognized FMA variant.");
21443 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21444 MachineInstrBuilder MIB =
21445 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21446 .addOperand(MI->getOperand(0))
21447 .addOperand(MI->getOperand(3))
21448 .addOperand(MI->getOperand(2))
21449 .addOperand(MI->getOperand(1));
21450 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21451 MI->eraseFromParent();
21458 MachineBasicBlock *
21459 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21460 MachineBasicBlock *BB) const {
21461 switch (MI->getOpcode()) {
21462 default: llvm_unreachable("Unexpected instr type to insert");
21463 case X86::TAILJMPd64:
21464 case X86::TAILJMPr64:
21465 case X86::TAILJMPm64:
21466 case X86::TAILJMPd64_REX:
21467 case X86::TAILJMPr64_REX:
21468 case X86::TAILJMPm64_REX:
21469 llvm_unreachable("TAILJMP64 would not be touched here.");
21470 case X86::TCRETURNdi64:
21471 case X86::TCRETURNri64:
21472 case X86::TCRETURNmi64:
21474 case X86::WIN_ALLOCA:
21475 return EmitLoweredWinAlloca(MI, BB);
21476 case X86::SEG_ALLOCA_32:
21477 case X86::SEG_ALLOCA_64:
21478 return EmitLoweredSegAlloca(MI, BB);
21479 case X86::TLSCall_32:
21480 case X86::TLSCall_64:
21481 return EmitLoweredTLSCall(MI, BB);
21482 case X86::CMOV_FR32:
21483 case X86::CMOV_FR64:
21484 case X86::CMOV_GR8:
21485 case X86::CMOV_GR16:
21486 case X86::CMOV_GR32:
21487 case X86::CMOV_RFP32:
21488 case X86::CMOV_RFP64:
21489 case X86::CMOV_RFP80:
21490 case X86::CMOV_V2F64:
21491 case X86::CMOV_V2I64:
21492 case X86::CMOV_V4F32:
21493 case X86::CMOV_V4F64:
21494 case X86::CMOV_V4I64:
21495 case X86::CMOV_V16F32:
21496 case X86::CMOV_V8F32:
21497 case X86::CMOV_V8F64:
21498 case X86::CMOV_V8I64:
21499 case X86::CMOV_V8I1:
21500 case X86::CMOV_V16I1:
21501 case X86::CMOV_V32I1:
21502 case X86::CMOV_V64I1:
21503 return EmitLoweredSelect(MI, BB);
21505 case X86::RELEASE_FADD32mr:
21506 case X86::RELEASE_FADD64mr:
21507 return EmitLoweredAtomicFP(MI, BB);
21509 case X86::FP32_TO_INT16_IN_MEM:
21510 case X86::FP32_TO_INT32_IN_MEM:
21511 case X86::FP32_TO_INT64_IN_MEM:
21512 case X86::FP64_TO_INT16_IN_MEM:
21513 case X86::FP64_TO_INT32_IN_MEM:
21514 case X86::FP64_TO_INT64_IN_MEM:
21515 case X86::FP80_TO_INT16_IN_MEM:
21516 case X86::FP80_TO_INT32_IN_MEM:
21517 case X86::FP80_TO_INT64_IN_MEM: {
21518 MachineFunction *F = BB->getParent();
21519 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21520 DebugLoc DL = MI->getDebugLoc();
21522 // Change the floating point control register to use "round towards zero"
21523 // mode when truncating to an integer value.
21524 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21525 addFrameReference(BuildMI(*BB, MI, DL,
21526 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21528 // Load the old value of the high byte of the control word...
21530 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21531 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21534 // Set the high part to be round to zero...
21535 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21538 // Reload the modified control word now...
21539 addFrameReference(BuildMI(*BB, MI, DL,
21540 TII->get(X86::FLDCW16m)), CWFrameIdx);
21542 // Restore the memory image of control word to original value
21543 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21546 // Get the X86 opcode to use.
21548 switch (MI->getOpcode()) {
21549 default: llvm_unreachable("illegal opcode!");
21550 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21551 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21552 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21553 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21554 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21555 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21556 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21557 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21558 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21562 MachineOperand &Op = MI->getOperand(0);
21564 AM.BaseType = X86AddressMode::RegBase;
21565 AM.Base.Reg = Op.getReg();
21567 AM.BaseType = X86AddressMode::FrameIndexBase;
21568 AM.Base.FrameIndex = Op.getIndex();
21570 Op = MI->getOperand(1);
21572 AM.Scale = Op.getImm();
21573 Op = MI->getOperand(2);
21575 AM.IndexReg = Op.getImm();
21576 Op = MI->getOperand(3);
21577 if (Op.isGlobal()) {
21578 AM.GV = Op.getGlobal();
21580 AM.Disp = Op.getImm();
21582 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21583 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21585 // Reload the original control word now.
21586 addFrameReference(BuildMI(*BB, MI, DL,
21587 TII->get(X86::FLDCW16m)), CWFrameIdx);
21589 MI->eraseFromParent(); // The pseudo instruction is gone now.
21592 // String/text processing lowering.
21593 case X86::PCMPISTRM128REG:
21594 case X86::VPCMPISTRM128REG:
21595 case X86::PCMPISTRM128MEM:
21596 case X86::VPCMPISTRM128MEM:
21597 case X86::PCMPESTRM128REG:
21598 case X86::VPCMPESTRM128REG:
21599 case X86::PCMPESTRM128MEM:
21600 case X86::VPCMPESTRM128MEM:
21601 assert(Subtarget->hasSSE42() &&
21602 "Target must have SSE4.2 or AVX features enabled");
21603 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21605 // String/text processing lowering.
21606 case X86::PCMPISTRIREG:
21607 case X86::VPCMPISTRIREG:
21608 case X86::PCMPISTRIMEM:
21609 case X86::VPCMPISTRIMEM:
21610 case X86::PCMPESTRIREG:
21611 case X86::VPCMPESTRIREG:
21612 case X86::PCMPESTRIMEM:
21613 case X86::VPCMPESTRIMEM:
21614 assert(Subtarget->hasSSE42() &&
21615 "Target must have SSE4.2 or AVX features enabled");
21616 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21618 // Thread synchronization.
21620 return EmitMonitor(MI, BB, Subtarget);
21624 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21626 case X86::VASTART_SAVE_XMM_REGS:
21627 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21629 case X86::VAARG_64:
21630 return EmitVAARG64WithCustomInserter(MI, BB);
21632 case X86::EH_SjLj_SetJmp32:
21633 case X86::EH_SjLj_SetJmp64:
21634 return emitEHSjLjSetJmp(MI, BB);
21636 case X86::EH_SjLj_LongJmp32:
21637 case X86::EH_SjLj_LongJmp64:
21638 return emitEHSjLjLongJmp(MI, BB);
21640 case TargetOpcode::STATEPOINT:
21641 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21642 // this point in the process. We diverge later.
21643 return emitPatchPoint(MI, BB);
21645 case TargetOpcode::STACKMAP:
21646 case TargetOpcode::PATCHPOINT:
21647 return emitPatchPoint(MI, BB);
21649 case X86::VFMADDPDr213r:
21650 case X86::VFMADDPSr213r:
21651 case X86::VFMADDSDr213r:
21652 case X86::VFMADDSSr213r:
21653 case X86::VFMSUBPDr213r:
21654 case X86::VFMSUBPSr213r:
21655 case X86::VFMSUBSDr213r:
21656 case X86::VFMSUBSSr213r:
21657 case X86::VFNMADDPDr213r:
21658 case X86::VFNMADDPSr213r:
21659 case X86::VFNMADDSDr213r:
21660 case X86::VFNMADDSSr213r:
21661 case X86::VFNMSUBPDr213r:
21662 case X86::VFNMSUBPSr213r:
21663 case X86::VFNMSUBSDr213r:
21664 case X86::VFNMSUBSSr213r:
21665 case X86::VFMADDSUBPDr213r:
21666 case X86::VFMADDSUBPSr213r:
21667 case X86::VFMSUBADDPDr213r:
21668 case X86::VFMSUBADDPSr213r:
21669 case X86::VFMADDPDr213rY:
21670 case X86::VFMADDPSr213rY:
21671 case X86::VFMSUBPDr213rY:
21672 case X86::VFMSUBPSr213rY:
21673 case X86::VFNMADDPDr213rY:
21674 case X86::VFNMADDPSr213rY:
21675 case X86::VFNMSUBPDr213rY:
21676 case X86::VFNMSUBPSr213rY:
21677 case X86::VFMADDSUBPDr213rY:
21678 case X86::VFMADDSUBPSr213rY:
21679 case X86::VFMSUBADDPDr213rY:
21680 case X86::VFMSUBADDPSr213rY:
21681 return emitFMA3Instr(MI, BB);
21685 //===----------------------------------------------------------------------===//
21686 // X86 Optimization Hooks
21687 //===----------------------------------------------------------------------===//
21689 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21692 const SelectionDAG &DAG,
21693 unsigned Depth) const {
21694 unsigned BitWidth = KnownZero.getBitWidth();
21695 unsigned Opc = Op.getOpcode();
21696 assert((Opc >= ISD::BUILTIN_OP_END ||
21697 Opc == ISD::INTRINSIC_WO_CHAIN ||
21698 Opc == ISD::INTRINSIC_W_CHAIN ||
21699 Opc == ISD::INTRINSIC_VOID) &&
21700 "Should use MaskedValueIsZero if you don't know whether Op"
21701 " is a target node!");
21703 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21717 // These nodes' second result is a boolean.
21718 if (Op.getResNo() == 0)
21721 case X86ISD::SETCC:
21722 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21724 case ISD::INTRINSIC_WO_CHAIN: {
21725 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21726 unsigned NumLoBits = 0;
21729 case Intrinsic::x86_sse_movmsk_ps:
21730 case Intrinsic::x86_avx_movmsk_ps_256:
21731 case Intrinsic::x86_sse2_movmsk_pd:
21732 case Intrinsic::x86_avx_movmsk_pd_256:
21733 case Intrinsic::x86_mmx_pmovmskb:
21734 case Intrinsic::x86_sse2_pmovmskb_128:
21735 case Intrinsic::x86_avx2_pmovmskb: {
21736 // High bits of movmskp{s|d}, pmovmskb are known zero.
21738 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21739 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21740 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21741 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21742 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21743 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21744 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21745 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21747 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21756 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21758 const SelectionDAG &,
21759 unsigned Depth) const {
21760 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21761 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21762 return Op.getValueType().getScalarType().getSizeInBits();
21768 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21769 /// node is a GlobalAddress + offset.
21770 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21771 const GlobalValue* &GA,
21772 int64_t &Offset) const {
21773 if (N->getOpcode() == X86ISD::Wrapper) {
21774 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21775 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21776 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21780 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21783 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21784 /// same as extracting the high 128-bit part of 256-bit vector and then
21785 /// inserting the result into the low part of a new 256-bit vector
21786 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21787 EVT VT = SVOp->getValueType(0);
21788 unsigned NumElems = VT.getVectorNumElements();
21790 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21791 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21792 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21793 SVOp->getMaskElt(j) >= 0)
21799 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21800 /// same as extracting the low 128-bit part of 256-bit vector and then
21801 /// inserting the result into the high part of a new 256-bit vector
21802 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21803 EVT VT = SVOp->getValueType(0);
21804 unsigned NumElems = VT.getVectorNumElements();
21806 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21807 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21808 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21809 SVOp->getMaskElt(j) >= 0)
21815 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21816 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21817 TargetLowering::DAGCombinerInfo &DCI,
21818 const X86Subtarget* Subtarget) {
21820 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21821 SDValue V1 = SVOp->getOperand(0);
21822 SDValue V2 = SVOp->getOperand(1);
21823 EVT VT = SVOp->getValueType(0);
21824 unsigned NumElems = VT.getVectorNumElements();
21826 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21827 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21831 // V UNDEF BUILD_VECTOR UNDEF
21833 // CONCAT_VECTOR CONCAT_VECTOR
21836 // RESULT: V + zero extended
21838 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21839 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21840 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21843 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21846 // To match the shuffle mask, the first half of the mask should
21847 // be exactly the first vector, and all the rest a splat with the
21848 // first element of the second one.
21849 for (unsigned i = 0; i != NumElems/2; ++i)
21850 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21851 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21854 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21855 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21856 if (Ld->hasNUsesOfValue(1, 0)) {
21857 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21858 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21860 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21862 Ld->getPointerInfo(),
21863 Ld->getAlignment(),
21864 false/*isVolatile*/, true/*ReadMem*/,
21865 false/*WriteMem*/);
21867 // Make sure the newly-created LOAD is in the same position as Ld in
21868 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21869 // and update uses of Ld's output chain to use the TokenFactor.
21870 if (Ld->hasAnyUseOfValue(1)) {
21871 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21872 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21873 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21874 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21875 SDValue(ResNode.getNode(), 1));
21878 return DAG.getBitcast(VT, ResNode);
21882 // Emit a zeroed vector and insert the desired subvector on its
21884 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21885 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21886 return DCI.CombineTo(N, InsV);
21889 //===--------------------------------------------------------------------===//
21890 // Combine some shuffles into subvector extracts and inserts:
21893 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21894 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21895 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21896 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21897 return DCI.CombineTo(N, InsV);
21900 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21901 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21902 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21903 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21904 return DCI.CombineTo(N, InsV);
21910 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21913 /// This is the leaf of the recursive combinine below. When we have found some
21914 /// chain of single-use x86 shuffle instructions and accumulated the combined
21915 /// shuffle mask represented by them, this will try to pattern match that mask
21916 /// into either a single instruction if there is a special purpose instruction
21917 /// for this operation, or into a PSHUFB instruction which is a fully general
21918 /// instruction but should only be used to replace chains over a certain depth.
21919 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21920 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21921 TargetLowering::DAGCombinerInfo &DCI,
21922 const X86Subtarget *Subtarget) {
21923 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21925 // Find the operand that enters the chain. Note that multiple uses are OK
21926 // here, we're not going to remove the operand we find.
21927 SDValue Input = Op.getOperand(0);
21928 while (Input.getOpcode() == ISD::BITCAST)
21929 Input = Input.getOperand(0);
21931 MVT VT = Input.getSimpleValueType();
21932 MVT RootVT = Root.getSimpleValueType();
21935 // Just remove no-op shuffle masks.
21936 if (Mask.size() == 1) {
21937 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
21942 // Use the float domain if the operand type is a floating point type.
21943 bool FloatDomain = VT.isFloatingPoint();
21945 // For floating point shuffles, we don't have free copies in the shuffle
21946 // instructions or the ability to load as part of the instruction, so
21947 // canonicalize their shuffles to UNPCK or MOV variants.
21949 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21950 // vectors because it can have a load folded into it that UNPCK cannot. This
21951 // doesn't preclude something switching to the shorter encoding post-RA.
21953 // FIXME: Should teach these routines about AVX vector widths.
21954 if (FloatDomain && VT.getSizeInBits() == 128) {
21955 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
21956 bool Lo = Mask.equals({0, 0});
21959 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21960 // is no slower than UNPCKLPD but has the option to fold the input operand
21961 // into even an unaligned memory load.
21962 if (Lo && Subtarget->hasSSE3()) {
21963 Shuffle = X86ISD::MOVDDUP;
21964 ShuffleVT = MVT::v2f64;
21966 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21967 // than the UNPCK variants.
21968 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21969 ShuffleVT = MVT::v4f32;
21971 if (Depth == 1 && Root->getOpcode() == Shuffle)
21972 return false; // Nothing to do!
21973 Op = DAG.getBitcast(ShuffleVT, Input);
21974 DCI.AddToWorklist(Op.getNode());
21975 if (Shuffle == X86ISD::MOVDDUP)
21976 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21978 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21979 DCI.AddToWorklist(Op.getNode());
21980 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21984 if (Subtarget->hasSSE3() &&
21985 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
21986 bool Lo = Mask.equals({0, 0, 2, 2});
21987 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21988 MVT ShuffleVT = MVT::v4f32;
21989 if (Depth == 1 && Root->getOpcode() == Shuffle)
21990 return false; // Nothing to do!
21991 Op = DAG.getBitcast(ShuffleVT, Input);
21992 DCI.AddToWorklist(Op.getNode());
21993 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21994 DCI.AddToWorklist(Op.getNode());
21995 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
21999 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22000 bool Lo = Mask.equals({0, 0, 1, 1});
22001 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22002 MVT ShuffleVT = MVT::v4f32;
22003 if (Depth == 1 && Root->getOpcode() == Shuffle)
22004 return false; // Nothing to do!
22005 Op = DAG.getBitcast(ShuffleVT, Input);
22006 DCI.AddToWorklist(Op.getNode());
22007 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22008 DCI.AddToWorklist(Op.getNode());
22009 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22015 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22016 // variants as none of these have single-instruction variants that are
22017 // superior to the UNPCK formulation.
22018 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22019 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22020 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22021 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22023 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22024 bool Lo = Mask[0] == 0;
22025 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22026 if (Depth == 1 && Root->getOpcode() == Shuffle)
22027 return false; // Nothing to do!
22029 switch (Mask.size()) {
22031 ShuffleVT = MVT::v8i16;
22034 ShuffleVT = MVT::v16i8;
22037 llvm_unreachable("Impossible mask size!");
22039 Op = DAG.getBitcast(ShuffleVT, Input);
22040 DCI.AddToWorklist(Op.getNode());
22041 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22042 DCI.AddToWorklist(Op.getNode());
22043 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22048 // Don't try to re-form single instruction chains under any circumstances now
22049 // that we've done encoding canonicalization for them.
22053 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22054 // can replace them with a single PSHUFB instruction profitably. Intel's
22055 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22056 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22057 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22058 SmallVector<SDValue, 16> PSHUFBMask;
22059 int NumBytes = VT.getSizeInBits() / 8;
22060 int Ratio = NumBytes / Mask.size();
22061 for (int i = 0; i < NumBytes; ++i) {
22062 if (Mask[i / Ratio] == SM_SentinelUndef) {
22063 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22066 int M = Mask[i / Ratio] != SM_SentinelZero
22067 ? Ratio * Mask[i / Ratio] + i % Ratio
22069 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22071 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22072 Op = DAG.getBitcast(ByteVT, Input);
22073 DCI.AddToWorklist(Op.getNode());
22074 SDValue PSHUFBMaskOp =
22075 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22076 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22077 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22078 DCI.AddToWorklist(Op.getNode());
22079 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22084 // Failed to find any combines.
22088 /// \brief Fully generic combining of x86 shuffle instructions.
22090 /// This should be the last combine run over the x86 shuffle instructions. Once
22091 /// they have been fully optimized, this will recursively consider all chains
22092 /// of single-use shuffle instructions, build a generic model of the cumulative
22093 /// shuffle operation, and check for simpler instructions which implement this
22094 /// operation. We use this primarily for two purposes:
22096 /// 1) Collapse generic shuffles to specialized single instructions when
22097 /// equivalent. In most cases, this is just an encoding size win, but
22098 /// sometimes we will collapse multiple generic shuffles into a single
22099 /// special-purpose shuffle.
22100 /// 2) Look for sequences of shuffle instructions with 3 or more total
22101 /// instructions, and replace them with the slightly more expensive SSSE3
22102 /// PSHUFB instruction if available. We do this as the last combining step
22103 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22104 /// a suitable short sequence of other instructions. The PHUFB will either
22105 /// use a register or have to read from memory and so is slightly (but only
22106 /// slightly) more expensive than the other shuffle instructions.
22108 /// Because this is inherently a quadratic operation (for each shuffle in
22109 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22110 /// This should never be an issue in practice as the shuffle lowering doesn't
22111 /// produce sequences of more than 8 instructions.
22113 /// FIXME: We will currently miss some cases where the redundant shuffling
22114 /// would simplify under the threshold for PSHUFB formation because of
22115 /// combine-ordering. To fix this, we should do the redundant instruction
22116 /// combining in this recursive walk.
22117 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22118 ArrayRef<int> RootMask,
22119 int Depth, bool HasPSHUFB,
22121 TargetLowering::DAGCombinerInfo &DCI,
22122 const X86Subtarget *Subtarget) {
22123 // Bound the depth of our recursive combine because this is ultimately
22124 // quadratic in nature.
22128 // Directly rip through bitcasts to find the underlying operand.
22129 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22130 Op = Op.getOperand(0);
22132 MVT VT = Op.getSimpleValueType();
22133 if (!VT.isVector())
22134 return false; // Bail if we hit a non-vector.
22136 assert(Root.getSimpleValueType().isVector() &&
22137 "Shuffles operate on vector types!");
22138 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22139 "Can only combine shuffles of the same vector register size.");
22141 if (!isTargetShuffle(Op.getOpcode()))
22143 SmallVector<int, 16> OpMask;
22145 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22146 // We only can combine unary shuffles which we can decode the mask for.
22147 if (!HaveMask || !IsUnary)
22150 assert(VT.getVectorNumElements() == OpMask.size() &&
22151 "Different mask size from vector size!");
22152 assert(((RootMask.size() > OpMask.size() &&
22153 RootMask.size() % OpMask.size() == 0) ||
22154 (OpMask.size() > RootMask.size() &&
22155 OpMask.size() % RootMask.size() == 0) ||
22156 OpMask.size() == RootMask.size()) &&
22157 "The smaller number of elements must divide the larger.");
22158 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22159 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22160 assert(((RootRatio == 1 && OpRatio == 1) ||
22161 (RootRatio == 1) != (OpRatio == 1)) &&
22162 "Must not have a ratio for both incoming and op masks!");
22164 SmallVector<int, 16> Mask;
22165 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22167 // Merge this shuffle operation's mask into our accumulated mask. Note that
22168 // this shuffle's mask will be the first applied to the input, followed by the
22169 // root mask to get us all the way to the root value arrangement. The reason
22170 // for this order is that we are recursing up the operation chain.
22171 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22172 int RootIdx = i / RootRatio;
22173 if (RootMask[RootIdx] < 0) {
22174 // This is a zero or undef lane, we're done.
22175 Mask.push_back(RootMask[RootIdx]);
22179 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22180 int OpIdx = RootMaskedIdx / OpRatio;
22181 if (OpMask[OpIdx] < 0) {
22182 // The incoming lanes are zero or undef, it doesn't matter which ones we
22184 Mask.push_back(OpMask[OpIdx]);
22188 // Ok, we have non-zero lanes, map them through.
22189 Mask.push_back(OpMask[OpIdx] * OpRatio +
22190 RootMaskedIdx % OpRatio);
22193 // See if we can recurse into the operand to combine more things.
22194 switch (Op.getOpcode()) {
22195 case X86ISD::PSHUFB:
22197 case X86ISD::PSHUFD:
22198 case X86ISD::PSHUFHW:
22199 case X86ISD::PSHUFLW:
22200 if (Op.getOperand(0).hasOneUse() &&
22201 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22202 HasPSHUFB, DAG, DCI, Subtarget))
22206 case X86ISD::UNPCKL:
22207 case X86ISD::UNPCKH:
22208 assert(Op.getOperand(0) == Op.getOperand(1) &&
22209 "We only combine unary shuffles!");
22210 // We can't check for single use, we have to check that this shuffle is the
22212 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22213 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22214 HasPSHUFB, DAG, DCI, Subtarget))
22219 // Minor canonicalization of the accumulated shuffle mask to make it easier
22220 // to match below. All this does is detect masks with squential pairs of
22221 // elements, and shrink them to the half-width mask. It does this in a loop
22222 // so it will reduce the size of the mask to the minimal width mask which
22223 // performs an equivalent shuffle.
22224 SmallVector<int, 16> WidenedMask;
22225 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22226 Mask = std::move(WidenedMask);
22227 WidenedMask.clear();
22230 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22234 /// \brief Get the PSHUF-style mask from PSHUF node.
22236 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22237 /// PSHUF-style masks that can be reused with such instructions.
22238 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22239 MVT VT = N.getSimpleValueType();
22240 SmallVector<int, 4> Mask;
22242 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22246 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22247 // matter. Check that the upper masks are repeats and remove them.
22248 if (VT.getSizeInBits() > 128) {
22249 int LaneElts = 128 / VT.getScalarSizeInBits();
22251 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22252 for (int j = 0; j < LaneElts; ++j)
22253 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22254 "Mask doesn't repeat in high 128-bit lanes!");
22256 Mask.resize(LaneElts);
22259 switch (N.getOpcode()) {
22260 case X86ISD::PSHUFD:
22262 case X86ISD::PSHUFLW:
22265 case X86ISD::PSHUFHW:
22266 Mask.erase(Mask.begin(), Mask.begin() + 4);
22267 for (int &M : Mask)
22271 llvm_unreachable("No valid shuffle instruction found!");
22275 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22277 /// We walk up the chain and look for a combinable shuffle, skipping over
22278 /// shuffles that we could hoist this shuffle's transformation past without
22279 /// altering anything.
22281 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22283 TargetLowering::DAGCombinerInfo &DCI) {
22284 assert(N.getOpcode() == X86ISD::PSHUFD &&
22285 "Called with something other than an x86 128-bit half shuffle!");
22288 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22289 // of the shuffles in the chain so that we can form a fresh chain to replace
22291 SmallVector<SDValue, 8> Chain;
22292 SDValue V = N.getOperand(0);
22293 for (; V.hasOneUse(); V = V.getOperand(0)) {
22294 switch (V.getOpcode()) {
22296 return SDValue(); // Nothing combined!
22299 // Skip bitcasts as we always know the type for the target specific
22303 case X86ISD::PSHUFD:
22304 // Found another dword shuffle.
22307 case X86ISD::PSHUFLW:
22308 // Check that the low words (being shuffled) are the identity in the
22309 // dword shuffle, and the high words are self-contained.
22310 if (Mask[0] != 0 || Mask[1] != 1 ||
22311 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22314 Chain.push_back(V);
22317 case X86ISD::PSHUFHW:
22318 // Check that the high words (being shuffled) are the identity in the
22319 // dword shuffle, and the low words are self-contained.
22320 if (Mask[2] != 2 || Mask[3] != 3 ||
22321 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22324 Chain.push_back(V);
22327 case X86ISD::UNPCKL:
22328 case X86ISD::UNPCKH:
22329 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22330 // shuffle into a preceding word shuffle.
22331 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22332 V.getSimpleValueType().getScalarType() != MVT::i16)
22335 // Search for a half-shuffle which we can combine with.
22336 unsigned CombineOp =
22337 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22338 if (V.getOperand(0) != V.getOperand(1) ||
22339 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22341 Chain.push_back(V);
22342 V = V.getOperand(0);
22344 switch (V.getOpcode()) {
22346 return SDValue(); // Nothing to combine.
22348 case X86ISD::PSHUFLW:
22349 case X86ISD::PSHUFHW:
22350 if (V.getOpcode() == CombineOp)
22353 Chain.push_back(V);
22357 V = V.getOperand(0);
22361 } while (V.hasOneUse());
22364 // Break out of the loop if we break out of the switch.
22368 if (!V.hasOneUse())
22369 // We fell out of the loop without finding a viable combining instruction.
22372 // Merge this node's mask and our incoming mask.
22373 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22374 for (int &M : Mask)
22376 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22377 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22379 // Rebuild the chain around this new shuffle.
22380 while (!Chain.empty()) {
22381 SDValue W = Chain.pop_back_val();
22383 if (V.getValueType() != W.getOperand(0).getValueType())
22384 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22386 switch (W.getOpcode()) {
22388 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22390 case X86ISD::UNPCKL:
22391 case X86ISD::UNPCKH:
22392 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22395 case X86ISD::PSHUFD:
22396 case X86ISD::PSHUFLW:
22397 case X86ISD::PSHUFHW:
22398 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22402 if (V.getValueType() != N.getValueType())
22403 V = DAG.getBitcast(N.getValueType(), V);
22405 // Return the new chain to replace N.
22409 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22412 /// We walk up the chain, skipping shuffles of the other half and looking
22413 /// through shuffles which switch halves trying to find a shuffle of the same
22414 /// pair of dwords.
22415 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22417 TargetLowering::DAGCombinerInfo &DCI) {
22419 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22420 "Called with something other than an x86 128-bit half shuffle!");
22422 unsigned CombineOpcode = N.getOpcode();
22424 // Walk up a single-use chain looking for a combinable shuffle.
22425 SDValue V = N.getOperand(0);
22426 for (; V.hasOneUse(); V = V.getOperand(0)) {
22427 switch (V.getOpcode()) {
22429 return false; // Nothing combined!
22432 // Skip bitcasts as we always know the type for the target specific
22436 case X86ISD::PSHUFLW:
22437 case X86ISD::PSHUFHW:
22438 if (V.getOpcode() == CombineOpcode)
22441 // Other-half shuffles are no-ops.
22444 // Break out of the loop if we break out of the switch.
22448 if (!V.hasOneUse())
22449 // We fell out of the loop without finding a viable combining instruction.
22452 // Combine away the bottom node as its shuffle will be accumulated into
22453 // a preceding shuffle.
22454 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22456 // Record the old value.
22459 // Merge this node's mask and our incoming mask (adjusted to account for all
22460 // the pshufd instructions encountered).
22461 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22462 for (int &M : Mask)
22464 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22465 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22467 // Check that the shuffles didn't cancel each other out. If not, we need to
22468 // combine to the new one.
22470 // Replace the combinable shuffle with the combined one, updating all users
22471 // so that we re-evaluate the chain here.
22472 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22477 /// \brief Try to combine x86 target specific shuffles.
22478 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22479 TargetLowering::DAGCombinerInfo &DCI,
22480 const X86Subtarget *Subtarget) {
22482 MVT VT = N.getSimpleValueType();
22483 SmallVector<int, 4> Mask;
22485 switch (N.getOpcode()) {
22486 case X86ISD::PSHUFD:
22487 case X86ISD::PSHUFLW:
22488 case X86ISD::PSHUFHW:
22489 Mask = getPSHUFShuffleMask(N);
22490 assert(Mask.size() == 4);
22496 // Nuke no-op shuffles that show up after combining.
22497 if (isNoopShuffleMask(Mask))
22498 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22500 // Look for simplifications involving one or two shuffle instructions.
22501 SDValue V = N.getOperand(0);
22502 switch (N.getOpcode()) {
22505 case X86ISD::PSHUFLW:
22506 case X86ISD::PSHUFHW:
22507 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22509 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22510 return SDValue(); // We combined away this shuffle, so we're done.
22512 // See if this reduces to a PSHUFD which is no more expensive and can
22513 // combine with more operations. Note that it has to at least flip the
22514 // dwords as otherwise it would have been removed as a no-op.
22515 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22516 int DMask[] = {0, 1, 2, 3};
22517 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22518 DMask[DOffset + 0] = DOffset + 1;
22519 DMask[DOffset + 1] = DOffset + 0;
22520 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22521 V = DAG.getBitcast(DVT, V);
22522 DCI.AddToWorklist(V.getNode());
22523 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22524 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22525 DCI.AddToWorklist(V.getNode());
22526 return DAG.getBitcast(VT, V);
22529 // Look for shuffle patterns which can be implemented as a single unpack.
22530 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22531 // only works when we have a PSHUFD followed by two half-shuffles.
22532 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22533 (V.getOpcode() == X86ISD::PSHUFLW ||
22534 V.getOpcode() == X86ISD::PSHUFHW) &&
22535 V.getOpcode() != N.getOpcode() &&
22537 SDValue D = V.getOperand(0);
22538 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22539 D = D.getOperand(0);
22540 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22541 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22542 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22543 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22544 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22546 for (int i = 0; i < 4; ++i) {
22547 WordMask[i + NOffset] = Mask[i] + NOffset;
22548 WordMask[i + VOffset] = VMask[i] + VOffset;
22550 // Map the word mask through the DWord mask.
22552 for (int i = 0; i < 8; ++i)
22553 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22554 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22555 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22556 // We can replace all three shuffles with an unpack.
22557 V = DAG.getBitcast(VT, D.getOperand(0));
22558 DCI.AddToWorklist(V.getNode());
22559 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22568 case X86ISD::PSHUFD:
22569 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22578 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22580 /// We combine this directly on the abstract vector shuffle nodes so it is
22581 /// easier to generically match. We also insert dummy vector shuffle nodes for
22582 /// the operands which explicitly discard the lanes which are unused by this
22583 /// operation to try to flow through the rest of the combiner the fact that
22584 /// they're unused.
22585 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22587 EVT VT = N->getValueType(0);
22589 // We only handle target-independent shuffles.
22590 // FIXME: It would be easy and harmless to use the target shuffle mask
22591 // extraction tool to support more.
22592 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22595 auto *SVN = cast<ShuffleVectorSDNode>(N);
22596 ArrayRef<int> Mask = SVN->getMask();
22597 SDValue V1 = N->getOperand(0);
22598 SDValue V2 = N->getOperand(1);
22600 // We require the first shuffle operand to be the SUB node, and the second to
22601 // be the ADD node.
22602 // FIXME: We should support the commuted patterns.
22603 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22606 // If there are other uses of these operations we can't fold them.
22607 if (!V1->hasOneUse() || !V2->hasOneUse())
22610 // Ensure that both operations have the same operands. Note that we can
22611 // commute the FADD operands.
22612 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22613 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22614 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22617 // We're looking for blends between FADD and FSUB nodes. We insist on these
22618 // nodes being lined up in a specific expected pattern.
22619 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22620 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22621 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22624 // Only specific types are legal at this point, assert so we notice if and
22625 // when these change.
22626 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22627 VT == MVT::v4f64) &&
22628 "Unknown vector type encountered!");
22630 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22633 /// PerformShuffleCombine - Performs several different shuffle combines.
22634 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22635 TargetLowering::DAGCombinerInfo &DCI,
22636 const X86Subtarget *Subtarget) {
22638 SDValue N0 = N->getOperand(0);
22639 SDValue N1 = N->getOperand(1);
22640 EVT VT = N->getValueType(0);
22642 // Don't create instructions with illegal types after legalize types has run.
22643 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22644 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22647 // If we have legalized the vector types, look for blends of FADD and FSUB
22648 // nodes that we can fuse into an ADDSUB node.
22649 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22650 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22653 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22654 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22655 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22656 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22658 // During Type Legalization, when promoting illegal vector types,
22659 // the backend might introduce new shuffle dag nodes and bitcasts.
22661 // This code performs the following transformation:
22662 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22663 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22665 // We do this only if both the bitcast and the BINOP dag nodes have
22666 // one use. Also, perform this transformation only if the new binary
22667 // operation is legal. This is to avoid introducing dag nodes that
22668 // potentially need to be further expanded (or custom lowered) into a
22669 // less optimal sequence of dag nodes.
22670 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22671 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22672 N0.getOpcode() == ISD::BITCAST) {
22673 SDValue BC0 = N0.getOperand(0);
22674 EVT SVT = BC0.getValueType();
22675 unsigned Opcode = BC0.getOpcode();
22676 unsigned NumElts = VT.getVectorNumElements();
22678 if (BC0.hasOneUse() && SVT.isVector() &&
22679 SVT.getVectorNumElements() * 2 == NumElts &&
22680 TLI.isOperationLegal(Opcode, VT)) {
22681 bool CanFold = false;
22693 unsigned SVTNumElts = SVT.getVectorNumElements();
22694 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22695 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22696 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22697 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22698 CanFold = SVOp->getMaskElt(i) < 0;
22701 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22702 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22703 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22704 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22709 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22710 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22711 // consecutive, non-overlapping, and in the right order.
22712 SmallVector<SDValue, 16> Elts;
22713 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22714 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22716 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22719 if (isTargetShuffle(N->getOpcode())) {
22721 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22722 if (Shuffle.getNode())
22725 // Try recursively combining arbitrary sequences of x86 shuffle
22726 // instructions into higher-order shuffles. We do this after combining
22727 // specific PSHUF instruction sequences into their minimal form so that we
22728 // can evaluate how many specialized shuffle instructions are involved in
22729 // a particular chain.
22730 SmallVector<int, 1> NonceMask; // Just a placeholder.
22731 NonceMask.push_back(0);
22732 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22733 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22735 return SDValue(); // This routine will use CombineTo to replace N.
22741 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22742 /// specific shuffle of a load can be folded into a single element load.
22743 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22744 /// shuffles have been custom lowered so we need to handle those here.
22745 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22746 TargetLowering::DAGCombinerInfo &DCI) {
22747 if (DCI.isBeforeLegalizeOps())
22750 SDValue InVec = N->getOperand(0);
22751 SDValue EltNo = N->getOperand(1);
22753 if (!isa<ConstantSDNode>(EltNo))
22756 EVT OriginalVT = InVec.getValueType();
22758 if (InVec.getOpcode() == ISD::BITCAST) {
22759 // Don't duplicate a load with other uses.
22760 if (!InVec.hasOneUse())
22762 EVT BCVT = InVec.getOperand(0).getValueType();
22763 if (!BCVT.isVector() ||
22764 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22766 InVec = InVec.getOperand(0);
22769 EVT CurrentVT = InVec.getValueType();
22771 if (!isTargetShuffle(InVec.getOpcode()))
22774 // Don't duplicate a load with other uses.
22775 if (!InVec.hasOneUse())
22778 SmallVector<int, 16> ShuffleMask;
22780 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22781 ShuffleMask, UnaryShuffle))
22784 // Select the input vector, guarding against out of range extract vector.
22785 unsigned NumElems = CurrentVT.getVectorNumElements();
22786 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22787 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22788 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22789 : InVec.getOperand(1);
22791 // If inputs to shuffle are the same for both ops, then allow 2 uses
22792 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22793 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22795 if (LdNode.getOpcode() == ISD::BITCAST) {
22796 // Don't duplicate a load with other uses.
22797 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22800 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22801 LdNode = LdNode.getOperand(0);
22804 if (!ISD::isNormalLoad(LdNode.getNode()))
22807 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22809 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22812 EVT EltVT = N->getValueType(0);
22813 // If there's a bitcast before the shuffle, check if the load type and
22814 // alignment is valid.
22815 unsigned Align = LN0->getAlignment();
22816 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22817 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22818 EltVT.getTypeForEVT(*DAG.getContext()));
22820 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22823 // All checks match so transform back to vector_shuffle so that DAG combiner
22824 // can finish the job
22827 // Create shuffle node taking into account the case that its a unary shuffle
22828 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22829 : InVec.getOperand(1);
22830 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22831 InVec.getOperand(0), Shuffle,
22833 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22834 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22838 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22839 /// special and don't usually play with other vector types, it's better to
22840 /// handle them early to be sure we emit efficient code by avoiding
22841 /// store-load conversions.
22842 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22843 if (N->getValueType(0) != MVT::x86mmx ||
22844 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22845 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22848 SDValue V = N->getOperand(0);
22849 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22850 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22851 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22852 N->getValueType(0), V.getOperand(0));
22857 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22858 /// generation and convert it from being a bunch of shuffles and extracts
22859 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22860 /// storing the value and loading scalars back, while for x64 we should
22861 /// use 64-bit extracts and shifts.
22862 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22863 TargetLowering::DAGCombinerInfo &DCI) {
22864 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22867 SDValue InputVector = N->getOperand(0);
22868 SDLoc dl(InputVector);
22869 // Detect mmx to i32 conversion through a v2i32 elt extract.
22870 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22871 N->getValueType(0) == MVT::i32 &&
22872 InputVector.getValueType() == MVT::v2i32) {
22874 // The bitcast source is a direct mmx result.
22875 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22876 if (MMXSrc.getValueType() == MVT::x86mmx)
22877 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22878 N->getValueType(0),
22879 InputVector.getNode()->getOperand(0));
22881 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22882 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22883 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22884 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
22885 MMXSrcOp.getOpcode() == ISD::BITCAST &&
22886 MMXSrcOp.getValueType() == MVT::v1i64 &&
22887 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22888 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22889 N->getValueType(0),
22890 MMXSrcOp.getOperand(0));
22893 EVT VT = N->getValueType(0);
22895 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22896 InputVector.getOpcode() == ISD::BITCAST &&
22897 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22898 uint64_t ExtractedElt =
22899 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
22900 uint64_t InputValue =
22901 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
22902 uint64_t Res = (InputValue >> ExtractedElt) & 1;
22903 return DAG.getConstant(Res, dl, MVT::i1);
22905 // Only operate on vectors of 4 elements, where the alternative shuffling
22906 // gets to be more expensive.
22907 if (InputVector.getValueType() != MVT::v4i32)
22910 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22911 // single use which is a sign-extend or zero-extend, and all elements are
22913 SmallVector<SDNode *, 4> Uses;
22914 unsigned ExtractedElements = 0;
22915 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22916 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22917 if (UI.getUse().getResNo() != InputVector.getResNo())
22920 SDNode *Extract = *UI;
22921 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22924 if (Extract->getValueType(0) != MVT::i32)
22926 if (!Extract->hasOneUse())
22928 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22929 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22931 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22934 // Record which element was extracted.
22935 ExtractedElements |=
22936 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22938 Uses.push_back(Extract);
22941 // If not all the elements were used, this may not be worthwhile.
22942 if (ExtractedElements != 15)
22945 // Ok, we've now decided to do the transformation.
22946 // If 64-bit shifts are legal, use the extract-shift sequence,
22947 // otherwise bounce the vector off the cache.
22948 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22951 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22952 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
22953 auto &DL = DAG.getDataLayout();
22954 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
22955 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22956 DAG.getConstant(0, dl, VecIdxTy));
22957 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22958 DAG.getConstant(1, dl, VecIdxTy));
22960 SDValue ShAmt = DAG.getConstant(
22961 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
22962 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22963 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22964 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22965 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22966 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22967 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22969 // Store the value to a temporary stack slot.
22970 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22971 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22972 MachinePointerInfo(), false, false, 0);
22974 EVT ElementType = InputVector.getValueType().getVectorElementType();
22975 unsigned EltSize = ElementType.getSizeInBits() / 8;
22977 // Replace each use (extract) with a load of the appropriate element.
22978 for (unsigned i = 0; i < 4; ++i) {
22979 uint64_t Offset = EltSize * i;
22980 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
22981 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
22983 SDValue ScalarAddr =
22984 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
22986 // Load the scalar.
22987 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22988 ScalarAddr, MachinePointerInfo(),
22989 false, false, false, 0);
22994 // Replace the extracts
22995 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22996 UE = Uses.end(); UI != UE; ++UI) {
22997 SDNode *Extract = *UI;
22999 SDValue Idx = Extract->getOperand(1);
23000 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23001 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23004 // The replacement was made in place; don't return anything.
23009 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23010 const X86Subtarget *Subtarget) {
23012 SDValue Cond = N->getOperand(0);
23013 SDValue LHS = N->getOperand(1);
23014 SDValue RHS = N->getOperand(2);
23016 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23017 SDValue CondSrc = Cond->getOperand(0);
23018 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23019 Cond = CondSrc->getOperand(0);
23022 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23025 // A vselect where all conditions and data are constants can be optimized into
23026 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23027 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23028 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23031 unsigned MaskValue = 0;
23032 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23035 MVT VT = N->getSimpleValueType(0);
23036 unsigned NumElems = VT.getVectorNumElements();
23037 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23038 for (unsigned i = 0; i < NumElems; ++i) {
23039 // Be sure we emit undef where we can.
23040 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23041 ShuffleMask[i] = -1;
23043 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23046 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23047 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23049 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23052 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23054 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23055 TargetLowering::DAGCombinerInfo &DCI,
23056 const X86Subtarget *Subtarget) {
23058 SDValue Cond = N->getOperand(0);
23059 // Get the LHS/RHS of the select.
23060 SDValue LHS = N->getOperand(1);
23061 SDValue RHS = N->getOperand(2);
23062 EVT VT = LHS.getValueType();
23063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23065 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23066 // instructions match the semantics of the common C idiom x<y?x:y but not
23067 // x<=y?x:y, because of how they handle negative zero (which can be
23068 // ignored in unsafe-math mode).
23069 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23070 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23071 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23072 (Subtarget->hasSSE2() ||
23073 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23074 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23076 unsigned Opcode = 0;
23077 // Check for x CC y ? x : y.
23078 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23079 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23083 // Converting this to a min would handle NaNs incorrectly, and swapping
23084 // the operands would cause it to handle comparisons between positive
23085 // and negative zero incorrectly.
23086 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23087 if (!DAG.getTarget().Options.UnsafeFPMath &&
23088 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23090 std::swap(LHS, RHS);
23092 Opcode = X86ISD::FMIN;
23095 // Converting this to a min would handle comparisons between positive
23096 // and negative zero incorrectly.
23097 if (!DAG.getTarget().Options.UnsafeFPMath &&
23098 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23100 Opcode = X86ISD::FMIN;
23103 // Converting this to a min would handle both negative zeros and NaNs
23104 // incorrectly, but we can swap the operands to fix both.
23105 std::swap(LHS, RHS);
23109 Opcode = X86ISD::FMIN;
23113 // Converting this to a max would handle comparisons between positive
23114 // and negative zero incorrectly.
23115 if (!DAG.getTarget().Options.UnsafeFPMath &&
23116 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23118 Opcode = X86ISD::FMAX;
23121 // Converting this to a max would handle NaNs incorrectly, and swapping
23122 // the operands would cause it to handle comparisons between positive
23123 // and negative zero incorrectly.
23124 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23125 if (!DAG.getTarget().Options.UnsafeFPMath &&
23126 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23128 std::swap(LHS, RHS);
23130 Opcode = X86ISD::FMAX;
23133 // Converting this to a max would handle both negative zeros and NaNs
23134 // incorrectly, but we can swap the operands to fix both.
23135 std::swap(LHS, RHS);
23139 Opcode = X86ISD::FMAX;
23142 // Check for x CC y ? y : x -- a min/max with reversed arms.
23143 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23144 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23148 // Converting this to a min would handle comparisons between positive
23149 // and negative zero incorrectly, and swapping the operands would
23150 // cause it to handle NaNs incorrectly.
23151 if (!DAG.getTarget().Options.UnsafeFPMath &&
23152 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23153 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23155 std::swap(LHS, RHS);
23157 Opcode = X86ISD::FMIN;
23160 // Converting this to a min would handle NaNs incorrectly.
23161 if (!DAG.getTarget().Options.UnsafeFPMath &&
23162 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23164 Opcode = X86ISD::FMIN;
23167 // Converting this to a min would handle both negative zeros and NaNs
23168 // incorrectly, but we can swap the operands to fix both.
23169 std::swap(LHS, RHS);
23173 Opcode = X86ISD::FMIN;
23177 // Converting this to a max would handle NaNs incorrectly.
23178 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23180 Opcode = X86ISD::FMAX;
23183 // Converting this to a max would handle comparisons between positive
23184 // and negative zero incorrectly, and swapping the operands would
23185 // cause it to handle NaNs incorrectly.
23186 if (!DAG.getTarget().Options.UnsafeFPMath &&
23187 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23188 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23190 std::swap(LHS, RHS);
23192 Opcode = X86ISD::FMAX;
23195 // Converting this to a max would handle both negative zeros and NaNs
23196 // incorrectly, but we can swap the operands to fix both.
23197 std::swap(LHS, RHS);
23201 Opcode = X86ISD::FMAX;
23207 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23210 EVT CondVT = Cond.getValueType();
23211 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23212 CondVT.getVectorElementType() == MVT::i1) {
23213 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23214 // lowering on KNL. In this case we convert it to
23215 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23216 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23217 // Since SKX these selects have a proper lowering.
23218 EVT OpVT = LHS.getValueType();
23219 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23220 (OpVT.getVectorElementType() == MVT::i8 ||
23221 OpVT.getVectorElementType() == MVT::i16) &&
23222 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23223 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23224 DCI.AddToWorklist(Cond.getNode());
23225 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23228 // If this is a select between two integer constants, try to do some
23230 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23231 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23232 // Don't do this for crazy integer types.
23233 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23234 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23235 // so that TrueC (the true value) is larger than FalseC.
23236 bool NeedsCondInvert = false;
23238 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23239 // Efficiently invertible.
23240 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23241 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23242 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23243 NeedsCondInvert = true;
23244 std::swap(TrueC, FalseC);
23247 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23248 if (FalseC->getAPIntValue() == 0 &&
23249 TrueC->getAPIntValue().isPowerOf2()) {
23250 if (NeedsCondInvert) // Invert the condition if needed.
23251 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23252 DAG.getConstant(1, DL, Cond.getValueType()));
23254 // Zero extend the condition if needed.
23255 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23257 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23258 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23259 DAG.getConstant(ShAmt, DL, MVT::i8));
23262 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23263 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23264 if (NeedsCondInvert) // Invert the condition if needed.
23265 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23266 DAG.getConstant(1, DL, Cond.getValueType()));
23268 // Zero extend the condition if needed.
23269 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23270 FalseC->getValueType(0), Cond);
23271 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23272 SDValue(FalseC, 0));
23275 // Optimize cases that will turn into an LEA instruction. This requires
23276 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23277 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23278 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23279 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23281 bool isFastMultiplier = false;
23283 switch ((unsigned char)Diff) {
23285 case 1: // result = add base, cond
23286 case 2: // result = lea base( , cond*2)
23287 case 3: // result = lea base(cond, cond*2)
23288 case 4: // result = lea base( , cond*4)
23289 case 5: // result = lea base(cond, cond*4)
23290 case 8: // result = lea base( , cond*8)
23291 case 9: // result = lea base(cond, cond*8)
23292 isFastMultiplier = true;
23297 if (isFastMultiplier) {
23298 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23299 if (NeedsCondInvert) // Invert the condition if needed.
23300 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23301 DAG.getConstant(1, DL, Cond.getValueType()));
23303 // Zero extend the condition if needed.
23304 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23306 // Scale the condition by the difference.
23308 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23309 DAG.getConstant(Diff, DL,
23310 Cond.getValueType()));
23312 // Add the base if non-zero.
23313 if (FalseC->getAPIntValue() != 0)
23314 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23315 SDValue(FalseC, 0));
23322 // Canonicalize max and min:
23323 // (x > y) ? x : y -> (x >= y) ? x : y
23324 // (x < y) ? x : y -> (x <= y) ? x : y
23325 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23326 // the need for an extra compare
23327 // against zero. e.g.
23328 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23330 // testl %edi, %edi
23332 // cmovgl %edi, %eax
23336 // cmovsl %eax, %edi
23337 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23338 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23339 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23340 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23345 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23346 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23347 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23348 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23353 // Early exit check
23354 if (!TLI.isTypeLegal(VT))
23357 // Match VSELECTs into subs with unsigned saturation.
23358 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23359 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23360 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23361 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23362 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23364 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23365 // left side invert the predicate to simplify logic below.
23367 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23369 CC = ISD::getSetCCInverse(CC, true);
23370 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23374 if (Other.getNode() && Other->getNumOperands() == 2 &&
23375 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23376 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23377 SDValue CondRHS = Cond->getOperand(1);
23379 // Look for a general sub with unsigned saturation first.
23380 // x >= y ? x-y : 0 --> subus x, y
23381 // x > y ? x-y : 0 --> subus x, y
23382 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23383 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23384 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23386 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23387 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23388 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23389 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23390 // If the RHS is a constant we have to reverse the const
23391 // canonicalization.
23392 // x > C-1 ? x+-C : 0 --> subus x, C
23393 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23394 CondRHSConst->getAPIntValue() ==
23395 (-OpRHSConst->getAPIntValue() - 1))
23396 return DAG.getNode(
23397 X86ISD::SUBUS, DL, VT, OpLHS,
23398 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23400 // Another special case: If C was a sign bit, the sub has been
23401 // canonicalized into a xor.
23402 // FIXME: Would it be better to use computeKnownBits to determine
23403 // whether it's safe to decanonicalize the xor?
23404 // x s< 0 ? x^C : 0 --> subus x, C
23405 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23406 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23407 OpRHSConst->getAPIntValue().isSignBit())
23408 // Note that we have to rebuild the RHS constant here to ensure we
23409 // don't rely on particular values of undef lanes.
23410 return DAG.getNode(
23411 X86ISD::SUBUS, DL, VT, OpLHS,
23412 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23417 // Simplify vector selection if condition value type matches vselect
23419 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23420 assert(Cond.getValueType().isVector() &&
23421 "vector select expects a vector selector!");
23423 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23424 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23426 // Try invert the condition if true value is not all 1s and false value
23428 if (!TValIsAllOnes && !FValIsAllZeros &&
23429 // Check if the selector will be produced by CMPP*/PCMP*
23430 Cond.getOpcode() == ISD::SETCC &&
23431 // Check if SETCC has already been promoted
23432 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23434 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23435 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23437 if (TValIsAllZeros || FValIsAllOnes) {
23438 SDValue CC = Cond.getOperand(2);
23439 ISD::CondCode NewCC =
23440 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23441 Cond.getOperand(0).getValueType().isInteger());
23442 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23443 std::swap(LHS, RHS);
23444 TValIsAllOnes = FValIsAllOnes;
23445 FValIsAllZeros = TValIsAllZeros;
23449 if (TValIsAllOnes || FValIsAllZeros) {
23452 if (TValIsAllOnes && FValIsAllZeros)
23454 else if (TValIsAllOnes)
23456 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23457 else if (FValIsAllZeros)
23458 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23459 DAG.getBitcast(CondVT, LHS));
23461 return DAG.getBitcast(VT, Ret);
23465 // We should generate an X86ISD::BLENDI from a vselect if its argument
23466 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23467 // constants. This specific pattern gets generated when we split a
23468 // selector for a 512 bit vector in a machine without AVX512 (but with
23469 // 256-bit vectors), during legalization:
23471 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23473 // Iff we find this pattern and the build_vectors are built from
23474 // constants, we translate the vselect into a shuffle_vector that we
23475 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23476 if ((N->getOpcode() == ISD::VSELECT ||
23477 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23478 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23479 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23480 if (Shuffle.getNode())
23484 // If this is a *dynamic* select (non-constant condition) and we can match
23485 // this node with one of the variable blend instructions, restructure the
23486 // condition so that the blends can use the high bit of each element and use
23487 // SimplifyDemandedBits to simplify the condition operand.
23488 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23489 !DCI.isBeforeLegalize() &&
23490 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23491 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23493 // Don't optimize vector selects that map to mask-registers.
23497 // We can only handle the cases where VSELECT is directly legal on the
23498 // subtarget. We custom lower VSELECT nodes with constant conditions and
23499 // this makes it hard to see whether a dynamic VSELECT will correctly
23500 // lower, so we both check the operation's status and explicitly handle the
23501 // cases where a *dynamic* blend will fail even though a constant-condition
23502 // blend could be custom lowered.
23503 // FIXME: We should find a better way to handle this class of problems.
23504 // Potentially, we should combine constant-condition vselect nodes
23505 // pre-legalization into shuffles and not mark as many types as custom
23507 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23509 // FIXME: We don't support i16-element blends currently. We could and
23510 // should support them by making *all* the bits in the condition be set
23511 // rather than just the high bit and using an i8-element blend.
23512 if (VT.getScalarType() == MVT::i16)
23514 // Dynamic blending was only available from SSE4.1 onward.
23515 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23517 // Byte blends are only available in AVX2
23518 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23519 !Subtarget->hasAVX2())
23522 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23523 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23525 APInt KnownZero, KnownOne;
23526 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23527 DCI.isBeforeLegalizeOps());
23528 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23529 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23531 // If we changed the computation somewhere in the DAG, this change
23532 // will affect all users of Cond.
23533 // Make sure it is fine and update all the nodes so that we do not
23534 // use the generic VSELECT anymore. Otherwise, we may perform
23535 // wrong optimizations as we messed up with the actual expectation
23536 // for the vector boolean values.
23537 if (Cond != TLO.Old) {
23538 // Check all uses of that condition operand to check whether it will be
23539 // consumed by non-BLEND instructions, which may depend on all bits are
23541 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23543 if (I->getOpcode() != ISD::VSELECT)
23544 // TODO: Add other opcodes eventually lowered into BLEND.
23547 // Update all the users of the condition, before committing the change,
23548 // so that the VSELECT optimizations that expect the correct vector
23549 // boolean value will not be triggered.
23550 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23552 DAG.ReplaceAllUsesOfValueWith(
23554 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23555 Cond, I->getOperand(1), I->getOperand(2)));
23556 DCI.CommitTargetLoweringOpt(TLO);
23559 // At this point, only Cond is changed. Change the condition
23560 // just for N to keep the opportunity to optimize all other
23561 // users their own way.
23562 DAG.ReplaceAllUsesOfValueWith(
23564 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23565 TLO.New, N->getOperand(1), N->getOperand(2)));
23573 // Check whether a boolean test is testing a boolean value generated by
23574 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23577 // Simplify the following patterns:
23578 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23579 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23580 // to (Op EFLAGS Cond)
23582 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23583 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23584 // to (Op EFLAGS !Cond)
23586 // where Op could be BRCOND or CMOV.
23588 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23589 // Quit if not CMP and SUB with its value result used.
23590 if (Cmp.getOpcode() != X86ISD::CMP &&
23591 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23594 // Quit if not used as a boolean value.
23595 if (CC != X86::COND_E && CC != X86::COND_NE)
23598 // Check CMP operands. One of them should be 0 or 1 and the other should be
23599 // an SetCC or extended from it.
23600 SDValue Op1 = Cmp.getOperand(0);
23601 SDValue Op2 = Cmp.getOperand(1);
23604 const ConstantSDNode* C = nullptr;
23605 bool needOppositeCond = (CC == X86::COND_E);
23606 bool checkAgainstTrue = false; // Is it a comparison against 1?
23608 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23610 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23612 else // Quit if all operands are not constants.
23615 if (C->getZExtValue() == 1) {
23616 needOppositeCond = !needOppositeCond;
23617 checkAgainstTrue = true;
23618 } else if (C->getZExtValue() != 0)
23619 // Quit if the constant is neither 0 or 1.
23622 bool truncatedToBoolWithAnd = false;
23623 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23624 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23625 SetCC.getOpcode() == ISD::TRUNCATE ||
23626 SetCC.getOpcode() == ISD::AND) {
23627 if (SetCC.getOpcode() == ISD::AND) {
23629 ConstantSDNode *CS;
23630 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23631 CS->getZExtValue() == 1)
23633 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23634 CS->getZExtValue() == 1)
23638 SetCC = SetCC.getOperand(OpIdx);
23639 truncatedToBoolWithAnd = true;
23641 SetCC = SetCC.getOperand(0);
23644 switch (SetCC.getOpcode()) {
23645 case X86ISD::SETCC_CARRY:
23646 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23647 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23648 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23649 // truncated to i1 using 'and'.
23650 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23652 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23653 "Invalid use of SETCC_CARRY!");
23655 case X86ISD::SETCC:
23656 // Set the condition code or opposite one if necessary.
23657 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23658 if (needOppositeCond)
23659 CC = X86::GetOppositeBranchCondition(CC);
23660 return SetCC.getOperand(1);
23661 case X86ISD::CMOV: {
23662 // Check whether false/true value has canonical one, i.e. 0 or 1.
23663 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23664 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23665 // Quit if true value is not a constant.
23668 // Quit if false value is not a constant.
23670 SDValue Op = SetCC.getOperand(0);
23671 // Skip 'zext' or 'trunc' node.
23672 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23673 Op.getOpcode() == ISD::TRUNCATE)
23674 Op = Op.getOperand(0);
23675 // A special case for rdrand/rdseed, where 0 is set if false cond is
23677 if ((Op.getOpcode() != X86ISD::RDRAND &&
23678 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23681 // Quit if false value is not the constant 0 or 1.
23682 bool FValIsFalse = true;
23683 if (FVal && FVal->getZExtValue() != 0) {
23684 if (FVal->getZExtValue() != 1)
23686 // If FVal is 1, opposite cond is needed.
23687 needOppositeCond = !needOppositeCond;
23688 FValIsFalse = false;
23690 // Quit if TVal is not the constant opposite of FVal.
23691 if (FValIsFalse && TVal->getZExtValue() != 1)
23693 if (!FValIsFalse && TVal->getZExtValue() != 0)
23695 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23696 if (needOppositeCond)
23697 CC = X86::GetOppositeBranchCondition(CC);
23698 return SetCC.getOperand(3);
23705 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23707 /// (X86or (X86setcc) (X86setcc))
23708 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23709 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23710 X86::CondCode &CC1, SDValue &Flags,
23712 if (Cond->getOpcode() == X86ISD::CMP) {
23713 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23714 if (!CondOp1C || !CondOp1C->isNullValue())
23717 Cond = Cond->getOperand(0);
23722 SDValue SetCC0, SetCC1;
23723 switch (Cond->getOpcode()) {
23724 default: return false;
23731 SetCC0 = Cond->getOperand(0);
23732 SetCC1 = Cond->getOperand(1);
23736 // Make sure we have SETCC nodes, using the same flags value.
23737 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23738 SetCC1.getOpcode() != X86ISD::SETCC ||
23739 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23742 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23743 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23744 Flags = SetCC0->getOperand(1);
23748 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23749 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23750 TargetLowering::DAGCombinerInfo &DCI,
23751 const X86Subtarget *Subtarget) {
23754 // If the flag operand isn't dead, don't touch this CMOV.
23755 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23758 SDValue FalseOp = N->getOperand(0);
23759 SDValue TrueOp = N->getOperand(1);
23760 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23761 SDValue Cond = N->getOperand(3);
23763 if (CC == X86::COND_E || CC == X86::COND_NE) {
23764 switch (Cond.getOpcode()) {
23768 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23769 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23770 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23776 Flags = checkBoolTestSetCCCombine(Cond, CC);
23777 if (Flags.getNode() &&
23778 // Extra check as FCMOV only supports a subset of X86 cond.
23779 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23780 SDValue Ops[] = { FalseOp, TrueOp,
23781 DAG.getConstant(CC, DL, MVT::i8), Flags };
23782 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23785 // If this is a select between two integer constants, try to do some
23786 // optimizations. Note that the operands are ordered the opposite of SELECT
23788 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23789 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23790 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23791 // larger than FalseC (the false value).
23792 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23793 CC = X86::GetOppositeBranchCondition(CC);
23794 std::swap(TrueC, FalseC);
23795 std::swap(TrueOp, FalseOp);
23798 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23799 // This is efficient for any integer data type (including i8/i16) and
23801 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23802 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23803 DAG.getConstant(CC, DL, MVT::i8), Cond);
23805 // Zero extend the condition if needed.
23806 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23808 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23809 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23810 DAG.getConstant(ShAmt, DL, MVT::i8));
23811 if (N->getNumValues() == 2) // Dead flag value?
23812 return DCI.CombineTo(N, Cond, SDValue());
23816 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23817 // for any integer data type, including i8/i16.
23818 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23819 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23820 DAG.getConstant(CC, DL, MVT::i8), Cond);
23822 // Zero extend the condition if needed.
23823 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23824 FalseC->getValueType(0), Cond);
23825 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23826 SDValue(FalseC, 0));
23828 if (N->getNumValues() == 2) // Dead flag value?
23829 return DCI.CombineTo(N, Cond, SDValue());
23833 // Optimize cases that will turn into an LEA instruction. This requires
23834 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23835 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23836 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23837 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23839 bool isFastMultiplier = false;
23841 switch ((unsigned char)Diff) {
23843 case 1: // result = add base, cond
23844 case 2: // result = lea base( , cond*2)
23845 case 3: // result = lea base(cond, cond*2)
23846 case 4: // result = lea base( , cond*4)
23847 case 5: // result = lea base(cond, cond*4)
23848 case 8: // result = lea base( , cond*8)
23849 case 9: // result = lea base(cond, cond*8)
23850 isFastMultiplier = true;
23855 if (isFastMultiplier) {
23856 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23857 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23858 DAG.getConstant(CC, DL, MVT::i8), Cond);
23859 // Zero extend the condition if needed.
23860 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23862 // Scale the condition by the difference.
23864 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23865 DAG.getConstant(Diff, DL, Cond.getValueType()));
23867 // Add the base if non-zero.
23868 if (FalseC->getAPIntValue() != 0)
23869 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23870 SDValue(FalseC, 0));
23871 if (N->getNumValues() == 2) // Dead flag value?
23872 return DCI.CombineTo(N, Cond, SDValue());
23879 // Handle these cases:
23880 // (select (x != c), e, c) -> select (x != c), e, x),
23881 // (select (x == c), c, e) -> select (x == c), x, e)
23882 // where the c is an integer constant, and the "select" is the combination
23883 // of CMOV and CMP.
23885 // The rationale for this change is that the conditional-move from a constant
23886 // needs two instructions, however, conditional-move from a register needs
23887 // only one instruction.
23889 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23890 // some instruction-combining opportunities. This opt needs to be
23891 // postponed as late as possible.
23893 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23894 // the DCI.xxxx conditions are provided to postpone the optimization as
23895 // late as possible.
23897 ConstantSDNode *CmpAgainst = nullptr;
23898 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23899 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23900 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23902 if (CC == X86::COND_NE &&
23903 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23904 CC = X86::GetOppositeBranchCondition(CC);
23905 std::swap(TrueOp, FalseOp);
23908 if (CC == X86::COND_E &&
23909 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23910 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23911 DAG.getConstant(CC, DL, MVT::i8), Cond };
23912 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23917 // Fold and/or of setcc's to double CMOV:
23918 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
23919 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
23921 // This combine lets us generate:
23922 // cmovcc1 (jcc1 if we don't have CMOV)
23928 // cmovne (jne if we don't have CMOV)
23929 // When we can't use the CMOV instruction, it might increase branch
23931 // When we can use CMOV, or when there is no mispredict, this improves
23932 // throughput and reduces register pressure.
23934 if (CC == X86::COND_NE) {
23936 X86::CondCode CC0, CC1;
23938 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
23940 std::swap(FalseOp, TrueOp);
23941 CC0 = X86::GetOppositeBranchCondition(CC0);
23942 CC1 = X86::GetOppositeBranchCondition(CC1);
23945 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
23947 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
23948 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
23949 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23950 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
23958 /// PerformMulCombine - Optimize a single multiply with constant into two
23959 /// in order to implement it with two cheaper instructions, e.g.
23960 /// LEA + SHL, LEA + LEA.
23961 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23962 TargetLowering::DAGCombinerInfo &DCI) {
23963 // An imul is usually smaller than the alternative sequence.
23964 if (DAG.getMachineFunction().getFunction()->optForMinSize())
23967 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23970 EVT VT = N->getValueType(0);
23971 if (VT != MVT::i64 && VT != MVT::i32)
23974 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23977 uint64_t MulAmt = C->getZExtValue();
23978 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23981 uint64_t MulAmt1 = 0;
23982 uint64_t MulAmt2 = 0;
23983 if ((MulAmt % 9) == 0) {
23985 MulAmt2 = MulAmt / 9;
23986 } else if ((MulAmt % 5) == 0) {
23988 MulAmt2 = MulAmt / 5;
23989 } else if ((MulAmt % 3) == 0) {
23991 MulAmt2 = MulAmt / 3;
23994 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23997 if (isPowerOf2_64(MulAmt2) &&
23998 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23999 // If second multiplifer is pow2, issue it first. We want the multiply by
24000 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24002 std::swap(MulAmt1, MulAmt2);
24005 if (isPowerOf2_64(MulAmt1))
24006 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24007 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24009 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24010 DAG.getConstant(MulAmt1, DL, VT));
24012 if (isPowerOf2_64(MulAmt2))
24013 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24014 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24016 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24017 DAG.getConstant(MulAmt2, DL, VT));
24019 // Do not add new nodes to DAG combiner worklist.
24020 DCI.CombineTo(N, NewMul, false);
24025 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24026 SDValue N0 = N->getOperand(0);
24027 SDValue N1 = N->getOperand(1);
24028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24029 EVT VT = N0.getValueType();
24031 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24032 // since the result of setcc_c is all zero's or all ones.
24033 if (VT.isInteger() && !VT.isVector() &&
24034 N1C && N0.getOpcode() == ISD::AND &&
24035 N0.getOperand(1).getOpcode() == ISD::Constant) {
24036 SDValue N00 = N0.getOperand(0);
24037 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24038 APInt ShAmt = N1C->getAPIntValue();
24039 Mask = Mask.shl(ShAmt);
24040 bool MaskOK = false;
24041 // We can handle cases concerning bit-widening nodes containing setcc_c if
24042 // we carefully interrogate the mask to make sure we are semantics
24044 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24045 // of the underlying setcc_c operation if the setcc_c was zero extended.
24046 // Consider the following example:
24047 // zext(setcc_c) -> i32 0x0000FFFF
24048 // c1 -> i32 0x0000FFFF
24049 // c2 -> i32 0x00000001
24050 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24051 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24052 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24054 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24055 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24057 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24058 N00.getOpcode() == ISD::ANY_EXTEND) &&
24059 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24060 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24062 if (MaskOK && Mask != 0) {
24064 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24068 // Hardware support for vector shifts is sparse which makes us scalarize the
24069 // vector operations in many cases. Also, on sandybridge ADD is faster than
24071 // (shl V, 1) -> add V,V
24072 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24073 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24074 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24075 // We shift all of the values by one. In many cases we do not have
24076 // hardware support for this operation. This is better expressed as an ADD
24078 if (N1SplatC->getAPIntValue() == 1)
24079 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24085 /// \brief Returns a vector of 0s if the node in input is a vector logical
24086 /// shift by a constant amount which is known to be bigger than or equal
24087 /// to the vector element size in bits.
24088 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24089 const X86Subtarget *Subtarget) {
24090 EVT VT = N->getValueType(0);
24092 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24093 (!Subtarget->hasInt256() ||
24094 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24097 SDValue Amt = N->getOperand(1);
24099 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24100 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24101 APInt ShiftAmt = AmtSplat->getAPIntValue();
24102 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24104 // SSE2/AVX2 logical shifts always return a vector of 0s
24105 // if the shift amount is bigger than or equal to
24106 // the element size. The constant shift amount will be
24107 // encoded as a 8-bit immediate.
24108 if (ShiftAmt.trunc(8).uge(MaxAmount))
24109 return getZeroVector(VT, Subtarget, DAG, DL);
24115 /// PerformShiftCombine - Combine shifts.
24116 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24117 TargetLowering::DAGCombinerInfo &DCI,
24118 const X86Subtarget *Subtarget) {
24119 if (N->getOpcode() == ISD::SHL)
24120 if (SDValue V = PerformSHLCombine(N, DAG))
24123 // Try to fold this logical shift into a zero vector.
24124 if (N->getOpcode() != ISD::SRA)
24125 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24131 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24132 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24133 // and friends. Likewise for OR -> CMPNEQSS.
24134 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24135 TargetLowering::DAGCombinerInfo &DCI,
24136 const X86Subtarget *Subtarget) {
24139 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24140 // we're requiring SSE2 for both.
24141 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24142 SDValue N0 = N->getOperand(0);
24143 SDValue N1 = N->getOperand(1);
24144 SDValue CMP0 = N0->getOperand(1);
24145 SDValue CMP1 = N1->getOperand(1);
24148 // The SETCCs should both refer to the same CMP.
24149 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24152 SDValue CMP00 = CMP0->getOperand(0);
24153 SDValue CMP01 = CMP0->getOperand(1);
24154 EVT VT = CMP00.getValueType();
24156 if (VT == MVT::f32 || VT == MVT::f64) {
24157 bool ExpectingFlags = false;
24158 // Check for any users that want flags:
24159 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24160 !ExpectingFlags && UI != UE; ++UI)
24161 switch (UI->getOpcode()) {
24166 ExpectingFlags = true;
24168 case ISD::CopyToReg:
24169 case ISD::SIGN_EXTEND:
24170 case ISD::ZERO_EXTEND:
24171 case ISD::ANY_EXTEND:
24175 if (!ExpectingFlags) {
24176 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24177 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24179 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24180 X86::CondCode tmp = cc0;
24185 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24186 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24187 // FIXME: need symbolic constants for these magic numbers.
24188 // See X86ATTInstPrinter.cpp:printSSECC().
24189 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24190 if (Subtarget->hasAVX512()) {
24191 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24193 DAG.getConstant(x86cc, DL, MVT::i8));
24194 if (N->getValueType(0) != MVT::i1)
24195 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24199 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24200 CMP00.getValueType(), CMP00, CMP01,
24201 DAG.getConstant(x86cc, DL,
24204 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24205 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24207 if (is64BitFP && !Subtarget->is64Bit()) {
24208 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24209 // 64-bit integer, since that's not a legal type. Since
24210 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24211 // bits, but can do this little dance to extract the lowest 32 bits
24212 // and work with those going forward.
24213 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24215 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24216 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24217 Vector32, DAG.getIntPtrConstant(0, DL));
24221 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24222 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24223 DAG.getConstant(1, DL, IntVT));
24224 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24226 return OneBitOfTruth;
24234 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24235 /// so it can be folded inside ANDNP.
24236 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24237 EVT VT = N->getValueType(0);
24239 // Match direct AllOnes for 128 and 256-bit vectors
24240 if (ISD::isBuildVectorAllOnes(N))
24243 // Look through a bit convert.
24244 if (N->getOpcode() == ISD::BITCAST)
24245 N = N->getOperand(0).getNode();
24247 // Sometimes the operand may come from a insert_subvector building a 256-bit
24249 if (VT.is256BitVector() &&
24250 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24251 SDValue V1 = N->getOperand(0);
24252 SDValue V2 = N->getOperand(1);
24254 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24255 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24256 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24257 ISD::isBuildVectorAllOnes(V2.getNode()))
24264 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24265 // register. In most cases we actually compare or select YMM-sized registers
24266 // and mixing the two types creates horrible code. This method optimizes
24267 // some of the transition sequences.
24268 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24269 TargetLowering::DAGCombinerInfo &DCI,
24270 const X86Subtarget *Subtarget) {
24271 EVT VT = N->getValueType(0);
24272 if (!VT.is256BitVector())
24275 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24276 N->getOpcode() == ISD::ZERO_EXTEND ||
24277 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24279 SDValue Narrow = N->getOperand(0);
24280 EVT NarrowVT = Narrow->getValueType(0);
24281 if (!NarrowVT.is128BitVector())
24284 if (Narrow->getOpcode() != ISD::XOR &&
24285 Narrow->getOpcode() != ISD::AND &&
24286 Narrow->getOpcode() != ISD::OR)
24289 SDValue N0 = Narrow->getOperand(0);
24290 SDValue N1 = Narrow->getOperand(1);
24293 // The Left side has to be a trunc.
24294 if (N0.getOpcode() != ISD::TRUNCATE)
24297 // The type of the truncated inputs.
24298 EVT WideVT = N0->getOperand(0)->getValueType(0);
24302 // The right side has to be a 'trunc' or a constant vector.
24303 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24304 ConstantSDNode *RHSConstSplat = nullptr;
24305 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24306 RHSConstSplat = RHSBV->getConstantSplatNode();
24307 if (!RHSTrunc && !RHSConstSplat)
24310 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24312 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24315 // Set N0 and N1 to hold the inputs to the new wide operation.
24316 N0 = N0->getOperand(0);
24317 if (RHSConstSplat) {
24318 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24319 SDValue(RHSConstSplat, 0));
24320 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24321 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24322 } else if (RHSTrunc) {
24323 N1 = N1->getOperand(0);
24326 // Generate the wide operation.
24327 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24328 unsigned Opcode = N->getOpcode();
24330 case ISD::ANY_EXTEND:
24332 case ISD::ZERO_EXTEND: {
24333 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24334 APInt Mask = APInt::getAllOnesValue(InBits);
24335 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24336 return DAG.getNode(ISD::AND, DL, VT,
24337 Op, DAG.getConstant(Mask, DL, VT));
24339 case ISD::SIGN_EXTEND:
24340 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24341 Op, DAG.getValueType(NarrowVT));
24343 llvm_unreachable("Unexpected opcode");
24347 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24348 TargetLowering::DAGCombinerInfo &DCI,
24349 const X86Subtarget *Subtarget) {
24350 SDValue N0 = N->getOperand(0);
24351 SDValue N1 = N->getOperand(1);
24354 // A vector zext_in_reg may be represented as a shuffle,
24355 // feeding into a bitcast (this represents anyext) feeding into
24356 // an and with a mask.
24357 // We'd like to try to combine that into a shuffle with zero
24358 // plus a bitcast, removing the and.
24359 if (N0.getOpcode() != ISD::BITCAST ||
24360 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24363 // The other side of the AND should be a splat of 2^C, where C
24364 // is the number of bits in the source type.
24365 if (N1.getOpcode() == ISD::BITCAST)
24366 N1 = N1.getOperand(0);
24367 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24369 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24371 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24372 EVT SrcType = Shuffle->getValueType(0);
24374 // We expect a single-source shuffle
24375 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24378 unsigned SrcSize = SrcType.getScalarSizeInBits();
24380 APInt SplatValue, SplatUndef;
24381 unsigned SplatBitSize;
24383 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24384 SplatBitSize, HasAnyUndefs))
24387 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24388 // Make sure the splat matches the mask we expect
24389 if (SplatBitSize > ResSize ||
24390 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24393 // Make sure the input and output size make sense
24394 if (SrcSize >= ResSize || ResSize % SrcSize)
24397 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24398 // The number of u's between each two values depends on the ratio between
24399 // the source and dest type.
24400 unsigned ZextRatio = ResSize / SrcSize;
24401 bool IsZext = true;
24402 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24403 if (i % ZextRatio) {
24404 if (Shuffle->getMaskElt(i) > 0) {
24410 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24411 // Expected element number
24421 // Ok, perform the transformation - replace the shuffle with
24422 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24423 // (instead of undef) where the k elements come from the zero vector.
24424 SmallVector<int, 8> Mask;
24425 unsigned NumElems = SrcType.getVectorNumElements();
24426 for (unsigned i = 0; i < NumElems; ++i)
24428 Mask.push_back(NumElems);
24430 Mask.push_back(i / ZextRatio);
24432 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24433 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24434 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24437 /// If both input operands of a logic op are being cast from floating point
24438 /// types, try to convert this into a floating point logic node to avoid
24439 /// unnecessary moves from SSE to integer registers.
24440 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24441 const X86Subtarget *Subtarget) {
24442 unsigned FPOpcode = ISD::DELETED_NODE;
24443 if (N->getOpcode() == ISD::AND)
24444 FPOpcode = X86ISD::FAND;
24445 else if (N->getOpcode() == ISD::OR)
24446 FPOpcode = X86ISD::FOR;
24447 else if (N->getOpcode() == ISD::XOR)
24448 FPOpcode = X86ISD::FXOR;
24450 assert(FPOpcode != ISD::DELETED_NODE &&
24451 "Unexpected input node for FP logic conversion");
24453 EVT VT = N->getValueType(0);
24454 SDValue N0 = N->getOperand(0);
24455 SDValue N1 = N->getOperand(1);
24457 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24458 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24459 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24460 SDValue N00 = N0.getOperand(0);
24461 SDValue N10 = N1.getOperand(0);
24462 EVT N00Type = N00.getValueType();
24463 EVT N10Type = N10.getValueType();
24464 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24465 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24466 return DAG.getBitcast(VT, FPLogic);
24472 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24473 TargetLowering::DAGCombinerInfo &DCI,
24474 const X86Subtarget *Subtarget) {
24475 if (DCI.isBeforeLegalizeOps())
24478 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24481 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24484 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24487 EVT VT = N->getValueType(0);
24488 SDValue N0 = N->getOperand(0);
24489 SDValue N1 = N->getOperand(1);
24492 // Create BEXTR instructions
24493 // BEXTR is ((X >> imm) & (2**size-1))
24494 if (VT == MVT::i32 || VT == MVT::i64) {
24495 // Check for BEXTR.
24496 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24497 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24498 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24499 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24500 if (MaskNode && ShiftNode) {
24501 uint64_t Mask = MaskNode->getZExtValue();
24502 uint64_t Shift = ShiftNode->getZExtValue();
24503 if (isMask_64(Mask)) {
24504 uint64_t MaskSize = countPopulation(Mask);
24505 if (Shift + MaskSize <= VT.getSizeInBits())
24506 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24507 DAG.getConstant(Shift | (MaskSize << 8), DL,
24516 // Want to form ANDNP nodes:
24517 // 1) In the hopes of then easily combining them with OR and AND nodes
24518 // to form PBLEND/PSIGN.
24519 // 2) To match ANDN packed intrinsics
24520 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24523 // Check LHS for vnot
24524 if (N0.getOpcode() == ISD::XOR &&
24525 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24526 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24527 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24529 // Check RHS for vnot
24530 if (N1.getOpcode() == ISD::XOR &&
24531 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24532 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24533 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24538 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24539 TargetLowering::DAGCombinerInfo &DCI,
24540 const X86Subtarget *Subtarget) {
24541 if (DCI.isBeforeLegalizeOps())
24544 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24547 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24550 SDValue N0 = N->getOperand(0);
24551 SDValue N1 = N->getOperand(1);
24552 EVT VT = N->getValueType(0);
24554 // look for psign/blend
24555 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24556 if (!Subtarget->hasSSSE3() ||
24557 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24560 // Canonicalize pandn to RHS
24561 if (N0.getOpcode() == X86ISD::ANDNP)
24563 // or (and (m, y), (pandn m, x))
24564 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24565 SDValue Mask = N1.getOperand(0);
24566 SDValue X = N1.getOperand(1);
24568 if (N0.getOperand(0) == Mask)
24569 Y = N0.getOperand(1);
24570 if (N0.getOperand(1) == Mask)
24571 Y = N0.getOperand(0);
24573 // Check to see if the mask appeared in both the AND and ANDNP and
24577 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24578 // Look through mask bitcast.
24579 if (Mask.getOpcode() == ISD::BITCAST)
24580 Mask = Mask.getOperand(0);
24581 if (X.getOpcode() == ISD::BITCAST)
24582 X = X.getOperand(0);
24583 if (Y.getOpcode() == ISD::BITCAST)
24584 Y = Y.getOperand(0);
24586 EVT MaskVT = Mask.getValueType();
24588 // Validate that the Mask operand is a vector sra node.
24589 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24590 // there is no psrai.b
24591 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24592 unsigned SraAmt = ~0;
24593 if (Mask.getOpcode() == ISD::SRA) {
24594 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24595 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24596 SraAmt = AmtConst->getZExtValue();
24597 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24598 SDValue SraC = Mask.getOperand(1);
24599 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24601 if ((SraAmt + 1) != EltBits)
24606 // Now we know we at least have a plendvb with the mask val. See if
24607 // we can form a psignb/w/d.
24608 // psign = x.type == y.type == mask.type && y = sub(0, x);
24609 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24610 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24611 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24612 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24613 "Unsupported VT for PSIGN");
24614 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24615 return DAG.getBitcast(VT, Mask);
24617 // PBLENDVB only available on SSE 4.1
24618 if (!Subtarget->hasSSE41())
24621 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24623 X = DAG.getBitcast(BlendVT, X);
24624 Y = DAG.getBitcast(BlendVT, Y);
24625 Mask = DAG.getBitcast(BlendVT, Mask);
24626 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24627 return DAG.getBitcast(VT, Mask);
24631 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24634 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24635 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24637 // SHLD/SHRD instructions have lower register pressure, but on some
24638 // platforms they have higher latency than the equivalent
24639 // series of shifts/or that would otherwise be generated.
24640 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24641 // have higher latencies and we are not optimizing for size.
24642 if (!OptForSize && Subtarget->isSHLDSlow())
24645 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24647 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24649 if (!N0.hasOneUse() || !N1.hasOneUse())
24652 SDValue ShAmt0 = N0.getOperand(1);
24653 if (ShAmt0.getValueType() != MVT::i8)
24655 SDValue ShAmt1 = N1.getOperand(1);
24656 if (ShAmt1.getValueType() != MVT::i8)
24658 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24659 ShAmt0 = ShAmt0.getOperand(0);
24660 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24661 ShAmt1 = ShAmt1.getOperand(0);
24664 unsigned Opc = X86ISD::SHLD;
24665 SDValue Op0 = N0.getOperand(0);
24666 SDValue Op1 = N1.getOperand(0);
24667 if (ShAmt0.getOpcode() == ISD::SUB) {
24668 Opc = X86ISD::SHRD;
24669 std::swap(Op0, Op1);
24670 std::swap(ShAmt0, ShAmt1);
24673 unsigned Bits = VT.getSizeInBits();
24674 if (ShAmt1.getOpcode() == ISD::SUB) {
24675 SDValue Sum = ShAmt1.getOperand(0);
24676 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24677 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24678 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24679 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24680 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24681 return DAG.getNode(Opc, DL, VT,
24683 DAG.getNode(ISD::TRUNCATE, DL,
24686 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24687 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24689 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24690 return DAG.getNode(Opc, DL, VT,
24691 N0.getOperand(0), N1.getOperand(0),
24692 DAG.getNode(ISD::TRUNCATE, DL,
24699 // Generate NEG and CMOV for integer abs.
24700 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24701 EVT VT = N->getValueType(0);
24703 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24704 // 8-bit integer abs to NEG and CMOV.
24705 if (VT.isInteger() && VT.getSizeInBits() == 8)
24708 SDValue N0 = N->getOperand(0);
24709 SDValue N1 = N->getOperand(1);
24712 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24713 // and change it to SUB and CMOV.
24714 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24715 N0.getOpcode() == ISD::ADD &&
24716 N0.getOperand(1) == N1 &&
24717 N1.getOpcode() == ISD::SRA &&
24718 N1.getOperand(0) == N0.getOperand(0))
24719 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24720 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24721 // Generate SUB & CMOV.
24722 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24723 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24725 SDValue Ops[] = { N0.getOperand(0), Neg,
24726 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24727 SDValue(Neg.getNode(), 1) };
24728 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24733 // Try to turn tests against the signbit in the form of:
24734 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24737 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24738 // This is only worth doing if the output type is i8.
24739 if (N->getValueType(0) != MVT::i8)
24742 SDValue N0 = N->getOperand(0);
24743 SDValue N1 = N->getOperand(1);
24745 // We should be performing an xor against a truncated shift.
24746 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24749 // Make sure we are performing an xor against one.
24750 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24753 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24754 SDValue Shift = N0.getOperand(0);
24755 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24758 // Make sure we are truncating from one of i16, i32 or i64.
24759 EVT ShiftTy = Shift.getValueType();
24760 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24763 // Make sure the shift amount extracts the sign bit.
24764 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24765 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24768 // Create a greater-than comparison against -1.
24769 // N.B. Using SETGE against 0 works but we want a canonical looking
24770 // comparison, using SETGT matches up with what TranslateX86CC.
24772 SDValue ShiftOp = Shift.getOperand(0);
24773 EVT ShiftOpTy = ShiftOp.getValueType();
24774 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24775 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24779 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24780 TargetLowering::DAGCombinerInfo &DCI,
24781 const X86Subtarget *Subtarget) {
24782 if (DCI.isBeforeLegalizeOps())
24785 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24788 if (Subtarget->hasCMov())
24789 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24792 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24798 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24799 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24800 TargetLowering::DAGCombinerInfo &DCI,
24801 const X86Subtarget *Subtarget) {
24802 LoadSDNode *Ld = cast<LoadSDNode>(N);
24803 EVT RegVT = Ld->getValueType(0);
24804 EVT MemVT = Ld->getMemoryVT();
24806 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24808 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24809 // into two 16-byte operations.
24810 ISD::LoadExtType Ext = Ld->getExtensionType();
24812 unsigned AddressSpace = Ld->getAddressSpace();
24813 unsigned Alignment = Ld->getAlignment();
24814 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24815 Ext == ISD::NON_EXTLOAD &&
24816 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24817 AddressSpace, Alignment, &Fast) && !Fast) {
24818 unsigned NumElems = RegVT.getVectorNumElements();
24822 SDValue Ptr = Ld->getBasePtr();
24823 SDValue Increment =
24824 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24826 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24828 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24829 Ld->getPointerInfo(), Ld->isVolatile(),
24830 Ld->isNonTemporal(), Ld->isInvariant(),
24832 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24833 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24834 Ld->getPointerInfo(), Ld->isVolatile(),
24835 Ld->isNonTemporal(), Ld->isInvariant(),
24836 std::min(16U, Alignment));
24837 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24839 Load2.getValue(1));
24841 SDValue NewVec = DAG.getUNDEF(RegVT);
24842 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24843 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24844 return DCI.CombineTo(N, NewVec, TF, true);
24850 /// PerformMLOADCombine - Resolve extending loads
24851 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24852 TargetLowering::DAGCombinerInfo &DCI,
24853 const X86Subtarget *Subtarget) {
24854 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24855 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24858 EVT VT = Mld->getValueType(0);
24859 unsigned NumElems = VT.getVectorNumElements();
24860 EVT LdVT = Mld->getMemoryVT();
24863 assert(LdVT != VT && "Cannot extend to the same type");
24864 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24865 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24866 // From, To sizes and ElemCount must be pow of two
24867 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24868 "Unexpected size for extending masked load");
24870 unsigned SizeRatio = ToSz / FromSz;
24871 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24873 // Create a type on which we perform the shuffle
24874 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24875 LdVT.getScalarType(), NumElems*SizeRatio);
24876 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24878 // Convert Src0 value
24879 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24880 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24881 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24882 for (unsigned i = 0; i != NumElems; ++i)
24883 ShuffleVec[i] = i * SizeRatio;
24885 // Can't shuffle using an illegal type.
24886 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24887 "WideVecVT should be legal");
24888 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24889 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24891 // Prepare the new mask
24893 SDValue Mask = Mld->getMask();
24894 if (Mask.getValueType() == VT) {
24895 // Mask and original value have the same type
24896 NewMask = DAG.getBitcast(WideVecVT, Mask);
24897 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24898 for (unsigned i = 0; i != NumElems; ++i)
24899 ShuffleVec[i] = i * SizeRatio;
24900 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24901 ShuffleVec[i] = NumElems*SizeRatio;
24902 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24903 DAG.getConstant(0, dl, WideVecVT),
24907 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
24908 unsigned WidenNumElts = NumElems*SizeRatio;
24909 unsigned MaskNumElts = VT.getVectorNumElements();
24910 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
24913 unsigned NumConcat = WidenNumElts / MaskNumElts;
24914 SmallVector<SDValue, 16> Ops(NumConcat);
24915 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24917 for (unsigned i = 1; i != NumConcat; ++i)
24920 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24923 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
24924 Mld->getBasePtr(), NewMask, WideSrc0,
24925 Mld->getMemoryVT(), Mld->getMemOperand(),
24927 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
24928 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
24930 /// PerformMSTORECombine - Resolve truncating stores
24931 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
24932 const X86Subtarget *Subtarget) {
24933 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
24934 if (!Mst->isTruncatingStore())
24937 EVT VT = Mst->getValue().getValueType();
24938 unsigned NumElems = VT.getVectorNumElements();
24939 EVT StVT = Mst->getMemoryVT();
24942 assert(StVT != VT && "Cannot truncate to the same type");
24943 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24944 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24946 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24948 // The truncating store is legal in some cases. For example
24949 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
24950 // are designated for truncate store.
24951 // In this case we don't need any further transformations.
24952 if (TLI.isTruncStoreLegal(VT, StVT))
24955 // From, To sizes and ElemCount must be pow of two
24956 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24957 "Unexpected size for truncating masked store");
24958 // We are going to use the original vector elt for storing.
24959 // Accumulated smaller vector elements must be a multiple of the store size.
24960 assert (((NumElems * FromSz) % ToSz) == 0 &&
24961 "Unexpected ratio for truncating masked store");
24963 unsigned SizeRatio = FromSz / ToSz;
24964 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24966 // Create a type on which we perform the shuffle
24967 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24968 StVT.getScalarType(), NumElems*SizeRatio);
24970 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24972 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
24973 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24974 for (unsigned i = 0; i != NumElems; ++i)
24975 ShuffleVec[i] = i * SizeRatio;
24977 // Can't shuffle using an illegal type.
24978 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24979 "WideVecVT should be legal");
24981 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24982 DAG.getUNDEF(WideVecVT),
24986 SDValue Mask = Mst->getMask();
24987 if (Mask.getValueType() == VT) {
24988 // Mask and original value have the same type
24989 NewMask = DAG.getBitcast(WideVecVT, Mask);
24990 for (unsigned i = 0; i != NumElems; ++i)
24991 ShuffleVec[i] = i * SizeRatio;
24992 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
24993 ShuffleVec[i] = NumElems*SizeRatio;
24994 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
24995 DAG.getConstant(0, dl, WideVecVT),
24999 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25000 unsigned WidenNumElts = NumElems*SizeRatio;
25001 unsigned MaskNumElts = VT.getVectorNumElements();
25002 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25005 unsigned NumConcat = WidenNumElts / MaskNumElts;
25006 SmallVector<SDValue, 16> Ops(NumConcat);
25007 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25009 for (unsigned i = 1; i != NumConcat; ++i)
25012 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25015 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25016 NewMask, StVT, Mst->getMemOperand(), false);
25018 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25019 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25020 const X86Subtarget *Subtarget) {
25021 StoreSDNode *St = cast<StoreSDNode>(N);
25022 EVT VT = St->getValue().getValueType();
25023 EVT StVT = St->getMemoryVT();
25025 SDValue StoredVal = St->getOperand(1);
25026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25028 // If we are saving a concatenation of two XMM registers and 32-byte stores
25029 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25031 unsigned AddressSpace = St->getAddressSpace();
25032 unsigned Alignment = St->getAlignment();
25033 if (VT.is256BitVector() && StVT == VT &&
25034 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25035 AddressSpace, Alignment, &Fast) && !Fast) {
25036 unsigned NumElems = VT.getVectorNumElements();
25040 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25041 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25044 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25045 SDValue Ptr0 = St->getBasePtr();
25046 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25048 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25049 St->getPointerInfo(), St->isVolatile(),
25050 St->isNonTemporal(), Alignment);
25051 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25052 St->getPointerInfo(), St->isVolatile(),
25053 St->isNonTemporal(),
25054 std::min(16U, Alignment));
25055 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25058 // Optimize trunc store (of multiple scalars) to shuffle and store.
25059 // First, pack all of the elements in one place. Next, store to memory
25060 // in fewer chunks.
25061 if (St->isTruncatingStore() && VT.isVector()) {
25062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25063 unsigned NumElems = VT.getVectorNumElements();
25064 assert(StVT != VT && "Cannot truncate to the same type");
25065 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25066 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25068 // The truncating store is legal in some cases. For example
25069 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25070 // are designated for truncate store.
25071 // In this case we don't need any further transformations.
25072 if (TLI.isTruncStoreLegal(VT, StVT))
25075 // From, To sizes and ElemCount must be pow of two
25076 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25077 // We are going to use the original vector elt for storing.
25078 // Accumulated smaller vector elements must be a multiple of the store size.
25079 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25081 unsigned SizeRatio = FromSz / ToSz;
25083 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25085 // Create a type on which we perform the shuffle
25086 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25087 StVT.getScalarType(), NumElems*SizeRatio);
25089 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25091 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25092 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25093 for (unsigned i = 0; i != NumElems; ++i)
25094 ShuffleVec[i] = i * SizeRatio;
25096 // Can't shuffle using an illegal type.
25097 if (!TLI.isTypeLegal(WideVecVT))
25100 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25101 DAG.getUNDEF(WideVecVT),
25103 // At this point all of the data is stored at the bottom of the
25104 // register. We now need to save it to mem.
25106 // Find the largest store unit
25107 MVT StoreType = MVT::i8;
25108 for (MVT Tp : MVT::integer_valuetypes()) {
25109 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25113 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25114 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25115 (64 <= NumElems * ToSz))
25116 StoreType = MVT::f64;
25118 // Bitcast the original vector into a vector of store-size units
25119 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25120 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25121 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25122 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25123 SmallVector<SDValue, 8> Chains;
25124 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25125 TLI.getPointerTy(DAG.getDataLayout()));
25126 SDValue Ptr = St->getBasePtr();
25128 // Perform one or more big stores into memory.
25129 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25130 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25131 StoreType, ShuffWide,
25132 DAG.getIntPtrConstant(i, dl));
25133 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25134 St->getPointerInfo(), St->isVolatile(),
25135 St->isNonTemporal(), St->getAlignment());
25136 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25137 Chains.push_back(Ch);
25140 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25143 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25144 // the FP state in cases where an emms may be missing.
25145 // A preferable solution to the general problem is to figure out the right
25146 // places to insert EMMS. This qualifies as a quick hack.
25148 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25149 if (VT.getSizeInBits() != 64)
25152 const Function *F = DAG.getMachineFunction().getFunction();
25153 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25155 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25156 if ((VT.isVector() ||
25157 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25158 isa<LoadSDNode>(St->getValue()) &&
25159 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25160 St->getChain().hasOneUse() && !St->isVolatile()) {
25161 SDNode* LdVal = St->getValue().getNode();
25162 LoadSDNode *Ld = nullptr;
25163 int TokenFactorIndex = -1;
25164 SmallVector<SDValue, 8> Ops;
25165 SDNode* ChainVal = St->getChain().getNode();
25166 // Must be a store of a load. We currently handle two cases: the load
25167 // is a direct child, and it's under an intervening TokenFactor. It is
25168 // possible to dig deeper under nested TokenFactors.
25169 if (ChainVal == LdVal)
25170 Ld = cast<LoadSDNode>(St->getChain());
25171 else if (St->getValue().hasOneUse() &&
25172 ChainVal->getOpcode() == ISD::TokenFactor) {
25173 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25174 if (ChainVal->getOperand(i).getNode() == LdVal) {
25175 TokenFactorIndex = i;
25176 Ld = cast<LoadSDNode>(St->getValue());
25178 Ops.push_back(ChainVal->getOperand(i));
25182 if (!Ld || !ISD::isNormalLoad(Ld))
25185 // If this is not the MMX case, i.e. we are just turning i64 load/store
25186 // into f64 load/store, avoid the transformation if there are multiple
25187 // uses of the loaded value.
25188 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25193 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25194 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25196 if (Subtarget->is64Bit() || F64IsLegal) {
25197 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25198 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25199 Ld->getPointerInfo(), Ld->isVolatile(),
25200 Ld->isNonTemporal(), Ld->isInvariant(),
25201 Ld->getAlignment());
25202 SDValue NewChain = NewLd.getValue(1);
25203 if (TokenFactorIndex != -1) {
25204 Ops.push_back(NewChain);
25205 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25207 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25208 St->getPointerInfo(),
25209 St->isVolatile(), St->isNonTemporal(),
25210 St->getAlignment());
25213 // Otherwise, lower to two pairs of 32-bit loads / stores.
25214 SDValue LoAddr = Ld->getBasePtr();
25215 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25216 DAG.getConstant(4, LdDL, MVT::i32));
25218 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25219 Ld->getPointerInfo(),
25220 Ld->isVolatile(), Ld->isNonTemporal(),
25221 Ld->isInvariant(), Ld->getAlignment());
25222 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25223 Ld->getPointerInfo().getWithOffset(4),
25224 Ld->isVolatile(), Ld->isNonTemporal(),
25226 MinAlign(Ld->getAlignment(), 4));
25228 SDValue NewChain = LoLd.getValue(1);
25229 if (TokenFactorIndex != -1) {
25230 Ops.push_back(LoLd);
25231 Ops.push_back(HiLd);
25232 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25235 LoAddr = St->getBasePtr();
25236 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25237 DAG.getConstant(4, StDL, MVT::i32));
25239 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25240 St->getPointerInfo(),
25241 St->isVolatile(), St->isNonTemporal(),
25242 St->getAlignment());
25243 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25244 St->getPointerInfo().getWithOffset(4),
25246 St->isNonTemporal(),
25247 MinAlign(St->getAlignment(), 4));
25248 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25251 // This is similar to the above case, but here we handle a scalar 64-bit
25252 // integer store that is extracted from a vector on a 32-bit target.
25253 // If we have SSE2, then we can treat it like a floating-point double
25254 // to get past legalization. The execution dependencies fixup pass will
25255 // choose the optimal machine instruction for the store if this really is
25256 // an integer or v2f32 rather than an f64.
25257 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25258 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25259 SDValue OldExtract = St->getOperand(1);
25260 SDValue ExtOp0 = OldExtract.getOperand(0);
25261 unsigned VecSize = ExtOp0.getValueSizeInBits();
25262 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25263 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25264 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25265 BitCast, OldExtract.getOperand(1));
25266 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25267 St->getPointerInfo(), St->isVolatile(),
25268 St->isNonTemporal(), St->getAlignment());
25274 /// Return 'true' if this vector operation is "horizontal"
25275 /// and return the operands for the horizontal operation in LHS and RHS. A
25276 /// horizontal operation performs the binary operation on successive elements
25277 /// of its first operand, then on successive elements of its second operand,
25278 /// returning the resulting values in a vector. For example, if
25279 /// A = < float a0, float a1, float a2, float a3 >
25281 /// B = < float b0, float b1, float b2, float b3 >
25282 /// then the result of doing a horizontal operation on A and B is
25283 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25284 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25285 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25286 /// set to A, RHS to B, and the routine returns 'true'.
25287 /// Note that the binary operation should have the property that if one of the
25288 /// operands is UNDEF then the result is UNDEF.
25289 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25290 // Look for the following pattern: if
25291 // A = < float a0, float a1, float a2, float a3 >
25292 // B = < float b0, float b1, float b2, float b3 >
25294 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25295 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25296 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25297 // which is A horizontal-op B.
25299 // At least one of the operands should be a vector shuffle.
25300 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25301 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25304 MVT VT = LHS.getSimpleValueType();
25306 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25307 "Unsupported vector type for horizontal add/sub");
25309 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25310 // operate independently on 128-bit lanes.
25311 unsigned NumElts = VT.getVectorNumElements();
25312 unsigned NumLanes = VT.getSizeInBits()/128;
25313 unsigned NumLaneElts = NumElts / NumLanes;
25314 assert((NumLaneElts % 2 == 0) &&
25315 "Vector type should have an even number of elements in each lane");
25316 unsigned HalfLaneElts = NumLaneElts/2;
25318 // View LHS in the form
25319 // LHS = VECTOR_SHUFFLE A, B, LMask
25320 // If LHS is not a shuffle then pretend it is the shuffle
25321 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25322 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25325 SmallVector<int, 16> LMask(NumElts);
25326 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25327 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25328 A = LHS.getOperand(0);
25329 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25330 B = LHS.getOperand(1);
25331 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25332 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25334 if (LHS.getOpcode() != ISD::UNDEF)
25336 for (unsigned i = 0; i != NumElts; ++i)
25340 // Likewise, view RHS in the form
25341 // RHS = VECTOR_SHUFFLE C, D, RMask
25343 SmallVector<int, 16> RMask(NumElts);
25344 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25345 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25346 C = RHS.getOperand(0);
25347 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25348 D = RHS.getOperand(1);
25349 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25350 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25352 if (RHS.getOpcode() != ISD::UNDEF)
25354 for (unsigned i = 0; i != NumElts; ++i)
25358 // Check that the shuffles are both shuffling the same vectors.
25359 if (!(A == C && B == D) && !(A == D && B == C))
25362 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25363 if (!A.getNode() && !B.getNode())
25366 // If A and B occur in reverse order in RHS, then "swap" them (which means
25367 // rewriting the mask).
25369 ShuffleVectorSDNode::commuteMask(RMask);
25371 // At this point LHS and RHS are equivalent to
25372 // LHS = VECTOR_SHUFFLE A, B, LMask
25373 // RHS = VECTOR_SHUFFLE A, B, RMask
25374 // Check that the masks correspond to performing a horizontal operation.
25375 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25376 for (unsigned i = 0; i != NumLaneElts; ++i) {
25377 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25379 // Ignore any UNDEF components.
25380 if (LIdx < 0 || RIdx < 0 ||
25381 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25382 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25385 // Check that successive elements are being operated on. If not, this is
25386 // not a horizontal operation.
25387 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25388 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25389 if (!(LIdx == Index && RIdx == Index + 1) &&
25390 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25395 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25396 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25400 /// Do target-specific dag combines on floating point adds.
25401 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25402 const X86Subtarget *Subtarget) {
25403 EVT VT = N->getValueType(0);
25404 SDValue LHS = N->getOperand(0);
25405 SDValue RHS = N->getOperand(1);
25407 // Try to synthesize horizontal adds from adds of shuffles.
25408 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25409 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25410 isHorizontalBinOp(LHS, RHS, true))
25411 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25415 /// Do target-specific dag combines on floating point subs.
25416 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25417 const X86Subtarget *Subtarget) {
25418 EVT VT = N->getValueType(0);
25419 SDValue LHS = N->getOperand(0);
25420 SDValue RHS = N->getOperand(1);
25422 // Try to synthesize horizontal subs from subs of shuffles.
25423 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25424 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25425 isHorizontalBinOp(LHS, RHS, false))
25426 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25430 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25431 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25432 const X86Subtarget *Subtarget) {
25433 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25435 // F[X]OR(0.0, x) -> x
25436 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25437 if (C->getValueAPF().isPosZero())
25438 return N->getOperand(1);
25440 // F[X]OR(x, 0.0) -> x
25441 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25442 if (C->getValueAPF().isPosZero())
25443 return N->getOperand(0);
25445 EVT VT = N->getValueType(0);
25446 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25448 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25449 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25451 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25452 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25453 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25454 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25455 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25460 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25461 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25462 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25464 // Only perform optimizations if UnsafeMath is used.
25465 if (!DAG.getTarget().Options.UnsafeFPMath)
25468 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25469 // into FMINC and FMAXC, which are Commutative operations.
25470 unsigned NewOp = 0;
25471 switch (N->getOpcode()) {
25472 default: llvm_unreachable("unknown opcode");
25473 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25474 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25477 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25478 N->getOperand(0), N->getOperand(1));
25481 /// Do target-specific dag combines on X86ISD::FAND nodes.
25482 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25483 // FAND(0.0, x) -> 0.0
25484 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25485 if (C->getValueAPF().isPosZero())
25486 return N->getOperand(0);
25488 // FAND(x, 0.0) -> 0.0
25489 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25490 if (C->getValueAPF().isPosZero())
25491 return N->getOperand(1);
25496 /// Do target-specific dag combines on X86ISD::FANDN nodes
25497 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25498 // FANDN(0.0, x) -> x
25499 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25500 if (C->getValueAPF().isPosZero())
25501 return N->getOperand(1);
25503 // FANDN(x, 0.0) -> 0.0
25504 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25505 if (C->getValueAPF().isPosZero())
25506 return N->getOperand(1);
25511 static SDValue PerformBTCombine(SDNode *N,
25513 TargetLowering::DAGCombinerInfo &DCI) {
25514 // BT ignores high bits in the bit index operand.
25515 SDValue Op1 = N->getOperand(1);
25516 if (Op1.hasOneUse()) {
25517 unsigned BitWidth = Op1.getValueSizeInBits();
25518 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25519 APInt KnownZero, KnownOne;
25520 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25521 !DCI.isBeforeLegalizeOps());
25522 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25523 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25524 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25525 DCI.CommitTargetLoweringOpt(TLO);
25530 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25531 SDValue Op = N->getOperand(0);
25532 if (Op.getOpcode() == ISD::BITCAST)
25533 Op = Op.getOperand(0);
25534 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25535 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25536 VT.getVectorElementType().getSizeInBits() ==
25537 OpVT.getVectorElementType().getSizeInBits()) {
25538 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25543 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25544 const X86Subtarget *Subtarget) {
25545 EVT VT = N->getValueType(0);
25546 if (!VT.isVector())
25549 SDValue N0 = N->getOperand(0);
25550 SDValue N1 = N->getOperand(1);
25551 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25554 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25555 // both SSE and AVX2 since there is no sign-extended shift right
25556 // operation on a vector with 64-bit elements.
25557 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25558 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25559 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25560 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25561 SDValue N00 = N0.getOperand(0);
25563 // EXTLOAD has a better solution on AVX2,
25564 // it may be replaced with X86ISD::VSEXT node.
25565 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25566 if (!ISD::isNormalLoad(N00.getNode()))
25569 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25570 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25572 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25578 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25579 TargetLowering::DAGCombinerInfo &DCI,
25580 const X86Subtarget *Subtarget) {
25581 SDValue N0 = N->getOperand(0);
25582 EVT VT = N->getValueType(0);
25583 EVT SVT = VT.getScalarType();
25584 EVT InVT = N0.getValueType();
25585 EVT InSVT = InVT.getScalarType();
25588 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25589 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25590 // This exposes the sext to the sdivrem lowering, so that it directly extends
25591 // from AH (which we otherwise need to do contortions to access).
25592 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25593 InVT == MVT::i8 && VT == MVT::i32) {
25594 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25595 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25596 N0.getOperand(0), N0.getOperand(1));
25597 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25598 return R.getValue(1);
25601 if (!DCI.isBeforeLegalizeOps()) {
25602 if (InVT == MVT::i1) {
25603 SDValue Zero = DAG.getConstant(0, DL, VT);
25605 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25606 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25611 if (VT.isVector() && Subtarget->hasSSE2()) {
25612 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25613 EVT InVT = N.getValueType();
25614 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25615 Size / InVT.getScalarSizeInBits());
25616 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25617 DAG.getUNDEF(InVT));
25619 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25622 // If target-size is less than 128-bits, extend to a type that would extend
25623 // to 128 bits, extend that and extract the original target vector.
25624 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25625 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25626 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25627 unsigned Scale = 128 / VT.getSizeInBits();
25629 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25630 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25631 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25632 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25633 DAG.getIntPtrConstant(0, DL));
25636 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25637 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25638 if (VT.getSizeInBits() == 128 &&
25639 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25640 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25641 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25642 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25645 // On pre-AVX2 targets, split into 128-bit nodes of
25646 // ISD::SIGN_EXTEND_VECTOR_INREG.
25647 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25648 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25649 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25650 unsigned NumVecs = VT.getSizeInBits() / 128;
25651 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25652 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25653 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25655 SmallVector<SDValue, 8> Opnds;
25656 for (unsigned i = 0, Offset = 0; i != NumVecs;
25657 ++i, Offset += NumSubElts) {
25658 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25659 DAG.getIntPtrConstant(Offset, DL));
25660 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25661 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25662 Opnds.push_back(SrcVec);
25664 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25668 if (!Subtarget->hasFp256())
25671 if (VT.isVector() && VT.getSizeInBits() == 256)
25672 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25678 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25679 const X86Subtarget* Subtarget) {
25681 EVT VT = N->getValueType(0);
25683 // Let legalize expand this if it isn't a legal type yet.
25684 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25687 EVT ScalarVT = VT.getScalarType();
25688 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25689 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25690 !Subtarget->hasAVX512()))
25693 SDValue A = N->getOperand(0);
25694 SDValue B = N->getOperand(1);
25695 SDValue C = N->getOperand(2);
25697 bool NegA = (A.getOpcode() == ISD::FNEG);
25698 bool NegB = (B.getOpcode() == ISD::FNEG);
25699 bool NegC = (C.getOpcode() == ISD::FNEG);
25701 // Negative multiplication when NegA xor NegB
25702 bool NegMul = (NegA != NegB);
25704 A = A.getOperand(0);
25706 B = B.getOperand(0);
25708 C = C.getOperand(0);
25712 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25714 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25716 return DAG.getNode(Opcode, dl, VT, A, B, C);
25719 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25720 TargetLowering::DAGCombinerInfo &DCI,
25721 const X86Subtarget *Subtarget) {
25722 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25723 // (and (i32 x86isd::setcc_carry), 1)
25724 // This eliminates the zext. This transformation is necessary because
25725 // ISD::SETCC is always legalized to i8.
25727 SDValue N0 = N->getOperand(0);
25728 EVT VT = N->getValueType(0);
25730 if (N0.getOpcode() == ISD::AND &&
25732 N0.getOperand(0).hasOneUse()) {
25733 SDValue N00 = N0.getOperand(0);
25734 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25735 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25736 if (!C || C->getZExtValue() != 1)
25738 return DAG.getNode(ISD::AND, dl, VT,
25739 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25740 N00.getOperand(0), N00.getOperand(1)),
25741 DAG.getConstant(1, dl, VT));
25745 if (N0.getOpcode() == ISD::TRUNCATE &&
25747 N0.getOperand(0).hasOneUse()) {
25748 SDValue N00 = N0.getOperand(0);
25749 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25750 return DAG.getNode(ISD::AND, dl, VT,
25751 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25752 N00.getOperand(0), N00.getOperand(1)),
25753 DAG.getConstant(1, dl, VT));
25757 if (VT.is256BitVector())
25758 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25761 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25762 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25763 // This exposes the zext to the udivrem lowering, so that it directly extends
25764 // from AH (which we otherwise need to do contortions to access).
25765 if (N0.getOpcode() == ISD::UDIVREM &&
25766 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25767 (VT == MVT::i32 || VT == MVT::i64)) {
25768 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25769 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25770 N0.getOperand(0), N0.getOperand(1));
25771 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25772 return R.getValue(1);
25778 // Optimize x == -y --> x+y == 0
25779 // x != -y --> x+y != 0
25780 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25781 const X86Subtarget* Subtarget) {
25782 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25783 SDValue LHS = N->getOperand(0);
25784 SDValue RHS = N->getOperand(1);
25785 EVT VT = N->getValueType(0);
25788 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25790 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25791 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25792 LHS.getOperand(1));
25793 return DAG.getSetCC(DL, N->getValueType(0), addV,
25794 DAG.getConstant(0, DL, addV.getValueType()), CC);
25796 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25798 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25799 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25800 RHS.getOperand(1));
25801 return DAG.getSetCC(DL, N->getValueType(0), addV,
25802 DAG.getConstant(0, DL, addV.getValueType()), CC);
25805 if (VT.getScalarType() == MVT::i1 &&
25806 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25808 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25809 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25810 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25812 if (!IsSEXT0 || !IsVZero1) {
25813 // Swap the operands and update the condition code.
25814 std::swap(LHS, RHS);
25815 CC = ISD::getSetCCSwappedOperands(CC);
25817 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25818 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25819 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25822 if (IsSEXT0 && IsVZero1) {
25823 assert(VT == LHS.getOperand(0).getValueType() &&
25824 "Uexpected operand type");
25825 if (CC == ISD::SETGT)
25826 return DAG.getConstant(0, DL, VT);
25827 if (CC == ISD::SETLE)
25828 return DAG.getConstant(1, DL, VT);
25829 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25830 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25832 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25833 "Unexpected condition code!");
25834 return LHS.getOperand(0);
25841 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25842 SelectionDAG &DAG) {
25844 MVT VT = Load->getSimpleValueType(0);
25845 MVT EVT = VT.getVectorElementType();
25846 SDValue Addr = Load->getOperand(1);
25847 SDValue NewAddr = DAG.getNode(
25848 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25849 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25850 Addr.getSimpleValueType()));
25853 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25854 DAG.getMachineFunction().getMachineMemOperand(
25855 Load->getMemOperand(), 0, EVT.getStoreSize()));
25859 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25860 const X86Subtarget *Subtarget) {
25862 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25863 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25864 "X86insertps is only defined for v4x32");
25866 SDValue Ld = N->getOperand(1);
25867 if (MayFoldLoad(Ld)) {
25868 // Extract the countS bits from the immediate so we can get the proper
25869 // address when narrowing the vector load to a specific element.
25870 // When the second source op is a memory address, insertps doesn't use
25871 // countS and just gets an f32 from that address.
25872 unsigned DestIndex =
25873 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25875 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25877 // Create this as a scalar to vector to match the instruction pattern.
25878 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25879 // countS bits are ignored when loading from memory on insertps, which
25880 // means we don't need to explicitly set them to 0.
25881 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25882 LoadScalarToVector, N->getOperand(2));
25887 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25888 SDValue V0 = N->getOperand(0);
25889 SDValue V1 = N->getOperand(1);
25891 EVT VT = N->getValueType(0);
25893 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25894 // operands and changing the mask to 1. This saves us a bunch of
25895 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25896 // x86InstrInfo knows how to commute this back after instruction selection
25897 // if it would help register allocation.
25899 // TODO: If optimizing for size or a processor that doesn't suffer from
25900 // partial register update stalls, this should be transformed into a MOVSD
25901 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
25903 if (VT == MVT::v2f64)
25904 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
25905 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
25906 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
25907 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
25913 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25914 // as "sbb reg,reg", since it can be extended without zext and produces
25915 // an all-ones bit which is more useful than 0/1 in some cases.
25916 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25919 return DAG.getNode(ISD::AND, DL, VT,
25920 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25921 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25923 DAG.getConstant(1, DL, VT));
25924 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25925 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25926 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25927 DAG.getConstant(X86::COND_B, DL, MVT::i8),
25931 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25932 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25933 TargetLowering::DAGCombinerInfo &DCI,
25934 const X86Subtarget *Subtarget) {
25936 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25937 SDValue EFLAGS = N->getOperand(1);
25939 if (CC == X86::COND_A) {
25940 // Try to convert COND_A into COND_B in an attempt to facilitate
25941 // materializing "setb reg".
25943 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25944 // cannot take an immediate as its first operand.
25946 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25947 EFLAGS.getValueType().isInteger() &&
25948 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25949 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25950 EFLAGS.getNode()->getVTList(),
25951 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25952 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25953 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25957 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25958 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25960 if (CC == X86::COND_B)
25961 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25963 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25964 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25965 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25971 // Optimize branch condition evaluation.
25973 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25974 TargetLowering::DAGCombinerInfo &DCI,
25975 const X86Subtarget *Subtarget) {
25977 SDValue Chain = N->getOperand(0);
25978 SDValue Dest = N->getOperand(1);
25979 SDValue EFLAGS = N->getOperand(3);
25980 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25982 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
25983 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
25984 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25991 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25992 SelectionDAG &DAG) {
25993 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25994 // optimize away operation when it's from a constant.
25996 // The general transformation is:
25997 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25998 // AND(VECTOR_CMP(x,y), constant2)
25999 // constant2 = UNARYOP(constant)
26001 // Early exit if this isn't a vector operation, the operand of the
26002 // unary operation isn't a bitwise AND, or if the sizes of the operations
26003 // aren't the same.
26004 EVT VT = N->getValueType(0);
26005 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26006 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26007 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26010 // Now check that the other operand of the AND is a constant. We could
26011 // make the transformation for non-constant splats as well, but it's unclear
26012 // that would be a benefit as it would not eliminate any operations, just
26013 // perform one more step in scalar code before moving to the vector unit.
26014 if (BuildVectorSDNode *BV =
26015 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26016 // Bail out if the vector isn't a constant.
26017 if (!BV->isConstant())
26020 // Everything checks out. Build up the new and improved node.
26022 EVT IntVT = BV->getValueType(0);
26023 // Create a new constant of the appropriate type for the transformed
26025 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26026 // The AND node needs bitcasts to/from an integer vector type around it.
26027 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26028 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26029 N->getOperand(0)->getOperand(0), MaskConst);
26030 SDValue Res = DAG.getBitcast(VT, NewAnd);
26037 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26038 const X86Subtarget *Subtarget) {
26039 SDValue Op0 = N->getOperand(0);
26040 EVT VT = N->getValueType(0);
26041 EVT InVT = Op0.getValueType();
26042 EVT InSVT = InVT.getScalarType();
26043 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26045 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26046 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26047 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26049 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26050 InVT.getVectorNumElements());
26051 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26053 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26054 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26056 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26062 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26063 const X86Subtarget *Subtarget) {
26064 // First try to optimize away the conversion entirely when it's
26065 // conditionally from a constant. Vectors only.
26066 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26069 // Now move on to more general possibilities.
26070 SDValue Op0 = N->getOperand(0);
26071 EVT VT = N->getValueType(0);
26072 EVT InVT = Op0.getValueType();
26073 EVT InSVT = InVT.getScalarType();
26075 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26076 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26077 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26079 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26080 InVT.getVectorNumElements());
26081 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26082 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26085 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26086 // a 32-bit target where SSE doesn't support i64->FP operations.
26087 if (Op0.getOpcode() == ISD::LOAD) {
26088 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26089 EVT LdVT = Ld->getValueType(0);
26091 // This transformation is not supported if the result type is f16
26092 if (VT == MVT::f16)
26095 if (!Ld->isVolatile() && !VT.isVector() &&
26096 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26097 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26098 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26099 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26100 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26107 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26108 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26109 X86TargetLowering::DAGCombinerInfo &DCI) {
26110 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26111 // the result is either zero or one (depending on the input carry bit).
26112 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26113 if (X86::isZeroNode(N->getOperand(0)) &&
26114 X86::isZeroNode(N->getOperand(1)) &&
26115 // We don't have a good way to replace an EFLAGS use, so only do this when
26117 SDValue(N, 1).use_empty()) {
26119 EVT VT = N->getValueType(0);
26120 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26121 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26122 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26123 DAG.getConstant(X86::COND_B, DL,
26126 DAG.getConstant(1, DL, VT));
26127 return DCI.CombineTo(N, Res1, CarryOut);
26133 // fold (add Y, (sete X, 0)) -> adc 0, Y
26134 // (add Y, (setne X, 0)) -> sbb -1, Y
26135 // (sub (sete X, 0), Y) -> sbb 0, Y
26136 // (sub (setne X, 0), Y) -> adc -1, Y
26137 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26140 // Look through ZExts.
26141 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26142 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26145 SDValue SetCC = Ext.getOperand(0);
26146 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26149 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26150 if (CC != X86::COND_E && CC != X86::COND_NE)
26153 SDValue Cmp = SetCC.getOperand(1);
26154 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26155 !X86::isZeroNode(Cmp.getOperand(1)) ||
26156 !Cmp.getOperand(0).getValueType().isInteger())
26159 SDValue CmpOp0 = Cmp.getOperand(0);
26160 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26161 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26163 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26164 if (CC == X86::COND_NE)
26165 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26166 DL, OtherVal.getValueType(), OtherVal,
26167 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26169 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26170 DL, OtherVal.getValueType(), OtherVal,
26171 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26174 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26175 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26176 const X86Subtarget *Subtarget) {
26177 EVT VT = N->getValueType(0);
26178 SDValue Op0 = N->getOperand(0);
26179 SDValue Op1 = N->getOperand(1);
26181 // Try to synthesize horizontal adds from adds of shuffles.
26182 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26183 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26184 isHorizontalBinOp(Op0, Op1, true))
26185 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26187 return OptimizeConditionalInDecrement(N, DAG);
26190 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26191 const X86Subtarget *Subtarget) {
26192 SDValue Op0 = N->getOperand(0);
26193 SDValue Op1 = N->getOperand(1);
26195 // X86 can't encode an immediate LHS of a sub. See if we can push the
26196 // negation into a preceding instruction.
26197 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26198 // If the RHS of the sub is a XOR with one use and a constant, invert the
26199 // immediate. Then add one to the LHS of the sub so we can turn
26200 // X-Y -> X+~Y+1, saving one register.
26201 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26202 isa<ConstantSDNode>(Op1.getOperand(1))) {
26203 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26204 EVT VT = Op0.getValueType();
26205 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26207 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26208 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26209 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26213 // Try to synthesize horizontal adds from adds of shuffles.
26214 EVT VT = N->getValueType(0);
26215 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26216 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26217 isHorizontalBinOp(Op0, Op1, true))
26218 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26220 return OptimizeConditionalInDecrement(N, DAG);
26223 /// performVZEXTCombine - Performs build vector combines
26224 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26225 TargetLowering::DAGCombinerInfo &DCI,
26226 const X86Subtarget *Subtarget) {
26228 MVT VT = N->getSimpleValueType(0);
26229 SDValue Op = N->getOperand(0);
26230 MVT OpVT = Op.getSimpleValueType();
26231 MVT OpEltVT = OpVT.getVectorElementType();
26232 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26234 // (vzext (bitcast (vzext (x)) -> (vzext x)
26236 while (V.getOpcode() == ISD::BITCAST)
26237 V = V.getOperand(0);
26239 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26240 MVT InnerVT = V.getSimpleValueType();
26241 MVT InnerEltVT = InnerVT.getVectorElementType();
26243 // If the element sizes match exactly, we can just do one larger vzext. This
26244 // is always an exact type match as vzext operates on integer types.
26245 if (OpEltVT == InnerEltVT) {
26246 assert(OpVT == InnerVT && "Types must match for vzext!");
26247 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26250 // The only other way we can combine them is if only a single element of the
26251 // inner vzext is used in the input to the outer vzext.
26252 if (InnerEltVT.getSizeInBits() < InputBits)
26255 // In this case, the inner vzext is completely dead because we're going to
26256 // only look at bits inside of the low element. Just do the outer vzext on
26257 // a bitcast of the input to the inner.
26258 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26261 // Check if we can bypass extracting and re-inserting an element of an input
26262 // vector. Essentially:
26263 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26264 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26265 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26266 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26267 SDValue ExtractedV = V.getOperand(0);
26268 SDValue OrigV = ExtractedV.getOperand(0);
26269 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26270 if (ExtractIdx->getZExtValue() == 0) {
26271 MVT OrigVT = OrigV.getSimpleValueType();
26272 // Extract a subvector if necessary...
26273 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26274 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26275 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26276 OrigVT.getVectorNumElements() / Ratio);
26277 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26278 DAG.getIntPtrConstant(0, DL));
26280 Op = DAG.getBitcast(OpVT, OrigV);
26281 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26288 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26289 DAGCombinerInfo &DCI) const {
26290 SelectionDAG &DAG = DCI.DAG;
26291 switch (N->getOpcode()) {
26293 case ISD::EXTRACT_VECTOR_ELT:
26294 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26297 case X86ISD::SHRUNKBLEND:
26298 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26299 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26300 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26301 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26302 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26303 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26304 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26307 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26308 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26309 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26310 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26311 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26312 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26313 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26314 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26315 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26316 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26317 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26318 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26320 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26322 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26323 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26324 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26325 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26326 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26327 case ISD::ANY_EXTEND:
26328 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26329 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26330 case ISD::SIGN_EXTEND_INREG:
26331 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26332 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26333 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26334 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26335 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26336 case X86ISD::SHUFP: // Handle all target specific shuffles
26337 case X86ISD::PALIGNR:
26338 case X86ISD::UNPCKH:
26339 case X86ISD::UNPCKL:
26340 case X86ISD::MOVHLPS:
26341 case X86ISD::MOVLHPS:
26342 case X86ISD::PSHUFB:
26343 case X86ISD::PSHUFD:
26344 case X86ISD::PSHUFHW:
26345 case X86ISD::PSHUFLW:
26346 case X86ISD::MOVSS:
26347 case X86ISD::MOVSD:
26348 case X86ISD::VPERMILPI:
26349 case X86ISD::VPERM2X128:
26350 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26351 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26352 case X86ISD::INSERTPS: {
26353 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26354 return PerformINSERTPSCombine(N, DAG, Subtarget);
26357 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26363 /// isTypeDesirableForOp - Return true if the target has native support for
26364 /// the specified value type and it is 'desirable' to use the type for the
26365 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26366 /// instruction encodings are longer and some i16 instructions are slow.
26367 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26368 if (!isTypeLegal(VT))
26370 if (VT != MVT::i16)
26377 case ISD::SIGN_EXTEND:
26378 case ISD::ZERO_EXTEND:
26379 case ISD::ANY_EXTEND:
26392 /// IsDesirableToPromoteOp - This method query the target whether it is
26393 /// beneficial for dag combiner to promote the specified node. If true, it
26394 /// should return the desired promotion type by reference.
26395 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26396 EVT VT = Op.getValueType();
26397 if (VT != MVT::i16)
26400 bool Promote = false;
26401 bool Commute = false;
26402 switch (Op.getOpcode()) {
26405 LoadSDNode *LD = cast<LoadSDNode>(Op);
26406 // If the non-extending load has a single use and it's not live out, then it
26407 // might be folded.
26408 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26409 Op.hasOneUse()*/) {
26410 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26411 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26412 // The only case where we'd want to promote LOAD (rather then it being
26413 // promoted as an operand is when it's only use is liveout.
26414 if (UI->getOpcode() != ISD::CopyToReg)
26421 case ISD::SIGN_EXTEND:
26422 case ISD::ZERO_EXTEND:
26423 case ISD::ANY_EXTEND:
26428 SDValue N0 = Op.getOperand(0);
26429 // Look out for (store (shl (load), x)).
26430 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26443 SDValue N0 = Op.getOperand(0);
26444 SDValue N1 = Op.getOperand(1);
26445 if (!Commute && MayFoldLoad(N1))
26447 // Avoid disabling potential load folding opportunities.
26448 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26450 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26460 //===----------------------------------------------------------------------===//
26461 // X86 Inline Assembly Support
26462 //===----------------------------------------------------------------------===//
26464 // Helper to match a string separated by whitespace.
26465 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26466 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26468 for (StringRef Piece : Pieces) {
26469 if (!S.startswith(Piece)) // Check if the piece matches.
26472 S = S.substr(Piece.size());
26473 StringRef::size_type Pos = S.find_first_not_of(" \t");
26474 if (Pos == 0) // We matched a prefix.
26483 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26485 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26486 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26487 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26488 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26490 if (AsmPieces.size() == 3)
26492 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26499 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26500 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26502 std::string AsmStr = IA->getAsmString();
26504 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26505 if (!Ty || Ty->getBitWidth() % 16 != 0)
26508 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26509 SmallVector<StringRef, 4> AsmPieces;
26510 SplitString(AsmStr, AsmPieces, ";\n");
26512 switch (AsmPieces.size()) {
26513 default: return false;
26515 // FIXME: this should verify that we are targeting a 486 or better. If not,
26516 // we will turn this bswap into something that will be lowered to logical
26517 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26518 // lower so don't worry about this.
26520 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26521 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26522 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26523 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26524 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26525 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26526 // No need to check constraints, nothing other than the equivalent of
26527 // "=r,0" would be valid here.
26528 return IntrinsicLowering::LowerToByteSwap(CI);
26531 // rorw $$8, ${0:w} --> llvm.bswap.i16
26532 if (CI->getType()->isIntegerTy(16) &&
26533 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26534 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26535 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26537 StringRef ConstraintsStr = IA->getConstraintString();
26538 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26539 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26540 if (clobbersFlagRegisters(AsmPieces))
26541 return IntrinsicLowering::LowerToByteSwap(CI);
26545 if (CI->getType()->isIntegerTy(32) &&
26546 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26547 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26548 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26549 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26551 StringRef ConstraintsStr = IA->getConstraintString();
26552 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26553 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26554 if (clobbersFlagRegisters(AsmPieces))
26555 return IntrinsicLowering::LowerToByteSwap(CI);
26558 if (CI->getType()->isIntegerTy(64)) {
26559 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26560 if (Constraints.size() >= 2 &&
26561 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26562 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26563 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26564 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26565 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26566 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26567 return IntrinsicLowering::LowerToByteSwap(CI);
26575 /// getConstraintType - Given a constraint letter, return the type of
26576 /// constraint it is for this target.
26577 X86TargetLowering::ConstraintType
26578 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26579 if (Constraint.size() == 1) {
26580 switch (Constraint[0]) {
26591 return C_RegisterClass;
26615 return TargetLowering::getConstraintType(Constraint);
26618 /// Examine constraint type and operand type and determine a weight value.
26619 /// This object must already have been set up with the operand type
26620 /// and the current alternative constraint selected.
26621 TargetLowering::ConstraintWeight
26622 X86TargetLowering::getSingleConstraintMatchWeight(
26623 AsmOperandInfo &info, const char *constraint) const {
26624 ConstraintWeight weight = CW_Invalid;
26625 Value *CallOperandVal = info.CallOperandVal;
26626 // If we don't have a value, we can't do a match,
26627 // but allow it at the lowest weight.
26628 if (!CallOperandVal)
26630 Type *type = CallOperandVal->getType();
26631 // Look at the constraint type.
26632 switch (*constraint) {
26634 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26645 if (CallOperandVal->getType()->isIntegerTy())
26646 weight = CW_SpecificReg;
26651 if (type->isFloatingPointTy())
26652 weight = CW_SpecificReg;
26655 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26656 weight = CW_SpecificReg;
26660 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26661 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26662 weight = CW_Register;
26665 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26666 if (C->getZExtValue() <= 31)
26667 weight = CW_Constant;
26671 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26672 if (C->getZExtValue() <= 63)
26673 weight = CW_Constant;
26677 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26678 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26679 weight = CW_Constant;
26683 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26684 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26685 weight = CW_Constant;
26689 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26690 if (C->getZExtValue() <= 3)
26691 weight = CW_Constant;
26695 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26696 if (C->getZExtValue() <= 0xff)
26697 weight = CW_Constant;
26702 if (isa<ConstantFP>(CallOperandVal)) {
26703 weight = CW_Constant;
26707 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26708 if ((C->getSExtValue() >= -0x80000000LL) &&
26709 (C->getSExtValue() <= 0x7fffffffLL))
26710 weight = CW_Constant;
26714 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26715 if (C->getZExtValue() <= 0xffffffff)
26716 weight = CW_Constant;
26723 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26724 /// with another that has more specific requirements based on the type of the
26725 /// corresponding operand.
26726 const char *X86TargetLowering::
26727 LowerXConstraint(EVT ConstraintVT) const {
26728 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26729 // 'f' like normal targets.
26730 if (ConstraintVT.isFloatingPoint()) {
26731 if (Subtarget->hasSSE2())
26733 if (Subtarget->hasSSE1())
26737 return TargetLowering::LowerXConstraint(ConstraintVT);
26740 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26741 /// vector. If it is invalid, don't add anything to Ops.
26742 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26743 std::string &Constraint,
26744 std::vector<SDValue>&Ops,
26745 SelectionDAG &DAG) const {
26748 // Only support length 1 constraints for now.
26749 if (Constraint.length() > 1) return;
26751 char ConstraintLetter = Constraint[0];
26752 switch (ConstraintLetter) {
26755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26756 if (C->getZExtValue() <= 31) {
26757 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26758 Op.getValueType());
26764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26765 if (C->getZExtValue() <= 63) {
26766 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26767 Op.getValueType());
26773 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26774 if (isInt<8>(C->getSExtValue())) {
26775 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26776 Op.getValueType());
26782 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26783 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26784 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26785 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26786 Op.getValueType());
26792 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26793 if (C->getZExtValue() <= 3) {
26794 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26795 Op.getValueType());
26801 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26802 if (C->getZExtValue() <= 255) {
26803 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26804 Op.getValueType());
26810 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26811 if (C->getZExtValue() <= 127) {
26812 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26813 Op.getValueType());
26819 // 32-bit signed value
26820 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26821 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26822 C->getSExtValue())) {
26823 // Widen to 64 bits here to get it sign extended.
26824 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26827 // FIXME gcc accepts some relocatable values here too, but only in certain
26828 // memory models; it's complicated.
26833 // 32-bit unsigned value
26834 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26835 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26836 C->getZExtValue())) {
26837 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26838 Op.getValueType());
26842 // FIXME gcc accepts some relocatable values here too, but only in certain
26843 // memory models; it's complicated.
26847 // Literal immediates are always ok.
26848 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26849 // Widen to 64 bits here to get it sign extended.
26850 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26854 // In any sort of PIC mode addresses need to be computed at runtime by
26855 // adding in a register or some sort of table lookup. These can't
26856 // be used as immediates.
26857 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26860 // If we are in non-pic codegen mode, we allow the address of a global (with
26861 // an optional displacement) to be used with 'i'.
26862 GlobalAddressSDNode *GA = nullptr;
26863 int64_t Offset = 0;
26865 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26867 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26868 Offset += GA->getOffset();
26870 } else if (Op.getOpcode() == ISD::ADD) {
26871 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26872 Offset += C->getZExtValue();
26873 Op = Op.getOperand(0);
26876 } else if (Op.getOpcode() == ISD::SUB) {
26877 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26878 Offset += -C->getZExtValue();
26879 Op = Op.getOperand(0);
26884 // Otherwise, this isn't something we can handle, reject it.
26888 const GlobalValue *GV = GA->getGlobal();
26889 // If we require an extra load to get this address, as in PIC mode, we
26890 // can't accept it.
26891 if (isGlobalStubReference(
26892 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26895 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26896 GA->getValueType(0), Offset);
26901 if (Result.getNode()) {
26902 Ops.push_back(Result);
26905 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26908 std::pair<unsigned, const TargetRegisterClass *>
26909 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
26910 StringRef Constraint,
26912 // First, see if this is a constraint that directly corresponds to an LLVM
26914 if (Constraint.size() == 1) {
26915 // GCC Constraint Letters
26916 switch (Constraint[0]) {
26918 // TODO: Slight differences here in allocation order and leaving
26919 // RIP in the class. Do they matter any more here than they do
26920 // in the normal allocation?
26921 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26922 if (Subtarget->is64Bit()) {
26923 if (VT == MVT::i32 || VT == MVT::f32)
26924 return std::make_pair(0U, &X86::GR32RegClass);
26925 if (VT == MVT::i16)
26926 return std::make_pair(0U, &X86::GR16RegClass);
26927 if (VT == MVT::i8 || VT == MVT::i1)
26928 return std::make_pair(0U, &X86::GR8RegClass);
26929 if (VT == MVT::i64 || VT == MVT::f64)
26930 return std::make_pair(0U, &X86::GR64RegClass);
26933 // 32-bit fallthrough
26934 case 'Q': // Q_REGS
26935 if (VT == MVT::i32 || VT == MVT::f32)
26936 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26937 if (VT == MVT::i16)
26938 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26939 if (VT == MVT::i8 || VT == MVT::i1)
26940 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26941 if (VT == MVT::i64)
26942 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26944 case 'r': // GENERAL_REGS
26945 case 'l': // INDEX_REGS
26946 if (VT == MVT::i8 || VT == MVT::i1)
26947 return std::make_pair(0U, &X86::GR8RegClass);
26948 if (VT == MVT::i16)
26949 return std::make_pair(0U, &X86::GR16RegClass);
26950 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26951 return std::make_pair(0U, &X86::GR32RegClass);
26952 return std::make_pair(0U, &X86::GR64RegClass);
26953 case 'R': // LEGACY_REGS
26954 if (VT == MVT::i8 || VT == MVT::i1)
26955 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26956 if (VT == MVT::i16)
26957 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26958 if (VT == MVT::i32 || !Subtarget->is64Bit())
26959 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26960 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26961 case 'f': // FP Stack registers.
26962 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26963 // value to the correct fpstack register class.
26964 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26965 return std::make_pair(0U, &X86::RFP32RegClass);
26966 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26967 return std::make_pair(0U, &X86::RFP64RegClass);
26968 return std::make_pair(0U, &X86::RFP80RegClass);
26969 case 'y': // MMX_REGS if MMX allowed.
26970 if (!Subtarget->hasMMX()) break;
26971 return std::make_pair(0U, &X86::VR64RegClass);
26972 case 'Y': // SSE_REGS if SSE2 allowed
26973 if (!Subtarget->hasSSE2()) break;
26975 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26976 if (!Subtarget->hasSSE1()) break;
26978 switch (VT.SimpleTy) {
26980 // Scalar SSE types.
26983 return std::make_pair(0U, &X86::FR32RegClass);
26986 return std::make_pair(0U, &X86::FR64RegClass);
26994 return std::make_pair(0U, &X86::VR128RegClass);
27002 return std::make_pair(0U, &X86::VR256RegClass);
27007 return std::make_pair(0U, &X86::VR512RegClass);
27013 // Use the default implementation in TargetLowering to convert the register
27014 // constraint into a member of a register class.
27015 std::pair<unsigned, const TargetRegisterClass*> Res;
27016 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27018 // Not found as a standard register?
27020 // Map st(0) -> st(7) -> ST0
27021 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27022 tolower(Constraint[1]) == 's' &&
27023 tolower(Constraint[2]) == 't' &&
27024 Constraint[3] == '(' &&
27025 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27026 Constraint[5] == ')' &&
27027 Constraint[6] == '}') {
27029 Res.first = X86::FP0+Constraint[4]-'0';
27030 Res.second = &X86::RFP80RegClass;
27034 // GCC allows "st(0)" to be called just plain "st".
27035 if (StringRef("{st}").equals_lower(Constraint)) {
27036 Res.first = X86::FP0;
27037 Res.second = &X86::RFP80RegClass;
27042 if (StringRef("{flags}").equals_lower(Constraint)) {
27043 Res.first = X86::EFLAGS;
27044 Res.second = &X86::CCRRegClass;
27048 // 'A' means EAX + EDX.
27049 if (Constraint == "A") {
27050 Res.first = X86::EAX;
27051 Res.second = &X86::GR32_ADRegClass;
27057 // Otherwise, check to see if this is a register class of the wrong value
27058 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27059 // turn into {ax},{dx}.
27060 // MVT::Other is used to specify clobber names.
27061 if (Res.second->hasType(VT) || VT == MVT::Other)
27062 return Res; // Correct type already, nothing to do.
27064 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27065 // return "eax". This should even work for things like getting 64bit integer
27066 // registers when given an f64 type.
27067 const TargetRegisterClass *Class = Res.second;
27068 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27069 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27070 unsigned Size = VT.getSizeInBits();
27071 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27072 : Size == 16 ? MVT::i16
27073 : Size == 32 ? MVT::i32
27074 : Size == 64 ? MVT::i64
27076 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27078 Res.first = DestReg;
27079 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27080 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27081 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27082 : &X86::GR64RegClass;
27083 assert(Res.second->contains(Res.first) && "Register in register class");
27085 // No register found/type mismatch.
27087 Res.second = nullptr;
27089 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27090 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27091 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27092 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27093 Class == &X86::VR512RegClass) {
27094 // Handle references to XMM physical registers that got mapped into the
27095 // wrong class. This can happen with constraints like {xmm0} where the
27096 // target independent register mapper will just pick the first match it can
27097 // find, ignoring the required type.
27099 if (VT == MVT::f32 || VT == MVT::i32)
27100 Res.second = &X86::FR32RegClass;
27101 else if (VT == MVT::f64 || VT == MVT::i64)
27102 Res.second = &X86::FR64RegClass;
27103 else if (X86::VR128RegClass.hasType(VT))
27104 Res.second = &X86::VR128RegClass;
27105 else if (X86::VR256RegClass.hasType(VT))
27106 Res.second = &X86::VR256RegClass;
27107 else if (X86::VR512RegClass.hasType(VT))
27108 Res.second = &X86::VR512RegClass;
27110 // Type mismatch and not a clobber: Return an error;
27112 Res.second = nullptr;
27119 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27120 const AddrMode &AM, Type *Ty,
27121 unsigned AS) const {
27122 // Scaling factors are not free at all.
27123 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27124 // will take 2 allocations in the out of order engine instead of 1
27125 // for plain addressing mode, i.e. inst (reg1).
27127 // vaddps (%rsi,%drx), %ymm0, %ymm1
27128 // Requires two allocations (one for the load, one for the computation)
27130 // vaddps (%rsi), %ymm0, %ymm1
27131 // Requires just 1 allocation, i.e., freeing allocations for other operations
27132 // and having less micro operations to execute.
27134 // For some X86 architectures, this is even worse because for instance for
27135 // stores, the complex addressing mode forces the instruction to use the
27136 // "load" ports instead of the dedicated "store" port.
27137 // E.g., on Haswell:
27138 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27139 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27140 if (isLegalAddressingMode(DL, AM, Ty, AS))
27141 // Scale represents reg2 * scale, thus account for 1
27142 // as soon as we use a second register.
27143 return AM.Scale != 0;
27147 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27148 // Integer division on x86 is expensive. However, when aggressively optimizing
27149 // for code size, we prefer to use a div instruction, as it is usually smaller
27150 // than the alternative sequence.
27151 // The exception to this is vector division. Since x86 doesn't have vector
27152 // integer division, leaving the division as-is is a loss even in terms of
27153 // size, because it will have to be scalarized, while the alternative code
27154 // sequence can be performed in vector form.
27155 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27156 Attribute::MinSize);
27157 return OptSize && !VT.isVector();