1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetWindows())
193 return new X86WindowsTargetObjectFile();
194 if (Subtarget->isTargetCOFF())
195 return new TargetLoweringObjectFileCOFF();
196 llvm_unreachable("unknown subtarget type");
199 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
200 : TargetLowering(TM, createTLOF(TM)) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird, it always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit since we have so many registers use the ILP scheduler, for
234 // 32-bit code use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2
247 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
248 addBypassSlowDiv(32, 8);
249 if (Subtarget->is64Bit())
250 addBypassSlowDiv(64, 16);
253 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
254 // Setup Windows compiler runtime calls.
255 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
256 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
257 setLibcallName(RTLIB::SREM_I64, "_allrem");
258 setLibcallName(RTLIB::UREM_I64, "_aullrem");
259 setLibcallName(RTLIB::MUL_I64, "_allmul");
260 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
266 // The _ftol2 runtime function has an unusual calling conv, which
267 // is modeled by a special pseudo-instruction.
268 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
270 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
271 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
274 if (Subtarget->isTargetDarwin()) {
275 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
276 setUseUnderscoreSetJmp(false);
277 setUseUnderscoreLongJmp(false);
278 } else if (Subtarget->isTargetMingw()) {
279 // MS runtime is weird: it exports _setjmp, but longjmp!
280 setUseUnderscoreSetJmp(true);
281 setUseUnderscoreLongJmp(false);
283 setUseUnderscoreSetJmp(true);
284 setUseUnderscoreLongJmp(true);
287 // Set up the register classes.
288 addRegisterClass(MVT::i8, &X86::GR8RegClass);
289 addRegisterClass(MVT::i16, &X86::GR16RegClass);
290 addRegisterClass(MVT::i32, &X86::GR32RegClass);
291 if (Subtarget->is64Bit())
292 addRegisterClass(MVT::i64, &X86::GR64RegClass);
294 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
296 // We don't accept any truncstore of integer registers.
297 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
302 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
304 // SETOEQ and SETUNE require checking two conditions.
305 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
312 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
314 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
316 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
318 if (Subtarget->is64Bit()) {
319 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
320 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
321 } else if (!TM.Options.UseSoftFloat) {
322 // We have an algorithm for SSE2->double, and we turn this into a
323 // 64-bit FILD followed by conditional FADD for other targets.
324 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 // We have an algorithm for SSE2, and we turn this into a 64-bit
326 // FILD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
330 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
332 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
333 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
335 if (!TM.Options.UseSoftFloat) {
336 // SSE has no i16 to fp conversion, only i32
337 if (X86ScalarSSEf32) {
338 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
339 // f32 and f64 cases are Legal, f80 case is not
340 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
350 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
351 // are Legal, f80 is custom lowered.
352 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
355 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
357 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
358 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
360 if (X86ScalarSSEf32) {
361 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
362 // f32 and f64 cases are Legal, f80 case is not
363 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 // Handle FP_TO_UINT by promoting the destination to a larger signed
371 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
373 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
375 if (Subtarget->is64Bit()) {
376 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
377 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
378 } else if (!TM.Options.UseSoftFloat) {
379 // Since AVX is a superset of SSE3, only check for SSE here.
380 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
381 // Expand FP_TO_UINT into a select.
382 // FIXME: We would like to use a Custom expander here eventually to do
383 // the optimal thing for SSE vs. the default expansion in the legalizer.
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
386 // With SSE3 we can use fisttpll to convert to a signed i64; without
387 // SSE, we're stuck with a fistpll.
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
391 if (isTargetFTOL()) {
392 // Use the _ftol2 runtime function, which has a pseudo-instruction
393 // to handle its weird calling convention.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
397 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
398 if (!X86ScalarSSEf64) {
399 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
400 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
401 if (Subtarget->is64Bit()) {
402 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
403 // Without SSE, i64->f64 goes through memory.
404 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
408 // Scalar integer divide and remainder are lowered to use operations that
409 // produce two results, to match the available instructions. This exposes
410 // the two-result form to trivial CSE, which is able to combine x/y and x%y
411 // into a single instruction.
413 // Scalar integer multiply-high is also lowered to use two-result
414 // operations, to match the available instructions. However, plain multiply
415 // (low) operations are left as Legal, as there are single-result
416 // instructions for this in x86. Using the two-result multiply instructions
417 // when both high and low results are needed must be arranged by dagcombine.
418 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
420 setOperationAction(ISD::MULHS, VT, Expand);
421 setOperationAction(ISD::MULHU, VT, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
423 setOperationAction(ISD::UDIV, VT, Expand);
424 setOperationAction(ISD::SREM, VT, Expand);
425 setOperationAction(ISD::UREM, VT, Expand);
427 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
428 setOperationAction(ISD::ADDC, VT, Custom);
429 setOperationAction(ISD::ADDE, VT, Custom);
430 setOperationAction(ISD::SUBC, VT, Custom);
431 setOperationAction(ISD::SUBE, VT, Custom);
434 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
435 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
436 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
438 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
443 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
444 if (Subtarget->is64Bit())
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
448 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
449 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f32 , Expand);
451 setOperationAction(ISD::FREM , MVT::f64 , Expand);
452 setOperationAction(ISD::FREM , MVT::f80 , Expand);
453 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
455 // Promote the i8 variants and force them on up to i32 which has a shorter
457 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
459 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
460 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
461 if (Subtarget->hasBMI()) {
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
467 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
468 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
473 if (Subtarget->hasLZCNT()) {
474 // When promoting the i8 variants, force them to i32 for a shorter
476 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
485 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
487 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
491 if (Subtarget->is64Bit()) {
492 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
497 if (Subtarget->hasPOPCNT()) {
498 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
500 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
502 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
507 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
508 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
510 // These should be promoted to a larger select which is supported.
511 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
512 // X86 wants to expand cmov itself.
513 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
515 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
518 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
521 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
524 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
525 if (Subtarget->is64Bit()) {
526 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
527 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
529 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
530 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
531 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
532 // support continuation, user-level threading, and etc.. As a result, no
533 // other SjLj exception interfaces are implemented and please don't build
534 // your own exception handling based on them.
535 // LLVM/Clang supports zero-cost DWARF exception handling.
536 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
537 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
540 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
541 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
544 if (Subtarget->is64Bit())
545 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
546 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
547 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
550 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
551 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
552 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
553 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
555 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
556 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
558 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
562 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
565 if (Subtarget->hasSSE1())
566 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
568 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
570 // Expand certain atomics
571 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
573 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
575 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
578 if (!Subtarget->is64Bit()) {
579 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
590 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
593 if (Subtarget->hasCmpxchg16b()) {
594 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
597 // FIXME - use subtarget debug flags
598 if (!Subtarget->isTargetDarwin() &&
599 !Subtarget->isTargetELF() &&
600 !Subtarget->isTargetCygMing()) {
601 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
604 if (Subtarget->is64Bit()) {
605 setExceptionPointerRegister(X86::RAX);
606 setExceptionSelectorRegister(X86::RDX);
608 setExceptionPointerRegister(X86::EAX);
609 setExceptionSelectorRegister(X86::EDX);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
612 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
614 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
617 setOperationAction(ISD::TRAP, MVT::Other, Legal);
618 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
620 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
621 setOperationAction(ISD::VASTART , MVT::Other, Custom);
622 setOperationAction(ISD::VAEND , MVT::Other, Expand);
623 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
624 // TargetInfo::X86_64ABIBuiltinVaList
625 setOperationAction(ISD::VAARG , MVT::Other, Custom);
626 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
628 // TargetInfo::CharPtrBuiltinVaList
629 setOperationAction(ISD::VAARG , MVT::Other, Expand);
630 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
633 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
634 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
636 if (Subtarget->isOSWindows() && !Subtarget->isTargetMacho())
637 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
638 MVT::i64 : MVT::i32, Custom);
639 else if (TM.Options.EnableSegmentedStacks)
640 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
641 MVT::i64 : MVT::i32, Custom);
643 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
644 MVT::i64 : MVT::i32, Expand);
646 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
647 // f32 and f64 use SSE.
648 // Set up the FP register classes.
649 addRegisterClass(MVT::f32, &X86::FR32RegClass);
650 addRegisterClass(MVT::f64, &X86::FR64RegClass);
652 // Use ANDPD to simulate FABS.
653 setOperationAction(ISD::FABS , MVT::f64, Custom);
654 setOperationAction(ISD::FABS , MVT::f32, Custom);
656 // Use XORP to simulate FNEG.
657 setOperationAction(ISD::FNEG , MVT::f64, Custom);
658 setOperationAction(ISD::FNEG , MVT::f32, Custom);
660 // Use ANDPD and ORPD to simulate FCOPYSIGN.
661 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
664 // Lower this to FGETSIGNx86 plus an AND.
665 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
666 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
668 // We don't support sin/cos/fmod
669 setOperationAction(ISD::FSIN , MVT::f64, Expand);
670 setOperationAction(ISD::FCOS , MVT::f64, Expand);
671 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
672 setOperationAction(ISD::FSIN , MVT::f32, Expand);
673 setOperationAction(ISD::FCOS , MVT::f32, Expand);
674 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
676 // Expand FP immediates into loads from the stack, except for the special
678 addLegalFPImmediate(APFloat(+0.0)); // xorpd
679 addLegalFPImmediate(APFloat(+0.0f)); // xorps
680 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
681 // Use SSE for f32, x87 for f64.
682 // Set up the FP register classes.
683 addRegisterClass(MVT::f32, &X86::FR32RegClass);
684 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
686 // Use ANDPS to simulate FABS.
687 setOperationAction(ISD::FABS , MVT::f32, Custom);
689 // Use XORP to simulate FNEG.
690 setOperationAction(ISD::FNEG , MVT::f32, Custom);
692 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
694 // Use ANDPS and ORPS to simulate FCOPYSIGN.
695 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
696 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
698 // We don't support sin/cos/fmod
699 setOperationAction(ISD::FSIN , MVT::f32, Expand);
700 setOperationAction(ISD::FCOS , MVT::f32, Expand);
701 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
703 // Special cases we handle for FP constants.
704 addLegalFPImmediate(APFloat(+0.0f)); // xorps
705 addLegalFPImmediate(APFloat(+0.0)); // FLD0
706 addLegalFPImmediate(APFloat(+1.0)); // FLD1
707 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
708 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
710 if (!TM.Options.UnsafeFPMath) {
711 setOperationAction(ISD::FSIN , MVT::f64, Expand);
712 setOperationAction(ISD::FCOS , MVT::f64, Expand);
713 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
715 } else if (!TM.Options.UseSoftFloat) {
716 // f32 and f64 in x87.
717 // Set up the FP register classes.
718 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
719 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
721 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
722 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
724 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FSIN , MVT::f32, Expand);
729 setOperationAction(ISD::FCOS , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f32, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
734 addLegalFPImmediate(APFloat(+0.0)); // FLD0
735 addLegalFPImmediate(APFloat(+1.0)); // FLD1
736 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
737 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
738 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
739 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
740 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
741 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
744 // We don't support FMA.
745 setOperationAction(ISD::FMA, MVT::f64, Expand);
746 setOperationAction(ISD::FMA, MVT::f32, Expand);
748 // Long double always uses X87.
749 if (!TM.Options.UseSoftFloat) {
750 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
751 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
752 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
754 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
755 addLegalFPImmediate(TmpFlt); // FLD0
757 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
760 APFloat TmpFlt2(+1.0);
761 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
763 addLegalFPImmediate(TmpFlt2); // FLD1
764 TmpFlt2.changeSign();
765 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
768 if (!TM.Options.UnsafeFPMath) {
769 setOperationAction(ISD::FSIN , MVT::f80, Expand);
770 setOperationAction(ISD::FCOS , MVT::f80, Expand);
771 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
774 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
775 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
776 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
777 setOperationAction(ISD::FRINT, MVT::f80, Expand);
778 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
779 setOperationAction(ISD::FMA, MVT::f80, Expand);
782 // Always use a library call for pow.
783 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
785 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
787 setOperationAction(ISD::FLOG, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
789 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP, MVT::f80, Expand);
791 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
793 // First set operation action for all vector types to either promote
794 // (for widening) or expand (for scalarization). Then we will selectively
795 // turn on ones that can be effectively codegen'd.
796 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
797 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
798 MVT VT = (MVT::SimpleValueType)i;
799 setOperationAction(ISD::ADD , VT, Expand);
800 setOperationAction(ISD::SUB , VT, Expand);
801 setOperationAction(ISD::FADD, VT, Expand);
802 setOperationAction(ISD::FNEG, VT, Expand);
803 setOperationAction(ISD::FSUB, VT, Expand);
804 setOperationAction(ISD::MUL , VT, Expand);
805 setOperationAction(ISD::FMUL, VT, Expand);
806 setOperationAction(ISD::SDIV, VT, Expand);
807 setOperationAction(ISD::UDIV, VT, Expand);
808 setOperationAction(ISD::FDIV, VT, Expand);
809 setOperationAction(ISD::SREM, VT, Expand);
810 setOperationAction(ISD::UREM, VT, Expand);
811 setOperationAction(ISD::LOAD, VT, Expand);
812 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
813 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
815 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
817 setOperationAction(ISD::FABS, VT, Expand);
818 setOperationAction(ISD::FSIN, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FCOS, VT, Expand);
821 setOperationAction(ISD::FSINCOS, VT, Expand);
822 setOperationAction(ISD::FREM, VT, Expand);
823 setOperationAction(ISD::FMA, VT, Expand);
824 setOperationAction(ISD::FPOWI, VT, Expand);
825 setOperationAction(ISD::FSQRT, VT, Expand);
826 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
827 setOperationAction(ISD::FFLOOR, VT, Expand);
828 setOperationAction(ISD::FCEIL, VT, Expand);
829 setOperationAction(ISD::FTRUNC, VT, Expand);
830 setOperationAction(ISD::FRINT, VT, Expand);
831 setOperationAction(ISD::FNEARBYINT, VT, Expand);
832 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
834 setOperationAction(ISD::SDIVREM, VT, Expand);
835 setOperationAction(ISD::UDIVREM, VT, Expand);
836 setOperationAction(ISD::FPOW, VT, Expand);
837 setOperationAction(ISD::CTPOP, VT, Expand);
838 setOperationAction(ISD::CTTZ, VT, Expand);
839 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::CTLZ, VT, Expand);
841 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
842 setOperationAction(ISD::SHL, VT, Expand);
843 setOperationAction(ISD::SRA, VT, Expand);
844 setOperationAction(ISD::SRL, VT, Expand);
845 setOperationAction(ISD::ROTL, VT, Expand);
846 setOperationAction(ISD::ROTR, VT, Expand);
847 setOperationAction(ISD::BSWAP, VT, Expand);
848 setOperationAction(ISD::SETCC, VT, Expand);
849 setOperationAction(ISD::FLOG, VT, Expand);
850 setOperationAction(ISD::FLOG2, VT, Expand);
851 setOperationAction(ISD::FLOG10, VT, Expand);
852 setOperationAction(ISD::FEXP, VT, Expand);
853 setOperationAction(ISD::FEXP2, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::VSELECT, VT, Expand);
864 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
865 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
866 setTruncStoreAction(VT,
867 (MVT::SimpleValueType)InnerVT, Expand);
868 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
870 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
873 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
874 // with -msoft-float, disable use of MMX as well.
875 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
876 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
877 // No operations on x86mmx supported, everything uses intrinsics.
880 // MMX-sized vectors (other than x86mmx) are expected to be expanded
881 // into smaller operations.
882 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
883 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
884 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
885 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
886 setOperationAction(ISD::AND, MVT::v8i8, Expand);
887 setOperationAction(ISD::AND, MVT::v4i16, Expand);
888 setOperationAction(ISD::AND, MVT::v2i32, Expand);
889 setOperationAction(ISD::AND, MVT::v1i64, Expand);
890 setOperationAction(ISD::OR, MVT::v8i8, Expand);
891 setOperationAction(ISD::OR, MVT::v4i16, Expand);
892 setOperationAction(ISD::OR, MVT::v2i32, Expand);
893 setOperationAction(ISD::OR, MVT::v1i64, Expand);
894 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
895 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
896 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
897 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
901 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
903 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
904 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
905 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
906 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
910 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
912 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
913 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
915 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
916 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
917 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
918 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
919 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
920 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
921 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
922 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
926 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
930 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
932 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
933 // registers cannot be used even for integer operations.
934 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
935 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
936 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
937 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
939 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
940 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
941 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
942 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
943 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
944 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
945 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
946 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
947 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
948 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
949 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
950 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
951 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
952 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
953 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
954 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
955 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
956 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
959 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
960 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
961 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
970 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
971 MVT VT = (MVT::SimpleValueType)i;
972 // Do not attempt to custom lower non-power-of-2 vectors
973 if (!isPowerOf2_32(VT.getVectorNumElements()))
975 // Do not attempt to custom lower non-128-bit vectors
976 if (!VT.is128BitVector())
978 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
979 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
980 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
984 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
986 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
990 if (Subtarget->is64Bit()) {
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
995 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
999 // Do not attempt to promote non-128-bit vectors
1000 if (!VT.is128BitVector())
1003 setOperationAction(ISD::AND, VT, Promote);
1004 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1005 setOperationAction(ISD::OR, VT, Promote);
1006 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1007 setOperationAction(ISD::XOR, VT, Promote);
1008 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1009 setOperationAction(ISD::LOAD, VT, Promote);
1010 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1011 setOperationAction(ISD::SELECT, VT, Promote);
1012 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1015 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1017 // Custom lower v2i64 and v2f64 selects.
1018 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1020 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1021 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1024 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1027 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1028 // As there is no 64-bit GPR available, we need build a special custom
1029 // sequence to convert from v2i32 to v2f32.
1030 if (!Subtarget->is64Bit())
1031 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1034 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1036 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1039 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1040 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1041 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1042 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1043 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1045 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1046 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1047 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1048 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1051 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1056 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1062 // FIXME: Do we need to handle scalar-to-vector here?
1063 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1071 // i8 and i16 vectors are custom , because the source register and source
1072 // source memory operand types are not the same width. f32 vectors are
1073 // custom since the immediate controlling the insert encodes additional
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1078 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1083 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1085 // FIXME: these should be Legal but thats only for the case where
1086 // the index is constant. For now custom expand to deal with that.
1087 if (Subtarget->is64Bit()) {
1088 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1089 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1093 if (Subtarget->hasSSE2()) {
1094 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1095 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1097 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1098 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1100 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1101 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1103 // In the customized shift lowering, the legal cases in AVX2 will be
1105 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1114 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1117 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1118 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1123 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1125 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1127 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1129 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1139 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1142 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1152 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1153 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1155 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1157 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1160 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1163 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1165 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1167 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1168 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1170 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1173 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1174 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1187 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1200 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1203 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1205 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1206 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1209 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1210 setOperationAction(ISD::FMA, MVT::f32, Legal);
1211 setOperationAction(ISD::FMA, MVT::f64, Legal);
1214 if (Subtarget->hasInt256()) {
1215 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1216 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1217 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1218 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1220 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1221 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1222 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1223 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1225 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1226 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1227 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1228 // Don't lower v32i8 because there is no 128-bit byte mul
1230 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1232 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1234 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1235 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1236 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1237 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1244 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1247 // Don't lower v32i8 because there is no 128-bit byte mul
1250 // In the customized shift lowering, the legal cases in AVX2 will be
1252 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1253 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1255 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1256 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1258 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1260 // Custom lower several nodes for 256-bit types.
1261 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1262 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1263 MVT VT = (MVT::SimpleValueType)i;
1265 // Extract subvector is special because the value type
1266 // (result) is 128-bit but the source is 256-bit wide.
1267 if (VT.is128BitVector())
1268 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1270 // Do not attempt to custom lower other non-256-bit vectors
1271 if (!VT.is256BitVector())
1274 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1275 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1276 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1278 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1279 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1280 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1283 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1284 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1285 MVT VT = (MVT::SimpleValueType)i;
1287 // Do not attempt to promote non-256-bit vectors
1288 if (!VT.is256BitVector())
1291 setOperationAction(ISD::AND, VT, Promote);
1292 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1293 setOperationAction(ISD::OR, VT, Promote);
1294 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1295 setOperationAction(ISD::XOR, VT, Promote);
1296 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1297 setOperationAction(ISD::LOAD, VT, Promote);
1298 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1299 setOperationAction(ISD::SELECT, VT, Promote);
1300 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1304 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1305 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1308 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1310 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1311 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1312 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1314 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1315 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1316 setOperationAction(ISD::XOR, MVT::i1, Legal);
1317 setOperationAction(ISD::OR, MVT::i1, Legal);
1318 setOperationAction(ISD::AND, MVT::i1, Legal);
1319 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1322 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1323 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1324 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1326 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1333 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1339 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1340 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1341 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1343 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1344 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1345 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1346 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1347 if (Subtarget->is64Bit()) {
1348 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1350 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1359 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1360 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1362 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1364 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1365 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1366 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1367 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1368 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1369 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1373 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1374 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1377 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1378 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1379 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1380 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1381 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1383 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1384 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1386 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1390 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1391 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1392 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1393 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1396 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1399 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1400 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1402 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1404 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1405 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1407 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1408 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1410 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1411 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1413 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1414 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1415 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1416 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1417 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1418 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1420 // Custom lower several nodes.
1421 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1422 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1423 MVT VT = (MVT::SimpleValueType)i;
1425 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1426 // Extract subvector is special because the value type
1427 // (result) is 256/128-bit but the source is 512-bit wide.
1428 if (VT.is128BitVector() || VT.is256BitVector())
1429 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1431 if (VT.getVectorElementType() == MVT::i1)
1432 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1434 // Do not attempt to custom lower other non-512-bit vectors
1435 if (!VT.is512BitVector())
1438 if ( EltSize >= 32) {
1439 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1440 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1441 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1442 setOperationAction(ISD::VSELECT, VT, Legal);
1443 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1444 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1445 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1448 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1449 MVT VT = (MVT::SimpleValueType)i;
1451 // Do not attempt to promote non-256-bit vectors
1452 if (!VT.is512BitVector())
1455 setOperationAction(ISD::SELECT, VT, Promote);
1456 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1460 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1461 // of this type with custom code.
1462 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1463 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1464 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1468 // We want to custom lower some of our intrinsics.
1469 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1470 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1471 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1473 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1474 // handle type legalization for these operations here.
1476 // FIXME: We really should do custom legalization for addition and
1477 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1478 // than generic legalization for 64-bit multiplication-with-overflow, though.
1479 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1480 // Add/Sub/Mul with overflow operations are custom lowered.
1482 setOperationAction(ISD::SADDO, VT, Custom);
1483 setOperationAction(ISD::UADDO, VT, Custom);
1484 setOperationAction(ISD::SSUBO, VT, Custom);
1485 setOperationAction(ISD::USUBO, VT, Custom);
1486 setOperationAction(ISD::SMULO, VT, Custom);
1487 setOperationAction(ISD::UMULO, VT, Custom);
1490 // There are no 8-bit 3-address imul/mul instructions
1491 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1492 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1494 if (!Subtarget->is64Bit()) {
1495 // These libcalls are not available in 32-bit.
1496 setLibcallName(RTLIB::SHL_I128, 0);
1497 setLibcallName(RTLIB::SRL_I128, 0);
1498 setLibcallName(RTLIB::SRA_I128, 0);
1501 // Combine sin / cos into one node or libcall if possible.
1502 if (Subtarget->hasSinCos()) {
1503 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1504 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1505 if (Subtarget->isTargetDarwin()) {
1506 // For MacOSX, we don't want to the normal expansion of a libcall to
1507 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1509 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1510 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1514 // We have target-specific dag combine patterns for the following nodes:
1515 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1516 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1517 setTargetDAGCombine(ISD::VSELECT);
1518 setTargetDAGCombine(ISD::SELECT);
1519 setTargetDAGCombine(ISD::SHL);
1520 setTargetDAGCombine(ISD::SRA);
1521 setTargetDAGCombine(ISD::SRL);
1522 setTargetDAGCombine(ISD::OR);
1523 setTargetDAGCombine(ISD::AND);
1524 setTargetDAGCombine(ISD::ADD);
1525 setTargetDAGCombine(ISD::FADD);
1526 setTargetDAGCombine(ISD::FSUB);
1527 setTargetDAGCombine(ISD::FMA);
1528 setTargetDAGCombine(ISD::SUB);
1529 setTargetDAGCombine(ISD::LOAD);
1530 setTargetDAGCombine(ISD::STORE);
1531 setTargetDAGCombine(ISD::ZERO_EXTEND);
1532 setTargetDAGCombine(ISD::ANY_EXTEND);
1533 setTargetDAGCombine(ISD::SIGN_EXTEND);
1534 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1535 setTargetDAGCombine(ISD::TRUNCATE);
1536 setTargetDAGCombine(ISD::SINT_TO_FP);
1537 setTargetDAGCombine(ISD::SETCC);
1538 if (Subtarget->is64Bit())
1539 setTargetDAGCombine(ISD::MUL);
1540 setTargetDAGCombine(ISD::XOR);
1542 computeRegisterProperties();
1544 // On Darwin, -Os means optimize for size without hurting performance,
1545 // do not reduce the limit.
1546 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1547 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1548 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1549 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1550 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1551 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1552 setPrefLoopAlignment(4); // 2^4 bytes.
1554 // Predictable cmov don't hurt on atom because it's in-order.
1555 PredictableSelectIsExpensive = !Subtarget->isAtom();
1557 setPrefFunctionAlignment(4); // 2^4 bytes.
1560 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1562 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1564 if (Subtarget->hasAVX512())
1565 switch(VT.getVectorNumElements()) {
1566 case 8: return MVT::v8i1;
1567 case 16: return MVT::v16i1;
1570 return VT.changeVectorElementTypeToInteger();
1573 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1574 /// the desired ByVal argument alignment.
1575 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1578 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1579 if (VTy->getBitWidth() == 128)
1581 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1582 unsigned EltAlign = 0;
1583 getMaxByValAlign(ATy->getElementType(), EltAlign);
1584 if (EltAlign > MaxAlign)
1585 MaxAlign = EltAlign;
1586 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1587 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1588 unsigned EltAlign = 0;
1589 getMaxByValAlign(STy->getElementType(i), EltAlign);
1590 if (EltAlign > MaxAlign)
1591 MaxAlign = EltAlign;
1598 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1599 /// function arguments in the caller parameter area. For X86, aggregates
1600 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1601 /// are at 4-byte boundaries.
1602 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1603 if (Subtarget->is64Bit()) {
1604 // Max of 8 and alignment of type.
1605 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1612 if (Subtarget->hasSSE1())
1613 getMaxByValAlign(Ty, Align);
1617 /// getOptimalMemOpType - Returns the target specific optimal type for load
1618 /// and store operations as a result of memset, memcpy, and memmove
1619 /// lowering. If DstAlign is zero that means it's safe to destination
1620 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1621 /// means there isn't a need to check it against alignment requirement,
1622 /// probably because the source does not need to be loaded. If 'IsMemset' is
1623 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1624 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1625 /// source is constant so it does not need to be loaded.
1626 /// It returns EVT::Other if the type should be determined using generic
1627 /// target-independent logic.
1629 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1630 unsigned DstAlign, unsigned SrcAlign,
1631 bool IsMemset, bool ZeroMemset,
1633 MachineFunction &MF) const {
1634 const Function *F = MF.getFunction();
1635 if ((!IsMemset || ZeroMemset) &&
1636 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1637 Attribute::NoImplicitFloat)) {
1639 (Subtarget->isUnalignedMemAccessFast() ||
1640 ((DstAlign == 0 || DstAlign >= 16) &&
1641 (SrcAlign == 0 || SrcAlign >= 16)))) {
1643 if (Subtarget->hasInt256())
1645 if (Subtarget->hasFp256())
1648 if (Subtarget->hasSSE2())
1650 if (Subtarget->hasSSE1())
1652 } else if (!MemcpyStrSrc && Size >= 8 &&
1653 !Subtarget->is64Bit() &&
1654 Subtarget->hasSSE2()) {
1655 // Do not use f64 to lower memcpy if source is string constant. It's
1656 // better to use i32 to avoid the loads.
1660 if (Subtarget->is64Bit() && Size >= 8)
1665 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1667 return X86ScalarSSEf32;
1668 else if (VT == MVT::f64)
1669 return X86ScalarSSEf64;
1674 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1676 *Fast = Subtarget->isUnalignedMemAccessFast();
1680 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1681 /// current function. The returned value is a member of the
1682 /// MachineJumpTableInfo::JTEntryKind enum.
1683 unsigned X86TargetLowering::getJumpTableEncoding() const {
1684 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1686 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1687 Subtarget->isPICStyleGOT())
1688 return MachineJumpTableInfo::EK_Custom32;
1690 // Otherwise, use the normal jump table encoding heuristics.
1691 return TargetLowering::getJumpTableEncoding();
1695 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1696 const MachineBasicBlock *MBB,
1697 unsigned uid,MCContext &Ctx) const{
1698 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1699 Subtarget->isPICStyleGOT());
1700 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1702 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1703 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1706 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1708 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1709 SelectionDAG &DAG) const {
1710 if (!Subtarget->is64Bit())
1711 // This doesn't have SDLoc associated with it, but is not really the
1712 // same as a Register.
1713 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1717 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1718 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1720 const MCExpr *X86TargetLowering::
1721 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1722 MCContext &Ctx) const {
1723 // X86-64 uses RIP relative addressing based on the jump table label.
1724 if (Subtarget->isPICStyleRIPRel())
1725 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1727 // Otherwise, the reference is relative to the PIC base.
1728 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1731 // FIXME: Why this routine is here? Move to RegInfo!
1732 std::pair<const TargetRegisterClass*, uint8_t>
1733 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1734 const TargetRegisterClass *RRC = 0;
1736 switch (VT.SimpleTy) {
1738 return TargetLowering::findRepresentativeClass(VT);
1739 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1740 RRC = Subtarget->is64Bit() ?
1741 (const TargetRegisterClass*)&X86::GR64RegClass :
1742 (const TargetRegisterClass*)&X86::GR32RegClass;
1745 RRC = &X86::VR64RegClass;
1747 case MVT::f32: case MVT::f64:
1748 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1749 case MVT::v4f32: case MVT::v2f64:
1750 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1752 RRC = &X86::VR128RegClass;
1755 return std::make_pair(RRC, Cost);
1758 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1759 unsigned &Offset) const {
1760 if (!Subtarget->isTargetLinux())
1763 if (Subtarget->is64Bit()) {
1764 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1766 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1778 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1779 unsigned DestAS) const {
1780 assert(SrcAS != DestAS && "Expected different address spaces!");
1782 return SrcAS < 256 && DestAS < 256;
1785 //===----------------------------------------------------------------------===//
1786 // Return Value Calling Convention Implementation
1787 //===----------------------------------------------------------------------===//
1789 #include "X86GenCallingConv.inc"
1792 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1793 MachineFunction &MF, bool isVarArg,
1794 const SmallVectorImpl<ISD::OutputArg> &Outs,
1795 LLVMContext &Context) const {
1796 SmallVector<CCValAssign, 16> RVLocs;
1797 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1799 return CCInfo.CheckReturn(Outs, RetCC_X86);
1802 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1803 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1808 X86TargetLowering::LowerReturn(SDValue Chain,
1809 CallingConv::ID CallConv, bool isVarArg,
1810 const SmallVectorImpl<ISD::OutputArg> &Outs,
1811 const SmallVectorImpl<SDValue> &OutVals,
1812 SDLoc dl, SelectionDAG &DAG) const {
1813 MachineFunction &MF = DAG.getMachineFunction();
1814 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1816 SmallVector<CCValAssign, 16> RVLocs;
1817 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1818 RVLocs, *DAG.getContext());
1819 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1822 SmallVector<SDValue, 6> RetOps;
1823 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1824 // Operand #1 = Bytes To Pop
1825 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1828 // Copy the result values into the output registers.
1829 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1830 CCValAssign &VA = RVLocs[i];
1831 assert(VA.isRegLoc() && "Can only return in registers!");
1832 SDValue ValToCopy = OutVals[i];
1833 EVT ValVT = ValToCopy.getValueType();
1835 // Promote values to the appropriate types
1836 if (VA.getLocInfo() == CCValAssign::SExt)
1837 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1838 else if (VA.getLocInfo() == CCValAssign::ZExt)
1839 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1840 else if (VA.getLocInfo() == CCValAssign::AExt)
1841 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1842 else if (VA.getLocInfo() == CCValAssign::BCvt)
1843 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1845 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1846 "Unexpected FP-extend for return value.");
1848 // If this is x86-64, and we disabled SSE, we can't return FP values,
1849 // or SSE or MMX vectors.
1850 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1851 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1852 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1853 report_fatal_error("SSE register return with SSE disabled");
1855 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1856 // llvm-gcc has never done it right and no one has noticed, so this
1857 // should be OK for now.
1858 if (ValVT == MVT::f64 &&
1859 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1860 report_fatal_error("SSE2 register return with SSE2 disabled");
1862 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1863 // the RET instruction and handled by the FP Stackifier.
1864 if (VA.getLocReg() == X86::ST0 ||
1865 VA.getLocReg() == X86::ST1) {
1866 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1867 // change the value to the FP stack register class.
1868 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1869 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1870 RetOps.push_back(ValToCopy);
1871 // Don't emit a copytoreg.
1875 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1876 // which is returned in RAX / RDX.
1877 if (Subtarget->is64Bit()) {
1878 if (ValVT == MVT::x86mmx) {
1879 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1880 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1881 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1883 // If we don't have SSE2 available, convert to v4f32 so the generated
1884 // register is legal.
1885 if (!Subtarget->hasSSE2())
1886 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1891 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1892 Flag = Chain.getValue(1);
1893 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1896 // The x86-64 ABIs require that for returning structs by value we copy
1897 // the sret argument into %rax/%eax (depending on ABI) for the return.
1898 // Win32 requires us to put the sret argument to %eax as well.
1899 // We saved the argument into a virtual register in the entry block,
1900 // so now we copy the value out and into %rax/%eax.
1901 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1902 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1903 MachineFunction &MF = DAG.getMachineFunction();
1904 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1905 unsigned Reg = FuncInfo->getSRetReturnReg();
1907 "SRetReturnReg should have been set in LowerFormalArguments().");
1908 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1911 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1912 X86::RAX : X86::EAX;
1913 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1914 Flag = Chain.getValue(1);
1916 // RAX/EAX now acts like a return value.
1917 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1920 RetOps[0] = Chain; // Update chain.
1922 // Add the flag if we have it.
1924 RetOps.push_back(Flag);
1926 return DAG.getNode(X86ISD::RET_FLAG, dl,
1927 MVT::Other, &RetOps[0], RetOps.size());
1930 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1931 if (N->getNumValues() != 1)
1933 if (!N->hasNUsesOfValue(1, 0))
1936 SDValue TCChain = Chain;
1937 SDNode *Copy = *N->use_begin();
1938 if (Copy->getOpcode() == ISD::CopyToReg) {
1939 // If the copy has a glue operand, we conservatively assume it isn't safe to
1940 // perform a tail call.
1941 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1943 TCChain = Copy->getOperand(0);
1944 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1947 bool HasRet = false;
1948 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1950 if (UI->getOpcode() != X86ISD::RET_FLAG)
1963 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1964 ISD::NodeType ExtendKind) const {
1966 // TODO: Is this also valid on 32-bit?
1967 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1968 ReturnMVT = MVT::i8;
1970 ReturnMVT = MVT::i32;
1972 MVT MinVT = getRegisterType(ReturnMVT);
1973 return VT.bitsLT(MinVT) ? MinVT : VT;
1976 /// LowerCallResult - Lower the result values of a call into the
1977 /// appropriate copies out of appropriate physical registers.
1980 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1981 CallingConv::ID CallConv, bool isVarArg,
1982 const SmallVectorImpl<ISD::InputArg> &Ins,
1983 SDLoc dl, SelectionDAG &DAG,
1984 SmallVectorImpl<SDValue> &InVals) const {
1986 // Assign locations to each value returned by this call.
1987 SmallVector<CCValAssign, 16> RVLocs;
1988 bool Is64Bit = Subtarget->is64Bit();
1989 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1990 getTargetMachine(), RVLocs, *DAG.getContext());
1991 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1993 // Copy all of the result registers out of their specified physreg.
1994 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 EVT CopyVT = VA.getValVT();
1998 // If this is x86-64, and we disabled SSE, we can't return FP values
1999 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2000 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2001 report_fatal_error("SSE register return with SSE disabled");
2006 // If this is a call to a function that returns an fp value on the floating
2007 // point stack, we must guarantee the value is popped from the stack, so
2008 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2009 // if the return value is not used. We use the FpPOP_RETVAL instruction
2011 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2012 // If we prefer to use the value in xmm registers, copy it out as f80 and
2013 // use a truncate to move it from fp stack reg to xmm reg.
2014 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2015 SDValue Ops[] = { Chain, InFlag };
2016 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2017 MVT::Other, MVT::Glue, Ops), 1);
2018 Val = Chain.getValue(0);
2020 // Round the f80 to the right size, which also moves it to the appropriate
2022 if (CopyVT != VA.getValVT())
2023 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2024 // This truncation won't change the value.
2025 DAG.getIntPtrConstant(1));
2027 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2028 CopyVT, InFlag).getValue(1);
2029 Val = Chain.getValue(0);
2031 InFlag = Chain.getValue(2);
2032 InVals.push_back(Val);
2038 //===----------------------------------------------------------------------===//
2039 // C & StdCall & Fast Calling Convention implementation
2040 //===----------------------------------------------------------------------===//
2041 // StdCall calling convention seems to be standard for many Windows' API
2042 // routines and around. It differs from C calling convention just a little:
2043 // callee should clean up the stack, not caller. Symbols should be also
2044 // decorated in some fancy way :) It doesn't support any vector arguments.
2045 // For info on fast calling convention see Fast Calling Convention (tail call)
2046 // implementation LowerX86_32FastCCCallTo.
2048 /// CallIsStructReturn - Determines whether a call uses struct return
2050 enum StructReturnType {
2055 static StructReturnType
2056 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2058 return NotStructReturn;
2060 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2061 if (!Flags.isSRet())
2062 return NotStructReturn;
2063 if (Flags.isInReg())
2064 return RegStructReturn;
2065 return StackStructReturn;
2068 /// ArgsAreStructReturn - Determines whether a function uses struct
2069 /// return semantics.
2070 static StructReturnType
2071 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2073 return NotStructReturn;
2075 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2076 if (!Flags.isSRet())
2077 return NotStructReturn;
2078 if (Flags.isInReg())
2079 return RegStructReturn;
2080 return StackStructReturn;
2083 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2084 /// by "Src" to address "Dst" with size and alignment information specified by
2085 /// the specific parameter attribute. The copy will be passed as a byval
2086 /// function parameter.
2088 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2089 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2091 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2093 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2094 /*isVolatile*/false, /*AlwaysInline=*/true,
2095 MachinePointerInfo(), MachinePointerInfo());
2098 /// IsTailCallConvention - Return true if the calling convention is one that
2099 /// supports tail call optimization.
2100 static bool IsTailCallConvention(CallingConv::ID CC) {
2101 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2102 CC == CallingConv::HiPE);
2105 /// \brief Return true if the calling convention is a C calling convention.
2106 static bool IsCCallConvention(CallingConv::ID CC) {
2107 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2108 CC == CallingConv::X86_64_SysV);
2111 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2112 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2116 CallingConv::ID CalleeCC = CS.getCallingConv();
2117 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2123 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2124 /// a tailcall target by changing its ABI.
2125 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2126 bool GuaranteedTailCallOpt) {
2127 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2131 X86TargetLowering::LowerMemArgument(SDValue Chain,
2132 CallingConv::ID CallConv,
2133 const SmallVectorImpl<ISD::InputArg> &Ins,
2134 SDLoc dl, SelectionDAG &DAG,
2135 const CCValAssign &VA,
2136 MachineFrameInfo *MFI,
2138 // Create the nodes corresponding to a load from this parameter slot.
2139 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2140 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2141 getTargetMachine().Options.GuaranteedTailCallOpt);
2142 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2145 // If value is passed by pointer we have address passed instead of the value
2147 if (VA.getLocInfo() == CCValAssign::Indirect)
2148 ValVT = VA.getLocVT();
2150 ValVT = VA.getValVT();
2152 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2153 // changed with more analysis.
2154 // In case of tail call optimization mark all arguments mutable. Since they
2155 // could be overwritten by lowering of arguments in case of a tail call.
2156 if (Flags.isByVal()) {
2157 unsigned Bytes = Flags.getByValSize();
2158 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2159 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2160 return DAG.getFrameIndex(FI, getPointerTy());
2162 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2163 VA.getLocMemOffset(), isImmutable);
2164 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2165 return DAG.getLoad(ValVT, dl, Chain, FIN,
2166 MachinePointerInfo::getFixedStack(FI),
2167 false, false, false, 0);
2172 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2173 CallingConv::ID CallConv,
2175 const SmallVectorImpl<ISD::InputArg> &Ins,
2178 SmallVectorImpl<SDValue> &InVals)
2180 MachineFunction &MF = DAG.getMachineFunction();
2181 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2183 const Function* Fn = MF.getFunction();
2184 if (Fn->hasExternalLinkage() &&
2185 Subtarget->isTargetCygMing() &&
2186 Fn->getName() == "main")
2187 FuncInfo->setForceFramePointer(true);
2189 MachineFrameInfo *MFI = MF.getFrameInfo();
2190 bool Is64Bit = Subtarget->is64Bit();
2191 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2193 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2194 "Var args not supported with calling convention fastcc, ghc or hipe");
2196 // Assign locations to all of the incoming arguments.
2197 SmallVector<CCValAssign, 16> ArgLocs;
2198 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2199 ArgLocs, *DAG.getContext());
2201 // Allocate shadow area for Win64
2203 CCInfo.AllocateStack(32, 8);
2205 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2207 unsigned LastVal = ~0U;
2209 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2210 CCValAssign &VA = ArgLocs[i];
2211 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2213 assert(VA.getValNo() != LastVal &&
2214 "Don't support value assigned to multiple locs yet");
2216 LastVal = VA.getValNo();
2218 if (VA.isRegLoc()) {
2219 EVT RegVT = VA.getLocVT();
2220 const TargetRegisterClass *RC;
2221 if (RegVT == MVT::i32)
2222 RC = &X86::GR32RegClass;
2223 else if (Is64Bit && RegVT == MVT::i64)
2224 RC = &X86::GR64RegClass;
2225 else if (RegVT == MVT::f32)
2226 RC = &X86::FR32RegClass;
2227 else if (RegVT == MVT::f64)
2228 RC = &X86::FR64RegClass;
2229 else if (RegVT.is512BitVector())
2230 RC = &X86::VR512RegClass;
2231 else if (RegVT.is256BitVector())
2232 RC = &X86::VR256RegClass;
2233 else if (RegVT.is128BitVector())
2234 RC = &X86::VR128RegClass;
2235 else if (RegVT == MVT::x86mmx)
2236 RC = &X86::VR64RegClass;
2237 else if (RegVT == MVT::i1)
2238 RC = &X86::VK1RegClass;
2239 else if (RegVT == MVT::v8i1)
2240 RC = &X86::VK8RegClass;
2241 else if (RegVT == MVT::v16i1)
2242 RC = &X86::VK16RegClass;
2244 llvm_unreachable("Unknown argument type!");
2246 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2247 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2249 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2250 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2252 if (VA.getLocInfo() == CCValAssign::SExt)
2253 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2254 DAG.getValueType(VA.getValVT()));
2255 else if (VA.getLocInfo() == CCValAssign::ZExt)
2256 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2257 DAG.getValueType(VA.getValVT()));
2258 else if (VA.getLocInfo() == CCValAssign::BCvt)
2259 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2261 if (VA.isExtInLoc()) {
2262 // Handle MMX values passed in XMM regs.
2263 if (RegVT.isVector())
2264 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2266 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2269 assert(VA.isMemLoc());
2270 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2273 // If value is passed via pointer - do a load.
2274 if (VA.getLocInfo() == CCValAssign::Indirect)
2275 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2276 MachinePointerInfo(), false, false, false, 0);
2278 InVals.push_back(ArgValue);
2281 // The x86-64 ABIs require that for returning structs by value we copy
2282 // the sret argument into %rax/%eax (depending on ABI) for the return.
2283 // Win32 requires us to put the sret argument to %eax as well.
2284 // Save the argument into a virtual register so that we can access it
2285 // from the return points.
2286 if (MF.getFunction()->hasStructRetAttr() &&
2287 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2288 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2289 unsigned Reg = FuncInfo->getSRetReturnReg();
2291 MVT PtrTy = getPointerTy();
2292 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2293 FuncInfo->setSRetReturnReg(Reg);
2295 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2296 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2299 unsigned StackSize = CCInfo.getNextStackOffset();
2300 // Align stack specially for tail calls.
2301 if (FuncIsMadeTailCallSafe(CallConv,
2302 MF.getTarget().Options.GuaranteedTailCallOpt))
2303 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2305 // If the function takes variable number of arguments, make a frame index for
2306 // the start of the first vararg value... for expansion of llvm.va_start.
2308 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2309 CallConv != CallingConv::X86_ThisCall)) {
2310 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2313 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2315 // FIXME: We should really autogenerate these arrays
2316 static const uint16_t GPR64ArgRegsWin64[] = {
2317 X86::RCX, X86::RDX, X86::R8, X86::R9
2319 static const uint16_t GPR64ArgRegs64Bit[] = {
2320 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2322 static const uint16_t XMMArgRegs64Bit[] = {
2323 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2324 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2326 const uint16_t *GPR64ArgRegs;
2327 unsigned NumXMMRegs = 0;
2330 // The XMM registers which might contain var arg parameters are shadowed
2331 // in their paired GPR. So we only need to save the GPR to their home
2333 TotalNumIntRegs = 4;
2334 GPR64ArgRegs = GPR64ArgRegsWin64;
2336 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2337 GPR64ArgRegs = GPR64ArgRegs64Bit;
2339 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2342 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2345 bool NoImplicitFloatOps = Fn->getAttributes().
2346 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2347 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2348 "SSE register cannot be used when SSE is disabled!");
2349 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2350 NoImplicitFloatOps) &&
2351 "SSE register cannot be used when SSE is disabled!");
2352 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2353 !Subtarget->hasSSE1())
2354 // Kernel mode asks for SSE to be disabled, so don't push them
2356 TotalNumXMMRegs = 0;
2359 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2360 // Get to the caller-allocated home save location. Add 8 to account
2361 // for the return address.
2362 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2363 FuncInfo->setRegSaveFrameIndex(
2364 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2365 // Fixup to set vararg frame on shadow area (4 x i64).
2367 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2369 // For X86-64, if there are vararg parameters that are passed via
2370 // registers, then we must store them to their spots on the stack so
2371 // they may be loaded by deferencing the result of va_next.
2372 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2373 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2374 FuncInfo->setRegSaveFrameIndex(
2375 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2379 // Store the integer parameter registers.
2380 SmallVector<SDValue, 8> MemOps;
2381 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2383 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2384 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2385 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2386 DAG.getIntPtrConstant(Offset));
2387 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2388 &X86::GR64RegClass);
2389 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2391 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2392 MachinePointerInfo::getFixedStack(
2393 FuncInfo->getRegSaveFrameIndex(), Offset),
2395 MemOps.push_back(Store);
2399 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2400 // Now store the XMM (fp + vector) parameter registers.
2401 SmallVector<SDValue, 11> SaveXMMOps;
2402 SaveXMMOps.push_back(Chain);
2404 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2405 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2406 SaveXMMOps.push_back(ALVal);
2408 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2409 FuncInfo->getRegSaveFrameIndex()));
2410 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2411 FuncInfo->getVarArgsFPOffset()));
2413 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2414 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2415 &X86::VR128RegClass);
2416 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2417 SaveXMMOps.push_back(Val);
2419 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2421 &SaveXMMOps[0], SaveXMMOps.size()));
2424 if (!MemOps.empty())
2425 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2426 &MemOps[0], MemOps.size());
2430 // Some CCs need callee pop.
2431 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2432 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2433 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2435 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2436 // If this is an sret function, the return should pop the hidden pointer.
2437 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2438 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2439 argsAreStructReturn(Ins) == StackStructReturn)
2440 FuncInfo->setBytesToPopOnReturn(4);
2444 // RegSaveFrameIndex is X86-64 only.
2445 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2446 if (CallConv == CallingConv::X86_FastCall ||
2447 CallConv == CallingConv::X86_ThisCall)
2448 // fastcc functions can't have varargs.
2449 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2452 FuncInfo->setArgumentStackSize(StackSize);
2458 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2459 SDValue StackPtr, SDValue Arg,
2460 SDLoc dl, SelectionDAG &DAG,
2461 const CCValAssign &VA,
2462 ISD::ArgFlagsTy Flags) const {
2463 unsigned LocMemOffset = VA.getLocMemOffset();
2464 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2465 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2466 if (Flags.isByVal())
2467 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2469 return DAG.getStore(Chain, dl, Arg, PtrOff,
2470 MachinePointerInfo::getStack(LocMemOffset),
2474 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2475 /// optimization is performed and it is required.
2477 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2478 SDValue &OutRetAddr, SDValue Chain,
2479 bool IsTailCall, bool Is64Bit,
2480 int FPDiff, SDLoc dl) const {
2481 // Adjust the Return address stack slot.
2482 EVT VT = getPointerTy();
2483 OutRetAddr = getReturnAddressFrameIndex(DAG);
2485 // Load the "old" Return address.
2486 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2487 false, false, false, 0);
2488 return SDValue(OutRetAddr.getNode(), 1);
2491 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2492 /// optimization is performed and it is required (FPDiff!=0).
2494 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2495 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2496 unsigned SlotSize, int FPDiff, SDLoc dl) {
2497 // Store the return address to the appropriate stack slot.
2498 if (!FPDiff) return Chain;
2499 // Calculate the new stack slot for the return address.
2500 int NewReturnAddrFI =
2501 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2503 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2504 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2505 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2511 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2512 SmallVectorImpl<SDValue> &InVals) const {
2513 SelectionDAG &DAG = CLI.DAG;
2515 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2516 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2517 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2518 SDValue Chain = CLI.Chain;
2519 SDValue Callee = CLI.Callee;
2520 CallingConv::ID CallConv = CLI.CallConv;
2521 bool &isTailCall = CLI.IsTailCall;
2522 bool isVarArg = CLI.IsVarArg;
2524 MachineFunction &MF = DAG.getMachineFunction();
2525 bool Is64Bit = Subtarget->is64Bit();
2526 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2527 StructReturnType SR = callIsStructReturn(Outs);
2528 bool IsSibcall = false;
2530 if (MF.getTarget().Options.DisableTailCalls)
2534 // Check if it's really possible to do a tail call.
2535 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2536 isVarArg, SR != NotStructReturn,
2537 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2538 Outs, OutVals, Ins, DAG);
2540 // Sibcalls are automatically detected tailcalls which do not require
2542 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2549 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2550 "Var args not supported with calling convention fastcc, ghc or hipe");
2552 // Analyze operands of the call, assigning locations to each operand.
2553 SmallVector<CCValAssign, 16> ArgLocs;
2554 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2555 ArgLocs, *DAG.getContext());
2557 // Allocate shadow area for Win64
2559 CCInfo.AllocateStack(32, 8);
2561 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2563 // Get a count of how many bytes are to be pushed on the stack.
2564 unsigned NumBytes = CCInfo.getNextStackOffset();
2566 // This is a sibcall. The memory operands are available in caller's
2567 // own caller's stack.
2569 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2570 IsTailCallConvention(CallConv))
2571 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2574 if (isTailCall && !IsSibcall) {
2575 // Lower arguments at fp - stackoffset + fpdiff.
2576 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2577 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2579 FPDiff = NumBytesCallerPushed - NumBytes;
2581 // Set the delta of movement of the returnaddr stackslot.
2582 // But only set if delta is greater than previous delta.
2583 if (FPDiff < X86Info->getTCReturnAddrDelta())
2584 X86Info->setTCReturnAddrDelta(FPDiff);
2588 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2591 SDValue RetAddrFrIdx;
2592 // Load return address for tail calls.
2593 if (isTailCall && FPDiff)
2594 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2595 Is64Bit, FPDiff, dl);
2597 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2598 SmallVector<SDValue, 8> MemOpChains;
2601 // Walk the register/memloc assignments, inserting copies/loads. In the case
2602 // of tail call optimization arguments are handle later.
2603 const X86RegisterInfo *RegInfo =
2604 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2605 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2606 CCValAssign &VA = ArgLocs[i];
2607 EVT RegVT = VA.getLocVT();
2608 SDValue Arg = OutVals[i];
2609 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2610 bool isByVal = Flags.isByVal();
2612 // Promote the value if needed.
2613 switch (VA.getLocInfo()) {
2614 default: llvm_unreachable("Unknown loc info!");
2615 case CCValAssign::Full: break;
2616 case CCValAssign::SExt:
2617 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2619 case CCValAssign::ZExt:
2620 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2622 case CCValAssign::AExt:
2623 if (RegVT.is128BitVector()) {
2624 // Special case: passing MMX values in XMM registers.
2625 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2626 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2627 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2629 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2631 case CCValAssign::BCvt:
2632 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2634 case CCValAssign::Indirect: {
2635 // Store the argument.
2636 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2637 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2638 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2639 MachinePointerInfo::getFixedStack(FI),
2646 if (VA.isRegLoc()) {
2647 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2648 if (isVarArg && IsWin64) {
2649 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2650 // shadow reg if callee is a varargs function.
2651 unsigned ShadowReg = 0;
2652 switch (VA.getLocReg()) {
2653 case X86::XMM0: ShadowReg = X86::RCX; break;
2654 case X86::XMM1: ShadowReg = X86::RDX; break;
2655 case X86::XMM2: ShadowReg = X86::R8; break;
2656 case X86::XMM3: ShadowReg = X86::R9; break;
2659 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2661 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2662 assert(VA.isMemLoc());
2663 if (StackPtr.getNode() == 0)
2664 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2666 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2667 dl, DAG, VA, Flags));
2671 if (!MemOpChains.empty())
2672 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2673 &MemOpChains[0], MemOpChains.size());
2675 if (Subtarget->isPICStyleGOT()) {
2676 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2679 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2680 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2682 // If we are tail calling and generating PIC/GOT style code load the
2683 // address of the callee into ECX. The value in ecx is used as target of
2684 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2685 // for tail calls on PIC/GOT architectures. Normally we would just put the
2686 // address of GOT into ebx and then call target@PLT. But for tail calls
2687 // ebx would be restored (since ebx is callee saved) before jumping to the
2690 // Note: The actual moving to ECX is done further down.
2691 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2692 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2693 !G->getGlobal()->hasProtectedVisibility())
2694 Callee = LowerGlobalAddress(Callee, DAG);
2695 else if (isa<ExternalSymbolSDNode>(Callee))
2696 Callee = LowerExternalSymbol(Callee, DAG);
2700 if (Is64Bit && isVarArg && !IsWin64) {
2701 // From AMD64 ABI document:
2702 // For calls that may call functions that use varargs or stdargs
2703 // (prototype-less calls or calls to functions containing ellipsis (...) in
2704 // the declaration) %al is used as hidden argument to specify the number
2705 // of SSE registers used. The contents of %al do not need to match exactly
2706 // the number of registers, but must be an ubound on the number of SSE
2707 // registers used and is in the range 0 - 8 inclusive.
2709 // Count the number of XMM registers allocated.
2710 static const uint16_t XMMArgRegs[] = {
2711 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2712 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2714 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2715 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2716 && "SSE registers cannot be used when SSE is disabled");
2718 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2719 DAG.getConstant(NumXMMRegs, MVT::i8)));
2722 // For tail calls lower the arguments to the 'real' stack slot.
2724 // Force all the incoming stack arguments to be loaded from the stack
2725 // before any new outgoing arguments are stored to the stack, because the
2726 // outgoing stack slots may alias the incoming argument stack slots, and
2727 // the alias isn't otherwise explicit. This is slightly more conservative
2728 // than necessary, because it means that each store effectively depends
2729 // on every argument instead of just those arguments it would clobber.
2730 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2732 SmallVector<SDValue, 8> MemOpChains2;
2735 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2736 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2737 CCValAssign &VA = ArgLocs[i];
2740 assert(VA.isMemLoc());
2741 SDValue Arg = OutVals[i];
2742 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2743 // Create frame index.
2744 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2745 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2746 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2747 FIN = DAG.getFrameIndex(FI, getPointerTy());
2749 if (Flags.isByVal()) {
2750 // Copy relative to framepointer.
2751 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2752 if (StackPtr.getNode() == 0)
2753 StackPtr = DAG.getCopyFromReg(Chain, dl,
2754 RegInfo->getStackRegister(),
2756 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2758 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2762 // Store relative to framepointer.
2763 MemOpChains2.push_back(
2764 DAG.getStore(ArgChain, dl, Arg, FIN,
2765 MachinePointerInfo::getFixedStack(FI),
2771 if (!MemOpChains2.empty())
2772 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2773 &MemOpChains2[0], MemOpChains2.size());
2775 // Store the return address to the appropriate stack slot.
2776 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2777 getPointerTy(), RegInfo->getSlotSize(),
2781 // Build a sequence of copy-to-reg nodes chained together with token chain
2782 // and flag operands which copy the outgoing args into registers.
2784 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2785 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2786 RegsToPass[i].second, InFlag);
2787 InFlag = Chain.getValue(1);
2790 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2791 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2792 // In the 64-bit large code model, we have to make all calls
2793 // through a register, since the call instruction's 32-bit
2794 // pc-relative offset may not be large enough to hold the whole
2796 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2797 // If the callee is a GlobalAddress node (quite common, every direct call
2798 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2801 // We should use extra load for direct calls to dllimported functions in
2803 const GlobalValue *GV = G->getGlobal();
2804 if (!GV->hasDLLImportStorageClass()) {
2805 unsigned char OpFlags = 0;
2806 bool ExtraLoad = false;
2807 unsigned WrapperKind = ISD::DELETED_NODE;
2809 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2810 // external symbols most go through the PLT in PIC mode. If the symbol
2811 // has hidden or protected visibility, or if it is static or local, then
2812 // we don't need to use the PLT - we can directly call it.
2813 if (Subtarget->isTargetELF() &&
2814 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2815 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2816 OpFlags = X86II::MO_PLT;
2817 } else if (Subtarget->isPICStyleStubAny() &&
2818 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2819 (!Subtarget->getTargetTriple().isMacOSX() ||
2820 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2821 // PC-relative references to external symbols should go through $stub,
2822 // unless we're building with the leopard linker or later, which
2823 // automatically synthesizes these stubs.
2824 OpFlags = X86II::MO_DARWIN_STUB;
2825 } else if (Subtarget->isPICStyleRIPRel() &&
2826 isa<Function>(GV) &&
2827 cast<Function>(GV)->getAttributes().
2828 hasAttribute(AttributeSet::FunctionIndex,
2829 Attribute::NonLazyBind)) {
2830 // If the function is marked as non-lazy, generate an indirect call
2831 // which loads from the GOT directly. This avoids runtime overhead
2832 // at the cost of eager binding (and one extra byte of encoding).
2833 OpFlags = X86II::MO_GOTPCREL;
2834 WrapperKind = X86ISD::WrapperRIP;
2838 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2839 G->getOffset(), OpFlags);
2841 // Add a wrapper if needed.
2842 if (WrapperKind != ISD::DELETED_NODE)
2843 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2844 // Add extra indirection if needed.
2846 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2847 MachinePointerInfo::getGOT(),
2848 false, false, false, 0);
2850 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2851 unsigned char OpFlags = 0;
2853 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2854 // external symbols should go through the PLT.
2855 if (Subtarget->isTargetELF() &&
2856 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2857 OpFlags = X86II::MO_PLT;
2858 } else if (Subtarget->isPICStyleStubAny() &&
2859 (!Subtarget->getTargetTriple().isMacOSX() ||
2860 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2861 // PC-relative references to external symbols should go through $stub,
2862 // unless we're building with the leopard linker or later, which
2863 // automatically synthesizes these stubs.
2864 OpFlags = X86II::MO_DARWIN_STUB;
2867 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2871 // Returns a chain & a flag for retval copy to use.
2872 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2873 SmallVector<SDValue, 8> Ops;
2875 if (!IsSibcall && isTailCall) {
2876 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2877 DAG.getIntPtrConstant(0, true), InFlag, dl);
2878 InFlag = Chain.getValue(1);
2881 Ops.push_back(Chain);
2882 Ops.push_back(Callee);
2885 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2887 // Add argument registers to the end of the list so that they are known live
2889 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2890 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2891 RegsToPass[i].second.getValueType()));
2893 // Add a register mask operand representing the call-preserved registers.
2894 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2895 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2896 assert(Mask && "Missing call preserved mask for calling convention");
2897 Ops.push_back(DAG.getRegisterMask(Mask));
2899 if (InFlag.getNode())
2900 Ops.push_back(InFlag);
2904 //// If this is the first return lowered for this function, add the regs
2905 //// to the liveout set for the function.
2906 // This isn't right, although it's probably harmless on x86; liveouts
2907 // should be computed from returns not tail calls. Consider a void
2908 // function making a tail call to a function returning int.
2909 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2912 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2913 InFlag = Chain.getValue(1);
2915 // Create the CALLSEQ_END node.
2916 unsigned NumBytesForCalleeToPush;
2917 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2918 getTargetMachine().Options.GuaranteedTailCallOpt))
2919 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2920 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2921 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2922 SR == StackStructReturn)
2923 // If this is a call to a struct-return function, the callee
2924 // pops the hidden struct pointer, so we have to push it back.
2925 // This is common for Darwin/X86, Linux & Mingw32 targets.
2926 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2927 NumBytesForCalleeToPush = 4;
2929 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2931 // Returns a flag for retval copy to use.
2933 Chain = DAG.getCALLSEQ_END(Chain,
2934 DAG.getIntPtrConstant(NumBytes, true),
2935 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2938 InFlag = Chain.getValue(1);
2941 // Handle result values, copying them out of physregs into vregs that we
2943 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2944 Ins, dl, DAG, InVals);
2947 //===----------------------------------------------------------------------===//
2948 // Fast Calling Convention (tail call) implementation
2949 //===----------------------------------------------------------------------===//
2951 // Like std call, callee cleans arguments, convention except that ECX is
2952 // reserved for storing the tail called function address. Only 2 registers are
2953 // free for argument passing (inreg). Tail call optimization is performed
2955 // * tailcallopt is enabled
2956 // * caller/callee are fastcc
2957 // On X86_64 architecture with GOT-style position independent code only local
2958 // (within module) calls are supported at the moment.
2959 // To keep the stack aligned according to platform abi the function
2960 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2961 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2962 // If a tail called function callee has more arguments than the caller the
2963 // caller needs to make sure that there is room to move the RETADDR to. This is
2964 // achieved by reserving an area the size of the argument delta right after the
2965 // original REtADDR, but before the saved framepointer or the spilled registers
2966 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2978 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2979 /// for a 16 byte align requirement.
2981 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2982 SelectionDAG& DAG) const {
2983 MachineFunction &MF = DAG.getMachineFunction();
2984 const TargetMachine &TM = MF.getTarget();
2985 const X86RegisterInfo *RegInfo =
2986 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2987 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2988 unsigned StackAlignment = TFI.getStackAlignment();
2989 uint64_t AlignMask = StackAlignment - 1;
2990 int64_t Offset = StackSize;
2991 unsigned SlotSize = RegInfo->getSlotSize();
2992 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2993 // Number smaller than 12 so just add the difference.
2994 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2996 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2997 Offset = ((~AlignMask) & Offset) + StackAlignment +
2998 (StackAlignment-SlotSize);
3003 /// MatchingStackOffset - Return true if the given stack call argument is
3004 /// already available in the same position (relatively) of the caller's
3005 /// incoming argument stack.
3007 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3008 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3009 const X86InstrInfo *TII) {
3010 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3012 if (Arg.getOpcode() == ISD::CopyFromReg) {
3013 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3014 if (!TargetRegisterInfo::isVirtualRegister(VR))
3016 MachineInstr *Def = MRI->getVRegDef(VR);
3019 if (!Flags.isByVal()) {
3020 if (!TII->isLoadFromStackSlot(Def, FI))
3023 unsigned Opcode = Def->getOpcode();
3024 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3025 Def->getOperand(1).isFI()) {
3026 FI = Def->getOperand(1).getIndex();
3027 Bytes = Flags.getByValSize();
3031 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3032 if (Flags.isByVal())
3033 // ByVal argument is passed in as a pointer but it's now being
3034 // dereferenced. e.g.
3035 // define @foo(%struct.X* %A) {
3036 // tail call @bar(%struct.X* byval %A)
3039 SDValue Ptr = Ld->getBasePtr();
3040 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3043 FI = FINode->getIndex();
3044 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3045 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3046 FI = FINode->getIndex();
3047 Bytes = Flags.getByValSize();
3051 assert(FI != INT_MAX);
3052 if (!MFI->isFixedObjectIndex(FI))
3054 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3057 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3058 /// for tail call optimization. Targets which want to do tail call
3059 /// optimization should implement this function.
3061 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3062 CallingConv::ID CalleeCC,
3064 bool isCalleeStructRet,
3065 bool isCallerStructRet,
3067 const SmallVectorImpl<ISD::OutputArg> &Outs,
3068 const SmallVectorImpl<SDValue> &OutVals,
3069 const SmallVectorImpl<ISD::InputArg> &Ins,
3070 SelectionDAG &DAG) const {
3071 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3074 // If -tailcallopt is specified, make fastcc functions tail-callable.
3075 const MachineFunction &MF = DAG.getMachineFunction();
3076 const Function *CallerF = MF.getFunction();
3078 // If the function return type is x86_fp80 and the callee return type is not,
3079 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3080 // perform a tailcall optimization here.
3081 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3084 CallingConv::ID CallerCC = CallerF->getCallingConv();
3085 bool CCMatch = CallerCC == CalleeCC;
3086 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3087 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3089 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3090 if (IsTailCallConvention(CalleeCC) && CCMatch)
3095 // Look for obvious safe cases to perform tail call optimization that do not
3096 // require ABI changes. This is what gcc calls sibcall.
3098 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3099 // emit a special epilogue.
3100 const X86RegisterInfo *RegInfo =
3101 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3102 if (RegInfo->needsStackRealignment(MF))
3105 // Also avoid sibcall optimization if either caller or callee uses struct
3106 // return semantics.
3107 if (isCalleeStructRet || isCallerStructRet)
3110 // An stdcall/thiscall caller is expected to clean up its arguments; the
3111 // callee isn't going to do that.
3112 // FIXME: this is more restrictive than needed. We could produce a tailcall
3113 // when the stack adjustment matches. For example, with a thiscall that takes
3114 // only one argument.
3115 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3116 CallerCC == CallingConv::X86_ThisCall))
3119 // Do not sibcall optimize vararg calls unless all arguments are passed via
3121 if (isVarArg && !Outs.empty()) {
3123 // Optimizing for varargs on Win64 is unlikely to be safe without
3124 // additional testing.
3125 if (IsCalleeWin64 || IsCallerWin64)
3128 SmallVector<CCValAssign, 16> ArgLocs;
3129 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3130 getTargetMachine(), ArgLocs, *DAG.getContext());
3132 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3133 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3134 if (!ArgLocs[i].isRegLoc())
3138 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3139 // stack. Therefore, if it's not used by the call it is not safe to optimize
3140 // this into a sibcall.
3141 bool Unused = false;
3142 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3149 SmallVector<CCValAssign, 16> RVLocs;
3150 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3151 getTargetMachine(), RVLocs, *DAG.getContext());
3152 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3153 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3154 CCValAssign &VA = RVLocs[i];
3155 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3160 // If the calling conventions do not match, then we'd better make sure the
3161 // results are returned in the same way as what the caller expects.
3163 SmallVector<CCValAssign, 16> RVLocs1;
3164 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3165 getTargetMachine(), RVLocs1, *DAG.getContext());
3166 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3168 SmallVector<CCValAssign, 16> RVLocs2;
3169 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3170 getTargetMachine(), RVLocs2, *DAG.getContext());
3171 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3173 if (RVLocs1.size() != RVLocs2.size())
3175 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3176 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3178 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3180 if (RVLocs1[i].isRegLoc()) {
3181 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3184 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3190 // If the callee takes no arguments then go on to check the results of the
3192 if (!Outs.empty()) {
3193 // Check if stack adjustment is needed. For now, do not do this if any
3194 // argument is passed on the stack.
3195 SmallVector<CCValAssign, 16> ArgLocs;
3196 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3197 getTargetMachine(), ArgLocs, *DAG.getContext());
3199 // Allocate shadow area for Win64
3201 CCInfo.AllocateStack(32, 8);
3203 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3204 if (CCInfo.getNextStackOffset()) {
3205 MachineFunction &MF = DAG.getMachineFunction();
3206 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3209 // Check if the arguments are already laid out in the right way as
3210 // the caller's fixed stack objects.
3211 MachineFrameInfo *MFI = MF.getFrameInfo();
3212 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3213 const X86InstrInfo *TII =
3214 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3215 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3216 CCValAssign &VA = ArgLocs[i];
3217 SDValue Arg = OutVals[i];
3218 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3219 if (VA.getLocInfo() == CCValAssign::Indirect)
3221 if (!VA.isRegLoc()) {
3222 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3229 // If the tailcall address may be in a register, then make sure it's
3230 // possible to register allocate for it. In 32-bit, the call address can
3231 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3232 // callee-saved registers are restored. These happen to be the same
3233 // registers used to pass 'inreg' arguments so watch out for those.
3234 if (!Subtarget->is64Bit() &&
3235 ((!isa<GlobalAddressSDNode>(Callee) &&
3236 !isa<ExternalSymbolSDNode>(Callee)) ||
3237 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3238 unsigned NumInRegs = 0;
3239 // In PIC we need an extra register to formulate the address computation
3241 unsigned MaxInRegs =
3242 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3244 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3245 CCValAssign &VA = ArgLocs[i];
3248 unsigned Reg = VA.getLocReg();
3251 case X86::EAX: case X86::EDX: case X86::ECX:
3252 if (++NumInRegs == MaxInRegs)
3264 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3265 const TargetLibraryInfo *libInfo) const {
3266 return X86::createFastISel(funcInfo, libInfo);
3269 //===----------------------------------------------------------------------===//
3270 // Other Lowering Hooks
3271 //===----------------------------------------------------------------------===//
3273 static bool MayFoldLoad(SDValue Op) {
3274 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3277 static bool MayFoldIntoStore(SDValue Op) {
3278 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3281 static bool isTargetShuffle(unsigned Opcode) {
3283 default: return false;
3284 case X86ISD::PSHUFD:
3285 case X86ISD::PSHUFHW:
3286 case X86ISD::PSHUFLW:
3288 case X86ISD::PALIGNR:
3289 case X86ISD::MOVLHPS:
3290 case X86ISD::MOVLHPD:
3291 case X86ISD::MOVHLPS:
3292 case X86ISD::MOVLPS:
3293 case X86ISD::MOVLPD:
3294 case X86ISD::MOVSHDUP:
3295 case X86ISD::MOVSLDUP:
3296 case X86ISD::MOVDDUP:
3299 case X86ISD::UNPCKL:
3300 case X86ISD::UNPCKH:
3301 case X86ISD::VPERMILP:
3302 case X86ISD::VPERM2X128:
3303 case X86ISD::VPERMI:
3308 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3309 SDValue V1, SelectionDAG &DAG) {
3311 default: llvm_unreachable("Unknown x86 shuffle node");
3312 case X86ISD::MOVSHDUP:
3313 case X86ISD::MOVSLDUP:
3314 case X86ISD::MOVDDUP:
3315 return DAG.getNode(Opc, dl, VT, V1);
3319 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3320 SDValue V1, unsigned TargetMask,
3321 SelectionDAG &DAG) {
3323 default: llvm_unreachable("Unknown x86 shuffle node");
3324 case X86ISD::PSHUFD:
3325 case X86ISD::PSHUFHW:
3326 case X86ISD::PSHUFLW:
3327 case X86ISD::VPERMILP:
3328 case X86ISD::VPERMI:
3329 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3333 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3334 SDValue V1, SDValue V2, unsigned TargetMask,
3335 SelectionDAG &DAG) {
3337 default: llvm_unreachable("Unknown x86 shuffle node");
3338 case X86ISD::PALIGNR:
3340 case X86ISD::VPERM2X128:
3341 return DAG.getNode(Opc, dl, VT, V1, V2,
3342 DAG.getConstant(TargetMask, MVT::i8));
3346 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3347 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3349 default: llvm_unreachable("Unknown x86 shuffle node");
3350 case X86ISD::MOVLHPS:
3351 case X86ISD::MOVLHPD:
3352 case X86ISD::MOVHLPS:
3353 case X86ISD::MOVLPS:
3354 case X86ISD::MOVLPD:
3357 case X86ISD::UNPCKL:
3358 case X86ISD::UNPCKH:
3359 return DAG.getNode(Opc, dl, VT, V1, V2);
3363 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3364 MachineFunction &MF = DAG.getMachineFunction();
3365 const X86RegisterInfo *RegInfo =
3366 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3367 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3368 int ReturnAddrIndex = FuncInfo->getRAIndex();
3370 if (ReturnAddrIndex == 0) {
3371 // Set up a frame object for the return address.
3372 unsigned SlotSize = RegInfo->getSlotSize();
3373 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3376 FuncInfo->setRAIndex(ReturnAddrIndex);
3379 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3382 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3383 bool hasSymbolicDisplacement) {
3384 // Offset should fit into 32 bit immediate field.
3385 if (!isInt<32>(Offset))
3388 // If we don't have a symbolic displacement - we don't have any extra
3390 if (!hasSymbolicDisplacement)
3393 // FIXME: Some tweaks might be needed for medium code model.
3394 if (M != CodeModel::Small && M != CodeModel::Kernel)
3397 // For small code model we assume that latest object is 16MB before end of 31
3398 // bits boundary. We may also accept pretty large negative constants knowing
3399 // that all objects are in the positive half of address space.
3400 if (M == CodeModel::Small && Offset < 16*1024*1024)
3403 // For kernel code model we know that all object resist in the negative half
3404 // of 32bits address space. We may not accept negative offsets, since they may
3405 // be just off and we may accept pretty large positive ones.
3406 if (M == CodeModel::Kernel && Offset > 0)
3412 /// isCalleePop - Determines whether the callee is required to pop its
3413 /// own arguments. Callee pop is necessary to support tail calls.
3414 bool X86::isCalleePop(CallingConv::ID CallingConv,
3415 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3419 switch (CallingConv) {
3422 case CallingConv::X86_StdCall:
3424 case CallingConv::X86_FastCall:
3426 case CallingConv::X86_ThisCall:
3428 case CallingConv::Fast:
3430 case CallingConv::GHC:
3432 case CallingConv::HiPE:
3437 /// \brief Return true if the condition is an unsigned comparison operation.
3438 static bool isX86CCUnsigned(unsigned X86CC) {
3440 default: llvm_unreachable("Invalid integer condition!");
3441 case X86::COND_E: return true;
3442 case X86::COND_G: return false;
3443 case X86::COND_GE: return false;
3444 case X86::COND_L: return false;
3445 case X86::COND_LE: return false;
3446 case X86::COND_NE: return true;
3447 case X86::COND_B: return true;
3448 case X86::COND_A: return true;
3449 case X86::COND_BE: return true;
3450 case X86::COND_AE: return true;
3452 llvm_unreachable("covered switch fell through?!");
3455 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3456 /// specific condition code, returning the condition code and the LHS/RHS of the
3457 /// comparison to make.
3458 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3459 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3461 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3462 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3463 // X > -1 -> X == 0, jump !sign.
3464 RHS = DAG.getConstant(0, RHS.getValueType());
3465 return X86::COND_NS;
3467 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3468 // X < 0 -> X == 0, jump on sign.
3471 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3473 RHS = DAG.getConstant(0, RHS.getValueType());
3474 return X86::COND_LE;
3478 switch (SetCCOpcode) {
3479 default: llvm_unreachable("Invalid integer condition!");
3480 case ISD::SETEQ: return X86::COND_E;
3481 case ISD::SETGT: return X86::COND_G;
3482 case ISD::SETGE: return X86::COND_GE;
3483 case ISD::SETLT: return X86::COND_L;
3484 case ISD::SETLE: return X86::COND_LE;
3485 case ISD::SETNE: return X86::COND_NE;
3486 case ISD::SETULT: return X86::COND_B;
3487 case ISD::SETUGT: return X86::COND_A;
3488 case ISD::SETULE: return X86::COND_BE;
3489 case ISD::SETUGE: return X86::COND_AE;
3493 // First determine if it is required or is profitable to flip the operands.
3495 // If LHS is a foldable load, but RHS is not, flip the condition.
3496 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3497 !ISD::isNON_EXTLoad(RHS.getNode())) {
3498 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3499 std::swap(LHS, RHS);
3502 switch (SetCCOpcode) {
3508 std::swap(LHS, RHS);
3512 // On a floating point condition, the flags are set as follows:
3514 // 0 | 0 | 0 | X > Y
3515 // 0 | 0 | 1 | X < Y
3516 // 1 | 0 | 0 | X == Y
3517 // 1 | 1 | 1 | unordered
3518 switch (SetCCOpcode) {
3519 default: llvm_unreachable("Condcode should be pre-legalized away");
3521 case ISD::SETEQ: return X86::COND_E;
3522 case ISD::SETOLT: // flipped
3524 case ISD::SETGT: return X86::COND_A;
3525 case ISD::SETOLE: // flipped
3527 case ISD::SETGE: return X86::COND_AE;
3528 case ISD::SETUGT: // flipped
3530 case ISD::SETLT: return X86::COND_B;
3531 case ISD::SETUGE: // flipped
3533 case ISD::SETLE: return X86::COND_BE;
3535 case ISD::SETNE: return X86::COND_NE;
3536 case ISD::SETUO: return X86::COND_P;
3537 case ISD::SETO: return X86::COND_NP;
3539 case ISD::SETUNE: return X86::COND_INVALID;
3543 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3544 /// code. Current x86 isa includes the following FP cmov instructions:
3545 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3546 static bool hasFPCMov(unsigned X86CC) {
3562 /// isFPImmLegal - Returns true if the target can instruction select the
3563 /// specified FP immediate natively. If false, the legalizer will
3564 /// materialize the FP immediate as a load from a constant pool.
3565 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3566 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3567 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3573 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3574 /// the specified range (L, H].
3575 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3576 return (Val < 0) || (Val >= Low && Val < Hi);
3579 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3580 /// specified value.
3581 static bool isUndefOrEqual(int Val, int CmpVal) {
3582 return (Val < 0 || Val == CmpVal);
3585 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3586 /// from position Pos and ending in Pos+Size, falls within the specified
3587 /// sequential range (L, L+Pos]. or is undef.
3588 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3589 unsigned Pos, unsigned Size, int Low) {
3590 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3591 if (!isUndefOrEqual(Mask[i], Low))
3596 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3597 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3598 /// the second operand.
3599 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3600 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3601 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3602 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3603 return (Mask[0] < 2 && Mask[1] < 2);
3607 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3608 /// is suitable for input to PSHUFHW.
3609 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3610 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3613 // Lower quadword copied in order or undef.
3614 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3617 // Upper quadword shuffled.
3618 for (unsigned i = 4; i != 8; ++i)
3619 if (!isUndefOrInRange(Mask[i], 4, 8))
3622 if (VT == MVT::v16i16) {
3623 // Lower quadword copied in order or undef.
3624 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3627 // Upper quadword shuffled.
3628 for (unsigned i = 12; i != 16; ++i)
3629 if (!isUndefOrInRange(Mask[i], 12, 16))
3636 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3637 /// is suitable for input to PSHUFLW.
3638 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3639 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3642 // Upper quadword copied in order.
3643 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3646 // Lower quadword shuffled.
3647 for (unsigned i = 0; i != 4; ++i)
3648 if (!isUndefOrInRange(Mask[i], 0, 4))
3651 if (VT == MVT::v16i16) {
3652 // Upper quadword copied in order.
3653 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3656 // Lower quadword shuffled.
3657 for (unsigned i = 8; i != 12; ++i)
3658 if (!isUndefOrInRange(Mask[i], 8, 12))
3665 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3666 /// is suitable for input to PALIGNR.
3667 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3668 const X86Subtarget *Subtarget) {
3669 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3670 (VT.is256BitVector() && !Subtarget->hasInt256()))
3673 unsigned NumElts = VT.getVectorNumElements();
3674 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3675 unsigned NumLaneElts = NumElts/NumLanes;
3677 // Do not handle 64-bit element shuffles with palignr.
3678 if (NumLaneElts == 2)
3681 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3683 for (i = 0; i != NumLaneElts; ++i) {
3688 // Lane is all undef, go to next lane
3689 if (i == NumLaneElts)
3692 int Start = Mask[i+l];
3694 // Make sure its in this lane in one of the sources
3695 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3696 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3699 // If not lane 0, then we must match lane 0
3700 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3703 // Correct second source to be contiguous with first source
3704 if (Start >= (int)NumElts)
3705 Start -= NumElts - NumLaneElts;
3707 // Make sure we're shifting in the right direction.
3708 if (Start <= (int)(i+l))
3713 // Check the rest of the elements to see if they are consecutive.
3714 for (++i; i != NumLaneElts; ++i) {
3715 int Idx = Mask[i+l];
3717 // Make sure its in this lane
3718 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3719 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3722 // If not lane 0, then we must match lane 0
3723 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3726 if (Idx >= (int)NumElts)
3727 Idx -= NumElts - NumLaneElts;
3729 if (!isUndefOrEqual(Idx, Start+i))
3738 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3739 /// the two vector operands have swapped position.
3740 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3741 unsigned NumElems) {
3742 for (unsigned i = 0; i != NumElems; ++i) {
3746 else if (idx < (int)NumElems)
3747 Mask[i] = idx + NumElems;
3749 Mask[i] = idx - NumElems;
3753 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3754 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3755 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3756 /// reverse of what x86 shuffles want.
3757 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3759 unsigned NumElems = VT.getVectorNumElements();
3760 unsigned NumLanes = VT.getSizeInBits()/128;
3761 unsigned NumLaneElems = NumElems/NumLanes;
3763 if (NumLaneElems != 2 && NumLaneElems != 4)
3766 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3767 bool symetricMaskRequired =
3768 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3770 // VSHUFPSY divides the resulting vector into 4 chunks.
3771 // The sources are also splitted into 4 chunks, and each destination
3772 // chunk must come from a different source chunk.
3774 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3775 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3777 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3778 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3780 // VSHUFPDY divides the resulting vector into 4 chunks.
3781 // The sources are also splitted into 4 chunks, and each destination
3782 // chunk must come from a different source chunk.
3784 // SRC1 => X3 X2 X1 X0
3785 // SRC2 => Y3 Y2 Y1 Y0
3787 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3789 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3790 unsigned HalfLaneElems = NumLaneElems/2;
3791 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3792 for (unsigned i = 0; i != NumLaneElems; ++i) {
3793 int Idx = Mask[i+l];
3794 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3795 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3797 // For VSHUFPSY, the mask of the second half must be the same as the
3798 // first but with the appropriate offsets. This works in the same way as
3799 // VPERMILPS works with masks.
3800 if (!symetricMaskRequired || Idx < 0)
3802 if (MaskVal[i] < 0) {
3803 MaskVal[i] = Idx - l;
3806 if ((signed)(Idx - l) != MaskVal[i])
3814 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3815 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3816 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3817 if (!VT.is128BitVector())
3820 unsigned NumElems = VT.getVectorNumElements();
3825 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3826 return isUndefOrEqual(Mask[0], 6) &&
3827 isUndefOrEqual(Mask[1], 7) &&
3828 isUndefOrEqual(Mask[2], 2) &&
3829 isUndefOrEqual(Mask[3], 3);
3832 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3833 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3835 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3836 if (!VT.is128BitVector())
3839 unsigned NumElems = VT.getVectorNumElements();
3844 return isUndefOrEqual(Mask[0], 2) &&
3845 isUndefOrEqual(Mask[1], 3) &&
3846 isUndefOrEqual(Mask[2], 2) &&
3847 isUndefOrEqual(Mask[3], 3);
3850 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3851 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3852 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3853 if (!VT.is128BitVector())
3856 unsigned NumElems = VT.getVectorNumElements();
3858 if (NumElems != 2 && NumElems != 4)
3861 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3862 if (!isUndefOrEqual(Mask[i], i + NumElems))
3865 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3866 if (!isUndefOrEqual(Mask[i], i))
3872 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3873 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3874 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3875 if (!VT.is128BitVector())
3878 unsigned NumElems = VT.getVectorNumElements();
3880 if (NumElems != 2 && NumElems != 4)
3883 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3884 if (!isUndefOrEqual(Mask[i], i))
3887 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3888 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3895 // Some special combinations that can be optimized.
3898 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3899 SelectionDAG &DAG) {
3900 MVT VT = SVOp->getSimpleValueType(0);
3903 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3906 ArrayRef<int> Mask = SVOp->getMask();
3908 // These are the special masks that may be optimized.
3909 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3910 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3911 bool MatchEvenMask = true;
3912 bool MatchOddMask = true;
3913 for (int i=0; i<8; ++i) {
3914 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3915 MatchEvenMask = false;
3916 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3917 MatchOddMask = false;
3920 if (!MatchEvenMask && !MatchOddMask)
3923 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3925 SDValue Op0 = SVOp->getOperand(0);
3926 SDValue Op1 = SVOp->getOperand(1);
3928 if (MatchEvenMask) {
3929 // Shift the second operand right to 32 bits.
3930 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3931 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3933 // Shift the first operand left to 32 bits.
3934 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3935 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3937 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3938 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3941 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3942 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3943 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3944 bool HasInt256, bool V2IsSplat = false) {
3946 assert(VT.getSizeInBits() >= 128 &&
3947 "Unsupported vector type for unpckl");
3949 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3951 unsigned NumOf256BitLanes;
3952 unsigned NumElts = VT.getVectorNumElements();
3953 if (VT.is256BitVector()) {
3954 if (NumElts != 4 && NumElts != 8 &&
3955 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3958 NumOf256BitLanes = 1;
3959 } else if (VT.is512BitVector()) {
3960 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3961 "Unsupported vector type for unpckh");
3963 NumOf256BitLanes = 2;
3966 NumOf256BitLanes = 1;
3969 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3970 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3972 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3973 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3974 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3975 int BitI = Mask[l256*NumEltsInStride+l+i];
3976 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3977 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3979 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3981 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3989 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3990 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3991 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3992 bool HasInt256, bool V2IsSplat = false) {
3993 assert(VT.getSizeInBits() >= 128 &&
3994 "Unsupported vector type for unpckh");
3996 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3998 unsigned NumOf256BitLanes;
3999 unsigned NumElts = VT.getVectorNumElements();
4000 if (VT.is256BitVector()) {
4001 if (NumElts != 4 && NumElts != 8 &&
4002 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4005 NumOf256BitLanes = 1;
4006 } else if (VT.is512BitVector()) {
4007 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4008 "Unsupported vector type for unpckh");
4010 NumOf256BitLanes = 2;
4013 NumOf256BitLanes = 1;
4016 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4017 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4019 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4020 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4021 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4022 int BitI = Mask[l256*NumEltsInStride+l+i];
4023 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4024 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4026 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4028 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4036 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4037 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4039 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4040 unsigned NumElts = VT.getVectorNumElements();
4041 bool Is256BitVec = VT.is256BitVector();
4043 if (VT.is512BitVector())
4045 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4046 "Unsupported vector type for unpckh");
4048 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4049 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4052 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4053 // FIXME: Need a better way to get rid of this, there's no latency difference
4054 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4055 // the former later. We should also remove the "_undef" special mask.
4056 if (NumElts == 4 && Is256BitVec)
4059 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4060 // independently on 128-bit lanes.
4061 unsigned NumLanes = VT.getSizeInBits()/128;
4062 unsigned NumLaneElts = NumElts/NumLanes;
4064 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4065 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4066 int BitI = Mask[l+i];
4067 int BitI1 = Mask[l+i+1];
4069 if (!isUndefOrEqual(BitI, j))
4071 if (!isUndefOrEqual(BitI1, j))
4079 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4080 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4082 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4083 unsigned NumElts = VT.getVectorNumElements();
4085 if (VT.is512BitVector())
4088 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4089 "Unsupported vector type for unpckh");
4091 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4092 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4095 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4096 // independently on 128-bit lanes.
4097 unsigned NumLanes = VT.getSizeInBits()/128;
4098 unsigned NumLaneElts = NumElts/NumLanes;
4100 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4101 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4102 int BitI = Mask[l+i];
4103 int BitI1 = Mask[l+i+1];
4104 if (!isUndefOrEqual(BitI, j))
4106 if (!isUndefOrEqual(BitI1, j))
4113 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4114 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4115 /// MOVSD, and MOVD, i.e. setting the lowest element.
4116 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4117 if (VT.getVectorElementType().getSizeInBits() < 32)
4119 if (!VT.is128BitVector())
4122 unsigned NumElts = VT.getVectorNumElements();
4124 if (!isUndefOrEqual(Mask[0], NumElts))
4127 for (unsigned i = 1; i != NumElts; ++i)
4128 if (!isUndefOrEqual(Mask[i], i))
4134 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4135 /// as permutations between 128-bit chunks or halves. As an example: this
4137 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4138 /// The first half comes from the second half of V1 and the second half from the
4139 /// the second half of V2.
4140 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4141 if (!HasFp256 || !VT.is256BitVector())
4144 // The shuffle result is divided into half A and half B. In total the two
4145 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4146 // B must come from C, D, E or F.
4147 unsigned HalfSize = VT.getVectorNumElements()/2;
4148 bool MatchA = false, MatchB = false;
4150 // Check if A comes from one of C, D, E, F.
4151 for (unsigned Half = 0; Half != 4; ++Half) {
4152 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4158 // Check if B comes from one of C, D, E, F.
4159 for (unsigned Half = 0; Half != 4; ++Half) {
4160 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4166 return MatchA && MatchB;
4169 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4170 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4171 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4172 MVT VT = SVOp->getSimpleValueType(0);
4174 unsigned HalfSize = VT.getVectorNumElements()/2;
4176 unsigned FstHalf = 0, SndHalf = 0;
4177 for (unsigned i = 0; i < HalfSize; ++i) {
4178 if (SVOp->getMaskElt(i) > 0) {
4179 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4183 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4184 if (SVOp->getMaskElt(i) > 0) {
4185 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4190 return (FstHalf | (SndHalf << 4));
4193 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4194 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4195 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4199 unsigned NumElts = VT.getVectorNumElements();
4201 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4202 for (unsigned i = 0; i != NumElts; ++i) {
4205 Imm8 |= Mask[i] << (i*2);
4210 unsigned LaneSize = 4;
4211 SmallVector<int, 4> MaskVal(LaneSize, -1);
4213 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4214 for (unsigned i = 0; i != LaneSize; ++i) {
4215 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4219 if (MaskVal[i] < 0) {
4220 MaskVal[i] = Mask[i+l] - l;
4221 Imm8 |= MaskVal[i] << (i*2);
4224 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4231 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4232 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4233 /// Note that VPERMIL mask matching is different depending whether theunderlying
4234 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4235 /// to the same elements of the low, but to the higher half of the source.
4236 /// In VPERMILPD the two lanes could be shuffled independently of each other
4237 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4238 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4239 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4240 if (VT.getSizeInBits() < 256 || EltSize < 32)
4242 bool symetricMaskRequired = (EltSize == 32);
4243 unsigned NumElts = VT.getVectorNumElements();
4245 unsigned NumLanes = VT.getSizeInBits()/128;
4246 unsigned LaneSize = NumElts/NumLanes;
4247 // 2 or 4 elements in one lane
4249 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4250 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4251 for (unsigned i = 0; i != LaneSize; ++i) {
4252 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4254 if (symetricMaskRequired) {
4255 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4256 ExpectedMaskVal[i] = Mask[i+l] - l;
4259 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4267 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4268 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4269 /// element of vector 2 and the other elements to come from vector 1 in order.
4270 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4271 bool V2IsSplat = false, bool V2IsUndef = false) {
4272 if (!VT.is128BitVector())
4275 unsigned NumOps = VT.getVectorNumElements();
4276 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4279 if (!isUndefOrEqual(Mask[0], 0))
4282 for (unsigned i = 1; i != NumOps; ++i)
4283 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4284 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4285 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4291 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4292 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4293 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4294 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4295 const X86Subtarget *Subtarget) {
4296 if (!Subtarget->hasSSE3())
4299 unsigned NumElems = VT.getVectorNumElements();
4301 if ((VT.is128BitVector() && NumElems != 4) ||
4302 (VT.is256BitVector() && NumElems != 8) ||
4303 (VT.is512BitVector() && NumElems != 16))
4306 // "i+1" is the value the indexed mask element must have
4307 for (unsigned i = 0; i != NumElems; i += 2)
4308 if (!isUndefOrEqual(Mask[i], i+1) ||
4309 !isUndefOrEqual(Mask[i+1], i+1))
4315 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4316 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4317 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4318 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4319 const X86Subtarget *Subtarget) {
4320 if (!Subtarget->hasSSE3())
4323 unsigned NumElems = VT.getVectorNumElements();
4325 if ((VT.is128BitVector() && NumElems != 4) ||
4326 (VT.is256BitVector() && NumElems != 8) ||
4327 (VT.is512BitVector() && NumElems != 16))
4330 // "i" is the value the indexed mask element must have
4331 for (unsigned i = 0; i != NumElems; i += 2)
4332 if (!isUndefOrEqual(Mask[i], i) ||
4333 !isUndefOrEqual(Mask[i+1], i))
4339 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4340 /// specifies a shuffle of elements that is suitable for input to 256-bit
4341 /// version of MOVDDUP.
4342 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4343 if (!HasFp256 || !VT.is256BitVector())
4346 unsigned NumElts = VT.getVectorNumElements();
4350 for (unsigned i = 0; i != NumElts/2; ++i)
4351 if (!isUndefOrEqual(Mask[i], 0))
4353 for (unsigned i = NumElts/2; i != NumElts; ++i)
4354 if (!isUndefOrEqual(Mask[i], NumElts/2))
4359 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4360 /// specifies a shuffle of elements that is suitable for input to 128-bit
4361 /// version of MOVDDUP.
4362 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4363 if (!VT.is128BitVector())
4366 unsigned e = VT.getVectorNumElements() / 2;
4367 for (unsigned i = 0; i != e; ++i)
4368 if (!isUndefOrEqual(Mask[i], i))
4370 for (unsigned i = 0; i != e; ++i)
4371 if (!isUndefOrEqual(Mask[e+i], i))
4376 /// isVEXTRACTIndex - Return true if the specified
4377 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4378 /// suitable for instruction that extract 128 or 256 bit vectors
4379 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4380 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4381 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4384 // The index should be aligned on a vecWidth-bit boundary.
4386 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4388 MVT VT = N->getSimpleValueType(0);
4389 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4390 bool Result = (Index * ElSize) % vecWidth == 0;
4395 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4396 /// operand specifies a subvector insert that is suitable for input to
4397 /// insertion of 128 or 256-bit subvectors
4398 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4399 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4400 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4402 // The index should be aligned on a vecWidth-bit boundary.
4404 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4406 MVT VT = N->getSimpleValueType(0);
4407 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4408 bool Result = (Index * ElSize) % vecWidth == 0;
4413 bool X86::isVINSERT128Index(SDNode *N) {
4414 return isVINSERTIndex(N, 128);
4417 bool X86::isVINSERT256Index(SDNode *N) {
4418 return isVINSERTIndex(N, 256);
4421 bool X86::isVEXTRACT128Index(SDNode *N) {
4422 return isVEXTRACTIndex(N, 128);
4425 bool X86::isVEXTRACT256Index(SDNode *N) {
4426 return isVEXTRACTIndex(N, 256);
4429 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4430 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4431 /// Handles 128-bit and 256-bit.
4432 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4433 MVT VT = N->getSimpleValueType(0);
4435 assert((VT.getSizeInBits() >= 128) &&
4436 "Unsupported vector type for PSHUF/SHUFP");
4438 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4439 // independently on 128-bit lanes.
4440 unsigned NumElts = VT.getVectorNumElements();
4441 unsigned NumLanes = VT.getSizeInBits()/128;
4442 unsigned NumLaneElts = NumElts/NumLanes;
4444 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4445 "Only supports 2, 4 or 8 elements per lane");
4447 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4449 for (unsigned i = 0; i != NumElts; ++i) {
4450 int Elt = N->getMaskElt(i);
4451 if (Elt < 0) continue;
4452 Elt &= NumLaneElts - 1;
4453 unsigned ShAmt = (i << Shift) % 8;
4454 Mask |= Elt << ShAmt;
4460 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4461 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4462 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4463 MVT VT = N->getSimpleValueType(0);
4465 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4466 "Unsupported vector type for PSHUFHW");
4468 unsigned NumElts = VT.getVectorNumElements();
4471 for (unsigned l = 0; l != NumElts; l += 8) {
4472 // 8 nodes per lane, but we only care about the last 4.
4473 for (unsigned i = 0; i < 4; ++i) {
4474 int Elt = N->getMaskElt(l+i+4);
4475 if (Elt < 0) continue;
4476 Elt &= 0x3; // only 2-bits.
4477 Mask |= Elt << (i * 2);
4484 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4485 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4486 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4487 MVT VT = N->getSimpleValueType(0);
4489 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4490 "Unsupported vector type for PSHUFHW");
4492 unsigned NumElts = VT.getVectorNumElements();
4495 for (unsigned l = 0; l != NumElts; l += 8) {
4496 // 8 nodes per lane, but we only care about the first 4.
4497 for (unsigned i = 0; i < 4; ++i) {
4498 int Elt = N->getMaskElt(l+i);
4499 if (Elt < 0) continue;
4500 Elt &= 0x3; // only 2-bits
4501 Mask |= Elt << (i * 2);
4508 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4509 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4510 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4511 MVT VT = SVOp->getSimpleValueType(0);
4512 unsigned EltSize = VT.is512BitVector() ? 1 :
4513 VT.getVectorElementType().getSizeInBits() >> 3;
4515 unsigned NumElts = VT.getVectorNumElements();
4516 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4517 unsigned NumLaneElts = NumElts/NumLanes;
4521 for (i = 0; i != NumElts; ++i) {
4522 Val = SVOp->getMaskElt(i);
4526 if (Val >= (int)NumElts)
4527 Val -= NumElts - NumLaneElts;
4529 assert(Val - i > 0 && "PALIGNR imm should be positive");
4530 return (Val - i) * EltSize;
4533 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4534 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4535 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4536 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4539 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4541 MVT VecVT = N->getOperand(0).getSimpleValueType();
4542 MVT ElVT = VecVT.getVectorElementType();
4544 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4545 return Index / NumElemsPerChunk;
4548 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4549 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4550 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4551 llvm_unreachable("Illegal insert subvector for VINSERT");
4554 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4556 MVT VecVT = N->getSimpleValueType(0);
4557 MVT ElVT = VecVT.getVectorElementType();
4559 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4560 return Index / NumElemsPerChunk;
4563 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4564 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4565 /// and VINSERTI128 instructions.
4566 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4567 return getExtractVEXTRACTImmediate(N, 128);
4570 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4571 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4572 /// and VINSERTI64x4 instructions.
4573 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4574 return getExtractVEXTRACTImmediate(N, 256);
4577 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4578 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4579 /// and VINSERTI128 instructions.
4580 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4581 return getInsertVINSERTImmediate(N, 128);
4584 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4585 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4586 /// and VINSERTI64x4 instructions.
4587 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4588 return getInsertVINSERTImmediate(N, 256);
4591 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4593 bool X86::isZeroNode(SDValue Elt) {
4594 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4595 return CN->isNullValue();
4596 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4597 return CFP->getValueAPF().isPosZero();
4601 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4602 /// their permute mask.
4603 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4604 SelectionDAG &DAG) {
4605 MVT VT = SVOp->getSimpleValueType(0);
4606 unsigned NumElems = VT.getVectorNumElements();
4607 SmallVector<int, 8> MaskVec;
4609 for (unsigned i = 0; i != NumElems; ++i) {
4610 int Idx = SVOp->getMaskElt(i);
4612 if (Idx < (int)NumElems)
4617 MaskVec.push_back(Idx);
4619 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4620 SVOp->getOperand(0), &MaskVec[0]);
4623 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4624 /// match movhlps. The lower half elements should come from upper half of
4625 /// V1 (and in order), and the upper half elements should come from the upper
4626 /// half of V2 (and in order).
4627 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4628 if (!VT.is128BitVector())
4630 if (VT.getVectorNumElements() != 4)
4632 for (unsigned i = 0, e = 2; i != e; ++i)
4633 if (!isUndefOrEqual(Mask[i], i+2))
4635 for (unsigned i = 2; i != 4; ++i)
4636 if (!isUndefOrEqual(Mask[i], i+4))
4641 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4642 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4644 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4645 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4647 N = N->getOperand(0).getNode();
4648 if (!ISD::isNON_EXTLoad(N))
4651 *LD = cast<LoadSDNode>(N);
4655 // Test whether the given value is a vector value which will be legalized
4657 static bool WillBeConstantPoolLoad(SDNode *N) {
4658 if (N->getOpcode() != ISD::BUILD_VECTOR)
4661 // Check for any non-constant elements.
4662 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4663 switch (N->getOperand(i).getNode()->getOpcode()) {
4665 case ISD::ConstantFP:
4672 // Vectors of all-zeros and all-ones are materialized with special
4673 // instructions rather than being loaded.
4674 return !ISD::isBuildVectorAllZeros(N) &&
4675 !ISD::isBuildVectorAllOnes(N);
4678 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4679 /// match movlp{s|d}. The lower half elements should come from lower half of
4680 /// V1 (and in order), and the upper half elements should come from the upper
4681 /// half of V2 (and in order). And since V1 will become the source of the
4682 /// MOVLP, it must be either a vector load or a scalar load to vector.
4683 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4684 ArrayRef<int> Mask, MVT VT) {
4685 if (!VT.is128BitVector())
4688 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4690 // Is V2 is a vector load, don't do this transformation. We will try to use
4691 // load folding shufps op.
4692 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4695 unsigned NumElems = VT.getVectorNumElements();
4697 if (NumElems != 2 && NumElems != 4)
4699 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4700 if (!isUndefOrEqual(Mask[i], i))
4702 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4703 if (!isUndefOrEqual(Mask[i], i+NumElems))
4708 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4710 static bool isSplatVector(SDNode *N) {
4711 if (N->getOpcode() != ISD::BUILD_VECTOR)
4714 SDValue SplatValue = N->getOperand(0);
4715 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4716 if (N->getOperand(i) != SplatValue)
4721 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4722 /// to an zero vector.
4723 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4724 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4725 SDValue V1 = N->getOperand(0);
4726 SDValue V2 = N->getOperand(1);
4727 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4728 for (unsigned i = 0; i != NumElems; ++i) {
4729 int Idx = N->getMaskElt(i);
4730 if (Idx >= (int)NumElems) {
4731 unsigned Opc = V2.getOpcode();
4732 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4734 if (Opc != ISD::BUILD_VECTOR ||
4735 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4737 } else if (Idx >= 0) {
4738 unsigned Opc = V1.getOpcode();
4739 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4741 if (Opc != ISD::BUILD_VECTOR ||
4742 !X86::isZeroNode(V1.getOperand(Idx)))
4749 /// getZeroVector - Returns a vector of specified type with all zero elements.
4751 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4752 SelectionDAG &DAG, SDLoc dl) {
4753 assert(VT.isVector() && "Expected a vector type");
4755 // Always build SSE zero vectors as <4 x i32> bitcasted
4756 // to their dest type. This ensures they get CSE'd.
4758 if (VT.is128BitVector()) { // SSE
4759 if (Subtarget->hasSSE2()) { // SSE2
4760 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4761 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4763 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4764 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4766 } else if (VT.is256BitVector()) { // AVX
4767 if (Subtarget->hasInt256()) { // AVX2
4768 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4769 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4770 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4771 array_lengthof(Ops));
4773 // 256-bit logic and arithmetic instructions in AVX are all
4774 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4775 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4776 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4777 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4778 array_lengthof(Ops));
4780 } else if (VT.is512BitVector()) { // AVX-512
4781 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4782 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4783 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4784 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4786 llvm_unreachable("Unexpected vector type");
4788 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4791 /// getOnesVector - Returns a vector of specified type with all bits set.
4792 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4793 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4794 /// Then bitcast to their original type, ensuring they get CSE'd.
4795 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4797 assert(VT.isVector() && "Expected a vector type");
4799 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4801 if (VT.is256BitVector()) {
4802 if (HasInt256) { // AVX2
4803 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4804 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4805 array_lengthof(Ops));
4807 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4808 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4810 } else if (VT.is128BitVector()) {
4811 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4813 llvm_unreachable("Unexpected vector type");
4815 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4818 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4819 /// that point to V2 points to its first element.
4820 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4821 for (unsigned i = 0; i != NumElems; ++i) {
4822 if (Mask[i] > (int)NumElems) {
4828 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4829 /// operation of specified width.
4830 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4832 unsigned NumElems = VT.getVectorNumElements();
4833 SmallVector<int, 8> Mask;
4834 Mask.push_back(NumElems);
4835 for (unsigned i = 1; i != NumElems; ++i)
4837 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4840 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4841 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4843 unsigned NumElems = VT.getVectorNumElements();
4844 SmallVector<int, 8> Mask;
4845 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4847 Mask.push_back(i + NumElems);
4849 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4852 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4853 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4855 unsigned NumElems = VT.getVectorNumElements();
4856 SmallVector<int, 8> Mask;
4857 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4858 Mask.push_back(i + Half);
4859 Mask.push_back(i + NumElems + Half);
4861 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4864 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4865 // a generic shuffle instruction because the target has no such instructions.
4866 // Generate shuffles which repeat i16 and i8 several times until they can be
4867 // represented by v4f32 and then be manipulated by target suported shuffles.
4868 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4869 MVT VT = V.getSimpleValueType();
4870 int NumElems = VT.getVectorNumElements();
4873 while (NumElems > 4) {
4874 if (EltNo < NumElems/2) {
4875 V = getUnpackl(DAG, dl, VT, V, V);
4877 V = getUnpackh(DAG, dl, VT, V, V);
4878 EltNo -= NumElems/2;
4885 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4886 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4887 MVT VT = V.getSimpleValueType();
4890 if (VT.is128BitVector()) {
4891 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4892 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4893 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4895 } else if (VT.is256BitVector()) {
4896 // To use VPERMILPS to splat scalars, the second half of indicies must
4897 // refer to the higher part, which is a duplication of the lower one,
4898 // because VPERMILPS can only handle in-lane permutations.
4899 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4900 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4902 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4903 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4906 llvm_unreachable("Vector size not supported");
4908 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4911 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4912 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4913 MVT SrcVT = SV->getSimpleValueType(0);
4914 SDValue V1 = SV->getOperand(0);
4917 int EltNo = SV->getSplatIndex();
4918 int NumElems = SrcVT.getVectorNumElements();
4919 bool Is256BitVec = SrcVT.is256BitVector();
4921 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4922 "Unknown how to promote splat for type");
4924 // Extract the 128-bit part containing the splat element and update
4925 // the splat element index when it refers to the higher register.
4927 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4928 if (EltNo >= NumElems/2)
4929 EltNo -= NumElems/2;
4932 // All i16 and i8 vector types can't be used directly by a generic shuffle
4933 // instruction because the target has no such instruction. Generate shuffles
4934 // which repeat i16 and i8 several times until they fit in i32, and then can
4935 // be manipulated by target suported shuffles.
4936 MVT EltVT = SrcVT.getVectorElementType();
4937 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4938 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4940 // Recreate the 256-bit vector and place the same 128-bit vector
4941 // into the low and high part. This is necessary because we want
4942 // to use VPERM* to shuffle the vectors
4944 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4947 return getLegalSplat(DAG, V1, EltNo);
4950 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4951 /// vector of zero or undef vector. This produces a shuffle where the low
4952 /// element of V2 is swizzled into the zero/undef vector, landing at element
4953 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4954 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4956 const X86Subtarget *Subtarget,
4957 SelectionDAG &DAG) {
4958 MVT VT = V2.getSimpleValueType();
4960 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4961 unsigned NumElems = VT.getVectorNumElements();
4962 SmallVector<int, 16> MaskVec;
4963 for (unsigned i = 0; i != NumElems; ++i)
4964 // If this is the insertion idx, put the low elt of V2 here.
4965 MaskVec.push_back(i == Idx ? NumElems : i);
4966 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4969 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4970 /// target specific opcode. Returns true if the Mask could be calculated.
4971 /// Sets IsUnary to true if only uses one source.
4972 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4973 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4974 unsigned NumElems = VT.getVectorNumElements();
4978 switch(N->getOpcode()) {
4980 ImmN = N->getOperand(N->getNumOperands()-1);
4981 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4983 case X86ISD::UNPCKH:
4984 DecodeUNPCKHMask(VT, Mask);
4986 case X86ISD::UNPCKL:
4987 DecodeUNPCKLMask(VT, Mask);
4989 case X86ISD::MOVHLPS:
4990 DecodeMOVHLPSMask(NumElems, Mask);
4992 case X86ISD::MOVLHPS:
4993 DecodeMOVLHPSMask(NumElems, Mask);
4995 case X86ISD::PALIGNR:
4996 ImmN = N->getOperand(N->getNumOperands()-1);
4997 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4999 case X86ISD::PSHUFD:
5000 case X86ISD::VPERMILP:
5001 ImmN = N->getOperand(N->getNumOperands()-1);
5002 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5005 case X86ISD::PSHUFHW:
5006 ImmN = N->getOperand(N->getNumOperands()-1);
5007 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5010 case X86ISD::PSHUFLW:
5011 ImmN = N->getOperand(N->getNumOperands()-1);
5012 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5015 case X86ISD::VPERMI:
5016 ImmN = N->getOperand(N->getNumOperands()-1);
5017 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5021 case X86ISD::MOVSD: {
5022 // The index 0 always comes from the first element of the second source,
5023 // this is why MOVSS and MOVSD are used in the first place. The other
5024 // elements come from the other positions of the first source vector
5025 Mask.push_back(NumElems);
5026 for (unsigned i = 1; i != NumElems; ++i) {
5031 case X86ISD::VPERM2X128:
5032 ImmN = N->getOperand(N->getNumOperands()-1);
5033 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5034 if (Mask.empty()) return false;
5036 case X86ISD::MOVDDUP:
5037 case X86ISD::MOVLHPD:
5038 case X86ISD::MOVLPD:
5039 case X86ISD::MOVLPS:
5040 case X86ISD::MOVSHDUP:
5041 case X86ISD::MOVSLDUP:
5042 // Not yet implemented
5044 default: llvm_unreachable("unknown target shuffle node");
5050 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5051 /// element of the result of the vector shuffle.
5052 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5055 return SDValue(); // Limit search depth.
5057 SDValue V = SDValue(N, 0);
5058 EVT VT = V.getValueType();
5059 unsigned Opcode = V.getOpcode();
5061 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5062 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5063 int Elt = SV->getMaskElt(Index);
5066 return DAG.getUNDEF(VT.getVectorElementType());
5068 unsigned NumElems = VT.getVectorNumElements();
5069 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5070 : SV->getOperand(1);
5071 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5074 // Recurse into target specific vector shuffles to find scalars.
5075 if (isTargetShuffle(Opcode)) {
5076 MVT ShufVT = V.getSimpleValueType();
5077 unsigned NumElems = ShufVT.getVectorNumElements();
5078 SmallVector<int, 16> ShuffleMask;
5081 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5084 int Elt = ShuffleMask[Index];
5086 return DAG.getUNDEF(ShufVT.getVectorElementType());
5088 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5090 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5094 // Actual nodes that may contain scalar elements
5095 if (Opcode == ISD::BITCAST) {
5096 V = V.getOperand(0);
5097 EVT SrcVT = V.getValueType();
5098 unsigned NumElems = VT.getVectorNumElements();
5100 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5104 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5105 return (Index == 0) ? V.getOperand(0)
5106 : DAG.getUNDEF(VT.getVectorElementType());
5108 if (V.getOpcode() == ISD::BUILD_VECTOR)
5109 return V.getOperand(Index);
5114 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5115 /// shuffle operation which come from a consecutively from a zero. The
5116 /// search can start in two different directions, from left or right.
5117 /// We count undefs as zeros until PreferredNum is reached.
5118 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5119 unsigned NumElems, bool ZerosFromLeft,
5121 unsigned PreferredNum = -1U) {
5122 unsigned NumZeros = 0;
5123 for (unsigned i = 0; i != NumElems; ++i) {
5124 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5125 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5129 if (X86::isZeroNode(Elt))
5131 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5132 NumZeros = std::min(NumZeros + 1, PreferredNum);
5140 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5141 /// correspond consecutively to elements from one of the vector operands,
5142 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5144 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5145 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5146 unsigned NumElems, unsigned &OpNum) {
5147 bool SeenV1 = false;
5148 bool SeenV2 = false;
5150 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5151 int Idx = SVOp->getMaskElt(i);
5152 // Ignore undef indicies
5156 if (Idx < (int)NumElems)
5161 // Only accept consecutive elements from the same vector
5162 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5166 OpNum = SeenV1 ? 0 : 1;
5170 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5171 /// logical left shift of a vector.
5172 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5173 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5175 SVOp->getSimpleValueType(0).getVectorNumElements();
5176 unsigned NumZeros = getNumOfConsecutiveZeros(
5177 SVOp, NumElems, false /* check zeros from right */, DAG,
5178 SVOp->getMaskElt(0));
5184 // Considering the elements in the mask that are not consecutive zeros,
5185 // check if they consecutively come from only one of the source vectors.
5187 // V1 = {X, A, B, C} 0
5189 // vector_shuffle V1, V2 <1, 2, 3, X>
5191 if (!isShuffleMaskConsecutive(SVOp,
5192 0, // Mask Start Index
5193 NumElems-NumZeros, // Mask End Index(exclusive)
5194 NumZeros, // Where to start looking in the src vector
5195 NumElems, // Number of elements in vector
5196 OpSrc)) // Which source operand ?
5201 ShVal = SVOp->getOperand(OpSrc);
5205 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5206 /// logical left shift of a vector.
5207 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5208 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5210 SVOp->getSimpleValueType(0).getVectorNumElements();
5211 unsigned NumZeros = getNumOfConsecutiveZeros(
5212 SVOp, NumElems, true /* check zeros from left */, DAG,
5213 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5219 // Considering the elements in the mask that are not consecutive zeros,
5220 // check if they consecutively come from only one of the source vectors.
5222 // 0 { A, B, X, X } = V2
5224 // vector_shuffle V1, V2 <X, X, 4, 5>
5226 if (!isShuffleMaskConsecutive(SVOp,
5227 NumZeros, // Mask Start Index
5228 NumElems, // Mask End Index(exclusive)
5229 0, // Where to start looking in the src vector
5230 NumElems, // Number of elements in vector
5231 OpSrc)) // Which source operand ?
5236 ShVal = SVOp->getOperand(OpSrc);
5240 /// isVectorShift - Returns true if the shuffle can be implemented as a
5241 /// logical left or right shift of a vector.
5242 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5243 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5244 // Although the logic below support any bitwidth size, there are no
5245 // shift instructions which handle more than 128-bit vectors.
5246 if (!SVOp->getSimpleValueType(0).is128BitVector())
5249 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5250 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5256 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5258 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5259 unsigned NumNonZero, unsigned NumZero,
5261 const X86Subtarget* Subtarget,
5262 const TargetLowering &TLI) {
5269 for (unsigned i = 0; i < 16; ++i) {
5270 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5271 if (ThisIsNonZero && First) {
5273 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5275 V = DAG.getUNDEF(MVT::v8i16);
5280 SDValue ThisElt(0, 0), LastElt(0, 0);
5281 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5282 if (LastIsNonZero) {
5283 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5284 MVT::i16, Op.getOperand(i-1));
5286 if (ThisIsNonZero) {
5287 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5288 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5289 ThisElt, DAG.getConstant(8, MVT::i8));
5291 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5295 if (ThisElt.getNode())
5296 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5297 DAG.getIntPtrConstant(i/2));
5301 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5304 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5306 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5307 unsigned NumNonZero, unsigned NumZero,
5309 const X86Subtarget* Subtarget,
5310 const TargetLowering &TLI) {
5317 for (unsigned i = 0; i < 8; ++i) {
5318 bool isNonZero = (NonZeros & (1 << i)) != 0;
5322 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5324 V = DAG.getUNDEF(MVT::v8i16);
5327 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5328 MVT::v8i16, V, Op.getOperand(i),
5329 DAG.getIntPtrConstant(i));
5336 /// getVShift - Return a vector logical shift node.
5338 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5339 unsigned NumBits, SelectionDAG &DAG,
5340 const TargetLowering &TLI, SDLoc dl) {
5341 assert(VT.is128BitVector() && "Unknown type for VShift");
5342 EVT ShVT = MVT::v2i64;
5343 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5344 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5345 return DAG.getNode(ISD::BITCAST, dl, VT,
5346 DAG.getNode(Opc, dl, ShVT, SrcOp,
5347 DAG.getConstant(NumBits,
5348 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5352 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5354 // Check if the scalar load can be widened into a vector load. And if
5355 // the address is "base + cst" see if the cst can be "absorbed" into
5356 // the shuffle mask.
5357 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5358 SDValue Ptr = LD->getBasePtr();
5359 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5361 EVT PVT = LD->getValueType(0);
5362 if (PVT != MVT::i32 && PVT != MVT::f32)
5367 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5368 FI = FINode->getIndex();
5370 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5371 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5372 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5373 Offset = Ptr.getConstantOperandVal(1);
5374 Ptr = Ptr.getOperand(0);
5379 // FIXME: 256-bit vector instructions don't require a strict alignment,
5380 // improve this code to support it better.
5381 unsigned RequiredAlign = VT.getSizeInBits()/8;
5382 SDValue Chain = LD->getChain();
5383 // Make sure the stack object alignment is at least 16 or 32.
5384 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5385 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5386 if (MFI->isFixedObjectIndex(FI)) {
5387 // Can't change the alignment. FIXME: It's possible to compute
5388 // the exact stack offset and reference FI + adjust offset instead.
5389 // If someone *really* cares about this. That's the way to implement it.
5392 MFI->setObjectAlignment(FI, RequiredAlign);
5396 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5397 // Ptr + (Offset & ~15).
5400 if ((Offset % RequiredAlign) & 3)
5402 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5404 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5405 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5407 int EltNo = (Offset - StartOffset) >> 2;
5408 unsigned NumElems = VT.getVectorNumElements();
5410 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5411 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5412 LD->getPointerInfo().getWithOffset(StartOffset),
5413 false, false, false, 0);
5415 SmallVector<int, 8> Mask;
5416 for (unsigned i = 0; i != NumElems; ++i)
5417 Mask.push_back(EltNo);
5419 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5425 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5426 /// vector of type 'VT', see if the elements can be replaced by a single large
5427 /// load which has the same value as a build_vector whose operands are 'elts'.
5429 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5431 /// FIXME: we'd also like to handle the case where the last elements are zero
5432 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5433 /// There's even a handy isZeroNode for that purpose.
5434 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5435 SDLoc &DL, SelectionDAG &DAG,
5436 bool isAfterLegalize) {
5437 EVT EltVT = VT.getVectorElementType();
5438 unsigned NumElems = Elts.size();
5440 LoadSDNode *LDBase = NULL;
5441 unsigned LastLoadedElt = -1U;
5443 // For each element in the initializer, see if we've found a load or an undef.
5444 // If we don't find an initial load element, or later load elements are
5445 // non-consecutive, bail out.
5446 for (unsigned i = 0; i < NumElems; ++i) {
5447 SDValue Elt = Elts[i];
5449 if (!Elt.getNode() ||
5450 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5453 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5455 LDBase = cast<LoadSDNode>(Elt.getNode());
5459 if (Elt.getOpcode() == ISD::UNDEF)
5462 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5463 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5468 // If we have found an entire vector of loads and undefs, then return a large
5469 // load of the entire vector width starting at the base pointer. If we found
5470 // consecutive loads for the low half, generate a vzext_load node.
5471 if (LastLoadedElt == NumElems - 1) {
5473 if (isAfterLegalize &&
5474 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5477 SDValue NewLd = SDValue();
5479 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5480 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5481 LDBase->getPointerInfo(),
5482 LDBase->isVolatile(), LDBase->isNonTemporal(),
5483 LDBase->isInvariant(), 0);
5484 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5485 LDBase->getPointerInfo(),
5486 LDBase->isVolatile(), LDBase->isNonTemporal(),
5487 LDBase->isInvariant(), LDBase->getAlignment());
5489 if (LDBase->hasAnyUseOfValue(1)) {
5490 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5492 SDValue(NewLd.getNode(), 1));
5493 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5494 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5495 SDValue(NewLd.getNode(), 1));
5500 if (NumElems == 4 && LastLoadedElt == 1 &&
5501 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5502 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5503 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5505 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5506 array_lengthof(Ops), MVT::i64,
5507 LDBase->getPointerInfo(),
5508 LDBase->getAlignment(),
5509 false/*isVolatile*/, true/*ReadMem*/,
5512 // Make sure the newly-created LOAD is in the same position as LDBase in
5513 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5514 // update uses of LDBase's output chain to use the TokenFactor.
5515 if (LDBase->hasAnyUseOfValue(1)) {
5516 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5517 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5518 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5519 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5520 SDValue(ResNode.getNode(), 1));
5523 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5528 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5529 /// to generate a splat value for the following cases:
5530 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5531 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5532 /// a scalar load, or a constant.
5533 /// The VBROADCAST node is returned when a pattern is found,
5534 /// or SDValue() otherwise.
5535 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5536 SelectionDAG &DAG) {
5537 if (!Subtarget->hasFp256())
5540 MVT VT = Op.getSimpleValueType();
5543 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5544 "Unsupported vector type for broadcast.");
5549 switch (Op.getOpcode()) {
5551 // Unknown pattern found.
5554 case ISD::BUILD_VECTOR: {
5555 // The BUILD_VECTOR node must be a splat.
5556 if (!isSplatVector(Op.getNode()))
5559 Ld = Op.getOperand(0);
5560 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5561 Ld.getOpcode() == ISD::ConstantFP);
5563 // The suspected load node has several users. Make sure that all
5564 // of its users are from the BUILD_VECTOR node.
5565 // Constants may have multiple users.
5566 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5571 case ISD::VECTOR_SHUFFLE: {
5572 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5574 // Shuffles must have a splat mask where the first element is
5576 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5579 SDValue Sc = Op.getOperand(0);
5580 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5581 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5583 if (!Subtarget->hasInt256())
5586 // Use the register form of the broadcast instruction available on AVX2.
5587 if (VT.getSizeInBits() >= 256)
5588 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5589 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5592 Ld = Sc.getOperand(0);
5593 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5594 Ld.getOpcode() == ISD::ConstantFP);
5596 // The scalar_to_vector node and the suspected
5597 // load node must have exactly one user.
5598 // Constants may have multiple users.
5600 // AVX-512 has register version of the broadcast
5601 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5602 Ld.getValueType().getSizeInBits() >= 32;
5603 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5610 bool IsGE256 = (VT.getSizeInBits() >= 256);
5612 // Handle the broadcasting a single constant scalar from the constant pool
5613 // into a vector. On Sandybridge it is still better to load a constant vector
5614 // from the constant pool and not to broadcast it from a scalar.
5615 if (ConstSplatVal && Subtarget->hasInt256()) {
5616 EVT CVT = Ld.getValueType();
5617 assert(!CVT.isVector() && "Must not broadcast a vector type");
5618 unsigned ScalarSize = CVT.getSizeInBits();
5620 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5621 const Constant *C = 0;
5622 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5623 C = CI->getConstantIntValue();
5624 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5625 C = CF->getConstantFPValue();
5627 assert(C && "Invalid constant type");
5629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5630 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5631 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5632 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5633 MachinePointerInfo::getConstantPool(),
5634 false, false, false, Alignment);
5636 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5640 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5641 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5643 // Handle AVX2 in-register broadcasts.
5644 if (!IsLoad && Subtarget->hasInt256() &&
5645 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5646 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5648 // The scalar source must be a normal load.
5652 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5653 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5655 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5656 // double since there is no vbroadcastsd xmm
5657 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5658 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5659 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5662 // Unsupported broadcast.
5666 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5667 MVT VT = Op.getSimpleValueType();
5669 // Skip if insert_vec_elt is not supported.
5670 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5671 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5675 unsigned NumElems = Op.getNumOperands();
5679 SmallVector<unsigned, 4> InsertIndices;
5680 SmallVector<int, 8> Mask(NumElems, -1);
5682 for (unsigned i = 0; i != NumElems; ++i) {
5683 unsigned Opc = Op.getOperand(i).getOpcode();
5685 if (Opc == ISD::UNDEF)
5688 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5689 // Quit if more than 1 elements need inserting.
5690 if (InsertIndices.size() > 1)
5693 InsertIndices.push_back(i);
5697 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5698 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5700 // Quit if extracted from vector of different type.
5701 if (ExtractedFromVec.getValueType() != VT)
5704 // Quit if non-constant index.
5705 if (!isa<ConstantSDNode>(ExtIdx))
5708 if (VecIn1.getNode() == 0)
5709 VecIn1 = ExtractedFromVec;
5710 else if (VecIn1 != ExtractedFromVec) {
5711 if (VecIn2.getNode() == 0)
5712 VecIn2 = ExtractedFromVec;
5713 else if (VecIn2 != ExtractedFromVec)
5714 // Quit if more than 2 vectors to shuffle
5718 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5720 if (ExtractedFromVec == VecIn1)
5722 else if (ExtractedFromVec == VecIn2)
5723 Mask[i] = Idx + NumElems;
5726 if (VecIn1.getNode() == 0)
5729 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5730 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5731 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5732 unsigned Idx = InsertIndices[i];
5733 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5734 DAG.getIntPtrConstant(Idx));
5740 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5742 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5744 MVT VT = Op.getSimpleValueType();
5745 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5746 "Unexpected type in LowerBUILD_VECTORvXi1!");
5749 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5750 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5751 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5752 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5753 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5754 Ops, VT.getVectorNumElements());
5757 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5758 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5759 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5760 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5761 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5762 Ops, VT.getVectorNumElements());
5765 bool AllContants = true;
5766 uint64_t Immediate = 0;
5767 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5768 SDValue In = Op.getOperand(idx);
5769 if (In.getOpcode() == ISD::UNDEF)
5771 if (!isa<ConstantSDNode>(In)) {
5772 AllContants = false;
5775 if (cast<ConstantSDNode>(In)->getZExtValue())
5776 Immediate |= (1ULL << idx);
5780 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5781 DAG.getConstant(Immediate, MVT::i16));
5782 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5783 DAG.getIntPtrConstant(0));
5786 // Splat vector (with undefs)
5787 SDValue In = Op.getOperand(0);
5788 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5789 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5790 llvm_unreachable("Unsupported predicate operation");
5793 SDValue EFLAGS, X86CC;
5794 if (In.getOpcode() == ISD::SETCC) {
5795 SDValue Op0 = In.getOperand(0);
5796 SDValue Op1 = In.getOperand(1);
5797 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5798 bool isFP = Op1.getValueType().isFloatingPoint();
5799 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5801 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5803 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5804 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5805 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5806 } else if (In.getOpcode() == X86ISD::SETCC) {
5807 X86CC = In.getOperand(0);
5808 EFLAGS = In.getOperand(1);
5817 // res = allOnes ### CMOVNE -1, %res
5820 MVT InVT = In.getSimpleValueType();
5821 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5822 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5823 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5826 if (VT == MVT::v16i1) {
5827 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5828 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5829 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5830 Cst0, Cst1, X86CC, EFLAGS);
5831 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5834 if (VT == MVT::v8i1) {
5835 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5836 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5837 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5838 Cst0, Cst1, X86CC, EFLAGS);
5839 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5840 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5842 llvm_unreachable("Unsupported predicate operation");
5846 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5849 MVT VT = Op.getSimpleValueType();
5850 MVT ExtVT = VT.getVectorElementType();
5851 unsigned NumElems = Op.getNumOperands();
5853 // Generate vectors for predicate vectors.
5854 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5855 return LowerBUILD_VECTORvXi1(Op, DAG);
5857 // Vectors containing all zeros can be matched by pxor and xorps later
5858 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5859 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5860 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5861 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5864 return getZeroVector(VT, Subtarget, DAG, dl);
5867 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5868 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5869 // vpcmpeqd on 256-bit vectors.
5870 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5871 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5874 if (!VT.is512BitVector())
5875 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5878 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5879 if (Broadcast.getNode())
5882 unsigned EVTBits = ExtVT.getSizeInBits();
5884 unsigned NumZero = 0;
5885 unsigned NumNonZero = 0;
5886 unsigned NonZeros = 0;
5887 bool IsAllConstants = true;
5888 SmallSet<SDValue, 8> Values;
5889 for (unsigned i = 0; i < NumElems; ++i) {
5890 SDValue Elt = Op.getOperand(i);
5891 if (Elt.getOpcode() == ISD::UNDEF)
5894 if (Elt.getOpcode() != ISD::Constant &&
5895 Elt.getOpcode() != ISD::ConstantFP)
5896 IsAllConstants = false;
5897 if (X86::isZeroNode(Elt))
5900 NonZeros |= (1 << i);
5905 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5906 if (NumNonZero == 0)
5907 return DAG.getUNDEF(VT);
5909 // Special case for single non-zero, non-undef, element.
5910 if (NumNonZero == 1) {
5911 unsigned Idx = countTrailingZeros(NonZeros);
5912 SDValue Item = Op.getOperand(Idx);
5914 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5915 // the value are obviously zero, truncate the value to i32 and do the
5916 // insertion that way. Only do this if the value is non-constant or if the
5917 // value is a constant being inserted into element 0. It is cheaper to do
5918 // a constant pool load than it is to do a movd + shuffle.
5919 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5920 (!IsAllConstants || Idx == 0)) {
5921 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5923 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5924 EVT VecVT = MVT::v4i32;
5925 unsigned VecElts = 4;
5927 // Truncate the value (which may itself be a constant) to i32, and
5928 // convert it to a vector with movd (S2V+shuffle to zero extend).
5929 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5930 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5931 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5933 // Now we have our 32-bit value zero extended in the low element of
5934 // a vector. If Idx != 0, swizzle it into place.
5936 SmallVector<int, 4> Mask;
5937 Mask.push_back(Idx);
5938 for (unsigned i = 1; i != VecElts; ++i)
5940 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5943 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5947 // If we have a constant or non-constant insertion into the low element of
5948 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5949 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5950 // depending on what the source datatype is.
5953 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5955 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5956 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5957 if (VT.is256BitVector() || VT.is512BitVector()) {
5958 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5959 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5960 Item, DAG.getIntPtrConstant(0));
5962 assert(VT.is128BitVector() && "Expected an SSE value type!");
5963 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5964 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5965 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5968 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5969 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5970 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5971 if (VT.is256BitVector()) {
5972 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5973 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5975 assert(VT.is128BitVector() && "Expected an SSE value type!");
5976 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5978 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5982 // Is it a vector logical left shift?
5983 if (NumElems == 2 && Idx == 1 &&
5984 X86::isZeroNode(Op.getOperand(0)) &&
5985 !X86::isZeroNode(Op.getOperand(1))) {
5986 unsigned NumBits = VT.getSizeInBits();
5987 return getVShift(true, VT,
5988 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5989 VT, Op.getOperand(1)),
5990 NumBits/2, DAG, *this, dl);
5993 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5996 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5997 // is a non-constant being inserted into an element other than the low one,
5998 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5999 // movd/movss) to move this into the low element, then shuffle it into
6001 if (EVTBits == 32) {
6002 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6004 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6005 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6006 SmallVector<int, 8> MaskVec;
6007 for (unsigned i = 0; i != NumElems; ++i)
6008 MaskVec.push_back(i == Idx ? 0 : 1);
6009 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6013 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6014 if (Values.size() == 1) {
6015 if (EVTBits == 32) {
6016 // Instead of a shuffle like this:
6017 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6018 // Check if it's possible to issue this instead.
6019 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6020 unsigned Idx = countTrailingZeros(NonZeros);
6021 SDValue Item = Op.getOperand(Idx);
6022 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6023 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6028 // A vector full of immediates; various special cases are already
6029 // handled, so this is best done with a single constant-pool load.
6033 // For AVX-length vectors, build the individual 128-bit pieces and use
6034 // shuffles to put them in place.
6035 if (VT.is256BitVector()) {
6036 SmallVector<SDValue, 32> V;
6037 for (unsigned i = 0; i != NumElems; ++i)
6038 V.push_back(Op.getOperand(i));
6040 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6042 // Build both the lower and upper subvector.
6043 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6044 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6047 // Recreate the wider vector with the lower and upper part.
6048 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6051 // Let legalizer expand 2-wide build_vectors.
6052 if (EVTBits == 64) {
6053 if (NumNonZero == 1) {
6054 // One half is zero or undef.
6055 unsigned Idx = countTrailingZeros(NonZeros);
6056 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6057 Op.getOperand(Idx));
6058 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6063 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6064 if (EVTBits == 8 && NumElems == 16) {
6065 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6067 if (V.getNode()) return V;
6070 if (EVTBits == 16 && NumElems == 8) {
6071 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6073 if (V.getNode()) return V;
6076 // If element VT is == 32 bits, turn it into a number of shuffles.
6077 SmallVector<SDValue, 8> V(NumElems);
6078 if (NumElems == 4 && NumZero > 0) {
6079 for (unsigned i = 0; i < 4; ++i) {
6080 bool isZero = !(NonZeros & (1 << i));
6082 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6084 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6087 for (unsigned i = 0; i < 2; ++i) {
6088 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6091 V[i] = V[i*2]; // Must be a zero vector.
6094 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6097 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6100 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6105 bool Reverse1 = (NonZeros & 0x3) == 2;
6106 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6110 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6111 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6113 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6116 if (Values.size() > 1 && VT.is128BitVector()) {
6117 // Check for a build vector of consecutive loads.
6118 for (unsigned i = 0; i < NumElems; ++i)
6119 V[i] = Op.getOperand(i);
6121 // Check for elements which are consecutive loads.
6122 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6126 // Check for a build vector from mostly shuffle plus few inserting.
6127 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6131 // For SSE 4.1, use insertps to put the high elements into the low element.
6132 if (getSubtarget()->hasSSE41()) {
6134 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6135 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6137 Result = DAG.getUNDEF(VT);
6139 for (unsigned i = 1; i < NumElems; ++i) {
6140 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6141 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6142 Op.getOperand(i), DAG.getIntPtrConstant(i));
6147 // Otherwise, expand into a number of unpckl*, start by extending each of
6148 // our (non-undef) elements to the full vector width with the element in the
6149 // bottom slot of the vector (which generates no code for SSE).
6150 for (unsigned i = 0; i < NumElems; ++i) {
6151 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6152 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6154 V[i] = DAG.getUNDEF(VT);
6157 // Next, we iteratively mix elements, e.g. for v4f32:
6158 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6159 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6160 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6161 unsigned EltStride = NumElems >> 1;
6162 while (EltStride != 0) {
6163 for (unsigned i = 0; i < EltStride; ++i) {
6164 // If V[i+EltStride] is undef and this is the first round of mixing,
6165 // then it is safe to just drop this shuffle: V[i] is already in the
6166 // right place, the one element (since it's the first round) being
6167 // inserted as undef can be dropped. This isn't safe for successive
6168 // rounds because they will permute elements within both vectors.
6169 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6170 EltStride == NumElems/2)
6173 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6182 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6183 // to create 256-bit vectors from two other 128-bit ones.
6184 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6186 MVT ResVT = Op.getSimpleValueType();
6188 assert((ResVT.is256BitVector() ||
6189 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6191 SDValue V1 = Op.getOperand(0);
6192 SDValue V2 = Op.getOperand(1);
6193 unsigned NumElems = ResVT.getVectorNumElements();
6194 if(ResVT.is256BitVector())
6195 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6197 if (Op.getNumOperands() == 4) {
6198 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6199 ResVT.getVectorNumElements()/2);
6200 SDValue V3 = Op.getOperand(2);
6201 SDValue V4 = Op.getOperand(3);
6202 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6203 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6205 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6208 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6209 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6210 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6211 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6212 Op.getNumOperands() == 4)));
6214 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6215 // from two other 128-bit ones.
6217 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6218 return LowerAVXCONCAT_VECTORS(Op, DAG);
6221 // Try to lower a shuffle node into a simple blend instruction.
6223 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6224 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6225 SDValue V1 = SVOp->getOperand(0);
6226 SDValue V2 = SVOp->getOperand(1);
6228 MVT VT = SVOp->getSimpleValueType(0);
6229 MVT EltVT = VT.getVectorElementType();
6230 unsigned NumElems = VT.getVectorNumElements();
6232 // There is no blend with immediate in AVX-512.
6233 if (VT.is512BitVector())
6236 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6238 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6241 // Check the mask for BLEND and build the value.
6242 unsigned MaskValue = 0;
6243 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6244 unsigned NumLanes = (NumElems-1)/8 + 1;
6245 unsigned NumElemsInLane = NumElems / NumLanes;
6247 // Blend for v16i16 should be symetric for the both lanes.
6248 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6250 int SndLaneEltIdx = (NumLanes == 2) ?
6251 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6252 int EltIdx = SVOp->getMaskElt(i);
6254 if ((EltIdx < 0 || EltIdx == (int)i) &&
6255 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6258 if (((unsigned)EltIdx == (i + NumElems)) &&
6259 (SndLaneEltIdx < 0 ||
6260 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6261 MaskValue |= (1<<i);
6266 // Convert i32 vectors to floating point if it is not AVX2.
6267 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6269 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6270 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6272 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6273 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6276 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6277 DAG.getConstant(MaskValue, MVT::i32));
6278 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6281 // v8i16 shuffles - Prefer shuffles in the following order:
6282 // 1. [all] pshuflw, pshufhw, optional move
6283 // 2. [ssse3] 1 x pshufb
6284 // 3. [ssse3] 2 x pshufb + 1 x por
6285 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6287 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6288 SelectionDAG &DAG) {
6289 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6290 SDValue V1 = SVOp->getOperand(0);
6291 SDValue V2 = SVOp->getOperand(1);
6293 SmallVector<int, 8> MaskVals;
6295 // Determine if more than 1 of the words in each of the low and high quadwords
6296 // of the result come from the same quadword of one of the two inputs. Undef
6297 // mask values count as coming from any quadword, for better codegen.
6298 unsigned LoQuad[] = { 0, 0, 0, 0 };
6299 unsigned HiQuad[] = { 0, 0, 0, 0 };
6300 std::bitset<4> InputQuads;
6301 for (unsigned i = 0; i < 8; ++i) {
6302 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6303 int EltIdx = SVOp->getMaskElt(i);
6304 MaskVals.push_back(EltIdx);
6313 InputQuads.set(EltIdx / 4);
6316 int BestLoQuad = -1;
6317 unsigned MaxQuad = 1;
6318 for (unsigned i = 0; i < 4; ++i) {
6319 if (LoQuad[i] > MaxQuad) {
6321 MaxQuad = LoQuad[i];
6325 int BestHiQuad = -1;
6327 for (unsigned i = 0; i < 4; ++i) {
6328 if (HiQuad[i] > MaxQuad) {
6330 MaxQuad = HiQuad[i];
6334 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6335 // of the two input vectors, shuffle them into one input vector so only a
6336 // single pshufb instruction is necessary. If There are more than 2 input
6337 // quads, disable the next transformation since it does not help SSSE3.
6338 bool V1Used = InputQuads[0] || InputQuads[1];
6339 bool V2Used = InputQuads[2] || InputQuads[3];
6340 if (Subtarget->hasSSSE3()) {
6341 if (InputQuads.count() == 2 && V1Used && V2Used) {
6342 BestLoQuad = InputQuads[0] ? 0 : 1;
6343 BestHiQuad = InputQuads[2] ? 2 : 3;
6345 if (InputQuads.count() > 2) {
6351 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6352 // the shuffle mask. If a quad is scored as -1, that means that it contains
6353 // words from all 4 input quadwords.
6355 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6357 BestLoQuad < 0 ? 0 : BestLoQuad,
6358 BestHiQuad < 0 ? 1 : BestHiQuad
6360 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6361 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6362 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6363 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6365 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6366 // source words for the shuffle, to aid later transformations.
6367 bool AllWordsInNewV = true;
6368 bool InOrder[2] = { true, true };
6369 for (unsigned i = 0; i != 8; ++i) {
6370 int idx = MaskVals[i];
6372 InOrder[i/4] = false;
6373 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6375 AllWordsInNewV = false;
6379 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6380 if (AllWordsInNewV) {
6381 for (int i = 0; i != 8; ++i) {
6382 int idx = MaskVals[i];
6385 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6386 if ((idx != i) && idx < 4)
6388 if ((idx != i) && idx > 3)
6397 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6398 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6399 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6400 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6401 unsigned TargetMask = 0;
6402 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6403 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6404 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6405 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6406 getShufflePSHUFLWImmediate(SVOp);
6407 V1 = NewV.getOperand(0);
6408 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6412 // Promote splats to a larger type which usually leads to more efficient code.
6413 // FIXME: Is this true if pshufb is available?
6414 if (SVOp->isSplat())
6415 return PromoteSplat(SVOp, DAG);
6417 // If we have SSSE3, and all words of the result are from 1 input vector,
6418 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6419 // is present, fall back to case 4.
6420 if (Subtarget->hasSSSE3()) {
6421 SmallVector<SDValue,16> pshufbMask;
6423 // If we have elements from both input vectors, set the high bit of the
6424 // shuffle mask element to zero out elements that come from V2 in the V1
6425 // mask, and elements that come from V1 in the V2 mask, so that the two
6426 // results can be OR'd together.
6427 bool TwoInputs = V1Used && V2Used;
6428 for (unsigned i = 0; i != 8; ++i) {
6429 int EltIdx = MaskVals[i] * 2;
6430 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6431 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6432 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6433 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6435 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6436 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6437 DAG.getNode(ISD::BUILD_VECTOR, dl,
6438 MVT::v16i8, &pshufbMask[0], 16));
6440 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6442 // Calculate the shuffle mask for the second input, shuffle it, and
6443 // OR it with the first shuffled input.
6445 for (unsigned i = 0; i != 8; ++i) {
6446 int EltIdx = MaskVals[i] * 2;
6447 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6448 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6449 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6450 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6452 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6453 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6454 DAG.getNode(ISD::BUILD_VECTOR, dl,
6455 MVT::v16i8, &pshufbMask[0], 16));
6456 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6457 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6460 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6461 // and update MaskVals with new element order.
6462 std::bitset<8> InOrder;
6463 if (BestLoQuad >= 0) {
6464 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6465 for (int i = 0; i != 4; ++i) {
6466 int idx = MaskVals[i];
6469 } else if ((idx / 4) == BestLoQuad) {
6474 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6477 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6479 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6481 getShufflePSHUFLWImmediate(SVOp), DAG);
6485 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6486 // and update MaskVals with the new element order.
6487 if (BestHiQuad >= 0) {
6488 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6489 for (unsigned i = 4; i != 8; ++i) {
6490 int idx = MaskVals[i];
6493 } else if ((idx / 4) == BestHiQuad) {
6494 MaskV[i] = (idx & 3) + 4;
6498 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6501 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6502 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6503 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6505 getShufflePSHUFHWImmediate(SVOp), DAG);
6509 // In case BestHi & BestLo were both -1, which means each quadword has a word
6510 // from each of the four input quadwords, calculate the InOrder bitvector now
6511 // before falling through to the insert/extract cleanup.
6512 if (BestLoQuad == -1 && BestHiQuad == -1) {
6514 for (int i = 0; i != 8; ++i)
6515 if (MaskVals[i] < 0 || MaskVals[i] == i)
6519 // The other elements are put in the right place using pextrw and pinsrw.
6520 for (unsigned i = 0; i != 8; ++i) {
6523 int EltIdx = MaskVals[i];
6526 SDValue ExtOp = (EltIdx < 8) ?
6527 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6528 DAG.getIntPtrConstant(EltIdx)) :
6529 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6530 DAG.getIntPtrConstant(EltIdx - 8));
6531 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6532 DAG.getIntPtrConstant(i));
6537 // v16i8 shuffles - Prefer shuffles in the following order:
6538 // 1. [ssse3] 1 x pshufb
6539 // 2. [ssse3] 2 x pshufb + 1 x por
6540 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6541 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6542 const X86Subtarget* Subtarget,
6543 SelectionDAG &DAG) {
6544 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6545 SDValue V1 = SVOp->getOperand(0);
6546 SDValue V2 = SVOp->getOperand(1);
6548 ArrayRef<int> MaskVals = SVOp->getMask();
6550 // Promote splats to a larger type which usually leads to more efficient code.
6551 // FIXME: Is this true if pshufb is available?
6552 if (SVOp->isSplat())
6553 return PromoteSplat(SVOp, DAG);
6555 // If we have SSSE3, case 1 is generated when all result bytes come from
6556 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6557 // present, fall back to case 3.
6559 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6560 if (Subtarget->hasSSSE3()) {
6561 SmallVector<SDValue,16> pshufbMask;
6563 // If all result elements are from one input vector, then only translate
6564 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6566 // Otherwise, we have elements from both input vectors, and must zero out
6567 // elements that come from V2 in the first mask, and V1 in the second mask
6568 // so that we can OR them together.
6569 for (unsigned i = 0; i != 16; ++i) {
6570 int EltIdx = MaskVals[i];
6571 if (EltIdx < 0 || EltIdx >= 16)
6573 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6575 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6576 DAG.getNode(ISD::BUILD_VECTOR, dl,
6577 MVT::v16i8, &pshufbMask[0], 16));
6579 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6580 // the 2nd operand if it's undefined or zero.
6581 if (V2.getOpcode() == ISD::UNDEF ||
6582 ISD::isBuildVectorAllZeros(V2.getNode()))
6585 // Calculate the shuffle mask for the second input, shuffle it, and
6586 // OR it with the first shuffled input.
6588 for (unsigned i = 0; i != 16; ++i) {
6589 int EltIdx = MaskVals[i];
6590 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6591 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6593 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6594 DAG.getNode(ISD::BUILD_VECTOR, dl,
6595 MVT::v16i8, &pshufbMask[0], 16));
6596 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6599 // No SSSE3 - Calculate in place words and then fix all out of place words
6600 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6601 // the 16 different words that comprise the two doublequadword input vectors.
6602 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6603 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6605 for (int i = 0; i != 8; ++i) {
6606 int Elt0 = MaskVals[i*2];
6607 int Elt1 = MaskVals[i*2+1];
6609 // This word of the result is all undef, skip it.
6610 if (Elt0 < 0 && Elt1 < 0)
6613 // This word of the result is already in the correct place, skip it.
6614 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6617 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6618 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6621 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6622 // using a single extract together, load it and store it.
6623 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6624 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6625 DAG.getIntPtrConstant(Elt1 / 2));
6626 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6627 DAG.getIntPtrConstant(i));
6631 // If Elt1 is defined, extract it from the appropriate source. If the
6632 // source byte is not also odd, shift the extracted word left 8 bits
6633 // otherwise clear the bottom 8 bits if we need to do an or.
6635 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6636 DAG.getIntPtrConstant(Elt1 / 2));
6637 if ((Elt1 & 1) == 0)
6638 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6640 TLI.getShiftAmountTy(InsElt.getValueType())));
6642 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6643 DAG.getConstant(0xFF00, MVT::i16));
6645 // If Elt0 is defined, extract it from the appropriate source. If the
6646 // source byte is not also even, shift the extracted word right 8 bits. If
6647 // Elt1 was also defined, OR the extracted values together before
6648 // inserting them in the result.
6650 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6651 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6652 if ((Elt0 & 1) != 0)
6653 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6655 TLI.getShiftAmountTy(InsElt0.getValueType())));
6657 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6658 DAG.getConstant(0x00FF, MVT::i16));
6659 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6662 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6663 DAG.getIntPtrConstant(i));
6665 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6668 // v32i8 shuffles - Translate to VPSHUFB if possible.
6670 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6671 const X86Subtarget *Subtarget,
6672 SelectionDAG &DAG) {
6673 MVT VT = SVOp->getSimpleValueType(0);
6674 SDValue V1 = SVOp->getOperand(0);
6675 SDValue V2 = SVOp->getOperand(1);
6677 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6679 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6680 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6681 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6683 // VPSHUFB may be generated if
6684 // (1) one of input vector is undefined or zeroinitializer.
6685 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6686 // And (2) the mask indexes don't cross the 128-bit lane.
6687 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6688 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6691 if (V1IsAllZero && !V2IsAllZero) {
6692 CommuteVectorShuffleMask(MaskVals, 32);
6695 SmallVector<SDValue, 32> pshufbMask;
6696 for (unsigned i = 0; i != 32; i++) {
6697 int EltIdx = MaskVals[i];
6698 if (EltIdx < 0 || EltIdx >= 32)
6701 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6702 // Cross lane is not allowed.
6706 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6708 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6709 DAG.getNode(ISD::BUILD_VECTOR, dl,
6710 MVT::v32i8, &pshufbMask[0], 32));
6713 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6714 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6715 /// done when every pair / quad of shuffle mask elements point to elements in
6716 /// the right sequence. e.g.
6717 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6719 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6720 SelectionDAG &DAG) {
6721 MVT VT = SVOp->getSimpleValueType(0);
6723 unsigned NumElems = VT.getVectorNumElements();
6726 switch (VT.SimpleTy) {
6727 default: llvm_unreachable("Unexpected!");
6728 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6729 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6730 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6731 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6732 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6733 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6736 SmallVector<int, 8> MaskVec;
6737 for (unsigned i = 0; i != NumElems; i += Scale) {
6739 for (unsigned j = 0; j != Scale; ++j) {
6740 int EltIdx = SVOp->getMaskElt(i+j);
6744 StartIdx = (EltIdx / Scale);
6745 if (EltIdx != (int)(StartIdx*Scale + j))
6748 MaskVec.push_back(StartIdx);
6751 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6752 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6753 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6756 /// getVZextMovL - Return a zero-extending vector move low node.
6758 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6759 SDValue SrcOp, SelectionDAG &DAG,
6760 const X86Subtarget *Subtarget, SDLoc dl) {
6761 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6762 LoadSDNode *LD = NULL;
6763 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6764 LD = dyn_cast<LoadSDNode>(SrcOp);
6766 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6768 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6769 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6770 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6771 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6772 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6774 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6775 return DAG.getNode(ISD::BITCAST, dl, VT,
6776 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6777 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6785 return DAG.getNode(ISD::BITCAST, dl, VT,
6786 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6787 DAG.getNode(ISD::BITCAST, dl,
6791 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6792 /// which could not be matched by any known target speficic shuffle
6794 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6796 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6797 if (NewOp.getNode())
6800 MVT VT = SVOp->getSimpleValueType(0);
6802 unsigned NumElems = VT.getVectorNumElements();
6803 unsigned NumLaneElems = NumElems / 2;
6806 MVT EltVT = VT.getVectorElementType();
6807 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6810 SmallVector<int, 16> Mask;
6811 for (unsigned l = 0; l < 2; ++l) {
6812 // Build a shuffle mask for the output, discovering on the fly which
6813 // input vectors to use as shuffle operands (recorded in InputUsed).
6814 // If building a suitable shuffle vector proves too hard, then bail
6815 // out with UseBuildVector set.
6816 bool UseBuildVector = false;
6817 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6818 unsigned LaneStart = l * NumLaneElems;
6819 for (unsigned i = 0; i != NumLaneElems; ++i) {
6820 // The mask element. This indexes into the input.
6821 int Idx = SVOp->getMaskElt(i+LaneStart);
6823 // the mask element does not index into any input vector.
6828 // The input vector this mask element indexes into.
6829 int Input = Idx / NumLaneElems;
6831 // Turn the index into an offset from the start of the input vector.
6832 Idx -= Input * NumLaneElems;
6834 // Find or create a shuffle vector operand to hold this input.
6836 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6837 if (InputUsed[OpNo] == Input)
6838 // This input vector is already an operand.
6840 if (InputUsed[OpNo] < 0) {
6841 // Create a new operand for this input vector.
6842 InputUsed[OpNo] = Input;
6847 if (OpNo >= array_lengthof(InputUsed)) {
6848 // More than two input vectors used! Give up on trying to create a
6849 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6850 UseBuildVector = true;
6854 // Add the mask index for the new shuffle vector.
6855 Mask.push_back(Idx + OpNo * NumLaneElems);
6858 if (UseBuildVector) {
6859 SmallVector<SDValue, 16> SVOps;
6860 for (unsigned i = 0; i != NumLaneElems; ++i) {
6861 // The mask element. This indexes into the input.
6862 int Idx = SVOp->getMaskElt(i+LaneStart);
6864 SVOps.push_back(DAG.getUNDEF(EltVT));
6868 // The input vector this mask element indexes into.
6869 int Input = Idx / NumElems;
6871 // Turn the index into an offset from the start of the input vector.
6872 Idx -= Input * NumElems;
6874 // Extract the vector element by hand.
6875 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6876 SVOp->getOperand(Input),
6877 DAG.getIntPtrConstant(Idx)));
6880 // Construct the output using a BUILD_VECTOR.
6881 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6883 } else if (InputUsed[0] < 0) {
6884 // No input vectors were used! The result is undefined.
6885 Output[l] = DAG.getUNDEF(NVT);
6887 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6888 (InputUsed[0] % 2) * NumLaneElems,
6890 // If only one input was used, use an undefined vector for the other.
6891 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6892 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6893 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6894 // At least one input vector was used. Create a new shuffle vector.
6895 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6901 // Concatenate the result back
6902 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6905 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6906 /// 4 elements, and match them with several different shuffle types.
6908 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6909 SDValue V1 = SVOp->getOperand(0);
6910 SDValue V2 = SVOp->getOperand(1);
6912 MVT VT = SVOp->getSimpleValueType(0);
6914 assert(VT.is128BitVector() && "Unsupported vector size");
6916 std::pair<int, int> Locs[4];
6917 int Mask1[] = { -1, -1, -1, -1 };
6918 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6922 for (unsigned i = 0; i != 4; ++i) {
6923 int Idx = PermMask[i];
6925 Locs[i] = std::make_pair(-1, -1);
6927 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6929 Locs[i] = std::make_pair(0, NumLo);
6933 Locs[i] = std::make_pair(1, NumHi);
6935 Mask1[2+NumHi] = Idx;
6941 if (NumLo <= 2 && NumHi <= 2) {
6942 // If no more than two elements come from either vector. This can be
6943 // implemented with two shuffles. First shuffle gather the elements.
6944 // The second shuffle, which takes the first shuffle as both of its
6945 // vector operands, put the elements into the right order.
6946 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6948 int Mask2[] = { -1, -1, -1, -1 };
6950 for (unsigned i = 0; i != 4; ++i)
6951 if (Locs[i].first != -1) {
6952 unsigned Idx = (i < 2) ? 0 : 4;
6953 Idx += Locs[i].first * 2 + Locs[i].second;
6957 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6960 if (NumLo == 3 || NumHi == 3) {
6961 // Otherwise, we must have three elements from one vector, call it X, and
6962 // one element from the other, call it Y. First, use a shufps to build an
6963 // intermediate vector with the one element from Y and the element from X
6964 // that will be in the same half in the final destination (the indexes don't
6965 // matter). Then, use a shufps to build the final vector, taking the half
6966 // containing the element from Y from the intermediate, and the other half
6969 // Normalize it so the 3 elements come from V1.
6970 CommuteVectorShuffleMask(PermMask, 4);
6974 // Find the element from V2.
6976 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6977 int Val = PermMask[HiIndex];
6984 Mask1[0] = PermMask[HiIndex];
6986 Mask1[2] = PermMask[HiIndex^1];
6988 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6991 Mask1[0] = PermMask[0];
6992 Mask1[1] = PermMask[1];
6993 Mask1[2] = HiIndex & 1 ? 6 : 4;
6994 Mask1[3] = HiIndex & 1 ? 4 : 6;
6995 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6998 Mask1[0] = HiIndex & 1 ? 2 : 0;
6999 Mask1[1] = HiIndex & 1 ? 0 : 2;
7000 Mask1[2] = PermMask[2];
7001 Mask1[3] = PermMask[3];
7006 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7009 // Break it into (shuffle shuffle_hi, shuffle_lo).
7010 int LoMask[] = { -1, -1, -1, -1 };
7011 int HiMask[] = { -1, -1, -1, -1 };
7013 int *MaskPtr = LoMask;
7014 unsigned MaskIdx = 0;
7017 for (unsigned i = 0; i != 4; ++i) {
7024 int Idx = PermMask[i];
7026 Locs[i] = std::make_pair(-1, -1);
7027 } else if (Idx < 4) {
7028 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7029 MaskPtr[LoIdx] = Idx;
7032 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7033 MaskPtr[HiIdx] = Idx;
7038 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7039 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7040 int MaskOps[] = { -1, -1, -1, -1 };
7041 for (unsigned i = 0; i != 4; ++i)
7042 if (Locs[i].first != -1)
7043 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7044 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7047 static bool MayFoldVectorLoad(SDValue V) {
7048 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7049 V = V.getOperand(0);
7051 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7052 V = V.getOperand(0);
7053 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7054 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7055 // BUILD_VECTOR (load), undef
7056 V = V.getOperand(0);
7058 return MayFoldLoad(V);
7062 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7063 MVT VT = Op.getSimpleValueType();
7065 // Canonizalize to v2f64.
7066 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7067 return DAG.getNode(ISD::BITCAST, dl, VT,
7068 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7073 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7075 SDValue V1 = Op.getOperand(0);
7076 SDValue V2 = Op.getOperand(1);
7077 MVT VT = Op.getSimpleValueType();
7079 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7081 if (HasSSE2 && VT == MVT::v2f64)
7082 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7084 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7085 return DAG.getNode(ISD::BITCAST, dl, VT,
7086 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7087 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7088 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7092 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7093 SDValue V1 = Op.getOperand(0);
7094 SDValue V2 = Op.getOperand(1);
7095 MVT VT = Op.getSimpleValueType();
7097 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7098 "unsupported shuffle type");
7100 if (V2.getOpcode() == ISD::UNDEF)
7104 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7108 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7109 SDValue V1 = Op.getOperand(0);
7110 SDValue V2 = Op.getOperand(1);
7111 MVT VT = Op.getSimpleValueType();
7112 unsigned NumElems = VT.getVectorNumElements();
7114 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7115 // operand of these instructions is only memory, so check if there's a
7116 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7118 bool CanFoldLoad = false;
7120 // Trivial case, when V2 comes from a load.
7121 if (MayFoldVectorLoad(V2))
7124 // When V1 is a load, it can be folded later into a store in isel, example:
7125 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7127 // (MOVLPSmr addr:$src1, VR128:$src2)
7128 // So, recognize this potential and also use MOVLPS or MOVLPD
7129 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7132 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7134 if (HasSSE2 && NumElems == 2)
7135 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7138 // If we don't care about the second element, proceed to use movss.
7139 if (SVOp->getMaskElt(1) != -1)
7140 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7143 // movl and movlp will both match v2i64, but v2i64 is never matched by
7144 // movl earlier because we make it strict to avoid messing with the movlp load
7145 // folding logic (see the code above getMOVLP call). Match it here then,
7146 // this is horrible, but will stay like this until we move all shuffle
7147 // matching to x86 specific nodes. Note that for the 1st condition all
7148 // types are matched with movsd.
7150 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7151 // as to remove this logic from here, as much as possible
7152 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7153 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7154 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7157 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7159 // Invert the operand order and use SHUFPS to match it.
7160 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7161 getShuffleSHUFImmediate(SVOp), DAG);
7164 // Reduce a vector shuffle to zext.
7165 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7166 SelectionDAG &DAG) {
7167 // PMOVZX is only available from SSE41.
7168 if (!Subtarget->hasSSE41())
7171 MVT VT = Op.getSimpleValueType();
7173 // Only AVX2 support 256-bit vector integer extending.
7174 if (!Subtarget->hasInt256() && VT.is256BitVector())
7177 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7179 SDValue V1 = Op.getOperand(0);
7180 SDValue V2 = Op.getOperand(1);
7181 unsigned NumElems = VT.getVectorNumElements();
7183 // Extending is an unary operation and the element type of the source vector
7184 // won't be equal to or larger than i64.
7185 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7186 VT.getVectorElementType() == MVT::i64)
7189 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7190 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7191 while ((1U << Shift) < NumElems) {
7192 if (SVOp->getMaskElt(1U << Shift) == 1)
7195 // The maximal ratio is 8, i.e. from i8 to i64.
7200 // Check the shuffle mask.
7201 unsigned Mask = (1U << Shift) - 1;
7202 for (unsigned i = 0; i != NumElems; ++i) {
7203 int EltIdx = SVOp->getMaskElt(i);
7204 if ((i & Mask) != 0 && EltIdx != -1)
7206 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7210 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7211 MVT NeVT = MVT::getIntegerVT(NBits);
7212 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7214 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7217 // Simplify the operand as it's prepared to be fed into shuffle.
7218 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7219 if (V1.getOpcode() == ISD::BITCAST &&
7220 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7221 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7222 V1.getOperand(0).getOperand(0)
7223 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7224 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7225 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7226 ConstantSDNode *CIdx =
7227 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7228 // If it's foldable, i.e. normal load with single use, we will let code
7229 // selection to fold it. Otherwise, we will short the conversion sequence.
7230 if (CIdx && CIdx->getZExtValue() == 0 &&
7231 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7232 MVT FullVT = V.getSimpleValueType();
7233 MVT V1VT = V1.getSimpleValueType();
7234 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7235 // The "ext_vec_elt" node is wider than the result node.
7236 // In this case we should extract subvector from V.
7237 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7238 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7239 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7240 FullVT.getVectorNumElements()/Ratio);
7241 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7242 DAG.getIntPtrConstant(0));
7244 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7248 return DAG.getNode(ISD::BITCAST, DL, VT,
7249 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7253 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7254 SelectionDAG &DAG) {
7255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7256 MVT VT = Op.getSimpleValueType();
7258 SDValue V1 = Op.getOperand(0);
7259 SDValue V2 = Op.getOperand(1);
7261 if (isZeroShuffle(SVOp))
7262 return getZeroVector(VT, Subtarget, DAG, dl);
7264 // Handle splat operations
7265 if (SVOp->isSplat()) {
7266 // Use vbroadcast whenever the splat comes from a foldable load
7267 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7268 if (Broadcast.getNode())
7272 // Check integer expanding shuffles.
7273 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7274 if (NewOp.getNode())
7277 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7279 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7280 VT == MVT::v16i16 || VT == MVT::v32i8) {
7281 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7282 if (NewOp.getNode())
7283 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7284 } else if ((VT == MVT::v4i32 ||
7285 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7286 // FIXME: Figure out a cleaner way to do this.
7287 // Try to make use of movq to zero out the top part.
7288 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7289 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7290 if (NewOp.getNode()) {
7291 MVT NewVT = NewOp.getSimpleValueType();
7292 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7293 NewVT, true, false))
7294 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7295 DAG, Subtarget, dl);
7297 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7298 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7299 if (NewOp.getNode()) {
7300 MVT NewVT = NewOp.getSimpleValueType();
7301 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7302 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7303 DAG, Subtarget, dl);
7311 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7312 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7313 SDValue V1 = Op.getOperand(0);
7314 SDValue V2 = Op.getOperand(1);
7315 MVT VT = Op.getSimpleValueType();
7317 unsigned NumElems = VT.getVectorNumElements();
7318 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7319 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7320 bool V1IsSplat = false;
7321 bool V2IsSplat = false;
7322 bool HasSSE2 = Subtarget->hasSSE2();
7323 bool HasFp256 = Subtarget->hasFp256();
7324 bool HasInt256 = Subtarget->hasInt256();
7325 MachineFunction &MF = DAG.getMachineFunction();
7326 bool OptForSize = MF.getFunction()->getAttributes().
7327 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7329 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7331 if (V1IsUndef && V2IsUndef)
7332 return DAG.getUNDEF(VT);
7334 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7336 // Vector shuffle lowering takes 3 steps:
7338 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7339 // narrowing and commutation of operands should be handled.
7340 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7342 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7343 // so the shuffle can be broken into other shuffles and the legalizer can
7344 // try the lowering again.
7346 // The general idea is that no vector_shuffle operation should be left to
7347 // be matched during isel, all of them must be converted to a target specific
7350 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7351 // narrowing and commutation of operands should be handled. The actual code
7352 // doesn't include all of those, work in progress...
7353 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7354 if (NewOp.getNode())
7357 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7359 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7360 // unpckh_undef). Only use pshufd if speed is more important than size.
7361 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7362 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7363 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7364 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7366 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7367 V2IsUndef && MayFoldVectorLoad(V1))
7368 return getMOVDDup(Op, dl, V1, DAG);
7370 if (isMOVHLPS_v_undef_Mask(M, VT))
7371 return getMOVHighToLow(Op, dl, DAG);
7373 // Use to match splats
7374 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7375 (VT == MVT::v2f64 || VT == MVT::v2i64))
7376 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7378 if (isPSHUFDMask(M, VT)) {
7379 // The actual implementation will match the mask in the if above and then
7380 // during isel it can match several different instructions, not only pshufd
7381 // as its name says, sad but true, emulate the behavior for now...
7382 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7383 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7385 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7387 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7388 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7390 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7391 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7394 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7398 if (isPALIGNRMask(M, VT, Subtarget))
7399 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7400 getShufflePALIGNRImmediate(SVOp),
7403 // Check if this can be converted into a logical shift.
7404 bool isLeft = false;
7407 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7408 if (isShift && ShVal.hasOneUse()) {
7409 // If the shifted value has multiple uses, it may be cheaper to use
7410 // v_set0 + movlhps or movhlps, etc.
7411 MVT EltVT = VT.getVectorElementType();
7412 ShAmt *= EltVT.getSizeInBits();
7413 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7416 if (isMOVLMask(M, VT)) {
7417 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7418 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7419 if (!isMOVLPMask(M, VT)) {
7420 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7421 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7423 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7424 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7428 // FIXME: fold these into legal mask.
7429 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7430 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7432 if (isMOVHLPSMask(M, VT))
7433 return getMOVHighToLow(Op, dl, DAG);
7435 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7436 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7438 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7439 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7441 if (isMOVLPMask(M, VT))
7442 return getMOVLP(Op, dl, DAG, HasSSE2);
7444 if (ShouldXformToMOVHLPS(M, VT) ||
7445 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7446 return CommuteVectorShuffle(SVOp, DAG);
7449 // No better options. Use a vshldq / vsrldq.
7450 MVT EltVT = VT.getVectorElementType();
7451 ShAmt *= EltVT.getSizeInBits();
7452 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7455 bool Commuted = false;
7456 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7457 // 1,1,1,1 -> v8i16 though.
7458 V1IsSplat = isSplatVector(V1.getNode());
7459 V2IsSplat = isSplatVector(V2.getNode());
7461 // Canonicalize the splat or undef, if present, to be on the RHS.
7462 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7463 CommuteVectorShuffleMask(M, NumElems);
7465 std::swap(V1IsSplat, V2IsSplat);
7469 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7470 // Shuffling low element of v1 into undef, just return v1.
7473 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7474 // the instruction selector will not match, so get a canonical MOVL with
7475 // swapped operands to undo the commute.
7476 return getMOVL(DAG, dl, VT, V2, V1);
7479 if (isUNPCKLMask(M, VT, HasInt256))
7480 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7482 if (isUNPCKHMask(M, VT, HasInt256))
7483 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7486 // Normalize mask so all entries that point to V2 points to its first
7487 // element then try to match unpck{h|l} again. If match, return a
7488 // new vector_shuffle with the corrected mask.p
7489 SmallVector<int, 8> NewMask(M.begin(), M.end());
7490 NormalizeMask(NewMask, NumElems);
7491 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7492 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7493 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7494 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7498 // Commute is back and try unpck* again.
7499 // FIXME: this seems wrong.
7500 CommuteVectorShuffleMask(M, NumElems);
7502 std::swap(V1IsSplat, V2IsSplat);
7505 if (isUNPCKLMask(M, VT, HasInt256))
7506 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7508 if (isUNPCKHMask(M, VT, HasInt256))
7509 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7512 // Normalize the node to match x86 shuffle ops if needed
7513 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7514 return CommuteVectorShuffle(SVOp, DAG);
7516 // The checks below are all present in isShuffleMaskLegal, but they are
7517 // inlined here right now to enable us to directly emit target specific
7518 // nodes, and remove one by one until they don't return Op anymore.
7520 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7521 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7522 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7523 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7526 if (isPSHUFHWMask(M, VT, HasInt256))
7527 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7528 getShufflePSHUFHWImmediate(SVOp),
7531 if (isPSHUFLWMask(M, VT, HasInt256))
7532 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7533 getShufflePSHUFLWImmediate(SVOp),
7536 if (isSHUFPMask(M, VT))
7537 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7538 getShuffleSHUFImmediate(SVOp), DAG);
7540 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7541 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7542 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7543 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7545 //===--------------------------------------------------------------------===//
7546 // Generate target specific nodes for 128 or 256-bit shuffles only
7547 // supported in the AVX instruction set.
7550 // Handle VMOVDDUPY permutations
7551 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7552 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7554 // Handle VPERMILPS/D* permutations
7555 if (isVPERMILPMask(M, VT)) {
7556 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7557 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7558 getShuffleSHUFImmediate(SVOp), DAG);
7559 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7560 getShuffleSHUFImmediate(SVOp), DAG);
7563 // Handle VPERM2F128/VPERM2I128 permutations
7564 if (isVPERM2X128Mask(M, VT, HasFp256))
7565 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7566 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7568 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7569 if (BlendOp.getNode())
7573 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7574 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7576 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7577 VT.is512BitVector()) {
7578 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7579 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7580 SmallVector<SDValue, 16> permclMask;
7581 for (unsigned i = 0; i != NumElems; ++i) {
7582 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7585 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7586 &permclMask[0], NumElems);
7588 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7589 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7590 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7591 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7592 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7595 //===--------------------------------------------------------------------===//
7596 // Since no target specific shuffle was selected for this generic one,
7597 // lower it into other known shuffles. FIXME: this isn't true yet, but
7598 // this is the plan.
7601 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7602 if (VT == MVT::v8i16) {
7603 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7604 if (NewOp.getNode())
7608 if (VT == MVT::v16i8) {
7609 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7610 if (NewOp.getNode())
7614 if (VT == MVT::v32i8) {
7615 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7616 if (NewOp.getNode())
7620 // Handle all 128-bit wide vectors with 4 elements, and match them with
7621 // several different shuffle types.
7622 if (NumElems == 4 && VT.is128BitVector())
7623 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7625 // Handle general 256-bit shuffles
7626 if (VT.is256BitVector())
7627 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7632 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7633 MVT VT = Op.getSimpleValueType();
7636 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7639 if (VT.getSizeInBits() == 8) {
7640 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7641 Op.getOperand(0), Op.getOperand(1));
7642 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7643 DAG.getValueType(VT));
7644 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7647 if (VT.getSizeInBits() == 16) {
7648 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7649 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7651 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7653 DAG.getNode(ISD::BITCAST, dl,
7657 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7658 Op.getOperand(0), Op.getOperand(1));
7659 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7660 DAG.getValueType(VT));
7661 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7664 if (VT == MVT::f32) {
7665 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7666 // the result back to FR32 register. It's only worth matching if the
7667 // result has a single use which is a store or a bitcast to i32. And in
7668 // the case of a store, it's not worth it if the index is a constant 0,
7669 // because a MOVSSmr can be used instead, which is smaller and faster.
7670 if (!Op.hasOneUse())
7672 SDNode *User = *Op.getNode()->use_begin();
7673 if ((User->getOpcode() != ISD::STORE ||
7674 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7675 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7676 (User->getOpcode() != ISD::BITCAST ||
7677 User->getValueType(0) != MVT::i32))
7679 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7680 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7683 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7686 if (VT == MVT::i32 || VT == MVT::i64) {
7687 // ExtractPS/pextrq works with constant index.
7688 if (isa<ConstantSDNode>(Op.getOperand(1)))
7694 /// Extract one bit from mask vector, like v16i1 or v8i1.
7695 /// AVX-512 feature.
7696 static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
7697 SDValue Vec = Op.getOperand(0);
7699 MVT VecVT = Vec.getSimpleValueType();
7700 SDValue Idx = Op.getOperand(1);
7701 MVT EltVT = Op.getSimpleValueType();
7703 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7705 // variable index can't be handled in mask registers,
7706 // extend vector to VR512
7707 if (!isa<ConstantSDNode>(Idx)) {
7708 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7709 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7710 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7711 ExtVT.getVectorElementType(), Ext, Idx);
7712 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7715 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7717 unsigned MaxSift = VecVT.getSizeInBits() - 1;
7718 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7719 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7720 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7721 DAG.getConstant(MaxSift, MVT::i8));
7723 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i1, Vec,
7724 DAG.getIntPtrConstant(0));
7728 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7729 SelectionDAG &DAG) const {
7731 SDValue Vec = Op.getOperand(0);
7732 MVT VecVT = Vec.getSimpleValueType();
7733 SDValue Idx = Op.getOperand(1);
7735 if (Op.getSimpleValueType() == MVT::i1)
7736 return ExtractBitFromMaskVector(Op, DAG);
7738 if (!isa<ConstantSDNode>(Idx)) {
7739 if (VecVT.is512BitVector() ||
7740 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7741 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7744 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7745 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7746 MaskEltVT.getSizeInBits());
7748 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7749 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7750 getZeroVector(MaskVT, Subtarget, DAG, dl),
7751 Idx, DAG.getConstant(0, getPointerTy()));
7752 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7753 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7754 Perm, DAG.getConstant(0, getPointerTy()));
7759 // If this is a 256-bit vector result, first extract the 128-bit vector and
7760 // then extract the element from the 128-bit vector.
7761 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7763 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7764 // Get the 128-bit vector.
7765 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7766 MVT EltVT = VecVT.getVectorElementType();
7768 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7770 //if (IdxVal >= NumElems/2)
7771 // IdxVal -= NumElems/2;
7772 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7773 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7774 DAG.getConstant(IdxVal, MVT::i32));
7777 assert(VecVT.is128BitVector() && "Unexpected vector length");
7779 if (Subtarget->hasSSE41()) {
7780 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7785 MVT VT = Op.getSimpleValueType();
7786 // TODO: handle v16i8.
7787 if (VT.getSizeInBits() == 16) {
7788 SDValue Vec = Op.getOperand(0);
7789 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7791 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7792 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7793 DAG.getNode(ISD::BITCAST, dl,
7796 // Transform it so it match pextrw which produces a 32-bit result.
7797 MVT EltVT = MVT::i32;
7798 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7799 Op.getOperand(0), Op.getOperand(1));
7800 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7801 DAG.getValueType(VT));
7802 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7805 if (VT.getSizeInBits() == 32) {
7806 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7810 // SHUFPS the element to the lowest double word, then movss.
7811 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7812 MVT VVT = Op.getOperand(0).getSimpleValueType();
7813 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7814 DAG.getUNDEF(VVT), Mask);
7815 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7816 DAG.getIntPtrConstant(0));
7819 if (VT.getSizeInBits() == 64) {
7820 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7821 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7822 // to match extract_elt for f64.
7823 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7827 // UNPCKHPD the element to the lowest double word, then movsd.
7828 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7829 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7830 int Mask[2] = { 1, -1 };
7831 MVT VVT = Op.getOperand(0).getSimpleValueType();
7832 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7833 DAG.getUNDEF(VVT), Mask);
7834 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7835 DAG.getIntPtrConstant(0));
7841 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7842 MVT VT = Op.getSimpleValueType();
7843 MVT EltVT = VT.getVectorElementType();
7846 SDValue N0 = Op.getOperand(0);
7847 SDValue N1 = Op.getOperand(1);
7848 SDValue N2 = Op.getOperand(2);
7850 if (!VT.is128BitVector())
7853 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7854 isa<ConstantSDNode>(N2)) {
7856 if (VT == MVT::v8i16)
7857 Opc = X86ISD::PINSRW;
7858 else if (VT == MVT::v16i8)
7859 Opc = X86ISD::PINSRB;
7861 Opc = X86ISD::PINSRB;
7863 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7865 if (N1.getValueType() != MVT::i32)
7866 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7867 if (N2.getValueType() != MVT::i32)
7868 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7869 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7872 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7873 // Bits [7:6] of the constant are the source select. This will always be
7874 // zero here. The DAG Combiner may combine an extract_elt index into these
7875 // bits. For example (insert (extract, 3), 2) could be matched by putting
7876 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7877 // Bits [5:4] of the constant are the destination select. This is the
7878 // value of the incoming immediate.
7879 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7880 // combine either bitwise AND or insert of float 0.0 to set these bits.
7881 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7882 // Create this as a scalar to vector..
7883 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7884 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7887 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7888 // PINSR* works with constant index.
7895 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7896 MVT VT = Op.getSimpleValueType();
7897 MVT EltVT = VT.getVectorElementType();
7900 SDValue N0 = Op.getOperand(0);
7901 SDValue N1 = Op.getOperand(1);
7902 SDValue N2 = Op.getOperand(2);
7904 // If this is a 256-bit vector result, first extract the 128-bit vector,
7905 // insert the element into the extracted half and then place it back.
7906 if (VT.is256BitVector() || VT.is512BitVector()) {
7907 if (!isa<ConstantSDNode>(N2))
7910 // Get the desired 128-bit vector half.
7911 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7912 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7914 // Insert the element into the desired half.
7915 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7916 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7918 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7919 DAG.getConstant(IdxIn128, MVT::i32));
7921 // Insert the changed part back to the 256-bit vector
7922 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7925 if (Subtarget->hasSSE41())
7926 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7928 if (EltVT == MVT::i8)
7931 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7932 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7933 // as its second argument.
7934 if (N1.getValueType() != MVT::i32)
7935 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7936 if (N2.getValueType() != MVT::i32)
7937 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7938 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7943 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7945 MVT OpVT = Op.getSimpleValueType();
7947 // If this is a 256-bit vector result, first insert into a 128-bit
7948 // vector and then insert into the 256-bit vector.
7949 if (!OpVT.is128BitVector()) {
7950 // Insert into a 128-bit vector.
7951 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7952 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7953 OpVT.getVectorNumElements() / SizeFactor);
7955 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7957 // Insert the 128-bit vector.
7958 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7961 if (OpVT == MVT::v1i64 &&
7962 Op.getOperand(0).getValueType() == MVT::i64)
7963 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7965 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7966 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7967 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7968 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7971 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7972 // a simple subregister reference or explicit instructions to grab
7973 // upper bits of a vector.
7974 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7975 SelectionDAG &DAG) {
7977 SDValue In = Op.getOperand(0);
7978 SDValue Idx = Op.getOperand(1);
7979 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7980 MVT ResVT = Op.getSimpleValueType();
7981 MVT InVT = In.getSimpleValueType();
7983 if (Subtarget->hasFp256()) {
7984 if (ResVT.is128BitVector() &&
7985 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7986 isa<ConstantSDNode>(Idx)) {
7987 return Extract128BitVector(In, IdxVal, DAG, dl);
7989 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7990 isa<ConstantSDNode>(Idx)) {
7991 return Extract256BitVector(In, IdxVal, DAG, dl);
7997 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7998 // simple superregister reference or explicit instructions to insert
7999 // the upper bits of a vector.
8000 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8001 SelectionDAG &DAG) {
8002 if (Subtarget->hasFp256()) {
8003 SDLoc dl(Op.getNode());
8004 SDValue Vec = Op.getNode()->getOperand(0);
8005 SDValue SubVec = Op.getNode()->getOperand(1);
8006 SDValue Idx = Op.getNode()->getOperand(2);
8008 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8009 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8010 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8011 isa<ConstantSDNode>(Idx)) {
8012 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8013 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8016 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8017 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8018 isa<ConstantSDNode>(Idx)) {
8019 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8020 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8026 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8027 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8028 // one of the above mentioned nodes. It has to be wrapped because otherwise
8029 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8030 // be used to form addressing mode. These wrapped nodes will be selected
8033 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8034 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8036 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8038 unsigned char OpFlag = 0;
8039 unsigned WrapperKind = X86ISD::Wrapper;
8040 CodeModel::Model M = getTargetMachine().getCodeModel();
8042 if (Subtarget->isPICStyleRIPRel() &&
8043 (M == CodeModel::Small || M == CodeModel::Kernel))
8044 WrapperKind = X86ISD::WrapperRIP;
8045 else if (Subtarget->isPICStyleGOT())
8046 OpFlag = X86II::MO_GOTOFF;
8047 else if (Subtarget->isPICStyleStubPIC())
8048 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8050 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8052 CP->getOffset(), OpFlag);
8054 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8055 // With PIC, the address is actually $g + Offset.
8057 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8058 DAG.getNode(X86ISD::GlobalBaseReg,
8059 SDLoc(), getPointerTy()),
8066 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8067 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8069 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8071 unsigned char OpFlag = 0;
8072 unsigned WrapperKind = X86ISD::Wrapper;
8073 CodeModel::Model M = getTargetMachine().getCodeModel();
8075 if (Subtarget->isPICStyleRIPRel() &&
8076 (M == CodeModel::Small || M == CodeModel::Kernel))
8077 WrapperKind = X86ISD::WrapperRIP;
8078 else if (Subtarget->isPICStyleGOT())
8079 OpFlag = X86II::MO_GOTOFF;
8080 else if (Subtarget->isPICStyleStubPIC())
8081 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8083 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8086 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8088 // With PIC, the address is actually $g + Offset.
8090 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8091 DAG.getNode(X86ISD::GlobalBaseReg,
8092 SDLoc(), getPointerTy()),
8099 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8100 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8102 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8104 unsigned char OpFlag = 0;
8105 unsigned WrapperKind = X86ISD::Wrapper;
8106 CodeModel::Model M = getTargetMachine().getCodeModel();
8108 if (Subtarget->isPICStyleRIPRel() &&
8109 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8110 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8111 OpFlag = X86II::MO_GOTPCREL;
8112 WrapperKind = X86ISD::WrapperRIP;
8113 } else if (Subtarget->isPICStyleGOT()) {
8114 OpFlag = X86II::MO_GOT;
8115 } else if (Subtarget->isPICStyleStubPIC()) {
8116 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8117 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8118 OpFlag = X86II::MO_DARWIN_NONLAZY;
8121 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8124 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8126 // With PIC, the address is actually $g + Offset.
8127 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8128 !Subtarget->is64Bit()) {
8129 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8130 DAG.getNode(X86ISD::GlobalBaseReg,
8131 SDLoc(), getPointerTy()),
8135 // For symbols that require a load from a stub to get the address, emit the
8137 if (isGlobalStubReference(OpFlag))
8138 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8139 MachinePointerInfo::getGOT(), false, false, false, 0);
8145 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8146 // Create the TargetBlockAddressAddress node.
8147 unsigned char OpFlags =
8148 Subtarget->ClassifyBlockAddressReference();
8149 CodeModel::Model M = getTargetMachine().getCodeModel();
8150 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8151 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8153 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8156 if (Subtarget->isPICStyleRIPRel() &&
8157 (M == CodeModel::Small || M == CodeModel::Kernel))
8158 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8160 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8162 // With PIC, the address is actually $g + Offset.
8163 if (isGlobalRelativeToPICBase(OpFlags)) {
8164 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8165 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8173 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8174 int64_t Offset, SelectionDAG &DAG) const {
8175 // Create the TargetGlobalAddress node, folding in the constant
8176 // offset if it is legal.
8177 unsigned char OpFlags =
8178 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8179 CodeModel::Model M = getTargetMachine().getCodeModel();
8181 if (OpFlags == X86II::MO_NO_FLAG &&
8182 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8183 // A direct static reference to a global.
8184 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8187 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8190 if (Subtarget->isPICStyleRIPRel() &&
8191 (M == CodeModel::Small || M == CodeModel::Kernel))
8192 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8194 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8196 // With PIC, the address is actually $g + Offset.
8197 if (isGlobalRelativeToPICBase(OpFlags)) {
8198 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8199 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8203 // For globals that require a load from a stub to get the address, emit the
8205 if (isGlobalStubReference(OpFlags))
8206 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8207 MachinePointerInfo::getGOT(), false, false, false, 0);
8209 // If there was a non-zero offset that we didn't fold, create an explicit
8212 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8213 DAG.getConstant(Offset, getPointerTy()));
8219 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8220 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8221 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8222 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8226 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8227 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8228 unsigned char OperandFlags, bool LocalDynamic = false) {
8229 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8230 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8232 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8233 GA->getValueType(0),
8237 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8241 SDValue Ops[] = { Chain, TGA, *InFlag };
8242 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8244 SDValue Ops[] = { Chain, TGA };
8245 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8248 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8249 MFI->setAdjustsStack(true);
8251 SDValue Flag = Chain.getValue(1);
8252 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8255 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8257 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8260 SDLoc dl(GA); // ? function entry point might be better
8261 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8262 DAG.getNode(X86ISD::GlobalBaseReg,
8263 SDLoc(), PtrVT), InFlag);
8264 InFlag = Chain.getValue(1);
8266 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8269 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8271 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8273 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8274 X86::RAX, X86II::MO_TLSGD);
8277 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8283 // Get the start address of the TLS block for this module.
8284 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8285 .getInfo<X86MachineFunctionInfo>();
8286 MFI->incNumLocalDynamicTLSAccesses();
8290 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8291 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8294 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8295 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8296 InFlag = Chain.getValue(1);
8297 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8298 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8301 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8305 unsigned char OperandFlags = X86II::MO_DTPOFF;
8306 unsigned WrapperKind = X86ISD::Wrapper;
8307 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8308 GA->getValueType(0),
8309 GA->getOffset(), OperandFlags);
8310 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8312 // Add x@dtpoff with the base.
8313 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8316 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8317 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8318 const EVT PtrVT, TLSModel::Model model,
8319 bool is64Bit, bool isPIC) {
8322 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8323 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8324 is64Bit ? 257 : 256));
8326 SDValue ThreadPointer =
8327 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8328 MachinePointerInfo(Ptr), false, false, false, 0);
8330 unsigned char OperandFlags = 0;
8331 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8333 unsigned WrapperKind = X86ISD::Wrapper;
8334 if (model == TLSModel::LocalExec) {
8335 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8336 } else if (model == TLSModel::InitialExec) {
8338 OperandFlags = X86II::MO_GOTTPOFF;
8339 WrapperKind = X86ISD::WrapperRIP;
8341 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8344 llvm_unreachable("Unexpected model");
8347 // emit "addl x@ntpoff,%eax" (local exec)
8348 // or "addl x@indntpoff,%eax" (initial exec)
8349 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8351 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8352 GA->getOffset(), OperandFlags);
8353 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8355 if (model == TLSModel::InitialExec) {
8356 if (isPIC && !is64Bit) {
8357 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8358 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8362 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8363 MachinePointerInfo::getGOT(), false, false, false, 0);
8366 // The address of the thread local variable is the add of the thread
8367 // pointer with the offset of the variable.
8368 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8372 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8374 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8375 const GlobalValue *GV = GA->getGlobal();
8377 if (Subtarget->isTargetELF()) {
8378 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8381 case TLSModel::GeneralDynamic:
8382 if (Subtarget->is64Bit())
8383 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8384 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8385 case TLSModel::LocalDynamic:
8386 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8387 Subtarget->is64Bit());
8388 case TLSModel::InitialExec:
8389 case TLSModel::LocalExec:
8390 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8391 Subtarget->is64Bit(),
8392 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8394 llvm_unreachable("Unknown TLS model.");
8397 if (Subtarget->isTargetDarwin()) {
8398 // Darwin only has one model of TLS. Lower to that.
8399 unsigned char OpFlag = 0;
8400 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8401 X86ISD::WrapperRIP : X86ISD::Wrapper;
8403 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8405 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8406 !Subtarget->is64Bit();
8408 OpFlag = X86II::MO_TLVP_PIC_BASE;
8410 OpFlag = X86II::MO_TLVP;
8412 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8413 GA->getValueType(0),
8414 GA->getOffset(), OpFlag);
8415 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8417 // With PIC32, the address is actually $g + Offset.
8419 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8420 DAG.getNode(X86ISD::GlobalBaseReg,
8421 SDLoc(), getPointerTy()),
8424 // Lowering the machine isd will make sure everything is in the right
8426 SDValue Chain = DAG.getEntryNode();
8427 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8428 SDValue Args[] = { Chain, Offset };
8429 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8431 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8432 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8433 MFI->setAdjustsStack(true);
8435 // And our return value (tls address) is in the standard call return value
8437 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8438 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8442 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8443 // Just use the implicit TLS architecture
8444 // Need to generate someting similar to:
8445 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8447 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8448 // mov rcx, qword [rdx+rcx*8]
8449 // mov eax, .tls$:tlsvar
8450 // [rax+rcx] contains the address
8451 // Windows 64bit: gs:0x58
8452 // Windows 32bit: fs:__tls_array
8454 // If GV is an alias then use the aliasee for determining
8455 // thread-localness.
8456 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8457 GV = GA->resolveAliasedGlobal(false);
8459 SDValue Chain = DAG.getEntryNode();
8461 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8462 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8463 // use its literal value of 0x2C.
8464 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8465 ? Type::getInt8PtrTy(*DAG.getContext(),
8467 : Type::getInt32PtrTy(*DAG.getContext(),
8470 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8471 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8472 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8474 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8475 MachinePointerInfo(Ptr),
8476 false, false, false, 0);
8478 // Load the _tls_index variable
8479 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8480 if (Subtarget->is64Bit())
8481 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8482 IDX, MachinePointerInfo(), MVT::i32,
8485 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8486 false, false, false, 0);
8488 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8490 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8492 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8493 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8494 false, false, false, 0);
8496 // Get the offset of start of .tls section
8497 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8498 GA->getValueType(0),
8499 GA->getOffset(), X86II::MO_SECREL);
8500 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8502 // The address of the thread local variable is the add of the thread
8503 // pointer with the offset of the variable.
8504 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8507 llvm_unreachable("TLS not implemented for this target.");
8510 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8511 /// and take a 2 x i32 value to shift plus a shift amount.
8512 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
8513 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8514 MVT VT = Op.getSimpleValueType();
8515 unsigned VTBits = VT.getSizeInBits();
8517 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8518 SDValue ShOpLo = Op.getOperand(0);
8519 SDValue ShOpHi = Op.getOperand(1);
8520 SDValue ShAmt = Op.getOperand(2);
8521 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8522 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8524 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8525 DAG.getConstant(VTBits - 1, MVT::i8));
8526 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8527 DAG.getConstant(VTBits - 1, MVT::i8))
8528 : DAG.getConstant(0, VT);
8531 if (Op.getOpcode() == ISD::SHL_PARTS) {
8532 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8533 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8535 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8536 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8539 // If the shift amount is larger or equal than the width of a part we can't
8540 // rely on the results of shld/shrd. Insert a test and select the appropriate
8541 // values for large shift amounts.
8542 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8543 DAG.getConstant(VTBits, MVT::i8));
8544 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8545 AndNode, DAG.getConstant(0, MVT::i8));
8548 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8549 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8550 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8552 if (Op.getOpcode() == ISD::SHL_PARTS) {
8553 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8554 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8556 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8557 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8560 SDValue Ops[2] = { Lo, Hi };
8561 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8564 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8565 SelectionDAG &DAG) const {
8566 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
8568 if (SrcVT.isVector())
8571 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
8572 "Unknown SINT_TO_FP to lower!");
8574 // These are really Legal; return the operand so the caller accepts it as
8576 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8578 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8579 Subtarget->is64Bit()) {
8584 unsigned Size = SrcVT.getSizeInBits()/8;
8585 MachineFunction &MF = DAG.getMachineFunction();
8586 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8587 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8588 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8590 MachinePointerInfo::getFixedStack(SSFI),
8592 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8595 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8597 SelectionDAG &DAG) const {
8601 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8603 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8605 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8607 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8609 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8610 MachineMemOperand *MMO;
8612 int SSFI = FI->getIndex();
8614 DAG.getMachineFunction()
8615 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8616 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8618 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8619 StackSlot = StackSlot.getOperand(1);
8621 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8622 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8624 Tys, Ops, array_lengthof(Ops),
8628 Chain = Result.getValue(1);
8629 SDValue InFlag = Result.getValue(2);
8631 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8632 // shouldn't be necessary except that RFP cannot be live across
8633 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8634 MachineFunction &MF = DAG.getMachineFunction();
8635 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8636 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8637 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8638 Tys = DAG.getVTList(MVT::Other);
8640 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8642 MachineMemOperand *MMO =
8643 DAG.getMachineFunction()
8644 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8645 MachineMemOperand::MOStore, SSFISize, SSFISize);
8647 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8648 Ops, array_lengthof(Ops),
8649 Op.getValueType(), MMO);
8650 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8651 MachinePointerInfo::getFixedStack(SSFI),
8652 false, false, false, 0);
8658 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8659 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8660 SelectionDAG &DAG) const {
8661 // This algorithm is not obvious. Here it is what we're trying to output:
8664 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8665 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8669 pshufd $0x4e, %xmm0, %xmm1
8675 LLVMContext *Context = DAG.getContext();
8677 // Build some magic constants.
8678 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8679 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8680 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8682 SmallVector<Constant*,2> CV1;
8684 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8685 APInt(64, 0x4330000000000000ULL))));
8687 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8688 APInt(64, 0x4530000000000000ULL))));
8689 Constant *C1 = ConstantVector::get(CV1);
8690 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8692 // Load the 64-bit value into an XMM register.
8693 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8695 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8696 MachinePointerInfo::getConstantPool(),
8697 false, false, false, 16);
8698 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8699 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8702 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8703 MachinePointerInfo::getConstantPool(),
8704 false, false, false, 16);
8705 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8706 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8709 if (Subtarget->hasSSE3()) {
8710 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8711 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8713 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8714 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8716 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8717 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8721 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8722 DAG.getIntPtrConstant(0));
8725 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8726 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8727 SelectionDAG &DAG) const {
8729 // FP constant to bias correct the final result.
8730 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8733 // Load the 32-bit value into an XMM register.
8734 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8737 // Zero out the upper parts of the register.
8738 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8740 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8741 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8742 DAG.getIntPtrConstant(0));
8744 // Or the load with the bias.
8745 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8746 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8747 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8749 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8750 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8751 MVT::v2f64, Bias)));
8752 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8753 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8754 DAG.getIntPtrConstant(0));
8756 // Subtract the bias.
8757 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8759 // Handle final rounding.
8760 EVT DestVT = Op.getValueType();
8762 if (DestVT.bitsLT(MVT::f64))
8763 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8764 DAG.getIntPtrConstant(0));
8765 if (DestVT.bitsGT(MVT::f64))
8766 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8768 // Handle final rounding.
8772 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8773 SelectionDAG &DAG) const {
8774 SDValue N0 = Op.getOperand(0);
8775 MVT SVT = N0.getSimpleValueType();
8778 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8779 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8780 "Custom UINT_TO_FP is not supported!");
8782 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
8783 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8784 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8787 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8788 SelectionDAG &DAG) const {
8789 SDValue N0 = Op.getOperand(0);
8792 if (Op.getValueType().isVector())
8793 return lowerUINT_TO_FP_vec(Op, DAG);
8795 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8796 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8797 // the optimization here.
8798 if (DAG.SignBitIsZero(N0))
8799 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8801 MVT SrcVT = N0.getSimpleValueType();
8802 MVT DstVT = Op.getSimpleValueType();
8803 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8804 return LowerUINT_TO_FP_i64(Op, DAG);
8805 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8806 return LowerUINT_TO_FP_i32(Op, DAG);
8807 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8810 // Make a 64-bit buffer, and use it to build an FILD.
8811 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8812 if (SrcVT == MVT::i32) {
8813 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8814 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8815 getPointerTy(), StackSlot, WordOff);
8816 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8817 StackSlot, MachinePointerInfo(),
8819 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8820 OffsetSlot, MachinePointerInfo(),
8822 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8826 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8827 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8828 StackSlot, MachinePointerInfo(),
8830 // For i64 source, we need to add the appropriate power of 2 if the input
8831 // was negative. This is the same as the optimization in
8832 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8833 // we must be careful to do the computation in x87 extended precision, not
8834 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8835 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8836 MachineMemOperand *MMO =
8837 DAG.getMachineFunction()
8838 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8839 MachineMemOperand::MOLoad, 8, 8);
8841 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8842 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8843 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8844 array_lengthof(Ops), MVT::i64, MMO);
8846 APInt FF(32, 0x5F800000ULL);
8848 // Check whether the sign bit is set.
8849 SDValue SignSet = DAG.getSetCC(dl,
8850 getSetCCResultType(*DAG.getContext(), MVT::i64),
8851 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8854 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8855 SDValue FudgePtr = DAG.getConstantPool(
8856 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8859 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8860 SDValue Zero = DAG.getIntPtrConstant(0);
8861 SDValue Four = DAG.getIntPtrConstant(4);
8862 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8864 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8866 // Load the value out, extending it from f32 to f80.
8867 // FIXME: Avoid the extend by constructing the right constant pool?
8868 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8869 FudgePtr, MachinePointerInfo::getConstantPool(),
8870 MVT::f32, false, false, 4);
8871 // Extend everything to 80 bits to force it to be done on x87.
8872 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8873 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8876 std::pair<SDValue,SDValue>
8877 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8878 bool IsSigned, bool IsReplace) const {
8881 EVT DstTy = Op.getValueType();
8883 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8884 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8888 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8889 DstTy.getSimpleVT() >= MVT::i16 &&
8890 "Unknown FP_TO_INT to lower!");
8892 // These are really Legal.
8893 if (DstTy == MVT::i32 &&
8894 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8895 return std::make_pair(SDValue(), SDValue());
8896 if (Subtarget->is64Bit() &&
8897 DstTy == MVT::i64 &&
8898 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8899 return std::make_pair(SDValue(), SDValue());
8901 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8902 // stack slot, or into the FTOL runtime function.
8903 MachineFunction &MF = DAG.getMachineFunction();
8904 unsigned MemSize = DstTy.getSizeInBits()/8;
8905 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8906 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8909 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8910 Opc = X86ISD::WIN_FTOL;
8912 switch (DstTy.getSimpleVT().SimpleTy) {
8913 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8914 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8915 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8916 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8919 SDValue Chain = DAG.getEntryNode();
8920 SDValue Value = Op.getOperand(0);
8921 EVT TheVT = Op.getOperand(0).getValueType();
8922 // FIXME This causes a redundant load/store if the SSE-class value is already
8923 // in memory, such as if it is on the callstack.
8924 if (isScalarFPTypeInSSEReg(TheVT)) {
8925 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8926 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8927 MachinePointerInfo::getFixedStack(SSFI),
8929 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8931 Chain, StackSlot, DAG.getValueType(TheVT)
8934 MachineMemOperand *MMO =
8935 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8936 MachineMemOperand::MOLoad, MemSize, MemSize);
8937 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8938 array_lengthof(Ops), DstTy, MMO);
8939 Chain = Value.getValue(1);
8940 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8941 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8944 MachineMemOperand *MMO =
8945 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8946 MachineMemOperand::MOStore, MemSize, MemSize);
8948 if (Opc != X86ISD::WIN_FTOL) {
8949 // Build the FP_TO_INT*_IN_MEM
8950 SDValue Ops[] = { Chain, Value, StackSlot };
8951 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8952 Ops, array_lengthof(Ops), DstTy,
8954 return std::make_pair(FIST, StackSlot);
8956 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8957 DAG.getVTList(MVT::Other, MVT::Glue),
8959 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8960 MVT::i32, ftol.getValue(1));
8961 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8962 MVT::i32, eax.getValue(2));
8963 SDValue Ops[] = { eax, edx };
8964 SDValue pair = IsReplace
8965 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8966 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8967 return std::make_pair(pair, SDValue());
8971 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8972 const X86Subtarget *Subtarget) {
8973 MVT VT = Op->getSimpleValueType(0);
8974 SDValue In = Op->getOperand(0);
8975 MVT InVT = In.getSimpleValueType();
8978 // Optimize vectors in AVX mode:
8981 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8982 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8983 // Concat upper and lower parts.
8986 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8987 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8988 // Concat upper and lower parts.
8991 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
8992 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8993 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8996 if (Subtarget->hasInt256())
8997 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8999 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
9000 SDValue Undef = DAG.getUNDEF(InVT);
9001 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
9002 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9003 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9005 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9006 VT.getVectorNumElements()/2);
9008 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9009 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9011 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9014 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9015 SelectionDAG &DAG) {
9016 MVT VT = Op->getSimpleValueType(0);
9017 SDValue In = Op->getOperand(0);
9018 MVT InVT = In.getSimpleValueType();
9020 unsigned int NumElts = VT.getVectorNumElements();
9021 if (NumElts != 8 && NumElts != 16)
9024 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9025 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9027 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9028 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9029 // Now we have only mask extension
9030 assert(InVT.getVectorElementType() == MVT::i1);
9031 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9032 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9033 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9034 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9035 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9036 MachinePointerInfo::getConstantPool(),
9037 false, false, false, Alignment);
9039 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9040 if (VT.is512BitVector())
9042 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9045 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9046 SelectionDAG &DAG) {
9047 if (Subtarget->hasFp256()) {
9048 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9056 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9057 SelectionDAG &DAG) {
9059 MVT VT = Op.getSimpleValueType();
9060 SDValue In = Op.getOperand(0);
9061 MVT SVT = In.getSimpleValueType();
9063 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9064 return LowerZERO_EXTEND_AVX512(Op, DAG);
9066 if (Subtarget->hasFp256()) {
9067 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9072 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9073 VT.getVectorNumElements() != SVT.getVectorNumElements());
9077 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9079 MVT VT = Op.getSimpleValueType();
9080 SDValue In = Op.getOperand(0);
9081 MVT InVT = In.getSimpleValueType();
9083 if (VT == MVT::i1) {
9084 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9085 "Invalid scalar TRUNCATE operation");
9086 if (InVT == MVT::i32)
9088 if (InVT.getSizeInBits() == 64)
9089 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9090 else if (InVT.getSizeInBits() < 32)
9091 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9092 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9094 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9095 "Invalid TRUNCATE operation");
9097 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9098 if (VT.getVectorElementType().getSizeInBits() >=8)
9099 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9101 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9102 unsigned NumElts = InVT.getVectorNumElements();
9103 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9104 if (InVT.getSizeInBits() < 512) {
9105 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9106 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9109 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9110 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9111 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9112 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9113 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9114 MachinePointerInfo::getConstantPool(),
9115 false, false, false, Alignment);
9116 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9117 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9118 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9121 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9122 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9123 if (Subtarget->hasInt256()) {
9124 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9125 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9126 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9128 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9129 DAG.getIntPtrConstant(0));
9132 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9133 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9134 DAG.getIntPtrConstant(0));
9135 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9136 DAG.getIntPtrConstant(2));
9138 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9139 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9142 static const int ShufMask1[] = {0, 2, 0, 0};
9143 SDValue Undef = DAG.getUNDEF(VT);
9144 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9145 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9147 // The MOVLHPS mask:
9148 static const int ShufMask2[] = {0, 1, 4, 5};
9149 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9152 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9153 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9154 if (Subtarget->hasInt256()) {
9155 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9157 SmallVector<SDValue,32> pshufbMask;
9158 for (unsigned i = 0; i < 2; ++i) {
9159 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9160 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9161 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9162 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9163 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9164 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9165 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9166 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9167 for (unsigned j = 0; j < 8; ++j)
9168 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9170 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9171 &pshufbMask[0], 32);
9172 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9173 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9175 static const int ShufMask[] = {0, 2, -1, -1};
9176 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9178 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9179 DAG.getIntPtrConstant(0));
9180 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9183 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9184 DAG.getIntPtrConstant(0));
9186 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9187 DAG.getIntPtrConstant(4));
9189 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9190 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9193 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9194 -1, -1, -1, -1, -1, -1, -1, -1};
9196 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9197 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9198 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9200 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9201 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9203 // The MOVLHPS Mask:
9204 static const int ShufMask2[] = {0, 1, 4, 5};
9205 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9206 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9209 // Handle truncation of V256 to V128 using shuffles.
9210 if (!VT.is128BitVector() || !InVT.is256BitVector())
9213 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9215 unsigned NumElems = VT.getVectorNumElements();
9216 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
9218 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9219 // Prepare truncation shuffle mask
9220 for (unsigned i = 0; i != NumElems; ++i)
9222 SDValue V = DAG.getVectorShuffle(NVT, DL,
9223 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9224 DAG.getUNDEF(NVT), &MaskVec[0]);
9225 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9226 DAG.getIntPtrConstant(0));
9229 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9230 SelectionDAG &DAG) const {
9231 MVT VT = Op.getSimpleValueType();
9232 if (VT.isVector()) {
9233 if (VT == MVT::v8i16)
9234 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9235 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9236 MVT::v8i32, Op.getOperand(0)));
9240 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9241 /*IsSigned=*/ true, /*IsReplace=*/ false);
9242 SDValue FIST = Vals.first, StackSlot = Vals.second;
9243 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9244 if (FIST.getNode() == 0) return Op;
9246 if (StackSlot.getNode())
9248 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9249 FIST, StackSlot, MachinePointerInfo(),
9250 false, false, false, 0);
9252 // The node is the result.
9256 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9257 SelectionDAG &DAG) const {
9258 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9259 /*IsSigned=*/ false, /*IsReplace=*/ false);
9260 SDValue FIST = Vals.first, StackSlot = Vals.second;
9261 assert(FIST.getNode() && "Unexpected failure");
9263 if (StackSlot.getNode())
9265 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9266 FIST, StackSlot, MachinePointerInfo(),
9267 false, false, false, 0);
9269 // The node is the result.
9273 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9275 MVT VT = Op.getSimpleValueType();
9276 SDValue In = Op.getOperand(0);
9277 MVT SVT = In.getSimpleValueType();
9279 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9281 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9282 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9283 In, DAG.getUNDEF(SVT)));
9286 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
9287 LLVMContext *Context = DAG.getContext();
9289 MVT VT = Op.getSimpleValueType();
9291 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9292 if (VT.isVector()) {
9293 EltVT = VT.getVectorElementType();
9294 NumElts = VT.getVectorNumElements();
9297 if (EltVT == MVT::f64)
9298 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9299 APInt(64, ~(1ULL << 63))));
9301 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9302 APInt(32, ~(1U << 31))));
9303 C = ConstantVector::getSplat(NumElts, C);
9304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9305 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9306 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9307 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9308 MachinePointerInfo::getConstantPool(),
9309 false, false, false, Alignment);
9310 if (VT.isVector()) {
9311 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9312 return DAG.getNode(ISD::BITCAST, dl, VT,
9313 DAG.getNode(ISD::AND, dl, ANDVT,
9314 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9316 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9318 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9321 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
9322 LLVMContext *Context = DAG.getContext();
9324 MVT VT = Op.getSimpleValueType();
9326 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9327 if (VT.isVector()) {
9328 EltVT = VT.getVectorElementType();
9329 NumElts = VT.getVectorNumElements();
9332 if (EltVT == MVT::f64)
9333 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9334 APInt(64, 1ULL << 63)));
9336 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9337 APInt(32, 1U << 31)));
9338 C = ConstantVector::getSplat(NumElts, C);
9339 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9340 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9341 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9342 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9343 MachinePointerInfo::getConstantPool(),
9344 false, false, false, Alignment);
9345 if (VT.isVector()) {
9346 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9347 return DAG.getNode(ISD::BITCAST, dl, VT,
9348 DAG.getNode(ISD::XOR, dl, XORVT,
9349 DAG.getNode(ISD::BITCAST, dl, XORVT,
9351 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9354 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9357 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
9358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9359 LLVMContext *Context = DAG.getContext();
9360 SDValue Op0 = Op.getOperand(0);
9361 SDValue Op1 = Op.getOperand(1);
9363 MVT VT = Op.getSimpleValueType();
9364 MVT SrcVT = Op1.getSimpleValueType();
9366 // If second operand is smaller, extend it first.
9367 if (SrcVT.bitsLT(VT)) {
9368 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9371 // And if it is bigger, shrink it first.
9372 if (SrcVT.bitsGT(VT)) {
9373 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9377 // At this point the operands and the result should have the same
9378 // type, and that won't be f80 since that is not custom lowered.
9380 // First get the sign bit of second operand.
9381 SmallVector<Constant*,4> CV;
9382 if (SrcVT == MVT::f64) {
9383 const fltSemantics &Sem = APFloat::IEEEdouble;
9384 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9385 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9387 const fltSemantics &Sem = APFloat::IEEEsingle;
9388 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9389 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9390 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9391 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9393 Constant *C = ConstantVector::get(CV);
9394 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9395 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9396 MachinePointerInfo::getConstantPool(),
9397 false, false, false, 16);
9398 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9400 // Shift sign bit right or left if the two operands have different types.
9401 if (SrcVT.bitsGT(VT)) {
9402 // Op0 is MVT::f32, Op1 is MVT::f64.
9403 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9404 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9405 DAG.getConstant(32, MVT::i32));
9406 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9407 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9408 DAG.getIntPtrConstant(0));
9411 // Clear first operand sign bit.
9413 if (VT == MVT::f64) {
9414 const fltSemantics &Sem = APFloat::IEEEdouble;
9415 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9416 APInt(64, ~(1ULL << 63)))));
9417 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9419 const fltSemantics &Sem = APFloat::IEEEsingle;
9420 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9421 APInt(32, ~(1U << 31)))));
9422 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9423 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9424 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9426 C = ConstantVector::get(CV);
9427 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9428 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9429 MachinePointerInfo::getConstantPool(),
9430 false, false, false, 16);
9431 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9433 // Or the value with the sign bit.
9434 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9437 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9438 SDValue N0 = Op.getOperand(0);
9440 MVT VT = Op.getSimpleValueType();
9442 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9443 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9444 DAG.getConstant(1, VT));
9445 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9448 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9450 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9451 SelectionDAG &DAG) {
9452 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9454 if (!Subtarget->hasSSE41())
9457 if (!Op->hasOneUse())
9460 SDNode *N = Op.getNode();
9463 SmallVector<SDValue, 8> Opnds;
9464 DenseMap<SDValue, unsigned> VecInMap;
9465 EVT VT = MVT::Other;
9467 // Recognize a special case where a vector is casted into wide integer to
9469 Opnds.push_back(N->getOperand(0));
9470 Opnds.push_back(N->getOperand(1));
9472 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9473 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9474 // BFS traverse all OR'd operands.
9475 if (I->getOpcode() == ISD::OR) {
9476 Opnds.push_back(I->getOperand(0));
9477 Opnds.push_back(I->getOperand(1));
9478 // Re-evaluate the number of nodes to be traversed.
9479 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9483 // Quit if a non-EXTRACT_VECTOR_ELT
9484 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9487 // Quit if without a constant index.
9488 SDValue Idx = I->getOperand(1);
9489 if (!isa<ConstantSDNode>(Idx))
9492 SDValue ExtractedFromVec = I->getOperand(0);
9493 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9494 if (M == VecInMap.end()) {
9495 VT = ExtractedFromVec.getValueType();
9496 // Quit if not 128/256-bit vector.
9497 if (!VT.is128BitVector() && !VT.is256BitVector())
9499 // Quit if not the same type.
9500 if (VecInMap.begin() != VecInMap.end() &&
9501 VT != VecInMap.begin()->first.getValueType())
9503 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9505 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9508 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9509 "Not extracted from 128-/256-bit vector.");
9511 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9512 SmallVector<SDValue, 8> VecIns;
9514 for (DenseMap<SDValue, unsigned>::const_iterator
9515 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9516 // Quit if not all elements are used.
9517 if (I->second != FullMask)
9519 VecIns.push_back(I->first);
9522 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9524 // Cast all vectors into TestVT for PTEST.
9525 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9526 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9528 // If more than one full vectors are evaluated, OR them first before PTEST.
9529 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9530 // Each iteration will OR 2 nodes and append the result until there is only
9531 // 1 node left, i.e. the final OR'd value of all vectors.
9532 SDValue LHS = VecIns[Slot];
9533 SDValue RHS = VecIns[Slot + 1];
9534 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9537 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9538 VecIns.back(), VecIns.back());
9541 /// Emit nodes that will be selected as "test Op0,Op0", or something
9543 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9544 SelectionDAG &DAG) const {
9547 if (Op.getValueType() == MVT::i1)
9548 // KORTEST instruction should be selected
9549 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9550 DAG.getConstant(0, Op.getValueType()));
9552 // CF and OF aren't always set the way we want. Determine which
9553 // of these we need.
9554 bool NeedCF = false;
9555 bool NeedOF = false;
9558 case X86::COND_A: case X86::COND_AE:
9559 case X86::COND_B: case X86::COND_BE:
9562 case X86::COND_G: case X86::COND_GE:
9563 case X86::COND_L: case X86::COND_LE:
9564 case X86::COND_O: case X86::COND_NO:
9568 // See if we can use the EFLAGS value from the operand instead of
9569 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9570 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9571 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
9572 // Emit a CMP with 0, which is the TEST pattern.
9573 //if (Op.getValueType() == MVT::i1)
9574 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
9575 // DAG.getConstant(0, MVT::i1));
9576 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9577 DAG.getConstant(0, Op.getValueType()));
9579 unsigned Opcode = 0;
9580 unsigned NumOperands = 0;
9582 // Truncate operations may prevent the merge of the SETCC instruction
9583 // and the arithmetic instruction before it. Attempt to truncate the operands
9584 // of the arithmetic instruction and use a reduced bit-width instruction.
9585 bool NeedTruncation = false;
9586 SDValue ArithOp = Op;
9587 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9588 SDValue Arith = Op->getOperand(0);
9589 // Both the trunc and the arithmetic op need to have one user each.
9590 if (Arith->hasOneUse())
9591 switch (Arith.getOpcode()) {
9598 NeedTruncation = true;
9604 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9605 // which may be the result of a CAST. We use the variable 'Op', which is the
9606 // non-casted variable when we check for possible users.
9607 switch (ArithOp.getOpcode()) {
9609 // Due to an isel shortcoming, be conservative if this add is likely to be
9610 // selected as part of a load-modify-store instruction. When the root node
9611 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9612 // uses of other nodes in the match, such as the ADD in this case. This
9613 // leads to the ADD being left around and reselected, with the result being
9614 // two adds in the output. Alas, even if none our users are stores, that
9615 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9616 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9617 // climbing the DAG back to the root, and it doesn't seem to be worth the
9619 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9620 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9621 if (UI->getOpcode() != ISD::CopyToReg &&
9622 UI->getOpcode() != ISD::SETCC &&
9623 UI->getOpcode() != ISD::STORE)
9626 if (ConstantSDNode *C =
9627 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9628 // An add of one will be selected as an INC.
9629 if (C->getAPIntValue() == 1) {
9630 Opcode = X86ISD::INC;
9635 // An add of negative one (subtract of one) will be selected as a DEC.
9636 if (C->getAPIntValue().isAllOnesValue()) {
9637 Opcode = X86ISD::DEC;
9643 // Otherwise use a regular EFLAGS-setting add.
9644 Opcode = X86ISD::ADD;
9648 // If the primary and result isn't used, don't bother using X86ISD::AND,
9649 // because a TEST instruction will be better.
9650 bool NonFlagUse = false;
9651 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9652 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9654 unsigned UOpNo = UI.getOperandNo();
9655 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9656 // Look pass truncate.
9657 UOpNo = User->use_begin().getOperandNo();
9658 User = *User->use_begin();
9661 if (User->getOpcode() != ISD::BRCOND &&
9662 User->getOpcode() != ISD::SETCC &&
9663 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9676 // Due to the ISEL shortcoming noted above, be conservative if this op is
9677 // likely to be selected as part of a load-modify-store instruction.
9678 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9679 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9680 if (UI->getOpcode() == ISD::STORE)
9683 // Otherwise use a regular EFLAGS-setting instruction.
9684 switch (ArithOp.getOpcode()) {
9685 default: llvm_unreachable("unexpected operator!");
9686 case ISD::SUB: Opcode = X86ISD::SUB; break;
9687 case ISD::XOR: Opcode = X86ISD::XOR; break;
9688 case ISD::AND: Opcode = X86ISD::AND; break;
9690 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9691 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9692 if (EFLAGS.getNode())
9695 Opcode = X86ISD::OR;
9709 return SDValue(Op.getNode(), 1);
9715 // If we found that truncation is beneficial, perform the truncation and
9717 if (NeedTruncation) {
9718 EVT VT = Op.getValueType();
9719 SDValue WideVal = Op->getOperand(0);
9720 EVT WideVT = WideVal.getValueType();
9721 unsigned ConvertedOp = 0;
9722 // Use a target machine opcode to prevent further DAGCombine
9723 // optimizations that may separate the arithmetic operations
9724 // from the setcc node.
9725 switch (WideVal.getOpcode()) {
9727 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9728 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9729 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9730 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9731 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9735 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9736 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9737 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9738 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9739 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9745 // Emit a CMP with 0, which is the TEST pattern.
9746 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9747 DAG.getConstant(0, Op.getValueType()));
9749 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9750 SmallVector<SDValue, 4> Ops;
9751 for (unsigned i = 0; i != NumOperands; ++i)
9752 Ops.push_back(Op.getOperand(i));
9754 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9755 DAG.ReplaceAllUsesWith(Op, New);
9756 return SDValue(New.getNode(), 1);
9759 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9761 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9762 SelectionDAG &DAG) const {
9764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9765 if (C->getAPIntValue() == 0)
9766 return EmitTest(Op0, X86CC, DAG);
9768 if (Op0.getValueType() == MVT::i1) {
9770 Op0 = DAG.getNode(ISD::XOR, dl, MVT::i1, Op0,
9771 DAG.getConstant(-1, MVT::i1));
9772 return EmitTest(Op0, X86CC, DAG);
9776 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9777 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9778 // Do the comparison at i32 if it's smaller. This avoids subregister
9779 // aliasing issues. Keep the smaller reference if we're optimizing for
9780 // size, however, as that'll allow better folding of memory operations.
9781 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9782 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9783 AttributeSet::FunctionIndex, Attribute::MinSize)) {
9785 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9786 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9787 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9789 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9790 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9791 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9793 return SDValue(Sub.getNode(), 1);
9795 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9798 /// Convert a comparison if required by the subtarget.
9799 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9800 SelectionDAG &DAG) const {
9801 // If the subtarget does not support the FUCOMI instruction, floating-point
9802 // comparisons have to be converted.
9803 if (Subtarget->hasCMov() ||
9804 Cmp.getOpcode() != X86ISD::CMP ||
9805 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9806 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9809 // The instruction selector will select an FUCOM instruction instead of
9810 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9811 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9812 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9814 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9815 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9816 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9817 DAG.getConstant(8, MVT::i8));
9818 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9819 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9822 static bool isAllOnes(SDValue V) {
9823 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9824 return C && C->isAllOnesValue();
9827 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9828 /// if it's possible.
9829 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9830 SDLoc dl, SelectionDAG &DAG) const {
9831 SDValue Op0 = And.getOperand(0);
9832 SDValue Op1 = And.getOperand(1);
9833 if (Op0.getOpcode() == ISD::TRUNCATE)
9834 Op0 = Op0.getOperand(0);
9835 if (Op1.getOpcode() == ISD::TRUNCATE)
9836 Op1 = Op1.getOperand(0);
9839 if (Op1.getOpcode() == ISD::SHL)
9840 std::swap(Op0, Op1);
9841 if (Op0.getOpcode() == ISD::SHL) {
9842 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9843 if (And00C->getZExtValue() == 1) {
9844 // If we looked past a truncate, check that it's only truncating away
9846 unsigned BitWidth = Op0.getValueSizeInBits();
9847 unsigned AndBitWidth = And.getValueSizeInBits();
9848 if (BitWidth > AndBitWidth) {
9850 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9851 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9855 RHS = Op0.getOperand(1);
9857 } else if (Op1.getOpcode() == ISD::Constant) {
9858 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9859 uint64_t AndRHSVal = AndRHS->getZExtValue();
9860 SDValue AndLHS = Op0;
9862 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9863 LHS = AndLHS.getOperand(0);
9864 RHS = AndLHS.getOperand(1);
9867 // Use BT if the immediate can't be encoded in a TEST instruction.
9868 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9870 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9874 if (LHS.getNode()) {
9875 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9876 // instruction. Since the shift amount is in-range-or-undefined, we know
9877 // that doing a bittest on the i32 value is ok. We extend to i32 because
9878 // the encoding for the i16 version is larger than the i32 version.
9879 // Also promote i16 to i32 for performance / code size reason.
9880 if (LHS.getValueType() == MVT::i8 ||
9881 LHS.getValueType() == MVT::i16)
9882 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9884 // If the operand types disagree, extend the shift amount to match. Since
9885 // BT ignores high bits (like shifts) we can use anyextend.
9886 if (LHS.getValueType() != RHS.getValueType())
9887 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9889 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9890 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9891 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9892 DAG.getConstant(Cond, MVT::i8), BT);
9898 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9900 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9905 // SSE Condition code mapping:
9914 switch (SetCCOpcode) {
9915 default: llvm_unreachable("Unexpected SETCC condition");
9917 case ISD::SETEQ: SSECC = 0; break;
9919 case ISD::SETGT: Swap = true; // Fallthrough
9921 case ISD::SETOLT: SSECC = 1; break;
9923 case ISD::SETGE: Swap = true; // Fallthrough
9925 case ISD::SETOLE: SSECC = 2; break;
9926 case ISD::SETUO: SSECC = 3; break;
9928 case ISD::SETNE: SSECC = 4; break;
9929 case ISD::SETULE: Swap = true; // Fallthrough
9930 case ISD::SETUGE: SSECC = 5; break;
9931 case ISD::SETULT: Swap = true; // Fallthrough
9932 case ISD::SETUGT: SSECC = 6; break;
9933 case ISD::SETO: SSECC = 7; break;
9935 case ISD::SETONE: SSECC = 8; break;
9938 std::swap(Op0, Op1);
9943 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9944 // ones, and then concatenate the result back.
9945 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9946 MVT VT = Op.getSimpleValueType();
9948 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9949 "Unsupported value type for operation");
9951 unsigned NumElems = VT.getVectorNumElements();
9953 SDValue CC = Op.getOperand(2);
9955 // Extract the LHS vectors
9956 SDValue LHS = Op.getOperand(0);
9957 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9958 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9960 // Extract the RHS vectors
9961 SDValue RHS = Op.getOperand(1);
9962 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9963 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9965 // Issue the operation on the smaller types and concatenate the result back
9966 MVT EltVT = VT.getVectorElementType();
9967 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9968 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9969 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9970 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9973 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9974 SDValue Op0 = Op.getOperand(0);
9975 SDValue Op1 = Op.getOperand(1);
9976 SDValue CC = Op.getOperand(2);
9977 MVT VT = Op.getSimpleValueType();
9979 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9980 Op.getValueType().getScalarType() == MVT::i1 &&
9981 "Cannot set masked compare for this operation");
9983 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9986 bool Unsigned = false;
9988 switch (SetCCOpcode) {
9989 default: llvm_unreachable("Unexpected SETCC condition");
9990 case ISD::SETNE: SSECC = 4; break;
9991 case ISD::SETEQ: SSECC = 0; break;
9992 case ISD::SETUGT: Unsigned = true;
9993 case ISD::SETGT: SSECC = 6; break; // NLE
9994 case ISD::SETULT: Unsigned = true;
9995 case ISD::SETLT: SSECC = 1; break;
9996 case ISD::SETUGE: Unsigned = true;
9997 case ISD::SETGE: SSECC = 5; break; // NLT
9998 case ISD::SETULE: Unsigned = true;
9999 case ISD::SETLE: SSECC = 2; break;
10001 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
10002 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10003 DAG.getConstant(SSECC, MVT::i8));
10007 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
10008 SelectionDAG &DAG) {
10009 SDValue Op0 = Op.getOperand(0);
10010 SDValue Op1 = Op.getOperand(1);
10011 SDValue CC = Op.getOperand(2);
10012 MVT VT = Op.getSimpleValueType();
10013 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10014 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10019 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10020 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10023 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10024 unsigned Opc = X86ISD::CMPP;
10025 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10026 assert(VT.getVectorNumElements() <= 16);
10027 Opc = X86ISD::CMPM;
10029 // In the two special cases we can't handle, emit two comparisons.
10032 unsigned CombineOpc;
10033 if (SetCCOpcode == ISD::SETUEQ) {
10034 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10036 assert(SetCCOpcode == ISD::SETONE);
10037 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10040 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10041 DAG.getConstant(CC0, MVT::i8));
10042 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10043 DAG.getConstant(CC1, MVT::i8));
10044 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10046 // Handle all other FP comparisons here.
10047 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10048 DAG.getConstant(SSECC, MVT::i8));
10051 // Break 256-bit integer vector compare into smaller ones.
10052 if (VT.is256BitVector() && !Subtarget->hasInt256())
10053 return Lower256IntVSETCC(Op, DAG);
10055 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10056 EVT OpVT = Op1.getValueType();
10057 if (Subtarget->hasAVX512()) {
10058 if (Op1.getValueType().is512BitVector() ||
10059 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10060 return LowerIntVSETCC_AVX512(Op, DAG);
10062 // In AVX-512 architecture setcc returns mask with i1 elements,
10063 // But there is no compare instruction for i8 and i16 elements.
10064 // We are not talking about 512-bit operands in this case, these
10065 // types are illegal.
10067 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10068 OpVT.getVectorElementType().getSizeInBits() >= 8))
10069 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10070 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10073 // We are handling one of the integer comparisons here. Since SSE only has
10074 // GT and EQ comparisons for integer, swapping operands and multiple
10075 // operations may be required for some comparisons.
10077 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10079 switch (SetCCOpcode) {
10080 default: llvm_unreachable("Unexpected SETCC condition");
10081 case ISD::SETNE: Invert = true;
10082 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
10083 case ISD::SETLT: Swap = true;
10084 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
10085 case ISD::SETGE: Swap = true;
10086 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10087 Invert = true; break;
10088 case ISD::SETULT: Swap = true;
10089 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10090 FlipSigns = true; break;
10091 case ISD::SETUGE: Swap = true;
10092 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10093 FlipSigns = true; Invert = true; break;
10096 // Special case: Use min/max operations for SETULE/SETUGE
10097 MVT VET = VT.getVectorElementType();
10099 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10100 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10103 switch (SetCCOpcode) {
10105 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10106 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10109 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10113 std::swap(Op0, Op1);
10115 // Check that the operation in question is available (most are plain SSE2,
10116 // but PCMPGTQ and PCMPEQQ have different requirements).
10117 if (VT == MVT::v2i64) {
10118 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10119 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10121 // First cast everything to the right type.
10122 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10123 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10125 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10126 // bits of the inputs before performing those operations. The lower
10127 // compare is always unsigned.
10130 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10132 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10133 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10134 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10135 Sign, Zero, Sign, Zero);
10137 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10138 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10140 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10141 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10142 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10144 // Create masks for only the low parts/high parts of the 64 bit integers.
10145 static const int MaskHi[] = { 1, 1, 3, 3 };
10146 static const int MaskLo[] = { 0, 0, 2, 2 };
10147 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10148 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10149 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10151 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10152 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10155 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10157 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10160 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10161 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10162 // pcmpeqd + pshufd + pand.
10163 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10165 // First cast everything to the right type.
10166 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10167 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10170 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10172 // Make sure the lower and upper halves are both all-ones.
10173 static const int Mask[] = { 1, 0, 3, 2 };
10174 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10175 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10178 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10180 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10184 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10185 // bits of the inputs before performing those operations.
10187 EVT EltVT = VT.getVectorElementType();
10188 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10189 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10190 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10193 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10195 // If the logical-not of the result is required, perform that now.
10197 Result = DAG.getNOT(dl, Result, VT);
10200 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10205 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10207 MVT VT = Op.getSimpleValueType();
10209 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10211 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10212 && "SetCC type must be 8-bit or 1-bit integer");
10213 SDValue Op0 = Op.getOperand(0);
10214 SDValue Op1 = Op.getOperand(1);
10216 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10218 // Optimize to BT if possible.
10219 // Lower (X & (1 << N)) == 0 to BT(X, N).
10220 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10221 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10222 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10223 Op1.getOpcode() == ISD::Constant &&
10224 cast<ConstantSDNode>(Op1)->isNullValue() &&
10225 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10226 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10227 if (NewSetCC.getNode())
10231 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10233 if (Op1.getOpcode() == ISD::Constant &&
10234 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10235 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10236 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10238 // If the input is a setcc, then reuse the input setcc or use a new one with
10239 // the inverted condition.
10240 if (Op0.getOpcode() == X86ISD::SETCC) {
10241 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10242 bool Invert = (CC == ISD::SETNE) ^
10243 cast<ConstantSDNode>(Op1)->isNullValue();
10247 CCode = X86::GetOppositeBranchCondition(CCode);
10248 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10249 DAG.getConstant(CCode, MVT::i8),
10250 Op0.getOperand(1));
10252 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10257 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10258 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10259 if (X86CC == X86::COND_INVALID)
10262 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10263 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10264 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10265 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10267 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10271 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10272 static bool isX86LogicalCmp(SDValue Op) {
10273 unsigned Opc = Op.getNode()->getOpcode();
10274 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10275 Opc == X86ISD::SAHF)
10277 if (Op.getResNo() == 1 &&
10278 (Opc == X86ISD::ADD ||
10279 Opc == X86ISD::SUB ||
10280 Opc == X86ISD::ADC ||
10281 Opc == X86ISD::SBB ||
10282 Opc == X86ISD::SMUL ||
10283 Opc == X86ISD::UMUL ||
10284 Opc == X86ISD::INC ||
10285 Opc == X86ISD::DEC ||
10286 Opc == X86ISD::OR ||
10287 Opc == X86ISD::XOR ||
10288 Opc == X86ISD::AND))
10291 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10297 static bool isZero(SDValue V) {
10298 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10299 return C && C->isNullValue();
10302 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10303 if (V.getOpcode() != ISD::TRUNCATE)
10306 SDValue VOp0 = V.getOperand(0);
10307 unsigned InBits = VOp0.getValueSizeInBits();
10308 unsigned Bits = V.getValueSizeInBits();
10309 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10312 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10313 bool addTest = true;
10314 SDValue Cond = Op.getOperand(0);
10315 SDValue Op1 = Op.getOperand(1);
10316 SDValue Op2 = Op.getOperand(2);
10318 EVT VT = Op1.getValueType();
10321 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10322 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10323 // sequence later on.
10324 if (Cond.getOpcode() == ISD::SETCC &&
10325 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10326 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10327 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10328 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10329 int SSECC = translateX86FSETCC(
10330 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10333 if (Subtarget->hasAVX512()) {
10334 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10335 DAG.getConstant(SSECC, MVT::i8));
10336 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10338 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10339 DAG.getConstant(SSECC, MVT::i8));
10340 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10341 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10342 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10346 if (Cond.getOpcode() == ISD::SETCC) {
10347 SDValue NewCond = LowerSETCC(Cond, DAG);
10348 if (NewCond.getNode())
10352 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10353 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10354 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10355 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10356 if (Cond.getOpcode() == X86ISD::SETCC &&
10357 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10358 isZero(Cond.getOperand(1).getOperand(1))) {
10359 SDValue Cmp = Cond.getOperand(1);
10361 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10363 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10364 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10365 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10367 SDValue CmpOp0 = Cmp.getOperand(0);
10368 // Apply further optimizations for special cases
10369 // (select (x != 0), -1, 0) -> neg & sbb
10370 // (select (x == 0), 0, -1) -> neg & sbb
10371 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10372 if (YC->isNullValue() &&
10373 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10374 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10375 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10376 DAG.getConstant(0, CmpOp0.getValueType()),
10378 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10379 DAG.getConstant(X86::COND_B, MVT::i8),
10380 SDValue(Neg.getNode(), 1));
10384 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10385 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10386 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10388 SDValue Res = // Res = 0 or -1.
10389 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10390 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10392 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10393 Res = DAG.getNOT(DL, Res, Res.getValueType());
10395 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10396 if (N2C == 0 || !N2C->isNullValue())
10397 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10402 // Look past (and (setcc_carry (cmp ...)), 1).
10403 if (Cond.getOpcode() == ISD::AND &&
10404 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10405 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10406 if (C && C->getAPIntValue() == 1)
10407 Cond = Cond.getOperand(0);
10410 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10411 // setting operand in place of the X86ISD::SETCC.
10412 unsigned CondOpcode = Cond.getOpcode();
10413 if (CondOpcode == X86ISD::SETCC ||
10414 CondOpcode == X86ISD::SETCC_CARRY) {
10415 CC = Cond.getOperand(0);
10417 SDValue Cmp = Cond.getOperand(1);
10418 unsigned Opc = Cmp.getOpcode();
10419 MVT VT = Op.getSimpleValueType();
10421 bool IllegalFPCMov = false;
10422 if (VT.isFloatingPoint() && !VT.isVector() &&
10423 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10424 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10426 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10427 Opc == X86ISD::BT) { // FIXME
10431 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10432 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10433 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10434 Cond.getOperand(0).getValueType() != MVT::i8)) {
10435 SDValue LHS = Cond.getOperand(0);
10436 SDValue RHS = Cond.getOperand(1);
10437 unsigned X86Opcode;
10440 switch (CondOpcode) {
10441 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10442 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10443 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10444 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10445 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10446 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10447 default: llvm_unreachable("unexpected overflowing operator");
10449 if (CondOpcode == ISD::UMULO)
10450 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10453 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10455 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10457 if (CondOpcode == ISD::UMULO)
10458 Cond = X86Op.getValue(2);
10460 Cond = X86Op.getValue(1);
10462 CC = DAG.getConstant(X86Cond, MVT::i8);
10467 // Look pass the truncate if the high bits are known zero.
10468 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10469 Cond = Cond.getOperand(0);
10471 // We know the result of AND is compared against zero. Try to match
10473 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10474 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10475 if (NewSetCC.getNode()) {
10476 CC = NewSetCC.getOperand(0);
10477 Cond = NewSetCC.getOperand(1);
10484 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10485 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10488 // a < b ? -1 : 0 -> RES = ~setcc_carry
10489 // a < b ? 0 : -1 -> RES = setcc_carry
10490 // a >= b ? -1 : 0 -> RES = setcc_carry
10491 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10492 if (Cond.getOpcode() == X86ISD::SUB) {
10493 Cond = ConvertCmpIfNecessary(Cond, DAG);
10494 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10496 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10497 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10498 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10499 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10500 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10501 return DAG.getNOT(DL, Res, Res.getValueType());
10506 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10507 // widen the cmov and push the truncate through. This avoids introducing a new
10508 // branch during isel and doesn't add any extensions.
10509 if (Op.getValueType() == MVT::i8 &&
10510 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10511 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10512 if (T1.getValueType() == T2.getValueType() &&
10513 // Blacklist CopyFromReg to avoid partial register stalls.
10514 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10515 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10516 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10517 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10521 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10522 // condition is true.
10523 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10524 SDValue Ops[] = { Op2, Op1, CC, Cond };
10525 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10528 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10529 MVT VT = Op->getSimpleValueType(0);
10530 SDValue In = Op->getOperand(0);
10531 MVT InVT = In.getSimpleValueType();
10534 unsigned int NumElts = VT.getVectorNumElements();
10535 if (NumElts != 8 && NumElts != 16)
10538 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10539 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10542 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10544 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10545 Constant *C = ConstantInt::get(*DAG.getContext(),
10546 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10548 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10549 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10550 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10551 MachinePointerInfo::getConstantPool(),
10552 false, false, false, Alignment);
10553 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10554 if (VT.is512BitVector())
10556 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10559 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10560 SelectionDAG &DAG) {
10561 MVT VT = Op->getSimpleValueType(0);
10562 SDValue In = Op->getOperand(0);
10563 MVT InVT = In.getSimpleValueType();
10566 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10567 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10569 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10570 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10571 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10574 if (Subtarget->hasInt256())
10575 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10577 // Optimize vectors in AVX mode
10578 // Sign extend v8i16 to v8i32 and
10581 // Divide input vector into two parts
10582 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10583 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10584 // concat the vectors to original VT
10586 unsigned NumElems = InVT.getVectorNumElements();
10587 SDValue Undef = DAG.getUNDEF(InVT);
10589 SmallVector<int,8> ShufMask1(NumElems, -1);
10590 for (unsigned i = 0; i != NumElems/2; ++i)
10593 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10595 SmallVector<int,8> ShufMask2(NumElems, -1);
10596 for (unsigned i = 0; i != NumElems/2; ++i)
10597 ShufMask2[i] = i + NumElems/2;
10599 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10601 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10602 VT.getVectorNumElements()/2);
10604 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10605 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10607 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10610 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10611 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10612 // from the AND / OR.
10613 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10614 Opc = Op.getOpcode();
10615 if (Opc != ISD::OR && Opc != ISD::AND)
10617 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10618 Op.getOperand(0).hasOneUse() &&
10619 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10620 Op.getOperand(1).hasOneUse());
10623 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10624 // 1 and that the SETCC node has a single use.
10625 static bool isXor1OfSetCC(SDValue Op) {
10626 if (Op.getOpcode() != ISD::XOR)
10628 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10629 if (N1C && N1C->getAPIntValue() == 1) {
10630 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10631 Op.getOperand(0).hasOneUse();
10636 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10637 bool addTest = true;
10638 SDValue Chain = Op.getOperand(0);
10639 SDValue Cond = Op.getOperand(1);
10640 SDValue Dest = Op.getOperand(2);
10643 bool Inverted = false;
10645 if (Cond.getOpcode() == ISD::SETCC) {
10646 // Check for setcc([su]{add,sub,mul}o == 0).
10647 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10648 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10649 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10650 Cond.getOperand(0).getResNo() == 1 &&
10651 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10652 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10653 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10654 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10655 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10656 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10658 Cond = Cond.getOperand(0);
10660 SDValue NewCond = LowerSETCC(Cond, DAG);
10661 if (NewCond.getNode())
10666 // FIXME: LowerXALUO doesn't handle these!!
10667 else if (Cond.getOpcode() == X86ISD::ADD ||
10668 Cond.getOpcode() == X86ISD::SUB ||
10669 Cond.getOpcode() == X86ISD::SMUL ||
10670 Cond.getOpcode() == X86ISD::UMUL)
10671 Cond = LowerXALUO(Cond, DAG);
10674 // Look pass (and (setcc_carry (cmp ...)), 1).
10675 if (Cond.getOpcode() == ISD::AND &&
10676 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10677 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10678 if (C && C->getAPIntValue() == 1)
10679 Cond = Cond.getOperand(0);
10682 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10683 // setting operand in place of the X86ISD::SETCC.
10684 unsigned CondOpcode = Cond.getOpcode();
10685 if (CondOpcode == X86ISD::SETCC ||
10686 CondOpcode == X86ISD::SETCC_CARRY) {
10687 CC = Cond.getOperand(0);
10689 SDValue Cmp = Cond.getOperand(1);
10690 unsigned Opc = Cmp.getOpcode();
10691 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10692 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10696 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10700 // These can only come from an arithmetic instruction with overflow,
10701 // e.g. SADDO, UADDO.
10702 Cond = Cond.getNode()->getOperand(1);
10708 CondOpcode = Cond.getOpcode();
10709 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10710 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10711 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10712 Cond.getOperand(0).getValueType() != MVT::i8)) {
10713 SDValue LHS = Cond.getOperand(0);
10714 SDValue RHS = Cond.getOperand(1);
10715 unsigned X86Opcode;
10718 switch (CondOpcode) {
10719 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10720 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10721 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10722 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10723 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10724 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10725 default: llvm_unreachable("unexpected overflowing operator");
10728 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10729 if (CondOpcode == ISD::UMULO)
10730 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10733 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10735 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10737 if (CondOpcode == ISD::UMULO)
10738 Cond = X86Op.getValue(2);
10740 Cond = X86Op.getValue(1);
10742 CC = DAG.getConstant(X86Cond, MVT::i8);
10746 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10747 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10748 if (CondOpc == ISD::OR) {
10749 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10750 // two branches instead of an explicit OR instruction with a
10752 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10753 isX86LogicalCmp(Cmp)) {
10754 CC = Cond.getOperand(0).getOperand(0);
10755 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10756 Chain, Dest, CC, Cmp);
10757 CC = Cond.getOperand(1).getOperand(0);
10761 } else { // ISD::AND
10762 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10763 // two branches instead of an explicit AND instruction with a
10764 // separate test. However, we only do this if this block doesn't
10765 // have a fall-through edge, because this requires an explicit
10766 // jmp when the condition is false.
10767 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10768 isX86LogicalCmp(Cmp) &&
10769 Op.getNode()->hasOneUse()) {
10770 X86::CondCode CCode =
10771 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10772 CCode = X86::GetOppositeBranchCondition(CCode);
10773 CC = DAG.getConstant(CCode, MVT::i8);
10774 SDNode *User = *Op.getNode()->use_begin();
10775 // Look for an unconditional branch following this conditional branch.
10776 // We need this because we need to reverse the successors in order
10777 // to implement FCMP_OEQ.
10778 if (User->getOpcode() == ISD::BR) {
10779 SDValue FalseBB = User->getOperand(1);
10781 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10782 assert(NewBR == User);
10786 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10787 Chain, Dest, CC, Cmp);
10788 X86::CondCode CCode =
10789 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10790 CCode = X86::GetOppositeBranchCondition(CCode);
10791 CC = DAG.getConstant(CCode, MVT::i8);
10797 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10798 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10799 // It should be transformed during dag combiner except when the condition
10800 // is set by a arithmetics with overflow node.
10801 X86::CondCode CCode =
10802 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10803 CCode = X86::GetOppositeBranchCondition(CCode);
10804 CC = DAG.getConstant(CCode, MVT::i8);
10805 Cond = Cond.getOperand(0).getOperand(1);
10807 } else if (Cond.getOpcode() == ISD::SETCC &&
10808 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10809 // For FCMP_OEQ, we can emit
10810 // two branches instead of an explicit AND instruction with a
10811 // separate test. However, we only do this if this block doesn't
10812 // have a fall-through edge, because this requires an explicit
10813 // jmp when the condition is false.
10814 if (Op.getNode()->hasOneUse()) {
10815 SDNode *User = *Op.getNode()->use_begin();
10816 // Look for an unconditional branch following this conditional branch.
10817 // We need this because we need to reverse the successors in order
10818 // to implement FCMP_OEQ.
10819 if (User->getOpcode() == ISD::BR) {
10820 SDValue FalseBB = User->getOperand(1);
10822 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10823 assert(NewBR == User);
10827 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10828 Cond.getOperand(0), Cond.getOperand(1));
10829 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10830 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10831 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10832 Chain, Dest, CC, Cmp);
10833 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10838 } else if (Cond.getOpcode() == ISD::SETCC &&
10839 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10840 // For FCMP_UNE, we can emit
10841 // two branches instead of an explicit AND instruction with a
10842 // separate test. However, we only do this if this block doesn't
10843 // have a fall-through edge, because this requires an explicit
10844 // jmp when the condition is false.
10845 if (Op.getNode()->hasOneUse()) {
10846 SDNode *User = *Op.getNode()->use_begin();
10847 // Look for an unconditional branch following this conditional branch.
10848 // We need this because we need to reverse the successors in order
10849 // to implement FCMP_UNE.
10850 if (User->getOpcode() == ISD::BR) {
10851 SDValue FalseBB = User->getOperand(1);
10853 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10854 assert(NewBR == User);
10857 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10858 Cond.getOperand(0), Cond.getOperand(1));
10859 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10860 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10861 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10862 Chain, Dest, CC, Cmp);
10863 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10873 // Look pass the truncate if the high bits are known zero.
10874 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10875 Cond = Cond.getOperand(0);
10877 // We know the result of AND is compared against zero. Try to match
10879 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10880 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10881 if (NewSetCC.getNode()) {
10882 CC = NewSetCC.getOperand(0);
10883 Cond = NewSetCC.getOperand(1);
10890 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10891 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10893 Cond = ConvertCmpIfNecessary(Cond, DAG);
10894 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10895 Chain, Dest, CC, Cond);
10898 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10899 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10900 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10901 // that the guard pages used by the OS virtual memory manager are allocated in
10902 // correct sequence.
10904 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10905 SelectionDAG &DAG) const {
10906 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10907 getTargetMachine().Options.EnableSegmentedStacks) &&
10908 "This should be used only on Windows targets or when segmented stacks "
10910 assert(!Subtarget->isTargetMacho() && "Not implemented");
10914 SDValue Chain = Op.getOperand(0);
10915 SDValue Size = Op.getOperand(1);
10916 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10917 EVT VT = Op.getNode()->getValueType(0);
10919 bool Is64Bit = Subtarget->is64Bit();
10920 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10922 if (getTargetMachine().Options.EnableSegmentedStacks) {
10923 MachineFunction &MF = DAG.getMachineFunction();
10924 MachineRegisterInfo &MRI = MF.getRegInfo();
10927 // The 64 bit implementation of segmented stacks needs to clobber both r10
10928 // r11. This makes it impossible to use it along with nested parameters.
10929 const Function *F = MF.getFunction();
10931 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10933 if (I->hasNestAttr())
10934 report_fatal_error("Cannot use segmented stacks with functions that "
10935 "have nested arguments.");
10938 const TargetRegisterClass *AddrRegClass =
10939 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10940 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10941 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10942 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10943 DAG.getRegister(Vreg, SPTy));
10944 SDValue Ops1[2] = { Value, Chain };
10945 return DAG.getMergeValues(Ops1, 2, dl);
10948 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10950 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10951 Flag = Chain.getValue(1);
10952 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10954 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10956 const X86RegisterInfo *RegInfo =
10957 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10958 unsigned SPReg = RegInfo->getStackRegister();
10959 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10960 Chain = SP.getValue(1);
10963 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10964 DAG.getConstant(-(uint64_t)Align, VT));
10965 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10968 SDValue Ops1[2] = { SP, Chain };
10969 return DAG.getMergeValues(Ops1, 2, dl);
10973 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10974 MachineFunction &MF = DAG.getMachineFunction();
10975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10977 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10980 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10981 // vastart just stores the address of the VarArgsFrameIndex slot into the
10982 // memory location argument.
10983 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10985 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10986 MachinePointerInfo(SV), false, false, 0);
10990 // gp_offset (0 - 6 * 8)
10991 // fp_offset (48 - 48 + 8 * 16)
10992 // overflow_arg_area (point to parameters coming in memory).
10994 SmallVector<SDValue, 8> MemOps;
10995 SDValue FIN = Op.getOperand(1);
10997 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10998 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
11000 FIN, MachinePointerInfo(SV), false, false, 0);
11001 MemOps.push_back(Store);
11004 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11005 FIN, DAG.getIntPtrConstant(4));
11006 Store = DAG.getStore(Op.getOperand(0), DL,
11007 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
11009 FIN, MachinePointerInfo(SV, 4), false, false, 0);
11010 MemOps.push_back(Store);
11012 // Store ptr to overflow_arg_area
11013 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11014 FIN, DAG.getIntPtrConstant(4));
11015 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11017 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11018 MachinePointerInfo(SV, 8),
11020 MemOps.push_back(Store);
11022 // Store ptr to reg_save_area.
11023 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11024 FIN, DAG.getIntPtrConstant(8));
11025 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11027 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11028 MachinePointerInfo(SV, 16), false, false, 0);
11029 MemOps.push_back(Store);
11030 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11031 &MemOps[0], MemOps.size());
11034 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11035 assert(Subtarget->is64Bit() &&
11036 "LowerVAARG only handles 64-bit va_arg!");
11037 assert((Subtarget->isTargetLinux() ||
11038 Subtarget->isTargetDarwin()) &&
11039 "Unhandled target in LowerVAARG");
11040 assert(Op.getNode()->getNumOperands() == 4);
11041 SDValue Chain = Op.getOperand(0);
11042 SDValue SrcPtr = Op.getOperand(1);
11043 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11044 unsigned Align = Op.getConstantOperandVal(3);
11047 EVT ArgVT = Op.getNode()->getValueType(0);
11048 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11049 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11052 // Decide which area this value should be read from.
11053 // TODO: Implement the AMD64 ABI in its entirety. This simple
11054 // selection mechanism works only for the basic types.
11055 if (ArgVT == MVT::f80) {
11056 llvm_unreachable("va_arg for f80 not yet implemented");
11057 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11058 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11059 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11060 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11062 llvm_unreachable("Unhandled argument type in LowerVAARG");
11065 if (ArgMode == 2) {
11066 // Sanity Check: Make sure using fp_offset makes sense.
11067 assert(!getTargetMachine().Options.UseSoftFloat &&
11068 !(DAG.getMachineFunction()
11069 .getFunction()->getAttributes()
11070 .hasAttribute(AttributeSet::FunctionIndex,
11071 Attribute::NoImplicitFloat)) &&
11072 Subtarget->hasSSE1());
11075 // Insert VAARG_64 node into the DAG
11076 // VAARG_64 returns two values: Variable Argument Address, Chain
11077 SmallVector<SDValue, 11> InstOps;
11078 InstOps.push_back(Chain);
11079 InstOps.push_back(SrcPtr);
11080 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11081 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11082 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11083 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11084 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11085 VTs, &InstOps[0], InstOps.size(),
11087 MachinePointerInfo(SV),
11089 /*Volatile=*/false,
11091 /*WriteMem=*/true);
11092 Chain = VAARG.getValue(1);
11094 // Load the next argument and return it
11095 return DAG.getLoad(ArgVT, dl,
11098 MachinePointerInfo(),
11099 false, false, false, 0);
11102 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11103 SelectionDAG &DAG) {
11104 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11105 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11106 SDValue Chain = Op.getOperand(0);
11107 SDValue DstPtr = Op.getOperand(1);
11108 SDValue SrcPtr = Op.getOperand(2);
11109 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11110 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11113 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11114 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11116 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11119 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11120 // amount is a constant. Takes immediate version of shift as input.
11121 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
11122 SDValue SrcOp, uint64_t ShiftAmt,
11123 SelectionDAG &DAG) {
11124 MVT ElementType = VT.getVectorElementType();
11126 // Check for ShiftAmt >= element width
11127 if (ShiftAmt >= ElementType.getSizeInBits()) {
11128 if (Opc == X86ISD::VSRAI)
11129 ShiftAmt = ElementType.getSizeInBits() - 1;
11131 return DAG.getConstant(0, VT);
11134 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11135 && "Unknown target vector shift-by-constant node");
11137 // Fold this packed vector shift into a build vector if SrcOp is a
11138 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
11139 if (VT == SrcOp.getSimpleValueType() &&
11140 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11141 SmallVector<SDValue, 8> Elts;
11142 unsigned NumElts = SrcOp->getNumOperands();
11143 ConstantSDNode *ND;
11146 default: llvm_unreachable(0);
11147 case X86ISD::VSHLI:
11148 for (unsigned i=0; i!=NumElts; ++i) {
11149 SDValue CurrentOp = SrcOp->getOperand(i);
11150 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11151 Elts.push_back(CurrentOp);
11154 ND = cast<ConstantSDNode>(CurrentOp);
11155 const APInt &C = ND->getAPIntValue();
11156 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11159 case X86ISD::VSRLI:
11160 for (unsigned i=0; i!=NumElts; ++i) {
11161 SDValue CurrentOp = SrcOp->getOperand(i);
11162 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11163 Elts.push_back(CurrentOp);
11166 ND = cast<ConstantSDNode>(CurrentOp);
11167 const APInt &C = ND->getAPIntValue();
11168 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11171 case X86ISD::VSRAI:
11172 for (unsigned i=0; i!=NumElts; ++i) {
11173 SDValue CurrentOp = SrcOp->getOperand(i);
11174 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11175 Elts.push_back(CurrentOp);
11178 ND = cast<ConstantSDNode>(CurrentOp);
11179 const APInt &C = ND->getAPIntValue();
11180 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11185 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
11188 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11191 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11192 // may or may not be a constant. Takes immediate version of shift as input.
11193 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
11194 SDValue SrcOp, SDValue ShAmt,
11195 SelectionDAG &DAG) {
11196 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11198 // Catch shift-by-constant.
11199 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11200 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11201 CShAmt->getZExtValue(), DAG);
11203 // Change opcode to non-immediate version
11205 default: llvm_unreachable("Unknown target vector shift node");
11206 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11207 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11208 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11211 // Need to build a vector containing shift amount
11212 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11215 ShOps[1] = DAG.getConstant(0, MVT::i32);
11216 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11217 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11219 // The return type has to be a 128-bit type with the same element
11220 // type as the input type.
11221 MVT EltVT = VT.getVectorElementType();
11222 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11224 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11225 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11228 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11230 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11232 default: return SDValue(); // Don't custom lower most intrinsics.
11233 // Comparison intrinsics.
11234 case Intrinsic::x86_sse_comieq_ss:
11235 case Intrinsic::x86_sse_comilt_ss:
11236 case Intrinsic::x86_sse_comile_ss:
11237 case Intrinsic::x86_sse_comigt_ss:
11238 case Intrinsic::x86_sse_comige_ss:
11239 case Intrinsic::x86_sse_comineq_ss:
11240 case Intrinsic::x86_sse_ucomieq_ss:
11241 case Intrinsic::x86_sse_ucomilt_ss:
11242 case Intrinsic::x86_sse_ucomile_ss:
11243 case Intrinsic::x86_sse_ucomigt_ss:
11244 case Intrinsic::x86_sse_ucomige_ss:
11245 case Intrinsic::x86_sse_ucomineq_ss:
11246 case Intrinsic::x86_sse2_comieq_sd:
11247 case Intrinsic::x86_sse2_comilt_sd:
11248 case Intrinsic::x86_sse2_comile_sd:
11249 case Intrinsic::x86_sse2_comigt_sd:
11250 case Intrinsic::x86_sse2_comige_sd:
11251 case Intrinsic::x86_sse2_comineq_sd:
11252 case Intrinsic::x86_sse2_ucomieq_sd:
11253 case Intrinsic::x86_sse2_ucomilt_sd:
11254 case Intrinsic::x86_sse2_ucomile_sd:
11255 case Intrinsic::x86_sse2_ucomigt_sd:
11256 case Intrinsic::x86_sse2_ucomige_sd:
11257 case Intrinsic::x86_sse2_ucomineq_sd: {
11261 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11262 case Intrinsic::x86_sse_comieq_ss:
11263 case Intrinsic::x86_sse2_comieq_sd:
11264 Opc = X86ISD::COMI;
11267 case Intrinsic::x86_sse_comilt_ss:
11268 case Intrinsic::x86_sse2_comilt_sd:
11269 Opc = X86ISD::COMI;
11272 case Intrinsic::x86_sse_comile_ss:
11273 case Intrinsic::x86_sse2_comile_sd:
11274 Opc = X86ISD::COMI;
11277 case Intrinsic::x86_sse_comigt_ss:
11278 case Intrinsic::x86_sse2_comigt_sd:
11279 Opc = X86ISD::COMI;
11282 case Intrinsic::x86_sse_comige_ss:
11283 case Intrinsic::x86_sse2_comige_sd:
11284 Opc = X86ISD::COMI;
11287 case Intrinsic::x86_sse_comineq_ss:
11288 case Intrinsic::x86_sse2_comineq_sd:
11289 Opc = X86ISD::COMI;
11292 case Intrinsic::x86_sse_ucomieq_ss:
11293 case Intrinsic::x86_sse2_ucomieq_sd:
11294 Opc = X86ISD::UCOMI;
11297 case Intrinsic::x86_sse_ucomilt_ss:
11298 case Intrinsic::x86_sse2_ucomilt_sd:
11299 Opc = X86ISD::UCOMI;
11302 case Intrinsic::x86_sse_ucomile_ss:
11303 case Intrinsic::x86_sse2_ucomile_sd:
11304 Opc = X86ISD::UCOMI;
11307 case Intrinsic::x86_sse_ucomigt_ss:
11308 case Intrinsic::x86_sse2_ucomigt_sd:
11309 Opc = X86ISD::UCOMI;
11312 case Intrinsic::x86_sse_ucomige_ss:
11313 case Intrinsic::x86_sse2_ucomige_sd:
11314 Opc = X86ISD::UCOMI;
11317 case Intrinsic::x86_sse_ucomineq_ss:
11318 case Intrinsic::x86_sse2_ucomineq_sd:
11319 Opc = X86ISD::UCOMI;
11324 SDValue LHS = Op.getOperand(1);
11325 SDValue RHS = Op.getOperand(2);
11326 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11327 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11328 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11329 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11330 DAG.getConstant(X86CC, MVT::i8), Cond);
11331 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11334 // Arithmetic intrinsics.
11335 case Intrinsic::x86_sse2_pmulu_dq:
11336 case Intrinsic::x86_avx2_pmulu_dq:
11337 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11338 Op.getOperand(1), Op.getOperand(2));
11340 // SSE2/AVX2 sub with unsigned saturation intrinsics
11341 case Intrinsic::x86_sse2_psubus_b:
11342 case Intrinsic::x86_sse2_psubus_w:
11343 case Intrinsic::x86_avx2_psubus_b:
11344 case Intrinsic::x86_avx2_psubus_w:
11345 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11346 Op.getOperand(1), Op.getOperand(2));
11348 // SSE3/AVX horizontal add/sub intrinsics
11349 case Intrinsic::x86_sse3_hadd_ps:
11350 case Intrinsic::x86_sse3_hadd_pd:
11351 case Intrinsic::x86_avx_hadd_ps_256:
11352 case Intrinsic::x86_avx_hadd_pd_256:
11353 case Intrinsic::x86_sse3_hsub_ps:
11354 case Intrinsic::x86_sse3_hsub_pd:
11355 case Intrinsic::x86_avx_hsub_ps_256:
11356 case Intrinsic::x86_avx_hsub_pd_256:
11357 case Intrinsic::x86_ssse3_phadd_w_128:
11358 case Intrinsic::x86_ssse3_phadd_d_128:
11359 case Intrinsic::x86_avx2_phadd_w:
11360 case Intrinsic::x86_avx2_phadd_d:
11361 case Intrinsic::x86_ssse3_phsub_w_128:
11362 case Intrinsic::x86_ssse3_phsub_d_128:
11363 case Intrinsic::x86_avx2_phsub_w:
11364 case Intrinsic::x86_avx2_phsub_d: {
11367 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11368 case Intrinsic::x86_sse3_hadd_ps:
11369 case Intrinsic::x86_sse3_hadd_pd:
11370 case Intrinsic::x86_avx_hadd_ps_256:
11371 case Intrinsic::x86_avx_hadd_pd_256:
11372 Opcode = X86ISD::FHADD;
11374 case Intrinsic::x86_sse3_hsub_ps:
11375 case Intrinsic::x86_sse3_hsub_pd:
11376 case Intrinsic::x86_avx_hsub_ps_256:
11377 case Intrinsic::x86_avx_hsub_pd_256:
11378 Opcode = X86ISD::FHSUB;
11380 case Intrinsic::x86_ssse3_phadd_w_128:
11381 case Intrinsic::x86_ssse3_phadd_d_128:
11382 case Intrinsic::x86_avx2_phadd_w:
11383 case Intrinsic::x86_avx2_phadd_d:
11384 Opcode = X86ISD::HADD;
11386 case Intrinsic::x86_ssse3_phsub_w_128:
11387 case Intrinsic::x86_ssse3_phsub_d_128:
11388 case Intrinsic::x86_avx2_phsub_w:
11389 case Intrinsic::x86_avx2_phsub_d:
11390 Opcode = X86ISD::HSUB;
11393 return DAG.getNode(Opcode, dl, Op.getValueType(),
11394 Op.getOperand(1), Op.getOperand(2));
11397 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11398 case Intrinsic::x86_sse2_pmaxu_b:
11399 case Intrinsic::x86_sse41_pmaxuw:
11400 case Intrinsic::x86_sse41_pmaxud:
11401 case Intrinsic::x86_avx2_pmaxu_b:
11402 case Intrinsic::x86_avx2_pmaxu_w:
11403 case Intrinsic::x86_avx2_pmaxu_d:
11404 case Intrinsic::x86_sse2_pminu_b:
11405 case Intrinsic::x86_sse41_pminuw:
11406 case Intrinsic::x86_sse41_pminud:
11407 case Intrinsic::x86_avx2_pminu_b:
11408 case Intrinsic::x86_avx2_pminu_w:
11409 case Intrinsic::x86_avx2_pminu_d:
11410 case Intrinsic::x86_sse41_pmaxsb:
11411 case Intrinsic::x86_sse2_pmaxs_w:
11412 case Intrinsic::x86_sse41_pmaxsd:
11413 case Intrinsic::x86_avx2_pmaxs_b:
11414 case Intrinsic::x86_avx2_pmaxs_w:
11415 case Intrinsic::x86_avx2_pmaxs_d:
11416 case Intrinsic::x86_sse41_pminsb:
11417 case Intrinsic::x86_sse2_pmins_w:
11418 case Intrinsic::x86_sse41_pminsd:
11419 case Intrinsic::x86_avx2_pmins_b:
11420 case Intrinsic::x86_avx2_pmins_w:
11421 case Intrinsic::x86_avx2_pmins_d: {
11424 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11425 case Intrinsic::x86_sse2_pmaxu_b:
11426 case Intrinsic::x86_sse41_pmaxuw:
11427 case Intrinsic::x86_sse41_pmaxud:
11428 case Intrinsic::x86_avx2_pmaxu_b:
11429 case Intrinsic::x86_avx2_pmaxu_w:
11430 case Intrinsic::x86_avx2_pmaxu_d:
11431 Opcode = X86ISD::UMAX;
11433 case Intrinsic::x86_sse2_pminu_b:
11434 case Intrinsic::x86_sse41_pminuw:
11435 case Intrinsic::x86_sse41_pminud:
11436 case Intrinsic::x86_avx2_pminu_b:
11437 case Intrinsic::x86_avx2_pminu_w:
11438 case Intrinsic::x86_avx2_pminu_d:
11439 Opcode = X86ISD::UMIN;
11441 case Intrinsic::x86_sse41_pmaxsb:
11442 case Intrinsic::x86_sse2_pmaxs_w:
11443 case Intrinsic::x86_sse41_pmaxsd:
11444 case Intrinsic::x86_avx2_pmaxs_b:
11445 case Intrinsic::x86_avx2_pmaxs_w:
11446 case Intrinsic::x86_avx2_pmaxs_d:
11447 Opcode = X86ISD::SMAX;
11449 case Intrinsic::x86_sse41_pminsb:
11450 case Intrinsic::x86_sse2_pmins_w:
11451 case Intrinsic::x86_sse41_pminsd:
11452 case Intrinsic::x86_avx2_pmins_b:
11453 case Intrinsic::x86_avx2_pmins_w:
11454 case Intrinsic::x86_avx2_pmins_d:
11455 Opcode = X86ISD::SMIN;
11458 return DAG.getNode(Opcode, dl, Op.getValueType(),
11459 Op.getOperand(1), Op.getOperand(2));
11462 // SSE/SSE2/AVX floating point max/min intrinsics.
11463 case Intrinsic::x86_sse_max_ps:
11464 case Intrinsic::x86_sse2_max_pd:
11465 case Intrinsic::x86_avx_max_ps_256:
11466 case Intrinsic::x86_avx_max_pd_256:
11467 case Intrinsic::x86_sse_min_ps:
11468 case Intrinsic::x86_sse2_min_pd:
11469 case Intrinsic::x86_avx_min_ps_256:
11470 case Intrinsic::x86_avx_min_pd_256: {
11473 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11474 case Intrinsic::x86_sse_max_ps:
11475 case Intrinsic::x86_sse2_max_pd:
11476 case Intrinsic::x86_avx_max_ps_256:
11477 case Intrinsic::x86_avx_max_pd_256:
11478 Opcode = X86ISD::FMAX;
11480 case Intrinsic::x86_sse_min_ps:
11481 case Intrinsic::x86_sse2_min_pd:
11482 case Intrinsic::x86_avx_min_ps_256:
11483 case Intrinsic::x86_avx_min_pd_256:
11484 Opcode = X86ISD::FMIN;
11487 return DAG.getNode(Opcode, dl, Op.getValueType(),
11488 Op.getOperand(1), Op.getOperand(2));
11491 // AVX2 variable shift intrinsics
11492 case Intrinsic::x86_avx2_psllv_d:
11493 case Intrinsic::x86_avx2_psllv_q:
11494 case Intrinsic::x86_avx2_psllv_d_256:
11495 case Intrinsic::x86_avx2_psllv_q_256:
11496 case Intrinsic::x86_avx2_psrlv_d:
11497 case Intrinsic::x86_avx2_psrlv_q:
11498 case Intrinsic::x86_avx2_psrlv_d_256:
11499 case Intrinsic::x86_avx2_psrlv_q_256:
11500 case Intrinsic::x86_avx2_psrav_d:
11501 case Intrinsic::x86_avx2_psrav_d_256: {
11504 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11505 case Intrinsic::x86_avx2_psllv_d:
11506 case Intrinsic::x86_avx2_psllv_q:
11507 case Intrinsic::x86_avx2_psllv_d_256:
11508 case Intrinsic::x86_avx2_psllv_q_256:
11511 case Intrinsic::x86_avx2_psrlv_d:
11512 case Intrinsic::x86_avx2_psrlv_q:
11513 case Intrinsic::x86_avx2_psrlv_d_256:
11514 case Intrinsic::x86_avx2_psrlv_q_256:
11517 case Intrinsic::x86_avx2_psrav_d:
11518 case Intrinsic::x86_avx2_psrav_d_256:
11522 return DAG.getNode(Opcode, dl, Op.getValueType(),
11523 Op.getOperand(1), Op.getOperand(2));
11526 case Intrinsic::x86_ssse3_pshuf_b_128:
11527 case Intrinsic::x86_avx2_pshuf_b:
11528 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11529 Op.getOperand(1), Op.getOperand(2));
11531 case Intrinsic::x86_ssse3_psign_b_128:
11532 case Intrinsic::x86_ssse3_psign_w_128:
11533 case Intrinsic::x86_ssse3_psign_d_128:
11534 case Intrinsic::x86_avx2_psign_b:
11535 case Intrinsic::x86_avx2_psign_w:
11536 case Intrinsic::x86_avx2_psign_d:
11537 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11538 Op.getOperand(1), Op.getOperand(2));
11540 case Intrinsic::x86_sse41_insertps:
11541 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11542 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11544 case Intrinsic::x86_avx_vperm2f128_ps_256:
11545 case Intrinsic::x86_avx_vperm2f128_pd_256:
11546 case Intrinsic::x86_avx_vperm2f128_si_256:
11547 case Intrinsic::x86_avx2_vperm2i128:
11548 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11549 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11551 case Intrinsic::x86_avx2_permd:
11552 case Intrinsic::x86_avx2_permps:
11553 // Operands intentionally swapped. Mask is last operand to intrinsic,
11554 // but second operand for node/instruction.
11555 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11556 Op.getOperand(2), Op.getOperand(1));
11558 case Intrinsic::x86_sse_sqrt_ps:
11559 case Intrinsic::x86_sse2_sqrt_pd:
11560 case Intrinsic::x86_avx_sqrt_ps_256:
11561 case Intrinsic::x86_avx_sqrt_pd_256:
11562 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11564 // ptest and testp intrinsics. The intrinsic these come from are designed to
11565 // return an integer value, not just an instruction so lower it to the ptest
11566 // or testp pattern and a setcc for the result.
11567 case Intrinsic::x86_sse41_ptestz:
11568 case Intrinsic::x86_sse41_ptestc:
11569 case Intrinsic::x86_sse41_ptestnzc:
11570 case Intrinsic::x86_avx_ptestz_256:
11571 case Intrinsic::x86_avx_ptestc_256:
11572 case Intrinsic::x86_avx_ptestnzc_256:
11573 case Intrinsic::x86_avx_vtestz_ps:
11574 case Intrinsic::x86_avx_vtestc_ps:
11575 case Intrinsic::x86_avx_vtestnzc_ps:
11576 case Intrinsic::x86_avx_vtestz_pd:
11577 case Intrinsic::x86_avx_vtestc_pd:
11578 case Intrinsic::x86_avx_vtestnzc_pd:
11579 case Intrinsic::x86_avx_vtestz_ps_256:
11580 case Intrinsic::x86_avx_vtestc_ps_256:
11581 case Intrinsic::x86_avx_vtestnzc_ps_256:
11582 case Intrinsic::x86_avx_vtestz_pd_256:
11583 case Intrinsic::x86_avx_vtestc_pd_256:
11584 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11585 bool IsTestPacked = false;
11588 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11589 case Intrinsic::x86_avx_vtestz_ps:
11590 case Intrinsic::x86_avx_vtestz_pd:
11591 case Intrinsic::x86_avx_vtestz_ps_256:
11592 case Intrinsic::x86_avx_vtestz_pd_256:
11593 IsTestPacked = true; // Fallthrough
11594 case Intrinsic::x86_sse41_ptestz:
11595 case Intrinsic::x86_avx_ptestz_256:
11597 X86CC = X86::COND_E;
11599 case Intrinsic::x86_avx_vtestc_ps:
11600 case Intrinsic::x86_avx_vtestc_pd:
11601 case Intrinsic::x86_avx_vtestc_ps_256:
11602 case Intrinsic::x86_avx_vtestc_pd_256:
11603 IsTestPacked = true; // Fallthrough
11604 case Intrinsic::x86_sse41_ptestc:
11605 case Intrinsic::x86_avx_ptestc_256:
11607 X86CC = X86::COND_B;
11609 case Intrinsic::x86_avx_vtestnzc_ps:
11610 case Intrinsic::x86_avx_vtestnzc_pd:
11611 case Intrinsic::x86_avx_vtestnzc_ps_256:
11612 case Intrinsic::x86_avx_vtestnzc_pd_256:
11613 IsTestPacked = true; // Fallthrough
11614 case Intrinsic::x86_sse41_ptestnzc:
11615 case Intrinsic::x86_avx_ptestnzc_256:
11617 X86CC = X86::COND_A;
11621 SDValue LHS = Op.getOperand(1);
11622 SDValue RHS = Op.getOperand(2);
11623 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11624 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11625 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11626 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11627 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11629 case Intrinsic::x86_avx512_kortestz_w:
11630 case Intrinsic::x86_avx512_kortestc_w: {
11631 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11632 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11633 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11634 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11635 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11636 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
11637 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11640 // SSE/AVX shift intrinsics
11641 case Intrinsic::x86_sse2_psll_w:
11642 case Intrinsic::x86_sse2_psll_d:
11643 case Intrinsic::x86_sse2_psll_q:
11644 case Intrinsic::x86_avx2_psll_w:
11645 case Intrinsic::x86_avx2_psll_d:
11646 case Intrinsic::x86_avx2_psll_q:
11647 case Intrinsic::x86_sse2_psrl_w:
11648 case Intrinsic::x86_sse2_psrl_d:
11649 case Intrinsic::x86_sse2_psrl_q:
11650 case Intrinsic::x86_avx2_psrl_w:
11651 case Intrinsic::x86_avx2_psrl_d:
11652 case Intrinsic::x86_avx2_psrl_q:
11653 case Intrinsic::x86_sse2_psra_w:
11654 case Intrinsic::x86_sse2_psra_d:
11655 case Intrinsic::x86_avx2_psra_w:
11656 case Intrinsic::x86_avx2_psra_d: {
11659 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11660 case Intrinsic::x86_sse2_psll_w:
11661 case Intrinsic::x86_sse2_psll_d:
11662 case Intrinsic::x86_sse2_psll_q:
11663 case Intrinsic::x86_avx2_psll_w:
11664 case Intrinsic::x86_avx2_psll_d:
11665 case Intrinsic::x86_avx2_psll_q:
11666 Opcode = X86ISD::VSHL;
11668 case Intrinsic::x86_sse2_psrl_w:
11669 case Intrinsic::x86_sse2_psrl_d:
11670 case Intrinsic::x86_sse2_psrl_q:
11671 case Intrinsic::x86_avx2_psrl_w:
11672 case Intrinsic::x86_avx2_psrl_d:
11673 case Intrinsic::x86_avx2_psrl_q:
11674 Opcode = X86ISD::VSRL;
11676 case Intrinsic::x86_sse2_psra_w:
11677 case Intrinsic::x86_sse2_psra_d:
11678 case Intrinsic::x86_avx2_psra_w:
11679 case Intrinsic::x86_avx2_psra_d:
11680 Opcode = X86ISD::VSRA;
11683 return DAG.getNode(Opcode, dl, Op.getValueType(),
11684 Op.getOperand(1), Op.getOperand(2));
11687 // SSE/AVX immediate shift intrinsics
11688 case Intrinsic::x86_sse2_pslli_w:
11689 case Intrinsic::x86_sse2_pslli_d:
11690 case Intrinsic::x86_sse2_pslli_q:
11691 case Intrinsic::x86_avx2_pslli_w:
11692 case Intrinsic::x86_avx2_pslli_d:
11693 case Intrinsic::x86_avx2_pslli_q:
11694 case Intrinsic::x86_sse2_psrli_w:
11695 case Intrinsic::x86_sse2_psrli_d:
11696 case Intrinsic::x86_sse2_psrli_q:
11697 case Intrinsic::x86_avx2_psrli_w:
11698 case Intrinsic::x86_avx2_psrli_d:
11699 case Intrinsic::x86_avx2_psrli_q:
11700 case Intrinsic::x86_sse2_psrai_w:
11701 case Intrinsic::x86_sse2_psrai_d:
11702 case Intrinsic::x86_avx2_psrai_w:
11703 case Intrinsic::x86_avx2_psrai_d: {
11706 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11707 case Intrinsic::x86_sse2_pslli_w:
11708 case Intrinsic::x86_sse2_pslli_d:
11709 case Intrinsic::x86_sse2_pslli_q:
11710 case Intrinsic::x86_avx2_pslli_w:
11711 case Intrinsic::x86_avx2_pslli_d:
11712 case Intrinsic::x86_avx2_pslli_q:
11713 Opcode = X86ISD::VSHLI;
11715 case Intrinsic::x86_sse2_psrli_w:
11716 case Intrinsic::x86_sse2_psrli_d:
11717 case Intrinsic::x86_sse2_psrli_q:
11718 case Intrinsic::x86_avx2_psrli_w:
11719 case Intrinsic::x86_avx2_psrli_d:
11720 case Intrinsic::x86_avx2_psrli_q:
11721 Opcode = X86ISD::VSRLI;
11723 case Intrinsic::x86_sse2_psrai_w:
11724 case Intrinsic::x86_sse2_psrai_d:
11725 case Intrinsic::x86_avx2_psrai_w:
11726 case Intrinsic::x86_avx2_psrai_d:
11727 Opcode = X86ISD::VSRAI;
11730 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
11731 Op.getOperand(1), Op.getOperand(2), DAG);
11734 case Intrinsic::x86_sse42_pcmpistria128:
11735 case Intrinsic::x86_sse42_pcmpestria128:
11736 case Intrinsic::x86_sse42_pcmpistric128:
11737 case Intrinsic::x86_sse42_pcmpestric128:
11738 case Intrinsic::x86_sse42_pcmpistrio128:
11739 case Intrinsic::x86_sse42_pcmpestrio128:
11740 case Intrinsic::x86_sse42_pcmpistris128:
11741 case Intrinsic::x86_sse42_pcmpestris128:
11742 case Intrinsic::x86_sse42_pcmpistriz128:
11743 case Intrinsic::x86_sse42_pcmpestriz128: {
11747 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11748 case Intrinsic::x86_sse42_pcmpistria128:
11749 Opcode = X86ISD::PCMPISTRI;
11750 X86CC = X86::COND_A;
11752 case Intrinsic::x86_sse42_pcmpestria128:
11753 Opcode = X86ISD::PCMPESTRI;
11754 X86CC = X86::COND_A;
11756 case Intrinsic::x86_sse42_pcmpistric128:
11757 Opcode = X86ISD::PCMPISTRI;
11758 X86CC = X86::COND_B;
11760 case Intrinsic::x86_sse42_pcmpestric128:
11761 Opcode = X86ISD::PCMPESTRI;
11762 X86CC = X86::COND_B;
11764 case Intrinsic::x86_sse42_pcmpistrio128:
11765 Opcode = X86ISD::PCMPISTRI;
11766 X86CC = X86::COND_O;
11768 case Intrinsic::x86_sse42_pcmpestrio128:
11769 Opcode = X86ISD::PCMPESTRI;
11770 X86CC = X86::COND_O;
11772 case Intrinsic::x86_sse42_pcmpistris128:
11773 Opcode = X86ISD::PCMPISTRI;
11774 X86CC = X86::COND_S;
11776 case Intrinsic::x86_sse42_pcmpestris128:
11777 Opcode = X86ISD::PCMPESTRI;
11778 X86CC = X86::COND_S;
11780 case Intrinsic::x86_sse42_pcmpistriz128:
11781 Opcode = X86ISD::PCMPISTRI;
11782 X86CC = X86::COND_E;
11784 case Intrinsic::x86_sse42_pcmpestriz128:
11785 Opcode = X86ISD::PCMPESTRI;
11786 X86CC = X86::COND_E;
11789 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11790 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11791 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11792 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11793 DAG.getConstant(X86CC, MVT::i8),
11794 SDValue(PCMP.getNode(), 1));
11795 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11798 case Intrinsic::x86_sse42_pcmpistri128:
11799 case Intrinsic::x86_sse42_pcmpestri128: {
11801 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11802 Opcode = X86ISD::PCMPISTRI;
11804 Opcode = X86ISD::PCMPESTRI;
11806 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11807 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11808 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11810 case Intrinsic::x86_fma_vfmadd_ps:
11811 case Intrinsic::x86_fma_vfmadd_pd:
11812 case Intrinsic::x86_fma_vfmsub_ps:
11813 case Intrinsic::x86_fma_vfmsub_pd:
11814 case Intrinsic::x86_fma_vfnmadd_ps:
11815 case Intrinsic::x86_fma_vfnmadd_pd:
11816 case Intrinsic::x86_fma_vfnmsub_ps:
11817 case Intrinsic::x86_fma_vfnmsub_pd:
11818 case Intrinsic::x86_fma_vfmaddsub_ps:
11819 case Intrinsic::x86_fma_vfmaddsub_pd:
11820 case Intrinsic::x86_fma_vfmsubadd_ps:
11821 case Intrinsic::x86_fma_vfmsubadd_pd:
11822 case Intrinsic::x86_fma_vfmadd_ps_256:
11823 case Intrinsic::x86_fma_vfmadd_pd_256:
11824 case Intrinsic::x86_fma_vfmsub_ps_256:
11825 case Intrinsic::x86_fma_vfmsub_pd_256:
11826 case Intrinsic::x86_fma_vfnmadd_ps_256:
11827 case Intrinsic::x86_fma_vfnmadd_pd_256:
11828 case Intrinsic::x86_fma_vfnmsub_ps_256:
11829 case Intrinsic::x86_fma_vfnmsub_pd_256:
11830 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11831 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11832 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11833 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11834 case Intrinsic::x86_fma_vfmadd_ps_512:
11835 case Intrinsic::x86_fma_vfmadd_pd_512:
11836 case Intrinsic::x86_fma_vfmsub_ps_512:
11837 case Intrinsic::x86_fma_vfmsub_pd_512:
11838 case Intrinsic::x86_fma_vfnmadd_ps_512:
11839 case Intrinsic::x86_fma_vfnmadd_pd_512:
11840 case Intrinsic::x86_fma_vfnmsub_ps_512:
11841 case Intrinsic::x86_fma_vfnmsub_pd_512:
11842 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11843 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11844 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11845 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11848 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11849 case Intrinsic::x86_fma_vfmadd_ps:
11850 case Intrinsic::x86_fma_vfmadd_pd:
11851 case Intrinsic::x86_fma_vfmadd_ps_256:
11852 case Intrinsic::x86_fma_vfmadd_pd_256:
11853 case Intrinsic::x86_fma_vfmadd_ps_512:
11854 case Intrinsic::x86_fma_vfmadd_pd_512:
11855 Opc = X86ISD::FMADD;
11857 case Intrinsic::x86_fma_vfmsub_ps:
11858 case Intrinsic::x86_fma_vfmsub_pd:
11859 case Intrinsic::x86_fma_vfmsub_ps_256:
11860 case Intrinsic::x86_fma_vfmsub_pd_256:
11861 case Intrinsic::x86_fma_vfmsub_ps_512:
11862 case Intrinsic::x86_fma_vfmsub_pd_512:
11863 Opc = X86ISD::FMSUB;
11865 case Intrinsic::x86_fma_vfnmadd_ps:
11866 case Intrinsic::x86_fma_vfnmadd_pd:
11867 case Intrinsic::x86_fma_vfnmadd_ps_256:
11868 case Intrinsic::x86_fma_vfnmadd_pd_256:
11869 case Intrinsic::x86_fma_vfnmadd_ps_512:
11870 case Intrinsic::x86_fma_vfnmadd_pd_512:
11871 Opc = X86ISD::FNMADD;
11873 case Intrinsic::x86_fma_vfnmsub_ps:
11874 case Intrinsic::x86_fma_vfnmsub_pd:
11875 case Intrinsic::x86_fma_vfnmsub_ps_256:
11876 case Intrinsic::x86_fma_vfnmsub_pd_256:
11877 case Intrinsic::x86_fma_vfnmsub_ps_512:
11878 case Intrinsic::x86_fma_vfnmsub_pd_512:
11879 Opc = X86ISD::FNMSUB;
11881 case Intrinsic::x86_fma_vfmaddsub_ps:
11882 case Intrinsic::x86_fma_vfmaddsub_pd:
11883 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11884 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11885 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11886 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11887 Opc = X86ISD::FMADDSUB;
11889 case Intrinsic::x86_fma_vfmsubadd_ps:
11890 case Intrinsic::x86_fma_vfmsubadd_pd:
11891 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11892 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11893 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11894 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11895 Opc = X86ISD::FMSUBADD;
11899 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11900 Op.getOperand(2), Op.getOperand(3));
11905 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11906 SDValue Base, SDValue Index,
11907 SDValue ScaleOp, SDValue Chain,
11908 const X86Subtarget * Subtarget) {
11910 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11911 assert(C && "Invalid scale type");
11912 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11913 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11914 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11915 Index.getSimpleValueType().getVectorNumElements());
11916 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11917 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11918 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11919 SDValue Segment = DAG.getRegister(0, MVT::i32);
11920 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11921 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11922 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11923 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11926 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11927 SDValue Src, SDValue Mask, SDValue Base,
11928 SDValue Index, SDValue ScaleOp, SDValue Chain,
11929 const X86Subtarget * Subtarget) {
11931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11932 assert(C && "Invalid scale type");
11933 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11934 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11935 Index.getSimpleValueType().getVectorNumElements());
11936 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11937 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11938 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11939 SDValue Segment = DAG.getRegister(0, MVT::i32);
11940 if (Src.getOpcode() == ISD::UNDEF)
11941 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11942 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11943 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11944 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11945 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11948 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11949 SDValue Src, SDValue Base, SDValue Index,
11950 SDValue ScaleOp, SDValue Chain) {
11952 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11953 assert(C && "Invalid scale type");
11954 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11955 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11956 SDValue Segment = DAG.getRegister(0, MVT::i32);
11957 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11958 Index.getSimpleValueType().getVectorNumElements());
11959 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11960 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11961 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11962 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11963 return SDValue(Res, 1);
11966 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11967 SDValue Src, SDValue Mask, SDValue Base,
11968 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11970 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11971 assert(C && "Invalid scale type");
11972 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11973 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11974 SDValue Segment = DAG.getRegister(0, MVT::i32);
11975 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11976 Index.getSimpleValueType().getVectorNumElements());
11977 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11978 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11979 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11980 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11981 return SDValue(Res, 1);
11984 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11985 SelectionDAG &DAG) {
11987 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11989 default: return SDValue(); // Don't custom lower most intrinsics.
11991 // RDRAND/RDSEED intrinsics.
11992 case Intrinsic::x86_rdrand_16:
11993 case Intrinsic::x86_rdrand_32:
11994 case Intrinsic::x86_rdrand_64:
11995 case Intrinsic::x86_rdseed_16:
11996 case Intrinsic::x86_rdseed_32:
11997 case Intrinsic::x86_rdseed_64: {
11998 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11999 IntNo == Intrinsic::x86_rdseed_32 ||
12000 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
12002 // Emit the node with the right value type.
12003 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12004 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
12006 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12007 // Otherwise return the value from Rand, which is always 0, casted to i32.
12008 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12009 DAG.getConstant(1, Op->getValueType(1)),
12010 DAG.getConstant(X86::COND_B, MVT::i32),
12011 SDValue(Result.getNode(), 1) };
12012 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12013 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12014 Ops, array_lengthof(Ops));
12016 // Return { result, isValid, chain }.
12017 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12018 SDValue(Result.getNode(), 2));
12020 //int_gather(index, base, scale);
12021 case Intrinsic::x86_avx512_gather_qpd_512:
12022 case Intrinsic::x86_avx512_gather_qps_512:
12023 case Intrinsic::x86_avx512_gather_dpd_512:
12024 case Intrinsic::x86_avx512_gather_qpi_512:
12025 case Intrinsic::x86_avx512_gather_qpq_512:
12026 case Intrinsic::x86_avx512_gather_dpq_512:
12027 case Intrinsic::x86_avx512_gather_dps_512:
12028 case Intrinsic::x86_avx512_gather_dpi_512: {
12031 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12032 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
12033 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
12034 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
12035 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
12036 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
12037 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
12038 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
12039 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
12041 SDValue Chain = Op.getOperand(0);
12042 SDValue Index = Op.getOperand(2);
12043 SDValue Base = Op.getOperand(3);
12044 SDValue Scale = Op.getOperand(4);
12045 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
12047 //int_gather_mask(v1, mask, index, base, scale);
12048 case Intrinsic::x86_avx512_gather_qps_mask_512:
12049 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12050 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12051 case Intrinsic::x86_avx512_gather_dps_mask_512:
12052 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12053 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12054 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12055 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
12058 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12059 case Intrinsic::x86_avx512_gather_qps_mask_512:
12060 Opc = X86::VGATHERQPSZrm; break;
12061 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12062 Opc = X86::VGATHERQPDZrm; break;
12063 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12064 Opc = X86::VGATHERDPDZrm; break;
12065 case Intrinsic::x86_avx512_gather_dps_mask_512:
12066 Opc = X86::VGATHERDPSZrm; break;
12067 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12068 Opc = X86::VPGATHERQDZrm; break;
12069 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12070 Opc = X86::VPGATHERQQZrm; break;
12071 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12072 Opc = X86::VPGATHERDDZrm; break;
12073 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12074 Opc = X86::VPGATHERDQZrm; break;
12076 SDValue Chain = Op.getOperand(0);
12077 SDValue Src = Op.getOperand(2);
12078 SDValue Mask = Op.getOperand(3);
12079 SDValue Index = Op.getOperand(4);
12080 SDValue Base = Op.getOperand(5);
12081 SDValue Scale = Op.getOperand(6);
12082 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12085 //int_scatter(base, index, v1, scale);
12086 case Intrinsic::x86_avx512_scatter_qpd_512:
12087 case Intrinsic::x86_avx512_scatter_qps_512:
12088 case Intrinsic::x86_avx512_scatter_dpd_512:
12089 case Intrinsic::x86_avx512_scatter_qpi_512:
12090 case Intrinsic::x86_avx512_scatter_qpq_512:
12091 case Intrinsic::x86_avx512_scatter_dpq_512:
12092 case Intrinsic::x86_avx512_scatter_dps_512:
12093 case Intrinsic::x86_avx512_scatter_dpi_512: {
12096 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12097 case Intrinsic::x86_avx512_scatter_qpd_512:
12098 Opc = X86::VSCATTERQPDZmr; break;
12099 case Intrinsic::x86_avx512_scatter_qps_512:
12100 Opc = X86::VSCATTERQPSZmr; break;
12101 case Intrinsic::x86_avx512_scatter_dpd_512:
12102 Opc = X86::VSCATTERDPDZmr; break;
12103 case Intrinsic::x86_avx512_scatter_dps_512:
12104 Opc = X86::VSCATTERDPSZmr; break;
12105 case Intrinsic::x86_avx512_scatter_qpi_512:
12106 Opc = X86::VPSCATTERQDZmr; break;
12107 case Intrinsic::x86_avx512_scatter_qpq_512:
12108 Opc = X86::VPSCATTERQQZmr; break;
12109 case Intrinsic::x86_avx512_scatter_dpq_512:
12110 Opc = X86::VPSCATTERDQZmr; break;
12111 case Intrinsic::x86_avx512_scatter_dpi_512:
12112 Opc = X86::VPSCATTERDDZmr; break;
12114 SDValue Chain = Op.getOperand(0);
12115 SDValue Base = Op.getOperand(2);
12116 SDValue Index = Op.getOperand(3);
12117 SDValue Src = Op.getOperand(4);
12118 SDValue Scale = Op.getOperand(5);
12119 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12121 //int_scatter_mask(base, mask, index, v1, scale);
12122 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12123 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12124 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12125 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12126 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12127 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12128 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12129 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12132 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12133 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12134 Opc = X86::VSCATTERQPDZmr; break;
12135 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12136 Opc = X86::VSCATTERQPSZmr; break;
12137 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12138 Opc = X86::VSCATTERDPDZmr; break;
12139 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12140 Opc = X86::VSCATTERDPSZmr; break;
12141 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12142 Opc = X86::VPSCATTERQDZmr; break;
12143 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12144 Opc = X86::VPSCATTERQQZmr; break;
12145 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12146 Opc = X86::VPSCATTERDQZmr; break;
12147 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12148 Opc = X86::VPSCATTERDDZmr; break;
12150 SDValue Chain = Op.getOperand(0);
12151 SDValue Base = Op.getOperand(2);
12152 SDValue Mask = Op.getOperand(3);
12153 SDValue Index = Op.getOperand(4);
12154 SDValue Src = Op.getOperand(5);
12155 SDValue Scale = Op.getOperand(6);
12156 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12158 // XTEST intrinsics.
12159 case Intrinsic::x86_xtest: {
12160 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12161 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12162 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12163 DAG.getConstant(X86::COND_NE, MVT::i8),
12165 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12166 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12167 Ret, SDValue(InTrans.getNode(), 1));
12172 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12173 SelectionDAG &DAG) const {
12174 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12175 MFI->setReturnAddressIsTaken(true);
12177 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12180 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12182 EVT PtrVT = getPointerTy();
12185 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12186 const X86RegisterInfo *RegInfo =
12187 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12188 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12189 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12190 DAG.getNode(ISD::ADD, dl, PtrVT,
12191 FrameAddr, Offset),
12192 MachinePointerInfo(), false, false, false, 0);
12195 // Just load the return address.
12196 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12197 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12198 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12201 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12202 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12203 MFI->setFrameAddressIsTaken(true);
12205 EVT VT = Op.getValueType();
12206 SDLoc dl(Op); // FIXME probably not meaningful
12207 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12208 const X86RegisterInfo *RegInfo =
12209 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12210 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12211 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12212 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12213 "Invalid Frame Register!");
12214 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12216 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12217 MachinePointerInfo(),
12218 false, false, false, 0);
12222 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12223 SelectionDAG &DAG) const {
12224 const X86RegisterInfo *RegInfo =
12225 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12226 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12229 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12230 SDValue Chain = Op.getOperand(0);
12231 SDValue Offset = Op.getOperand(1);
12232 SDValue Handler = Op.getOperand(2);
12235 EVT PtrVT = getPointerTy();
12236 const X86RegisterInfo *RegInfo =
12237 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12238 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12239 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12240 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12241 "Invalid Frame Register!");
12242 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12243 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12245 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12246 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12247 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12248 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12250 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12252 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12253 DAG.getRegister(StoreAddrReg, PtrVT));
12256 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12257 SelectionDAG &DAG) const {
12259 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12260 DAG.getVTList(MVT::i32, MVT::Other),
12261 Op.getOperand(0), Op.getOperand(1));
12264 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12265 SelectionDAG &DAG) const {
12267 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12268 Op.getOperand(0), Op.getOperand(1));
12271 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12272 return Op.getOperand(0);
12275 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12276 SelectionDAG &DAG) const {
12277 SDValue Root = Op.getOperand(0);
12278 SDValue Trmp = Op.getOperand(1); // trampoline
12279 SDValue FPtr = Op.getOperand(2); // nested function
12280 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12283 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12284 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12286 if (Subtarget->is64Bit()) {
12287 SDValue OutChains[6];
12289 // Large code-model.
12290 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12291 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12293 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12294 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12296 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12298 // Load the pointer to the nested function into R11.
12299 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12300 SDValue Addr = Trmp;
12301 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12302 Addr, MachinePointerInfo(TrmpAddr),
12305 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12306 DAG.getConstant(2, MVT::i64));
12307 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12308 MachinePointerInfo(TrmpAddr, 2),
12311 // Load the 'nest' parameter value into R10.
12312 // R10 is specified in X86CallingConv.td
12313 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12314 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12315 DAG.getConstant(10, MVT::i64));
12316 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12317 Addr, MachinePointerInfo(TrmpAddr, 10),
12320 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12321 DAG.getConstant(12, MVT::i64));
12322 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12323 MachinePointerInfo(TrmpAddr, 12),
12326 // Jump to the nested function.
12327 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12328 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12329 DAG.getConstant(20, MVT::i64));
12330 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12331 Addr, MachinePointerInfo(TrmpAddr, 20),
12334 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12335 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12336 DAG.getConstant(22, MVT::i64));
12337 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12338 MachinePointerInfo(TrmpAddr, 22),
12341 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12343 const Function *Func =
12344 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12345 CallingConv::ID CC = Func->getCallingConv();
12350 llvm_unreachable("Unsupported calling convention");
12351 case CallingConv::C:
12352 case CallingConv::X86_StdCall: {
12353 // Pass 'nest' parameter in ECX.
12354 // Must be kept in sync with X86CallingConv.td
12355 NestReg = X86::ECX;
12357 // Check that ECX wasn't needed by an 'inreg' parameter.
12358 FunctionType *FTy = Func->getFunctionType();
12359 const AttributeSet &Attrs = Func->getAttributes();
12361 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12362 unsigned InRegCount = 0;
12365 for (FunctionType::param_iterator I = FTy->param_begin(),
12366 E = FTy->param_end(); I != E; ++I, ++Idx)
12367 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12368 // FIXME: should only count parameters that are lowered to integers.
12369 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12371 if (InRegCount > 2) {
12372 report_fatal_error("Nest register in use - reduce number of inreg"
12378 case CallingConv::X86_FastCall:
12379 case CallingConv::X86_ThisCall:
12380 case CallingConv::Fast:
12381 // Pass 'nest' parameter in EAX.
12382 // Must be kept in sync with X86CallingConv.td
12383 NestReg = X86::EAX;
12387 SDValue OutChains[4];
12388 SDValue Addr, Disp;
12390 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12391 DAG.getConstant(10, MVT::i32));
12392 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12394 // This is storing the opcode for MOV32ri.
12395 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12396 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12397 OutChains[0] = DAG.getStore(Root, dl,
12398 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12399 Trmp, MachinePointerInfo(TrmpAddr),
12402 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12403 DAG.getConstant(1, MVT::i32));
12404 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12405 MachinePointerInfo(TrmpAddr, 1),
12408 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12409 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12410 DAG.getConstant(5, MVT::i32));
12411 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12412 MachinePointerInfo(TrmpAddr, 5),
12415 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12416 DAG.getConstant(6, MVT::i32));
12417 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12418 MachinePointerInfo(TrmpAddr, 6),
12421 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12425 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12426 SelectionDAG &DAG) const {
12428 The rounding mode is in bits 11:10 of FPSR, and has the following
12430 00 Round to nearest
12435 FLT_ROUNDS, on the other hand, expects the following:
12442 To perform the conversion, we do:
12443 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12446 MachineFunction &MF = DAG.getMachineFunction();
12447 const TargetMachine &TM = MF.getTarget();
12448 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12449 unsigned StackAlignment = TFI.getStackAlignment();
12450 MVT VT = Op.getSimpleValueType();
12453 // Save FP Control Word to stack slot
12454 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12455 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12457 MachineMemOperand *MMO =
12458 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12459 MachineMemOperand::MOStore, 2, 2);
12461 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12462 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12463 DAG.getVTList(MVT::Other),
12464 Ops, array_lengthof(Ops), MVT::i16,
12467 // Load FP Control Word from stack slot
12468 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12469 MachinePointerInfo(), false, false, false, 0);
12471 // Transform as necessary
12473 DAG.getNode(ISD::SRL, DL, MVT::i16,
12474 DAG.getNode(ISD::AND, DL, MVT::i16,
12475 CWD, DAG.getConstant(0x800, MVT::i16)),
12476 DAG.getConstant(11, MVT::i8));
12478 DAG.getNode(ISD::SRL, DL, MVT::i16,
12479 DAG.getNode(ISD::AND, DL, MVT::i16,
12480 CWD, DAG.getConstant(0x400, MVT::i16)),
12481 DAG.getConstant(9, MVT::i8));
12484 DAG.getNode(ISD::AND, DL, MVT::i16,
12485 DAG.getNode(ISD::ADD, DL, MVT::i16,
12486 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12487 DAG.getConstant(1, MVT::i16)),
12488 DAG.getConstant(3, MVT::i16));
12490 return DAG.getNode((VT.getSizeInBits() < 16 ?
12491 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12494 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12495 MVT VT = Op.getSimpleValueType();
12497 unsigned NumBits = VT.getSizeInBits();
12500 Op = Op.getOperand(0);
12501 if (VT == MVT::i8) {
12502 // Zero extend to i32 since there is not an i8 bsr.
12504 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12507 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12508 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12509 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12511 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12514 DAG.getConstant(NumBits+NumBits-1, OpVT),
12515 DAG.getConstant(X86::COND_E, MVT::i8),
12518 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12520 // Finally xor with NumBits-1.
12521 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12524 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12528 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12529 MVT VT = Op.getSimpleValueType();
12531 unsigned NumBits = VT.getSizeInBits();
12534 Op = Op.getOperand(0);
12535 if (VT == MVT::i8) {
12536 // Zero extend to i32 since there is not an i8 bsr.
12538 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12541 // Issue a bsr (scan bits in reverse).
12542 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12543 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12545 // And xor with NumBits-1.
12546 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12549 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12553 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12554 MVT VT = Op.getSimpleValueType();
12555 unsigned NumBits = VT.getSizeInBits();
12557 Op = Op.getOperand(0);
12559 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12560 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12561 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12563 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12566 DAG.getConstant(NumBits, VT),
12567 DAG.getConstant(X86::COND_E, MVT::i8),
12570 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12573 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12574 // ones, and then concatenate the result back.
12575 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12576 MVT VT = Op.getSimpleValueType();
12578 assert(VT.is256BitVector() && VT.isInteger() &&
12579 "Unsupported value type for operation");
12581 unsigned NumElems = VT.getVectorNumElements();
12584 // Extract the LHS vectors
12585 SDValue LHS = Op.getOperand(0);
12586 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12587 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12589 // Extract the RHS vectors
12590 SDValue RHS = Op.getOperand(1);
12591 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12592 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12594 MVT EltVT = VT.getVectorElementType();
12595 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12597 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12598 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12599 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12602 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12603 assert(Op.getSimpleValueType().is256BitVector() &&
12604 Op.getSimpleValueType().isInteger() &&
12605 "Only handle AVX 256-bit vector integer operation");
12606 return Lower256IntArith(Op, DAG);
12609 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12610 assert(Op.getSimpleValueType().is256BitVector() &&
12611 Op.getSimpleValueType().isInteger() &&
12612 "Only handle AVX 256-bit vector integer operation");
12613 return Lower256IntArith(Op, DAG);
12616 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12617 SelectionDAG &DAG) {
12619 MVT VT = Op.getSimpleValueType();
12621 // Decompose 256-bit ops into smaller 128-bit ops.
12622 if (VT.is256BitVector() && !Subtarget->hasInt256())
12623 return Lower256IntArith(Op, DAG);
12625 SDValue A = Op.getOperand(0);
12626 SDValue B = Op.getOperand(1);
12628 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12629 if (VT == MVT::v4i32) {
12630 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12631 "Should not custom lower when pmuldq is available!");
12633 // Extract the odd parts.
12634 static const int UnpackMask[] = { 1, -1, 3, -1 };
12635 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12636 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12638 // Multiply the even parts.
12639 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12640 // Now multiply odd parts.
12641 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12643 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12644 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12646 // Merge the two vectors back together with a shuffle. This expands into 2
12648 static const int ShufMask[] = { 0, 4, 2, 6 };
12649 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12652 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12653 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12655 // Ahi = psrlqi(a, 32);
12656 // Bhi = psrlqi(b, 32);
12658 // AloBlo = pmuludq(a, b);
12659 // AloBhi = pmuludq(a, Bhi);
12660 // AhiBlo = pmuludq(Ahi, b);
12662 // AloBhi = psllqi(AloBhi, 32);
12663 // AhiBlo = psllqi(AhiBlo, 32);
12664 // return AloBlo + AloBhi + AhiBlo;
12666 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12667 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12669 // Bit cast to 32-bit vectors for MULUDQ
12670 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12671 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12672 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12673 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12674 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12675 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12677 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12678 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12679 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12681 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12682 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12684 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12685 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12688 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12689 MVT VT = Op.getSimpleValueType();
12690 MVT EltTy = VT.getVectorElementType();
12691 unsigned NumElts = VT.getVectorNumElements();
12692 SDValue N0 = Op.getOperand(0);
12695 // Lower sdiv X, pow2-const.
12696 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12700 APInt SplatValue, SplatUndef;
12701 unsigned SplatBitSize;
12703 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12705 EltTy.getSizeInBits() < SplatBitSize)
12708 if ((SplatValue != 0) &&
12709 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12710 unsigned Lg2 = SplatValue.countTrailingZeros();
12711 // Splat the sign bit.
12712 SmallVector<SDValue, 16> Sz(NumElts,
12713 DAG.getConstant(EltTy.getSizeInBits() - 1,
12715 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12716 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12718 // Add (N0 < 0) ? abs2 - 1 : 0;
12719 SmallVector<SDValue, 16> Amt(NumElts,
12720 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12722 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12723 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12725 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12726 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12727 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12728 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12731 // If we're dividing by a positive value, we're done. Otherwise, we must
12732 // negate the result.
12733 if (SplatValue.isNonNegative())
12736 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12737 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12738 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12743 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12744 const X86Subtarget *Subtarget) {
12745 MVT VT = Op.getSimpleValueType();
12747 SDValue R = Op.getOperand(0);
12748 SDValue Amt = Op.getOperand(1);
12750 // Optimize shl/srl/sra with constant shift amount.
12751 if (isSplatVector(Amt.getNode())) {
12752 SDValue SclrAmt = Amt->getOperand(0);
12753 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12754 uint64_t ShiftAmt = C->getZExtValue();
12756 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12757 (Subtarget->hasInt256() &&
12758 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12759 (Subtarget->hasAVX512() &&
12760 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12761 if (Op.getOpcode() == ISD::SHL)
12762 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12764 if (Op.getOpcode() == ISD::SRL)
12765 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12767 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12768 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12772 if (VT == MVT::v16i8) {
12773 if (Op.getOpcode() == ISD::SHL) {
12774 // Make a large shift.
12775 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12776 MVT::v8i16, R, ShiftAmt,
12778 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12779 // Zero out the rightmost bits.
12780 SmallVector<SDValue, 16> V(16,
12781 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12783 return DAG.getNode(ISD::AND, dl, VT, SHL,
12784 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12786 if (Op.getOpcode() == ISD::SRL) {
12787 // Make a large shift.
12788 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12789 MVT::v8i16, R, ShiftAmt,
12791 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12792 // Zero out the leftmost bits.
12793 SmallVector<SDValue, 16> V(16,
12794 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12796 return DAG.getNode(ISD::AND, dl, VT, SRL,
12797 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12799 if (Op.getOpcode() == ISD::SRA) {
12800 if (ShiftAmt == 7) {
12801 // R s>> 7 === R s< 0
12802 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12803 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12806 // R s>> a === ((R u>> a) ^ m) - m
12807 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12808 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12810 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12811 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12812 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12815 llvm_unreachable("Unknown shift opcode.");
12818 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12819 if (Op.getOpcode() == ISD::SHL) {
12820 // Make a large shift.
12821 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12822 MVT::v16i16, R, ShiftAmt,
12824 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12825 // Zero out the rightmost bits.
12826 SmallVector<SDValue, 32> V(32,
12827 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12829 return DAG.getNode(ISD::AND, dl, VT, SHL,
12830 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12832 if (Op.getOpcode() == ISD::SRL) {
12833 // Make a large shift.
12834 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12835 MVT::v16i16, R, ShiftAmt,
12837 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12838 // Zero out the leftmost bits.
12839 SmallVector<SDValue, 32> V(32,
12840 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12842 return DAG.getNode(ISD::AND, dl, VT, SRL,
12843 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12845 if (Op.getOpcode() == ISD::SRA) {
12846 if (ShiftAmt == 7) {
12847 // R s>> 7 === R s< 0
12848 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12849 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12852 // R s>> a === ((R u>> a) ^ m) - m
12853 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12854 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12856 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12857 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12858 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12861 llvm_unreachable("Unknown shift opcode.");
12866 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12867 if (!Subtarget->is64Bit() &&
12868 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12869 Amt.getOpcode() == ISD::BITCAST &&
12870 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12871 Amt = Amt.getOperand(0);
12872 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
12873 VT.getVectorNumElements();
12874 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12875 uint64_t ShiftAmt = 0;
12876 for (unsigned i = 0; i != Ratio; ++i) {
12877 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12881 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12883 // Check remaining shift amounts.
12884 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12885 uint64_t ShAmt = 0;
12886 for (unsigned j = 0; j != Ratio; ++j) {
12887 ConstantSDNode *C =
12888 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12892 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12894 if (ShAmt != ShiftAmt)
12897 switch (Op.getOpcode()) {
12899 llvm_unreachable("Unknown shift opcode!");
12901 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12904 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12907 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12915 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12916 const X86Subtarget* Subtarget) {
12917 MVT VT = Op.getSimpleValueType();
12919 SDValue R = Op.getOperand(0);
12920 SDValue Amt = Op.getOperand(1);
12922 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12923 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12924 (Subtarget->hasInt256() &&
12925 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12926 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12927 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12929 EVT EltVT = VT.getVectorElementType();
12931 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12932 unsigned NumElts = VT.getVectorNumElements();
12934 for (i = 0; i != NumElts; ++i) {
12935 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12939 for (j = i; j != NumElts; ++j) {
12940 SDValue Arg = Amt.getOperand(j);
12941 if (Arg.getOpcode() == ISD::UNDEF) continue;
12942 if (Arg != Amt.getOperand(i))
12945 if (i != NumElts && j == NumElts)
12946 BaseShAmt = Amt.getOperand(i);
12948 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12949 Amt = Amt.getOperand(0);
12950 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12951 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12952 SDValue InVec = Amt.getOperand(0);
12953 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12954 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12956 for (; i != NumElts; ++i) {
12957 SDValue Arg = InVec.getOperand(i);
12958 if (Arg.getOpcode() == ISD::UNDEF) continue;
12962 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12963 if (ConstantSDNode *C =
12964 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12965 unsigned SplatIdx =
12966 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12967 if (C->getZExtValue() == SplatIdx)
12968 BaseShAmt = InVec.getOperand(1);
12971 if (BaseShAmt.getNode() == 0)
12972 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12973 DAG.getIntPtrConstant(0));
12977 if (BaseShAmt.getNode()) {
12978 if (EltVT.bitsGT(MVT::i32))
12979 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12980 else if (EltVT.bitsLT(MVT::i32))
12981 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12983 switch (Op.getOpcode()) {
12985 llvm_unreachable("Unknown shift opcode!");
12987 switch (VT.SimpleTy) {
12988 default: return SDValue();
12997 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13000 switch (VT.SimpleTy) {
13001 default: return SDValue();
13008 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13011 switch (VT.SimpleTy) {
13012 default: return SDValue();
13021 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13027 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13028 if (!Subtarget->is64Bit() &&
13029 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13030 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13031 Amt.getOpcode() == ISD::BITCAST &&
13032 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13033 Amt = Amt.getOperand(0);
13034 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13035 VT.getVectorNumElements();
13036 std::vector<SDValue> Vals(Ratio);
13037 for (unsigned i = 0; i != Ratio; ++i)
13038 Vals[i] = Amt.getOperand(i);
13039 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13040 for (unsigned j = 0; j != Ratio; ++j)
13041 if (Vals[j] != Amt.getOperand(i + j))
13044 switch (Op.getOpcode()) {
13046 llvm_unreachable("Unknown shift opcode!");
13048 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13050 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13052 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13059 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13060 SelectionDAG &DAG) {
13062 MVT VT = Op.getSimpleValueType();
13064 SDValue R = Op.getOperand(0);
13065 SDValue Amt = Op.getOperand(1);
13068 if (!Subtarget->hasSSE2())
13071 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13075 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13079 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13081 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13082 if (Subtarget->hasInt256()) {
13083 if (Op.getOpcode() == ISD::SRL &&
13084 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13085 VT == MVT::v4i64 || VT == MVT::v8i32))
13087 if (Op.getOpcode() == ISD::SHL &&
13088 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13089 VT == MVT::v4i64 || VT == MVT::v8i32))
13091 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13095 // Lower SHL with variable shift amount.
13096 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13097 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13099 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13100 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13101 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13102 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13104 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13105 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13108 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13109 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13111 // Turn 'a' into a mask suitable for VSELECT
13112 SDValue VSelM = DAG.getConstant(0x80, VT);
13113 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13114 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13116 SDValue CM1 = DAG.getConstant(0x0f, VT);
13117 SDValue CM2 = DAG.getConstant(0x3f, VT);
13119 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13120 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13121 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13122 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13123 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13126 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13127 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13128 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13130 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13131 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13132 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13133 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13134 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13137 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13138 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13139 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13141 // return VSELECT(r, r+r, a);
13142 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13143 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13147 // Decompose 256-bit shifts into smaller 128-bit shifts.
13148 if (VT.is256BitVector()) {
13149 unsigned NumElems = VT.getVectorNumElements();
13150 MVT EltVT = VT.getVectorElementType();
13151 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13153 // Extract the two vectors
13154 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13155 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13157 // Recreate the shift amount vectors
13158 SDValue Amt1, Amt2;
13159 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13160 // Constant shift amount
13161 SmallVector<SDValue, 4> Amt1Csts;
13162 SmallVector<SDValue, 4> Amt2Csts;
13163 for (unsigned i = 0; i != NumElems/2; ++i)
13164 Amt1Csts.push_back(Amt->getOperand(i));
13165 for (unsigned i = NumElems/2; i != NumElems; ++i)
13166 Amt2Csts.push_back(Amt->getOperand(i));
13168 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13169 &Amt1Csts[0], NumElems/2);
13170 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13171 &Amt2Csts[0], NumElems/2);
13173 // Variable shift amount
13174 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13175 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13178 // Issue new vector shifts for the smaller types
13179 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13180 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13182 // Concatenate the result back
13183 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13189 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13190 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13191 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13192 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13193 // has only one use.
13194 SDNode *N = Op.getNode();
13195 SDValue LHS = N->getOperand(0);
13196 SDValue RHS = N->getOperand(1);
13197 unsigned BaseOp = 0;
13200 switch (Op.getOpcode()) {
13201 default: llvm_unreachable("Unknown ovf instruction!");
13203 // A subtract of one will be selected as a INC. Note that INC doesn't
13204 // set CF, so we can't do this for UADDO.
13205 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13207 BaseOp = X86ISD::INC;
13208 Cond = X86::COND_O;
13211 BaseOp = X86ISD::ADD;
13212 Cond = X86::COND_O;
13215 BaseOp = X86ISD::ADD;
13216 Cond = X86::COND_B;
13219 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13220 // set CF, so we can't do this for USUBO.
13221 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13223 BaseOp = X86ISD::DEC;
13224 Cond = X86::COND_O;
13227 BaseOp = X86ISD::SUB;
13228 Cond = X86::COND_O;
13231 BaseOp = X86ISD::SUB;
13232 Cond = X86::COND_B;
13235 BaseOp = X86ISD::SMUL;
13236 Cond = X86::COND_O;
13238 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13239 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13241 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13244 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13245 DAG.getConstant(X86::COND_O, MVT::i32),
13246 SDValue(Sum.getNode(), 2));
13248 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13252 // Also sets EFLAGS.
13253 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13254 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13257 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13258 DAG.getConstant(Cond, MVT::i32),
13259 SDValue(Sum.getNode(), 1));
13261 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13264 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13265 SelectionDAG &DAG) const {
13267 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13268 MVT VT = Op.getSimpleValueType();
13270 if (!Subtarget->hasSSE2() || !VT.isVector())
13273 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13274 ExtraVT.getScalarType().getSizeInBits();
13276 switch (VT.SimpleTy) {
13277 default: return SDValue();
13280 if (!Subtarget->hasFp256())
13282 if (!Subtarget->hasInt256()) {
13283 // needs to be split
13284 unsigned NumElems = VT.getVectorNumElements();
13286 // Extract the LHS vectors
13287 SDValue LHS = Op.getOperand(0);
13288 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13289 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13291 MVT EltVT = VT.getVectorElementType();
13292 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13294 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13295 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13296 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13298 SDValue Extra = DAG.getValueType(ExtraVT);
13300 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13301 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13303 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13308 SDValue Op0 = Op.getOperand(0);
13309 SDValue Op00 = Op0.getOperand(0);
13311 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13312 if (Op0.getOpcode() == ISD::BITCAST &&
13313 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13314 // (sext (vzext x)) -> (vsext x)
13315 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13316 if (Tmp1.getNode()) {
13317 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13318 // This folding is only valid when the in-reg type is a vector of i8,
13320 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13321 ExtraEltVT == MVT::i32) {
13322 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13323 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13324 "This optimization is invalid without a VZEXT.");
13325 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13331 // If the above didn't work, then just use Shift-Left + Shift-Right.
13332 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13334 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13340 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13341 SelectionDAG &DAG) {
13343 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13344 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13345 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13346 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13348 // The only fence that needs an instruction is a sequentially-consistent
13349 // cross-thread fence.
13350 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13351 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13352 // no-sse2). There isn't any reason to disable it if the target processor
13354 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13355 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13357 SDValue Chain = Op.getOperand(0);
13358 SDValue Zero = DAG.getConstant(0, MVT::i32);
13360 DAG.getRegister(X86::ESP, MVT::i32), // Base
13361 DAG.getTargetConstant(1, MVT::i8), // Scale
13362 DAG.getRegister(0, MVT::i32), // Index
13363 DAG.getTargetConstant(0, MVT::i32), // Disp
13364 DAG.getRegister(0, MVT::i32), // Segment.
13368 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13369 return SDValue(Res, 0);
13372 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13373 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13376 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13377 SelectionDAG &DAG) {
13378 MVT T = Op.getSimpleValueType();
13382 switch(T.SimpleTy) {
13383 default: llvm_unreachable("Invalid value type!");
13384 case MVT::i8: Reg = X86::AL; size = 1; break;
13385 case MVT::i16: Reg = X86::AX; size = 2; break;
13386 case MVT::i32: Reg = X86::EAX; size = 4; break;
13388 assert(Subtarget->is64Bit() && "Node not type legal!");
13389 Reg = X86::RAX; size = 8;
13392 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13393 Op.getOperand(2), SDValue());
13394 SDValue Ops[] = { cpIn.getValue(0),
13397 DAG.getTargetConstant(size, MVT::i8),
13398 cpIn.getValue(1) };
13399 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13400 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13401 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13402 Ops, array_lengthof(Ops), T, MMO);
13404 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13408 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13409 SelectionDAG &DAG) {
13410 assert(Subtarget->is64Bit() && "Result not type legalized?");
13411 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13412 SDValue TheChain = Op.getOperand(0);
13414 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13415 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13416 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13418 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13419 DAG.getConstant(32, MVT::i8));
13421 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13424 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13427 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13428 SelectionDAG &DAG) {
13429 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13430 MVT DstVT = Op.getSimpleValueType();
13431 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13432 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13433 assert((DstVT == MVT::i64 ||
13434 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13435 "Unexpected custom BITCAST");
13436 // i64 <=> MMX conversions are Legal.
13437 if (SrcVT==MVT::i64 && DstVT.isVector())
13439 if (DstVT==MVT::i64 && SrcVT.isVector())
13441 // MMX <=> MMX conversions are Legal.
13442 if (SrcVT.isVector() && DstVT.isVector())
13444 // All other conversions need to be expanded.
13448 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13449 SDNode *Node = Op.getNode();
13451 EVT T = Node->getValueType(0);
13452 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13453 DAG.getConstant(0, T), Node->getOperand(2));
13454 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13455 cast<AtomicSDNode>(Node)->getMemoryVT(),
13456 Node->getOperand(0),
13457 Node->getOperand(1), negOp,
13458 cast<AtomicSDNode>(Node)->getSrcValue(),
13459 cast<AtomicSDNode>(Node)->getAlignment(),
13460 cast<AtomicSDNode>(Node)->getOrdering(),
13461 cast<AtomicSDNode>(Node)->getSynchScope());
13464 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13465 SDNode *Node = Op.getNode();
13467 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13469 // Convert seq_cst store -> xchg
13470 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13471 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13472 // (The only way to get a 16-byte store is cmpxchg16b)
13473 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13474 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13475 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13476 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13477 cast<AtomicSDNode>(Node)->getMemoryVT(),
13478 Node->getOperand(0),
13479 Node->getOperand(1), Node->getOperand(2),
13480 cast<AtomicSDNode>(Node)->getMemOperand(),
13481 cast<AtomicSDNode>(Node)->getOrdering(),
13482 cast<AtomicSDNode>(Node)->getSynchScope());
13483 return Swap.getValue(1);
13485 // Other atomic stores have a simple pattern.
13489 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13490 EVT VT = Op.getNode()->getSimpleValueType(0);
13492 // Let legalize expand this if it isn't a legal type yet.
13493 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13496 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13499 bool ExtraOp = false;
13500 switch (Op.getOpcode()) {
13501 default: llvm_unreachable("Invalid code");
13502 case ISD::ADDC: Opc = X86ISD::ADD; break;
13503 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13504 case ISD::SUBC: Opc = X86ISD::SUB; break;
13505 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13509 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13511 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13512 Op.getOperand(1), Op.getOperand(2));
13515 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13516 SelectionDAG &DAG) {
13517 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13519 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13520 // which returns the values as { float, float } (in XMM0) or
13521 // { double, double } (which is returned in XMM0, XMM1).
13523 SDValue Arg = Op.getOperand(0);
13524 EVT ArgVT = Arg.getValueType();
13525 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13527 TargetLowering::ArgListTy Args;
13528 TargetLowering::ArgListEntry Entry;
13532 Entry.isSExt = false;
13533 Entry.isZExt = false;
13534 Args.push_back(Entry);
13536 bool isF64 = ArgVT == MVT::f64;
13537 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13538 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13539 // the results are returned via SRet in memory.
13540 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13541 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13542 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13544 Type *RetTy = isF64
13545 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13546 : (Type*)VectorType::get(ArgTy, 4);
13548 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13549 false, false, false, false, 0,
13550 CallingConv::C, /*isTaillCall=*/false,
13551 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13552 Callee, Args, DAG, dl);
13553 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13556 // Returned in xmm0 and xmm1.
13557 return CallResult.first;
13559 // Returned in bits 0:31 and 32:64 xmm0.
13560 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13561 CallResult.first, DAG.getIntPtrConstant(0));
13562 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13563 CallResult.first, DAG.getIntPtrConstant(1));
13564 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13565 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13568 /// LowerOperation - Provide custom lowering hooks for some operations.
13570 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13571 switch (Op.getOpcode()) {
13572 default: llvm_unreachable("Should not custom lower this!");
13573 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13574 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13575 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13576 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13577 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13578 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13579 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13580 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13581 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13582 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13583 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13584 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13585 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13586 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13587 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13588 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13589 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13590 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13591 case ISD::SHL_PARTS:
13592 case ISD::SRA_PARTS:
13593 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13594 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13595 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13596 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13597 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13598 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13599 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13600 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13601 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13602 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13603 case ISD::FABS: return LowerFABS(Op, DAG);
13604 case ISD::FNEG: return LowerFNEG(Op, DAG);
13605 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13606 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13607 case ISD::SETCC: return LowerSETCC(Op, DAG);
13608 case ISD::SELECT: return LowerSELECT(Op, DAG);
13609 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13610 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13611 case ISD::VASTART: return LowerVASTART(Op, DAG);
13612 case ISD::VAARG: return LowerVAARG(Op, DAG);
13613 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13614 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13615 case ISD::INTRINSIC_VOID:
13616 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13617 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13618 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13619 case ISD::FRAME_TO_ARGS_OFFSET:
13620 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13621 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13622 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13623 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13624 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13625 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13626 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13627 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13628 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13629 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13630 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13631 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13634 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13640 case ISD::UMULO: return LowerXALUO(Op, DAG);
13641 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13642 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13646 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13647 case ISD::ADD: return LowerADD(Op, DAG);
13648 case ISD::SUB: return LowerSUB(Op, DAG);
13649 case ISD::SDIV: return LowerSDIV(Op, DAG);
13650 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13654 static void ReplaceATOMIC_LOAD(SDNode *Node,
13655 SmallVectorImpl<SDValue> &Results,
13656 SelectionDAG &DAG) {
13658 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13660 // Convert wide load -> cmpxchg8b/cmpxchg16b
13661 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13662 // (The only way to get a 16-byte load is cmpxchg16b)
13663 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13664 SDValue Zero = DAG.getConstant(0, VT);
13665 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13666 Node->getOperand(0),
13667 Node->getOperand(1), Zero, Zero,
13668 cast<AtomicSDNode>(Node)->getMemOperand(),
13669 cast<AtomicSDNode>(Node)->getOrdering(),
13670 cast<AtomicSDNode>(Node)->getSynchScope());
13671 Results.push_back(Swap.getValue(0));
13672 Results.push_back(Swap.getValue(1));
13676 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13677 SelectionDAG &DAG, unsigned NewOp) {
13679 assert (Node->getValueType(0) == MVT::i64 &&
13680 "Only know how to expand i64 atomics");
13682 SDValue Chain = Node->getOperand(0);
13683 SDValue In1 = Node->getOperand(1);
13684 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13685 Node->getOperand(2), DAG.getIntPtrConstant(0));
13686 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13687 Node->getOperand(2), DAG.getIntPtrConstant(1));
13688 SDValue Ops[] = { Chain, In1, In2L, In2H };
13689 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13691 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13692 cast<MemSDNode>(Node)->getMemOperand());
13693 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13694 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13695 Results.push_back(Result.getValue(2));
13698 /// ReplaceNodeResults - Replace a node with an illegal result type
13699 /// with a new node built out of custom code.
13700 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13701 SmallVectorImpl<SDValue>&Results,
13702 SelectionDAG &DAG) const {
13704 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13705 switch (N->getOpcode()) {
13707 llvm_unreachable("Do not know how to custom type legalize this operation!");
13708 case ISD::SIGN_EXTEND_INREG:
13713 // We don't want to expand or promote these.
13715 case ISD::FP_TO_SINT:
13716 case ISD::FP_TO_UINT: {
13717 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13719 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13722 std::pair<SDValue,SDValue> Vals =
13723 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13724 SDValue FIST = Vals.first, StackSlot = Vals.second;
13725 if (FIST.getNode() != 0) {
13726 EVT VT = N->getValueType(0);
13727 // Return a load from the stack slot.
13728 if (StackSlot.getNode() != 0)
13729 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13730 MachinePointerInfo(),
13731 false, false, false, 0));
13733 Results.push_back(FIST);
13737 case ISD::UINT_TO_FP: {
13738 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13739 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13740 N->getValueType(0) != MVT::v2f32)
13742 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13744 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13746 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13747 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13748 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13749 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13750 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13751 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13754 case ISD::FP_ROUND: {
13755 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13757 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13758 Results.push_back(V);
13761 case ISD::READCYCLECOUNTER: {
13762 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13763 SDValue TheChain = N->getOperand(0);
13764 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13765 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13767 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13769 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13770 SDValue Ops[] = { eax, edx };
13771 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13772 array_lengthof(Ops)));
13773 Results.push_back(edx.getValue(1));
13776 case ISD::ATOMIC_CMP_SWAP: {
13777 EVT T = N->getValueType(0);
13778 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13779 bool Regs64bit = T == MVT::i128;
13780 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13781 SDValue cpInL, cpInH;
13782 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13783 DAG.getConstant(0, HalfT));
13784 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13785 DAG.getConstant(1, HalfT));
13786 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13787 Regs64bit ? X86::RAX : X86::EAX,
13789 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13790 Regs64bit ? X86::RDX : X86::EDX,
13791 cpInH, cpInL.getValue(1));
13792 SDValue swapInL, swapInH;
13793 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13794 DAG.getConstant(0, HalfT));
13795 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13796 DAG.getConstant(1, HalfT));
13797 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13798 Regs64bit ? X86::RBX : X86::EBX,
13799 swapInL, cpInH.getValue(1));
13800 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13801 Regs64bit ? X86::RCX : X86::ECX,
13802 swapInH, swapInL.getValue(1));
13803 SDValue Ops[] = { swapInH.getValue(0),
13805 swapInH.getValue(1) };
13806 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13807 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13808 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13809 X86ISD::LCMPXCHG8_DAG;
13810 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13811 Ops, array_lengthof(Ops), T, MMO);
13812 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13813 Regs64bit ? X86::RAX : X86::EAX,
13814 HalfT, Result.getValue(1));
13815 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13816 Regs64bit ? X86::RDX : X86::EDX,
13817 HalfT, cpOutL.getValue(2));
13818 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13819 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13820 Results.push_back(cpOutH.getValue(1));
13823 case ISD::ATOMIC_LOAD_ADD:
13824 case ISD::ATOMIC_LOAD_AND:
13825 case ISD::ATOMIC_LOAD_NAND:
13826 case ISD::ATOMIC_LOAD_OR:
13827 case ISD::ATOMIC_LOAD_SUB:
13828 case ISD::ATOMIC_LOAD_XOR:
13829 case ISD::ATOMIC_LOAD_MAX:
13830 case ISD::ATOMIC_LOAD_MIN:
13831 case ISD::ATOMIC_LOAD_UMAX:
13832 case ISD::ATOMIC_LOAD_UMIN:
13833 case ISD::ATOMIC_SWAP: {
13835 switch (N->getOpcode()) {
13836 default: llvm_unreachable("Unexpected opcode");
13837 case ISD::ATOMIC_LOAD_ADD:
13838 Opc = X86ISD::ATOMADD64_DAG;
13840 case ISD::ATOMIC_LOAD_AND:
13841 Opc = X86ISD::ATOMAND64_DAG;
13843 case ISD::ATOMIC_LOAD_NAND:
13844 Opc = X86ISD::ATOMNAND64_DAG;
13846 case ISD::ATOMIC_LOAD_OR:
13847 Opc = X86ISD::ATOMOR64_DAG;
13849 case ISD::ATOMIC_LOAD_SUB:
13850 Opc = X86ISD::ATOMSUB64_DAG;
13852 case ISD::ATOMIC_LOAD_XOR:
13853 Opc = X86ISD::ATOMXOR64_DAG;
13855 case ISD::ATOMIC_LOAD_MAX:
13856 Opc = X86ISD::ATOMMAX64_DAG;
13858 case ISD::ATOMIC_LOAD_MIN:
13859 Opc = X86ISD::ATOMMIN64_DAG;
13861 case ISD::ATOMIC_LOAD_UMAX:
13862 Opc = X86ISD::ATOMUMAX64_DAG;
13864 case ISD::ATOMIC_LOAD_UMIN:
13865 Opc = X86ISD::ATOMUMIN64_DAG;
13867 case ISD::ATOMIC_SWAP:
13868 Opc = X86ISD::ATOMSWAP64_DAG;
13871 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13874 case ISD::ATOMIC_LOAD:
13875 ReplaceATOMIC_LOAD(N, Results, DAG);
13879 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13881 default: return NULL;
13882 case X86ISD::BSF: return "X86ISD::BSF";
13883 case X86ISD::BSR: return "X86ISD::BSR";
13884 case X86ISD::SHLD: return "X86ISD::SHLD";
13885 case X86ISD::SHRD: return "X86ISD::SHRD";
13886 case X86ISD::FAND: return "X86ISD::FAND";
13887 case X86ISD::FANDN: return "X86ISD::FANDN";
13888 case X86ISD::FOR: return "X86ISD::FOR";
13889 case X86ISD::FXOR: return "X86ISD::FXOR";
13890 case X86ISD::FSRL: return "X86ISD::FSRL";
13891 case X86ISD::FILD: return "X86ISD::FILD";
13892 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13893 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13894 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13895 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13896 case X86ISD::FLD: return "X86ISD::FLD";
13897 case X86ISD::FST: return "X86ISD::FST";
13898 case X86ISD::CALL: return "X86ISD::CALL";
13899 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13900 case X86ISD::BT: return "X86ISD::BT";
13901 case X86ISD::CMP: return "X86ISD::CMP";
13902 case X86ISD::COMI: return "X86ISD::COMI";
13903 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13904 case X86ISD::CMPM: return "X86ISD::CMPM";
13905 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13906 case X86ISD::SETCC: return "X86ISD::SETCC";
13907 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13908 case X86ISD::FSETCC: return "X86ISD::FSETCC";
13909 case X86ISD::CMOV: return "X86ISD::CMOV";
13910 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13911 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13912 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13913 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13914 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13915 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13916 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13917 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13918 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13919 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13920 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13921 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13922 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13923 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13924 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13925 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13926 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13927 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13928 case X86ISD::HADD: return "X86ISD::HADD";
13929 case X86ISD::HSUB: return "X86ISD::HSUB";
13930 case X86ISD::FHADD: return "X86ISD::FHADD";
13931 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13932 case X86ISD::UMAX: return "X86ISD::UMAX";
13933 case X86ISD::UMIN: return "X86ISD::UMIN";
13934 case X86ISD::SMAX: return "X86ISD::SMAX";
13935 case X86ISD::SMIN: return "X86ISD::SMIN";
13936 case X86ISD::FMAX: return "X86ISD::FMAX";
13937 case X86ISD::FMIN: return "X86ISD::FMIN";
13938 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13939 case X86ISD::FMINC: return "X86ISD::FMINC";
13940 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13941 case X86ISD::FRCP: return "X86ISD::FRCP";
13942 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13943 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13944 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13945 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13946 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13947 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13948 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13949 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13950 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13951 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13952 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13953 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13954 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13955 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13956 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13957 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13958 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13959 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13960 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13961 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13962 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13963 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13964 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13965 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13966 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13967 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13968 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13969 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13970 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13971 case X86ISD::VSHL: return "X86ISD::VSHL";
13972 case X86ISD::VSRL: return "X86ISD::VSRL";
13973 case X86ISD::VSRA: return "X86ISD::VSRA";
13974 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13975 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13976 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13977 case X86ISD::CMPP: return "X86ISD::CMPP";
13978 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13979 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13980 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13981 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13982 case X86ISD::ADD: return "X86ISD::ADD";
13983 case X86ISD::SUB: return "X86ISD::SUB";
13984 case X86ISD::ADC: return "X86ISD::ADC";
13985 case X86ISD::SBB: return "X86ISD::SBB";
13986 case X86ISD::SMUL: return "X86ISD::SMUL";
13987 case X86ISD::UMUL: return "X86ISD::UMUL";
13988 case X86ISD::INC: return "X86ISD::INC";
13989 case X86ISD::DEC: return "X86ISD::DEC";
13990 case X86ISD::OR: return "X86ISD::OR";
13991 case X86ISD::XOR: return "X86ISD::XOR";
13992 case X86ISD::AND: return "X86ISD::AND";
13993 case X86ISD::BLSI: return "X86ISD::BLSI";
13994 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13995 case X86ISD::BLSR: return "X86ISD::BLSR";
13996 case X86ISD::BZHI: return "X86ISD::BZHI";
13997 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13998 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13999 case X86ISD::PTEST: return "X86ISD::PTEST";
14000 case X86ISD::TESTP: return "X86ISD::TESTP";
14001 case X86ISD::TESTM: return "X86ISD::TESTM";
14002 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14003 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14004 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14005 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14006 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14007 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14008 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14009 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14010 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14011 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14012 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14013 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14014 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14015 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14016 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14017 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14018 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14019 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14020 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14021 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14022 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14023 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14024 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14025 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14026 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14027 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14028 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14029 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14030 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14031 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14032 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14033 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14034 case X86ISD::SAHF: return "X86ISD::SAHF";
14035 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14036 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14037 case X86ISD::FMADD: return "X86ISD::FMADD";
14038 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14039 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14040 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14041 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14042 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14043 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14044 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14045 case X86ISD::XTEST: return "X86ISD::XTEST";
14049 // isLegalAddressingMode - Return true if the addressing mode represented
14050 // by AM is legal for this target, for a load/store of the specified type.
14051 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14053 // X86 supports extremely general addressing modes.
14054 CodeModel::Model M = getTargetMachine().getCodeModel();
14055 Reloc::Model R = getTargetMachine().getRelocationModel();
14057 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14058 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
14063 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14065 // If a reference to this global requires an extra load, we can't fold it.
14066 if (isGlobalStubReference(GVFlags))
14069 // If BaseGV requires a register for the PIC base, we cannot also have a
14070 // BaseReg specified.
14071 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14074 // If lower 4G is not available, then we must use rip-relative addressing.
14075 if ((M != CodeModel::Small || R != Reloc::Static) &&
14076 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14080 switch (AM.Scale) {
14086 // These scales always work.
14091 // These scales are formed with basereg+scalereg. Only accept if there is
14096 default: // Other stuff never works.
14103 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14104 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14106 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14107 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14108 return NumBits1 > NumBits2;
14111 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14112 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14115 if (!isTypeLegal(EVT::getEVT(Ty1)))
14118 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14120 // Assuming the caller doesn't have a zeroext or signext return parameter,
14121 // truncation all the way down to i1 is valid.
14125 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14126 return isInt<32>(Imm);
14129 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14130 // Can also use sub to handle negated immediates.
14131 return isInt<32>(Imm);
14134 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14135 if (!VT1.isInteger() || !VT2.isInteger())
14137 unsigned NumBits1 = VT1.getSizeInBits();
14138 unsigned NumBits2 = VT2.getSizeInBits();
14139 return NumBits1 > NumBits2;
14142 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14143 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14144 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14147 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14148 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14149 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14152 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14153 EVT VT1 = Val.getValueType();
14154 if (isZExtFree(VT1, VT2))
14157 if (Val.getOpcode() != ISD::LOAD)
14160 if (!VT1.isSimple() || !VT1.isInteger() ||
14161 !VT2.isSimple() || !VT2.isInteger())
14164 switch (VT1.getSimpleVT().SimpleTy) {
14169 // X86 has 8, 16, and 32-bit zero-extending loads.
14177 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14178 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14181 VT = VT.getScalarType();
14183 if (!VT.isSimple())
14186 switch (VT.getSimpleVT().SimpleTy) {
14197 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14198 // i16 instructions are longer (0x66 prefix) and potentially slower.
14199 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14202 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14203 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14204 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14205 /// are assumed to be legal.
14207 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14209 if (!VT.isSimple())
14212 MVT SVT = VT.getSimpleVT();
14214 // Very little shuffling can be done for 64-bit vectors right now.
14215 if (VT.getSizeInBits() == 64)
14218 // FIXME: pshufb, blends, shifts.
14219 return (SVT.getVectorNumElements() == 2 ||
14220 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14221 isMOVLMask(M, SVT) ||
14222 isSHUFPMask(M, SVT) ||
14223 isPSHUFDMask(M, SVT) ||
14224 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14225 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14226 isPALIGNRMask(M, SVT, Subtarget) ||
14227 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14228 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14229 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14230 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14234 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14236 if (!VT.isSimple())
14239 MVT SVT = VT.getSimpleVT();
14240 unsigned NumElts = SVT.getVectorNumElements();
14241 // FIXME: This collection of masks seems suspect.
14244 if (NumElts == 4 && SVT.is128BitVector()) {
14245 return (isMOVLMask(Mask, SVT) ||
14246 isCommutedMOVLMask(Mask, SVT, true) ||
14247 isSHUFPMask(Mask, SVT) ||
14248 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14253 //===----------------------------------------------------------------------===//
14254 // X86 Scheduler Hooks
14255 //===----------------------------------------------------------------------===//
14257 /// Utility function to emit xbegin specifying the start of an RTM region.
14258 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14259 const TargetInstrInfo *TII) {
14260 DebugLoc DL = MI->getDebugLoc();
14262 const BasicBlock *BB = MBB->getBasicBlock();
14263 MachineFunction::iterator I = MBB;
14266 // For the v = xbegin(), we generate
14277 MachineBasicBlock *thisMBB = MBB;
14278 MachineFunction *MF = MBB->getParent();
14279 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14280 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14281 MF->insert(I, mainMBB);
14282 MF->insert(I, sinkMBB);
14284 // Transfer the remainder of BB and its successor edges to sinkMBB.
14285 sinkMBB->splice(sinkMBB->begin(), MBB,
14286 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14287 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14291 // # fallthrough to mainMBB
14292 // # abortion to sinkMBB
14293 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14294 thisMBB->addSuccessor(mainMBB);
14295 thisMBB->addSuccessor(sinkMBB);
14299 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14300 mainMBB->addSuccessor(sinkMBB);
14303 // EAX is live into the sinkMBB
14304 sinkMBB->addLiveIn(X86::EAX);
14305 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14306 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14309 MI->eraseFromParent();
14313 // Get CMPXCHG opcode for the specified data type.
14314 static unsigned getCmpXChgOpcode(EVT VT) {
14315 switch (VT.getSimpleVT().SimpleTy) {
14316 case MVT::i8: return X86::LCMPXCHG8;
14317 case MVT::i16: return X86::LCMPXCHG16;
14318 case MVT::i32: return X86::LCMPXCHG32;
14319 case MVT::i64: return X86::LCMPXCHG64;
14323 llvm_unreachable("Invalid operand size!");
14326 // Get LOAD opcode for the specified data type.
14327 static unsigned getLoadOpcode(EVT VT) {
14328 switch (VT.getSimpleVT().SimpleTy) {
14329 case MVT::i8: return X86::MOV8rm;
14330 case MVT::i16: return X86::MOV16rm;
14331 case MVT::i32: return X86::MOV32rm;
14332 case MVT::i64: return X86::MOV64rm;
14336 llvm_unreachable("Invalid operand size!");
14339 // Get opcode of the non-atomic one from the specified atomic instruction.
14340 static unsigned getNonAtomicOpcode(unsigned Opc) {
14342 case X86::ATOMAND8: return X86::AND8rr;
14343 case X86::ATOMAND16: return X86::AND16rr;
14344 case X86::ATOMAND32: return X86::AND32rr;
14345 case X86::ATOMAND64: return X86::AND64rr;
14346 case X86::ATOMOR8: return X86::OR8rr;
14347 case X86::ATOMOR16: return X86::OR16rr;
14348 case X86::ATOMOR32: return X86::OR32rr;
14349 case X86::ATOMOR64: return X86::OR64rr;
14350 case X86::ATOMXOR8: return X86::XOR8rr;
14351 case X86::ATOMXOR16: return X86::XOR16rr;
14352 case X86::ATOMXOR32: return X86::XOR32rr;
14353 case X86::ATOMXOR64: return X86::XOR64rr;
14355 llvm_unreachable("Unhandled atomic-load-op opcode!");
14358 // Get opcode of the non-atomic one from the specified atomic instruction with
14360 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14361 unsigned &ExtraOpc) {
14363 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14364 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14365 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14366 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14367 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14368 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14369 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14370 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14371 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14372 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14373 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14374 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14375 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14376 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14377 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14378 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14379 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14380 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14381 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14382 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14384 llvm_unreachable("Unhandled atomic-load-op opcode!");
14387 // Get opcode of the non-atomic one from the specified atomic instruction for
14388 // 64-bit data type on 32-bit target.
14389 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14391 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14392 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14393 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14394 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14395 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14396 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14397 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14398 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14399 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14400 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14402 llvm_unreachable("Unhandled atomic-load-op opcode!");
14405 // Get opcode of the non-atomic one from the specified atomic instruction for
14406 // 64-bit data type on 32-bit target with extra opcode.
14407 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14409 unsigned &ExtraOpc) {
14411 case X86::ATOMNAND6432:
14412 ExtraOpc = X86::NOT32r;
14413 HiOpc = X86::AND32rr;
14414 return X86::AND32rr;
14416 llvm_unreachable("Unhandled atomic-load-op opcode!");
14419 // Get pseudo CMOV opcode from the specified data type.
14420 static unsigned getPseudoCMOVOpc(EVT VT) {
14421 switch (VT.getSimpleVT().SimpleTy) {
14422 case MVT::i8: return X86::CMOV_GR8;
14423 case MVT::i16: return X86::CMOV_GR16;
14424 case MVT::i32: return X86::CMOV_GR32;
14428 llvm_unreachable("Unknown CMOV opcode!");
14431 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14432 // They will be translated into a spin-loop or compare-exchange loop from
14435 // dst = atomic-fetch-op MI.addr, MI.val
14441 // t1 = LOAD MI.addr
14443 // t4 = phi(t1, t3 / loop)
14444 // t2 = OP MI.val, t4
14446 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14452 MachineBasicBlock *
14453 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14454 MachineBasicBlock *MBB) const {
14455 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14456 DebugLoc DL = MI->getDebugLoc();
14458 MachineFunction *MF = MBB->getParent();
14459 MachineRegisterInfo &MRI = MF->getRegInfo();
14461 const BasicBlock *BB = MBB->getBasicBlock();
14462 MachineFunction::iterator I = MBB;
14465 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14466 "Unexpected number of operands");
14468 assert(MI->hasOneMemOperand() &&
14469 "Expected atomic-load-op to have one memoperand");
14471 // Memory Reference
14472 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14473 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14475 unsigned DstReg, SrcReg;
14476 unsigned MemOpndSlot;
14478 unsigned CurOp = 0;
14480 DstReg = MI->getOperand(CurOp++).getReg();
14481 MemOpndSlot = CurOp;
14482 CurOp += X86::AddrNumOperands;
14483 SrcReg = MI->getOperand(CurOp++).getReg();
14485 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14486 MVT::SimpleValueType VT = *RC->vt_begin();
14487 unsigned t1 = MRI.createVirtualRegister(RC);
14488 unsigned t2 = MRI.createVirtualRegister(RC);
14489 unsigned t3 = MRI.createVirtualRegister(RC);
14490 unsigned t4 = MRI.createVirtualRegister(RC);
14491 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14493 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14494 unsigned LOADOpc = getLoadOpcode(VT);
14496 // For the atomic load-arith operator, we generate
14499 // t1 = LOAD [MI.addr]
14501 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14502 // t1 = OP MI.val, EAX
14504 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14510 MachineBasicBlock *thisMBB = MBB;
14511 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14512 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14513 MF->insert(I, mainMBB);
14514 MF->insert(I, sinkMBB);
14516 MachineInstrBuilder MIB;
14518 // Transfer the remainder of BB and its successor edges to sinkMBB.
14519 sinkMBB->splice(sinkMBB->begin(), MBB,
14520 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14521 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14524 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14525 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14526 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14528 NewMO.setIsKill(false);
14529 MIB.addOperand(NewMO);
14531 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14532 unsigned flags = (*MMOI)->getFlags();
14533 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14534 MachineMemOperand *MMO =
14535 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14536 (*MMOI)->getSize(),
14537 (*MMOI)->getBaseAlignment(),
14538 (*MMOI)->getTBAAInfo(),
14539 (*MMOI)->getRanges());
14540 MIB.addMemOperand(MMO);
14543 thisMBB->addSuccessor(mainMBB);
14546 MachineBasicBlock *origMainMBB = mainMBB;
14549 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14550 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14552 unsigned Opc = MI->getOpcode();
14555 llvm_unreachable("Unhandled atomic-load-op opcode!");
14556 case X86::ATOMAND8:
14557 case X86::ATOMAND16:
14558 case X86::ATOMAND32:
14559 case X86::ATOMAND64:
14561 case X86::ATOMOR16:
14562 case X86::ATOMOR32:
14563 case X86::ATOMOR64:
14564 case X86::ATOMXOR8:
14565 case X86::ATOMXOR16:
14566 case X86::ATOMXOR32:
14567 case X86::ATOMXOR64: {
14568 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14569 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14573 case X86::ATOMNAND8:
14574 case X86::ATOMNAND16:
14575 case X86::ATOMNAND32:
14576 case X86::ATOMNAND64: {
14577 unsigned Tmp = MRI.createVirtualRegister(RC);
14579 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14580 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14582 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14585 case X86::ATOMMAX8:
14586 case X86::ATOMMAX16:
14587 case X86::ATOMMAX32:
14588 case X86::ATOMMAX64:
14589 case X86::ATOMMIN8:
14590 case X86::ATOMMIN16:
14591 case X86::ATOMMIN32:
14592 case X86::ATOMMIN64:
14593 case X86::ATOMUMAX8:
14594 case X86::ATOMUMAX16:
14595 case X86::ATOMUMAX32:
14596 case X86::ATOMUMAX64:
14597 case X86::ATOMUMIN8:
14598 case X86::ATOMUMIN16:
14599 case X86::ATOMUMIN32:
14600 case X86::ATOMUMIN64: {
14602 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14604 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14608 if (Subtarget->hasCMov()) {
14609 if (VT != MVT::i8) {
14611 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14615 // Promote i8 to i32 to use CMOV32
14616 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14617 const TargetRegisterClass *RC32 =
14618 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14619 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14620 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14621 unsigned Tmp = MRI.createVirtualRegister(RC32);
14623 unsigned Undef = MRI.createVirtualRegister(RC32);
14624 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14626 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14629 .addImm(X86::sub_8bit);
14630 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14633 .addImm(X86::sub_8bit);
14635 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14639 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14640 .addReg(Tmp, 0, X86::sub_8bit);
14643 // Use pseudo select and lower them.
14644 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14645 "Invalid atomic-load-op transformation!");
14646 unsigned SelOpc = getPseudoCMOVOpc(VT);
14647 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14648 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14649 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14650 .addReg(SrcReg).addReg(t4)
14652 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14653 // Replace the original PHI node as mainMBB is changed after CMOV
14655 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14656 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14657 Phi->eraseFromParent();
14663 // Copy PhyReg back from virtual register.
14664 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14667 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14668 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14669 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14671 NewMO.setIsKill(false);
14672 MIB.addOperand(NewMO);
14675 MIB.setMemRefs(MMOBegin, MMOEnd);
14677 // Copy PhyReg back to virtual register.
14678 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14681 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14683 mainMBB->addSuccessor(origMainMBB);
14684 mainMBB->addSuccessor(sinkMBB);
14687 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14688 TII->get(TargetOpcode::COPY), DstReg)
14691 MI->eraseFromParent();
14695 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14696 // instructions. They will be translated into a spin-loop or compare-exchange
14700 // dst = atomic-fetch-op MI.addr, MI.val
14706 // t1L = LOAD [MI.addr + 0]
14707 // t1H = LOAD [MI.addr + 4]
14709 // t4L = phi(t1L, t3L / loop)
14710 // t4H = phi(t1H, t3H / loop)
14711 // t2L = OP MI.val.lo, t4L
14712 // t2H = OP MI.val.hi, t4H
14717 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14725 MachineBasicBlock *
14726 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14727 MachineBasicBlock *MBB) const {
14728 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14729 DebugLoc DL = MI->getDebugLoc();
14731 MachineFunction *MF = MBB->getParent();
14732 MachineRegisterInfo &MRI = MF->getRegInfo();
14734 const BasicBlock *BB = MBB->getBasicBlock();
14735 MachineFunction::iterator I = MBB;
14738 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14739 "Unexpected number of operands");
14741 assert(MI->hasOneMemOperand() &&
14742 "Expected atomic-load-op32 to have one memoperand");
14744 // Memory Reference
14745 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14746 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14748 unsigned DstLoReg, DstHiReg;
14749 unsigned SrcLoReg, SrcHiReg;
14750 unsigned MemOpndSlot;
14752 unsigned CurOp = 0;
14754 DstLoReg = MI->getOperand(CurOp++).getReg();
14755 DstHiReg = MI->getOperand(CurOp++).getReg();
14756 MemOpndSlot = CurOp;
14757 CurOp += X86::AddrNumOperands;
14758 SrcLoReg = MI->getOperand(CurOp++).getReg();
14759 SrcHiReg = MI->getOperand(CurOp++).getReg();
14761 const TargetRegisterClass *RC = &X86::GR32RegClass;
14762 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14764 unsigned t1L = MRI.createVirtualRegister(RC);
14765 unsigned t1H = MRI.createVirtualRegister(RC);
14766 unsigned t2L = MRI.createVirtualRegister(RC);
14767 unsigned t2H = MRI.createVirtualRegister(RC);
14768 unsigned t3L = MRI.createVirtualRegister(RC);
14769 unsigned t3H = MRI.createVirtualRegister(RC);
14770 unsigned t4L = MRI.createVirtualRegister(RC);
14771 unsigned t4H = MRI.createVirtualRegister(RC);
14773 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14774 unsigned LOADOpc = X86::MOV32rm;
14776 // For the atomic load-arith operator, we generate
14779 // t1L = LOAD [MI.addr + 0]
14780 // t1H = LOAD [MI.addr + 4]
14782 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14783 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14784 // t2L = OP MI.val.lo, t4L
14785 // t2H = OP MI.val.hi, t4H
14788 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14796 MachineBasicBlock *thisMBB = MBB;
14797 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14798 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14799 MF->insert(I, mainMBB);
14800 MF->insert(I, sinkMBB);
14802 MachineInstrBuilder MIB;
14804 // Transfer the remainder of BB and its successor edges to sinkMBB.
14805 sinkMBB->splice(sinkMBB->begin(), MBB,
14806 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14807 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14811 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14812 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14813 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14815 NewMO.setIsKill(false);
14816 MIB.addOperand(NewMO);
14818 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14819 unsigned flags = (*MMOI)->getFlags();
14820 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14821 MachineMemOperand *MMO =
14822 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14823 (*MMOI)->getSize(),
14824 (*MMOI)->getBaseAlignment(),
14825 (*MMOI)->getTBAAInfo(),
14826 (*MMOI)->getRanges());
14827 MIB.addMemOperand(MMO);
14829 MachineInstr *LowMI = MIB;
14832 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14833 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14834 if (i == X86::AddrDisp) {
14835 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14837 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14839 NewMO.setIsKill(false);
14840 MIB.addOperand(NewMO);
14843 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14845 thisMBB->addSuccessor(mainMBB);
14848 MachineBasicBlock *origMainMBB = mainMBB;
14851 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14852 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14853 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14854 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14856 unsigned Opc = MI->getOpcode();
14859 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14860 case X86::ATOMAND6432:
14861 case X86::ATOMOR6432:
14862 case X86::ATOMXOR6432:
14863 case X86::ATOMADD6432:
14864 case X86::ATOMSUB6432: {
14866 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14867 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14869 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14873 case X86::ATOMNAND6432: {
14874 unsigned HiOpc, NOTOpc;
14875 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14876 unsigned TmpL = MRI.createVirtualRegister(RC);
14877 unsigned TmpH = MRI.createVirtualRegister(RC);
14878 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14880 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14882 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14883 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14886 case X86::ATOMMAX6432:
14887 case X86::ATOMMIN6432:
14888 case X86::ATOMUMAX6432:
14889 case X86::ATOMUMIN6432: {
14891 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14892 unsigned cL = MRI.createVirtualRegister(RC8);
14893 unsigned cH = MRI.createVirtualRegister(RC8);
14894 unsigned cL32 = MRI.createVirtualRegister(RC);
14895 unsigned cH32 = MRI.createVirtualRegister(RC);
14896 unsigned cc = MRI.createVirtualRegister(RC);
14897 // cl := cmp src_lo, lo
14898 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14899 .addReg(SrcLoReg).addReg(t4L);
14900 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14901 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14902 // ch := cmp src_hi, hi
14903 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14904 .addReg(SrcHiReg).addReg(t4H);
14905 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14906 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14907 // cc := if (src_hi == hi) ? cl : ch;
14908 if (Subtarget->hasCMov()) {
14909 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14910 .addReg(cH32).addReg(cL32);
14912 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14913 .addReg(cH32).addReg(cL32)
14914 .addImm(X86::COND_E);
14915 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14917 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14918 if (Subtarget->hasCMov()) {
14919 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14920 .addReg(SrcLoReg).addReg(t4L);
14921 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14922 .addReg(SrcHiReg).addReg(t4H);
14924 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14925 .addReg(SrcLoReg).addReg(t4L)
14926 .addImm(X86::COND_NE);
14927 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14928 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14929 // 2nd CMOV lowering.
14930 mainMBB->addLiveIn(X86::EFLAGS);
14931 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14932 .addReg(SrcHiReg).addReg(t4H)
14933 .addImm(X86::COND_NE);
14934 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14935 // Replace the original PHI node as mainMBB is changed after CMOV
14937 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14938 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14939 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14940 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14941 PhiL->eraseFromParent();
14942 PhiH->eraseFromParent();
14946 case X86::ATOMSWAP6432: {
14948 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14949 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14950 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14955 // Copy EDX:EAX back from HiReg:LoReg
14956 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14957 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14958 // Copy ECX:EBX from t1H:t1L
14959 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14960 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14962 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14963 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14964 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14966 NewMO.setIsKill(false);
14967 MIB.addOperand(NewMO);
14969 MIB.setMemRefs(MMOBegin, MMOEnd);
14971 // Copy EDX:EAX back to t3H:t3L
14972 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14973 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14975 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14977 mainMBB->addSuccessor(origMainMBB);
14978 mainMBB->addSuccessor(sinkMBB);
14981 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14982 TII->get(TargetOpcode::COPY), DstLoReg)
14984 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14985 TII->get(TargetOpcode::COPY), DstHiReg)
14988 MI->eraseFromParent();
14992 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14993 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14994 // in the .td file.
14995 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14996 const TargetInstrInfo *TII) {
14998 switch (MI->getOpcode()) {
14999 default: llvm_unreachable("illegal opcode!");
15000 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15001 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15002 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15003 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15004 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15005 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15006 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15007 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15010 DebugLoc dl = MI->getDebugLoc();
15011 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15013 unsigned NumArgs = MI->getNumOperands();
15014 for (unsigned i = 1; i < NumArgs; ++i) {
15015 MachineOperand &Op = MI->getOperand(i);
15016 if (!(Op.isReg() && Op.isImplicit()))
15017 MIB.addOperand(Op);
15019 if (MI->hasOneMemOperand())
15020 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15022 BuildMI(*BB, MI, dl,
15023 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15024 .addReg(X86::XMM0);
15026 MI->eraseFromParent();
15030 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15031 // defs in an instruction pattern
15032 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15033 const TargetInstrInfo *TII) {
15035 switch (MI->getOpcode()) {
15036 default: llvm_unreachable("illegal opcode!");
15037 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15038 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15039 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15040 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15041 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15042 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15043 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15044 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15047 DebugLoc dl = MI->getDebugLoc();
15048 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15050 unsigned NumArgs = MI->getNumOperands(); // remove the results
15051 for (unsigned i = 1; i < NumArgs; ++i) {
15052 MachineOperand &Op = MI->getOperand(i);
15053 if (!(Op.isReg() && Op.isImplicit()))
15054 MIB.addOperand(Op);
15056 if (MI->hasOneMemOperand())
15057 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15059 BuildMI(*BB, MI, dl,
15060 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15063 MI->eraseFromParent();
15067 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15068 const TargetInstrInfo *TII,
15069 const X86Subtarget* Subtarget) {
15070 DebugLoc dl = MI->getDebugLoc();
15072 // Address into RAX/EAX, other two args into ECX, EDX.
15073 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
15074 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15075 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15076 for (int i = 0; i < X86::AddrNumOperands; ++i)
15077 MIB.addOperand(MI->getOperand(i));
15079 unsigned ValOps = X86::AddrNumOperands;
15080 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15081 .addReg(MI->getOperand(ValOps).getReg());
15082 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15083 .addReg(MI->getOperand(ValOps+1).getReg());
15085 // The instruction doesn't actually take any operands though.
15086 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15088 MI->eraseFromParent(); // The pseudo is gone now.
15092 MachineBasicBlock *
15093 X86TargetLowering::EmitVAARG64WithCustomInserter(
15095 MachineBasicBlock *MBB) const {
15096 // Emit va_arg instruction on X86-64.
15098 // Operands to this pseudo-instruction:
15099 // 0 ) Output : destination address (reg)
15100 // 1-5) Input : va_list address (addr, i64mem)
15101 // 6 ) ArgSize : Size (in bytes) of vararg type
15102 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15103 // 8 ) Align : Alignment of type
15104 // 9 ) EFLAGS (implicit-def)
15106 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15107 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15109 unsigned DestReg = MI->getOperand(0).getReg();
15110 MachineOperand &Base = MI->getOperand(1);
15111 MachineOperand &Scale = MI->getOperand(2);
15112 MachineOperand &Index = MI->getOperand(3);
15113 MachineOperand &Disp = MI->getOperand(4);
15114 MachineOperand &Segment = MI->getOperand(5);
15115 unsigned ArgSize = MI->getOperand(6).getImm();
15116 unsigned ArgMode = MI->getOperand(7).getImm();
15117 unsigned Align = MI->getOperand(8).getImm();
15119 // Memory Reference
15120 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15121 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15122 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15124 // Machine Information
15125 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15126 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15127 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15128 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15129 DebugLoc DL = MI->getDebugLoc();
15131 // struct va_list {
15134 // i64 overflow_area (address)
15135 // i64 reg_save_area (address)
15137 // sizeof(va_list) = 24
15138 // alignment(va_list) = 8
15140 unsigned TotalNumIntRegs = 6;
15141 unsigned TotalNumXMMRegs = 8;
15142 bool UseGPOffset = (ArgMode == 1);
15143 bool UseFPOffset = (ArgMode == 2);
15144 unsigned MaxOffset = TotalNumIntRegs * 8 +
15145 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15147 /* Align ArgSize to a multiple of 8 */
15148 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15149 bool NeedsAlign = (Align > 8);
15151 MachineBasicBlock *thisMBB = MBB;
15152 MachineBasicBlock *overflowMBB;
15153 MachineBasicBlock *offsetMBB;
15154 MachineBasicBlock *endMBB;
15156 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15157 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15158 unsigned OffsetReg = 0;
15160 if (!UseGPOffset && !UseFPOffset) {
15161 // If we only pull from the overflow region, we don't create a branch.
15162 // We don't need to alter control flow.
15163 OffsetDestReg = 0; // unused
15164 OverflowDestReg = DestReg;
15167 overflowMBB = thisMBB;
15170 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15171 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15172 // If not, pull from overflow_area. (branch to overflowMBB)
15177 // offsetMBB overflowMBB
15182 // Registers for the PHI in endMBB
15183 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15184 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15186 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15187 MachineFunction *MF = MBB->getParent();
15188 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15189 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15190 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15192 MachineFunction::iterator MBBIter = MBB;
15195 // Insert the new basic blocks
15196 MF->insert(MBBIter, offsetMBB);
15197 MF->insert(MBBIter, overflowMBB);
15198 MF->insert(MBBIter, endMBB);
15200 // Transfer the remainder of MBB and its successor edges to endMBB.
15201 endMBB->splice(endMBB->begin(), thisMBB,
15202 llvm::next(MachineBasicBlock::iterator(MI)),
15204 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15206 // Make offsetMBB and overflowMBB successors of thisMBB
15207 thisMBB->addSuccessor(offsetMBB);
15208 thisMBB->addSuccessor(overflowMBB);
15210 // endMBB is a successor of both offsetMBB and overflowMBB
15211 offsetMBB->addSuccessor(endMBB);
15212 overflowMBB->addSuccessor(endMBB);
15214 // Load the offset value into a register
15215 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15216 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15220 .addDisp(Disp, UseFPOffset ? 4 : 0)
15221 .addOperand(Segment)
15222 .setMemRefs(MMOBegin, MMOEnd);
15224 // Check if there is enough room left to pull this argument.
15225 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15227 .addImm(MaxOffset + 8 - ArgSizeA8);
15229 // Branch to "overflowMBB" if offset >= max
15230 // Fall through to "offsetMBB" otherwise
15231 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15232 .addMBB(overflowMBB);
15235 // In offsetMBB, emit code to use the reg_save_area.
15237 assert(OffsetReg != 0);
15239 // Read the reg_save_area address.
15240 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15241 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15246 .addOperand(Segment)
15247 .setMemRefs(MMOBegin, MMOEnd);
15249 // Zero-extend the offset
15250 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15251 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15254 .addImm(X86::sub_32bit);
15256 // Add the offset to the reg_save_area to get the final address.
15257 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15258 .addReg(OffsetReg64)
15259 .addReg(RegSaveReg);
15261 // Compute the offset for the next argument
15262 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15263 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15265 .addImm(UseFPOffset ? 16 : 8);
15267 // Store it back into the va_list.
15268 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15272 .addDisp(Disp, UseFPOffset ? 4 : 0)
15273 .addOperand(Segment)
15274 .addReg(NextOffsetReg)
15275 .setMemRefs(MMOBegin, MMOEnd);
15278 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15283 // Emit code to use overflow area
15286 // Load the overflow_area address into a register.
15287 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15288 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15293 .addOperand(Segment)
15294 .setMemRefs(MMOBegin, MMOEnd);
15296 // If we need to align it, do so. Otherwise, just copy the address
15297 // to OverflowDestReg.
15299 // Align the overflow address
15300 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15301 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15303 // aligned_addr = (addr + (align-1)) & ~(align-1)
15304 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15305 .addReg(OverflowAddrReg)
15308 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15310 .addImm(~(uint64_t)(Align-1));
15312 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15313 .addReg(OverflowAddrReg);
15316 // Compute the next overflow address after this argument.
15317 // (the overflow address should be kept 8-byte aligned)
15318 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15319 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15320 .addReg(OverflowDestReg)
15321 .addImm(ArgSizeA8);
15323 // Store the new overflow address.
15324 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15329 .addOperand(Segment)
15330 .addReg(NextAddrReg)
15331 .setMemRefs(MMOBegin, MMOEnd);
15333 // If we branched, emit the PHI to the front of endMBB.
15335 BuildMI(*endMBB, endMBB->begin(), DL,
15336 TII->get(X86::PHI), DestReg)
15337 .addReg(OffsetDestReg).addMBB(offsetMBB)
15338 .addReg(OverflowDestReg).addMBB(overflowMBB);
15341 // Erase the pseudo instruction
15342 MI->eraseFromParent();
15347 MachineBasicBlock *
15348 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15350 MachineBasicBlock *MBB) const {
15351 // Emit code to save XMM registers to the stack. The ABI says that the
15352 // number of registers to save is given in %al, so it's theoretically
15353 // possible to do an indirect jump trick to avoid saving all of them,
15354 // however this code takes a simpler approach and just executes all
15355 // of the stores if %al is non-zero. It's less code, and it's probably
15356 // easier on the hardware branch predictor, and stores aren't all that
15357 // expensive anyway.
15359 // Create the new basic blocks. One block contains all the XMM stores,
15360 // and one block is the final destination regardless of whether any
15361 // stores were performed.
15362 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15363 MachineFunction *F = MBB->getParent();
15364 MachineFunction::iterator MBBIter = MBB;
15366 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15367 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15368 F->insert(MBBIter, XMMSaveMBB);
15369 F->insert(MBBIter, EndMBB);
15371 // Transfer the remainder of MBB and its successor edges to EndMBB.
15372 EndMBB->splice(EndMBB->begin(), MBB,
15373 llvm::next(MachineBasicBlock::iterator(MI)),
15375 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15377 // The original block will now fall through to the XMM save block.
15378 MBB->addSuccessor(XMMSaveMBB);
15379 // The XMMSaveMBB will fall through to the end block.
15380 XMMSaveMBB->addSuccessor(EndMBB);
15382 // Now add the instructions.
15383 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15384 DebugLoc DL = MI->getDebugLoc();
15386 unsigned CountReg = MI->getOperand(0).getReg();
15387 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15388 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15390 if (!Subtarget->isTargetWin64()) {
15391 // If %al is 0, branch around the XMM save block.
15392 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15393 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15394 MBB->addSuccessor(EndMBB);
15397 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
15398 // that was just emitted, but clearly shouldn't be "saved".
15399 assert((MI->getNumOperands() <= 3 ||
15400 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
15401 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
15402 && "Expected last argument to be EFLAGS");
15403 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15404 // In the XMM save block, save all the XMM argument registers.
15405 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
15406 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15407 MachineMemOperand *MMO =
15408 F->getMachineMemOperand(
15409 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15410 MachineMemOperand::MOStore,
15411 /*Size=*/16, /*Align=*/16);
15412 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15413 .addFrameIndex(RegSaveFrameIndex)
15414 .addImm(/*Scale=*/1)
15415 .addReg(/*IndexReg=*/0)
15416 .addImm(/*Disp=*/Offset)
15417 .addReg(/*Segment=*/0)
15418 .addReg(MI->getOperand(i).getReg())
15419 .addMemOperand(MMO);
15422 MI->eraseFromParent(); // The pseudo instruction is gone now.
15427 // The EFLAGS operand of SelectItr might be missing a kill marker
15428 // because there were multiple uses of EFLAGS, and ISel didn't know
15429 // which to mark. Figure out whether SelectItr should have had a
15430 // kill marker, and set it if it should. Returns the correct kill
15432 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15433 MachineBasicBlock* BB,
15434 const TargetRegisterInfo* TRI) {
15435 // Scan forward through BB for a use/def of EFLAGS.
15436 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15437 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15438 const MachineInstr& mi = *miI;
15439 if (mi.readsRegister(X86::EFLAGS))
15441 if (mi.definesRegister(X86::EFLAGS))
15442 break; // Should have kill-flag - update below.
15445 // If we hit the end of the block, check whether EFLAGS is live into a
15447 if (miI == BB->end()) {
15448 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15449 sEnd = BB->succ_end();
15450 sItr != sEnd; ++sItr) {
15451 MachineBasicBlock* succ = *sItr;
15452 if (succ->isLiveIn(X86::EFLAGS))
15457 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15458 // out. SelectMI should have a kill flag on EFLAGS.
15459 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15463 MachineBasicBlock *
15464 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15465 MachineBasicBlock *BB) const {
15466 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15467 DebugLoc DL = MI->getDebugLoc();
15469 // To "insert" a SELECT_CC instruction, we actually have to insert the
15470 // diamond control-flow pattern. The incoming instruction knows the
15471 // destination vreg to set, the condition code register to branch on, the
15472 // true/false values to select between, and a branch opcode to use.
15473 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15474 MachineFunction::iterator It = BB;
15480 // cmpTY ccX, r1, r2
15482 // fallthrough --> copy0MBB
15483 MachineBasicBlock *thisMBB = BB;
15484 MachineFunction *F = BB->getParent();
15485 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15486 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15487 F->insert(It, copy0MBB);
15488 F->insert(It, sinkMBB);
15490 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15491 // live into the sink and copy blocks.
15492 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15493 if (!MI->killsRegister(X86::EFLAGS) &&
15494 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15495 copy0MBB->addLiveIn(X86::EFLAGS);
15496 sinkMBB->addLiveIn(X86::EFLAGS);
15499 // Transfer the remainder of BB and its successor edges to sinkMBB.
15500 sinkMBB->splice(sinkMBB->begin(), BB,
15501 llvm::next(MachineBasicBlock::iterator(MI)),
15503 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15505 // Add the true and fallthrough blocks as its successors.
15506 BB->addSuccessor(copy0MBB);
15507 BB->addSuccessor(sinkMBB);
15509 // Create the conditional branch instruction.
15511 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15512 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15515 // %FalseValue = ...
15516 // # fallthrough to sinkMBB
15517 copy0MBB->addSuccessor(sinkMBB);
15520 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15522 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15523 TII->get(X86::PHI), MI->getOperand(0).getReg())
15524 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15525 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15527 MI->eraseFromParent(); // The pseudo instruction is gone now.
15531 MachineBasicBlock *
15532 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15533 bool Is64Bit) const {
15534 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15535 DebugLoc DL = MI->getDebugLoc();
15536 MachineFunction *MF = BB->getParent();
15537 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15539 assert(getTargetMachine().Options.EnableSegmentedStacks);
15541 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15542 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15545 // ... [Till the alloca]
15546 // If stacklet is not large enough, jump to mallocMBB
15549 // Allocate by subtracting from RSP
15550 // Jump to continueMBB
15553 // Allocate by call to runtime
15557 // [rest of original BB]
15560 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15561 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15562 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15564 MachineRegisterInfo &MRI = MF->getRegInfo();
15565 const TargetRegisterClass *AddrRegClass =
15566 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15568 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15569 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15570 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15571 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15572 sizeVReg = MI->getOperand(1).getReg(),
15573 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15575 MachineFunction::iterator MBBIter = BB;
15578 MF->insert(MBBIter, bumpMBB);
15579 MF->insert(MBBIter, mallocMBB);
15580 MF->insert(MBBIter, continueMBB);
15582 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15583 (MachineBasicBlock::iterator(MI)), BB->end());
15584 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15586 // Add code to the main basic block to check if the stack limit has been hit,
15587 // and if so, jump to mallocMBB otherwise to bumpMBB.
15588 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15589 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15590 .addReg(tmpSPVReg).addReg(sizeVReg);
15591 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15592 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15593 .addReg(SPLimitVReg);
15594 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15596 // bumpMBB simply decreases the stack pointer, since we know the current
15597 // stacklet has enough space.
15598 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15599 .addReg(SPLimitVReg);
15600 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15601 .addReg(SPLimitVReg);
15602 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15604 // Calls into a routine in libgcc to allocate more space from the heap.
15605 const uint32_t *RegMask =
15606 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15608 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15610 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15611 .addExternalSymbol("__morestack_allocate_stack_space")
15612 .addRegMask(RegMask)
15613 .addReg(X86::RDI, RegState::Implicit)
15614 .addReg(X86::RAX, RegState::ImplicitDefine);
15616 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15618 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15619 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15620 .addExternalSymbol("__morestack_allocate_stack_space")
15621 .addRegMask(RegMask)
15622 .addReg(X86::EAX, RegState::ImplicitDefine);
15626 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15629 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15630 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15631 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15633 // Set up the CFG correctly.
15634 BB->addSuccessor(bumpMBB);
15635 BB->addSuccessor(mallocMBB);
15636 mallocMBB->addSuccessor(continueMBB);
15637 bumpMBB->addSuccessor(continueMBB);
15639 // Take care of the PHI nodes.
15640 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15641 MI->getOperand(0).getReg())
15642 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15643 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15645 // Delete the original pseudo instruction.
15646 MI->eraseFromParent();
15649 return continueMBB;
15652 MachineBasicBlock *
15653 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15654 MachineBasicBlock *BB) const {
15655 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15656 DebugLoc DL = MI->getDebugLoc();
15658 assert(!Subtarget->isTargetMacho());
15660 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15661 // non-trivial part is impdef of ESP.
15663 if (Subtarget->isTargetWin64()) {
15664 if (Subtarget->isTargetCygMing()) {
15665 // ___chkstk(Mingw64):
15666 // Clobbers R10, R11, RAX and EFLAGS.
15668 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15669 .addExternalSymbol("___chkstk")
15670 .addReg(X86::RAX, RegState::Implicit)
15671 .addReg(X86::RSP, RegState::Implicit)
15672 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15673 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15674 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15676 // __chkstk(MSVCRT): does not update stack pointer.
15677 // Clobbers R10, R11 and EFLAGS.
15678 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15679 .addExternalSymbol("__chkstk")
15680 .addReg(X86::RAX, RegState::Implicit)
15681 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15682 // RAX has the offset to be subtracted from RSP.
15683 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15688 const char *StackProbeSymbol =
15689 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15691 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15692 .addExternalSymbol(StackProbeSymbol)
15693 .addReg(X86::EAX, RegState::Implicit)
15694 .addReg(X86::ESP, RegState::Implicit)
15695 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15696 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15697 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15700 MI->eraseFromParent(); // The pseudo instruction is gone now.
15704 MachineBasicBlock *
15705 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15706 MachineBasicBlock *BB) const {
15707 // This is pretty easy. We're taking the value that we received from
15708 // our load from the relocation, sticking it in either RDI (x86-64)
15709 // or EAX and doing an indirect call. The return value will then
15710 // be in the normal return register.
15711 const X86InstrInfo *TII
15712 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15713 DebugLoc DL = MI->getDebugLoc();
15714 MachineFunction *F = BB->getParent();
15716 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15717 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15719 // Get a register mask for the lowered call.
15720 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15721 // proper register mask.
15722 const uint32_t *RegMask =
15723 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15724 if (Subtarget->is64Bit()) {
15725 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15726 TII->get(X86::MOV64rm), X86::RDI)
15728 .addImm(0).addReg(0)
15729 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15730 MI->getOperand(3).getTargetFlags())
15732 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15733 addDirectMem(MIB, X86::RDI);
15734 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15735 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15736 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15737 TII->get(X86::MOV32rm), X86::EAX)
15739 .addImm(0).addReg(0)
15740 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15741 MI->getOperand(3).getTargetFlags())
15743 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15744 addDirectMem(MIB, X86::EAX);
15745 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15747 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15748 TII->get(X86::MOV32rm), X86::EAX)
15749 .addReg(TII->getGlobalBaseReg(F))
15750 .addImm(0).addReg(0)
15751 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15752 MI->getOperand(3).getTargetFlags())
15754 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15755 addDirectMem(MIB, X86::EAX);
15756 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15759 MI->eraseFromParent(); // The pseudo instruction is gone now.
15763 MachineBasicBlock *
15764 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15765 MachineBasicBlock *MBB) const {
15766 DebugLoc DL = MI->getDebugLoc();
15767 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15769 MachineFunction *MF = MBB->getParent();
15770 MachineRegisterInfo &MRI = MF->getRegInfo();
15772 const BasicBlock *BB = MBB->getBasicBlock();
15773 MachineFunction::iterator I = MBB;
15776 // Memory Reference
15777 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15778 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15781 unsigned MemOpndSlot = 0;
15783 unsigned CurOp = 0;
15785 DstReg = MI->getOperand(CurOp++).getReg();
15786 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15787 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15788 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15789 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15791 MemOpndSlot = CurOp;
15793 MVT PVT = getPointerTy();
15794 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15795 "Invalid Pointer Size!");
15797 // For v = setjmp(buf), we generate
15800 // buf[LabelOffset] = restoreMBB
15801 // SjLjSetup restoreMBB
15807 // v = phi(main, restore)
15812 MachineBasicBlock *thisMBB = MBB;
15813 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15814 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15815 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15816 MF->insert(I, mainMBB);
15817 MF->insert(I, sinkMBB);
15818 MF->push_back(restoreMBB);
15820 MachineInstrBuilder MIB;
15822 // Transfer the remainder of BB and its successor edges to sinkMBB.
15823 sinkMBB->splice(sinkMBB->begin(), MBB,
15824 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15825 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15828 unsigned PtrStoreOpc = 0;
15829 unsigned LabelReg = 0;
15830 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15831 Reloc::Model RM = getTargetMachine().getRelocationModel();
15832 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15833 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15835 // Prepare IP either in reg or imm.
15836 if (!UseImmLabel) {
15837 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15838 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15839 LabelReg = MRI.createVirtualRegister(PtrRC);
15840 if (Subtarget->is64Bit()) {
15841 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15845 .addMBB(restoreMBB)
15848 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15849 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15850 .addReg(XII->getGlobalBaseReg(MF))
15853 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15857 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15859 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15860 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15861 if (i == X86::AddrDisp)
15862 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15864 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15867 MIB.addReg(LabelReg);
15869 MIB.addMBB(restoreMBB);
15870 MIB.setMemRefs(MMOBegin, MMOEnd);
15872 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15873 .addMBB(restoreMBB);
15875 const X86RegisterInfo *RegInfo =
15876 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15877 MIB.addRegMask(RegInfo->getNoPreservedMask());
15878 thisMBB->addSuccessor(mainMBB);
15879 thisMBB->addSuccessor(restoreMBB);
15883 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15884 mainMBB->addSuccessor(sinkMBB);
15887 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15888 TII->get(X86::PHI), DstReg)
15889 .addReg(mainDstReg).addMBB(mainMBB)
15890 .addReg(restoreDstReg).addMBB(restoreMBB);
15893 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15894 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15895 restoreMBB->addSuccessor(sinkMBB);
15897 MI->eraseFromParent();
15901 MachineBasicBlock *
15902 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15903 MachineBasicBlock *MBB) const {
15904 DebugLoc DL = MI->getDebugLoc();
15905 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15907 MachineFunction *MF = MBB->getParent();
15908 MachineRegisterInfo &MRI = MF->getRegInfo();
15910 // Memory Reference
15911 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15912 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15914 MVT PVT = getPointerTy();
15915 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15916 "Invalid Pointer Size!");
15918 const TargetRegisterClass *RC =
15919 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15920 unsigned Tmp = MRI.createVirtualRegister(RC);
15921 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15922 const X86RegisterInfo *RegInfo =
15923 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15924 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15925 unsigned SP = RegInfo->getStackRegister();
15927 MachineInstrBuilder MIB;
15929 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15930 const int64_t SPOffset = 2 * PVT.getStoreSize();
15932 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15933 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15936 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15937 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15938 MIB.addOperand(MI->getOperand(i));
15939 MIB.setMemRefs(MMOBegin, MMOEnd);
15941 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15942 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15943 if (i == X86::AddrDisp)
15944 MIB.addDisp(MI->getOperand(i), LabelOffset);
15946 MIB.addOperand(MI->getOperand(i));
15948 MIB.setMemRefs(MMOBegin, MMOEnd);
15950 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15951 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15952 if (i == X86::AddrDisp)
15953 MIB.addDisp(MI->getOperand(i), SPOffset);
15955 MIB.addOperand(MI->getOperand(i));
15957 MIB.setMemRefs(MMOBegin, MMOEnd);
15959 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15961 MI->eraseFromParent();
15965 MachineBasicBlock *
15966 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15967 MachineBasicBlock *BB) const {
15968 switch (MI->getOpcode()) {
15969 default: llvm_unreachable("Unexpected instr type to insert");
15970 case X86::TAILJMPd64:
15971 case X86::TAILJMPr64:
15972 case X86::TAILJMPm64:
15973 llvm_unreachable("TAILJMP64 would not be touched here.");
15974 case X86::TCRETURNdi64:
15975 case X86::TCRETURNri64:
15976 case X86::TCRETURNmi64:
15978 case X86::WIN_ALLOCA:
15979 return EmitLoweredWinAlloca(MI, BB);
15980 case X86::SEG_ALLOCA_32:
15981 return EmitLoweredSegAlloca(MI, BB, false);
15982 case X86::SEG_ALLOCA_64:
15983 return EmitLoweredSegAlloca(MI, BB, true);
15984 case X86::TLSCall_32:
15985 case X86::TLSCall_64:
15986 return EmitLoweredTLSCall(MI, BB);
15987 case X86::CMOV_GR8:
15988 case X86::CMOV_FR32:
15989 case X86::CMOV_FR64:
15990 case X86::CMOV_V4F32:
15991 case X86::CMOV_V2F64:
15992 case X86::CMOV_V2I64:
15993 case X86::CMOV_V8F32:
15994 case X86::CMOV_V4F64:
15995 case X86::CMOV_V4I64:
15996 case X86::CMOV_V16F32:
15997 case X86::CMOV_V8F64:
15998 case X86::CMOV_V8I64:
15999 case X86::CMOV_GR16:
16000 case X86::CMOV_GR32:
16001 case X86::CMOV_RFP32:
16002 case X86::CMOV_RFP64:
16003 case X86::CMOV_RFP80:
16004 return EmitLoweredSelect(MI, BB);
16006 case X86::FP32_TO_INT16_IN_MEM:
16007 case X86::FP32_TO_INT32_IN_MEM:
16008 case X86::FP32_TO_INT64_IN_MEM:
16009 case X86::FP64_TO_INT16_IN_MEM:
16010 case X86::FP64_TO_INT32_IN_MEM:
16011 case X86::FP64_TO_INT64_IN_MEM:
16012 case X86::FP80_TO_INT16_IN_MEM:
16013 case X86::FP80_TO_INT32_IN_MEM:
16014 case X86::FP80_TO_INT64_IN_MEM: {
16015 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16016 DebugLoc DL = MI->getDebugLoc();
16018 // Change the floating point control register to use "round towards zero"
16019 // mode when truncating to an integer value.
16020 MachineFunction *F = BB->getParent();
16021 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
16022 addFrameReference(BuildMI(*BB, MI, DL,
16023 TII->get(X86::FNSTCW16m)), CWFrameIdx);
16025 // Load the old value of the high byte of the control word...
16027 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
16028 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
16031 // Set the high part to be round to zero...
16032 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
16035 // Reload the modified control word now...
16036 addFrameReference(BuildMI(*BB, MI, DL,
16037 TII->get(X86::FLDCW16m)), CWFrameIdx);
16039 // Restore the memory image of control word to original value
16040 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
16043 // Get the X86 opcode to use.
16045 switch (MI->getOpcode()) {
16046 default: llvm_unreachable("illegal opcode!");
16047 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
16048 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
16049 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
16050 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
16051 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
16052 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
16053 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
16054 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
16055 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
16059 MachineOperand &Op = MI->getOperand(0);
16061 AM.BaseType = X86AddressMode::RegBase;
16062 AM.Base.Reg = Op.getReg();
16064 AM.BaseType = X86AddressMode::FrameIndexBase;
16065 AM.Base.FrameIndex = Op.getIndex();
16067 Op = MI->getOperand(1);
16069 AM.Scale = Op.getImm();
16070 Op = MI->getOperand(2);
16072 AM.IndexReg = Op.getImm();
16073 Op = MI->getOperand(3);
16074 if (Op.isGlobal()) {
16075 AM.GV = Op.getGlobal();
16077 AM.Disp = Op.getImm();
16079 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
16080 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16082 // Reload the original control word now.
16083 addFrameReference(BuildMI(*BB, MI, DL,
16084 TII->get(X86::FLDCW16m)), CWFrameIdx);
16086 MI->eraseFromParent(); // The pseudo instruction is gone now.
16089 // String/text processing lowering.
16090 case X86::PCMPISTRM128REG:
16091 case X86::VPCMPISTRM128REG:
16092 case X86::PCMPISTRM128MEM:
16093 case X86::VPCMPISTRM128MEM:
16094 case X86::PCMPESTRM128REG:
16095 case X86::VPCMPESTRM128REG:
16096 case X86::PCMPESTRM128MEM:
16097 case X86::VPCMPESTRM128MEM:
16098 assert(Subtarget->hasSSE42() &&
16099 "Target must have SSE4.2 or AVX features enabled");
16100 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16102 // String/text processing lowering.
16103 case X86::PCMPISTRIREG:
16104 case X86::VPCMPISTRIREG:
16105 case X86::PCMPISTRIMEM:
16106 case X86::VPCMPISTRIMEM:
16107 case X86::PCMPESTRIREG:
16108 case X86::VPCMPESTRIREG:
16109 case X86::PCMPESTRIMEM:
16110 case X86::VPCMPESTRIMEM:
16111 assert(Subtarget->hasSSE42() &&
16112 "Target must have SSE4.2 or AVX features enabled");
16113 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16115 // Thread synchronization.
16117 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16121 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16123 // Atomic Lowering.
16124 case X86::ATOMAND8:
16125 case X86::ATOMAND16:
16126 case X86::ATOMAND32:
16127 case X86::ATOMAND64:
16130 case X86::ATOMOR16:
16131 case X86::ATOMOR32:
16132 case X86::ATOMOR64:
16134 case X86::ATOMXOR16:
16135 case X86::ATOMXOR8:
16136 case X86::ATOMXOR32:
16137 case X86::ATOMXOR64:
16139 case X86::ATOMNAND8:
16140 case X86::ATOMNAND16:
16141 case X86::ATOMNAND32:
16142 case X86::ATOMNAND64:
16144 case X86::ATOMMAX8:
16145 case X86::ATOMMAX16:
16146 case X86::ATOMMAX32:
16147 case X86::ATOMMAX64:
16149 case X86::ATOMMIN8:
16150 case X86::ATOMMIN16:
16151 case X86::ATOMMIN32:
16152 case X86::ATOMMIN64:
16154 case X86::ATOMUMAX8:
16155 case X86::ATOMUMAX16:
16156 case X86::ATOMUMAX32:
16157 case X86::ATOMUMAX64:
16159 case X86::ATOMUMIN8:
16160 case X86::ATOMUMIN16:
16161 case X86::ATOMUMIN32:
16162 case X86::ATOMUMIN64:
16163 return EmitAtomicLoadArith(MI, BB);
16165 // This group does 64-bit operations on a 32-bit host.
16166 case X86::ATOMAND6432:
16167 case X86::ATOMOR6432:
16168 case X86::ATOMXOR6432:
16169 case X86::ATOMNAND6432:
16170 case X86::ATOMADD6432:
16171 case X86::ATOMSUB6432:
16172 case X86::ATOMMAX6432:
16173 case X86::ATOMMIN6432:
16174 case X86::ATOMUMAX6432:
16175 case X86::ATOMUMIN6432:
16176 case X86::ATOMSWAP6432:
16177 return EmitAtomicLoadArith6432(MI, BB);
16179 case X86::VASTART_SAVE_XMM_REGS:
16180 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16182 case X86::VAARG_64:
16183 return EmitVAARG64WithCustomInserter(MI, BB);
16185 case X86::EH_SjLj_SetJmp32:
16186 case X86::EH_SjLj_SetJmp64:
16187 return emitEHSjLjSetJmp(MI, BB);
16189 case X86::EH_SjLj_LongJmp32:
16190 case X86::EH_SjLj_LongJmp64:
16191 return emitEHSjLjLongJmp(MI, BB);
16193 case TargetOpcode::STACKMAP:
16194 case TargetOpcode::PATCHPOINT:
16195 return emitPatchPoint(MI, BB);
16199 //===----------------------------------------------------------------------===//
16200 // X86 Optimization Hooks
16201 //===----------------------------------------------------------------------===//
16203 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16206 const SelectionDAG &DAG,
16207 unsigned Depth) const {
16208 unsigned BitWidth = KnownZero.getBitWidth();
16209 unsigned Opc = Op.getOpcode();
16210 assert((Opc >= ISD::BUILTIN_OP_END ||
16211 Opc == ISD::INTRINSIC_WO_CHAIN ||
16212 Opc == ISD::INTRINSIC_W_CHAIN ||
16213 Opc == ISD::INTRINSIC_VOID) &&
16214 "Should use MaskedValueIsZero if you don't know whether Op"
16215 " is a target node!");
16217 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16231 // These nodes' second result is a boolean.
16232 if (Op.getResNo() == 0)
16235 case X86ISD::SETCC:
16236 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16238 case ISD::INTRINSIC_WO_CHAIN: {
16239 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16240 unsigned NumLoBits = 0;
16243 case Intrinsic::x86_sse_movmsk_ps:
16244 case Intrinsic::x86_avx_movmsk_ps_256:
16245 case Intrinsic::x86_sse2_movmsk_pd:
16246 case Intrinsic::x86_avx_movmsk_pd_256:
16247 case Intrinsic::x86_mmx_pmovmskb:
16248 case Intrinsic::x86_sse2_pmovmskb_128:
16249 case Intrinsic::x86_avx2_pmovmskb: {
16250 // High bits of movmskp{s|d}, pmovmskb are known zero.
16252 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16253 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16254 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16255 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16256 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16257 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16258 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16259 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16261 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16270 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16271 unsigned Depth) const {
16272 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16273 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16274 return Op.getValueType().getScalarType().getSizeInBits();
16280 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16281 /// node is a GlobalAddress + offset.
16282 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16283 const GlobalValue* &GA,
16284 int64_t &Offset) const {
16285 if (N->getOpcode() == X86ISD::Wrapper) {
16286 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16287 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16288 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16292 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16295 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16296 /// same as extracting the high 128-bit part of 256-bit vector and then
16297 /// inserting the result into the low part of a new 256-bit vector
16298 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16299 EVT VT = SVOp->getValueType(0);
16300 unsigned NumElems = VT.getVectorNumElements();
16302 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16303 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16304 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16305 SVOp->getMaskElt(j) >= 0)
16311 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16312 /// same as extracting the low 128-bit part of 256-bit vector and then
16313 /// inserting the result into the high part of a new 256-bit vector
16314 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16315 EVT VT = SVOp->getValueType(0);
16316 unsigned NumElems = VT.getVectorNumElements();
16318 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16319 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16320 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16321 SVOp->getMaskElt(j) >= 0)
16327 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16328 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16329 TargetLowering::DAGCombinerInfo &DCI,
16330 const X86Subtarget* Subtarget) {
16332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16333 SDValue V1 = SVOp->getOperand(0);
16334 SDValue V2 = SVOp->getOperand(1);
16335 EVT VT = SVOp->getValueType(0);
16336 unsigned NumElems = VT.getVectorNumElements();
16338 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16339 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16343 // V UNDEF BUILD_VECTOR UNDEF
16345 // CONCAT_VECTOR CONCAT_VECTOR
16348 // RESULT: V + zero extended
16350 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16351 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16352 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16355 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16358 // To match the shuffle mask, the first half of the mask should
16359 // be exactly the first vector, and all the rest a splat with the
16360 // first element of the second one.
16361 for (unsigned i = 0; i != NumElems/2; ++i)
16362 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16363 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16366 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16367 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16368 if (Ld->hasNUsesOfValue(1, 0)) {
16369 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16370 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16372 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16373 array_lengthof(Ops),
16375 Ld->getPointerInfo(),
16376 Ld->getAlignment(),
16377 false/*isVolatile*/, true/*ReadMem*/,
16378 false/*WriteMem*/);
16380 // Make sure the newly-created LOAD is in the same position as Ld in
16381 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16382 // and update uses of Ld's output chain to use the TokenFactor.
16383 if (Ld->hasAnyUseOfValue(1)) {
16384 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16385 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16386 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16387 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16388 SDValue(ResNode.getNode(), 1));
16391 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16395 // Emit a zeroed vector and insert the desired subvector on its
16397 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16398 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16399 return DCI.CombineTo(N, InsV);
16402 //===--------------------------------------------------------------------===//
16403 // Combine some shuffles into subvector extracts and inserts:
16406 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16407 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16408 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16409 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16410 return DCI.CombineTo(N, InsV);
16413 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16414 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16415 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16416 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16417 return DCI.CombineTo(N, InsV);
16423 /// PerformShuffleCombine - Performs several different shuffle combines.
16424 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16425 TargetLowering::DAGCombinerInfo &DCI,
16426 const X86Subtarget *Subtarget) {
16428 EVT VT = N->getValueType(0);
16430 // Don't create instructions with illegal types after legalize types has run.
16431 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16432 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16435 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16436 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16437 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16438 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16440 // Only handle 128 wide vector from here on.
16441 if (!VT.is128BitVector())
16444 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16445 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16446 // consecutive, non-overlapping, and in the right order.
16447 SmallVector<SDValue, 16> Elts;
16448 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16449 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16451 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
16454 /// PerformTruncateCombine - Converts truncate operation to
16455 /// a sequence of vector shuffle operations.
16456 /// It is possible when we truncate 256-bit vector to 128-bit vector
16457 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16458 TargetLowering::DAGCombinerInfo &DCI,
16459 const X86Subtarget *Subtarget) {
16463 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16464 /// specific shuffle of a load can be folded into a single element load.
16465 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16466 /// shuffles have been customed lowered so we need to handle those here.
16467 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16468 TargetLowering::DAGCombinerInfo &DCI) {
16469 if (DCI.isBeforeLegalizeOps())
16472 SDValue InVec = N->getOperand(0);
16473 SDValue EltNo = N->getOperand(1);
16475 if (!isa<ConstantSDNode>(EltNo))
16478 EVT VT = InVec.getValueType();
16480 bool HasShuffleIntoBitcast = false;
16481 if (InVec.getOpcode() == ISD::BITCAST) {
16482 // Don't duplicate a load with other uses.
16483 if (!InVec.hasOneUse())
16485 EVT BCVT = InVec.getOperand(0).getValueType();
16486 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16488 InVec = InVec.getOperand(0);
16489 HasShuffleIntoBitcast = true;
16492 if (!isTargetShuffle(InVec.getOpcode()))
16495 // Don't duplicate a load with other uses.
16496 if (!InVec.hasOneUse())
16499 SmallVector<int, 16> ShuffleMask;
16501 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16505 // Select the input vector, guarding against out of range extract vector.
16506 unsigned NumElems = VT.getVectorNumElements();
16507 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16508 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16509 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16510 : InVec.getOperand(1);
16512 // If inputs to shuffle are the same for both ops, then allow 2 uses
16513 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16515 if (LdNode.getOpcode() == ISD::BITCAST) {
16516 // Don't duplicate a load with other uses.
16517 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16520 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16521 LdNode = LdNode.getOperand(0);
16524 if (!ISD::isNormalLoad(LdNode.getNode()))
16527 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16529 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16532 if (HasShuffleIntoBitcast) {
16533 // If there's a bitcast before the shuffle, check if the load type and
16534 // alignment is valid.
16535 unsigned Align = LN0->getAlignment();
16536 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16537 unsigned NewAlign = TLI.getDataLayout()->
16538 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16540 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16544 // All checks match so transform back to vector_shuffle so that DAG combiner
16545 // can finish the job
16548 // Create shuffle node taking into account the case that its a unary shuffle
16549 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16550 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16551 InVec.getOperand(0), Shuffle,
16553 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16554 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16558 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16559 /// generation and convert it from being a bunch of shuffles and extracts
16560 /// to a simple store and scalar loads to extract the elements.
16561 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16562 TargetLowering::DAGCombinerInfo &DCI) {
16563 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16564 if (NewOp.getNode())
16567 SDValue InputVector = N->getOperand(0);
16569 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16570 // from mmx to v2i32 has a single usage.
16571 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16572 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16573 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16574 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16575 N->getValueType(0),
16576 InputVector.getNode()->getOperand(0));
16578 // Only operate on vectors of 4 elements, where the alternative shuffling
16579 // gets to be more expensive.
16580 if (InputVector.getValueType() != MVT::v4i32)
16583 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16584 // single use which is a sign-extend or zero-extend, and all elements are
16586 SmallVector<SDNode *, 4> Uses;
16587 unsigned ExtractedElements = 0;
16588 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16589 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16590 if (UI.getUse().getResNo() != InputVector.getResNo())
16593 SDNode *Extract = *UI;
16594 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16597 if (Extract->getValueType(0) != MVT::i32)
16599 if (!Extract->hasOneUse())
16601 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16602 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16604 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16607 // Record which element was extracted.
16608 ExtractedElements |=
16609 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16611 Uses.push_back(Extract);
16614 // If not all the elements were used, this may not be worthwhile.
16615 if (ExtractedElements != 15)
16618 // Ok, we've now decided to do the transformation.
16619 SDLoc dl(InputVector);
16621 // Store the value to a temporary stack slot.
16622 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16623 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16624 MachinePointerInfo(), false, false, 0);
16626 // Replace each use (extract) with a load of the appropriate element.
16627 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16628 UE = Uses.end(); UI != UE; ++UI) {
16629 SDNode *Extract = *UI;
16631 // cOMpute the element's address.
16632 SDValue Idx = Extract->getOperand(1);
16634 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16635 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16636 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16637 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16639 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16640 StackPtr, OffsetVal);
16642 // Load the scalar.
16643 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16644 ScalarAddr, MachinePointerInfo(),
16645 false, false, false, 0);
16647 // Replace the exact with the load.
16648 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16651 // The replacement was made in place; don't return anything.
16655 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16656 static std::pair<unsigned, bool>
16657 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16658 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16659 if (!VT.isVector())
16660 return std::make_pair(0, false);
16662 bool NeedSplit = false;
16663 switch (VT.getSimpleVT().SimpleTy) {
16664 default: return std::make_pair(0, false);
16668 if (!Subtarget->hasAVX2())
16670 if (!Subtarget->hasAVX())
16671 return std::make_pair(0, false);
16676 if (!Subtarget->hasSSE2())
16677 return std::make_pair(0, false);
16680 // SSE2 has only a small subset of the operations.
16681 bool hasUnsigned = Subtarget->hasSSE41() ||
16682 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16683 bool hasSigned = Subtarget->hasSSE41() ||
16684 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16686 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16689 // Check for x CC y ? x : y.
16690 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16691 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16696 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16699 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16702 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16705 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16707 // Check for x CC y ? y : x -- a min/max with reversed arms.
16708 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16709 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16714 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16717 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16720 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16723 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16727 return std::make_pair(Opc, NeedSplit);
16730 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16732 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16733 TargetLowering::DAGCombinerInfo &DCI,
16734 const X86Subtarget *Subtarget) {
16736 SDValue Cond = N->getOperand(0);
16737 // Get the LHS/RHS of the select.
16738 SDValue LHS = N->getOperand(1);
16739 SDValue RHS = N->getOperand(2);
16740 EVT VT = LHS.getValueType();
16741 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16743 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16744 // instructions match the semantics of the common C idiom x<y?x:y but not
16745 // x<=y?x:y, because of how they handle negative zero (which can be
16746 // ignored in unsafe-math mode).
16747 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16748 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16749 (Subtarget->hasSSE2() ||
16750 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16751 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16753 unsigned Opcode = 0;
16754 // Check for x CC y ? x : y.
16755 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16756 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16760 // Converting this to a min would handle NaNs incorrectly, and swapping
16761 // the operands would cause it to handle comparisons between positive
16762 // and negative zero incorrectly.
16763 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16764 if (!DAG.getTarget().Options.UnsafeFPMath &&
16765 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16767 std::swap(LHS, RHS);
16769 Opcode = X86ISD::FMIN;
16772 // Converting this to a min would handle comparisons between positive
16773 // and negative zero incorrectly.
16774 if (!DAG.getTarget().Options.UnsafeFPMath &&
16775 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16777 Opcode = X86ISD::FMIN;
16780 // Converting this to a min would handle both negative zeros and NaNs
16781 // incorrectly, but we can swap the operands to fix both.
16782 std::swap(LHS, RHS);
16786 Opcode = X86ISD::FMIN;
16790 // Converting this to a max would handle comparisons between positive
16791 // and negative zero incorrectly.
16792 if (!DAG.getTarget().Options.UnsafeFPMath &&
16793 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16795 Opcode = X86ISD::FMAX;
16798 // Converting this to a max would handle NaNs incorrectly, and swapping
16799 // the operands would cause it to handle comparisons between positive
16800 // and negative zero incorrectly.
16801 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16802 if (!DAG.getTarget().Options.UnsafeFPMath &&
16803 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16805 std::swap(LHS, RHS);
16807 Opcode = X86ISD::FMAX;
16810 // Converting this to a max would handle both negative zeros and NaNs
16811 // incorrectly, but we can swap the operands to fix both.
16812 std::swap(LHS, RHS);
16816 Opcode = X86ISD::FMAX;
16819 // Check for x CC y ? y : x -- a min/max with reversed arms.
16820 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16821 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16825 // Converting this to a min would handle comparisons between positive
16826 // and negative zero incorrectly, and swapping the operands would
16827 // cause it to handle NaNs incorrectly.
16828 if (!DAG.getTarget().Options.UnsafeFPMath &&
16829 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16830 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16832 std::swap(LHS, RHS);
16834 Opcode = X86ISD::FMIN;
16837 // Converting this to a min would handle NaNs incorrectly.
16838 if (!DAG.getTarget().Options.UnsafeFPMath &&
16839 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16841 Opcode = X86ISD::FMIN;
16844 // Converting this to a min would handle both negative zeros and NaNs
16845 // incorrectly, but we can swap the operands to fix both.
16846 std::swap(LHS, RHS);
16850 Opcode = X86ISD::FMIN;
16854 // Converting this to a max would handle NaNs incorrectly.
16855 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16857 Opcode = X86ISD::FMAX;
16860 // Converting this to a max would handle comparisons between positive
16861 // and negative zero incorrectly, and swapping the operands would
16862 // cause it to handle NaNs incorrectly.
16863 if (!DAG.getTarget().Options.UnsafeFPMath &&
16864 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16865 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16867 std::swap(LHS, RHS);
16869 Opcode = X86ISD::FMAX;
16872 // Converting this to a max would handle both negative zeros and NaNs
16873 // incorrectly, but we can swap the operands to fix both.
16874 std::swap(LHS, RHS);
16878 Opcode = X86ISD::FMAX;
16884 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16887 EVT CondVT = Cond.getValueType();
16888 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
16889 CondVT.getVectorElementType() == MVT::i1) {
16890 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16891 // lowering on AVX-512. In this case we convert it to
16892 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16893 // The same situation for all 128 and 256-bit vectors of i8 and i16
16894 EVT OpVT = LHS.getValueType();
16895 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16896 (OpVT.getVectorElementType() == MVT::i8 ||
16897 OpVT.getVectorElementType() == MVT::i16)) {
16898 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16899 DCI.AddToWorklist(Cond.getNode());
16900 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16903 // If this is a select between two integer constants, try to do some
16905 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16906 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16907 // Don't do this for crazy integer types.
16908 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16909 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16910 // so that TrueC (the true value) is larger than FalseC.
16911 bool NeedsCondInvert = false;
16913 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16914 // Efficiently invertible.
16915 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16916 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16917 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16918 NeedsCondInvert = true;
16919 std::swap(TrueC, FalseC);
16922 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16923 if (FalseC->getAPIntValue() == 0 &&
16924 TrueC->getAPIntValue().isPowerOf2()) {
16925 if (NeedsCondInvert) // Invert the condition if needed.
16926 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16927 DAG.getConstant(1, Cond.getValueType()));
16929 // Zero extend the condition if needed.
16930 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16932 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16933 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16934 DAG.getConstant(ShAmt, MVT::i8));
16937 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16938 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16939 if (NeedsCondInvert) // Invert the condition if needed.
16940 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16941 DAG.getConstant(1, Cond.getValueType()));
16943 // Zero extend the condition if needed.
16944 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16945 FalseC->getValueType(0), Cond);
16946 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16947 SDValue(FalseC, 0));
16950 // Optimize cases that will turn into an LEA instruction. This requires
16951 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16952 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16953 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16954 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16956 bool isFastMultiplier = false;
16958 switch ((unsigned char)Diff) {
16960 case 1: // result = add base, cond
16961 case 2: // result = lea base( , cond*2)
16962 case 3: // result = lea base(cond, cond*2)
16963 case 4: // result = lea base( , cond*4)
16964 case 5: // result = lea base(cond, cond*4)
16965 case 8: // result = lea base( , cond*8)
16966 case 9: // result = lea base(cond, cond*8)
16967 isFastMultiplier = true;
16972 if (isFastMultiplier) {
16973 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16974 if (NeedsCondInvert) // Invert the condition if needed.
16975 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16976 DAG.getConstant(1, Cond.getValueType()));
16978 // Zero extend the condition if needed.
16979 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16981 // Scale the condition by the difference.
16983 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16984 DAG.getConstant(Diff, Cond.getValueType()));
16986 // Add the base if non-zero.
16987 if (FalseC->getAPIntValue() != 0)
16988 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16989 SDValue(FalseC, 0));
16996 // Canonicalize max and min:
16997 // (x > y) ? x : y -> (x >= y) ? x : y
16998 // (x < y) ? x : y -> (x <= y) ? x : y
16999 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
17000 // the need for an extra compare
17001 // against zero. e.g.
17002 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
17004 // testl %edi, %edi
17006 // cmovgl %edi, %eax
17010 // cmovsl %eax, %edi
17011 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
17012 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17013 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17014 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17019 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
17020 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
17021 Cond.getOperand(0), Cond.getOperand(1), NewCC);
17022 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
17027 // Early exit check
17028 if (!TLI.isTypeLegal(VT))
17031 // Match VSELECTs into subs with unsigned saturation.
17032 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17033 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
17034 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
17035 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
17036 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17038 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
17039 // left side invert the predicate to simplify logic below.
17041 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
17043 CC = ISD::getSetCCInverse(CC, true);
17044 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
17048 if (Other.getNode() && Other->getNumOperands() == 2 &&
17049 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
17050 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
17051 SDValue CondRHS = Cond->getOperand(1);
17053 // Look for a general sub with unsigned saturation first.
17054 // x >= y ? x-y : 0 --> subus x, y
17055 // x > y ? x-y : 0 --> subus x, y
17056 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
17057 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
17058 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17060 // If the RHS is a constant we have to reverse the const canonicalization.
17061 // x > C-1 ? x+-C : 0 --> subus x, C
17062 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
17063 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
17064 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17065 if (CondRHS.getConstantOperandVal(0) == -A-1)
17066 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
17067 DAG.getConstant(-A, VT));
17070 // Another special case: If C was a sign bit, the sub has been
17071 // canonicalized into a xor.
17072 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
17073 // it's safe to decanonicalize the xor?
17074 // x s< 0 ? x^C : 0 --> subus x, C
17075 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
17076 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
17077 isSplatVector(OpRHS.getNode())) {
17078 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17080 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17085 // Try to match a min/max vector operation.
17086 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17087 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17088 unsigned Opc = ret.first;
17089 bool NeedSplit = ret.second;
17091 if (Opc && NeedSplit) {
17092 unsigned NumElems = VT.getVectorNumElements();
17093 // Extract the LHS vectors
17094 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17095 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17097 // Extract the RHS vectors
17098 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17099 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17101 // Create min/max for each subvector
17102 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17103 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17105 // Merge the result
17106 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17108 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17111 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17112 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17113 // Check if SETCC has already been promoted
17114 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17115 // Check that condition value type matches vselect operand type
17118 assert(Cond.getValueType().isVector() &&
17119 "vector select expects a vector selector!");
17121 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17122 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17124 if (!TValIsAllOnes && !FValIsAllZeros) {
17125 // Try invert the condition if true value is not all 1s and false value
17127 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17128 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17130 if (TValIsAllZeros || FValIsAllOnes) {
17131 SDValue CC = Cond.getOperand(2);
17132 ISD::CondCode NewCC =
17133 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17134 Cond.getOperand(0).getValueType().isInteger());
17135 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17136 std::swap(LHS, RHS);
17137 TValIsAllOnes = FValIsAllOnes;
17138 FValIsAllZeros = TValIsAllZeros;
17142 if (TValIsAllOnes || FValIsAllZeros) {
17145 if (TValIsAllOnes && FValIsAllZeros)
17147 else if (TValIsAllOnes)
17148 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17149 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17150 else if (FValIsAllZeros)
17151 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17152 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17154 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17158 // If we know that this node is legal then we know that it is going to be
17159 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17160 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17161 // to simplify previous instructions.
17162 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17163 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17164 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17166 // Don't optimize vector selects that map to mask-registers.
17170 // Check all uses of that condition operand to check whether it will be
17171 // consumed by non-BLEND instructions, which may depend on all bits are set
17173 for (SDNode::use_iterator I = Cond->use_begin(),
17174 E = Cond->use_end(); I != E; ++I)
17175 if (I->getOpcode() != ISD::VSELECT)
17176 // TODO: Add other opcodes eventually lowered into BLEND.
17179 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17180 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17182 APInt KnownZero, KnownOne;
17183 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17184 DCI.isBeforeLegalizeOps());
17185 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17186 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17187 DCI.CommitTargetLoweringOpt(TLO);
17193 // Check whether a boolean test is testing a boolean value generated by
17194 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17197 // Simplify the following patterns:
17198 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17199 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17200 // to (Op EFLAGS Cond)
17202 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17203 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17204 // to (Op EFLAGS !Cond)
17206 // where Op could be BRCOND or CMOV.
17208 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17209 // Quit if not CMP and SUB with its value result used.
17210 if (Cmp.getOpcode() != X86ISD::CMP &&
17211 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17214 // Quit if not used as a boolean value.
17215 if (CC != X86::COND_E && CC != X86::COND_NE)
17218 // Check CMP operands. One of them should be 0 or 1 and the other should be
17219 // an SetCC or extended from it.
17220 SDValue Op1 = Cmp.getOperand(0);
17221 SDValue Op2 = Cmp.getOperand(1);
17224 const ConstantSDNode* C = 0;
17225 bool needOppositeCond = (CC == X86::COND_E);
17226 bool checkAgainstTrue = false; // Is it a comparison against 1?
17228 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17230 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17232 else // Quit if all operands are not constants.
17235 if (C->getZExtValue() == 1) {
17236 needOppositeCond = !needOppositeCond;
17237 checkAgainstTrue = true;
17238 } else if (C->getZExtValue() != 0)
17239 // Quit if the constant is neither 0 or 1.
17242 bool truncatedToBoolWithAnd = false;
17243 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17244 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17245 SetCC.getOpcode() == ISD::TRUNCATE ||
17246 SetCC.getOpcode() == ISD::AND) {
17247 if (SetCC.getOpcode() == ISD::AND) {
17249 ConstantSDNode *CS;
17250 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17251 CS->getZExtValue() == 1)
17253 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17254 CS->getZExtValue() == 1)
17258 SetCC = SetCC.getOperand(OpIdx);
17259 truncatedToBoolWithAnd = true;
17261 SetCC = SetCC.getOperand(0);
17264 switch (SetCC.getOpcode()) {
17265 case X86ISD::SETCC_CARRY:
17266 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17267 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17268 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17269 // truncated to i1 using 'and'.
17270 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17272 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17273 "Invalid use of SETCC_CARRY!");
17275 case X86ISD::SETCC:
17276 // Set the condition code or opposite one if necessary.
17277 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17278 if (needOppositeCond)
17279 CC = X86::GetOppositeBranchCondition(CC);
17280 return SetCC.getOperand(1);
17281 case X86ISD::CMOV: {
17282 // Check whether false/true value has canonical one, i.e. 0 or 1.
17283 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17284 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17285 // Quit if true value is not a constant.
17288 // Quit if false value is not a constant.
17290 SDValue Op = SetCC.getOperand(0);
17291 // Skip 'zext' or 'trunc' node.
17292 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17293 Op.getOpcode() == ISD::TRUNCATE)
17294 Op = Op.getOperand(0);
17295 // A special case for rdrand/rdseed, where 0 is set if false cond is
17297 if ((Op.getOpcode() != X86ISD::RDRAND &&
17298 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17301 // Quit if false value is not the constant 0 or 1.
17302 bool FValIsFalse = true;
17303 if (FVal && FVal->getZExtValue() != 0) {
17304 if (FVal->getZExtValue() != 1)
17306 // If FVal is 1, opposite cond is needed.
17307 needOppositeCond = !needOppositeCond;
17308 FValIsFalse = false;
17310 // Quit if TVal is not the constant opposite of FVal.
17311 if (FValIsFalse && TVal->getZExtValue() != 1)
17313 if (!FValIsFalse && TVal->getZExtValue() != 0)
17315 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17316 if (needOppositeCond)
17317 CC = X86::GetOppositeBranchCondition(CC);
17318 return SetCC.getOperand(3);
17325 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17326 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17327 TargetLowering::DAGCombinerInfo &DCI,
17328 const X86Subtarget *Subtarget) {
17331 // If the flag operand isn't dead, don't touch this CMOV.
17332 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17335 SDValue FalseOp = N->getOperand(0);
17336 SDValue TrueOp = N->getOperand(1);
17337 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17338 SDValue Cond = N->getOperand(3);
17340 if (CC == X86::COND_E || CC == X86::COND_NE) {
17341 switch (Cond.getOpcode()) {
17345 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17346 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17347 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17353 Flags = checkBoolTestSetCCCombine(Cond, CC);
17354 if (Flags.getNode() &&
17355 // Extra check as FCMOV only supports a subset of X86 cond.
17356 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17357 SDValue Ops[] = { FalseOp, TrueOp,
17358 DAG.getConstant(CC, MVT::i8), Flags };
17359 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17360 Ops, array_lengthof(Ops));
17363 // If this is a select between two integer constants, try to do some
17364 // optimizations. Note that the operands are ordered the opposite of SELECT
17366 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17367 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17368 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17369 // larger than FalseC (the false value).
17370 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17371 CC = X86::GetOppositeBranchCondition(CC);
17372 std::swap(TrueC, FalseC);
17373 std::swap(TrueOp, FalseOp);
17376 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17377 // This is efficient for any integer data type (including i8/i16) and
17379 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17380 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17381 DAG.getConstant(CC, MVT::i8), Cond);
17383 // Zero extend the condition if needed.
17384 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17386 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17387 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17388 DAG.getConstant(ShAmt, MVT::i8));
17389 if (N->getNumValues() == 2) // Dead flag value?
17390 return DCI.CombineTo(N, Cond, SDValue());
17394 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17395 // for any integer data type, including i8/i16.
17396 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17397 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17398 DAG.getConstant(CC, MVT::i8), Cond);
17400 // Zero extend the condition if needed.
17401 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17402 FalseC->getValueType(0), Cond);
17403 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17404 SDValue(FalseC, 0));
17406 if (N->getNumValues() == 2) // Dead flag value?
17407 return DCI.CombineTo(N, Cond, SDValue());
17411 // Optimize cases that will turn into an LEA instruction. This requires
17412 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17413 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17414 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17415 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17417 bool isFastMultiplier = false;
17419 switch ((unsigned char)Diff) {
17421 case 1: // result = add base, cond
17422 case 2: // result = lea base( , cond*2)
17423 case 3: // result = lea base(cond, cond*2)
17424 case 4: // result = lea base( , cond*4)
17425 case 5: // result = lea base(cond, cond*4)
17426 case 8: // result = lea base( , cond*8)
17427 case 9: // result = lea base(cond, cond*8)
17428 isFastMultiplier = true;
17433 if (isFastMultiplier) {
17434 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17435 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17436 DAG.getConstant(CC, MVT::i8), Cond);
17437 // Zero extend the condition if needed.
17438 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17440 // Scale the condition by the difference.
17442 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17443 DAG.getConstant(Diff, Cond.getValueType()));
17445 // Add the base if non-zero.
17446 if (FalseC->getAPIntValue() != 0)
17447 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17448 SDValue(FalseC, 0));
17449 if (N->getNumValues() == 2) // Dead flag value?
17450 return DCI.CombineTo(N, Cond, SDValue());
17457 // Handle these cases:
17458 // (select (x != c), e, c) -> select (x != c), e, x),
17459 // (select (x == c), c, e) -> select (x == c), x, e)
17460 // where the c is an integer constant, and the "select" is the combination
17461 // of CMOV and CMP.
17463 // The rationale for this change is that the conditional-move from a constant
17464 // needs two instructions, however, conditional-move from a register needs
17465 // only one instruction.
17467 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17468 // some instruction-combining opportunities. This opt needs to be
17469 // postponed as late as possible.
17471 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17472 // the DCI.xxxx conditions are provided to postpone the optimization as
17473 // late as possible.
17475 ConstantSDNode *CmpAgainst = 0;
17476 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17477 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17478 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17480 if (CC == X86::COND_NE &&
17481 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17482 CC = X86::GetOppositeBranchCondition(CC);
17483 std::swap(TrueOp, FalseOp);
17486 if (CC == X86::COND_E &&
17487 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17488 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17489 DAG.getConstant(CC, MVT::i8), Cond };
17490 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17491 array_lengthof(Ops));
17499 /// PerformMulCombine - Optimize a single multiply with constant into two
17500 /// in order to implement it with two cheaper instructions, e.g.
17501 /// LEA + SHL, LEA + LEA.
17502 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17503 TargetLowering::DAGCombinerInfo &DCI) {
17504 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17507 EVT VT = N->getValueType(0);
17508 if (VT != MVT::i64)
17511 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17514 uint64_t MulAmt = C->getZExtValue();
17515 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17518 uint64_t MulAmt1 = 0;
17519 uint64_t MulAmt2 = 0;
17520 if ((MulAmt % 9) == 0) {
17522 MulAmt2 = MulAmt / 9;
17523 } else if ((MulAmt % 5) == 0) {
17525 MulAmt2 = MulAmt / 5;
17526 } else if ((MulAmt % 3) == 0) {
17528 MulAmt2 = MulAmt / 3;
17531 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17534 if (isPowerOf2_64(MulAmt2) &&
17535 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17536 // If second multiplifer is pow2, issue it first. We want the multiply by
17537 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17539 std::swap(MulAmt1, MulAmt2);
17542 if (isPowerOf2_64(MulAmt1))
17543 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17544 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17546 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17547 DAG.getConstant(MulAmt1, VT));
17549 if (isPowerOf2_64(MulAmt2))
17550 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17551 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17553 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17554 DAG.getConstant(MulAmt2, VT));
17556 // Do not add new nodes to DAG combiner worklist.
17557 DCI.CombineTo(N, NewMul, false);
17562 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17563 SDValue N0 = N->getOperand(0);
17564 SDValue N1 = N->getOperand(1);
17565 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17566 EVT VT = N0.getValueType();
17568 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17569 // since the result of setcc_c is all zero's or all ones.
17570 if (VT.isInteger() && !VT.isVector() &&
17571 N1C && N0.getOpcode() == ISD::AND &&
17572 N0.getOperand(1).getOpcode() == ISD::Constant) {
17573 SDValue N00 = N0.getOperand(0);
17574 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17575 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17576 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17577 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17578 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17579 APInt ShAmt = N1C->getAPIntValue();
17580 Mask = Mask.shl(ShAmt);
17582 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17583 N00, DAG.getConstant(Mask, VT));
17587 // Hardware support for vector shifts is sparse which makes us scalarize the
17588 // vector operations in many cases. Also, on sandybridge ADD is faster than
17590 // (shl V, 1) -> add V,V
17591 if (isSplatVector(N1.getNode())) {
17592 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17593 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17594 // We shift all of the values by one. In many cases we do not have
17595 // hardware support for this operation. This is better expressed as an ADD
17597 if (N1C && (1 == N1C->getZExtValue())) {
17598 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17605 /// \brief Returns a vector of 0s if the node in input is a vector logical
17606 /// shift by a constant amount which is known to be bigger than or equal
17607 /// to the vector element size in bits.
17608 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17609 const X86Subtarget *Subtarget) {
17610 EVT VT = N->getValueType(0);
17612 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17613 (!Subtarget->hasInt256() ||
17614 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17617 SDValue Amt = N->getOperand(1);
17619 if (isSplatVector(Amt.getNode())) {
17620 SDValue SclrAmt = Amt->getOperand(0);
17621 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17622 APInt ShiftAmt = C->getAPIntValue();
17623 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17625 // SSE2/AVX2 logical shifts always return a vector of 0s
17626 // if the shift amount is bigger than or equal to
17627 // the element size. The constant shift amount will be
17628 // encoded as a 8-bit immediate.
17629 if (ShiftAmt.trunc(8).uge(MaxAmount))
17630 return getZeroVector(VT, Subtarget, DAG, DL);
17637 /// PerformShiftCombine - Combine shifts.
17638 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17639 TargetLowering::DAGCombinerInfo &DCI,
17640 const X86Subtarget *Subtarget) {
17641 if (N->getOpcode() == ISD::SHL) {
17642 SDValue V = PerformSHLCombine(N, DAG);
17643 if (V.getNode()) return V;
17646 if (N->getOpcode() != ISD::SRA) {
17647 // Try to fold this logical shift into a zero vector.
17648 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17649 if (V.getNode()) return V;
17655 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17656 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17657 // and friends. Likewise for OR -> CMPNEQSS.
17658 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17659 TargetLowering::DAGCombinerInfo &DCI,
17660 const X86Subtarget *Subtarget) {
17663 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17664 // we're requiring SSE2 for both.
17665 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17666 SDValue N0 = N->getOperand(0);
17667 SDValue N1 = N->getOperand(1);
17668 SDValue CMP0 = N0->getOperand(1);
17669 SDValue CMP1 = N1->getOperand(1);
17672 // The SETCCs should both refer to the same CMP.
17673 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17676 SDValue CMP00 = CMP0->getOperand(0);
17677 SDValue CMP01 = CMP0->getOperand(1);
17678 EVT VT = CMP00.getValueType();
17680 if (VT == MVT::f32 || VT == MVT::f64) {
17681 bool ExpectingFlags = false;
17682 // Check for any users that want flags:
17683 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17684 !ExpectingFlags && UI != UE; ++UI)
17685 switch (UI->getOpcode()) {
17690 ExpectingFlags = true;
17692 case ISD::CopyToReg:
17693 case ISD::SIGN_EXTEND:
17694 case ISD::ZERO_EXTEND:
17695 case ISD::ANY_EXTEND:
17699 if (!ExpectingFlags) {
17700 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17701 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17703 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17704 X86::CondCode tmp = cc0;
17709 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17710 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17711 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17712 // FIXME: need symbolic constants for these magic numbers.
17713 // See X86ATTInstPrinter.cpp:printSSECC().
17714 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17715 if (Subtarget->hasAVX512()) {
17716 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
17717 CMP01, DAG.getConstant(x86cc, MVT::i8));
17718 if (N->getValueType(0) != MVT::i1)
17719 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
17723 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
17724 CMP00.getValueType(), CMP00, CMP01,
17725 DAG.getConstant(x86cc, MVT::i8));
17726 MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
17727 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
17729 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
17730 DAG.getConstant(1, IntVT));
17731 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17732 return OneBitOfTruth;
17740 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17741 /// so it can be folded inside ANDNP.
17742 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17743 EVT VT = N->getValueType(0);
17745 // Match direct AllOnes for 128 and 256-bit vectors
17746 if (ISD::isBuildVectorAllOnes(N))
17749 // Look through a bit convert.
17750 if (N->getOpcode() == ISD::BITCAST)
17751 N = N->getOperand(0).getNode();
17753 // Sometimes the operand may come from a insert_subvector building a 256-bit
17755 if (VT.is256BitVector() &&
17756 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17757 SDValue V1 = N->getOperand(0);
17758 SDValue V2 = N->getOperand(1);
17760 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17761 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17762 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17763 ISD::isBuildVectorAllOnes(V2.getNode()))
17770 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17771 // register. In most cases we actually compare or select YMM-sized registers
17772 // and mixing the two types creates horrible code. This method optimizes
17773 // some of the transition sequences.
17774 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17775 TargetLowering::DAGCombinerInfo &DCI,
17776 const X86Subtarget *Subtarget) {
17777 EVT VT = N->getValueType(0);
17778 if (!VT.is256BitVector())
17781 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17782 N->getOpcode() == ISD::ZERO_EXTEND ||
17783 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17785 SDValue Narrow = N->getOperand(0);
17786 EVT NarrowVT = Narrow->getValueType(0);
17787 if (!NarrowVT.is128BitVector())
17790 if (Narrow->getOpcode() != ISD::XOR &&
17791 Narrow->getOpcode() != ISD::AND &&
17792 Narrow->getOpcode() != ISD::OR)
17795 SDValue N0 = Narrow->getOperand(0);
17796 SDValue N1 = Narrow->getOperand(1);
17799 // The Left side has to be a trunc.
17800 if (N0.getOpcode() != ISD::TRUNCATE)
17803 // The type of the truncated inputs.
17804 EVT WideVT = N0->getOperand(0)->getValueType(0);
17808 // The right side has to be a 'trunc' or a constant vector.
17809 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17810 bool RHSConst = (isSplatVector(N1.getNode()) &&
17811 isa<ConstantSDNode>(N1->getOperand(0)));
17812 if (!RHSTrunc && !RHSConst)
17815 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17817 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17820 // Set N0 and N1 to hold the inputs to the new wide operation.
17821 N0 = N0->getOperand(0);
17823 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17824 N1->getOperand(0));
17825 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17826 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17827 } else if (RHSTrunc) {
17828 N1 = N1->getOperand(0);
17831 // Generate the wide operation.
17832 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17833 unsigned Opcode = N->getOpcode();
17835 case ISD::ANY_EXTEND:
17837 case ISD::ZERO_EXTEND: {
17838 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17839 APInt Mask = APInt::getAllOnesValue(InBits);
17840 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17841 return DAG.getNode(ISD::AND, DL, VT,
17842 Op, DAG.getConstant(Mask, VT));
17844 case ISD::SIGN_EXTEND:
17845 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17846 Op, DAG.getValueType(NarrowVT));
17848 llvm_unreachable("Unexpected opcode");
17852 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17853 TargetLowering::DAGCombinerInfo &DCI,
17854 const X86Subtarget *Subtarget) {
17855 EVT VT = N->getValueType(0);
17856 if (DCI.isBeforeLegalizeOps())
17859 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17863 // Create BLSI, BLSR, and BZHI instructions
17864 // BLSI is X & (-X)
17865 // BLSR is X & (X-1)
17866 // BZHI is X & ((1 << Y) - 1)
17867 // BEXTR is ((X >> imm) & (2**size-1))
17868 if (VT == MVT::i32 || VT == MVT::i64) {
17869 SDValue N0 = N->getOperand(0);
17870 SDValue N1 = N->getOperand(1);
17873 if (Subtarget->hasBMI()) {
17874 // Check LHS for neg
17875 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17876 isZero(N0.getOperand(0)))
17877 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17879 // Check RHS for neg
17880 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17881 isZero(N1.getOperand(0)))
17882 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17884 // Check LHS for X-1
17885 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17886 isAllOnes(N0.getOperand(1)))
17887 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17889 // Check RHS for X-1
17890 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17891 isAllOnes(N1.getOperand(1)))
17892 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17895 if (Subtarget->hasBMI2()) {
17896 // Check for (and (add (shl 1, Y), -1), X)
17897 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17898 SDValue N00 = N0.getOperand(0);
17899 if (N00.getOpcode() == ISD::SHL) {
17900 SDValue N001 = N00.getOperand(1);
17901 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17902 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17903 if (C && C->getZExtValue() == 1)
17904 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17908 // Check for (and X, (add (shl 1, Y), -1))
17909 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17910 SDValue N10 = N1.getOperand(0);
17911 if (N10.getOpcode() == ISD::SHL) {
17912 SDValue N101 = N10.getOperand(1);
17913 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17914 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17915 if (C && C->getZExtValue() == 1)
17916 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17921 // Check for BEXTR.
17922 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17923 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17924 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17925 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17926 if (MaskNode && ShiftNode) {
17927 uint64_t Mask = MaskNode->getZExtValue();
17928 uint64_t Shift = ShiftNode->getZExtValue();
17929 if (isMask_64(Mask)) {
17930 uint64_t MaskSize = CountPopulation_64(Mask);
17931 if (Shift + MaskSize <= VT.getSizeInBits())
17932 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17933 DAG.getConstant(Shift | (MaskSize << 8), VT));
17941 // Want to form ANDNP nodes:
17942 // 1) In the hopes of then easily combining them with OR and AND nodes
17943 // to form PBLEND/PSIGN.
17944 // 2) To match ANDN packed intrinsics
17945 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17948 SDValue N0 = N->getOperand(0);
17949 SDValue N1 = N->getOperand(1);
17952 // Check LHS for vnot
17953 if (N0.getOpcode() == ISD::XOR &&
17954 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17955 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17956 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17958 // Check RHS for vnot
17959 if (N1.getOpcode() == ISD::XOR &&
17960 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17961 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17962 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17967 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17968 TargetLowering::DAGCombinerInfo &DCI,
17969 const X86Subtarget *Subtarget) {
17970 EVT VT = N->getValueType(0);
17971 if (DCI.isBeforeLegalizeOps())
17974 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17978 SDValue N0 = N->getOperand(0);
17979 SDValue N1 = N->getOperand(1);
17981 // look for psign/blend
17982 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17983 if (!Subtarget->hasSSSE3() ||
17984 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17987 // Canonicalize pandn to RHS
17988 if (N0.getOpcode() == X86ISD::ANDNP)
17990 // or (and (m, y), (pandn m, x))
17991 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17992 SDValue Mask = N1.getOperand(0);
17993 SDValue X = N1.getOperand(1);
17995 if (N0.getOperand(0) == Mask)
17996 Y = N0.getOperand(1);
17997 if (N0.getOperand(1) == Mask)
17998 Y = N0.getOperand(0);
18000 // Check to see if the mask appeared in both the AND and ANDNP and
18004 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
18005 // Look through mask bitcast.
18006 if (Mask.getOpcode() == ISD::BITCAST)
18007 Mask = Mask.getOperand(0);
18008 if (X.getOpcode() == ISD::BITCAST)
18009 X = X.getOperand(0);
18010 if (Y.getOpcode() == ISD::BITCAST)
18011 Y = Y.getOperand(0);
18013 EVT MaskVT = Mask.getValueType();
18015 // Validate that the Mask operand is a vector sra node.
18016 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
18017 // there is no psrai.b
18018 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
18019 unsigned SraAmt = ~0;
18020 if (Mask.getOpcode() == ISD::SRA) {
18021 SDValue Amt = Mask.getOperand(1);
18022 if (isSplatVector(Amt.getNode())) {
18023 SDValue SclrAmt = Amt->getOperand(0);
18024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
18025 SraAmt = C->getZExtValue();
18027 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
18028 SDValue SraC = Mask.getOperand(1);
18029 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
18031 if ((SraAmt + 1) != EltBits)
18036 // Now we know we at least have a plendvb with the mask val. See if
18037 // we can form a psignb/w/d.
18038 // psign = x.type == y.type == mask.type && y = sub(0, x);
18039 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
18040 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
18041 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
18042 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
18043 "Unsupported VT for PSIGN");
18044 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
18045 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18047 // PBLENDVB only available on SSE 4.1
18048 if (!Subtarget->hasSSE41())
18051 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
18053 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
18054 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
18055 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
18056 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
18057 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18061 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
18064 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
18065 MachineFunction &MF = DAG.getMachineFunction();
18066 bool OptForSize = MF.getFunction()->getAttributes().
18067 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
18069 // SHLD/SHRD instructions have lower register pressure, but on some
18070 // platforms they have higher latency than the equivalent
18071 // series of shifts/or that would otherwise be generated.
18072 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
18073 // have higher latencies and we are not optimizing for size.
18074 if (!OptForSize && Subtarget->isSHLDSlow())
18077 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
18079 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
18081 if (!N0.hasOneUse() || !N1.hasOneUse())
18084 SDValue ShAmt0 = N0.getOperand(1);
18085 if (ShAmt0.getValueType() != MVT::i8)
18087 SDValue ShAmt1 = N1.getOperand(1);
18088 if (ShAmt1.getValueType() != MVT::i8)
18090 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18091 ShAmt0 = ShAmt0.getOperand(0);
18092 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18093 ShAmt1 = ShAmt1.getOperand(0);
18096 unsigned Opc = X86ISD::SHLD;
18097 SDValue Op0 = N0.getOperand(0);
18098 SDValue Op1 = N1.getOperand(0);
18099 if (ShAmt0.getOpcode() == ISD::SUB) {
18100 Opc = X86ISD::SHRD;
18101 std::swap(Op0, Op1);
18102 std::swap(ShAmt0, ShAmt1);
18105 unsigned Bits = VT.getSizeInBits();
18106 if (ShAmt1.getOpcode() == ISD::SUB) {
18107 SDValue Sum = ShAmt1.getOperand(0);
18108 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18109 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18110 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18111 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18112 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18113 return DAG.getNode(Opc, DL, VT,
18115 DAG.getNode(ISD::TRUNCATE, DL,
18118 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18119 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18121 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18122 return DAG.getNode(Opc, DL, VT,
18123 N0.getOperand(0), N1.getOperand(0),
18124 DAG.getNode(ISD::TRUNCATE, DL,
18131 // Generate NEG and CMOV for integer abs.
18132 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18133 EVT VT = N->getValueType(0);
18135 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18136 // 8-bit integer abs to NEG and CMOV.
18137 if (VT.isInteger() && VT.getSizeInBits() == 8)
18140 SDValue N0 = N->getOperand(0);
18141 SDValue N1 = N->getOperand(1);
18144 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18145 // and change it to SUB and CMOV.
18146 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18147 N0.getOpcode() == ISD::ADD &&
18148 N0.getOperand(1) == N1 &&
18149 N1.getOpcode() == ISD::SRA &&
18150 N1.getOperand(0) == N0.getOperand(0))
18151 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18152 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18153 // Generate SUB & CMOV.
18154 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18155 DAG.getConstant(0, VT), N0.getOperand(0));
18157 SDValue Ops[] = { N0.getOperand(0), Neg,
18158 DAG.getConstant(X86::COND_GE, MVT::i8),
18159 SDValue(Neg.getNode(), 1) };
18160 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18161 Ops, array_lengthof(Ops));
18166 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18167 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18168 TargetLowering::DAGCombinerInfo &DCI,
18169 const X86Subtarget *Subtarget) {
18170 EVT VT = N->getValueType(0);
18171 if (DCI.isBeforeLegalizeOps())
18174 if (Subtarget->hasCMov()) {
18175 SDValue RV = performIntegerAbsCombine(N, DAG);
18180 // Try forming BMI if it is available.
18181 if (!Subtarget->hasBMI())
18184 if (VT != MVT::i32 && VT != MVT::i64)
18187 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
18189 // Create BLSMSK instructions by finding X ^ (X-1)
18190 SDValue N0 = N->getOperand(0);
18191 SDValue N1 = N->getOperand(1);
18194 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18195 isAllOnes(N0.getOperand(1)))
18196 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
18198 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18199 isAllOnes(N1.getOperand(1)))
18200 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
18205 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18206 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18207 TargetLowering::DAGCombinerInfo &DCI,
18208 const X86Subtarget *Subtarget) {
18209 LoadSDNode *Ld = cast<LoadSDNode>(N);
18210 EVT RegVT = Ld->getValueType(0);
18211 EVT MemVT = Ld->getMemoryVT();
18213 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18214 unsigned RegSz = RegVT.getSizeInBits();
18216 // On Sandybridge unaligned 256bit loads are inefficient.
18217 ISD::LoadExtType Ext = Ld->getExtensionType();
18218 unsigned Alignment = Ld->getAlignment();
18219 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18220 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18221 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18222 unsigned NumElems = RegVT.getVectorNumElements();
18226 SDValue Ptr = Ld->getBasePtr();
18227 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18229 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18231 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18232 Ld->getPointerInfo(), Ld->isVolatile(),
18233 Ld->isNonTemporal(), Ld->isInvariant(),
18235 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18236 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18237 Ld->getPointerInfo(), Ld->isVolatile(),
18238 Ld->isNonTemporal(), Ld->isInvariant(),
18239 std::min(16U, Alignment));
18240 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18242 Load2.getValue(1));
18244 SDValue NewVec = DAG.getUNDEF(RegVT);
18245 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18246 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18247 return DCI.CombineTo(N, NewVec, TF, true);
18250 // If this is a vector EXT Load then attempt to optimize it using a
18251 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18252 // expansion is still better than scalar code.
18253 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18254 // emit a shuffle and a arithmetic shift.
18255 // TODO: It is possible to support ZExt by zeroing the undef values
18256 // during the shuffle phase or after the shuffle.
18257 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18258 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18259 assert(MemVT != RegVT && "Cannot extend to the same type");
18260 assert(MemVT.isVector() && "Must load a vector from memory");
18262 unsigned NumElems = RegVT.getVectorNumElements();
18263 unsigned MemSz = MemVT.getSizeInBits();
18264 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18266 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18269 // All sizes must be a power of two.
18270 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18273 // Attempt to load the original value using scalar loads.
18274 // Find the largest scalar type that divides the total loaded size.
18275 MVT SclrLoadTy = MVT::i8;
18276 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18277 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18278 MVT Tp = (MVT::SimpleValueType)tp;
18279 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18284 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18285 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18287 SclrLoadTy = MVT::f64;
18289 // Calculate the number of scalar loads that we need to perform
18290 // in order to load our vector from memory.
18291 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18292 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18295 unsigned loadRegZize = RegSz;
18296 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18299 // Represent our vector as a sequence of elements which are the
18300 // largest scalar that we can load.
18301 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18302 loadRegZize/SclrLoadTy.getSizeInBits());
18304 // Represent the data using the same element type that is stored in
18305 // memory. In practice, we ''widen'' MemVT.
18307 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18308 loadRegZize/MemVT.getScalarType().getSizeInBits());
18310 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18311 "Invalid vector type");
18313 // We can't shuffle using an illegal type.
18314 if (!TLI.isTypeLegal(WideVecVT))
18317 SmallVector<SDValue, 8> Chains;
18318 SDValue Ptr = Ld->getBasePtr();
18319 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18320 TLI.getPointerTy());
18321 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18323 for (unsigned i = 0; i < NumLoads; ++i) {
18324 // Perform a single load.
18325 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18326 Ptr, Ld->getPointerInfo(),
18327 Ld->isVolatile(), Ld->isNonTemporal(),
18328 Ld->isInvariant(), Ld->getAlignment());
18329 Chains.push_back(ScalarLoad.getValue(1));
18330 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18331 // another round of DAGCombining.
18333 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18335 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18336 ScalarLoad, DAG.getIntPtrConstant(i));
18338 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18341 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18344 // Bitcast the loaded value to a vector of the original element type, in
18345 // the size of the target vector type.
18346 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18347 unsigned SizeRatio = RegSz/MemSz;
18349 if (Ext == ISD::SEXTLOAD) {
18350 // If we have SSE4.1 we can directly emit a VSEXT node.
18351 if (Subtarget->hasSSE41()) {
18352 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18353 return DCI.CombineTo(N, Sext, TF, true);
18356 // Otherwise we'll shuffle the small elements in the high bits of the
18357 // larger type and perform an arithmetic shift. If the shift is not legal
18358 // it's better to scalarize.
18359 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18362 // Redistribute the loaded elements into the different locations.
18363 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18364 for (unsigned i = 0; i != NumElems; ++i)
18365 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18367 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18368 DAG.getUNDEF(WideVecVT),
18371 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18373 // Build the arithmetic shift.
18374 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18375 MemVT.getVectorElementType().getSizeInBits();
18376 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18377 DAG.getConstant(Amt, RegVT));
18379 return DCI.CombineTo(N, Shuff, TF, true);
18382 // Redistribute the loaded elements into the different locations.
18383 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18384 for (unsigned i = 0; i != NumElems; ++i)
18385 ShuffleVec[i*SizeRatio] = i;
18387 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18388 DAG.getUNDEF(WideVecVT),
18391 // Bitcast to the requested type.
18392 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18393 // Replace the original load with the new sequence
18394 // and return the new chain.
18395 return DCI.CombineTo(N, Shuff, TF, true);
18401 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18402 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18403 const X86Subtarget *Subtarget) {
18404 StoreSDNode *St = cast<StoreSDNode>(N);
18405 EVT VT = St->getValue().getValueType();
18406 EVT StVT = St->getMemoryVT();
18408 SDValue StoredVal = St->getOperand(1);
18409 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18411 // If we are saving a concatenation of two XMM registers, perform two stores.
18412 // On Sandy Bridge, 256-bit memory operations are executed by two
18413 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18414 // memory operation.
18415 unsigned Alignment = St->getAlignment();
18416 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18417 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18418 StVT == VT && !IsAligned) {
18419 unsigned NumElems = VT.getVectorNumElements();
18423 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18424 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18426 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18427 SDValue Ptr0 = St->getBasePtr();
18428 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18430 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18431 St->getPointerInfo(), St->isVolatile(),
18432 St->isNonTemporal(), Alignment);
18433 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18434 St->getPointerInfo(), St->isVolatile(),
18435 St->isNonTemporal(),
18436 std::min(16U, Alignment));
18437 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18440 // Optimize trunc store (of multiple scalars) to shuffle and store.
18441 // First, pack all of the elements in one place. Next, store to memory
18442 // in fewer chunks.
18443 if (St->isTruncatingStore() && VT.isVector()) {
18444 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18445 unsigned NumElems = VT.getVectorNumElements();
18446 assert(StVT != VT && "Cannot truncate to the same type");
18447 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18448 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18450 // From, To sizes and ElemCount must be pow of two
18451 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18452 // We are going to use the original vector elt for storing.
18453 // Accumulated smaller vector elements must be a multiple of the store size.
18454 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18456 unsigned SizeRatio = FromSz / ToSz;
18458 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18460 // Create a type on which we perform the shuffle
18461 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18462 StVT.getScalarType(), NumElems*SizeRatio);
18464 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18466 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18467 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18468 for (unsigned i = 0; i != NumElems; ++i)
18469 ShuffleVec[i] = i * SizeRatio;
18471 // Can't shuffle using an illegal type.
18472 if (!TLI.isTypeLegal(WideVecVT))
18475 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18476 DAG.getUNDEF(WideVecVT),
18478 // At this point all of the data is stored at the bottom of the
18479 // register. We now need to save it to mem.
18481 // Find the largest store unit
18482 MVT StoreType = MVT::i8;
18483 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18484 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18485 MVT Tp = (MVT::SimpleValueType)tp;
18486 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18490 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18491 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18492 (64 <= NumElems * ToSz))
18493 StoreType = MVT::f64;
18495 // Bitcast the original vector into a vector of store-size units
18496 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18497 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18498 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18499 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18500 SmallVector<SDValue, 8> Chains;
18501 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18502 TLI.getPointerTy());
18503 SDValue Ptr = St->getBasePtr();
18505 // Perform one or more big stores into memory.
18506 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18507 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18508 StoreType, ShuffWide,
18509 DAG.getIntPtrConstant(i));
18510 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18511 St->getPointerInfo(), St->isVolatile(),
18512 St->isNonTemporal(), St->getAlignment());
18513 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18514 Chains.push_back(Ch);
18517 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18521 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18522 // the FP state in cases where an emms may be missing.
18523 // A preferable solution to the general problem is to figure out the right
18524 // places to insert EMMS. This qualifies as a quick hack.
18526 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18527 if (VT.getSizeInBits() != 64)
18530 const Function *F = DAG.getMachineFunction().getFunction();
18531 bool NoImplicitFloatOps = F->getAttributes().
18532 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18533 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18534 && Subtarget->hasSSE2();
18535 if ((VT.isVector() ||
18536 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18537 isa<LoadSDNode>(St->getValue()) &&
18538 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18539 St->getChain().hasOneUse() && !St->isVolatile()) {
18540 SDNode* LdVal = St->getValue().getNode();
18541 LoadSDNode *Ld = 0;
18542 int TokenFactorIndex = -1;
18543 SmallVector<SDValue, 8> Ops;
18544 SDNode* ChainVal = St->getChain().getNode();
18545 // Must be a store of a load. We currently handle two cases: the load
18546 // is a direct child, and it's under an intervening TokenFactor. It is
18547 // possible to dig deeper under nested TokenFactors.
18548 if (ChainVal == LdVal)
18549 Ld = cast<LoadSDNode>(St->getChain());
18550 else if (St->getValue().hasOneUse() &&
18551 ChainVal->getOpcode() == ISD::TokenFactor) {
18552 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18553 if (ChainVal->getOperand(i).getNode() == LdVal) {
18554 TokenFactorIndex = i;
18555 Ld = cast<LoadSDNode>(St->getValue());
18557 Ops.push_back(ChainVal->getOperand(i));
18561 if (!Ld || !ISD::isNormalLoad(Ld))
18564 // If this is not the MMX case, i.e. we are just turning i64 load/store
18565 // into f64 load/store, avoid the transformation if there are multiple
18566 // uses of the loaded value.
18567 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18572 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18573 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18575 if (Subtarget->is64Bit() || F64IsLegal) {
18576 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18577 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18578 Ld->getPointerInfo(), Ld->isVolatile(),
18579 Ld->isNonTemporal(), Ld->isInvariant(),
18580 Ld->getAlignment());
18581 SDValue NewChain = NewLd.getValue(1);
18582 if (TokenFactorIndex != -1) {
18583 Ops.push_back(NewChain);
18584 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18587 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18588 St->getPointerInfo(),
18589 St->isVolatile(), St->isNonTemporal(),
18590 St->getAlignment());
18593 // Otherwise, lower to two pairs of 32-bit loads / stores.
18594 SDValue LoAddr = Ld->getBasePtr();
18595 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18596 DAG.getConstant(4, MVT::i32));
18598 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18599 Ld->getPointerInfo(),
18600 Ld->isVolatile(), Ld->isNonTemporal(),
18601 Ld->isInvariant(), Ld->getAlignment());
18602 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18603 Ld->getPointerInfo().getWithOffset(4),
18604 Ld->isVolatile(), Ld->isNonTemporal(),
18606 MinAlign(Ld->getAlignment(), 4));
18608 SDValue NewChain = LoLd.getValue(1);
18609 if (TokenFactorIndex != -1) {
18610 Ops.push_back(LoLd);
18611 Ops.push_back(HiLd);
18612 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18616 LoAddr = St->getBasePtr();
18617 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18618 DAG.getConstant(4, MVT::i32));
18620 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18621 St->getPointerInfo(),
18622 St->isVolatile(), St->isNonTemporal(),
18623 St->getAlignment());
18624 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18625 St->getPointerInfo().getWithOffset(4),
18627 St->isNonTemporal(),
18628 MinAlign(St->getAlignment(), 4));
18629 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18634 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18635 /// and return the operands for the horizontal operation in LHS and RHS. A
18636 /// horizontal operation performs the binary operation on successive elements
18637 /// of its first operand, then on successive elements of its second operand,
18638 /// returning the resulting values in a vector. For example, if
18639 /// A = < float a0, float a1, float a2, float a3 >
18641 /// B = < float b0, float b1, float b2, float b3 >
18642 /// then the result of doing a horizontal operation on A and B is
18643 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18644 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18645 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18646 /// set to A, RHS to B, and the routine returns 'true'.
18647 /// Note that the binary operation should have the property that if one of the
18648 /// operands is UNDEF then the result is UNDEF.
18649 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18650 // Look for the following pattern: if
18651 // A = < float a0, float a1, float a2, float a3 >
18652 // B = < float b0, float b1, float b2, float b3 >
18654 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18655 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18656 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18657 // which is A horizontal-op B.
18659 // At least one of the operands should be a vector shuffle.
18660 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18661 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18664 MVT VT = LHS.getSimpleValueType();
18666 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18667 "Unsupported vector type for horizontal add/sub");
18669 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18670 // operate independently on 128-bit lanes.
18671 unsigned NumElts = VT.getVectorNumElements();
18672 unsigned NumLanes = VT.getSizeInBits()/128;
18673 unsigned NumLaneElts = NumElts / NumLanes;
18674 assert((NumLaneElts % 2 == 0) &&
18675 "Vector type should have an even number of elements in each lane");
18676 unsigned HalfLaneElts = NumLaneElts/2;
18678 // View LHS in the form
18679 // LHS = VECTOR_SHUFFLE A, B, LMask
18680 // If LHS is not a shuffle then pretend it is the shuffle
18681 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18682 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18685 SmallVector<int, 16> LMask(NumElts);
18686 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18687 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18688 A = LHS.getOperand(0);
18689 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18690 B = LHS.getOperand(1);
18691 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18692 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18694 if (LHS.getOpcode() != ISD::UNDEF)
18696 for (unsigned i = 0; i != NumElts; ++i)
18700 // Likewise, view RHS in the form
18701 // RHS = VECTOR_SHUFFLE C, D, RMask
18703 SmallVector<int, 16> RMask(NumElts);
18704 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18705 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18706 C = RHS.getOperand(0);
18707 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18708 D = RHS.getOperand(1);
18709 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18710 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18712 if (RHS.getOpcode() != ISD::UNDEF)
18714 for (unsigned i = 0; i != NumElts; ++i)
18718 // Check that the shuffles are both shuffling the same vectors.
18719 if (!(A == C && B == D) && !(A == D && B == C))
18722 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18723 if (!A.getNode() && !B.getNode())
18726 // If A and B occur in reverse order in RHS, then "swap" them (which means
18727 // rewriting the mask).
18729 CommuteVectorShuffleMask(RMask, NumElts);
18731 // At this point LHS and RHS are equivalent to
18732 // LHS = VECTOR_SHUFFLE A, B, LMask
18733 // RHS = VECTOR_SHUFFLE A, B, RMask
18734 // Check that the masks correspond to performing a horizontal operation.
18735 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18736 for (unsigned i = 0; i != NumLaneElts; ++i) {
18737 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18739 // Ignore any UNDEF components.
18740 if (LIdx < 0 || RIdx < 0 ||
18741 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18742 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18745 // Check that successive elements are being operated on. If not, this is
18746 // not a horizontal operation.
18747 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18748 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18749 if (!(LIdx == Index && RIdx == Index + 1) &&
18750 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18755 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18756 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18760 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18761 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18762 const X86Subtarget *Subtarget) {
18763 EVT VT = N->getValueType(0);
18764 SDValue LHS = N->getOperand(0);
18765 SDValue RHS = N->getOperand(1);
18767 // Try to synthesize horizontal adds from adds of shuffles.
18768 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18769 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18770 isHorizontalBinOp(LHS, RHS, true))
18771 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18775 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18776 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18777 const X86Subtarget *Subtarget) {
18778 EVT VT = N->getValueType(0);
18779 SDValue LHS = N->getOperand(0);
18780 SDValue RHS = N->getOperand(1);
18782 // Try to synthesize horizontal subs from subs of shuffles.
18783 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18784 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18785 isHorizontalBinOp(LHS, RHS, false))
18786 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18790 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18791 /// X86ISD::FXOR nodes.
18792 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18793 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18794 // F[X]OR(0.0, x) -> x
18795 // F[X]OR(x, 0.0) -> x
18796 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18797 if (C->getValueAPF().isPosZero())
18798 return N->getOperand(1);
18799 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18800 if (C->getValueAPF().isPosZero())
18801 return N->getOperand(0);
18805 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18806 /// X86ISD::FMAX nodes.
18807 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18808 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18810 // Only perform optimizations if UnsafeMath is used.
18811 if (!DAG.getTarget().Options.UnsafeFPMath)
18814 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18815 // into FMINC and FMAXC, which are Commutative operations.
18816 unsigned NewOp = 0;
18817 switch (N->getOpcode()) {
18818 default: llvm_unreachable("unknown opcode");
18819 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18820 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18823 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18824 N->getOperand(0), N->getOperand(1));
18827 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18828 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18829 // FAND(0.0, x) -> 0.0
18830 // FAND(x, 0.0) -> 0.0
18831 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18832 if (C->getValueAPF().isPosZero())
18833 return N->getOperand(0);
18834 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18835 if (C->getValueAPF().isPosZero())
18836 return N->getOperand(1);
18840 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18841 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18842 // FANDN(x, 0.0) -> 0.0
18843 // FANDN(0.0, x) -> x
18844 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18845 if (C->getValueAPF().isPosZero())
18846 return N->getOperand(1);
18847 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18848 if (C->getValueAPF().isPosZero())
18849 return N->getOperand(1);
18853 static SDValue PerformBTCombine(SDNode *N,
18855 TargetLowering::DAGCombinerInfo &DCI) {
18856 // BT ignores high bits in the bit index operand.
18857 SDValue Op1 = N->getOperand(1);
18858 if (Op1.hasOneUse()) {
18859 unsigned BitWidth = Op1.getValueSizeInBits();
18860 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18861 APInt KnownZero, KnownOne;
18862 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18863 !DCI.isBeforeLegalizeOps());
18864 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18865 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18866 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18867 DCI.CommitTargetLoweringOpt(TLO);
18872 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18873 SDValue Op = N->getOperand(0);
18874 if (Op.getOpcode() == ISD::BITCAST)
18875 Op = Op.getOperand(0);
18876 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18877 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18878 VT.getVectorElementType().getSizeInBits() ==
18879 OpVT.getVectorElementType().getSizeInBits()) {
18880 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18885 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18886 const X86Subtarget *Subtarget) {
18887 EVT VT = N->getValueType(0);
18888 if (!VT.isVector())
18891 SDValue N0 = N->getOperand(0);
18892 SDValue N1 = N->getOperand(1);
18893 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18896 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18897 // both SSE and AVX2 since there is no sign-extended shift right
18898 // operation on a vector with 64-bit elements.
18899 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18900 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18901 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18902 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18903 SDValue N00 = N0.getOperand(0);
18905 // EXTLOAD has a better solution on AVX2,
18906 // it may be replaced with X86ISD::VSEXT node.
18907 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18908 if (!ISD::isNormalLoad(N00.getNode()))
18911 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18912 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18914 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18920 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18921 TargetLowering::DAGCombinerInfo &DCI,
18922 const X86Subtarget *Subtarget) {
18923 if (!DCI.isBeforeLegalizeOps())
18926 if (!Subtarget->hasFp256())
18929 EVT VT = N->getValueType(0);
18930 if (VT.isVector() && VT.getSizeInBits() == 256) {
18931 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18939 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18940 const X86Subtarget* Subtarget) {
18942 EVT VT = N->getValueType(0);
18944 // Let legalize expand this if it isn't a legal type yet.
18945 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18948 EVT ScalarVT = VT.getScalarType();
18949 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18950 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18953 SDValue A = N->getOperand(0);
18954 SDValue B = N->getOperand(1);
18955 SDValue C = N->getOperand(2);
18957 bool NegA = (A.getOpcode() == ISD::FNEG);
18958 bool NegB = (B.getOpcode() == ISD::FNEG);
18959 bool NegC = (C.getOpcode() == ISD::FNEG);
18961 // Negative multiplication when NegA xor NegB
18962 bool NegMul = (NegA != NegB);
18964 A = A.getOperand(0);
18966 B = B.getOperand(0);
18968 C = C.getOperand(0);
18972 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18974 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18976 return DAG.getNode(Opcode, dl, VT, A, B, C);
18979 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18980 TargetLowering::DAGCombinerInfo &DCI,
18981 const X86Subtarget *Subtarget) {
18982 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18983 // (and (i32 x86isd::setcc_carry), 1)
18984 // This eliminates the zext. This transformation is necessary because
18985 // ISD::SETCC is always legalized to i8.
18987 SDValue N0 = N->getOperand(0);
18988 EVT VT = N->getValueType(0);
18990 if (N0.getOpcode() == ISD::AND &&
18992 N0.getOperand(0).hasOneUse()) {
18993 SDValue N00 = N0.getOperand(0);
18994 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18995 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18996 if (!C || C->getZExtValue() != 1)
18998 return DAG.getNode(ISD::AND, dl, VT,
18999 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19000 N00.getOperand(0), N00.getOperand(1)),
19001 DAG.getConstant(1, VT));
19005 if (N0.getOpcode() == ISD::TRUNCATE &&
19007 N0.getOperand(0).hasOneUse()) {
19008 SDValue N00 = N0.getOperand(0);
19009 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19010 return DAG.getNode(ISD::AND, dl, VT,
19011 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19012 N00.getOperand(0), N00.getOperand(1)),
19013 DAG.getConstant(1, VT));
19016 if (VT.is256BitVector()) {
19017 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19025 // Optimize x == -y --> x+y == 0
19026 // x != -y --> x+y != 0
19027 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
19028 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
19029 SDValue LHS = N->getOperand(0);
19030 SDValue RHS = N->getOperand(1);
19032 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
19033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
19034 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
19035 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19036 LHS.getValueType(), RHS, LHS.getOperand(1));
19037 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19038 addV, DAG.getConstant(0, addV.getValueType()), CC);
19040 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
19041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
19042 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
19043 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19044 RHS.getValueType(), LHS, RHS.getOperand(1));
19045 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19046 addV, DAG.getConstant(0, addV.getValueType()), CC);
19051 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
19052 // as "sbb reg,reg", since it can be extended without zext and produces
19053 // an all-ones bit which is more useful than 0/1 in some cases.
19054 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
19057 return DAG.getNode(ISD::AND, DL, VT,
19058 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19059 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
19060 DAG.getConstant(1, VT));
19061 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
19062 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
19063 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19064 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
19067 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
19068 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
19069 TargetLowering::DAGCombinerInfo &DCI,
19070 const X86Subtarget *Subtarget) {
19072 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
19073 SDValue EFLAGS = N->getOperand(1);
19075 if (CC == X86::COND_A) {
19076 // Try to convert COND_A into COND_B in an attempt to facilitate
19077 // materializing "setb reg".
19079 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
19080 // cannot take an immediate as its first operand.
19082 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
19083 EFLAGS.getValueType().isInteger() &&
19084 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
19085 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
19086 EFLAGS.getNode()->getVTList(),
19087 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
19088 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
19089 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
19093 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
19094 // a zext and produces an all-ones bit which is more useful than 0/1 in some
19096 if (CC == X86::COND_B)
19097 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
19101 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19102 if (Flags.getNode()) {
19103 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19104 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19110 // Optimize branch condition evaluation.
19112 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19113 TargetLowering::DAGCombinerInfo &DCI,
19114 const X86Subtarget *Subtarget) {
19116 SDValue Chain = N->getOperand(0);
19117 SDValue Dest = N->getOperand(1);
19118 SDValue EFLAGS = N->getOperand(3);
19119 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19123 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19124 if (Flags.getNode()) {
19125 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19126 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19133 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19134 const X86TargetLowering *XTLI) {
19135 SDValue Op0 = N->getOperand(0);
19136 EVT InVT = Op0->getValueType(0);
19138 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19139 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19141 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19142 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19143 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19146 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19147 // a 32-bit target where SSE doesn't support i64->FP operations.
19148 if (Op0.getOpcode() == ISD::LOAD) {
19149 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19150 EVT VT = Ld->getValueType(0);
19151 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19152 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19153 !XTLI->getSubtarget()->is64Bit() &&
19155 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19156 Ld->getChain(), Op0, DAG);
19157 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19164 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19165 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19166 X86TargetLowering::DAGCombinerInfo &DCI) {
19167 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19168 // the result is either zero or one (depending on the input carry bit).
19169 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19170 if (X86::isZeroNode(N->getOperand(0)) &&
19171 X86::isZeroNode(N->getOperand(1)) &&
19172 // We don't have a good way to replace an EFLAGS use, so only do this when
19174 SDValue(N, 1).use_empty()) {
19176 EVT VT = N->getValueType(0);
19177 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19178 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19179 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19180 DAG.getConstant(X86::COND_B,MVT::i8),
19182 DAG.getConstant(1, VT));
19183 return DCI.CombineTo(N, Res1, CarryOut);
19189 // fold (add Y, (sete X, 0)) -> adc 0, Y
19190 // (add Y, (setne X, 0)) -> sbb -1, Y
19191 // (sub (sete X, 0), Y) -> sbb 0, Y
19192 // (sub (setne X, 0), Y) -> adc -1, Y
19193 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19196 // Look through ZExts.
19197 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19198 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19201 SDValue SetCC = Ext.getOperand(0);
19202 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19205 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19206 if (CC != X86::COND_E && CC != X86::COND_NE)
19209 SDValue Cmp = SetCC.getOperand(1);
19210 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19211 !X86::isZeroNode(Cmp.getOperand(1)) ||
19212 !Cmp.getOperand(0).getValueType().isInteger())
19215 SDValue CmpOp0 = Cmp.getOperand(0);
19216 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19217 DAG.getConstant(1, CmpOp0.getValueType()));
19219 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19220 if (CC == X86::COND_NE)
19221 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19222 DL, OtherVal.getValueType(), OtherVal,
19223 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19224 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19225 DL, OtherVal.getValueType(), OtherVal,
19226 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19229 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19230 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19231 const X86Subtarget *Subtarget) {
19232 EVT VT = N->getValueType(0);
19233 SDValue Op0 = N->getOperand(0);
19234 SDValue Op1 = N->getOperand(1);
19236 // Try to synthesize horizontal adds from adds of shuffles.
19237 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19238 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19239 isHorizontalBinOp(Op0, Op1, true))
19240 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19242 return OptimizeConditionalInDecrement(N, DAG);
19245 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19246 const X86Subtarget *Subtarget) {
19247 SDValue Op0 = N->getOperand(0);
19248 SDValue Op1 = N->getOperand(1);
19250 // X86 can't encode an immediate LHS of a sub. See if we can push the
19251 // negation into a preceding instruction.
19252 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19253 // If the RHS of the sub is a XOR with one use and a constant, invert the
19254 // immediate. Then add one to the LHS of the sub so we can turn
19255 // X-Y -> X+~Y+1, saving one register.
19256 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19257 isa<ConstantSDNode>(Op1.getOperand(1))) {
19258 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19259 EVT VT = Op0.getValueType();
19260 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19262 DAG.getConstant(~XorC, VT));
19263 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19264 DAG.getConstant(C->getAPIntValue()+1, VT));
19268 // Try to synthesize horizontal adds from adds of shuffles.
19269 EVT VT = N->getValueType(0);
19270 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19271 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19272 isHorizontalBinOp(Op0, Op1, true))
19273 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19275 return OptimizeConditionalInDecrement(N, DAG);
19278 /// performVZEXTCombine - Performs build vector combines
19279 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19280 TargetLowering::DAGCombinerInfo &DCI,
19281 const X86Subtarget *Subtarget) {
19282 // (vzext (bitcast (vzext (x)) -> (vzext x)
19283 SDValue In = N->getOperand(0);
19284 while (In.getOpcode() == ISD::BITCAST)
19285 In = In.getOperand(0);
19287 if (In.getOpcode() != X86ISD::VZEXT)
19290 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19294 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19295 DAGCombinerInfo &DCI) const {
19296 SelectionDAG &DAG = DCI.DAG;
19297 switch (N->getOpcode()) {
19299 case ISD::EXTRACT_VECTOR_ELT:
19300 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19302 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19303 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19304 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19305 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19306 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19307 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19310 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19311 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19312 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19313 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19314 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19315 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19316 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19317 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19318 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19320 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19322 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19323 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19324 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19325 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19326 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19327 case ISD::ANY_EXTEND:
19328 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19329 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19330 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19331 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19332 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19333 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19334 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19335 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19336 case X86ISD::SHUFP: // Handle all target specific shuffles
19337 case X86ISD::PALIGNR:
19338 case X86ISD::UNPCKH:
19339 case X86ISD::UNPCKL:
19340 case X86ISD::MOVHLPS:
19341 case X86ISD::MOVLHPS:
19342 case X86ISD::PSHUFD:
19343 case X86ISD::PSHUFHW:
19344 case X86ISD::PSHUFLW:
19345 case X86ISD::MOVSS:
19346 case X86ISD::MOVSD:
19347 case X86ISD::VPERMILP:
19348 case X86ISD::VPERM2X128:
19349 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19350 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19356 /// isTypeDesirableForOp - Return true if the target has native support for
19357 /// the specified value type and it is 'desirable' to use the type for the
19358 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19359 /// instruction encodings are longer and some i16 instructions are slow.
19360 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19361 if (!isTypeLegal(VT))
19363 if (VT != MVT::i16)
19370 case ISD::SIGN_EXTEND:
19371 case ISD::ZERO_EXTEND:
19372 case ISD::ANY_EXTEND:
19385 /// IsDesirableToPromoteOp - This method query the target whether it is
19386 /// beneficial for dag combiner to promote the specified node. If true, it
19387 /// should return the desired promotion type by reference.
19388 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19389 EVT VT = Op.getValueType();
19390 if (VT != MVT::i16)
19393 bool Promote = false;
19394 bool Commute = false;
19395 switch (Op.getOpcode()) {
19398 LoadSDNode *LD = cast<LoadSDNode>(Op);
19399 // If the non-extending load has a single use and it's not live out, then it
19400 // might be folded.
19401 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19402 Op.hasOneUse()*/) {
19403 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19404 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19405 // The only case where we'd want to promote LOAD (rather then it being
19406 // promoted as an operand is when it's only use is liveout.
19407 if (UI->getOpcode() != ISD::CopyToReg)
19414 case ISD::SIGN_EXTEND:
19415 case ISD::ZERO_EXTEND:
19416 case ISD::ANY_EXTEND:
19421 SDValue N0 = Op.getOperand(0);
19422 // Look out for (store (shl (load), x)).
19423 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19436 SDValue N0 = Op.getOperand(0);
19437 SDValue N1 = Op.getOperand(1);
19438 if (!Commute && MayFoldLoad(N1))
19440 // Avoid disabling potential load folding opportunities.
19441 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19443 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19453 //===----------------------------------------------------------------------===//
19454 // X86 Inline Assembly Support
19455 //===----------------------------------------------------------------------===//
19458 // Helper to match a string separated by whitespace.
19459 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19460 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19462 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19463 StringRef piece(*args[i]);
19464 if (!s.startswith(piece)) // Check if the piece matches.
19467 s = s.substr(piece.size());
19468 StringRef::size_type pos = s.find_first_not_of(" \t");
19469 if (pos == 0) // We matched a prefix.
19477 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19480 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19482 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19483 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19484 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19485 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19487 if (AsmPieces.size() == 3)
19489 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19496 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19497 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19499 std::string AsmStr = IA->getAsmString();
19501 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19502 if (!Ty || Ty->getBitWidth() % 16 != 0)
19505 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19506 SmallVector<StringRef, 4> AsmPieces;
19507 SplitString(AsmStr, AsmPieces, ";\n");
19509 switch (AsmPieces.size()) {
19510 default: return false;
19512 // FIXME: this should verify that we are targeting a 486 or better. If not,
19513 // we will turn this bswap into something that will be lowered to logical
19514 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19515 // lower so don't worry about this.
19517 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19518 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19519 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19520 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19521 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19522 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19523 // No need to check constraints, nothing other than the equivalent of
19524 // "=r,0" would be valid here.
19525 return IntrinsicLowering::LowerToByteSwap(CI);
19528 // rorw $$8, ${0:w} --> llvm.bswap.i16
19529 if (CI->getType()->isIntegerTy(16) &&
19530 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19531 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19532 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19534 const std::string &ConstraintsStr = IA->getConstraintString();
19535 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19536 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19537 if (clobbersFlagRegisters(AsmPieces))
19538 return IntrinsicLowering::LowerToByteSwap(CI);
19542 if (CI->getType()->isIntegerTy(32) &&
19543 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19544 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19545 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19546 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19548 const std::string &ConstraintsStr = IA->getConstraintString();
19549 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19550 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19551 if (clobbersFlagRegisters(AsmPieces))
19552 return IntrinsicLowering::LowerToByteSwap(CI);
19555 if (CI->getType()->isIntegerTy(64)) {
19556 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19557 if (Constraints.size() >= 2 &&
19558 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19559 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19560 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19561 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19562 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19563 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19564 return IntrinsicLowering::LowerToByteSwap(CI);
19572 /// getConstraintType - Given a constraint letter, return the type of
19573 /// constraint it is for this target.
19574 X86TargetLowering::ConstraintType
19575 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19576 if (Constraint.size() == 1) {
19577 switch (Constraint[0]) {
19588 return C_RegisterClass;
19612 return TargetLowering::getConstraintType(Constraint);
19615 /// Examine constraint type and operand type and determine a weight value.
19616 /// This object must already have been set up with the operand type
19617 /// and the current alternative constraint selected.
19618 TargetLowering::ConstraintWeight
19619 X86TargetLowering::getSingleConstraintMatchWeight(
19620 AsmOperandInfo &info, const char *constraint) const {
19621 ConstraintWeight weight = CW_Invalid;
19622 Value *CallOperandVal = info.CallOperandVal;
19623 // If we don't have a value, we can't do a match,
19624 // but allow it at the lowest weight.
19625 if (CallOperandVal == NULL)
19627 Type *type = CallOperandVal->getType();
19628 // Look at the constraint type.
19629 switch (*constraint) {
19631 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19642 if (CallOperandVal->getType()->isIntegerTy())
19643 weight = CW_SpecificReg;
19648 if (type->isFloatingPointTy())
19649 weight = CW_SpecificReg;
19652 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19653 weight = CW_SpecificReg;
19657 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19658 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19659 weight = CW_Register;
19662 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19663 if (C->getZExtValue() <= 31)
19664 weight = CW_Constant;
19668 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19669 if (C->getZExtValue() <= 63)
19670 weight = CW_Constant;
19674 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19675 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19676 weight = CW_Constant;
19680 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19681 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19682 weight = CW_Constant;
19686 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19687 if (C->getZExtValue() <= 3)
19688 weight = CW_Constant;
19692 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19693 if (C->getZExtValue() <= 0xff)
19694 weight = CW_Constant;
19699 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19700 weight = CW_Constant;
19704 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19705 if ((C->getSExtValue() >= -0x80000000LL) &&
19706 (C->getSExtValue() <= 0x7fffffffLL))
19707 weight = CW_Constant;
19711 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19712 if (C->getZExtValue() <= 0xffffffff)
19713 weight = CW_Constant;
19720 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19721 /// with another that has more specific requirements based on the type of the
19722 /// corresponding operand.
19723 const char *X86TargetLowering::
19724 LowerXConstraint(EVT ConstraintVT) const {
19725 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19726 // 'f' like normal targets.
19727 if (ConstraintVT.isFloatingPoint()) {
19728 if (Subtarget->hasSSE2())
19730 if (Subtarget->hasSSE1())
19734 return TargetLowering::LowerXConstraint(ConstraintVT);
19737 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19738 /// vector. If it is invalid, don't add anything to Ops.
19739 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19740 std::string &Constraint,
19741 std::vector<SDValue>&Ops,
19742 SelectionDAG &DAG) const {
19743 SDValue Result(0, 0);
19745 // Only support length 1 constraints for now.
19746 if (Constraint.length() > 1) return;
19748 char ConstraintLetter = Constraint[0];
19749 switch (ConstraintLetter) {
19752 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19753 if (C->getZExtValue() <= 31) {
19754 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19760 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19761 if (C->getZExtValue() <= 63) {
19762 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19768 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19769 if (isInt<8>(C->getSExtValue())) {
19770 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19776 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19777 if (C->getZExtValue() <= 255) {
19778 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19784 // 32-bit signed value
19785 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19786 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19787 C->getSExtValue())) {
19788 // Widen to 64 bits here to get it sign extended.
19789 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19792 // FIXME gcc accepts some relocatable values here too, but only in certain
19793 // memory models; it's complicated.
19798 // 32-bit unsigned value
19799 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19800 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19801 C->getZExtValue())) {
19802 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19806 // FIXME gcc accepts some relocatable values here too, but only in certain
19807 // memory models; it's complicated.
19811 // Literal immediates are always ok.
19812 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19813 // Widen to 64 bits here to get it sign extended.
19814 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19818 // In any sort of PIC mode addresses need to be computed at runtime by
19819 // adding in a register or some sort of table lookup. These can't
19820 // be used as immediates.
19821 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19824 // If we are in non-pic codegen mode, we allow the address of a global (with
19825 // an optional displacement) to be used with 'i'.
19826 GlobalAddressSDNode *GA = 0;
19827 int64_t Offset = 0;
19829 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19831 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19832 Offset += GA->getOffset();
19834 } else if (Op.getOpcode() == ISD::ADD) {
19835 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19836 Offset += C->getZExtValue();
19837 Op = Op.getOperand(0);
19840 } else if (Op.getOpcode() == ISD::SUB) {
19841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19842 Offset += -C->getZExtValue();
19843 Op = Op.getOperand(0);
19848 // Otherwise, this isn't something we can handle, reject it.
19852 const GlobalValue *GV = GA->getGlobal();
19853 // If we require an extra load to get this address, as in PIC mode, we
19854 // can't accept it.
19855 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19856 getTargetMachine())))
19859 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19860 GA->getValueType(0), Offset);
19865 if (Result.getNode()) {
19866 Ops.push_back(Result);
19869 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19872 std::pair<unsigned, const TargetRegisterClass*>
19873 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19875 // First, see if this is a constraint that directly corresponds to an LLVM
19877 if (Constraint.size() == 1) {
19878 // GCC Constraint Letters
19879 switch (Constraint[0]) {
19881 // TODO: Slight differences here in allocation order and leaving
19882 // RIP in the class. Do they matter any more here than they do
19883 // in the normal allocation?
19884 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19885 if (Subtarget->is64Bit()) {
19886 if (VT == MVT::i32 || VT == MVT::f32)
19887 return std::make_pair(0U, &X86::GR32RegClass);
19888 if (VT == MVT::i16)
19889 return std::make_pair(0U, &X86::GR16RegClass);
19890 if (VT == MVT::i8 || VT == MVT::i1)
19891 return std::make_pair(0U, &X86::GR8RegClass);
19892 if (VT == MVT::i64 || VT == MVT::f64)
19893 return std::make_pair(0U, &X86::GR64RegClass);
19896 // 32-bit fallthrough
19897 case 'Q': // Q_REGS
19898 if (VT == MVT::i32 || VT == MVT::f32)
19899 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19900 if (VT == MVT::i16)
19901 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19902 if (VT == MVT::i8 || VT == MVT::i1)
19903 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19904 if (VT == MVT::i64)
19905 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19907 case 'r': // GENERAL_REGS
19908 case 'l': // INDEX_REGS
19909 if (VT == MVT::i8 || VT == MVT::i1)
19910 return std::make_pair(0U, &X86::GR8RegClass);
19911 if (VT == MVT::i16)
19912 return std::make_pair(0U, &X86::GR16RegClass);
19913 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19914 return std::make_pair(0U, &X86::GR32RegClass);
19915 return std::make_pair(0U, &X86::GR64RegClass);
19916 case 'R': // LEGACY_REGS
19917 if (VT == MVT::i8 || VT == MVT::i1)
19918 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19919 if (VT == MVT::i16)
19920 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19921 if (VT == MVT::i32 || !Subtarget->is64Bit())
19922 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19923 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19924 case 'f': // FP Stack registers.
19925 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19926 // value to the correct fpstack register class.
19927 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19928 return std::make_pair(0U, &X86::RFP32RegClass);
19929 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19930 return std::make_pair(0U, &X86::RFP64RegClass);
19931 return std::make_pair(0U, &X86::RFP80RegClass);
19932 case 'y': // MMX_REGS if MMX allowed.
19933 if (!Subtarget->hasMMX()) break;
19934 return std::make_pair(0U, &X86::VR64RegClass);
19935 case 'Y': // SSE_REGS if SSE2 allowed
19936 if (!Subtarget->hasSSE2()) break;
19938 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19939 if (!Subtarget->hasSSE1()) break;
19941 switch (VT.SimpleTy) {
19943 // Scalar SSE types.
19946 return std::make_pair(0U, &X86::FR32RegClass);
19949 return std::make_pair(0U, &X86::FR64RegClass);
19957 return std::make_pair(0U, &X86::VR128RegClass);
19965 return std::make_pair(0U, &X86::VR256RegClass);
19970 return std::make_pair(0U, &X86::VR512RegClass);
19976 // Use the default implementation in TargetLowering to convert the register
19977 // constraint into a member of a register class.
19978 std::pair<unsigned, const TargetRegisterClass*> Res;
19979 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19981 // Not found as a standard register?
19982 if (Res.second == 0) {
19983 // Map st(0) -> st(7) -> ST0
19984 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19985 tolower(Constraint[1]) == 's' &&
19986 tolower(Constraint[2]) == 't' &&
19987 Constraint[3] == '(' &&
19988 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19989 Constraint[5] == ')' &&
19990 Constraint[6] == '}') {
19992 Res.first = X86::ST0+Constraint[4]-'0';
19993 Res.second = &X86::RFP80RegClass;
19997 // GCC allows "st(0)" to be called just plain "st".
19998 if (StringRef("{st}").equals_lower(Constraint)) {
19999 Res.first = X86::ST0;
20000 Res.second = &X86::RFP80RegClass;
20005 if (StringRef("{flags}").equals_lower(Constraint)) {
20006 Res.first = X86::EFLAGS;
20007 Res.second = &X86::CCRRegClass;
20011 // 'A' means EAX + EDX.
20012 if (Constraint == "A") {
20013 Res.first = X86::EAX;
20014 Res.second = &X86::GR32_ADRegClass;
20020 // Otherwise, check to see if this is a register class of the wrong value
20021 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
20022 // turn into {ax},{dx}.
20023 if (Res.second->hasType(VT))
20024 return Res; // Correct type already, nothing to do.
20026 // All of the single-register GCC register classes map their values onto
20027 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
20028 // really want an 8-bit or 32-bit register, map to the appropriate register
20029 // class and return the appropriate register.
20030 if (Res.second == &X86::GR16RegClass) {
20031 if (VT == MVT::i8 || VT == MVT::i1) {
20032 unsigned DestReg = 0;
20033 switch (Res.first) {
20035 case X86::AX: DestReg = X86::AL; break;
20036 case X86::DX: DestReg = X86::DL; break;
20037 case X86::CX: DestReg = X86::CL; break;
20038 case X86::BX: DestReg = X86::BL; break;
20041 Res.first = DestReg;
20042 Res.second = &X86::GR8RegClass;
20044 } else if (VT == MVT::i32 || VT == MVT::f32) {
20045 unsigned DestReg = 0;
20046 switch (Res.first) {
20048 case X86::AX: DestReg = X86::EAX; break;
20049 case X86::DX: DestReg = X86::EDX; break;
20050 case X86::CX: DestReg = X86::ECX; break;
20051 case X86::BX: DestReg = X86::EBX; break;
20052 case X86::SI: DestReg = X86::ESI; break;
20053 case X86::DI: DestReg = X86::EDI; break;
20054 case X86::BP: DestReg = X86::EBP; break;
20055 case X86::SP: DestReg = X86::ESP; break;
20058 Res.first = DestReg;
20059 Res.second = &X86::GR32RegClass;
20061 } else if (VT == MVT::i64 || VT == MVT::f64) {
20062 unsigned DestReg = 0;
20063 switch (Res.first) {
20065 case X86::AX: DestReg = X86::RAX; break;
20066 case X86::DX: DestReg = X86::RDX; break;
20067 case X86::CX: DestReg = X86::RCX; break;
20068 case X86::BX: DestReg = X86::RBX; break;
20069 case X86::SI: DestReg = X86::RSI; break;
20070 case X86::DI: DestReg = X86::RDI; break;
20071 case X86::BP: DestReg = X86::RBP; break;
20072 case X86::SP: DestReg = X86::RSP; break;
20075 Res.first = DestReg;
20076 Res.second = &X86::GR64RegClass;
20079 } else if (Res.second == &X86::FR32RegClass ||
20080 Res.second == &X86::FR64RegClass ||
20081 Res.second == &X86::VR128RegClass ||
20082 Res.second == &X86::VR256RegClass ||
20083 Res.second == &X86::FR32XRegClass ||
20084 Res.second == &X86::FR64XRegClass ||
20085 Res.second == &X86::VR128XRegClass ||
20086 Res.second == &X86::VR256XRegClass ||
20087 Res.second == &X86::VR512RegClass) {
20088 // Handle references to XMM physical registers that got mapped into the
20089 // wrong class. This can happen with constraints like {xmm0} where the
20090 // target independent register mapper will just pick the first match it can
20091 // find, ignoring the required type.
20093 if (VT == MVT::f32 || VT == MVT::i32)
20094 Res.second = &X86::FR32RegClass;
20095 else if (VT == MVT::f64 || VT == MVT::i64)
20096 Res.second = &X86::FR64RegClass;
20097 else if (X86::VR128RegClass.hasType(VT))
20098 Res.second = &X86::VR128RegClass;
20099 else if (X86::VR256RegClass.hasType(VT))
20100 Res.second = &X86::VR256RegClass;
20101 else if (X86::VR512RegClass.hasType(VT))
20102 Res.second = &X86::VR512RegClass;