1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
54 using namespace dwarf;
56 STATISTIC(NumTailCalls, "Number of tail calls");
59 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
61 // Forward declarations.
62 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
65 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
67 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
69 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
70 if (is64Bit) return new X8664_MachoTargetObjectFile();
71 return new TargetLoweringObjectFileMachO();
72 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
73 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
74 return new X8632_ELFTargetObjectFile(TM);
75 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
76 return new TargetLoweringObjectFileCOFF();
78 llvm_unreachable("unknown subtarget type");
81 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
82 : TargetLowering(TM, createTLOF(TM)) {
83 Subtarget = &TM.getSubtarget<X86Subtarget>();
84 X86ScalarSSEf64 = Subtarget->hasSSE2();
85 X86ScalarSSEf32 = Subtarget->hasSSE1();
86 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
88 RegInfo = TM.getRegisterInfo();
91 // Set up the TargetLowering object.
93 // X86 is weird, it always uses i8 for shift amounts and setcc results.
94 setShiftAmountType(MVT::i8);
95 setBooleanContents(ZeroOrOneBooleanContent);
96 setSchedulingPreference(Sched::RegPressure);
97 setStackPointerRegisterToSaveRestore(X86StackPtr);
99 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
100 // Setup Windows compiler runtime calls.
101 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
102 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
103 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
104 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
105 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
106 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::X86_StdCall);
109 if (Subtarget->isTargetDarwin()) {
110 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
111 setUseUnderscoreSetJmp(false);
112 setUseUnderscoreLongJmp(false);
113 } else if (Subtarget->isTargetMingw()) {
114 // MS runtime is weird: it exports _setjmp, but longjmp!
115 setUseUnderscoreSetJmp(true);
116 setUseUnderscoreLongJmp(false);
118 setUseUnderscoreSetJmp(true);
119 setUseUnderscoreLongJmp(true);
122 // Set up the register classes.
123 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
124 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
125 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
126 if (Subtarget->is64Bit())
127 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
129 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
131 // We don't accept any truncstore of integer registers.
132 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
133 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
134 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
135 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
136 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
137 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
139 // SETOEQ and SETUNE require checking two conditions.
140 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
141 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
142 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
143 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
144 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
145 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
147 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
149 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
150 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
151 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
153 if (Subtarget->is64Bit()) {
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
155 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
156 } else if (!UseSoftFloat) {
157 // We have an algorithm for SSE2->double, and we turn this into a
158 // 64-bit FILD followed by conditional FADD for other targets.
159 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
160 // We have an algorithm for SSE2, and we turn this into a 64-bit
161 // FILD for other targets.
162 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
165 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
167 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
171 // SSE has no i16 to fp conversion, only i32
172 if (X86ScalarSSEf32) {
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 // f32 and f64 cases are Legal, f80 case is not
175 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
177 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
185 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
186 // are Legal, f80 is custom lowered.
187 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
188 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
190 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
192 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
195 if (X86ScalarSSEf32) {
196 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
197 // f32 and f64 cases are Legal, f80 case is not
198 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
200 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
201 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
204 // Handle FP_TO_UINT by promoting the destination to a larger signed
206 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
207 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
208 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
210 if (Subtarget->is64Bit()) {
211 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
212 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
213 } else if (!UseSoftFloat) {
214 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
215 // Expand FP_TO_UINT into a select.
216 // FIXME: We would like to use a Custom expander here eventually to do
217 // the optimal thing for SSE vs. the default expansion in the legalizer.
218 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
220 // With SSE3 we can use fisttpll to convert to a signed i64; without
221 // SSE, we're stuck with a fistpll.
222 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
225 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
226 if (!X86ScalarSSEf64) {
227 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
228 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
229 if (Subtarget->is64Bit()) {
230 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
231 // Without SSE, i64->f64 goes through memory.
232 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
236 // Scalar integer divide and remainder are lowered to use operations that
237 // produce two results, to match the available instructions. This exposes
238 // the two-result form to trivial CSE, which is able to combine x/y and x%y
239 // into a single instruction.
241 // Scalar integer multiply-high is also lowered to use two-result
242 // operations, to match the available instructions. However, plain multiply
243 // (low) operations are left as Legal, as there are single-result
244 // instructions for this in x86. Using the two-result multiply instructions
245 // when both high and low results are needed must be arranged by dagcombine.
246 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
247 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
248 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
249 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
250 setOperationAction(ISD::SREM , MVT::i8 , Expand);
251 setOperationAction(ISD::UREM , MVT::i8 , Expand);
252 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
253 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
254 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
255 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
256 setOperationAction(ISD::SREM , MVT::i16 , Expand);
257 setOperationAction(ISD::UREM , MVT::i16 , Expand);
258 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
259 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
260 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
261 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
262 setOperationAction(ISD::SREM , MVT::i32 , Expand);
263 setOperationAction(ISD::UREM , MVT::i32 , Expand);
264 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
265 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
266 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
267 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
268 setOperationAction(ISD::SREM , MVT::i64 , Expand);
269 setOperationAction(ISD::UREM , MVT::i64 , Expand);
271 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
272 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
273 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
274 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
275 if (Subtarget->is64Bit())
276 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
277 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
278 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
279 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
280 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
281 setOperationAction(ISD::FREM , MVT::f32 , Expand);
282 setOperationAction(ISD::FREM , MVT::f64 , Expand);
283 setOperationAction(ISD::FREM , MVT::f80 , Expand);
284 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
287 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
288 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
289 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
290 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
291 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
292 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
293 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
294 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
295 if (Subtarget->is64Bit()) {
296 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
297 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
298 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
301 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
302 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
304 // These should be promoted to a larger select which is supported.
305 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
306 // X86 wants to expand cmov itself.
307 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
308 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
309 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
310 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
311 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
312 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
314 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
316 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
317 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
318 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
319 if (Subtarget->is64Bit()) {
320 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
321 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
323 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
326 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
327 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
328 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
329 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
330 if (Subtarget->is64Bit())
331 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
332 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
333 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
334 if (Subtarget->is64Bit()) {
335 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
336 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
337 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
338 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
339 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
341 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
342 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
343 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
344 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
345 if (Subtarget->is64Bit()) {
346 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
347 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
348 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
351 if (Subtarget->hasSSE1())
352 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
354 // We may not have a libcall for MEMBARRIER so we should lower this.
355 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
357 // On X86 and X86-64, atomic operations are lowered to locked instructions.
358 // Locked instructions, in turn, have implicit fence semantics (all memory
359 // operations are flushed before issuing the locked instruction, and they
360 // are not buffered), so we can fold away the common pattern of
361 // fence-atomic-fence.
362 setShouldFoldAtomicFences(true);
364 // Expand certain atomics
365 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
366 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
375 if (!Subtarget->is64Bit()) {
376 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
382 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
385 // FIXME - use subtarget debug flags
386 if (!Subtarget->isTargetDarwin() &&
387 !Subtarget->isTargetELF() &&
388 !Subtarget->isTargetCygMing()) {
389 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
392 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
393 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
395 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
396 if (Subtarget->is64Bit()) {
397 setExceptionPointerRegister(X86::RAX);
398 setExceptionSelectorRegister(X86::RDX);
400 setExceptionPointerRegister(X86::EAX);
401 setExceptionSelectorRegister(X86::EDX);
403 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
404 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
406 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
408 setOperationAction(ISD::TRAP, MVT::Other, Legal);
410 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
411 setOperationAction(ISD::VASTART , MVT::Other, Custom);
412 setOperationAction(ISD::VAEND , MVT::Other, Expand);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::VAARG , MVT::Other, Custom);
415 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
417 setOperationAction(ISD::VAARG , MVT::Other, Expand);
418 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
421 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
422 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
425 if (Subtarget->isTargetCygMing())
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
430 if (!UseSoftFloat && X86ScalarSSEf64) {
431 // f32 and f64 use SSE.
432 // Set up the FP register classes.
433 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
434 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
436 // Use ANDPD to simulate FABS.
437 setOperationAction(ISD::FABS , MVT::f64, Custom);
438 setOperationAction(ISD::FABS , MVT::f32, Custom);
440 // Use XORP to simulate FNEG.
441 setOperationAction(ISD::FNEG , MVT::f64, Custom);
442 setOperationAction(ISD::FNEG , MVT::f32, Custom);
444 // Use ANDPD and ORPD to simulate FCOPYSIGN.
445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
448 // We don't support sin/cos/fmod
449 setOperationAction(ISD::FSIN , MVT::f64, Expand);
450 setOperationAction(ISD::FCOS , MVT::f64, Expand);
451 setOperationAction(ISD::FSIN , MVT::f32, Expand);
452 setOperationAction(ISD::FCOS , MVT::f32, Expand);
454 // Expand FP immediates into loads from the stack, except for the special
456 addLegalFPImmediate(APFloat(+0.0)); // xorpd
457 addLegalFPImmediate(APFloat(+0.0f)); // xorps
458 } else if (!UseSoftFloat && X86ScalarSSEf32) {
459 // Use SSE for f32, x87 for f64.
460 // Set up the FP register classes.
461 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
462 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
464 // Use ANDPS to simulate FABS.
465 setOperationAction(ISD::FABS , MVT::f32, Custom);
467 // Use XORP to simulate FNEG.
468 setOperationAction(ISD::FNEG , MVT::f32, Custom);
470 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
472 // Use ANDPS and ORPS to simulate FCOPYSIGN.
473 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
474 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
476 // We don't support sin/cos/fmod
477 setOperationAction(ISD::FSIN , MVT::f32, Expand);
478 setOperationAction(ISD::FCOS , MVT::f32, Expand);
480 // Special cases we handle for FP constants.
481 addLegalFPImmediate(APFloat(+0.0f)); // xorps
482 addLegalFPImmediate(APFloat(+0.0)); // FLD0
483 addLegalFPImmediate(APFloat(+1.0)); // FLD1
484 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
485 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
488 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
489 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
491 } else if (!UseSoftFloat) {
492 // f32 and f64 in x87.
493 // Set up the FP register classes.
494 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
495 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
497 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
498 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
499 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
500 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
503 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
504 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
506 addLegalFPImmediate(APFloat(+0.0)); // FLD0
507 addLegalFPImmediate(APFloat(+1.0)); // FLD1
508 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
509 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
510 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
511 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
512 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
513 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
516 // Long double always uses X87.
518 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
519 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
520 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
523 APFloat TmpFlt(+0.0);
524 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
526 addLegalFPImmediate(TmpFlt); // FLD0
528 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
529 APFloat TmpFlt2(+1.0);
530 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
532 addLegalFPImmediate(TmpFlt2); // FLD1
533 TmpFlt2.changeSign();
534 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
538 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
539 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
543 // Always use a library call for pow.
544 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
545 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
546 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
548 setOperationAction(ISD::FLOG, MVT::f80, Expand);
549 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
550 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
551 setOperationAction(ISD::FEXP, MVT::f80, Expand);
552 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
554 // First set operation action for all vector types to either promote
555 // (for widening) or expand (for scalarization). Then we will selectively
556 // turn on ones that can be effectively codegen'd.
557 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
558 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
559 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
574 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
575 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
608 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
610 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
611 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
612 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
613 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
614 setTruncStoreAction((MVT::SimpleValueType)VT,
615 (MVT::SimpleValueType)InnerVT, Expand);
616 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
617 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
618 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
621 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
622 // with -msoft-float, disable use of MMX as well.
623 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
624 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass, false);
625 // No operations on x86mmx supported, everything uses intrinsics.
628 // MMX-sized vectors (other than x86mmx) are expected to be expanded
629 // into smaller operations.
630 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
631 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
632 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
633 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
634 setOperationAction(ISD::AND, MVT::v8i8, Expand);
635 setOperationAction(ISD::AND, MVT::v4i16, Expand);
636 setOperationAction(ISD::AND, MVT::v2i32, Expand);
637 setOperationAction(ISD::AND, MVT::v1i64, Expand);
638 setOperationAction(ISD::OR, MVT::v8i8, Expand);
639 setOperationAction(ISD::OR, MVT::v4i16, Expand);
640 setOperationAction(ISD::OR, MVT::v2i32, Expand);
641 setOperationAction(ISD::OR, MVT::v1i64, Expand);
642 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
643 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
644 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
645 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
646 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
650 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
651 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
652 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
653 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
654 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
655 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Expand);
656 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Expand);
657 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Expand);
658 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Expand);
660 if (!UseSoftFloat && Subtarget->hasSSE1()) {
661 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
663 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
664 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
665 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
666 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
667 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
668 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
669 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
671 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
672 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
673 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
674 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
677 if (!UseSoftFloat && Subtarget->hasSSE2()) {
678 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
680 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
681 // registers cannot be used even for integer operations.
682 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
683 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
684 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
685 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
687 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
688 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
689 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
690 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
691 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
692 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
693 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
694 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
695 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
696 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
697 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
698 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
699 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
700 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
701 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
702 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
704 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
705 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
707 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
709 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
710 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
712 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
715 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
716 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
717 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
718 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
719 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
721 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
722 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
723 EVT VT = (MVT::SimpleValueType)i;
724 // Do not attempt to custom lower non-power-of-2 vectors
725 if (!isPowerOf2_32(VT.getVectorNumElements()))
727 // Do not attempt to custom lower non-128-bit vectors
728 if (!VT.is128BitVector())
730 setOperationAction(ISD::BUILD_VECTOR,
731 VT.getSimpleVT().SimpleTy, Custom);
732 setOperationAction(ISD::VECTOR_SHUFFLE,
733 VT.getSimpleVT().SimpleTy, Custom);
734 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
735 VT.getSimpleVT().SimpleTy, Custom);
738 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
739 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
740 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
741 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
742 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
743 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
745 if (Subtarget->is64Bit()) {
746 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
747 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
750 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
751 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
752 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
755 // Do not attempt to promote non-128-bit vectors
756 if (!VT.is128BitVector())
759 setOperationAction(ISD::AND, SVT, Promote);
760 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
761 setOperationAction(ISD::OR, SVT, Promote);
762 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
763 setOperationAction(ISD::XOR, SVT, Promote);
764 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
765 setOperationAction(ISD::LOAD, SVT, Promote);
766 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
767 setOperationAction(ISD::SELECT, SVT, Promote);
768 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
771 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
773 // Custom lower v2i64 and v2f64 selects.
774 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
775 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
776 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
777 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
779 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
780 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
783 if (Subtarget->hasSSE41()) {
784 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
785 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
786 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
787 setOperationAction(ISD::FRINT, MVT::f32, Legal);
788 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
789 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
790 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
791 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
792 setOperationAction(ISD::FRINT, MVT::f64, Legal);
793 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
795 // FIXME: Do we need to handle scalar-to-vector here?
796 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
798 // Can turn SHL into an integer multiply.
799 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
800 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
802 // i8 and i16 vectors are custom , because the source register and source
803 // source memory operand types are not the same width. f32 vectors are
804 // custom since the immediate controlling the insert encodes additional
806 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
807 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
809 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
812 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
813 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
814 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
816 if (Subtarget->is64Bit()) {
817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
818 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
822 if (Subtarget->hasSSE42()) {
823 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
826 if (!UseSoftFloat && Subtarget->hasAVX()) {
827 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
828 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
829 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
830 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
831 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
833 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
834 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
835 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
836 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
837 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
838 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
839 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
840 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
841 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
842 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
843 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
844 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
845 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
846 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
847 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
849 // Operations to consider commented out -v16i16 v32i8
850 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
851 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
852 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
853 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
854 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
855 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
856 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
857 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
858 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
859 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
860 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
861 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
862 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
863 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
865 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
866 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
867 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
868 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
870 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
871 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
872 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
873 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
874 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
877 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
879 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
881 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
884 // Not sure we want to do this since there are no 256-bit integer
887 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
888 // This includes 256-bit vectors
889 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
890 EVT VT = (MVT::SimpleValueType)i;
892 // Do not attempt to custom lower non-power-of-2 vectors
893 if (!isPowerOf2_32(VT.getVectorNumElements()))
896 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
901 if (Subtarget->is64Bit()) {
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
903 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
908 // Not sure we want to do this since there are no 256-bit integer
911 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
912 // Including 256-bit vectors
913 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
914 EVT VT = (MVT::SimpleValueType)i;
916 if (!VT.is256BitVector()) {
919 setOperationAction(ISD::AND, VT, Promote);
920 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
921 setOperationAction(ISD::OR, VT, Promote);
922 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
923 setOperationAction(ISD::XOR, VT, Promote);
924 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
925 setOperationAction(ISD::LOAD, VT, Promote);
926 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
927 setOperationAction(ISD::SELECT, VT, Promote);
928 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
931 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
935 // We want to custom lower some of our intrinsics.
936 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
938 // Add/Sub/Mul with overflow operations are custom lowered.
939 setOperationAction(ISD::SADDO, MVT::i32, Custom);
940 setOperationAction(ISD::UADDO, MVT::i32, Custom);
941 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
942 setOperationAction(ISD::USUBO, MVT::i32, Custom);
943 setOperationAction(ISD::SMULO, MVT::i32, Custom);
945 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
946 // handle type legalization for these operations here.
948 // FIXME: We really should do custom legalization for addition and
949 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
950 // than generic legalization for 64-bit multiplication-with-overflow, though.
951 if (Subtarget->is64Bit()) {
952 setOperationAction(ISD::SADDO, MVT::i64, Custom);
953 setOperationAction(ISD::UADDO, MVT::i64, Custom);
954 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
955 setOperationAction(ISD::USUBO, MVT::i64, Custom);
956 setOperationAction(ISD::SMULO, MVT::i64, Custom);
959 if (!Subtarget->is64Bit()) {
960 // These libcalls are not available in 32-bit.
961 setLibcallName(RTLIB::SHL_I128, 0);
962 setLibcallName(RTLIB::SRL_I128, 0);
963 setLibcallName(RTLIB::SRA_I128, 0);
966 // We have target-specific dag combine patterns for the following nodes:
967 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
968 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
969 setTargetDAGCombine(ISD::BUILD_VECTOR);
970 setTargetDAGCombine(ISD::SELECT);
971 setTargetDAGCombine(ISD::SHL);
972 setTargetDAGCombine(ISD::SRA);
973 setTargetDAGCombine(ISD::SRL);
974 setTargetDAGCombine(ISD::OR);
975 setTargetDAGCombine(ISD::STORE);
976 setTargetDAGCombine(ISD::ZERO_EXTEND);
977 if (Subtarget->is64Bit())
978 setTargetDAGCombine(ISD::MUL);
980 computeRegisterProperties();
982 // FIXME: These should be based on subtarget info. Plus, the values should
983 // be smaller when we are in optimizing for size mode.
984 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
985 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
986 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
987 setPrefLoopAlignment(16);
988 benefitFromCodePlacementOpt = true;
992 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
997 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
998 /// the desired ByVal argument alignment.
999 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1002 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1003 if (VTy->getBitWidth() == 128)
1005 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1006 unsigned EltAlign = 0;
1007 getMaxByValAlign(ATy->getElementType(), EltAlign);
1008 if (EltAlign > MaxAlign)
1009 MaxAlign = EltAlign;
1010 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1011 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1012 unsigned EltAlign = 0;
1013 getMaxByValAlign(STy->getElementType(i), EltAlign);
1014 if (EltAlign > MaxAlign)
1015 MaxAlign = EltAlign;
1023 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1024 /// function arguments in the caller parameter area. For X86, aggregates
1025 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1026 /// are at 4-byte boundaries.
1027 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1028 if (Subtarget->is64Bit()) {
1029 // Max of 8 and alignment of type.
1030 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1037 if (Subtarget->hasSSE1())
1038 getMaxByValAlign(Ty, Align);
1042 /// getOptimalMemOpType - Returns the target specific optimal type for load
1043 /// and store operations as a result of memset, memcpy, and memmove
1044 /// lowering. If DstAlign is zero that means it's safe to destination
1045 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1046 /// means there isn't a need to check it against alignment requirement,
1047 /// probably because the source does not need to be loaded. If
1048 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1049 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1050 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1051 /// constant so it does not need to be loaded.
1052 /// It returns EVT::Other if the type should be determined using generic
1053 /// target-independent logic.
1055 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1056 unsigned DstAlign, unsigned SrcAlign,
1057 bool NonScalarIntSafe,
1059 MachineFunction &MF) const {
1060 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1061 // linux. This is because the stack realignment code can't handle certain
1062 // cases like PR2962. This should be removed when PR2962 is fixed.
1063 const Function *F = MF.getFunction();
1064 if (NonScalarIntSafe &&
1065 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1067 (Subtarget->isUnalignedMemAccessFast() ||
1068 ((DstAlign == 0 || DstAlign >= 16) &&
1069 (SrcAlign == 0 || SrcAlign >= 16))) &&
1070 Subtarget->getStackAlignment() >= 16) {
1071 if (Subtarget->hasSSE2())
1073 if (Subtarget->hasSSE1())
1075 } else if (!MemcpyStrSrc && Size >= 8 &&
1076 !Subtarget->is64Bit() &&
1077 Subtarget->getStackAlignment() >= 8 &&
1078 Subtarget->hasSSE2()) {
1079 // Do not use f64 to lower memcpy if source is string constant. It's
1080 // better to use i32 to avoid the loads.
1084 if (Subtarget->is64Bit() && Size >= 8)
1089 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1090 /// current function. The returned value is a member of the
1091 /// MachineJumpTableInfo::JTEntryKind enum.
1092 unsigned X86TargetLowering::getJumpTableEncoding() const {
1093 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1095 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1096 Subtarget->isPICStyleGOT())
1097 return MachineJumpTableInfo::EK_Custom32;
1099 // Otherwise, use the normal jump table encoding heuristics.
1100 return TargetLowering::getJumpTableEncoding();
1103 /// getPICBaseSymbol - Return the X86-32 PIC base.
1105 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1106 MCContext &Ctx) const {
1107 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1108 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1109 Twine(MF->getFunctionNumber())+"$pb");
1114 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1115 const MachineBasicBlock *MBB,
1116 unsigned uid,MCContext &Ctx) const{
1117 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1118 Subtarget->isPICStyleGOT());
1119 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1121 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1122 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1125 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1127 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1128 SelectionDAG &DAG) const {
1129 if (!Subtarget->is64Bit())
1130 // This doesn't have DebugLoc associated with it, but is not really the
1131 // same as a Register.
1132 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1136 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1137 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1139 const MCExpr *X86TargetLowering::
1140 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1141 MCContext &Ctx) const {
1142 // X86-64 uses RIP relative addressing based on the jump table label.
1143 if (Subtarget->isPICStyleRIPRel())
1144 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1146 // Otherwise, the reference is relative to the PIC base.
1147 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1150 /// getFunctionAlignment - Return the Log2 alignment of this function.
1151 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1152 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1155 std::pair<const TargetRegisterClass*, uint8_t>
1156 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1157 const TargetRegisterClass *RRC = 0;
1159 switch (VT.getSimpleVT().SimpleTy) {
1161 return TargetLowering::findRepresentativeClass(VT);
1162 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1163 RRC = (Subtarget->is64Bit()
1164 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1167 RRC = X86::VR64RegisterClass;
1169 case MVT::f32: case MVT::f64:
1170 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1171 case MVT::v4f32: case MVT::v2f64:
1172 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1174 RRC = X86::VR128RegisterClass;
1177 return std::make_pair(RRC, Cost);
1181 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1182 MachineFunction &MF) const {
1183 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
1184 switch (RC->getID()) {
1187 case X86::GR32RegClassID:
1189 case X86::GR64RegClassID:
1191 case X86::VR128RegClassID:
1192 return Subtarget->is64Bit() ? 10 : 4;
1193 case X86::VR64RegClassID:
1198 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1199 unsigned &Offset) const {
1200 if (!Subtarget->isTargetLinux())
1203 if (Subtarget->is64Bit()) {
1204 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1206 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1219 //===----------------------------------------------------------------------===//
1220 // Return Value Calling Convention Implementation
1221 //===----------------------------------------------------------------------===//
1223 #include "X86GenCallingConv.inc"
1226 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1227 const SmallVectorImpl<ISD::OutputArg> &Outs,
1228 LLVMContext &Context) const {
1229 SmallVector<CCValAssign, 16> RVLocs;
1230 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1232 return CCInfo.CheckReturn(Outs, RetCC_X86);
1236 X86TargetLowering::LowerReturn(SDValue Chain,
1237 CallingConv::ID CallConv, bool isVarArg,
1238 const SmallVectorImpl<ISD::OutputArg> &Outs,
1239 const SmallVectorImpl<SDValue> &OutVals,
1240 DebugLoc dl, SelectionDAG &DAG) const {
1241 MachineFunction &MF = DAG.getMachineFunction();
1242 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1244 SmallVector<CCValAssign, 16> RVLocs;
1245 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1246 RVLocs, *DAG.getContext());
1247 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1249 // Add the regs to the liveout set for the function.
1250 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1251 for (unsigned i = 0; i != RVLocs.size(); ++i)
1252 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1253 MRI.addLiveOut(RVLocs[i].getLocReg());
1257 SmallVector<SDValue, 6> RetOps;
1258 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1259 // Operand #1 = Bytes To Pop
1260 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1263 // Copy the result values into the output registers.
1264 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1265 CCValAssign &VA = RVLocs[i];
1266 assert(VA.isRegLoc() && "Can only return in registers!");
1267 SDValue ValToCopy = OutVals[i];
1268 EVT ValVT = ValToCopy.getValueType();
1270 // If this is x86-64, and we disabled SSE, we can't return FP values,
1271 // or SSE or MMX vectors.
1272 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1273 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1274 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1275 report_fatal_error("SSE register return with SSE disabled");
1277 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1278 // llvm-gcc has never done it right and no one has noticed, so this
1279 // should be OK for now.
1280 if (ValVT == MVT::f64 &&
1281 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1282 report_fatal_error("SSE2 register return with SSE2 disabled");
1284 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1285 // the RET instruction and handled by the FP Stackifier.
1286 if (VA.getLocReg() == X86::ST0 ||
1287 VA.getLocReg() == X86::ST1) {
1288 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1289 // change the value to the FP stack register class.
1290 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1291 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1292 RetOps.push_back(ValToCopy);
1293 // Don't emit a copytoreg.
1297 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1298 // which is returned in RAX / RDX.
1299 if (Subtarget->is64Bit()) {
1300 if (ValVT == MVT::x86mmx) {
1301 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1302 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1303 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1305 // If we don't have SSE2 available, convert to v4f32 so the generated
1306 // register is legal.
1307 if (!Subtarget->hasSSE2())
1308 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy);
1313 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1314 Flag = Chain.getValue(1);
1317 // The x86-64 ABI for returning structs by value requires that we copy
1318 // the sret argument into %rax for the return. We saved the argument into
1319 // a virtual register in the entry block, so now we copy the value out
1321 if (Subtarget->is64Bit() &&
1322 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1323 MachineFunction &MF = DAG.getMachineFunction();
1324 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1325 unsigned Reg = FuncInfo->getSRetReturnReg();
1327 "SRetReturnReg should have been set in LowerFormalArguments().");
1328 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1330 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1331 Flag = Chain.getValue(1);
1333 // RAX now acts like a return value.
1334 MRI.addLiveOut(X86::RAX);
1337 RetOps[0] = Chain; // Update chain.
1339 // Add the flag if we have it.
1341 RetOps.push_back(Flag);
1343 return DAG.getNode(X86ISD::RET_FLAG, dl,
1344 MVT::Other, &RetOps[0], RetOps.size());
1347 /// LowerCallResult - Lower the result values of a call into the
1348 /// appropriate copies out of appropriate physical registers.
1351 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1352 CallingConv::ID CallConv, bool isVarArg,
1353 const SmallVectorImpl<ISD::InputArg> &Ins,
1354 DebugLoc dl, SelectionDAG &DAG,
1355 SmallVectorImpl<SDValue> &InVals) const {
1357 // Assign locations to each value returned by this call.
1358 SmallVector<CCValAssign, 16> RVLocs;
1359 bool Is64Bit = Subtarget->is64Bit();
1360 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1361 RVLocs, *DAG.getContext());
1362 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1364 // Copy all of the result registers out of their specified physreg.
1365 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1366 CCValAssign &VA = RVLocs[i];
1367 EVT CopyVT = VA.getValVT();
1369 // If this is x86-64, and we disabled SSE, we can't return FP values
1370 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1371 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1372 report_fatal_error("SSE register return with SSE disabled");
1377 // If this is a call to a function that returns an fp value on the floating
1378 // point stack, we must guarantee the the value is popped from the stack, so
1379 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1380 // if the return value is not used. We use the FpGET_ST0 instructions
1382 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1383 // If we prefer to use the value in xmm registers, copy it out as f80 and
1384 // use a truncate to move it from fp stack reg to xmm reg.
1385 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1386 bool isST0 = VA.getLocReg() == X86::ST0;
1388 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1389 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1390 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1391 SDValue Ops[] = { Chain, InFlag };
1392 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1394 Val = Chain.getValue(0);
1396 // Round the f80 to the right size, which also moves it to the appropriate
1398 if (CopyVT != VA.getValVT())
1399 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1400 // This truncation won't change the value.
1401 DAG.getIntPtrConstant(1));
1402 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1403 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1404 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1405 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1406 MVT::v2i64, InFlag).getValue(1);
1407 Val = Chain.getValue(0);
1408 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1409 Val, DAG.getConstant(0, MVT::i64));
1411 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1412 MVT::i64, InFlag).getValue(1);
1413 Val = Chain.getValue(0);
1415 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1417 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1418 CopyVT, InFlag).getValue(1);
1419 Val = Chain.getValue(0);
1421 InFlag = Chain.getValue(2);
1422 InVals.push_back(Val);
1429 //===----------------------------------------------------------------------===//
1430 // C & StdCall & Fast Calling Convention implementation
1431 //===----------------------------------------------------------------------===//
1432 // StdCall calling convention seems to be standard for many Windows' API
1433 // routines and around. It differs from C calling convention just a little:
1434 // callee should clean up the stack, not caller. Symbols should be also
1435 // decorated in some fancy way :) It doesn't support any vector arguments.
1436 // For info on fast calling convention see Fast Calling Convention (tail call)
1437 // implementation LowerX86_32FastCCCallTo.
1439 /// CallIsStructReturn - Determines whether a call uses struct return
1441 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1445 return Outs[0].Flags.isSRet();
1448 /// ArgsAreStructReturn - Determines whether a function uses struct
1449 /// return semantics.
1451 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1455 return Ins[0].Flags.isSRet();
1458 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1459 /// given CallingConvention value.
1460 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1461 if (Subtarget->is64Bit()) {
1462 if (CC == CallingConv::GHC)
1463 return CC_X86_64_GHC;
1464 else if (Subtarget->isTargetWin64())
1465 return CC_X86_Win64_C;
1470 if (CC == CallingConv::X86_FastCall)
1471 return CC_X86_32_FastCall;
1472 else if (CC == CallingConv::X86_ThisCall)
1473 return CC_X86_32_ThisCall;
1474 else if (CC == CallingConv::Fast)
1475 return CC_X86_32_FastCC;
1476 else if (CC == CallingConv::GHC)
1477 return CC_X86_32_GHC;
1482 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1483 /// by "Src" to address "Dst" with size and alignment information specified by
1484 /// the specific parameter attribute. The copy will be passed as a byval
1485 /// function parameter.
1487 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1488 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1490 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1492 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1493 /*isVolatile*/false, /*AlwaysInline=*/true,
1494 MachinePointerInfo(), MachinePointerInfo());
1497 /// IsTailCallConvention - Return true if the calling convention is one that
1498 /// supports tail call optimization.
1499 static bool IsTailCallConvention(CallingConv::ID CC) {
1500 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1503 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1504 /// a tailcall target by changing its ABI.
1505 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1506 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1510 X86TargetLowering::LowerMemArgument(SDValue Chain,
1511 CallingConv::ID CallConv,
1512 const SmallVectorImpl<ISD::InputArg> &Ins,
1513 DebugLoc dl, SelectionDAG &DAG,
1514 const CCValAssign &VA,
1515 MachineFrameInfo *MFI,
1517 // Create the nodes corresponding to a load from this parameter slot.
1518 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1519 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1520 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1523 // If value is passed by pointer we have address passed instead of the value
1525 if (VA.getLocInfo() == CCValAssign::Indirect)
1526 ValVT = VA.getLocVT();
1528 ValVT = VA.getValVT();
1530 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1531 // changed with more analysis.
1532 // In case of tail call optimization mark all arguments mutable. Since they
1533 // could be overwritten by lowering of arguments in case of a tail call.
1534 if (Flags.isByVal()) {
1535 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1536 VA.getLocMemOffset(), isImmutable);
1537 return DAG.getFrameIndex(FI, getPointerTy());
1539 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1540 VA.getLocMemOffset(), isImmutable);
1541 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1542 return DAG.getLoad(ValVT, dl, Chain, FIN,
1543 MachinePointerInfo::getFixedStack(FI),
1549 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1550 CallingConv::ID CallConv,
1552 const SmallVectorImpl<ISD::InputArg> &Ins,
1555 SmallVectorImpl<SDValue> &InVals)
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1560 const Function* Fn = MF.getFunction();
1561 if (Fn->hasExternalLinkage() &&
1562 Subtarget->isTargetCygMing() &&
1563 Fn->getName() == "main")
1564 FuncInfo->setForceFramePointer(true);
1566 MachineFrameInfo *MFI = MF.getFrameInfo();
1567 bool Is64Bit = Subtarget->is64Bit();
1568 bool IsWin64 = Subtarget->isTargetWin64();
1570 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1571 "Var args not supported with calling convention fastcc or ghc");
1573 // Assign locations to all of the incoming arguments.
1574 SmallVector<CCValAssign, 16> ArgLocs;
1575 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1576 ArgLocs, *DAG.getContext());
1577 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1579 unsigned LastVal = ~0U;
1581 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1582 CCValAssign &VA = ArgLocs[i];
1583 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1585 assert(VA.getValNo() != LastVal &&
1586 "Don't support value assigned to multiple locs yet");
1587 LastVal = VA.getValNo();
1589 if (VA.isRegLoc()) {
1590 EVT RegVT = VA.getLocVT();
1591 TargetRegisterClass *RC = NULL;
1592 if (RegVT == MVT::i32)
1593 RC = X86::GR32RegisterClass;
1594 else if (Is64Bit && RegVT == MVT::i64)
1595 RC = X86::GR64RegisterClass;
1596 else if (RegVT == MVT::f32)
1597 RC = X86::FR32RegisterClass;
1598 else if (RegVT == MVT::f64)
1599 RC = X86::FR64RegisterClass;
1600 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1601 RC = X86::VR256RegisterClass;
1602 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1603 RC = X86::VR128RegisterClass;
1604 else if (RegVT == MVT::x86mmx)
1605 RC = X86::VR64RegisterClass;
1607 llvm_unreachable("Unknown argument type!");
1609 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1610 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1612 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1613 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1615 if (VA.getLocInfo() == CCValAssign::SExt)
1616 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1617 DAG.getValueType(VA.getValVT()));
1618 else if (VA.getLocInfo() == CCValAssign::ZExt)
1619 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1620 DAG.getValueType(VA.getValVT()));
1621 else if (VA.getLocInfo() == CCValAssign::BCvt)
1622 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1624 if (VA.isExtInLoc()) {
1625 // Handle MMX values passed in XMM regs.
1626 if (RegVT.isVector()) {
1627 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1630 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1633 assert(VA.isMemLoc());
1634 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1637 // If value is passed via pointer - do a load.
1638 if (VA.getLocInfo() == CCValAssign::Indirect)
1639 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1640 MachinePointerInfo(), false, false, 0);
1642 InVals.push_back(ArgValue);
1645 // The x86-64 ABI for returning structs by value requires that we copy
1646 // the sret argument into %rax for the return. Save the argument into
1647 // a virtual register so that we can access it from the return points.
1648 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1649 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1650 unsigned Reg = FuncInfo->getSRetReturnReg();
1652 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1653 FuncInfo->setSRetReturnReg(Reg);
1655 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1656 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1659 unsigned StackSize = CCInfo.getNextStackOffset();
1660 // Align stack specially for tail calls.
1661 if (FuncIsMadeTailCallSafe(CallConv))
1662 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1664 // If the function takes variable number of arguments, make a frame index for
1665 // the start of the first vararg value... for expansion of llvm.va_start.
1667 if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1668 CallConv != CallingConv::X86_ThisCall))) {
1669 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1672 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1674 // FIXME: We should really autogenerate these arrays
1675 static const unsigned GPR64ArgRegsWin64[] = {
1676 X86::RCX, X86::RDX, X86::R8, X86::R9
1678 static const unsigned GPR64ArgRegs64Bit[] = {
1679 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1681 static const unsigned XMMArgRegs64Bit[] = {
1682 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1683 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1685 const unsigned *GPR64ArgRegs;
1686 unsigned NumXMMRegs = 0;
1689 // The XMM registers which might contain var arg parameters are shadowed
1690 // in their paired GPR. So we only need to save the GPR to their home
1692 TotalNumIntRegs = 4;
1693 GPR64ArgRegs = GPR64ArgRegsWin64;
1695 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1696 GPR64ArgRegs = GPR64ArgRegs64Bit;
1698 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1700 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1703 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1704 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1705 "SSE register cannot be used when SSE is disabled!");
1706 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1707 "SSE register cannot be used when SSE is disabled!");
1708 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1709 // Kernel mode asks for SSE to be disabled, so don't push them
1711 TotalNumXMMRegs = 0;
1714 const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo();
1715 // Get to the caller-allocated home save location. Add 8 to account
1716 // for the return address.
1717 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1718 FuncInfo->setRegSaveFrameIndex(
1719 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1720 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1722 // For X86-64, if there are vararg parameters that are passed via
1723 // registers, then we must store them to their spots on the stack so they
1724 // may be loaded by deferencing the result of va_next.
1725 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1726 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1727 FuncInfo->setRegSaveFrameIndex(
1728 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1732 // Store the integer parameter registers.
1733 SmallVector<SDValue, 8> MemOps;
1734 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1736 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1737 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1738 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1739 DAG.getIntPtrConstant(Offset));
1740 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1741 X86::GR64RegisterClass);
1742 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1744 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1745 MachinePointerInfo::getFixedStack(
1746 FuncInfo->getRegSaveFrameIndex(), Offset),
1748 MemOps.push_back(Store);
1752 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1753 // Now store the XMM (fp + vector) parameter registers.
1754 SmallVector<SDValue, 11> SaveXMMOps;
1755 SaveXMMOps.push_back(Chain);
1757 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1758 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1759 SaveXMMOps.push_back(ALVal);
1761 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1762 FuncInfo->getRegSaveFrameIndex()));
1763 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1764 FuncInfo->getVarArgsFPOffset()));
1766 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1767 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1768 X86::VR128RegisterClass);
1769 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1770 SaveXMMOps.push_back(Val);
1772 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1774 &SaveXMMOps[0], SaveXMMOps.size()));
1777 if (!MemOps.empty())
1778 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1779 &MemOps[0], MemOps.size());
1783 // Some CCs need callee pop.
1784 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1785 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1787 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1788 // If this is an sret function, the return should pop the hidden pointer.
1789 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1790 FuncInfo->setBytesToPopOnReturn(4);
1794 // RegSaveFrameIndex is X86-64 only.
1795 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1796 if (CallConv == CallingConv::X86_FastCall ||
1797 CallConv == CallingConv::X86_ThisCall)
1798 // fastcc functions can't have varargs.
1799 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1806 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1807 SDValue StackPtr, SDValue Arg,
1808 DebugLoc dl, SelectionDAG &DAG,
1809 const CCValAssign &VA,
1810 ISD::ArgFlagsTy Flags) const {
1811 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1812 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1813 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1814 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1815 if (Flags.isByVal())
1816 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1818 return DAG.getStore(Chain, dl, Arg, PtrOff,
1819 MachinePointerInfo::getStack(LocMemOffset),
1823 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1824 /// optimization is performed and it is required.
1826 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1827 SDValue &OutRetAddr, SDValue Chain,
1828 bool IsTailCall, bool Is64Bit,
1829 int FPDiff, DebugLoc dl) const {
1830 // Adjust the Return address stack slot.
1831 EVT VT = getPointerTy();
1832 OutRetAddr = getReturnAddressFrameIndex(DAG);
1834 // Load the "old" Return address.
1835 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1837 return SDValue(OutRetAddr.getNode(), 1);
1840 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1841 /// optimization is performed and it is required (FPDiff!=0).
1843 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1844 SDValue Chain, SDValue RetAddrFrIdx,
1845 bool Is64Bit, int FPDiff, DebugLoc dl) {
1846 // Store the return address to the appropriate stack slot.
1847 if (!FPDiff) return Chain;
1848 // Calculate the new stack slot for the return address.
1849 int SlotSize = Is64Bit ? 8 : 4;
1850 int NewReturnAddrFI =
1851 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1852 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1853 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1854 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1855 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1861 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1862 CallingConv::ID CallConv, bool isVarArg,
1864 const SmallVectorImpl<ISD::OutputArg> &Outs,
1865 const SmallVectorImpl<SDValue> &OutVals,
1866 const SmallVectorImpl<ISD::InputArg> &Ins,
1867 DebugLoc dl, SelectionDAG &DAG,
1868 SmallVectorImpl<SDValue> &InVals) const {
1869 MachineFunction &MF = DAG.getMachineFunction();
1870 bool Is64Bit = Subtarget->is64Bit();
1871 bool IsStructRet = CallIsStructReturn(Outs);
1872 bool IsSibcall = false;
1875 // Check if it's really possible to do a tail call.
1876 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1877 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1878 Outs, OutVals, Ins, DAG);
1880 // Sibcalls are automatically detected tailcalls which do not require
1882 if (!GuaranteedTailCallOpt && isTailCall)
1889 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1890 "Var args not supported with calling convention fastcc or ghc");
1892 // Analyze operands of the call, assigning locations to each operand.
1893 SmallVector<CCValAssign, 16> ArgLocs;
1894 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1895 ArgLocs, *DAG.getContext());
1896 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1898 // Get a count of how many bytes are to be pushed on the stack.
1899 unsigned NumBytes = CCInfo.getNextStackOffset();
1901 // This is a sibcall. The memory operands are available in caller's
1902 // own caller's stack.
1904 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1905 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1908 if (isTailCall && !IsSibcall) {
1909 // Lower arguments at fp - stackoffset + fpdiff.
1910 unsigned NumBytesCallerPushed =
1911 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1912 FPDiff = NumBytesCallerPushed - NumBytes;
1914 // Set the delta of movement of the returnaddr stackslot.
1915 // But only set if delta is greater than previous delta.
1916 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1917 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1921 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1923 SDValue RetAddrFrIdx;
1924 // Load return adress for tail calls.
1925 if (isTailCall && FPDiff)
1926 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1927 Is64Bit, FPDiff, dl);
1929 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1930 SmallVector<SDValue, 8> MemOpChains;
1933 // Walk the register/memloc assignments, inserting copies/loads. In the case
1934 // of tail call optimization arguments are handle later.
1935 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1936 CCValAssign &VA = ArgLocs[i];
1937 EVT RegVT = VA.getLocVT();
1938 SDValue Arg = OutVals[i];
1939 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1940 bool isByVal = Flags.isByVal();
1942 // Promote the value if needed.
1943 switch (VA.getLocInfo()) {
1944 default: llvm_unreachable("Unknown loc info!");
1945 case CCValAssign::Full: break;
1946 case CCValAssign::SExt:
1947 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1949 case CCValAssign::ZExt:
1950 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1952 case CCValAssign::AExt:
1953 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1954 // Special case: passing MMX values in XMM registers.
1955 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1956 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1957 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1959 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1961 case CCValAssign::BCvt:
1962 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1964 case CCValAssign::Indirect: {
1965 // Store the argument.
1966 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1967 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1968 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1969 MachinePointerInfo::getFixedStack(FI),
1976 if (VA.isRegLoc()) {
1977 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1978 if (isVarArg && Subtarget->isTargetWin64()) {
1979 // Win64 ABI requires argument XMM reg to be copied to the corresponding
1980 // shadow reg if callee is a varargs function.
1981 unsigned ShadowReg = 0;
1982 switch (VA.getLocReg()) {
1983 case X86::XMM0: ShadowReg = X86::RCX; break;
1984 case X86::XMM1: ShadowReg = X86::RDX; break;
1985 case X86::XMM2: ShadowReg = X86::R8; break;
1986 case X86::XMM3: ShadowReg = X86::R9; break;
1989 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
1991 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1992 assert(VA.isMemLoc());
1993 if (StackPtr.getNode() == 0)
1994 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1995 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1996 dl, DAG, VA, Flags));
2000 if (!MemOpChains.empty())
2001 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2002 &MemOpChains[0], MemOpChains.size());
2004 // Build a sequence of copy-to-reg nodes chained together with token chain
2005 // and flag operands which copy the outgoing args into registers.
2007 // Tail call byval lowering might overwrite argument registers so in case of
2008 // tail call optimization the copies to registers are lowered later.
2010 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2011 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2012 RegsToPass[i].second, InFlag);
2013 InFlag = Chain.getValue(1);
2016 if (Subtarget->isPICStyleGOT()) {
2017 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2020 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2021 DAG.getNode(X86ISD::GlobalBaseReg,
2022 DebugLoc(), getPointerTy()),
2024 InFlag = Chain.getValue(1);
2026 // If we are tail calling and generating PIC/GOT style code load the
2027 // address of the callee into ECX. The value in ecx is used as target of
2028 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2029 // for tail calls on PIC/GOT architectures. Normally we would just put the
2030 // address of GOT into ebx and then call target@PLT. But for tail calls
2031 // ebx would be restored (since ebx is callee saved) before jumping to the
2034 // Note: The actual moving to ECX is done further down.
2035 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2036 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2037 !G->getGlobal()->hasProtectedVisibility())
2038 Callee = LowerGlobalAddress(Callee, DAG);
2039 else if (isa<ExternalSymbolSDNode>(Callee))
2040 Callee = LowerExternalSymbol(Callee, DAG);
2044 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2045 // From AMD64 ABI document:
2046 // For calls that may call functions that use varargs or stdargs
2047 // (prototype-less calls or calls to functions containing ellipsis (...) in
2048 // the declaration) %al is used as hidden argument to specify the number
2049 // of SSE registers used. The contents of %al do not need to match exactly
2050 // the number of registers, but must be an ubound on the number of SSE
2051 // registers used and is in the range 0 - 8 inclusive.
2053 // Count the number of XMM registers allocated.
2054 static const unsigned XMMArgRegs[] = {
2055 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2056 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2058 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2059 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2060 && "SSE registers cannot be used when SSE is disabled");
2062 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2063 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2064 InFlag = Chain.getValue(1);
2068 // For tail calls lower the arguments to the 'real' stack slot.
2070 // Force all the incoming stack arguments to be loaded from the stack
2071 // before any new outgoing arguments are stored to the stack, because the
2072 // outgoing stack slots may alias the incoming argument stack slots, and
2073 // the alias isn't otherwise explicit. This is slightly more conservative
2074 // than necessary, because it means that each store effectively depends
2075 // on every argument instead of just those arguments it would clobber.
2076 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2078 SmallVector<SDValue, 8> MemOpChains2;
2081 // Do not flag preceeding copytoreg stuff together with the following stuff.
2083 if (GuaranteedTailCallOpt) {
2084 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2085 CCValAssign &VA = ArgLocs[i];
2088 assert(VA.isMemLoc());
2089 SDValue Arg = OutVals[i];
2090 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2091 // Create frame index.
2092 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2093 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2094 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2095 FIN = DAG.getFrameIndex(FI, getPointerTy());
2097 if (Flags.isByVal()) {
2098 // Copy relative to framepointer.
2099 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2100 if (StackPtr.getNode() == 0)
2101 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2103 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2105 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2109 // Store relative to framepointer.
2110 MemOpChains2.push_back(
2111 DAG.getStore(ArgChain, dl, Arg, FIN,
2112 MachinePointerInfo::getFixedStack(FI),
2118 if (!MemOpChains2.empty())
2119 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2120 &MemOpChains2[0], MemOpChains2.size());
2122 // Copy arguments to their registers.
2123 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2124 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2125 RegsToPass[i].second, InFlag);
2126 InFlag = Chain.getValue(1);
2130 // Store the return address to the appropriate stack slot.
2131 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2135 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2136 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2137 // In the 64-bit large code model, we have to make all calls
2138 // through a register, since the call instruction's 32-bit
2139 // pc-relative offset may not be large enough to hold the whole
2141 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2142 // If the callee is a GlobalAddress node (quite common, every direct call
2143 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2146 // We should use extra load for direct calls to dllimported functions in
2148 const GlobalValue *GV = G->getGlobal();
2149 if (!GV->hasDLLImportLinkage()) {
2150 unsigned char OpFlags = 0;
2152 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2153 // external symbols most go through the PLT in PIC mode. If the symbol
2154 // has hidden or protected visibility, or if it is static or local, then
2155 // we don't need to use the PLT - we can directly call it.
2156 if (Subtarget->isTargetELF() &&
2157 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2158 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2159 OpFlags = X86II::MO_PLT;
2160 } else if (Subtarget->isPICStyleStubAny() &&
2161 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2162 Subtarget->getDarwinVers() < 9) {
2163 // PC-relative references to external symbols should go through $stub,
2164 // unless we're building with the leopard linker or later, which
2165 // automatically synthesizes these stubs.
2166 OpFlags = X86II::MO_DARWIN_STUB;
2169 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2170 G->getOffset(), OpFlags);
2172 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2173 unsigned char OpFlags = 0;
2175 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2176 // symbols should go through the PLT.
2177 if (Subtarget->isTargetELF() &&
2178 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2179 OpFlags = X86II::MO_PLT;
2180 } else if (Subtarget->isPICStyleStubAny() &&
2181 Subtarget->getDarwinVers() < 9) {
2182 // PC-relative references to external symbols should go through $stub,
2183 // unless we're building with the leopard linker or later, which
2184 // automatically synthesizes these stubs.
2185 OpFlags = X86II::MO_DARWIN_STUB;
2188 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2192 // Returns a chain & a flag for retval copy to use.
2193 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2194 SmallVector<SDValue, 8> Ops;
2196 if (!IsSibcall && isTailCall) {
2197 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2198 DAG.getIntPtrConstant(0, true), InFlag);
2199 InFlag = Chain.getValue(1);
2202 Ops.push_back(Chain);
2203 Ops.push_back(Callee);
2206 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2208 // Add argument registers to the end of the list so that they are known live
2210 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2211 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2212 RegsToPass[i].second.getValueType()));
2214 // Add an implicit use GOT pointer in EBX.
2215 if (!isTailCall && Subtarget->isPICStyleGOT())
2216 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2218 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2219 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2220 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2222 if (InFlag.getNode())
2223 Ops.push_back(InFlag);
2227 //// If this is the first return lowered for this function, add the regs
2228 //// to the liveout set for the function.
2229 // This isn't right, although it's probably harmless on x86; liveouts
2230 // should be computed from returns not tail calls. Consider a void
2231 // function making a tail call to a function returning int.
2232 return DAG.getNode(X86ISD::TC_RETURN, dl,
2233 NodeTys, &Ops[0], Ops.size());
2236 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2237 InFlag = Chain.getValue(1);
2239 // Create the CALLSEQ_END node.
2240 unsigned NumBytesForCalleeToPush;
2241 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2242 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2243 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2244 // If this is a call to a struct-return function, the callee
2245 // pops the hidden struct pointer, so we have to push it back.
2246 // This is common for Darwin/X86, Linux & Mingw32 targets.
2247 NumBytesForCalleeToPush = 4;
2249 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2251 // Returns a flag for retval copy to use.
2253 Chain = DAG.getCALLSEQ_END(Chain,
2254 DAG.getIntPtrConstant(NumBytes, true),
2255 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2258 InFlag = Chain.getValue(1);
2261 // Handle result values, copying them out of physregs into vregs that we
2263 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2264 Ins, dl, DAG, InVals);
2268 //===----------------------------------------------------------------------===//
2269 // Fast Calling Convention (tail call) implementation
2270 //===----------------------------------------------------------------------===//
2272 // Like std call, callee cleans arguments, convention except that ECX is
2273 // reserved for storing the tail called function address. Only 2 registers are
2274 // free for argument passing (inreg). Tail call optimization is performed
2276 // * tailcallopt is enabled
2277 // * caller/callee are fastcc
2278 // On X86_64 architecture with GOT-style position independent code only local
2279 // (within module) calls are supported at the moment.
2280 // To keep the stack aligned according to platform abi the function
2281 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2282 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2283 // If a tail called function callee has more arguments than the caller the
2284 // caller needs to make sure that there is room to move the RETADDR to. This is
2285 // achieved by reserving an area the size of the argument delta right after the
2286 // original REtADDR, but before the saved framepointer or the spilled registers
2287 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2299 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2300 /// for a 16 byte align requirement.
2302 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2303 SelectionDAG& DAG) const {
2304 MachineFunction &MF = DAG.getMachineFunction();
2305 const TargetMachine &TM = MF.getTarget();
2306 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2307 unsigned StackAlignment = TFI.getStackAlignment();
2308 uint64_t AlignMask = StackAlignment - 1;
2309 int64_t Offset = StackSize;
2310 uint64_t SlotSize = TD->getPointerSize();
2311 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2312 // Number smaller than 12 so just add the difference.
2313 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2315 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2316 Offset = ((~AlignMask) & Offset) + StackAlignment +
2317 (StackAlignment-SlotSize);
2322 /// MatchingStackOffset - Return true if the given stack call argument is
2323 /// already available in the same position (relatively) of the caller's
2324 /// incoming argument stack.
2326 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2327 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2328 const X86InstrInfo *TII) {
2329 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2331 if (Arg.getOpcode() == ISD::CopyFromReg) {
2332 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2333 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2335 MachineInstr *Def = MRI->getVRegDef(VR);
2338 if (!Flags.isByVal()) {
2339 if (!TII->isLoadFromStackSlot(Def, FI))
2342 unsigned Opcode = Def->getOpcode();
2343 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2344 Def->getOperand(1).isFI()) {
2345 FI = Def->getOperand(1).getIndex();
2346 Bytes = Flags.getByValSize();
2350 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2351 if (Flags.isByVal())
2352 // ByVal argument is passed in as a pointer but it's now being
2353 // dereferenced. e.g.
2354 // define @foo(%struct.X* %A) {
2355 // tail call @bar(%struct.X* byval %A)
2358 SDValue Ptr = Ld->getBasePtr();
2359 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2362 FI = FINode->getIndex();
2366 assert(FI != INT_MAX);
2367 if (!MFI->isFixedObjectIndex(FI))
2369 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2372 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2373 /// for tail call optimization. Targets which want to do tail call
2374 /// optimization should implement this function.
2376 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2377 CallingConv::ID CalleeCC,
2379 bool isCalleeStructRet,
2380 bool isCallerStructRet,
2381 const SmallVectorImpl<ISD::OutputArg> &Outs,
2382 const SmallVectorImpl<SDValue> &OutVals,
2383 const SmallVectorImpl<ISD::InputArg> &Ins,
2384 SelectionDAG& DAG) const {
2385 if (!IsTailCallConvention(CalleeCC) &&
2386 CalleeCC != CallingConv::C)
2389 // If -tailcallopt is specified, make fastcc functions tail-callable.
2390 const MachineFunction &MF = DAG.getMachineFunction();
2391 const Function *CallerF = DAG.getMachineFunction().getFunction();
2392 CallingConv::ID CallerCC = CallerF->getCallingConv();
2393 bool CCMatch = CallerCC == CalleeCC;
2395 if (GuaranteedTailCallOpt) {
2396 if (IsTailCallConvention(CalleeCC) && CCMatch)
2401 // Look for obvious safe cases to perform tail call optimization that do not
2402 // require ABI changes. This is what gcc calls sibcall.
2404 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2405 // emit a special epilogue.
2406 if (RegInfo->needsStackRealignment(MF))
2409 // Do not sibcall optimize vararg calls unless the call site is not passing
2411 if (isVarArg && !Outs.empty())
2414 // Also avoid sibcall optimization if either caller or callee uses struct
2415 // return semantics.
2416 if (isCalleeStructRet || isCallerStructRet)
2419 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2420 // Therefore if it's not used by the call it is not safe to optimize this into
2422 bool Unused = false;
2423 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2430 SmallVector<CCValAssign, 16> RVLocs;
2431 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2432 RVLocs, *DAG.getContext());
2433 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2434 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2435 CCValAssign &VA = RVLocs[i];
2436 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2441 // If the calling conventions do not match, then we'd better make sure the
2442 // results are returned in the same way as what the caller expects.
2444 SmallVector<CCValAssign, 16> RVLocs1;
2445 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2446 RVLocs1, *DAG.getContext());
2447 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2449 SmallVector<CCValAssign, 16> RVLocs2;
2450 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2451 RVLocs2, *DAG.getContext());
2452 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2454 if (RVLocs1.size() != RVLocs2.size())
2456 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2457 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2459 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2461 if (RVLocs1[i].isRegLoc()) {
2462 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2465 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2471 // If the callee takes no arguments then go on to check the results of the
2473 if (!Outs.empty()) {
2474 // Check if stack adjustment is needed. For now, do not do this if any
2475 // argument is passed on the stack.
2476 SmallVector<CCValAssign, 16> ArgLocs;
2477 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2478 ArgLocs, *DAG.getContext());
2479 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2480 if (CCInfo.getNextStackOffset()) {
2481 MachineFunction &MF = DAG.getMachineFunction();
2482 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2484 if (Subtarget->isTargetWin64())
2485 // Win64 ABI has additional complications.
2488 // Check if the arguments are already laid out in the right way as
2489 // the caller's fixed stack objects.
2490 MachineFrameInfo *MFI = MF.getFrameInfo();
2491 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2492 const X86InstrInfo *TII =
2493 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 CCValAssign &VA = ArgLocs[i];
2496 SDValue Arg = OutVals[i];
2497 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2498 if (VA.getLocInfo() == CCValAssign::Indirect)
2500 if (!VA.isRegLoc()) {
2501 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2508 // If the tailcall address may be in a register, then make sure it's
2509 // possible to register allocate for it. In 32-bit, the call address can
2510 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2511 // callee-saved registers are restored. These happen to be the same
2512 // registers used to pass 'inreg' arguments so watch out for those.
2513 if (!Subtarget->is64Bit() &&
2514 !isa<GlobalAddressSDNode>(Callee) &&
2515 !isa<ExternalSymbolSDNode>(Callee)) {
2516 unsigned NumInRegs = 0;
2517 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2518 CCValAssign &VA = ArgLocs[i];
2521 unsigned Reg = VA.getLocReg();
2524 case X86::EAX: case X86::EDX: case X86::ECX:
2525 if (++NumInRegs == 3)
2537 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2538 return X86::createFastISel(funcInfo);
2542 //===----------------------------------------------------------------------===//
2543 // Other Lowering Hooks
2544 //===----------------------------------------------------------------------===//
2546 static bool MayFoldLoad(SDValue Op) {
2547 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2550 static bool MayFoldIntoStore(SDValue Op) {
2551 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2554 static bool isTargetShuffle(unsigned Opcode) {
2556 default: return false;
2557 case X86ISD::PSHUFD:
2558 case X86ISD::PSHUFHW:
2559 case X86ISD::PSHUFLW:
2560 case X86ISD::SHUFPD:
2561 case X86ISD::PALIGN:
2562 case X86ISD::SHUFPS:
2563 case X86ISD::MOVLHPS:
2564 case X86ISD::MOVLHPD:
2565 case X86ISD::MOVHLPS:
2566 case X86ISD::MOVLPS:
2567 case X86ISD::MOVLPD:
2568 case X86ISD::MOVSHDUP:
2569 case X86ISD::MOVSLDUP:
2570 case X86ISD::MOVDDUP:
2573 case X86ISD::UNPCKLPS:
2574 case X86ISD::UNPCKLPD:
2575 case X86ISD::PUNPCKLWD:
2576 case X86ISD::PUNPCKLBW:
2577 case X86ISD::PUNPCKLDQ:
2578 case X86ISD::PUNPCKLQDQ:
2579 case X86ISD::UNPCKHPS:
2580 case X86ISD::UNPCKHPD:
2581 case X86ISD::PUNPCKHWD:
2582 case X86ISD::PUNPCKHBW:
2583 case X86ISD::PUNPCKHDQ:
2584 case X86ISD::PUNPCKHQDQ:
2590 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2591 SDValue V1, SelectionDAG &DAG) {
2593 default: llvm_unreachable("Unknown x86 shuffle node");
2594 case X86ISD::MOVSHDUP:
2595 case X86ISD::MOVSLDUP:
2596 case X86ISD::MOVDDUP:
2597 return DAG.getNode(Opc, dl, VT, V1);
2603 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2604 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2606 default: llvm_unreachable("Unknown x86 shuffle node");
2607 case X86ISD::PSHUFD:
2608 case X86ISD::PSHUFHW:
2609 case X86ISD::PSHUFLW:
2610 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2616 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2617 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2619 default: llvm_unreachable("Unknown x86 shuffle node");
2620 case X86ISD::PALIGN:
2621 case X86ISD::SHUFPD:
2622 case X86ISD::SHUFPS:
2623 return DAG.getNode(Opc, dl, VT, V1, V2,
2624 DAG.getConstant(TargetMask, MVT::i8));
2629 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2630 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2632 default: llvm_unreachable("Unknown x86 shuffle node");
2633 case X86ISD::MOVLHPS:
2634 case X86ISD::MOVLHPD:
2635 case X86ISD::MOVHLPS:
2636 case X86ISD::MOVLPS:
2637 case X86ISD::MOVLPD:
2640 case X86ISD::UNPCKLPS:
2641 case X86ISD::UNPCKLPD:
2642 case X86ISD::PUNPCKLWD:
2643 case X86ISD::PUNPCKLBW:
2644 case X86ISD::PUNPCKLDQ:
2645 case X86ISD::PUNPCKLQDQ:
2646 case X86ISD::UNPCKHPS:
2647 case X86ISD::UNPCKHPD:
2648 case X86ISD::PUNPCKHWD:
2649 case X86ISD::PUNPCKHBW:
2650 case X86ISD::PUNPCKHDQ:
2651 case X86ISD::PUNPCKHQDQ:
2652 return DAG.getNode(Opc, dl, VT, V1, V2);
2657 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2658 MachineFunction &MF = DAG.getMachineFunction();
2659 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2660 int ReturnAddrIndex = FuncInfo->getRAIndex();
2662 if (ReturnAddrIndex == 0) {
2663 // Set up a frame object for the return address.
2664 uint64_t SlotSize = TD->getPointerSize();
2665 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2667 FuncInfo->setRAIndex(ReturnAddrIndex);
2670 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2674 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2675 bool hasSymbolicDisplacement) {
2676 // Offset should fit into 32 bit immediate field.
2677 if (!isInt<32>(Offset))
2680 // If we don't have a symbolic displacement - we don't have any extra
2682 if (!hasSymbolicDisplacement)
2685 // FIXME: Some tweaks might be needed for medium code model.
2686 if (M != CodeModel::Small && M != CodeModel::Kernel)
2689 // For small code model we assume that latest object is 16MB before end of 31
2690 // bits boundary. We may also accept pretty large negative constants knowing
2691 // that all objects are in the positive half of address space.
2692 if (M == CodeModel::Small && Offset < 16*1024*1024)
2695 // For kernel code model we know that all object resist in the negative half
2696 // of 32bits address space. We may not accept negative offsets, since they may
2697 // be just off and we may accept pretty large positive ones.
2698 if (M == CodeModel::Kernel && Offset > 0)
2704 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2705 /// specific condition code, returning the condition code and the LHS/RHS of the
2706 /// comparison to make.
2707 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2708 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2710 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2711 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2712 // X > -1 -> X == 0, jump !sign.
2713 RHS = DAG.getConstant(0, RHS.getValueType());
2714 return X86::COND_NS;
2715 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2716 // X < 0 -> X == 0, jump on sign.
2718 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2720 RHS = DAG.getConstant(0, RHS.getValueType());
2721 return X86::COND_LE;
2725 switch (SetCCOpcode) {
2726 default: llvm_unreachable("Invalid integer condition!");
2727 case ISD::SETEQ: return X86::COND_E;
2728 case ISD::SETGT: return X86::COND_G;
2729 case ISD::SETGE: return X86::COND_GE;
2730 case ISD::SETLT: return X86::COND_L;
2731 case ISD::SETLE: return X86::COND_LE;
2732 case ISD::SETNE: return X86::COND_NE;
2733 case ISD::SETULT: return X86::COND_B;
2734 case ISD::SETUGT: return X86::COND_A;
2735 case ISD::SETULE: return X86::COND_BE;
2736 case ISD::SETUGE: return X86::COND_AE;
2740 // First determine if it is required or is profitable to flip the operands.
2742 // If LHS is a foldable load, but RHS is not, flip the condition.
2743 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2744 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2745 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2746 std::swap(LHS, RHS);
2749 switch (SetCCOpcode) {
2755 std::swap(LHS, RHS);
2759 // On a floating point condition, the flags are set as follows:
2761 // 0 | 0 | 0 | X > Y
2762 // 0 | 0 | 1 | X < Y
2763 // 1 | 0 | 0 | X == Y
2764 // 1 | 1 | 1 | unordered
2765 switch (SetCCOpcode) {
2766 default: llvm_unreachable("Condcode should be pre-legalized away");
2768 case ISD::SETEQ: return X86::COND_E;
2769 case ISD::SETOLT: // flipped
2771 case ISD::SETGT: return X86::COND_A;
2772 case ISD::SETOLE: // flipped
2774 case ISD::SETGE: return X86::COND_AE;
2775 case ISD::SETUGT: // flipped
2777 case ISD::SETLT: return X86::COND_B;
2778 case ISD::SETUGE: // flipped
2780 case ISD::SETLE: return X86::COND_BE;
2782 case ISD::SETNE: return X86::COND_NE;
2783 case ISD::SETUO: return X86::COND_P;
2784 case ISD::SETO: return X86::COND_NP;
2786 case ISD::SETUNE: return X86::COND_INVALID;
2790 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2791 /// code. Current x86 isa includes the following FP cmov instructions:
2792 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2793 static bool hasFPCMov(unsigned X86CC) {
2809 /// isFPImmLegal - Returns true if the target can instruction select the
2810 /// specified FP immediate natively. If false, the legalizer will
2811 /// materialize the FP immediate as a load from a constant pool.
2812 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2813 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2814 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2820 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2821 /// the specified range (L, H].
2822 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2823 return (Val < 0) || (Val >= Low && Val < Hi);
2826 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2827 /// specified value.
2828 static bool isUndefOrEqual(int Val, int CmpVal) {
2829 if (Val < 0 || Val == CmpVal)
2834 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2835 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2836 /// the second operand.
2837 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2838 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
2839 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2840 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2841 return (Mask[0] < 2 && Mask[1] < 2);
2845 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2846 SmallVector<int, 8> M;
2848 return ::isPSHUFDMask(M, N->getValueType(0));
2851 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2852 /// is suitable for input to PSHUFHW.
2853 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2854 if (VT != MVT::v8i16)
2857 // Lower quadword copied in order or undef.
2858 for (int i = 0; i != 4; ++i)
2859 if (Mask[i] >= 0 && Mask[i] != i)
2862 // Upper quadword shuffled.
2863 for (int i = 4; i != 8; ++i)
2864 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2870 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2871 SmallVector<int, 8> M;
2873 return ::isPSHUFHWMask(M, N->getValueType(0));
2876 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2877 /// is suitable for input to PSHUFLW.
2878 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2879 if (VT != MVT::v8i16)
2882 // Upper quadword copied in order.
2883 for (int i = 4; i != 8; ++i)
2884 if (Mask[i] >= 0 && Mask[i] != i)
2887 // Lower quadword shuffled.
2888 for (int i = 0; i != 4; ++i)
2895 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2896 SmallVector<int, 8> M;
2898 return ::isPSHUFLWMask(M, N->getValueType(0));
2901 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2902 /// is suitable for input to PALIGNR.
2903 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2905 int i, e = VT.getVectorNumElements();
2907 // Do not handle v2i64 / v2f64 shuffles with palignr.
2908 if (e < 4 || !hasSSSE3)
2911 for (i = 0; i != e; ++i)
2915 // All undef, not a palignr.
2919 // Determine if it's ok to perform a palignr with only the LHS, since we
2920 // don't have access to the actual shuffle elements to see if RHS is undef.
2921 bool Unary = Mask[i] < (int)e;
2922 bool NeedsUnary = false;
2924 int s = Mask[i] - i;
2926 // Check the rest of the elements to see if they are consecutive.
2927 for (++i; i != e; ++i) {
2932 Unary = Unary && (m < (int)e);
2933 NeedsUnary = NeedsUnary || (m < s);
2935 if (NeedsUnary && !Unary)
2937 if (Unary && m != ((s+i) & (e-1)))
2939 if (!Unary && m != (s+i))
2945 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2946 SmallVector<int, 8> M;
2948 return ::isPALIGNRMask(M, N->getValueType(0), true);
2951 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2952 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2953 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2954 int NumElems = VT.getVectorNumElements();
2955 if (NumElems != 2 && NumElems != 4)
2958 int Half = NumElems / 2;
2959 for (int i = 0; i < Half; ++i)
2960 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2962 for (int i = Half; i < NumElems; ++i)
2963 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2969 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2970 SmallVector<int, 8> M;
2972 return ::isSHUFPMask(M, N->getValueType(0));
2975 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2976 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2977 /// half elements to come from vector 1 (which would equal the dest.) and
2978 /// the upper half to come from vector 2.
2979 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2980 int NumElems = VT.getVectorNumElements();
2982 if (NumElems != 2 && NumElems != 4)
2985 int Half = NumElems / 2;
2986 for (int i = 0; i < Half; ++i)
2987 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2989 for (int i = Half; i < NumElems; ++i)
2990 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2995 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2996 SmallVector<int, 8> M;
2998 return isCommutedSHUFPMask(M, N->getValueType(0));
3001 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3002 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3003 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3004 if (N->getValueType(0).getVectorNumElements() != 4)
3007 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3008 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3009 isUndefOrEqual(N->getMaskElt(1), 7) &&
3010 isUndefOrEqual(N->getMaskElt(2), 2) &&
3011 isUndefOrEqual(N->getMaskElt(3), 3);
3014 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3015 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3017 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3018 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3023 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3024 isUndefOrEqual(N->getMaskElt(1), 3) &&
3025 isUndefOrEqual(N->getMaskElt(2), 2) &&
3026 isUndefOrEqual(N->getMaskElt(3), 3);
3029 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3030 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3031 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3032 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3034 if (NumElems != 2 && NumElems != 4)
3037 for (unsigned i = 0; i < NumElems/2; ++i)
3038 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3041 for (unsigned i = NumElems/2; i < NumElems; ++i)
3042 if (!isUndefOrEqual(N->getMaskElt(i), i))
3048 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3049 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3050 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3051 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3053 if (NumElems != 2 && NumElems != 4)
3056 for (unsigned i = 0; i < NumElems/2; ++i)
3057 if (!isUndefOrEqual(N->getMaskElt(i), i))
3060 for (unsigned i = 0; i < NumElems/2; ++i)
3061 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3067 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3068 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3069 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3070 bool V2IsSplat = false) {
3071 int NumElts = VT.getVectorNumElements();
3072 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3075 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3077 int BitI1 = Mask[i+1];
3078 if (!isUndefOrEqual(BitI, j))
3081 if (!isUndefOrEqual(BitI1, NumElts))
3084 if (!isUndefOrEqual(BitI1, j + NumElts))
3091 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3092 SmallVector<int, 8> M;
3094 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3097 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3098 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3099 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3100 bool V2IsSplat = false) {
3101 int NumElts = VT.getVectorNumElements();
3102 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3105 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3107 int BitI1 = Mask[i+1];
3108 if (!isUndefOrEqual(BitI, j + NumElts/2))
3111 if (isUndefOrEqual(BitI1, NumElts))
3114 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3121 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3122 SmallVector<int, 8> M;
3124 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3127 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3128 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3130 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3131 int NumElems = VT.getVectorNumElements();
3132 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3135 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3137 int BitI1 = Mask[i+1];
3138 if (!isUndefOrEqual(BitI, j))
3140 if (!isUndefOrEqual(BitI1, j))
3146 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3147 SmallVector<int, 8> M;
3149 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3152 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3153 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3155 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3156 int NumElems = VT.getVectorNumElements();
3157 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3160 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3162 int BitI1 = Mask[i+1];
3163 if (!isUndefOrEqual(BitI, j))
3165 if (!isUndefOrEqual(BitI1, j))
3171 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3172 SmallVector<int, 8> M;
3174 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3177 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3178 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3179 /// MOVSD, and MOVD, i.e. setting the lowest element.
3180 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3181 if (VT.getVectorElementType().getSizeInBits() < 32)
3184 int NumElts = VT.getVectorNumElements();
3186 if (!isUndefOrEqual(Mask[0], NumElts))
3189 for (int i = 1; i < NumElts; ++i)
3190 if (!isUndefOrEqual(Mask[i], i))
3196 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3197 SmallVector<int, 8> M;
3199 return ::isMOVLMask(M, N->getValueType(0));
3202 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3203 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3204 /// element of vector 2 and the other elements to come from vector 1 in order.
3205 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3206 bool V2IsSplat = false, bool V2IsUndef = false) {
3207 int NumOps = VT.getVectorNumElements();
3208 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3211 if (!isUndefOrEqual(Mask[0], 0))
3214 for (int i = 1; i < NumOps; ++i)
3215 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3216 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3217 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3223 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3224 bool V2IsUndef = false) {
3225 SmallVector<int, 8> M;
3227 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3230 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3231 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3232 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3233 if (N->getValueType(0).getVectorNumElements() != 4)
3236 // Expect 1, 1, 3, 3
3237 for (unsigned i = 0; i < 2; ++i) {
3238 int Elt = N->getMaskElt(i);
3239 if (Elt >= 0 && Elt != 1)
3244 for (unsigned i = 2; i < 4; ++i) {
3245 int Elt = N->getMaskElt(i);
3246 if (Elt >= 0 && Elt != 3)
3251 // Don't use movshdup if it can be done with a shufps.
3252 // FIXME: verify that matching u, u, 3, 3 is what we want.
3256 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3257 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3258 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3259 if (N->getValueType(0).getVectorNumElements() != 4)
3262 // Expect 0, 0, 2, 2
3263 for (unsigned i = 0; i < 2; ++i)
3264 if (N->getMaskElt(i) > 0)
3268 for (unsigned i = 2; i < 4; ++i) {
3269 int Elt = N->getMaskElt(i);
3270 if (Elt >= 0 && Elt != 2)
3275 // Don't use movsldup if it can be done with a shufps.
3279 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3280 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3281 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3282 int e = N->getValueType(0).getVectorNumElements() / 2;
3284 for (int i = 0; i < e; ++i)
3285 if (!isUndefOrEqual(N->getMaskElt(i), i))
3287 for (int i = 0; i < e; ++i)
3288 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3293 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3294 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3295 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3296 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3297 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3299 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3301 for (int i = 0; i < NumOperands; ++i) {
3302 int Val = SVOp->getMaskElt(NumOperands-i-1);
3303 if (Val < 0) Val = 0;
3304 if (Val >= NumOperands) Val -= NumOperands;
3306 if (i != NumOperands - 1)
3312 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3313 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3314 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3317 // 8 nodes, but we only care about the last 4.
3318 for (unsigned i = 7; i >= 4; --i) {
3319 int Val = SVOp->getMaskElt(i);
3328 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3329 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3330 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3331 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3333 // 8 nodes, but we only care about the first 4.
3334 for (int i = 3; i >= 0; --i) {
3335 int Val = SVOp->getMaskElt(i);
3344 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3345 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3346 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3348 EVT VVT = N->getValueType(0);
3349 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3353 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3354 Val = SVOp->getMaskElt(i);
3358 return (Val - i) * EltSize;
3361 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3363 bool X86::isZeroNode(SDValue Elt) {
3364 return ((isa<ConstantSDNode>(Elt) &&
3365 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3366 (isa<ConstantFPSDNode>(Elt) &&
3367 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3370 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3371 /// their permute mask.
3372 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3373 SelectionDAG &DAG) {
3374 EVT VT = SVOp->getValueType(0);
3375 unsigned NumElems = VT.getVectorNumElements();
3376 SmallVector<int, 8> MaskVec;
3378 for (unsigned i = 0; i != NumElems; ++i) {
3379 int idx = SVOp->getMaskElt(i);
3381 MaskVec.push_back(idx);
3382 else if (idx < (int)NumElems)
3383 MaskVec.push_back(idx + NumElems);
3385 MaskVec.push_back(idx - NumElems);
3387 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3388 SVOp->getOperand(0), &MaskVec[0]);
3391 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3392 /// the two vector operands have swapped position.
3393 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3394 unsigned NumElems = VT.getVectorNumElements();
3395 for (unsigned i = 0; i != NumElems; ++i) {
3399 else if (idx < (int)NumElems)
3400 Mask[i] = idx + NumElems;
3402 Mask[i] = idx - NumElems;
3406 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3407 /// match movhlps. The lower half elements should come from upper half of
3408 /// V1 (and in order), and the upper half elements should come from the upper
3409 /// half of V2 (and in order).
3410 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3411 if (Op->getValueType(0).getVectorNumElements() != 4)
3413 for (unsigned i = 0, e = 2; i != e; ++i)
3414 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3416 for (unsigned i = 2; i != 4; ++i)
3417 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3422 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3423 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3425 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3426 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3428 N = N->getOperand(0).getNode();
3429 if (!ISD::isNON_EXTLoad(N))
3432 *LD = cast<LoadSDNode>(N);
3436 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3437 /// match movlp{s|d}. The lower half elements should come from lower half of
3438 /// V1 (and in order), and the upper half elements should come from the upper
3439 /// half of V2 (and in order). And since V1 will become the source of the
3440 /// MOVLP, it must be either a vector load or a scalar load to vector.
3441 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3442 ShuffleVectorSDNode *Op) {
3443 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3445 // Is V2 is a vector load, don't do this transformation. We will try to use
3446 // load folding shufps op.
3447 if (ISD::isNON_EXTLoad(V2))
3450 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3452 if (NumElems != 2 && NumElems != 4)
3454 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3455 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3457 for (unsigned i = NumElems/2; i != NumElems; ++i)
3458 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3463 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3465 static bool isSplatVector(SDNode *N) {
3466 if (N->getOpcode() != ISD::BUILD_VECTOR)
3469 SDValue SplatValue = N->getOperand(0);
3470 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3471 if (N->getOperand(i) != SplatValue)
3476 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3477 /// to an zero vector.
3478 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3479 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3480 SDValue V1 = N->getOperand(0);
3481 SDValue V2 = N->getOperand(1);
3482 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3483 for (unsigned i = 0; i != NumElems; ++i) {
3484 int Idx = N->getMaskElt(i);
3485 if (Idx >= (int)NumElems) {
3486 unsigned Opc = V2.getOpcode();
3487 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3489 if (Opc != ISD::BUILD_VECTOR ||
3490 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3492 } else if (Idx >= 0) {
3493 unsigned Opc = V1.getOpcode();
3494 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3496 if (Opc != ISD::BUILD_VECTOR ||
3497 !X86::isZeroNode(V1.getOperand(Idx)))
3504 /// getZeroVector - Returns a vector of specified type with all zero elements.
3506 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3508 assert(VT.isVector() && "Expected a vector type");
3510 // Always build SSE zero vectors as <4 x i32> bitcasted
3511 // to their dest type. This ensures they get CSE'd.
3513 if (VT.getSizeInBits() == 128) { // SSE
3514 if (HasSSE2) { // SSE2
3515 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3516 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3518 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3519 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3521 } else if (VT.getSizeInBits() == 256) { // AVX
3522 // 256-bit logic and arithmetic instructions in AVX are
3523 // all floating-point, no support for integer ops. Default
3524 // to emitting fp zeroed vectors then.
3525 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3526 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3527 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3529 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3532 /// getOnesVector - Returns a vector of specified type with all bits set.
3534 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3535 assert(VT.isVector() && "Expected a vector type");
3537 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3538 // type. This ensures they get CSE'd.
3539 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3541 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3542 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3546 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3547 /// that point to V2 points to its first element.
3548 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3549 EVT VT = SVOp->getValueType(0);
3550 unsigned NumElems = VT.getVectorNumElements();
3552 bool Changed = false;
3553 SmallVector<int, 8> MaskVec;
3554 SVOp->getMask(MaskVec);
3556 for (unsigned i = 0; i != NumElems; ++i) {
3557 if (MaskVec[i] > (int)NumElems) {
3558 MaskVec[i] = NumElems;
3563 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3564 SVOp->getOperand(1), &MaskVec[0]);
3565 return SDValue(SVOp, 0);
3568 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3569 /// operation of specified width.
3570 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3572 unsigned NumElems = VT.getVectorNumElements();
3573 SmallVector<int, 8> Mask;
3574 Mask.push_back(NumElems);
3575 for (unsigned i = 1; i != NumElems; ++i)
3577 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3580 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3581 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3583 unsigned NumElems = VT.getVectorNumElements();
3584 SmallVector<int, 8> Mask;
3585 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3587 Mask.push_back(i + NumElems);
3589 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3592 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3593 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3595 unsigned NumElems = VT.getVectorNumElements();
3596 unsigned Half = NumElems/2;
3597 SmallVector<int, 8> Mask;
3598 for (unsigned i = 0; i != Half; ++i) {
3599 Mask.push_back(i + Half);
3600 Mask.push_back(i + NumElems + Half);
3602 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3605 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3606 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3607 EVT PVT = MVT::v4f32;
3608 EVT VT = SV->getValueType(0);
3609 DebugLoc dl = SV->getDebugLoc();
3610 SDValue V1 = SV->getOperand(0);
3611 int NumElems = VT.getVectorNumElements();
3612 int EltNo = SV->getSplatIndex();
3614 // unpack elements to the correct location
3615 while (NumElems > 4) {
3616 if (EltNo < NumElems/2) {
3617 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3619 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3620 EltNo -= NumElems/2;
3625 // Perform the splat.
3626 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3627 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3628 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3629 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3632 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3633 /// vector of zero or undef vector. This produces a shuffle where the low
3634 /// element of V2 is swizzled into the zero/undef vector, landing at element
3635 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3636 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3637 bool isZero, bool HasSSE2,
3638 SelectionDAG &DAG) {
3639 EVT VT = V2.getValueType();
3641 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3642 unsigned NumElems = VT.getVectorNumElements();
3643 SmallVector<int, 16> MaskVec;
3644 for (unsigned i = 0; i != NumElems; ++i)
3645 // If this is the insertion idx, put the low elt of V2 here.
3646 MaskVec.push_back(i == Idx ? NumElems : i);
3647 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3650 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3651 /// element of the result of the vector shuffle.
3652 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3655 return SDValue(); // Limit search depth.
3657 SDValue V = SDValue(N, 0);
3658 EVT VT = V.getValueType();
3659 unsigned Opcode = V.getOpcode();
3661 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3662 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3663 Index = SV->getMaskElt(Index);
3666 return DAG.getUNDEF(VT.getVectorElementType());
3668 int NumElems = VT.getVectorNumElements();
3669 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3670 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3673 // Recurse into target specific vector shuffles to find scalars.
3674 if (isTargetShuffle(Opcode)) {
3675 int NumElems = VT.getVectorNumElements();
3676 SmallVector<unsigned, 16> ShuffleMask;
3680 case X86ISD::SHUFPS:
3681 case X86ISD::SHUFPD:
3682 ImmN = N->getOperand(N->getNumOperands()-1);
3683 DecodeSHUFPSMask(NumElems,
3684 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3687 case X86ISD::PUNPCKHBW:
3688 case X86ISD::PUNPCKHWD:
3689 case X86ISD::PUNPCKHDQ:
3690 case X86ISD::PUNPCKHQDQ:
3691 DecodePUNPCKHMask(NumElems, ShuffleMask);
3693 case X86ISD::UNPCKHPS:
3694 case X86ISD::UNPCKHPD:
3695 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3697 case X86ISD::PUNPCKLBW:
3698 case X86ISD::PUNPCKLWD:
3699 case X86ISD::PUNPCKLDQ:
3700 case X86ISD::PUNPCKLQDQ:
3701 DecodePUNPCKLMask(NumElems, ShuffleMask);
3703 case X86ISD::UNPCKLPS:
3704 case X86ISD::UNPCKLPD:
3705 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3707 case X86ISD::MOVHLPS:
3708 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3710 case X86ISD::MOVLHPS:
3711 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3713 case X86ISD::PSHUFD:
3714 ImmN = N->getOperand(N->getNumOperands()-1);
3715 DecodePSHUFMask(NumElems,
3716 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3719 case X86ISD::PSHUFHW:
3720 ImmN = N->getOperand(N->getNumOperands()-1);
3721 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3724 case X86ISD::PSHUFLW:
3725 ImmN = N->getOperand(N->getNumOperands()-1);
3726 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3730 case X86ISD::MOVSD: {
3731 // The index 0 always comes from the first element of the second source,
3732 // this is why MOVSS and MOVSD are used in the first place. The other
3733 // elements come from the other positions of the first source vector.
3734 unsigned OpNum = (Index == 0) ? 1 : 0;
3735 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3739 assert("not implemented for target shuffle node");
3743 Index = ShuffleMask[Index];
3745 return DAG.getUNDEF(VT.getVectorElementType());
3747 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3748 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3752 // Actual nodes that may contain scalar elements
3753 if (Opcode == ISD::BIT_CONVERT) {
3754 V = V.getOperand(0);
3755 EVT SrcVT = V.getValueType();
3756 unsigned NumElems = VT.getVectorNumElements();
3758 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3762 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3763 return (Index == 0) ? V.getOperand(0)
3764 : DAG.getUNDEF(VT.getVectorElementType());
3766 if (V.getOpcode() == ISD::BUILD_VECTOR)
3767 return V.getOperand(Index);
3772 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3773 /// shuffle operation which come from a consecutively from a zero. The
3774 /// search can start in two diferent directions, from left or right.
3776 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3777 bool ZerosFromLeft, SelectionDAG &DAG) {
3780 while (i < NumElems) {
3781 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3782 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3783 if (!(Elt.getNode() &&
3784 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3792 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3793 /// MaskE correspond consecutively to elements from one of the vector operands,
3794 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3796 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3797 int OpIdx, int NumElems, unsigned &OpNum) {
3798 bool SeenV1 = false;
3799 bool SeenV2 = false;
3801 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3802 int Idx = SVOp->getMaskElt(i);
3803 // Ignore undef indicies
3812 // Only accept consecutive elements from the same vector
3813 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3817 OpNum = SeenV1 ? 0 : 1;
3821 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3822 /// logical left shift of a vector.
3823 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3824 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3825 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3826 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3827 false /* check zeros from right */, DAG);
3833 // Considering the elements in the mask that are not consecutive zeros,
3834 // check if they consecutively come from only one of the source vectors.
3836 // V1 = {X, A, B, C} 0
3838 // vector_shuffle V1, V2 <1, 2, 3, X>
3840 if (!isShuffleMaskConsecutive(SVOp,
3841 0, // Mask Start Index
3842 NumElems-NumZeros-1, // Mask End Index
3843 NumZeros, // Where to start looking in the src vector
3844 NumElems, // Number of elements in vector
3845 OpSrc)) // Which source operand ?
3850 ShVal = SVOp->getOperand(OpSrc);
3854 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3855 /// logical left shift of a vector.
3856 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3857 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3858 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3859 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3860 true /* check zeros from left */, DAG);
3866 // Considering the elements in the mask that are not consecutive zeros,
3867 // check if they consecutively come from only one of the source vectors.
3869 // 0 { A, B, X, X } = V2
3871 // vector_shuffle V1, V2 <X, X, 4, 5>
3873 if (!isShuffleMaskConsecutive(SVOp,
3874 NumZeros, // Mask Start Index
3875 NumElems-1, // Mask End Index
3876 0, // Where to start looking in the src vector
3877 NumElems, // Number of elements in vector
3878 OpSrc)) // Which source operand ?
3883 ShVal = SVOp->getOperand(OpSrc);
3887 /// isVectorShift - Returns true if the shuffle can be implemented as a
3888 /// logical left or right shift of a vector.
3889 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3890 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3891 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3892 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3898 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3900 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3901 unsigned NumNonZero, unsigned NumZero,
3903 const TargetLowering &TLI) {
3907 DebugLoc dl = Op.getDebugLoc();
3910 for (unsigned i = 0; i < 16; ++i) {
3911 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3912 if (ThisIsNonZero && First) {
3914 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3916 V = DAG.getUNDEF(MVT::v8i16);
3921 SDValue ThisElt(0, 0), LastElt(0, 0);
3922 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3923 if (LastIsNonZero) {
3924 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3925 MVT::i16, Op.getOperand(i-1));
3927 if (ThisIsNonZero) {
3928 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3929 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3930 ThisElt, DAG.getConstant(8, MVT::i8));
3932 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3936 if (ThisElt.getNode())
3937 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3938 DAG.getIntPtrConstant(i/2));
3942 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3945 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3947 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3948 unsigned NumNonZero, unsigned NumZero,
3950 const TargetLowering &TLI) {
3954 DebugLoc dl = Op.getDebugLoc();
3957 for (unsigned i = 0; i < 8; ++i) {
3958 bool isNonZero = (NonZeros & (1 << i)) != 0;
3962 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3964 V = DAG.getUNDEF(MVT::v8i16);
3967 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3968 MVT::v8i16, V, Op.getOperand(i),
3969 DAG.getIntPtrConstant(i));
3976 /// getVShift - Return a vector logical shift node.
3978 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3979 unsigned NumBits, SelectionDAG &DAG,
3980 const TargetLowering &TLI, DebugLoc dl) {
3981 EVT ShVT = MVT::v2i64;
3982 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3983 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3984 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3985 DAG.getNode(Opc, dl, ShVT, SrcOp,
3986 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3990 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3991 SelectionDAG &DAG) const {
3993 // Check if the scalar load can be widened into a vector load. And if
3994 // the address is "base + cst" see if the cst can be "absorbed" into
3995 // the shuffle mask.
3996 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3997 SDValue Ptr = LD->getBasePtr();
3998 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4000 EVT PVT = LD->getValueType(0);
4001 if (PVT != MVT::i32 && PVT != MVT::f32)
4006 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4007 FI = FINode->getIndex();
4009 } else if (Ptr.getOpcode() == ISD::ADD &&
4010 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4011 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4012 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4013 Offset = Ptr.getConstantOperandVal(1);
4014 Ptr = Ptr.getOperand(0);
4019 SDValue Chain = LD->getChain();
4020 // Make sure the stack object alignment is at least 16.
4021 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4022 if (DAG.InferPtrAlignment(Ptr) < 16) {
4023 if (MFI->isFixedObjectIndex(FI)) {
4024 // Can't change the alignment. FIXME: It's possible to compute
4025 // the exact stack offset and reference FI + adjust offset instead.
4026 // If someone *really* cares about this. That's the way to implement it.
4029 MFI->setObjectAlignment(FI, 16);
4033 // (Offset % 16) must be multiple of 4. Then address is then
4034 // Ptr + (Offset & ~15).
4037 if ((Offset % 16) & 3)
4039 int64_t StartOffset = Offset & ~15;
4041 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4042 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4044 int EltNo = (Offset - StartOffset) >> 2;
4045 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4046 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4047 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4048 LD->getPointerInfo().getWithOffset(StartOffset),
4050 // Canonicalize it to a v4i32 shuffle.
4051 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
4052 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4053 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4054 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4060 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4061 /// vector of type 'VT', see if the elements can be replaced by a single large
4062 /// load which has the same value as a build_vector whose operands are 'elts'.
4064 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4066 /// FIXME: we'd also like to handle the case where the last elements are zero
4067 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4068 /// There's even a handy isZeroNode for that purpose.
4069 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4070 DebugLoc &DL, SelectionDAG &DAG) {
4071 EVT EltVT = VT.getVectorElementType();
4072 unsigned NumElems = Elts.size();
4074 LoadSDNode *LDBase = NULL;
4075 unsigned LastLoadedElt = -1U;
4077 // For each element in the initializer, see if we've found a load or an undef.
4078 // If we don't find an initial load element, or later load elements are
4079 // non-consecutive, bail out.
4080 for (unsigned i = 0; i < NumElems; ++i) {
4081 SDValue Elt = Elts[i];
4083 if (!Elt.getNode() ||
4084 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4087 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4089 LDBase = cast<LoadSDNode>(Elt.getNode());
4093 if (Elt.getOpcode() == ISD::UNDEF)
4096 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4097 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4102 // If we have found an entire vector of loads and undefs, then return a large
4103 // load of the entire vector width starting at the base pointer. If we found
4104 // consecutive loads for the low half, generate a vzext_load node.
4105 if (LastLoadedElt == NumElems - 1) {
4106 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4107 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4108 LDBase->getPointerInfo(),
4109 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4110 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4111 LDBase->getPointerInfo(),
4112 LDBase->isVolatile(), LDBase->isNonTemporal(),
4113 LDBase->getAlignment());
4114 } else if (NumElems == 4 && LastLoadedElt == 1) {
4115 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4116 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4117 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4119 LDBase->getMemOperand());
4120 return DAG.getNode(ISD::BIT_CONVERT, DL, VT, ResNode);
4126 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4127 DebugLoc dl = Op.getDebugLoc();
4128 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4129 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4130 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4131 // is present, so AllOnes is ignored.
4132 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4133 (Op.getValueType().getSizeInBits() != 256 &&
4134 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4135 // Canonicalize this to <4 x i32> (SSE) to
4136 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4137 // eliminated on x86-32 hosts.
4138 if (Op.getValueType() == MVT::v4i32)
4141 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4142 return getOnesVector(Op.getValueType(), DAG, dl);
4143 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4146 EVT VT = Op.getValueType();
4147 EVT ExtVT = VT.getVectorElementType();
4148 unsigned EVTBits = ExtVT.getSizeInBits();
4150 unsigned NumElems = Op.getNumOperands();
4151 unsigned NumZero = 0;
4152 unsigned NumNonZero = 0;
4153 unsigned NonZeros = 0;
4154 bool IsAllConstants = true;
4155 SmallSet<SDValue, 8> Values;
4156 for (unsigned i = 0; i < NumElems; ++i) {
4157 SDValue Elt = Op.getOperand(i);
4158 if (Elt.getOpcode() == ISD::UNDEF)
4161 if (Elt.getOpcode() != ISD::Constant &&
4162 Elt.getOpcode() != ISD::ConstantFP)
4163 IsAllConstants = false;
4164 if (X86::isZeroNode(Elt))
4167 NonZeros |= (1 << i);
4172 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4173 if (NumNonZero == 0)
4174 return DAG.getUNDEF(VT);
4176 // Special case for single non-zero, non-undef, element.
4177 if (NumNonZero == 1) {
4178 unsigned Idx = CountTrailingZeros_32(NonZeros);
4179 SDValue Item = Op.getOperand(Idx);
4181 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4182 // the value are obviously zero, truncate the value to i32 and do the
4183 // insertion that way. Only do this if the value is non-constant or if the
4184 // value is a constant being inserted into element 0. It is cheaper to do
4185 // a constant pool load than it is to do a movd + shuffle.
4186 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4187 (!IsAllConstants || Idx == 0)) {
4188 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4190 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4191 EVT VecVT = MVT::v4i32;
4192 unsigned VecElts = 4;
4194 // Truncate the value (which may itself be a constant) to i32, and
4195 // convert it to a vector with movd (S2V+shuffle to zero extend).
4196 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4197 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4198 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4199 Subtarget->hasSSE2(), DAG);
4201 // Now we have our 32-bit value zero extended in the low element of
4202 // a vector. If Idx != 0, swizzle it into place.
4204 SmallVector<int, 4> Mask;
4205 Mask.push_back(Idx);
4206 for (unsigned i = 1; i != VecElts; ++i)
4208 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4209 DAG.getUNDEF(Item.getValueType()),
4212 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
4216 // If we have a constant or non-constant insertion into the low element of
4217 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4218 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4219 // depending on what the source datatype is.
4222 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4223 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4224 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4225 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4226 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4227 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4229 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4230 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4231 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4232 EVT MiddleVT = MVT::v4i32;
4233 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4234 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4235 Subtarget->hasSSE2(), DAG);
4236 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
4240 // Is it a vector logical left shift?
4241 if (NumElems == 2 && Idx == 1 &&
4242 X86::isZeroNode(Op.getOperand(0)) &&
4243 !X86::isZeroNode(Op.getOperand(1))) {
4244 unsigned NumBits = VT.getSizeInBits();
4245 return getVShift(true, VT,
4246 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4247 VT, Op.getOperand(1)),
4248 NumBits/2, DAG, *this, dl);
4251 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4254 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4255 // is a non-constant being inserted into an element other than the low one,
4256 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4257 // movd/movss) to move this into the low element, then shuffle it into
4259 if (EVTBits == 32) {
4260 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4262 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4263 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4264 Subtarget->hasSSE2(), DAG);
4265 SmallVector<int, 8> MaskVec;
4266 for (unsigned i = 0; i < NumElems; i++)
4267 MaskVec.push_back(i == Idx ? 0 : 1);
4268 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4272 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4273 if (Values.size() == 1) {
4274 if (EVTBits == 32) {
4275 // Instead of a shuffle like this:
4276 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4277 // Check if it's possible to issue this instead.
4278 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4279 unsigned Idx = CountTrailingZeros_32(NonZeros);
4280 SDValue Item = Op.getOperand(Idx);
4281 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4282 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4287 // A vector full of immediates; various special cases are already
4288 // handled, so this is best done with a single constant-pool load.
4292 // Let legalizer expand 2-wide build_vectors.
4293 if (EVTBits == 64) {
4294 if (NumNonZero == 1) {
4295 // One half is zero or undef.
4296 unsigned Idx = CountTrailingZeros_32(NonZeros);
4297 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4298 Op.getOperand(Idx));
4299 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4300 Subtarget->hasSSE2(), DAG);
4305 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4306 if (EVTBits == 8 && NumElems == 16) {
4307 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4309 if (V.getNode()) return V;
4312 if (EVTBits == 16 && NumElems == 8) {
4313 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4315 if (V.getNode()) return V;
4318 // If element VT is == 32 bits, turn it into a number of shuffles.
4319 SmallVector<SDValue, 8> V;
4321 if (NumElems == 4 && NumZero > 0) {
4322 for (unsigned i = 0; i < 4; ++i) {
4323 bool isZero = !(NonZeros & (1 << i));
4325 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4327 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4330 for (unsigned i = 0; i < 2; ++i) {
4331 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4334 V[i] = V[i*2]; // Must be a zero vector.
4337 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4340 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4343 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4348 SmallVector<int, 8> MaskVec;
4349 bool Reverse = (NonZeros & 0x3) == 2;
4350 for (unsigned i = 0; i < 2; ++i)
4351 MaskVec.push_back(Reverse ? 1-i : i);
4352 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4353 for (unsigned i = 0; i < 2; ++i)
4354 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4355 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4358 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4359 // Check for a build vector of consecutive loads.
4360 for (unsigned i = 0; i < NumElems; ++i)
4361 V[i] = Op.getOperand(i);
4363 // Check for elements which are consecutive loads.
4364 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4368 // For SSE 4.1, use insertps to put the high elements into the low element.
4369 if (getSubtarget()->hasSSE41()) {
4371 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4372 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4374 Result = DAG.getUNDEF(VT);
4376 for (unsigned i = 1; i < NumElems; ++i) {
4377 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4378 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4379 Op.getOperand(i), DAG.getIntPtrConstant(i));
4384 // Otherwise, expand into a number of unpckl*, start by extending each of
4385 // our (non-undef) elements to the full vector width with the element in the
4386 // bottom slot of the vector (which generates no code for SSE).
4387 for (unsigned i = 0; i < NumElems; ++i) {
4388 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4389 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4391 V[i] = DAG.getUNDEF(VT);
4394 // Next, we iteratively mix elements, e.g. for v4f32:
4395 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4396 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4397 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4398 unsigned EltStride = NumElems >> 1;
4399 while (EltStride != 0) {
4400 for (unsigned i = 0; i < EltStride; ++i) {
4401 // If V[i+EltStride] is undef and this is the first round of mixing,
4402 // then it is safe to just drop this shuffle: V[i] is already in the
4403 // right place, the one element (since it's the first round) being
4404 // inserted as undef can be dropped. This isn't safe for successive
4405 // rounds because they will permute elements within both vectors.
4406 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4407 EltStride == NumElems/2)
4410 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4420 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4421 // We support concatenate two MMX registers and place them in a MMX
4422 // register. This is better than doing a stack convert.
4423 DebugLoc dl = Op.getDebugLoc();
4424 EVT ResVT = Op.getValueType();
4425 assert(Op.getNumOperands() == 2);
4426 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4427 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4429 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4430 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4431 InVec = Op.getOperand(1);
4432 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4433 unsigned NumElts = ResVT.getVectorNumElements();
4434 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4435 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4436 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4438 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4439 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4440 Mask[0] = 0; Mask[1] = 2;
4441 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4443 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4446 // v8i16 shuffles - Prefer shuffles in the following order:
4447 // 1. [all] pshuflw, pshufhw, optional move
4448 // 2. [ssse3] 1 x pshufb
4449 // 3. [ssse3] 2 x pshufb + 1 x por
4450 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4452 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4453 SelectionDAG &DAG) const {
4454 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4455 SDValue V1 = SVOp->getOperand(0);
4456 SDValue V2 = SVOp->getOperand(1);
4457 DebugLoc dl = SVOp->getDebugLoc();
4458 SmallVector<int, 8> MaskVals;
4460 // Determine if more than 1 of the words in each of the low and high quadwords
4461 // of the result come from the same quadword of one of the two inputs. Undef
4462 // mask values count as coming from any quadword, for better codegen.
4463 SmallVector<unsigned, 4> LoQuad(4);
4464 SmallVector<unsigned, 4> HiQuad(4);
4465 BitVector InputQuads(4);
4466 for (unsigned i = 0; i < 8; ++i) {
4467 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4468 int EltIdx = SVOp->getMaskElt(i);
4469 MaskVals.push_back(EltIdx);
4478 InputQuads.set(EltIdx / 4);
4481 int BestLoQuad = -1;
4482 unsigned MaxQuad = 1;
4483 for (unsigned i = 0; i < 4; ++i) {
4484 if (LoQuad[i] > MaxQuad) {
4486 MaxQuad = LoQuad[i];
4490 int BestHiQuad = -1;
4492 for (unsigned i = 0; i < 4; ++i) {
4493 if (HiQuad[i] > MaxQuad) {
4495 MaxQuad = HiQuad[i];
4499 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4500 // of the two input vectors, shuffle them into one input vector so only a
4501 // single pshufb instruction is necessary. If There are more than 2 input
4502 // quads, disable the next transformation since it does not help SSSE3.
4503 bool V1Used = InputQuads[0] || InputQuads[1];
4504 bool V2Used = InputQuads[2] || InputQuads[3];
4505 if (Subtarget->hasSSSE3()) {
4506 if (InputQuads.count() == 2 && V1Used && V2Used) {
4507 BestLoQuad = InputQuads.find_first();
4508 BestHiQuad = InputQuads.find_next(BestLoQuad);
4510 if (InputQuads.count() > 2) {
4516 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4517 // the shuffle mask. If a quad is scored as -1, that means that it contains
4518 // words from all 4 input quadwords.
4520 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4521 SmallVector<int, 8> MaskV;
4522 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4523 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4524 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4525 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4526 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4527 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4529 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4530 // source words for the shuffle, to aid later transformations.
4531 bool AllWordsInNewV = true;
4532 bool InOrder[2] = { true, true };
4533 for (unsigned i = 0; i != 8; ++i) {
4534 int idx = MaskVals[i];
4536 InOrder[i/4] = false;
4537 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4539 AllWordsInNewV = false;
4543 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4544 if (AllWordsInNewV) {
4545 for (int i = 0; i != 8; ++i) {
4546 int idx = MaskVals[i];
4549 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4550 if ((idx != i) && idx < 4)
4552 if ((idx != i) && idx > 3)
4561 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4562 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4563 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4564 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4565 unsigned TargetMask = 0;
4566 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4567 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4568 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4569 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4570 V1 = NewV.getOperand(0);
4571 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4575 // If we have SSSE3, and all words of the result are from 1 input vector,
4576 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4577 // is present, fall back to case 4.
4578 if (Subtarget->hasSSSE3()) {
4579 SmallVector<SDValue,16> pshufbMask;
4581 // If we have elements from both input vectors, set the high bit of the
4582 // shuffle mask element to zero out elements that come from V2 in the V1
4583 // mask, and elements that come from V1 in the V2 mask, so that the two
4584 // results can be OR'd together.
4585 bool TwoInputs = V1Used && V2Used;
4586 for (unsigned i = 0; i != 8; ++i) {
4587 int EltIdx = MaskVals[i] * 2;
4588 if (TwoInputs && (EltIdx >= 16)) {
4589 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4590 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4593 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4594 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4596 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4597 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4598 DAG.getNode(ISD::BUILD_VECTOR, dl,
4599 MVT::v16i8, &pshufbMask[0], 16));
4601 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4603 // Calculate the shuffle mask for the second input, shuffle it, and
4604 // OR it with the first shuffled input.
4606 for (unsigned i = 0; i != 8; ++i) {
4607 int EltIdx = MaskVals[i] * 2;
4609 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4610 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4613 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4614 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4616 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4617 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4618 DAG.getNode(ISD::BUILD_VECTOR, dl,
4619 MVT::v16i8, &pshufbMask[0], 16));
4620 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4621 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4624 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4625 // and update MaskVals with new element order.
4626 BitVector InOrder(8);
4627 if (BestLoQuad >= 0) {
4628 SmallVector<int, 8> MaskV;
4629 for (int i = 0; i != 4; ++i) {
4630 int idx = MaskVals[i];
4632 MaskV.push_back(-1);
4634 } else if ((idx / 4) == BestLoQuad) {
4635 MaskV.push_back(idx & 3);
4638 MaskV.push_back(-1);
4641 for (unsigned i = 4; i != 8; ++i)
4643 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4646 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4647 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4649 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4653 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4654 // and update MaskVals with the new element order.
4655 if (BestHiQuad >= 0) {
4656 SmallVector<int, 8> MaskV;
4657 for (unsigned i = 0; i != 4; ++i)
4659 for (unsigned i = 4; i != 8; ++i) {
4660 int idx = MaskVals[i];
4662 MaskV.push_back(-1);
4664 } else if ((idx / 4) == BestHiQuad) {
4665 MaskV.push_back((idx & 3) + 4);
4668 MaskV.push_back(-1);
4671 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4674 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4675 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4677 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4681 // In case BestHi & BestLo were both -1, which means each quadword has a word
4682 // from each of the four input quadwords, calculate the InOrder bitvector now
4683 // before falling through to the insert/extract cleanup.
4684 if (BestLoQuad == -1 && BestHiQuad == -1) {
4686 for (int i = 0; i != 8; ++i)
4687 if (MaskVals[i] < 0 || MaskVals[i] == i)
4691 // The other elements are put in the right place using pextrw and pinsrw.
4692 for (unsigned i = 0; i != 8; ++i) {
4695 int EltIdx = MaskVals[i];
4698 SDValue ExtOp = (EltIdx < 8)
4699 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4700 DAG.getIntPtrConstant(EltIdx))
4701 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4702 DAG.getIntPtrConstant(EltIdx - 8));
4703 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4704 DAG.getIntPtrConstant(i));
4709 // v16i8 shuffles - Prefer shuffles in the following order:
4710 // 1. [ssse3] 1 x pshufb
4711 // 2. [ssse3] 2 x pshufb + 1 x por
4712 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4714 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4716 const X86TargetLowering &TLI) {
4717 SDValue V1 = SVOp->getOperand(0);
4718 SDValue V2 = SVOp->getOperand(1);
4719 DebugLoc dl = SVOp->getDebugLoc();
4720 SmallVector<int, 16> MaskVals;
4721 SVOp->getMask(MaskVals);
4723 // If we have SSSE3, case 1 is generated when all result bytes come from
4724 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4725 // present, fall back to case 3.
4726 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4729 for (unsigned i = 0; i < 16; ++i) {
4730 int EltIdx = MaskVals[i];
4739 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4740 if (TLI.getSubtarget()->hasSSSE3()) {
4741 SmallVector<SDValue,16> pshufbMask;
4743 // If all result elements are from one input vector, then only translate
4744 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4746 // Otherwise, we have elements from both input vectors, and must zero out
4747 // elements that come from V2 in the first mask, and V1 in the second mask
4748 // so that we can OR them together.
4749 bool TwoInputs = !(V1Only || V2Only);
4750 for (unsigned i = 0; i != 16; ++i) {
4751 int EltIdx = MaskVals[i];
4752 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4753 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4756 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4758 // If all the elements are from V2, assign it to V1 and return after
4759 // building the first pshufb.
4762 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4763 DAG.getNode(ISD::BUILD_VECTOR, dl,
4764 MVT::v16i8, &pshufbMask[0], 16));
4768 // Calculate the shuffle mask for the second input, shuffle it, and
4769 // OR it with the first shuffled input.
4771 for (unsigned i = 0; i != 16; ++i) {
4772 int EltIdx = MaskVals[i];
4774 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4777 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4779 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4780 DAG.getNode(ISD::BUILD_VECTOR, dl,
4781 MVT::v16i8, &pshufbMask[0], 16));
4782 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4785 // No SSSE3 - Calculate in place words and then fix all out of place words
4786 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4787 // the 16 different words that comprise the two doublequadword input vectors.
4788 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4789 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4790 SDValue NewV = V2Only ? V2 : V1;
4791 for (int i = 0; i != 8; ++i) {
4792 int Elt0 = MaskVals[i*2];
4793 int Elt1 = MaskVals[i*2+1];
4795 // This word of the result is all undef, skip it.
4796 if (Elt0 < 0 && Elt1 < 0)
4799 // This word of the result is already in the correct place, skip it.
4800 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4802 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4805 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4806 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4809 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4810 // using a single extract together, load it and store it.
4811 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4812 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4813 DAG.getIntPtrConstant(Elt1 / 2));
4814 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4815 DAG.getIntPtrConstant(i));
4819 // If Elt1 is defined, extract it from the appropriate source. If the
4820 // source byte is not also odd, shift the extracted word left 8 bits
4821 // otherwise clear the bottom 8 bits if we need to do an or.
4823 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4824 DAG.getIntPtrConstant(Elt1 / 2));
4825 if ((Elt1 & 1) == 0)
4826 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4827 DAG.getConstant(8, TLI.getShiftAmountTy()));
4829 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4830 DAG.getConstant(0xFF00, MVT::i16));
4832 // If Elt0 is defined, extract it from the appropriate source. If the
4833 // source byte is not also even, shift the extracted word right 8 bits. If
4834 // Elt1 was also defined, OR the extracted values together before
4835 // inserting them in the result.
4837 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4838 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4839 if ((Elt0 & 1) != 0)
4840 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4841 DAG.getConstant(8, TLI.getShiftAmountTy()));
4843 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4844 DAG.getConstant(0x00FF, MVT::i16));
4845 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4848 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4849 DAG.getIntPtrConstant(i));
4851 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4854 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4855 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
4856 /// done when every pair / quad of shuffle mask elements point to elements in
4857 /// the right sequence. e.g.
4858 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
4860 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4861 SelectionDAG &DAG, DebugLoc dl) {
4862 EVT VT = SVOp->getValueType(0);
4863 SDValue V1 = SVOp->getOperand(0);
4864 SDValue V2 = SVOp->getOperand(1);
4865 unsigned NumElems = VT.getVectorNumElements();
4866 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4868 switch (VT.getSimpleVT().SimpleTy) {
4869 default: assert(false && "Unexpected!");
4870 case MVT::v4f32: NewVT = MVT::v2f64; break;
4871 case MVT::v4i32: NewVT = MVT::v2i64; break;
4872 case MVT::v8i16: NewVT = MVT::v4i32; break;
4873 case MVT::v16i8: NewVT = MVT::v4i32; break;
4876 int Scale = NumElems / NewWidth;
4877 SmallVector<int, 8> MaskVec;
4878 for (unsigned i = 0; i < NumElems; i += Scale) {
4880 for (int j = 0; j < Scale; ++j) {
4881 int EltIdx = SVOp->getMaskElt(i+j);
4885 StartIdx = EltIdx - (EltIdx % Scale);
4886 if (EltIdx != StartIdx + j)
4890 MaskVec.push_back(-1);
4892 MaskVec.push_back(StartIdx / Scale);
4895 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4896 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4897 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4900 /// getVZextMovL - Return a zero-extending vector move low node.
4902 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4903 SDValue SrcOp, SelectionDAG &DAG,
4904 const X86Subtarget *Subtarget, DebugLoc dl) {
4905 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4906 LoadSDNode *LD = NULL;
4907 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4908 LD = dyn_cast<LoadSDNode>(SrcOp);
4910 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4912 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4913 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4914 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4915 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4916 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4918 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4919 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4920 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4921 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4929 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4930 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4931 DAG.getNode(ISD::BIT_CONVERT, dl,
4935 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4938 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4939 SDValue V1 = SVOp->getOperand(0);
4940 SDValue V2 = SVOp->getOperand(1);
4941 DebugLoc dl = SVOp->getDebugLoc();
4942 EVT VT = SVOp->getValueType(0);
4944 SmallVector<std::pair<int, int>, 8> Locs;
4946 SmallVector<int, 8> Mask1(4U, -1);
4947 SmallVector<int, 8> PermMask;
4948 SVOp->getMask(PermMask);
4952 for (unsigned i = 0; i != 4; ++i) {
4953 int Idx = PermMask[i];
4955 Locs[i] = std::make_pair(-1, -1);
4957 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4959 Locs[i] = std::make_pair(0, NumLo);
4963 Locs[i] = std::make_pair(1, NumHi);
4965 Mask1[2+NumHi] = Idx;
4971 if (NumLo <= 2 && NumHi <= 2) {
4972 // If no more than two elements come from either vector. This can be
4973 // implemented with two shuffles. First shuffle gather the elements.
4974 // The second shuffle, which takes the first shuffle as both of its
4975 // vector operands, put the elements into the right order.
4976 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4978 SmallVector<int, 8> Mask2(4U, -1);
4980 for (unsigned i = 0; i != 4; ++i) {
4981 if (Locs[i].first == -1)
4984 unsigned Idx = (i < 2) ? 0 : 4;
4985 Idx += Locs[i].first * 2 + Locs[i].second;
4990 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4991 } else if (NumLo == 3 || NumHi == 3) {
4992 // Otherwise, we must have three elements from one vector, call it X, and
4993 // one element from the other, call it Y. First, use a shufps to build an
4994 // intermediate vector with the one element from Y and the element from X
4995 // that will be in the same half in the final destination (the indexes don't
4996 // matter). Then, use a shufps to build the final vector, taking the half
4997 // containing the element from Y from the intermediate, and the other half
5000 // Normalize it so the 3 elements come from V1.
5001 CommuteVectorShuffleMask(PermMask, VT);
5005 // Find the element from V2.
5007 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5008 int Val = PermMask[HiIndex];
5015 Mask1[0] = PermMask[HiIndex];
5017 Mask1[2] = PermMask[HiIndex^1];
5019 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5022 Mask1[0] = PermMask[0];
5023 Mask1[1] = PermMask[1];
5024 Mask1[2] = HiIndex & 1 ? 6 : 4;
5025 Mask1[3] = HiIndex & 1 ? 4 : 6;
5026 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5028 Mask1[0] = HiIndex & 1 ? 2 : 0;
5029 Mask1[1] = HiIndex & 1 ? 0 : 2;
5030 Mask1[2] = PermMask[2];
5031 Mask1[3] = PermMask[3];
5036 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5040 // Break it into (shuffle shuffle_hi, shuffle_lo).
5042 SmallVector<int,8> LoMask(4U, -1);
5043 SmallVector<int,8> HiMask(4U, -1);
5045 SmallVector<int,8> *MaskPtr = &LoMask;
5046 unsigned MaskIdx = 0;
5049 for (unsigned i = 0; i != 4; ++i) {
5056 int Idx = PermMask[i];
5058 Locs[i] = std::make_pair(-1, -1);
5059 } else if (Idx < 4) {
5060 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5061 (*MaskPtr)[LoIdx] = Idx;
5064 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5065 (*MaskPtr)[HiIdx] = Idx;
5070 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5071 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5072 SmallVector<int, 8> MaskOps;
5073 for (unsigned i = 0; i != 4; ++i) {
5074 if (Locs[i].first == -1) {
5075 MaskOps.push_back(-1);
5077 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5078 MaskOps.push_back(Idx);
5081 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5084 static bool MayFoldVectorLoad(SDValue V) {
5085 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5086 V = V.getOperand(0);
5087 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5088 V = V.getOperand(0);
5094 // FIXME: the version above should always be used. Since there's
5095 // a bug where several vector shuffles can't be folded because the
5096 // DAG is not updated during lowering and a node claims to have two
5097 // uses while it only has one, use this version, and let isel match
5098 // another instruction if the load really happens to have more than
5099 // one use. Remove this version after this bug get fixed.
5100 // rdar://8434668, PR8156
5101 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5102 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5103 V = V.getOperand(0);
5104 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5105 V = V.getOperand(0);
5106 if (ISD::isNormalLoad(V.getNode()))
5111 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5112 /// a vector extract, and if both can be later optimized into a single load.
5113 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5114 /// here because otherwise a target specific shuffle node is going to be
5115 /// emitted for this shuffle, and the optimization not done.
5116 /// FIXME: This is probably not the best approach, but fix the problem
5117 /// until the right path is decided.
5119 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5120 const TargetLowering &TLI) {
5121 EVT VT = V.getValueType();
5122 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5124 // Be sure that the vector shuffle is present in a pattern like this:
5125 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5129 SDNode *N = *V.getNode()->use_begin();
5130 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5133 SDValue EltNo = N->getOperand(1);
5134 if (!isa<ConstantSDNode>(EltNo))
5137 // If the bit convert changed the number of elements, it is unsafe
5138 // to examine the mask.
5139 bool HasShuffleIntoBitcast = false;
5140 if (V.getOpcode() == ISD::BIT_CONVERT) {
5141 EVT SrcVT = V.getOperand(0).getValueType();
5142 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5144 V = V.getOperand(0);
5145 HasShuffleIntoBitcast = true;
5148 // Select the input vector, guarding against out of range extract vector.
5149 unsigned NumElems = VT.getVectorNumElements();
5150 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5151 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5152 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5154 // Skip one more bit_convert if necessary
5155 if (V.getOpcode() == ISD::BIT_CONVERT)
5156 V = V.getOperand(0);
5158 if (ISD::isNormalLoad(V.getNode())) {
5159 // Is the original load suitable?
5160 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5162 // FIXME: avoid the multi-use bug that is preventing lots of
5163 // of foldings to be detected, this is still wrong of course, but
5164 // give the temporary desired behavior, and if it happens that
5165 // the load has real more uses, during isel it will not fold, and
5166 // will generate poor code.
5167 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5170 if (!HasShuffleIntoBitcast)
5173 // If there's a bitcast before the shuffle, check if the load type and
5174 // alignment is valid.
5175 unsigned Align = LN0->getAlignment();
5177 TLI.getTargetData()->getABITypeAlignment(
5178 VT.getTypeForEVT(*DAG.getContext()));
5180 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5188 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5189 EVT VT = Op.getValueType();
5191 // Canonizalize to v2f64.
5192 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, V1);
5193 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5194 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5199 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5201 SDValue V1 = Op.getOperand(0);
5202 SDValue V2 = Op.getOperand(1);
5203 EVT VT = Op.getValueType();
5205 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5207 if (HasSSE2 && VT == MVT::v2f64)
5208 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5211 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5215 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5216 SDValue V1 = Op.getOperand(0);
5217 SDValue V2 = Op.getOperand(1);
5218 EVT VT = Op.getValueType();
5220 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5221 "unsupported shuffle type");
5223 if (V2.getOpcode() == ISD::UNDEF)
5227 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5231 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5232 SDValue V1 = Op.getOperand(0);
5233 SDValue V2 = Op.getOperand(1);
5234 EVT VT = Op.getValueType();
5235 unsigned NumElems = VT.getVectorNumElements();
5237 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5238 // operand of these instructions is only memory, so check if there's a
5239 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5241 bool CanFoldLoad = false;
5243 // Trivial case, when V2 comes from a load.
5244 if (MayFoldVectorLoad(V2))
5247 // When V1 is a load, it can be folded later into a store in isel, example:
5248 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5250 // (MOVLPSmr addr:$src1, VR128:$src2)
5251 // So, recognize this potential and also use MOVLPS or MOVLPD
5252 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5256 if (HasSSE2 && NumElems == 2)
5257 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5260 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5263 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5264 // movl and movlp will both match v2i64, but v2i64 is never matched by
5265 // movl earlier because we make it strict to avoid messing with the movlp load
5266 // folding logic (see the code above getMOVLP call). Match it here then,
5267 // this is horrible, but will stay like this until we move all shuffle
5268 // matching to x86 specific nodes. Note that for the 1st condition all
5269 // types are matched with movsd.
5270 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5271 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5273 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5276 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5278 // Invert the operand order and use SHUFPS to match it.
5279 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5280 X86::getShuffleSHUFImmediate(SVOp), DAG);
5283 static inline unsigned getUNPCKLOpcode(EVT VT) {
5284 switch(VT.getSimpleVT().SimpleTy) {
5285 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5286 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5287 case MVT::v4f32: return X86ISD::UNPCKLPS;
5288 case MVT::v2f64: return X86ISD::UNPCKLPD;
5289 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5290 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5292 llvm_unreachable("Unknow type for unpckl");
5297 static inline unsigned getUNPCKHOpcode(EVT VT) {
5298 switch(VT.getSimpleVT().SimpleTy) {
5299 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5300 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5301 case MVT::v4f32: return X86ISD::UNPCKHPS;
5302 case MVT::v2f64: return X86ISD::UNPCKHPD;
5303 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5304 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5306 llvm_unreachable("Unknow type for unpckh");
5312 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5313 const TargetLowering &TLI,
5314 const X86Subtarget *Subtarget) {
5315 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5316 EVT VT = Op.getValueType();
5317 DebugLoc dl = Op.getDebugLoc();
5318 SDValue V1 = Op.getOperand(0);
5319 SDValue V2 = Op.getOperand(1);
5321 if (isZeroShuffle(SVOp))
5322 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5324 // Handle splat operations
5325 if (SVOp->isSplat()) {
5326 // Special case, this is the only place now where it's
5327 // allowed to return a vector_shuffle operation without
5328 // using a target specific node, because *hopefully* it
5329 // will be optimized away by the dag combiner.
5330 if (VT.getVectorNumElements() <= 4 &&
5331 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5334 // Handle splats by matching through known masks
5335 if (VT.getVectorNumElements() <= 4)
5338 // Canonicalize all of the remaining to v4f32.
5339 return PromoteSplat(SVOp, DAG);
5342 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5344 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5345 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5346 if (NewOp.getNode())
5347 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, NewOp);
5348 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5349 // FIXME: Figure out a cleaner way to do this.
5350 // Try to make use of movq to zero out the top part.
5351 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5352 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5353 if (NewOp.getNode()) {
5354 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5355 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5356 DAG, Subtarget, dl);
5358 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5359 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5360 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5361 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5362 DAG, Subtarget, dl);
5369 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5371 SDValue V1 = Op.getOperand(0);
5372 SDValue V2 = Op.getOperand(1);
5373 EVT VT = Op.getValueType();
5374 DebugLoc dl = Op.getDebugLoc();
5375 unsigned NumElems = VT.getVectorNumElements();
5376 bool isMMX = VT.getSizeInBits() == 64;
5377 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5378 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5379 bool V1IsSplat = false;
5380 bool V2IsSplat = false;
5381 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5382 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5383 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5384 MachineFunction &MF = DAG.getMachineFunction();
5385 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5387 // Shuffle operations on MMX not supported.
5391 // Vector shuffle lowering takes 3 steps:
5393 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5394 // narrowing and commutation of operands should be handled.
5395 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5397 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5398 // so the shuffle can be broken into other shuffles and the legalizer can
5399 // try the lowering again.
5401 // The general ideia is that no vector_shuffle operation should be left to
5402 // be matched during isel, all of them must be converted to a target specific
5405 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5406 // narrowing and commutation of operands should be handled. The actual code
5407 // doesn't include all of those, work in progress...
5408 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5409 if (NewOp.getNode())
5412 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5413 // unpckh_undef). Only use pshufd if speed is more important than size.
5414 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5415 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5416 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5417 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5418 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5419 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5421 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5422 RelaxedMayFoldVectorLoad(V1))
5423 return getMOVDDup(Op, dl, V1, DAG);
5425 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5426 return getMOVHighToLow(Op, dl, DAG);
5428 // Use to match splats
5429 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5430 (VT == MVT::v2f64 || VT == MVT::v2i64))
5431 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5433 if (X86::isPSHUFDMask(SVOp)) {
5434 // The actual implementation will match the mask in the if above and then
5435 // during isel it can match several different instructions, not only pshufd
5436 // as its name says, sad but true, emulate the behavior for now...
5437 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5438 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5440 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5442 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5443 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5445 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5446 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5449 if (VT == MVT::v4f32)
5450 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5454 // Check if this can be converted into a logical shift.
5455 bool isLeft = false;
5458 bool isShift = getSubtarget()->hasSSE2() &&
5459 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5460 if (isShift && ShVal.hasOneUse()) {
5461 // If the shifted value has multiple uses, it may be cheaper to use
5462 // v_set0 + movlhps or movhlps, etc.
5463 EVT EltVT = VT.getVectorElementType();
5464 ShAmt *= EltVT.getSizeInBits();
5465 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5468 if (X86::isMOVLMask(SVOp)) {
5471 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5472 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5473 if (!X86::isMOVLPMask(SVOp)) {
5474 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5475 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5477 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5478 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5482 // FIXME: fold these into legal mask.
5483 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5484 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5486 if (X86::isMOVHLPSMask(SVOp))
5487 return getMOVHighToLow(Op, dl, DAG);
5489 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5490 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5492 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5493 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5495 if (X86::isMOVLPMask(SVOp))
5496 return getMOVLP(Op, dl, DAG, HasSSE2);
5498 if (ShouldXformToMOVHLPS(SVOp) ||
5499 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5500 return CommuteVectorShuffle(SVOp, DAG);
5503 // No better options. Use a vshl / vsrl.
5504 EVT EltVT = VT.getVectorElementType();
5505 ShAmt *= EltVT.getSizeInBits();
5506 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5509 bool Commuted = false;
5510 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5511 // 1,1,1,1 -> v8i16 though.
5512 V1IsSplat = isSplatVector(V1.getNode());
5513 V2IsSplat = isSplatVector(V2.getNode());
5515 // Canonicalize the splat or undef, if present, to be on the RHS.
5516 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5517 Op = CommuteVectorShuffle(SVOp, DAG);
5518 SVOp = cast<ShuffleVectorSDNode>(Op);
5519 V1 = SVOp->getOperand(0);
5520 V2 = SVOp->getOperand(1);
5521 std::swap(V1IsSplat, V2IsSplat);
5522 std::swap(V1IsUndef, V2IsUndef);
5526 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5527 // Shuffling low element of v1 into undef, just return v1.
5530 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5531 // the instruction selector will not match, so get a canonical MOVL with
5532 // swapped operands to undo the commute.
5533 return getMOVL(DAG, dl, VT, V2, V1);
5536 if (X86::isUNPCKLMask(SVOp))
5537 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5539 if (X86::isUNPCKHMask(SVOp))
5540 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5543 // Normalize mask so all entries that point to V2 points to its first
5544 // element then try to match unpck{h|l} again. If match, return a
5545 // new vector_shuffle with the corrected mask.
5546 SDValue NewMask = NormalizeMask(SVOp, DAG);
5547 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5548 if (NSVOp != SVOp) {
5549 if (X86::isUNPCKLMask(NSVOp, true)) {
5551 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5558 // Commute is back and try unpck* again.
5559 // FIXME: this seems wrong.
5560 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5561 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5563 if (X86::isUNPCKLMask(NewSVOp))
5564 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5566 if (X86::isUNPCKHMask(NewSVOp))
5567 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5570 // Normalize the node to match x86 shuffle ops if needed
5571 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5572 return CommuteVectorShuffle(SVOp, DAG);
5574 // The checks below are all present in isShuffleMaskLegal, but they are
5575 // inlined here right now to enable us to directly emit target specific
5576 // nodes, and remove one by one until they don't return Op anymore.
5577 SmallVector<int, 16> M;
5580 if (isPALIGNRMask(M, VT, HasSSSE3))
5581 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5582 X86::getShufflePALIGNRImmediate(SVOp),
5585 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5586 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5587 if (VT == MVT::v2f64)
5588 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5589 if (VT == MVT::v2i64)
5590 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5593 if (isPSHUFHWMask(M, VT))
5594 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5595 X86::getShufflePSHUFHWImmediate(SVOp),
5598 if (isPSHUFLWMask(M, VT))
5599 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5600 X86::getShufflePSHUFLWImmediate(SVOp),
5603 if (isSHUFPMask(M, VT)) {
5604 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5605 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5606 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5608 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5609 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5613 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5614 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5615 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5616 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5617 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5618 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5620 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5621 if (VT == MVT::v8i16) {
5622 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5623 if (NewOp.getNode())
5627 if (VT == MVT::v16i8) {
5628 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5629 if (NewOp.getNode())
5633 // Handle all 4 wide cases with a number of shuffles.
5635 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5641 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5642 SelectionDAG &DAG) const {
5643 EVT VT = Op.getValueType();
5644 DebugLoc dl = Op.getDebugLoc();
5645 if (VT.getSizeInBits() == 8) {
5646 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5647 Op.getOperand(0), Op.getOperand(1));
5648 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5649 DAG.getValueType(VT));
5650 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5651 } else if (VT.getSizeInBits() == 16) {
5652 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5653 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5655 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5657 DAG.getNode(ISD::BIT_CONVERT, dl,
5661 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5662 Op.getOperand(0), Op.getOperand(1));
5663 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5664 DAG.getValueType(VT));
5665 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5666 } else if (VT == MVT::f32) {
5667 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5668 // the result back to FR32 register. It's only worth matching if the
5669 // result has a single use which is a store or a bitcast to i32. And in
5670 // the case of a store, it's not worth it if the index is a constant 0,
5671 // because a MOVSSmr can be used instead, which is smaller and faster.
5672 if (!Op.hasOneUse())
5674 SDNode *User = *Op.getNode()->use_begin();
5675 if ((User->getOpcode() != ISD::STORE ||
5676 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5677 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5678 (User->getOpcode() != ISD::BIT_CONVERT ||
5679 User->getValueType(0) != MVT::i32))
5681 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5682 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
5685 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
5686 } else if (VT == MVT::i32) {
5687 // ExtractPS works with constant index.
5688 if (isa<ConstantSDNode>(Op.getOperand(1)))
5696 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5697 SelectionDAG &DAG) const {
5698 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5701 if (Subtarget->hasSSE41()) {
5702 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5707 EVT VT = Op.getValueType();
5708 DebugLoc dl = Op.getDebugLoc();
5709 // TODO: handle v16i8.
5710 if (VT.getSizeInBits() == 16) {
5711 SDValue Vec = Op.getOperand(0);
5712 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5714 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5715 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5716 DAG.getNode(ISD::BIT_CONVERT, dl,
5719 // Transform it so it match pextrw which produces a 32-bit result.
5720 EVT EltVT = MVT::i32;
5721 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5722 Op.getOperand(0), Op.getOperand(1));
5723 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5724 DAG.getValueType(VT));
5725 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5726 } else if (VT.getSizeInBits() == 32) {
5727 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5731 // SHUFPS the element to the lowest double word, then movss.
5732 int Mask[4] = { Idx, -1, -1, -1 };
5733 EVT VVT = Op.getOperand(0).getValueType();
5734 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5735 DAG.getUNDEF(VVT), Mask);
5736 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5737 DAG.getIntPtrConstant(0));
5738 } else if (VT.getSizeInBits() == 64) {
5739 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5740 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5741 // to match extract_elt for f64.
5742 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5746 // UNPCKHPD the element to the lowest double word, then movsd.
5747 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5748 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5749 int Mask[2] = { 1, -1 };
5750 EVT VVT = Op.getOperand(0).getValueType();
5751 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5752 DAG.getUNDEF(VVT), Mask);
5753 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5754 DAG.getIntPtrConstant(0));
5761 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5762 SelectionDAG &DAG) const {
5763 EVT VT = Op.getValueType();
5764 EVT EltVT = VT.getVectorElementType();
5765 DebugLoc dl = Op.getDebugLoc();
5767 SDValue N0 = Op.getOperand(0);
5768 SDValue N1 = Op.getOperand(1);
5769 SDValue N2 = Op.getOperand(2);
5771 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5772 isa<ConstantSDNode>(N2)) {
5774 if (VT == MVT::v8i16)
5775 Opc = X86ISD::PINSRW;
5776 else if (VT == MVT::v16i8)
5777 Opc = X86ISD::PINSRB;
5779 Opc = X86ISD::PINSRB;
5781 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5783 if (N1.getValueType() != MVT::i32)
5784 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5785 if (N2.getValueType() != MVT::i32)
5786 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5787 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5788 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5789 // Bits [7:6] of the constant are the source select. This will always be
5790 // zero here. The DAG Combiner may combine an extract_elt index into these
5791 // bits. For example (insert (extract, 3), 2) could be matched by putting
5792 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5793 // Bits [5:4] of the constant are the destination select. This is the
5794 // value of the incoming immediate.
5795 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5796 // combine either bitwise AND or insert of float 0.0 to set these bits.
5797 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5798 // Create this as a scalar to vector..
5799 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5800 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5801 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5802 // PINSR* works with constant index.
5809 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5810 EVT VT = Op.getValueType();
5811 EVT EltVT = VT.getVectorElementType();
5813 if (Subtarget->hasSSE41())
5814 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5816 if (EltVT == MVT::i8)
5819 DebugLoc dl = Op.getDebugLoc();
5820 SDValue N0 = Op.getOperand(0);
5821 SDValue N1 = Op.getOperand(1);
5822 SDValue N2 = Op.getOperand(2);
5824 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5825 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5826 // as its second argument.
5827 if (N1.getValueType() != MVT::i32)
5828 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5829 if (N2.getValueType() != MVT::i32)
5830 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5831 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
5837 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5838 DebugLoc dl = Op.getDebugLoc();
5840 if (Op.getValueType() == MVT::v1i64 &&
5841 Op.getOperand(0).getValueType() == MVT::i64)
5842 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5844 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5845 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
5846 "Expected an SSE type!");
5847 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5848 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
5851 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5852 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5853 // one of the above mentioned nodes. It has to be wrapped because otherwise
5854 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5855 // be used to form addressing mode. These wrapped nodes will be selected
5858 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5859 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5861 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5863 unsigned char OpFlag = 0;
5864 unsigned WrapperKind = X86ISD::Wrapper;
5865 CodeModel::Model M = getTargetMachine().getCodeModel();
5867 if (Subtarget->isPICStyleRIPRel() &&
5868 (M == CodeModel::Small || M == CodeModel::Kernel))
5869 WrapperKind = X86ISD::WrapperRIP;
5870 else if (Subtarget->isPICStyleGOT())
5871 OpFlag = X86II::MO_GOTOFF;
5872 else if (Subtarget->isPICStyleStubPIC())
5873 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5875 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5877 CP->getOffset(), OpFlag);
5878 DebugLoc DL = CP->getDebugLoc();
5879 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5880 // With PIC, the address is actually $g + Offset.
5882 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5883 DAG.getNode(X86ISD::GlobalBaseReg,
5884 DebugLoc(), getPointerTy()),
5891 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5892 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5894 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5896 unsigned char OpFlag = 0;
5897 unsigned WrapperKind = X86ISD::Wrapper;
5898 CodeModel::Model M = getTargetMachine().getCodeModel();
5900 if (Subtarget->isPICStyleRIPRel() &&
5901 (M == CodeModel::Small || M == CodeModel::Kernel))
5902 WrapperKind = X86ISD::WrapperRIP;
5903 else if (Subtarget->isPICStyleGOT())
5904 OpFlag = X86II::MO_GOTOFF;
5905 else if (Subtarget->isPICStyleStubPIC())
5906 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5908 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5910 DebugLoc DL = JT->getDebugLoc();
5911 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5913 // With PIC, the address is actually $g + Offset.
5915 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5916 DAG.getNode(X86ISD::GlobalBaseReg,
5917 DebugLoc(), getPointerTy()),
5925 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5926 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5928 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5930 unsigned char OpFlag = 0;
5931 unsigned WrapperKind = X86ISD::Wrapper;
5932 CodeModel::Model M = getTargetMachine().getCodeModel();
5934 if (Subtarget->isPICStyleRIPRel() &&
5935 (M == CodeModel::Small || M == CodeModel::Kernel))
5936 WrapperKind = X86ISD::WrapperRIP;
5937 else if (Subtarget->isPICStyleGOT())
5938 OpFlag = X86II::MO_GOTOFF;
5939 else if (Subtarget->isPICStyleStubPIC())
5940 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5942 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5944 DebugLoc DL = Op.getDebugLoc();
5945 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5948 // With PIC, the address is actually $g + Offset.
5949 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5950 !Subtarget->is64Bit()) {
5951 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5952 DAG.getNode(X86ISD::GlobalBaseReg,
5953 DebugLoc(), getPointerTy()),
5961 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5962 // Create the TargetBlockAddressAddress node.
5963 unsigned char OpFlags =
5964 Subtarget->ClassifyBlockAddressReference();
5965 CodeModel::Model M = getTargetMachine().getCodeModel();
5966 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5967 DebugLoc dl = Op.getDebugLoc();
5968 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5969 /*isTarget=*/true, OpFlags);
5971 if (Subtarget->isPICStyleRIPRel() &&
5972 (M == CodeModel::Small || M == CodeModel::Kernel))
5973 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5975 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5977 // With PIC, the address is actually $g + Offset.
5978 if (isGlobalRelativeToPICBase(OpFlags)) {
5979 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5980 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5988 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5990 SelectionDAG &DAG) const {
5991 // Create the TargetGlobalAddress node, folding in the constant
5992 // offset if it is legal.
5993 unsigned char OpFlags =
5994 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5995 CodeModel::Model M = getTargetMachine().getCodeModel();
5997 if (OpFlags == X86II::MO_NO_FLAG &&
5998 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5999 // A direct static reference to a global.
6000 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
6003 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6006 if (Subtarget->isPICStyleRIPRel() &&
6007 (M == CodeModel::Small || M == CodeModel::Kernel))
6008 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6010 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6012 // With PIC, the address is actually $g + Offset.
6013 if (isGlobalRelativeToPICBase(OpFlags)) {
6014 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6015 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6019 // For globals that require a load from a stub to get the address, emit the
6021 if (isGlobalStubReference(OpFlags))
6022 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6023 MachinePointerInfo::getGOT(), false, false, 0);
6025 // If there was a non-zero offset that we didn't fold, create an explicit
6028 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6029 DAG.getConstant(Offset, getPointerTy()));
6035 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6036 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6037 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6038 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6042 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6043 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6044 unsigned char OperandFlags) {
6045 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6046 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6047 DebugLoc dl = GA->getDebugLoc();
6048 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6049 GA->getValueType(0),
6053 SDValue Ops[] = { Chain, TGA, *InFlag };
6054 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6056 SDValue Ops[] = { Chain, TGA };
6057 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6060 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6061 MFI->setAdjustsStack(true);
6063 SDValue Flag = Chain.getValue(1);
6064 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6067 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6069 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6072 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6073 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6074 DAG.getNode(X86ISD::GlobalBaseReg,
6075 DebugLoc(), PtrVT), InFlag);
6076 InFlag = Chain.getValue(1);
6078 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6081 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6083 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6085 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6086 X86::RAX, X86II::MO_TLSGD);
6089 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6090 // "local exec" model.
6091 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6092 const EVT PtrVT, TLSModel::Model model,
6094 DebugLoc dl = GA->getDebugLoc();
6096 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6097 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6098 is64Bit ? 257 : 256));
6100 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6101 DAG.getIntPtrConstant(0),
6102 MachinePointerInfo(Ptr), false, false, 0);
6104 unsigned char OperandFlags = 0;
6105 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6107 unsigned WrapperKind = X86ISD::Wrapper;
6108 if (model == TLSModel::LocalExec) {
6109 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6110 } else if (is64Bit) {
6111 assert(model == TLSModel::InitialExec);
6112 OperandFlags = X86II::MO_GOTTPOFF;
6113 WrapperKind = X86ISD::WrapperRIP;
6115 assert(model == TLSModel::InitialExec);
6116 OperandFlags = X86II::MO_INDNTPOFF;
6119 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6121 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6122 GA->getValueType(0),
6123 GA->getOffset(), OperandFlags);
6124 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6126 if (model == TLSModel::InitialExec)
6127 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6128 MachinePointerInfo::getGOT(), false, false, 0);
6130 // The address of the thread local variable is the add of the thread
6131 // pointer with the offset of the variable.
6132 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6136 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6138 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6139 const GlobalValue *GV = GA->getGlobal();
6141 if (Subtarget->isTargetELF()) {
6142 // TODO: implement the "local dynamic" model
6143 // TODO: implement the "initial exec"model for pic executables
6145 // If GV is an alias then use the aliasee for determining
6146 // thread-localness.
6147 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6148 GV = GA->resolveAliasedGlobal(false);
6150 TLSModel::Model model
6151 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6154 case TLSModel::GeneralDynamic:
6155 case TLSModel::LocalDynamic: // not implemented
6156 if (Subtarget->is64Bit())
6157 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6158 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6160 case TLSModel::InitialExec:
6161 case TLSModel::LocalExec:
6162 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6163 Subtarget->is64Bit());
6165 } else if (Subtarget->isTargetDarwin()) {
6166 // Darwin only has one model of TLS. Lower to that.
6167 unsigned char OpFlag = 0;
6168 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6169 X86ISD::WrapperRIP : X86ISD::Wrapper;
6171 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6173 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6174 !Subtarget->is64Bit();
6176 OpFlag = X86II::MO_TLVP_PIC_BASE;
6178 OpFlag = X86II::MO_TLVP;
6179 DebugLoc DL = Op.getDebugLoc();
6180 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6182 GA->getOffset(), OpFlag);
6183 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6185 // With PIC32, the address is actually $g + Offset.
6187 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6188 DAG.getNode(X86ISD::GlobalBaseReg,
6189 DebugLoc(), getPointerTy()),
6192 // Lowering the machine isd will make sure everything is in the right
6194 SDValue Args[] = { Offset };
6195 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
6197 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6198 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6199 MFI->setAdjustsStack(true);
6201 // And our return value (tls address) is in the standard call return value
6203 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6204 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6208 "TLS not implemented for this target.");
6210 llvm_unreachable("Unreachable");
6215 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6216 /// take a 2 x i32 value to shift plus a shift amount.
6217 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6218 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6219 EVT VT = Op.getValueType();
6220 unsigned VTBits = VT.getSizeInBits();
6221 DebugLoc dl = Op.getDebugLoc();
6222 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6223 SDValue ShOpLo = Op.getOperand(0);
6224 SDValue ShOpHi = Op.getOperand(1);
6225 SDValue ShAmt = Op.getOperand(2);
6226 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6227 DAG.getConstant(VTBits - 1, MVT::i8))
6228 : DAG.getConstant(0, VT);
6231 if (Op.getOpcode() == ISD::SHL_PARTS) {
6232 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6233 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6235 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6236 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6239 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6240 DAG.getConstant(VTBits, MVT::i8));
6241 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6242 AndNode, DAG.getConstant(0, MVT::i8));
6245 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6246 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6247 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6249 if (Op.getOpcode() == ISD::SHL_PARTS) {
6250 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6251 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6253 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6254 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6257 SDValue Ops[2] = { Lo, Hi };
6258 return DAG.getMergeValues(Ops, 2, dl);
6261 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6262 SelectionDAG &DAG) const {
6263 EVT SrcVT = Op.getOperand(0).getValueType();
6265 if (SrcVT.isVector())
6268 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6269 "Unknown SINT_TO_FP to lower!");
6271 // These are really Legal; return the operand so the caller accepts it as
6273 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6275 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6276 Subtarget->is64Bit()) {
6280 DebugLoc dl = Op.getDebugLoc();
6281 unsigned Size = SrcVT.getSizeInBits()/8;
6282 MachineFunction &MF = DAG.getMachineFunction();
6283 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6284 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6285 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6287 MachinePointerInfo::getFixedStack(SSFI),
6289 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6292 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6294 SelectionDAG &DAG) const {
6296 DebugLoc DL = Op.getDebugLoc();
6298 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6300 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
6302 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6304 unsigned ByteSize = SrcVT.getSizeInBits()/8;
6306 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6307 MachineMemOperand *MMO =
6308 DAG.getMachineFunction()
6309 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6310 MachineMemOperand::MOLoad, ByteSize, ByteSize);
6312 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6313 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
6315 Tys, Ops, array_lengthof(Ops),
6319 Chain = Result.getValue(1);
6320 SDValue InFlag = Result.getValue(2);
6322 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6323 // shouldn't be necessary except that RFP cannot be live across
6324 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6325 MachineFunction &MF = DAG.getMachineFunction();
6326 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
6327 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
6328 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6329 Tys = DAG.getVTList(MVT::Other);
6331 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6333 MachineMemOperand *MMO =
6334 DAG.getMachineFunction()
6335 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6336 MachineMemOperand::MOStore, SSFISize, SSFISize);
6338 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
6339 Ops, array_lengthof(Ops),
6340 Op.getValueType(), MMO);
6341 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
6342 MachinePointerInfo::getFixedStack(SSFI),
6349 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6350 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6351 SelectionDAG &DAG) const {
6352 // This algorithm is not obvious. Here it is in C code, more or less:
6354 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6355 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6356 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6358 // Copy ints to xmm registers.
6359 __m128i xh = _mm_cvtsi32_si128( hi );
6360 __m128i xl = _mm_cvtsi32_si128( lo );
6362 // Combine into low half of a single xmm register.
6363 __m128i x = _mm_unpacklo_epi32( xh, xl );
6367 // Merge in appropriate exponents to give the integer bits the right
6369 x = _mm_unpacklo_epi32( x, exp );
6371 // Subtract away the biases to deal with the IEEE-754 double precision
6373 d = _mm_sub_pd( (__m128d) x, bias );
6375 // All conversions up to here are exact. The correctly rounded result is
6376 // calculated using the current rounding mode using the following
6378 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6379 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6380 // store doesn't really need to be here (except
6381 // maybe to zero the other double)
6386 DebugLoc dl = Op.getDebugLoc();
6387 LLVMContext *Context = DAG.getContext();
6389 // Build some magic constants.
6390 std::vector<Constant*> CV0;
6391 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6392 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6393 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6394 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6395 Constant *C0 = ConstantVector::get(CV0);
6396 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6398 std::vector<Constant*> CV1;
6400 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6402 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6403 Constant *C1 = ConstantVector::get(CV1);
6404 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6406 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6407 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6409 DAG.getIntPtrConstant(1)));
6410 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6411 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6413 DAG.getIntPtrConstant(0)));
6414 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6415 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6416 MachinePointerInfo::getConstantPool(),
6418 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6419 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
6420 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6421 MachinePointerInfo::getConstantPool(),
6423 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6425 // Add the halves; easiest way is to swap them into another reg first.
6426 int ShufMask[2] = { 1, -1 };
6427 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6428 DAG.getUNDEF(MVT::v2f64), ShufMask);
6429 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6430 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6431 DAG.getIntPtrConstant(0));
6434 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6435 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6436 SelectionDAG &DAG) const {
6437 DebugLoc dl = Op.getDebugLoc();
6438 // FP constant to bias correct the final result.
6439 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6442 // Load the 32-bit value into an XMM register.
6443 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6444 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6446 DAG.getIntPtrConstant(0)));
6448 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6449 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
6450 DAG.getIntPtrConstant(0));
6452 // Or the load with the bias.
6453 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6454 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6455 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6457 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6458 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6459 MVT::v2f64, Bias)));
6460 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6461 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
6462 DAG.getIntPtrConstant(0));
6464 // Subtract the bias.
6465 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6467 // Handle final rounding.
6468 EVT DestVT = Op.getValueType();
6470 if (DestVT.bitsLT(MVT::f64)) {
6471 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6472 DAG.getIntPtrConstant(0));
6473 } else if (DestVT.bitsGT(MVT::f64)) {
6474 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6477 // Handle final rounding.
6481 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6482 SelectionDAG &DAG) const {
6483 SDValue N0 = Op.getOperand(0);
6484 DebugLoc dl = Op.getDebugLoc();
6486 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6487 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6488 // the optimization here.
6489 if (DAG.SignBitIsZero(N0))
6490 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6492 EVT SrcVT = N0.getValueType();
6493 EVT DstVT = Op.getValueType();
6494 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6495 return LowerUINT_TO_FP_i64(Op, DAG);
6496 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6497 return LowerUINT_TO_FP_i32(Op, DAG);
6499 // Make a 64-bit buffer, and use it to build an FILD.
6500 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6501 if (SrcVT == MVT::i32) {
6502 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6503 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6504 getPointerTy(), StackSlot, WordOff);
6505 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6506 StackSlot, MachinePointerInfo(),
6508 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6509 OffsetSlot, MachinePointerInfo(),
6511 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6515 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6516 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6517 StackSlot, MachinePointerInfo(),
6519 // For i64 source, we need to add the appropriate power of 2 if the input
6520 // was negative. This is the same as the optimization in
6521 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6522 // we must be careful to do the computation in x87 extended precision, not
6523 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6524 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6525 MachineMemOperand *MMO =
6526 DAG.getMachineFunction()
6527 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6528 MachineMemOperand::MOLoad, 8, 8);
6530 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6531 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6532 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
6535 APInt FF(32, 0x5F800000ULL);
6537 // Check whether the sign bit is set.
6538 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6539 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6542 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6543 SDValue FudgePtr = DAG.getConstantPool(
6544 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6547 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6548 SDValue Zero = DAG.getIntPtrConstant(0);
6549 SDValue Four = DAG.getIntPtrConstant(4);
6550 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6552 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6554 // Load the value out, extending it from f32 to f80.
6555 // FIXME: Avoid the extend by constructing the right constant pool?
6556 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6557 FudgePtr, MachinePointerInfo::getConstantPool(),
6558 MVT::f32, false, false, 4);
6559 // Extend everything to 80 bits to force it to be done on x87.
6560 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6561 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6564 std::pair<SDValue,SDValue> X86TargetLowering::
6565 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6566 DebugLoc DL = Op.getDebugLoc();
6568 EVT DstTy = Op.getValueType();
6571 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6575 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6576 DstTy.getSimpleVT() >= MVT::i16 &&
6577 "Unknown FP_TO_SINT to lower!");
6579 // These are really Legal.
6580 if (DstTy == MVT::i32 &&
6581 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6582 return std::make_pair(SDValue(), SDValue());
6583 if (Subtarget->is64Bit() &&
6584 DstTy == MVT::i64 &&
6585 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6586 return std::make_pair(SDValue(), SDValue());
6588 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6590 MachineFunction &MF = DAG.getMachineFunction();
6591 unsigned MemSize = DstTy.getSizeInBits()/8;
6592 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6593 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6598 switch (DstTy.getSimpleVT().SimpleTy) {
6599 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6600 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6601 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6602 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6605 SDValue Chain = DAG.getEntryNode();
6606 SDValue Value = Op.getOperand(0);
6607 EVT TheVT = Op.getOperand(0).getValueType();
6608 if (isScalarFPTypeInSSEReg(TheVT)) {
6609 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6610 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
6611 MachinePointerInfo::getFixedStack(SSFI),
6613 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6615 Chain, StackSlot, DAG.getValueType(TheVT)
6618 MachineMemOperand *MMO =
6619 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6620 MachineMemOperand::MOLoad, MemSize, MemSize);
6621 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
6623 Chain = Value.getValue(1);
6624 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6625 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6628 MachineMemOperand *MMO =
6629 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6630 MachineMemOperand::MOStore, MemSize, MemSize);
6632 // Build the FP_TO_INT*_IN_MEM
6633 SDValue Ops[] = { Chain, Value, StackSlot };
6634 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
6635 Ops, 3, DstTy, MMO);
6637 return std::make_pair(FIST, StackSlot);
6640 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6641 SelectionDAG &DAG) const {
6642 if (Op.getValueType().isVector())
6645 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6646 SDValue FIST = Vals.first, StackSlot = Vals.second;
6647 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6648 if (FIST.getNode() == 0) return Op;
6651 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6652 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6655 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6656 SelectionDAG &DAG) const {
6657 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6658 SDValue FIST = Vals.first, StackSlot = Vals.second;
6659 assert(FIST.getNode() && "Unexpected failure");
6662 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6663 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6666 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6667 SelectionDAG &DAG) const {
6668 LLVMContext *Context = DAG.getContext();
6669 DebugLoc dl = Op.getDebugLoc();
6670 EVT VT = Op.getValueType();
6673 EltVT = VT.getVectorElementType();
6674 std::vector<Constant*> CV;
6675 if (EltVT == MVT::f64) {
6676 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6680 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6686 Constant *C = ConstantVector::get(CV);
6687 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6688 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6689 MachinePointerInfo::getConstantPool(),
6691 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6694 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6695 LLVMContext *Context = DAG.getContext();
6696 DebugLoc dl = Op.getDebugLoc();
6697 EVT VT = Op.getValueType();
6700 EltVT = VT.getVectorElementType();
6701 std::vector<Constant*> CV;
6702 if (EltVT == MVT::f64) {
6703 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6707 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6713 Constant *C = ConstantVector::get(CV);
6714 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6715 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6716 MachinePointerInfo::getConstantPool(),
6718 if (VT.isVector()) {
6719 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6720 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6721 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6723 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
6725 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6729 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6730 LLVMContext *Context = DAG.getContext();
6731 SDValue Op0 = Op.getOperand(0);
6732 SDValue Op1 = Op.getOperand(1);
6733 DebugLoc dl = Op.getDebugLoc();
6734 EVT VT = Op.getValueType();
6735 EVT SrcVT = Op1.getValueType();
6737 // If second operand is smaller, extend it first.
6738 if (SrcVT.bitsLT(VT)) {
6739 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6742 // And if it is bigger, shrink it first.
6743 if (SrcVT.bitsGT(VT)) {
6744 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6748 // At this point the operands and the result should have the same
6749 // type, and that won't be f80 since that is not custom lowered.
6751 // First get the sign bit of second operand.
6752 std::vector<Constant*> CV;
6753 if (SrcVT == MVT::f64) {
6754 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6755 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6757 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6758 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6759 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6760 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6762 Constant *C = ConstantVector::get(CV);
6763 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6764 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6765 MachinePointerInfo::getConstantPool(),
6767 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6769 // Shift sign bit right or left if the two operands have different types.
6770 if (SrcVT.bitsGT(VT)) {
6771 // Op0 is MVT::f32, Op1 is MVT::f64.
6772 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6773 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6774 DAG.getConstant(32, MVT::i32));
6775 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
6776 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6777 DAG.getIntPtrConstant(0));
6780 // Clear first operand sign bit.
6782 if (VT == MVT::f64) {
6783 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6784 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6786 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6787 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6788 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6789 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6791 C = ConstantVector::get(CV);
6792 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6793 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6794 MachinePointerInfo::getConstantPool(),
6796 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6798 // Or the value with the sign bit.
6799 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6802 /// Emit nodes that will be selected as "test Op0,Op0", or something
6804 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6805 SelectionDAG &DAG) const {
6806 DebugLoc dl = Op.getDebugLoc();
6808 // CF and OF aren't always set the way we want. Determine which
6809 // of these we need.
6810 bool NeedCF = false;
6811 bool NeedOF = false;
6814 case X86::COND_A: case X86::COND_AE:
6815 case X86::COND_B: case X86::COND_BE:
6818 case X86::COND_G: case X86::COND_GE:
6819 case X86::COND_L: case X86::COND_LE:
6820 case X86::COND_O: case X86::COND_NO:
6825 // See if we can use the EFLAGS value from the operand instead of
6826 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6827 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6828 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6829 // Emit a CMP with 0, which is the TEST pattern.
6830 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6831 DAG.getConstant(0, Op.getValueType()));
6833 unsigned Opcode = 0;
6834 unsigned NumOperands = 0;
6835 switch (Op.getNode()->getOpcode()) {
6837 // Due to an isel shortcoming, be conservative if this add is likely to be
6838 // selected as part of a load-modify-store instruction. When the root node
6839 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6840 // uses of other nodes in the match, such as the ADD in this case. This
6841 // leads to the ADD being left around and reselected, with the result being
6842 // two adds in the output. Alas, even if none our users are stores, that
6843 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6844 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6845 // climbing the DAG back to the root, and it doesn't seem to be worth the
6847 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6848 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6849 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6852 if (ConstantSDNode *C =
6853 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6854 // An add of one will be selected as an INC.
6855 if (C->getAPIntValue() == 1) {
6856 Opcode = X86ISD::INC;
6861 // An add of negative one (subtract of one) will be selected as a DEC.
6862 if (C->getAPIntValue().isAllOnesValue()) {
6863 Opcode = X86ISD::DEC;
6869 // Otherwise use a regular EFLAGS-setting add.
6870 Opcode = X86ISD::ADD;
6874 // If the primary and result isn't used, don't bother using X86ISD::AND,
6875 // because a TEST instruction will be better.
6876 bool NonFlagUse = false;
6877 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6878 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6880 unsigned UOpNo = UI.getOperandNo();
6881 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6882 // Look pass truncate.
6883 UOpNo = User->use_begin().getOperandNo();
6884 User = *User->use_begin();
6887 if (User->getOpcode() != ISD::BRCOND &&
6888 User->getOpcode() != ISD::SETCC &&
6889 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6902 // Due to the ISEL shortcoming noted above, be conservative if this op is
6903 // likely to be selected as part of a load-modify-store instruction.
6904 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6905 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6906 if (UI->getOpcode() == ISD::STORE)
6909 // Otherwise use a regular EFLAGS-setting instruction.
6910 switch (Op.getNode()->getOpcode()) {
6911 default: llvm_unreachable("unexpected operator!");
6912 case ISD::SUB: Opcode = X86ISD::SUB; break;
6913 case ISD::OR: Opcode = X86ISD::OR; break;
6914 case ISD::XOR: Opcode = X86ISD::XOR; break;
6915 case ISD::AND: Opcode = X86ISD::AND; break;
6927 return SDValue(Op.getNode(), 1);
6934 // Emit a CMP with 0, which is the TEST pattern.
6935 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6936 DAG.getConstant(0, Op.getValueType()));
6938 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6939 SmallVector<SDValue, 4> Ops;
6940 for (unsigned i = 0; i != NumOperands; ++i)
6941 Ops.push_back(Op.getOperand(i));
6943 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6944 DAG.ReplaceAllUsesWith(Op, New);
6945 return SDValue(New.getNode(), 1);
6948 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6950 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6951 SelectionDAG &DAG) const {
6952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6953 if (C->getAPIntValue() == 0)
6954 return EmitTest(Op0, X86CC, DAG);
6956 DebugLoc dl = Op0.getDebugLoc();
6957 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6960 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6961 /// if it's possible.
6962 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6963 DebugLoc dl, SelectionDAG &DAG) const {
6964 SDValue Op0 = And.getOperand(0);
6965 SDValue Op1 = And.getOperand(1);
6966 if (Op0.getOpcode() == ISD::TRUNCATE)
6967 Op0 = Op0.getOperand(0);
6968 if (Op1.getOpcode() == ISD::TRUNCATE)
6969 Op1 = Op1.getOperand(0);
6972 if (Op1.getOpcode() == ISD::SHL)
6973 std::swap(Op0, Op1);
6974 if (Op0.getOpcode() == ISD::SHL) {
6975 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6976 if (And00C->getZExtValue() == 1) {
6977 // If we looked past a truncate, check that it's only truncating away
6979 unsigned BitWidth = Op0.getValueSizeInBits();
6980 unsigned AndBitWidth = And.getValueSizeInBits();
6981 if (BitWidth > AndBitWidth) {
6982 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6983 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6984 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6988 RHS = Op0.getOperand(1);
6990 } else if (Op1.getOpcode() == ISD::Constant) {
6991 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6992 SDValue AndLHS = Op0;
6993 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6994 LHS = AndLHS.getOperand(0);
6995 RHS = AndLHS.getOperand(1);
6999 if (LHS.getNode()) {
7000 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
7001 // instruction. Since the shift amount is in-range-or-undefined, we know
7002 // that doing a bittest on the i32 value is ok. We extend to i32 because
7003 // the encoding for the i16 version is larger than the i32 version.
7004 // Also promote i16 to i32 for performance / code size reason.
7005 if (LHS.getValueType() == MVT::i8 ||
7006 LHS.getValueType() == MVT::i16)
7007 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7009 // If the operand types disagree, extend the shift amount to match. Since
7010 // BT ignores high bits (like shifts) we can use anyextend.
7011 if (LHS.getValueType() != RHS.getValueType())
7012 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7014 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7015 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7016 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7017 DAG.getConstant(Cond, MVT::i8), BT);
7023 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7024 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7025 SDValue Op0 = Op.getOperand(0);
7026 SDValue Op1 = Op.getOperand(1);
7027 DebugLoc dl = Op.getDebugLoc();
7028 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7030 // Optimize to BT if possible.
7031 // Lower (X & (1 << N)) == 0 to BT(X, N).
7032 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7033 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7034 if (Op0.getOpcode() == ISD::AND &&
7036 Op1.getOpcode() == ISD::Constant &&
7037 cast<ConstantSDNode>(Op1)->isNullValue() &&
7038 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7039 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7040 if (NewSetCC.getNode())
7044 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
7045 if (Op0.getOpcode() == X86ISD::SETCC &&
7046 Op1.getOpcode() == ISD::Constant &&
7047 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7048 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7049 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7050 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7051 bool Invert = (CC == ISD::SETNE) ^
7052 cast<ConstantSDNode>(Op1)->isNullValue();
7054 CCode = X86::GetOppositeBranchCondition(CCode);
7055 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7056 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7059 bool isFP = Op1.getValueType().isFloatingPoint();
7060 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7061 if (X86CC == X86::COND_INVALID)
7064 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
7066 // Use sbb x, x to materialize carry bit into a GPR.
7067 if (X86CC == X86::COND_B)
7068 return DAG.getNode(ISD::AND, dl, MVT::i8,
7069 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
7070 DAG.getConstant(X86CC, MVT::i8), Cond),
7071 DAG.getConstant(1, MVT::i8));
7073 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7074 DAG.getConstant(X86CC, MVT::i8), Cond);
7077 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7079 SDValue Op0 = Op.getOperand(0);
7080 SDValue Op1 = Op.getOperand(1);
7081 SDValue CC = Op.getOperand(2);
7082 EVT VT = Op.getValueType();
7083 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7084 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7085 DebugLoc dl = Op.getDebugLoc();
7089 EVT VT0 = Op0.getValueType();
7090 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7091 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7094 switch (SetCCOpcode) {
7097 case ISD::SETEQ: SSECC = 0; break;
7099 case ISD::SETGT: Swap = true; // Fallthrough
7101 case ISD::SETOLT: SSECC = 1; break;
7103 case ISD::SETGE: Swap = true; // Fallthrough
7105 case ISD::SETOLE: SSECC = 2; break;
7106 case ISD::SETUO: SSECC = 3; break;
7108 case ISD::SETNE: SSECC = 4; break;
7109 case ISD::SETULE: Swap = true;
7110 case ISD::SETUGE: SSECC = 5; break;
7111 case ISD::SETULT: Swap = true;
7112 case ISD::SETUGT: SSECC = 6; break;
7113 case ISD::SETO: SSECC = 7; break;
7116 std::swap(Op0, Op1);
7118 // In the two special cases we can't handle, emit two comparisons.
7120 if (SetCCOpcode == ISD::SETUEQ) {
7122 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7123 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7124 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7126 else if (SetCCOpcode == ISD::SETONE) {
7128 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7129 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7130 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7132 llvm_unreachable("Illegal FP comparison");
7134 // Handle all other FP comparisons here.
7135 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7138 // We are handling one of the integer comparisons here. Since SSE only has
7139 // GT and EQ comparisons for integer, swapping operands and multiple
7140 // operations may be required for some comparisons.
7141 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7142 bool Swap = false, Invert = false, FlipSigns = false;
7144 switch (VT.getSimpleVT().SimpleTy) {
7146 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7147 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7148 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7149 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7152 switch (SetCCOpcode) {
7154 case ISD::SETNE: Invert = true;
7155 case ISD::SETEQ: Opc = EQOpc; break;
7156 case ISD::SETLT: Swap = true;
7157 case ISD::SETGT: Opc = GTOpc; break;
7158 case ISD::SETGE: Swap = true;
7159 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7160 case ISD::SETULT: Swap = true;
7161 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7162 case ISD::SETUGE: Swap = true;
7163 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7166 std::swap(Op0, Op1);
7168 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7169 // bits of the inputs before performing those operations.
7171 EVT EltVT = VT.getVectorElementType();
7172 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7174 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7175 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7177 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7178 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7181 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7183 // If the logical-not of the result is required, perform that now.
7185 Result = DAG.getNOT(dl, Result, VT);
7190 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7191 static bool isX86LogicalCmp(SDValue Op) {
7192 unsigned Opc = Op.getNode()->getOpcode();
7193 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7195 if (Op.getResNo() == 1 &&
7196 (Opc == X86ISD::ADD ||
7197 Opc == X86ISD::SUB ||
7198 Opc == X86ISD::SMUL ||
7199 Opc == X86ISD::UMUL ||
7200 Opc == X86ISD::INC ||
7201 Opc == X86ISD::DEC ||
7202 Opc == X86ISD::OR ||
7203 Opc == X86ISD::XOR ||
7204 Opc == X86ISD::AND))
7210 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7211 bool addTest = true;
7212 SDValue Cond = Op.getOperand(0);
7213 DebugLoc dl = Op.getDebugLoc();
7216 if (Cond.getOpcode() == ISD::SETCC) {
7217 SDValue NewCond = LowerSETCC(Cond, DAG);
7218 if (NewCond.getNode())
7222 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
7223 SDValue Op1 = Op.getOperand(1);
7224 SDValue Op2 = Op.getOperand(2);
7225 if (Cond.getOpcode() == X86ISD::SETCC &&
7226 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
7227 SDValue Cmp = Cond.getOperand(1);
7228 if (Cmp.getOpcode() == X86ISD::CMP) {
7229 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
7230 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7231 ConstantSDNode *RHSC =
7232 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
7233 if (N1C && N1C->isAllOnesValue() &&
7234 N2C && N2C->isNullValue() &&
7235 RHSC && RHSC->isNullValue()) {
7236 SDValue CmpOp0 = Cmp.getOperand(0);
7237 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7238 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7239 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
7240 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7245 // Look pass (and (setcc_carry (cmp ...)), 1).
7246 if (Cond.getOpcode() == ISD::AND &&
7247 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7248 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7249 if (C && C->getAPIntValue() == 1)
7250 Cond = Cond.getOperand(0);
7253 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7254 // setting operand in place of the X86ISD::SETCC.
7255 if (Cond.getOpcode() == X86ISD::SETCC ||
7256 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7257 CC = Cond.getOperand(0);
7259 SDValue Cmp = Cond.getOperand(1);
7260 unsigned Opc = Cmp.getOpcode();
7261 EVT VT = Op.getValueType();
7263 bool IllegalFPCMov = false;
7264 if (VT.isFloatingPoint() && !VT.isVector() &&
7265 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7266 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7268 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7269 Opc == X86ISD::BT) { // FIXME
7276 // Look pass the truncate.
7277 if (Cond.getOpcode() == ISD::TRUNCATE)
7278 Cond = Cond.getOperand(0);
7280 // We know the result of AND is compared against zero. Try to match
7282 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7283 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7284 if (NewSetCC.getNode()) {
7285 CC = NewSetCC.getOperand(0);
7286 Cond = NewSetCC.getOperand(1);
7293 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7294 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7297 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7298 // condition is true.
7299 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
7300 SDValue Ops[] = { Op2, Op1, CC, Cond };
7301 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
7304 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7305 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7306 // from the AND / OR.
7307 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7308 Opc = Op.getOpcode();
7309 if (Opc != ISD::OR && Opc != ISD::AND)
7311 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7312 Op.getOperand(0).hasOneUse() &&
7313 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7314 Op.getOperand(1).hasOneUse());
7317 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7318 // 1 and that the SETCC node has a single use.
7319 static bool isXor1OfSetCC(SDValue Op) {
7320 if (Op.getOpcode() != ISD::XOR)
7322 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7323 if (N1C && N1C->getAPIntValue() == 1) {
7324 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7325 Op.getOperand(0).hasOneUse();
7330 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7331 bool addTest = true;
7332 SDValue Chain = Op.getOperand(0);
7333 SDValue Cond = Op.getOperand(1);
7334 SDValue Dest = Op.getOperand(2);
7335 DebugLoc dl = Op.getDebugLoc();
7338 if (Cond.getOpcode() == ISD::SETCC) {
7339 SDValue NewCond = LowerSETCC(Cond, DAG);
7340 if (NewCond.getNode())
7344 // FIXME: LowerXALUO doesn't handle these!!
7345 else if (Cond.getOpcode() == X86ISD::ADD ||
7346 Cond.getOpcode() == X86ISD::SUB ||
7347 Cond.getOpcode() == X86ISD::SMUL ||
7348 Cond.getOpcode() == X86ISD::UMUL)
7349 Cond = LowerXALUO(Cond, DAG);
7352 // Look pass (and (setcc_carry (cmp ...)), 1).
7353 if (Cond.getOpcode() == ISD::AND &&
7354 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7355 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7356 if (C && C->getAPIntValue() == 1)
7357 Cond = Cond.getOperand(0);
7360 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7361 // setting operand in place of the X86ISD::SETCC.
7362 if (Cond.getOpcode() == X86ISD::SETCC ||
7363 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7364 CC = Cond.getOperand(0);
7366 SDValue Cmp = Cond.getOperand(1);
7367 unsigned Opc = Cmp.getOpcode();
7368 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7369 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7373 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7377 // These can only come from an arithmetic instruction with overflow,
7378 // e.g. SADDO, UADDO.
7379 Cond = Cond.getNode()->getOperand(1);
7386 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7387 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7388 if (CondOpc == ISD::OR) {
7389 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7390 // two branches instead of an explicit OR instruction with a
7392 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7393 isX86LogicalCmp(Cmp)) {
7394 CC = Cond.getOperand(0).getOperand(0);
7395 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7396 Chain, Dest, CC, Cmp);
7397 CC = Cond.getOperand(1).getOperand(0);
7401 } else { // ISD::AND
7402 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7403 // two branches instead of an explicit AND instruction with a
7404 // separate test. However, we only do this if this block doesn't
7405 // have a fall-through edge, because this requires an explicit
7406 // jmp when the condition is false.
7407 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7408 isX86LogicalCmp(Cmp) &&
7409 Op.getNode()->hasOneUse()) {
7410 X86::CondCode CCode =
7411 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7412 CCode = X86::GetOppositeBranchCondition(CCode);
7413 CC = DAG.getConstant(CCode, MVT::i8);
7414 SDNode *User = *Op.getNode()->use_begin();
7415 // Look for an unconditional branch following this conditional branch.
7416 // We need this because we need to reverse the successors in order
7417 // to implement FCMP_OEQ.
7418 if (User->getOpcode() == ISD::BR) {
7419 SDValue FalseBB = User->getOperand(1);
7421 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7422 assert(NewBR == User);
7426 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7427 Chain, Dest, CC, Cmp);
7428 X86::CondCode CCode =
7429 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7430 CCode = X86::GetOppositeBranchCondition(CCode);
7431 CC = DAG.getConstant(CCode, MVT::i8);
7437 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7438 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7439 // It should be transformed during dag combiner except when the condition
7440 // is set by a arithmetics with overflow node.
7441 X86::CondCode CCode =
7442 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7443 CCode = X86::GetOppositeBranchCondition(CCode);
7444 CC = DAG.getConstant(CCode, MVT::i8);
7445 Cond = Cond.getOperand(0).getOperand(1);
7451 // Look pass the truncate.
7452 if (Cond.getOpcode() == ISD::TRUNCATE)
7453 Cond = Cond.getOperand(0);
7455 // We know the result of AND is compared against zero. Try to match
7457 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7458 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7459 if (NewSetCC.getNode()) {
7460 CC = NewSetCC.getOperand(0);
7461 Cond = NewSetCC.getOperand(1);
7468 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7469 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7471 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7472 Chain, Dest, CC, Cond);
7476 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7477 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7478 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7479 // that the guard pages used by the OS virtual memory manager are allocated in
7480 // correct sequence.
7482 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7483 SelectionDAG &DAG) const {
7484 assert(Subtarget->isTargetCygMing() &&
7485 "This should be used only on Cygwin/Mingw targets");
7486 DebugLoc dl = Op.getDebugLoc();
7489 SDValue Chain = Op.getOperand(0);
7490 SDValue Size = Op.getOperand(1);
7491 // FIXME: Ensure alignment here
7495 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7497 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7498 Flag = Chain.getValue(1);
7500 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
7502 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
7503 Flag = Chain.getValue(1);
7505 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7507 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7508 return DAG.getMergeValues(Ops1, 2, dl);
7511 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7512 MachineFunction &MF = DAG.getMachineFunction();
7513 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7515 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7516 DebugLoc DL = Op.getDebugLoc();
7518 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
7519 // vastart just stores the address of the VarArgsFrameIndex slot into the
7520 // memory location argument.
7521 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7523 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7524 MachinePointerInfo(SV), false, false, 0);
7528 // gp_offset (0 - 6 * 8)
7529 // fp_offset (48 - 48 + 8 * 16)
7530 // overflow_arg_area (point to parameters coming in memory).
7532 SmallVector<SDValue, 8> MemOps;
7533 SDValue FIN = Op.getOperand(1);
7535 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7536 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7538 FIN, MachinePointerInfo(SV), false, false, 0);
7539 MemOps.push_back(Store);
7542 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7543 FIN, DAG.getIntPtrConstant(4));
7544 Store = DAG.getStore(Op.getOperand(0), DL,
7545 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7547 FIN, MachinePointerInfo(SV, 4), false, false, 0);
7548 MemOps.push_back(Store);
7550 // Store ptr to overflow_arg_area
7551 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7552 FIN, DAG.getIntPtrConstant(4));
7553 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7555 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
7556 MachinePointerInfo(SV, 8),
7558 MemOps.push_back(Store);
7560 // Store ptr to reg_save_area.
7561 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7562 FIN, DAG.getIntPtrConstant(8));
7563 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7565 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
7566 MachinePointerInfo(SV, 16), false, false, 0);
7567 MemOps.push_back(Store);
7568 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
7569 &MemOps[0], MemOps.size());
7572 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7573 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7574 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
7576 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
7580 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7581 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7582 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7583 SDValue Chain = Op.getOperand(0);
7584 SDValue DstPtr = Op.getOperand(1);
7585 SDValue SrcPtr = Op.getOperand(2);
7586 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7587 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7588 DebugLoc DL = Op.getDebugLoc();
7590 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
7591 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7593 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
7597 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7598 DebugLoc dl = Op.getDebugLoc();
7599 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7601 default: return SDValue(); // Don't custom lower most intrinsics.
7602 // Comparison intrinsics.
7603 case Intrinsic::x86_sse_comieq_ss:
7604 case Intrinsic::x86_sse_comilt_ss:
7605 case Intrinsic::x86_sse_comile_ss:
7606 case Intrinsic::x86_sse_comigt_ss:
7607 case Intrinsic::x86_sse_comige_ss:
7608 case Intrinsic::x86_sse_comineq_ss:
7609 case Intrinsic::x86_sse_ucomieq_ss:
7610 case Intrinsic::x86_sse_ucomilt_ss:
7611 case Intrinsic::x86_sse_ucomile_ss:
7612 case Intrinsic::x86_sse_ucomigt_ss:
7613 case Intrinsic::x86_sse_ucomige_ss:
7614 case Intrinsic::x86_sse_ucomineq_ss:
7615 case Intrinsic::x86_sse2_comieq_sd:
7616 case Intrinsic::x86_sse2_comilt_sd:
7617 case Intrinsic::x86_sse2_comile_sd:
7618 case Intrinsic::x86_sse2_comigt_sd:
7619 case Intrinsic::x86_sse2_comige_sd:
7620 case Intrinsic::x86_sse2_comineq_sd:
7621 case Intrinsic::x86_sse2_ucomieq_sd:
7622 case Intrinsic::x86_sse2_ucomilt_sd:
7623 case Intrinsic::x86_sse2_ucomile_sd:
7624 case Intrinsic::x86_sse2_ucomigt_sd:
7625 case Intrinsic::x86_sse2_ucomige_sd:
7626 case Intrinsic::x86_sse2_ucomineq_sd: {
7628 ISD::CondCode CC = ISD::SETCC_INVALID;
7631 case Intrinsic::x86_sse_comieq_ss:
7632 case Intrinsic::x86_sse2_comieq_sd:
7636 case Intrinsic::x86_sse_comilt_ss:
7637 case Intrinsic::x86_sse2_comilt_sd:
7641 case Intrinsic::x86_sse_comile_ss:
7642 case Intrinsic::x86_sse2_comile_sd:
7646 case Intrinsic::x86_sse_comigt_ss:
7647 case Intrinsic::x86_sse2_comigt_sd:
7651 case Intrinsic::x86_sse_comige_ss:
7652 case Intrinsic::x86_sse2_comige_sd:
7656 case Intrinsic::x86_sse_comineq_ss:
7657 case Intrinsic::x86_sse2_comineq_sd:
7661 case Intrinsic::x86_sse_ucomieq_ss:
7662 case Intrinsic::x86_sse2_ucomieq_sd:
7663 Opc = X86ISD::UCOMI;
7666 case Intrinsic::x86_sse_ucomilt_ss:
7667 case Intrinsic::x86_sse2_ucomilt_sd:
7668 Opc = X86ISD::UCOMI;
7671 case Intrinsic::x86_sse_ucomile_ss:
7672 case Intrinsic::x86_sse2_ucomile_sd:
7673 Opc = X86ISD::UCOMI;
7676 case Intrinsic::x86_sse_ucomigt_ss:
7677 case Intrinsic::x86_sse2_ucomigt_sd:
7678 Opc = X86ISD::UCOMI;
7681 case Intrinsic::x86_sse_ucomige_ss:
7682 case Intrinsic::x86_sse2_ucomige_sd:
7683 Opc = X86ISD::UCOMI;
7686 case Intrinsic::x86_sse_ucomineq_ss:
7687 case Intrinsic::x86_sse2_ucomineq_sd:
7688 Opc = X86ISD::UCOMI;
7693 SDValue LHS = Op.getOperand(1);
7694 SDValue RHS = Op.getOperand(2);
7695 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7696 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7697 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7698 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7699 DAG.getConstant(X86CC, MVT::i8), Cond);
7700 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7702 // ptest and testp intrinsics. The intrinsic these come from are designed to
7703 // return an integer value, not just an instruction so lower it to the ptest
7704 // or testp pattern and a setcc for the result.
7705 case Intrinsic::x86_sse41_ptestz:
7706 case Intrinsic::x86_sse41_ptestc:
7707 case Intrinsic::x86_sse41_ptestnzc:
7708 case Intrinsic::x86_avx_ptestz_256:
7709 case Intrinsic::x86_avx_ptestc_256:
7710 case Intrinsic::x86_avx_ptestnzc_256:
7711 case Intrinsic::x86_avx_vtestz_ps:
7712 case Intrinsic::x86_avx_vtestc_ps:
7713 case Intrinsic::x86_avx_vtestnzc_ps:
7714 case Intrinsic::x86_avx_vtestz_pd:
7715 case Intrinsic::x86_avx_vtestc_pd:
7716 case Intrinsic::x86_avx_vtestnzc_pd:
7717 case Intrinsic::x86_avx_vtestz_ps_256:
7718 case Intrinsic::x86_avx_vtestc_ps_256:
7719 case Intrinsic::x86_avx_vtestnzc_ps_256:
7720 case Intrinsic::x86_avx_vtestz_pd_256:
7721 case Intrinsic::x86_avx_vtestc_pd_256:
7722 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7723 bool IsTestPacked = false;
7726 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7727 case Intrinsic::x86_avx_vtestz_ps:
7728 case Intrinsic::x86_avx_vtestz_pd:
7729 case Intrinsic::x86_avx_vtestz_ps_256:
7730 case Intrinsic::x86_avx_vtestz_pd_256:
7731 IsTestPacked = true; // Fallthrough
7732 case Intrinsic::x86_sse41_ptestz:
7733 case Intrinsic::x86_avx_ptestz_256:
7735 X86CC = X86::COND_E;
7737 case Intrinsic::x86_avx_vtestc_ps:
7738 case Intrinsic::x86_avx_vtestc_pd:
7739 case Intrinsic::x86_avx_vtestc_ps_256:
7740 case Intrinsic::x86_avx_vtestc_pd_256:
7741 IsTestPacked = true; // Fallthrough
7742 case Intrinsic::x86_sse41_ptestc:
7743 case Intrinsic::x86_avx_ptestc_256:
7745 X86CC = X86::COND_B;
7747 case Intrinsic::x86_avx_vtestnzc_ps:
7748 case Intrinsic::x86_avx_vtestnzc_pd:
7749 case Intrinsic::x86_avx_vtestnzc_ps_256:
7750 case Intrinsic::x86_avx_vtestnzc_pd_256:
7751 IsTestPacked = true; // Fallthrough
7752 case Intrinsic::x86_sse41_ptestnzc:
7753 case Intrinsic::x86_avx_ptestnzc_256:
7755 X86CC = X86::COND_A;
7759 SDValue LHS = Op.getOperand(1);
7760 SDValue RHS = Op.getOperand(2);
7761 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7762 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7763 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7764 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7765 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7768 // Fix vector shift instructions where the last operand is a non-immediate
7770 case Intrinsic::x86_sse2_pslli_w:
7771 case Intrinsic::x86_sse2_pslli_d:
7772 case Intrinsic::x86_sse2_pslli_q:
7773 case Intrinsic::x86_sse2_psrli_w:
7774 case Intrinsic::x86_sse2_psrli_d:
7775 case Intrinsic::x86_sse2_psrli_q:
7776 case Intrinsic::x86_sse2_psrai_w:
7777 case Intrinsic::x86_sse2_psrai_d:
7778 case Intrinsic::x86_mmx_pslli_w:
7779 case Intrinsic::x86_mmx_pslli_d:
7780 case Intrinsic::x86_mmx_pslli_q:
7781 case Intrinsic::x86_mmx_psrli_w:
7782 case Intrinsic::x86_mmx_psrli_d:
7783 case Intrinsic::x86_mmx_psrli_q:
7784 case Intrinsic::x86_mmx_psrai_w:
7785 case Intrinsic::x86_mmx_psrai_d: {
7786 SDValue ShAmt = Op.getOperand(2);
7787 if (isa<ConstantSDNode>(ShAmt))
7790 unsigned NewIntNo = 0;
7791 EVT ShAmtVT = MVT::v4i32;
7793 case Intrinsic::x86_sse2_pslli_w:
7794 NewIntNo = Intrinsic::x86_sse2_psll_w;
7796 case Intrinsic::x86_sse2_pslli_d:
7797 NewIntNo = Intrinsic::x86_sse2_psll_d;
7799 case Intrinsic::x86_sse2_pslli_q:
7800 NewIntNo = Intrinsic::x86_sse2_psll_q;
7802 case Intrinsic::x86_sse2_psrli_w:
7803 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7805 case Intrinsic::x86_sse2_psrli_d:
7806 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7808 case Intrinsic::x86_sse2_psrli_q:
7809 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7811 case Intrinsic::x86_sse2_psrai_w:
7812 NewIntNo = Intrinsic::x86_sse2_psra_w;
7814 case Intrinsic::x86_sse2_psrai_d:
7815 NewIntNo = Intrinsic::x86_sse2_psra_d;
7818 ShAmtVT = MVT::v2i32;
7820 case Intrinsic::x86_mmx_pslli_w:
7821 NewIntNo = Intrinsic::x86_mmx_psll_w;
7823 case Intrinsic::x86_mmx_pslli_d:
7824 NewIntNo = Intrinsic::x86_mmx_psll_d;
7826 case Intrinsic::x86_mmx_pslli_q:
7827 NewIntNo = Intrinsic::x86_mmx_psll_q;
7829 case Intrinsic::x86_mmx_psrli_w:
7830 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7832 case Intrinsic::x86_mmx_psrli_d:
7833 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7835 case Intrinsic::x86_mmx_psrli_q:
7836 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7838 case Intrinsic::x86_mmx_psrai_w:
7839 NewIntNo = Intrinsic::x86_mmx_psra_w;
7841 case Intrinsic::x86_mmx_psrai_d:
7842 NewIntNo = Intrinsic::x86_mmx_psra_d;
7844 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7850 // The vector shift intrinsics with scalars uses 32b shift amounts but
7851 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7855 ShOps[1] = DAG.getConstant(0, MVT::i32);
7856 if (ShAmtVT == MVT::v4i32) {
7857 ShOps[2] = DAG.getUNDEF(MVT::i32);
7858 ShOps[3] = DAG.getUNDEF(MVT::i32);
7859 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7861 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7862 // FIXME this must be lowered to get rid of the invalid type.
7865 EVT VT = Op.getValueType();
7866 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7867 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7868 DAG.getConstant(NewIntNo, MVT::i32),
7869 Op.getOperand(1), ShAmt);
7874 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7875 SelectionDAG &DAG) const {
7876 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7877 MFI->setReturnAddressIsTaken(true);
7879 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7880 DebugLoc dl = Op.getDebugLoc();
7883 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7885 DAG.getConstant(TD->getPointerSize(),
7886 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7887 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7888 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7890 MachinePointerInfo(), false, false, 0);
7893 // Just load the return address.
7894 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7895 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7896 RetAddrFI, MachinePointerInfo(), false, false, 0);
7899 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7900 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7901 MFI->setFrameAddressIsTaken(true);
7903 EVT VT = Op.getValueType();
7904 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7905 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7906 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7907 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7909 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
7910 MachinePointerInfo(),
7915 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7916 SelectionDAG &DAG) const {
7917 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7920 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7921 MachineFunction &MF = DAG.getMachineFunction();
7922 SDValue Chain = Op.getOperand(0);
7923 SDValue Offset = Op.getOperand(1);
7924 SDValue Handler = Op.getOperand(2);
7925 DebugLoc dl = Op.getDebugLoc();
7927 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
7928 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7930 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7932 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
7933 DAG.getIntPtrConstant(TD->getPointerSize()));
7934 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7935 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
7937 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7938 MF.getRegInfo().addLiveOut(StoreAddrReg);
7940 return DAG.getNode(X86ISD::EH_RETURN, dl,
7942 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7945 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7946 SelectionDAG &DAG) const {
7947 SDValue Root = Op.getOperand(0);
7948 SDValue Trmp = Op.getOperand(1); // trampoline
7949 SDValue FPtr = Op.getOperand(2); // nested function
7950 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7951 DebugLoc dl = Op.getDebugLoc();
7953 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7955 if (Subtarget->is64Bit()) {
7956 SDValue OutChains[6];
7958 // Large code-model.
7959 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7960 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7962 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7963 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7965 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7967 // Load the pointer to the nested function into R11.
7968 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7969 SDValue Addr = Trmp;
7970 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7971 Addr, MachinePointerInfo(TrmpAddr),
7974 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7975 DAG.getConstant(2, MVT::i64));
7976 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
7977 MachinePointerInfo(TrmpAddr, 2),
7980 // Load the 'nest' parameter value into R10.
7981 // R10 is specified in X86CallingConv.td
7982 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
7983 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7984 DAG.getConstant(10, MVT::i64));
7985 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
7986 Addr, MachinePointerInfo(TrmpAddr, 10),
7989 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7990 DAG.getConstant(12, MVT::i64));
7991 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
7992 MachinePointerInfo(TrmpAddr, 12),
7995 // Jump to the nested function.
7996 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
7997 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
7998 DAG.getConstant(20, MVT::i64));
7999 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8000 Addr, MachinePointerInfo(TrmpAddr, 20),
8003 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8004 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8005 DAG.getConstant(22, MVT::i64));
8006 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8007 MachinePointerInfo(TrmpAddr, 22),
8011 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8012 return DAG.getMergeValues(Ops, 2, dl);
8014 const Function *Func =
8015 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8016 CallingConv::ID CC = Func->getCallingConv();
8021 llvm_unreachable("Unsupported calling convention");
8022 case CallingConv::C:
8023 case CallingConv::X86_StdCall: {
8024 // Pass 'nest' parameter in ECX.
8025 // Must be kept in sync with X86CallingConv.td
8028 // Check that ECX wasn't needed by an 'inreg' parameter.
8029 const FunctionType *FTy = Func->getFunctionType();
8030 const AttrListPtr &Attrs = Func->getAttributes();
8032 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8033 unsigned InRegCount = 0;
8036 for (FunctionType::param_iterator I = FTy->param_begin(),
8037 E = FTy->param_end(); I != E; ++I, ++Idx)
8038 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8039 // FIXME: should only count parameters that are lowered to integers.
8040 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8042 if (InRegCount > 2) {
8043 report_fatal_error("Nest register in use - reduce number of inreg"
8049 case CallingConv::X86_FastCall:
8050 case CallingConv::X86_ThisCall:
8051 case CallingConv::Fast:
8052 // Pass 'nest' parameter in EAX.
8053 // Must be kept in sync with X86CallingConv.td
8058 SDValue OutChains[4];
8061 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8062 DAG.getConstant(10, MVT::i32));
8063 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8065 // This is storing the opcode for MOV32ri.
8066 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8067 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8068 OutChains[0] = DAG.getStore(Root, dl,
8069 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8070 Trmp, MachinePointerInfo(TrmpAddr),
8073 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8074 DAG.getConstant(1, MVT::i32));
8075 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8076 MachinePointerInfo(TrmpAddr, 1),
8079 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8080 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8081 DAG.getConstant(5, MVT::i32));
8082 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8083 MachinePointerInfo(TrmpAddr, 5),
8086 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8087 DAG.getConstant(6, MVT::i32));
8088 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8089 MachinePointerInfo(TrmpAddr, 6),
8093 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8094 return DAG.getMergeValues(Ops, 2, dl);
8098 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8099 SelectionDAG &DAG) const {
8101 The rounding mode is in bits 11:10 of FPSR, and has the following
8108 FLT_ROUNDS, on the other hand, expects the following:
8115 To perform the conversion, we do:
8116 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8119 MachineFunction &MF = DAG.getMachineFunction();
8120 const TargetMachine &TM = MF.getTarget();
8121 const TargetFrameInfo &TFI = *TM.getFrameInfo();
8122 unsigned StackAlignment = TFI.getStackAlignment();
8123 EVT VT = Op.getValueType();
8124 DebugLoc DL = Op.getDebugLoc();
8126 // Save FP Control Word to stack slot
8127 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8128 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8131 MachineMemOperand *MMO =
8132 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8133 MachineMemOperand::MOStore, 2, 2);
8135 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8136 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8137 DAG.getVTList(MVT::Other),
8138 Ops, 2, MVT::i16, MMO);
8140 // Load FP Control Word from stack slot
8141 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8142 MachinePointerInfo(), false, false, 0);
8144 // Transform as necessary
8146 DAG.getNode(ISD::SRL, DL, MVT::i16,
8147 DAG.getNode(ISD::AND, DL, MVT::i16,
8148 CWD, DAG.getConstant(0x800, MVT::i16)),
8149 DAG.getConstant(11, MVT::i8));
8151 DAG.getNode(ISD::SRL, DL, MVT::i16,
8152 DAG.getNode(ISD::AND, DL, MVT::i16,
8153 CWD, DAG.getConstant(0x400, MVT::i16)),
8154 DAG.getConstant(9, MVT::i8));
8157 DAG.getNode(ISD::AND, DL, MVT::i16,
8158 DAG.getNode(ISD::ADD, DL, MVT::i16,
8159 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8160 DAG.getConstant(1, MVT::i16)),
8161 DAG.getConstant(3, MVT::i16));
8164 return DAG.getNode((VT.getSizeInBits() < 16 ?
8165 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8168 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8169 EVT VT = Op.getValueType();
8171 unsigned NumBits = VT.getSizeInBits();
8172 DebugLoc dl = Op.getDebugLoc();
8174 Op = Op.getOperand(0);
8175 if (VT == MVT::i8) {
8176 // Zero extend to i32 since there is not an i8 bsr.
8178 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8181 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8182 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8183 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8185 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8188 DAG.getConstant(NumBits+NumBits-1, OpVT),
8189 DAG.getConstant(X86::COND_E, MVT::i8),
8192 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8194 // Finally xor with NumBits-1.
8195 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8198 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8202 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8203 EVT VT = Op.getValueType();
8205 unsigned NumBits = VT.getSizeInBits();
8206 DebugLoc dl = Op.getDebugLoc();
8208 Op = Op.getOperand(0);
8209 if (VT == MVT::i8) {
8211 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8214 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8215 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8216 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8218 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8221 DAG.getConstant(NumBits, OpVT),
8222 DAG.getConstant(X86::COND_E, MVT::i8),
8225 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8228 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8232 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8233 EVT VT = Op.getValueType();
8234 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8235 DebugLoc dl = Op.getDebugLoc();
8237 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8238 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8239 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8240 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8241 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8243 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8244 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8245 // return AloBlo + AloBhi + AhiBlo;
8247 SDValue A = Op.getOperand(0);
8248 SDValue B = Op.getOperand(1);
8250 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8251 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8252 A, DAG.getConstant(32, MVT::i32));
8253 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8254 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8255 B, DAG.getConstant(32, MVT::i32));
8256 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8257 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8259 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8260 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8262 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8263 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8265 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8266 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8267 AloBhi, DAG.getConstant(32, MVT::i32));
8268 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8269 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8270 AhiBlo, DAG.getConstant(32, MVT::i32));
8271 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8272 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8276 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8277 EVT VT = Op.getValueType();
8278 DebugLoc dl = Op.getDebugLoc();
8279 SDValue R = Op.getOperand(0);
8281 LLVMContext *Context = DAG.getContext();
8283 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8285 if (VT == MVT::v4i32) {
8286 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8287 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8288 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8290 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8292 std::vector<Constant*> CV(4, CI);
8293 Constant *C = ConstantVector::get(CV);
8294 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8295 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8296 MachinePointerInfo::getConstantPool(),
8299 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8300 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op);
8301 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8302 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8304 if (VT == MVT::v16i8) {
8306 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8307 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8308 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8310 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8311 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8313 std::vector<Constant*> CVM1(16, CM1);
8314 std::vector<Constant*> CVM2(16, CM2);
8315 Constant *C = ConstantVector::get(CVM1);
8316 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8317 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8318 MachinePointerInfo::getConstantPool(),
8321 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8322 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8323 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8324 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8325 DAG.getConstant(4, MVT::i32));
8326 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8327 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8330 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8332 C = ConstantVector::get(CVM2);
8333 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8334 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8335 MachinePointerInfo::getConstantPool(),
8338 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8339 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8340 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8341 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8342 DAG.getConstant(2, MVT::i32));
8343 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8344 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8347 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8349 // return pblendv(r, r+r, a);
8350 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8351 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8352 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8358 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8359 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8360 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8361 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8362 // has only one use.
8363 SDNode *N = Op.getNode();
8364 SDValue LHS = N->getOperand(0);
8365 SDValue RHS = N->getOperand(1);
8366 unsigned BaseOp = 0;
8368 DebugLoc dl = Op.getDebugLoc();
8370 switch (Op.getOpcode()) {
8371 default: llvm_unreachable("Unknown ovf instruction!");
8373 // A subtract of one will be selected as a INC. Note that INC doesn't
8374 // set CF, so we can't do this for UADDO.
8375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8376 if (C->getAPIntValue() == 1) {
8377 BaseOp = X86ISD::INC;
8381 BaseOp = X86ISD::ADD;
8385 BaseOp = X86ISD::ADD;
8389 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8390 // set CF, so we can't do this for USUBO.
8391 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8392 if (C->getAPIntValue() == 1) {
8393 BaseOp = X86ISD::DEC;
8397 BaseOp = X86ISD::SUB;
8401 BaseOp = X86ISD::SUB;
8405 BaseOp = X86ISD::SMUL;
8409 BaseOp = X86ISD::UMUL;
8414 // Also sets EFLAGS.
8415 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8416 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
8419 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
8420 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
8422 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8426 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8427 DebugLoc dl = Op.getDebugLoc();
8429 if (!Subtarget->hasSSE2()) {
8430 SDValue Chain = Op.getOperand(0);
8431 SDValue Zero = DAG.getConstant(0,
8432 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8434 DAG.getRegister(X86::ESP, MVT::i32), // Base
8435 DAG.getTargetConstant(1, MVT::i8), // Scale
8436 DAG.getRegister(0, MVT::i32), // Index
8437 DAG.getTargetConstant(0, MVT::i32), // Disp
8438 DAG.getRegister(0, MVT::i32), // Segment.
8443 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8444 array_lengthof(Ops));
8445 return SDValue(Res, 0);
8448 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8450 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8452 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8453 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8454 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8455 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8457 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8458 if (!Op1 && !Op2 && !Op3 && Op4)
8459 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8461 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8462 if (Op1 && !Op2 && !Op3 && !Op4)
8463 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8465 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8467 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8470 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8471 EVT T = Op.getValueType();
8472 DebugLoc DL = Op.getDebugLoc();
8475 switch(T.getSimpleVT().SimpleTy) {
8477 assert(false && "Invalid value type!");
8478 case MVT::i8: Reg = X86::AL; size = 1; break;
8479 case MVT::i16: Reg = X86::AX; size = 2; break;
8480 case MVT::i32: Reg = X86::EAX; size = 4; break;
8482 assert(Subtarget->is64Bit() && "Node not type legal!");
8483 Reg = X86::RAX; size = 8;
8486 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
8487 Op.getOperand(2), SDValue());
8488 SDValue Ops[] = { cpIn.getValue(0),
8491 DAG.getTargetConstant(size, MVT::i8),
8493 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8494 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
8495 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
8498 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
8502 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8503 SelectionDAG &DAG) const {
8504 assert(Subtarget->is64Bit() && "Result not type legalized?");
8505 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8506 SDValue TheChain = Op.getOperand(0);
8507 DebugLoc dl = Op.getDebugLoc();
8508 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8509 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8510 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8512 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8513 DAG.getConstant(32, MVT::i8));
8515 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8518 return DAG.getMergeValues(Ops, 2, dl);
8521 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
8522 SelectionDAG &DAG) const {
8523 EVT SrcVT = Op.getOperand(0).getValueType();
8524 EVT DstVT = Op.getValueType();
8525 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8526 Subtarget->hasMMX() && !DisableMMX) &&
8527 "Unexpected custom BIT_CONVERT");
8528 assert((DstVT == MVT::i64 ||
8529 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8530 "Unexpected custom BIT_CONVERT");
8531 // i64 <=> MMX conversions are Legal.
8532 if (SrcVT==MVT::i64 && DstVT.isVector())
8534 if (DstVT==MVT::i64 && SrcVT.isVector())
8536 // MMX <=> MMX conversions are Legal.
8537 if (SrcVT.isVector() && DstVT.isVector())
8539 // All other conversions need to be expanded.
8542 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8543 SDNode *Node = Op.getNode();
8544 DebugLoc dl = Node->getDebugLoc();
8545 EVT T = Node->getValueType(0);
8546 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8547 DAG.getConstant(0, T), Node->getOperand(2));
8548 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8549 cast<AtomicSDNode>(Node)->getMemoryVT(),
8550 Node->getOperand(0),
8551 Node->getOperand(1), negOp,
8552 cast<AtomicSDNode>(Node)->getSrcValue(),
8553 cast<AtomicSDNode>(Node)->getAlignment());
8556 /// LowerOperation - Provide custom lowering hooks for some operations.
8558 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8559 switch (Op.getOpcode()) {
8560 default: llvm_unreachable("Should not custom lower this!");
8561 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8562 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8563 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8564 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8565 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8566 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8567 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8568 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8569 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8570 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8571 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8572 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8573 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8574 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8575 case ISD::SHL_PARTS:
8576 case ISD::SRA_PARTS:
8577 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8578 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8579 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8580 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8581 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8582 case ISD::FABS: return LowerFABS(Op, DAG);
8583 case ISD::FNEG: return LowerFNEG(Op, DAG);
8584 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8585 case ISD::SETCC: return LowerSETCC(Op, DAG);
8586 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8587 case ISD::SELECT: return LowerSELECT(Op, DAG);
8588 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8589 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8590 case ISD::VASTART: return LowerVASTART(Op, DAG);
8591 case ISD::VAARG: return LowerVAARG(Op, DAG);
8592 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8593 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8594 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8595 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8596 case ISD::FRAME_TO_ARGS_OFFSET:
8597 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8598 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8599 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8600 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8601 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8602 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8603 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8604 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8605 case ISD::SHL: return LowerSHL(Op, DAG);
8611 case ISD::UMULO: return LowerXALUO(Op, DAG);
8612 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8613 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
8617 void X86TargetLowering::
8618 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8619 SelectionDAG &DAG, unsigned NewOp) const {
8620 EVT T = Node->getValueType(0);
8621 DebugLoc dl = Node->getDebugLoc();
8622 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8624 SDValue Chain = Node->getOperand(0);
8625 SDValue In1 = Node->getOperand(1);
8626 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8627 Node->getOperand(2), DAG.getIntPtrConstant(0));
8628 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8629 Node->getOperand(2), DAG.getIntPtrConstant(1));
8630 SDValue Ops[] = { Chain, In1, In2L, In2H };
8631 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8633 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8634 cast<MemSDNode>(Node)->getMemOperand());
8635 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8636 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8637 Results.push_back(Result.getValue(2));
8640 /// ReplaceNodeResults - Replace a node with an illegal result type
8641 /// with a new node built out of custom code.
8642 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8643 SmallVectorImpl<SDValue>&Results,
8644 SelectionDAG &DAG) const {
8645 DebugLoc dl = N->getDebugLoc();
8646 switch (N->getOpcode()) {
8648 assert(false && "Do not know how to custom type legalize this operation!");
8650 case ISD::FP_TO_SINT: {
8651 std::pair<SDValue,SDValue> Vals =
8652 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8653 SDValue FIST = Vals.first, StackSlot = Vals.second;
8654 if (FIST.getNode() != 0) {
8655 EVT VT = N->getValueType(0);
8656 // Return a load from the stack slot.
8657 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
8658 MachinePointerInfo(), false, false, 0));
8662 case ISD::READCYCLECOUNTER: {
8663 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8664 SDValue TheChain = N->getOperand(0);
8665 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8666 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8668 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8670 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8671 SDValue Ops[] = { eax, edx };
8672 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8673 Results.push_back(edx.getValue(1));
8676 case ISD::ATOMIC_CMP_SWAP: {
8677 EVT T = N->getValueType(0);
8678 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8679 SDValue cpInL, cpInH;
8680 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8681 DAG.getConstant(0, MVT::i32));
8682 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8683 DAG.getConstant(1, MVT::i32));
8684 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8685 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8687 SDValue swapInL, swapInH;
8688 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8689 DAG.getConstant(0, MVT::i32));
8690 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8691 DAG.getConstant(1, MVT::i32));
8692 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8694 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8695 swapInL.getValue(1));
8696 SDValue Ops[] = { swapInH.getValue(0),
8698 swapInH.getValue(1) };
8699 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8700 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
8701 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
8703 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8704 MVT::i32, Result.getValue(1));
8705 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8706 MVT::i32, cpOutL.getValue(2));
8707 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8708 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8709 Results.push_back(cpOutH.getValue(1));
8712 case ISD::ATOMIC_LOAD_ADD:
8713 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8715 case ISD::ATOMIC_LOAD_AND:
8716 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8718 case ISD::ATOMIC_LOAD_NAND:
8719 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8721 case ISD::ATOMIC_LOAD_OR:
8722 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8724 case ISD::ATOMIC_LOAD_SUB:
8725 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8727 case ISD::ATOMIC_LOAD_XOR:
8728 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8730 case ISD::ATOMIC_SWAP:
8731 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8736 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8738 default: return NULL;
8739 case X86ISD::BSF: return "X86ISD::BSF";
8740 case X86ISD::BSR: return "X86ISD::BSR";
8741 case X86ISD::SHLD: return "X86ISD::SHLD";
8742 case X86ISD::SHRD: return "X86ISD::SHRD";
8743 case X86ISD::FAND: return "X86ISD::FAND";
8744 case X86ISD::FOR: return "X86ISD::FOR";
8745 case X86ISD::FXOR: return "X86ISD::FXOR";
8746 case X86ISD::FSRL: return "X86ISD::FSRL";
8747 case X86ISD::FILD: return "X86ISD::FILD";
8748 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8749 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8750 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8751 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8752 case X86ISD::FLD: return "X86ISD::FLD";
8753 case X86ISD::FST: return "X86ISD::FST";
8754 case X86ISD::CALL: return "X86ISD::CALL";
8755 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8756 case X86ISD::BT: return "X86ISD::BT";
8757 case X86ISD::CMP: return "X86ISD::CMP";
8758 case X86ISD::COMI: return "X86ISD::COMI";
8759 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8760 case X86ISD::SETCC: return "X86ISD::SETCC";
8761 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8762 case X86ISD::CMOV: return "X86ISD::CMOV";
8763 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8764 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8765 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8766 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8767 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8768 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8769 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8770 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8771 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8772 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8773 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8774 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8775 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8776 case X86ISD::FMAX: return "X86ISD::FMAX";
8777 case X86ISD::FMIN: return "X86ISD::FMIN";
8778 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8779 case X86ISD::FRCP: return "X86ISD::FRCP";
8780 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8781 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8782 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8783 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8784 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8785 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8786 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8787 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8788 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8789 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8790 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8791 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8792 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8793 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8794 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8795 case X86ISD::VSHL: return "X86ISD::VSHL";
8796 case X86ISD::VSRL: return "X86ISD::VSRL";
8797 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8798 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8799 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8800 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8801 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8802 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8803 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8804 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8805 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8806 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8807 case X86ISD::ADD: return "X86ISD::ADD";
8808 case X86ISD::SUB: return "X86ISD::SUB";
8809 case X86ISD::SMUL: return "X86ISD::SMUL";
8810 case X86ISD::UMUL: return "X86ISD::UMUL";
8811 case X86ISD::INC: return "X86ISD::INC";
8812 case X86ISD::DEC: return "X86ISD::DEC";
8813 case X86ISD::OR: return "X86ISD::OR";
8814 case X86ISD::XOR: return "X86ISD::XOR";
8815 case X86ISD::AND: return "X86ISD::AND";
8816 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8817 case X86ISD::PTEST: return "X86ISD::PTEST";
8818 case X86ISD::TESTP: return "X86ISD::TESTP";
8819 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8820 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8821 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8822 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8823 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8824 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8825 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8826 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8827 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8828 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8829 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8830 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8831 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8832 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8833 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8834 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8835 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8836 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8837 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8838 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8839 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8840 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8841 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8842 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8843 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8844 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8845 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8846 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8847 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8848 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8849 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8850 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8851 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8852 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8853 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
8857 // isLegalAddressingMode - Return true if the addressing mode represented
8858 // by AM is legal for this target, for a load/store of the specified type.
8859 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
8860 const Type *Ty) const {
8861 // X86 supports extremely general addressing modes.
8862 CodeModel::Model M = getTargetMachine().getCodeModel();
8863 Reloc::Model R = getTargetMachine().getRelocationModel();
8865 // X86 allows a sign-extended 32-bit immediate field as a displacement.
8866 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
8871 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
8873 // If a reference to this global requires an extra load, we can't fold it.
8874 if (isGlobalStubReference(GVFlags))
8877 // If BaseGV requires a register for the PIC base, we cannot also have a
8878 // BaseReg specified.
8879 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
8882 // If lower 4G is not available, then we must use rip-relative addressing.
8883 if ((M != CodeModel::Small || R != Reloc::Static) &&
8884 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
8894 // These scales always work.
8899 // These scales are formed with basereg+scalereg. Only accept if there is
8904 default: // Other stuff never works.
8912 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
8913 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8915 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8916 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8917 if (NumBits1 <= NumBits2)
8922 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8923 if (!VT1.isInteger() || !VT2.isInteger())
8925 unsigned NumBits1 = VT1.getSizeInBits();
8926 unsigned NumBits2 = VT2.getSizeInBits();
8927 if (NumBits1 <= NumBits2)
8932 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
8933 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8934 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
8937 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
8938 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8939 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
8942 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
8943 // i16 instructions are longer (0x66 prefix) and potentially slower.
8944 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
8947 /// isShuffleMaskLegal - Targets can use this to indicate that they only
8948 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
8949 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
8950 /// are assumed to be legal.
8952 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
8954 // Very little shuffling can be done for 64-bit vectors right now.
8955 if (VT.getSizeInBits() == 64)
8956 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
8958 // FIXME: pshufb, blends, shifts.
8959 return (VT.getVectorNumElements() == 2 ||
8960 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
8961 isMOVLMask(M, VT) ||
8962 isSHUFPMask(M, VT) ||
8963 isPSHUFDMask(M, VT) ||
8964 isPSHUFHWMask(M, VT) ||
8965 isPSHUFLWMask(M, VT) ||
8966 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
8967 isUNPCKLMask(M, VT) ||
8968 isUNPCKHMask(M, VT) ||
8969 isUNPCKL_v_undef_Mask(M, VT) ||
8970 isUNPCKH_v_undef_Mask(M, VT));
8974 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
8976 unsigned NumElts = VT.getVectorNumElements();
8977 // FIXME: This collection of masks seems suspect.
8980 if (NumElts == 4 && VT.getSizeInBits() == 128) {
8981 return (isMOVLMask(Mask, VT) ||
8982 isCommutedMOVLMask(Mask, VT, true) ||
8983 isSHUFPMask(Mask, VT) ||
8984 isCommutedSHUFPMask(Mask, VT));
8989 //===----------------------------------------------------------------------===//
8990 // X86 Scheduler Hooks
8991 //===----------------------------------------------------------------------===//
8993 // private utility function
8995 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
8996 MachineBasicBlock *MBB,
9003 TargetRegisterClass *RC,
9004 bool invSrc) const {
9005 // For the atomic bitwise operator, we generate
9008 // ld t1 = [bitinstr.addr]
9009 // op t2 = t1, [bitinstr.val]
9011 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9013 // fallthrough -->nextMBB
9014 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9015 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9016 MachineFunction::iterator MBBIter = MBB;
9019 /// First build the CFG
9020 MachineFunction *F = MBB->getParent();
9021 MachineBasicBlock *thisMBB = MBB;
9022 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9023 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9024 F->insert(MBBIter, newMBB);
9025 F->insert(MBBIter, nextMBB);
9027 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9028 nextMBB->splice(nextMBB->begin(), thisMBB,
9029 llvm::next(MachineBasicBlock::iterator(bInstr)),
9031 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9033 // Update thisMBB to fall through to newMBB
9034 thisMBB->addSuccessor(newMBB);
9036 // newMBB jumps to itself and fall through to nextMBB
9037 newMBB->addSuccessor(nextMBB);
9038 newMBB->addSuccessor(newMBB);
9040 // Insert instructions into newMBB based on incoming instruction
9041 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9042 "unexpected number of operands");
9043 DebugLoc dl = bInstr->getDebugLoc();
9044 MachineOperand& destOper = bInstr->getOperand(0);
9045 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9046 int numArgs = bInstr->getNumOperands() - 1;
9047 for (int i=0; i < numArgs; ++i)
9048 argOpers[i] = &bInstr->getOperand(i+1);
9050 // x86 address has 4 operands: base, index, scale, and displacement
9051 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9052 int valArgIndx = lastAddrIndx + 1;
9054 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9055 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9056 for (int i=0; i <= lastAddrIndx; ++i)
9057 (*MIB).addOperand(*argOpers[i]);
9059 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9061 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9066 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9067 assert((argOpers[valArgIndx]->isReg() ||
9068 argOpers[valArgIndx]->isImm()) &&
9070 if (argOpers[valArgIndx]->isReg())
9071 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9073 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9075 (*MIB).addOperand(*argOpers[valArgIndx]);
9077 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9080 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9081 for (int i=0; i <= lastAddrIndx; ++i)
9082 (*MIB).addOperand(*argOpers[i]);
9084 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9085 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9086 bInstr->memoperands_end());
9088 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9092 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9094 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9098 // private utility function: 64 bit atomics on 32 bit host.
9100 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9101 MachineBasicBlock *MBB,
9106 bool invSrc) const {
9107 // For the atomic bitwise operator, we generate
9108 // thisMBB (instructions are in pairs, except cmpxchg8b)
9109 // ld t1,t2 = [bitinstr.addr]
9111 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9112 // op t5, t6 <- out1, out2, [bitinstr.val]
9113 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9114 // mov ECX, EBX <- t5, t6
9115 // mov EAX, EDX <- t1, t2
9116 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9117 // mov t3, t4 <- EAX, EDX
9119 // result in out1, out2
9120 // fallthrough -->nextMBB
9122 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9123 const unsigned LoadOpc = X86::MOV32rm;
9124 const unsigned NotOpc = X86::NOT32r;
9125 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9126 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9127 MachineFunction::iterator MBBIter = MBB;
9130 /// First build the CFG
9131 MachineFunction *F = MBB->getParent();
9132 MachineBasicBlock *thisMBB = MBB;
9133 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9134 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9135 F->insert(MBBIter, newMBB);
9136 F->insert(MBBIter, nextMBB);
9138 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9139 nextMBB->splice(nextMBB->begin(), thisMBB,
9140 llvm::next(MachineBasicBlock::iterator(bInstr)),
9142 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9144 // Update thisMBB to fall through to newMBB
9145 thisMBB->addSuccessor(newMBB);
9147 // newMBB jumps to itself and fall through to nextMBB
9148 newMBB->addSuccessor(nextMBB);
9149 newMBB->addSuccessor(newMBB);
9151 DebugLoc dl = bInstr->getDebugLoc();
9152 // Insert instructions into newMBB based on incoming instruction
9153 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9154 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9155 "unexpected number of operands");
9156 MachineOperand& dest1Oper = bInstr->getOperand(0);
9157 MachineOperand& dest2Oper = bInstr->getOperand(1);
9158 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9159 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9160 argOpers[i] = &bInstr->getOperand(i+2);
9162 // We use some of the operands multiple times, so conservatively just
9163 // clear any kill flags that might be present.
9164 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9165 argOpers[i]->setIsKill(false);
9168 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9169 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9171 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9172 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9173 for (int i=0; i <= lastAddrIndx; ++i)
9174 (*MIB).addOperand(*argOpers[i]);
9175 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9176 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9177 // add 4 to displacement.
9178 for (int i=0; i <= lastAddrIndx-2; ++i)
9179 (*MIB).addOperand(*argOpers[i]);
9180 MachineOperand newOp3 = *(argOpers[3]);
9182 newOp3.setImm(newOp3.getImm()+4);
9184 newOp3.setOffset(newOp3.getOffset()+4);
9185 (*MIB).addOperand(newOp3);
9186 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9188 // t3/4 are defined later, at the bottom of the loop
9189 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9190 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9191 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9192 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9193 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9194 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9196 // The subsequent operations should be using the destination registers of
9197 //the PHI instructions.
9199 t1 = F->getRegInfo().createVirtualRegister(RC);
9200 t2 = F->getRegInfo().createVirtualRegister(RC);
9201 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9202 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9204 t1 = dest1Oper.getReg();
9205 t2 = dest2Oper.getReg();
9208 int valArgIndx = lastAddrIndx + 1;
9209 assert((argOpers[valArgIndx]->isReg() ||
9210 argOpers[valArgIndx]->isImm()) &&
9212 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9213 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9214 if (argOpers[valArgIndx]->isReg())
9215 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9217 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9218 if (regOpcL != X86::MOV32rr)
9220 (*MIB).addOperand(*argOpers[valArgIndx]);
9221 assert(argOpers[valArgIndx + 1]->isReg() ==
9222 argOpers[valArgIndx]->isReg());
9223 assert(argOpers[valArgIndx + 1]->isImm() ==
9224 argOpers[valArgIndx]->isImm());
9225 if (argOpers[valArgIndx + 1]->isReg())
9226 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9228 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9229 if (regOpcH != X86::MOV32rr)
9231 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9233 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9235 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9238 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9240 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9243 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9244 for (int i=0; i <= lastAddrIndx; ++i)
9245 (*MIB).addOperand(*argOpers[i]);
9247 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9248 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9249 bInstr->memoperands_end());
9251 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9252 MIB.addReg(X86::EAX);
9253 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9254 MIB.addReg(X86::EDX);
9257 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9259 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9263 // private utility function
9265 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9266 MachineBasicBlock *MBB,
9267 unsigned cmovOpc) const {
9268 // For the atomic min/max operator, we generate
9271 // ld t1 = [min/max.addr]
9272 // mov t2 = [min/max.val]
9274 // cmov[cond] t2 = t1
9276 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9278 // fallthrough -->nextMBB
9280 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9281 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9282 MachineFunction::iterator MBBIter = MBB;
9285 /// First build the CFG
9286 MachineFunction *F = MBB->getParent();
9287 MachineBasicBlock *thisMBB = MBB;
9288 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9289 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9290 F->insert(MBBIter, newMBB);
9291 F->insert(MBBIter, nextMBB);
9293 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9294 nextMBB->splice(nextMBB->begin(), thisMBB,
9295 llvm::next(MachineBasicBlock::iterator(mInstr)),
9297 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9299 // Update thisMBB to fall through to newMBB
9300 thisMBB->addSuccessor(newMBB);
9302 // newMBB jumps to newMBB and fall through to nextMBB
9303 newMBB->addSuccessor(nextMBB);
9304 newMBB->addSuccessor(newMBB);
9306 DebugLoc dl = mInstr->getDebugLoc();
9307 // Insert instructions into newMBB based on incoming instruction
9308 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9309 "unexpected number of operands");
9310 MachineOperand& destOper = mInstr->getOperand(0);
9311 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9312 int numArgs = mInstr->getNumOperands() - 1;
9313 for (int i=0; i < numArgs; ++i)
9314 argOpers[i] = &mInstr->getOperand(i+1);
9316 // x86 address has 4 operands: base, index, scale, and displacement
9317 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9318 int valArgIndx = lastAddrIndx + 1;
9320 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9321 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9322 for (int i=0; i <= lastAddrIndx; ++i)
9323 (*MIB).addOperand(*argOpers[i]);
9325 // We only support register and immediate values
9326 assert((argOpers[valArgIndx]->isReg() ||
9327 argOpers[valArgIndx]->isImm()) &&
9330 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9331 if (argOpers[valArgIndx]->isReg())
9332 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9334 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9335 (*MIB).addOperand(*argOpers[valArgIndx]);
9337 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9340 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9345 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9346 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9350 // Cmp and exchange if none has modified the memory location
9351 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9352 for (int i=0; i <= lastAddrIndx; ++i)
9353 (*MIB).addOperand(*argOpers[i]);
9355 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9356 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9357 mInstr->memoperands_end());
9359 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9360 MIB.addReg(X86::EAX);
9363 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9365 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9369 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9370 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9373 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9374 unsigned numArgs, bool memArg) const {
9376 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9377 "Target must have SSE4.2 or AVX features enabled");
9379 DebugLoc dl = MI->getDebugLoc();
9380 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9384 if (!Subtarget->hasAVX()) {
9386 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9388 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9391 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9393 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9396 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
9398 for (unsigned i = 0; i < numArgs; ++i) {
9399 MachineOperand &Op = MI->getOperand(i+1);
9401 if (!(Op.isReg() && Op.isImplicit()))
9405 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9408 MI->eraseFromParent();
9414 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9416 MachineBasicBlock *MBB) const {
9417 // Emit code to save XMM registers to the stack. The ABI says that the
9418 // number of registers to save is given in %al, so it's theoretically
9419 // possible to do an indirect jump trick to avoid saving all of them,
9420 // however this code takes a simpler approach and just executes all
9421 // of the stores if %al is non-zero. It's less code, and it's probably
9422 // easier on the hardware branch predictor, and stores aren't all that
9423 // expensive anyway.
9425 // Create the new basic blocks. One block contains all the XMM stores,
9426 // and one block is the final destination regardless of whether any
9427 // stores were performed.
9428 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9429 MachineFunction *F = MBB->getParent();
9430 MachineFunction::iterator MBBIter = MBB;
9432 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9433 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9434 F->insert(MBBIter, XMMSaveMBB);
9435 F->insert(MBBIter, EndMBB);
9437 // Transfer the remainder of MBB and its successor edges to EndMBB.
9438 EndMBB->splice(EndMBB->begin(), MBB,
9439 llvm::next(MachineBasicBlock::iterator(MI)),
9441 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9443 // The original block will now fall through to the XMM save block.
9444 MBB->addSuccessor(XMMSaveMBB);
9445 // The XMMSaveMBB will fall through to the end block.
9446 XMMSaveMBB->addSuccessor(EndMBB);
9448 // Now add the instructions.
9449 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9450 DebugLoc DL = MI->getDebugLoc();
9452 unsigned CountReg = MI->getOperand(0).getReg();
9453 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9454 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9456 if (!Subtarget->isTargetWin64()) {
9457 // If %al is 0, branch around the XMM save block.
9458 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9459 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9460 MBB->addSuccessor(EndMBB);
9463 // In the XMM save block, save all the XMM argument registers.
9464 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9465 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9466 MachineMemOperand *MMO =
9467 F->getMachineMemOperand(
9468 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
9469 MachineMemOperand::MOStore,
9470 /*Size=*/16, /*Align=*/16);
9471 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9472 .addFrameIndex(RegSaveFrameIndex)
9473 .addImm(/*Scale=*/1)
9474 .addReg(/*IndexReg=*/0)
9475 .addImm(/*Disp=*/Offset)
9476 .addReg(/*Segment=*/0)
9477 .addReg(MI->getOperand(i).getReg())
9478 .addMemOperand(MMO);
9481 MI->eraseFromParent(); // The pseudo instruction is gone now.
9487 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9488 MachineBasicBlock *BB) const {
9489 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9490 DebugLoc DL = MI->getDebugLoc();
9492 // To "insert" a SELECT_CC instruction, we actually have to insert the
9493 // diamond control-flow pattern. The incoming instruction knows the
9494 // destination vreg to set, the condition code register to branch on, the
9495 // true/false values to select between, and a branch opcode to use.
9496 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9497 MachineFunction::iterator It = BB;
9503 // cmpTY ccX, r1, r2
9505 // fallthrough --> copy0MBB
9506 MachineBasicBlock *thisMBB = BB;
9507 MachineFunction *F = BB->getParent();
9508 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9509 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9510 F->insert(It, copy0MBB);
9511 F->insert(It, sinkMBB);
9513 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9514 // live into the sink and copy blocks.
9515 const MachineFunction *MF = BB->getParent();
9516 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9517 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9519 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9520 const MachineOperand &MO = MI->getOperand(I);
9521 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9522 unsigned Reg = MO.getReg();
9523 if (Reg != X86::EFLAGS) continue;
9524 copy0MBB->addLiveIn(Reg);
9525 sinkMBB->addLiveIn(Reg);
9528 // Transfer the remainder of BB and its successor edges to sinkMBB.
9529 sinkMBB->splice(sinkMBB->begin(), BB,
9530 llvm::next(MachineBasicBlock::iterator(MI)),
9532 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9534 // Add the true and fallthrough blocks as its successors.
9535 BB->addSuccessor(copy0MBB);
9536 BB->addSuccessor(sinkMBB);
9538 // Create the conditional branch instruction.
9540 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9541 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9544 // %FalseValue = ...
9545 // # fallthrough to sinkMBB
9546 copy0MBB->addSuccessor(sinkMBB);
9549 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9551 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9552 TII->get(X86::PHI), MI->getOperand(0).getReg())
9553 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9554 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9556 MI->eraseFromParent(); // The pseudo instruction is gone now.
9561 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
9562 MachineBasicBlock *BB) const {
9563 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9564 DebugLoc DL = MI->getDebugLoc();
9566 // The lowering is pretty easy: we're just emitting the call to _alloca. The
9567 // non-trivial part is impdef of ESP.
9568 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
9571 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
9572 .addExternalSymbol("_alloca")
9573 .addReg(X86::EAX, RegState::Implicit)
9574 .addReg(X86::ESP, RegState::Implicit)
9575 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
9576 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
9577 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
9579 MI->eraseFromParent(); // The pseudo instruction is gone now.
9584 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
9585 MachineBasicBlock *BB) const {
9586 // This is pretty easy. We're taking the value that we received from
9587 // our load from the relocation, sticking it in either RDI (x86-64)
9588 // or EAX and doing an indirect call. The return value will then
9589 // be in the normal return register.
9590 const X86InstrInfo *TII
9591 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
9592 DebugLoc DL = MI->getDebugLoc();
9593 MachineFunction *F = BB->getParent();
9595 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
9596 assert(MI->getOperand(3).isGlobal() && "This should be a global");
9598 if (Subtarget->is64Bit()) {
9599 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9600 TII->get(X86::MOV64rm), X86::RDI)
9602 .addImm(0).addReg(0)
9603 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9604 MI->getOperand(3).getTargetFlags())
9606 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
9607 addDirectMem(MIB, X86::RDI);
9608 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
9609 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9610 TII->get(X86::MOV32rm), X86::EAX)
9612 .addImm(0).addReg(0)
9613 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9614 MI->getOperand(3).getTargetFlags())
9616 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9617 addDirectMem(MIB, X86::EAX);
9619 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9620 TII->get(X86::MOV32rm), X86::EAX)
9621 .addReg(TII->getGlobalBaseReg(F))
9622 .addImm(0).addReg(0)
9623 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9624 MI->getOperand(3).getTargetFlags())
9626 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9627 addDirectMem(MIB, X86::EAX);
9630 MI->eraseFromParent(); // The pseudo instruction is gone now.
9635 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
9636 MachineBasicBlock *BB) const {
9637 switch (MI->getOpcode()) {
9638 default: assert(false && "Unexpected instr type to insert");
9639 case X86::MINGW_ALLOCA:
9640 return EmitLoweredMingwAlloca(MI, BB);
9641 case X86::TLSCall_32:
9642 case X86::TLSCall_64:
9643 return EmitLoweredTLSCall(MI, BB);
9645 case X86::CMOV_FR32:
9646 case X86::CMOV_FR64:
9647 case X86::CMOV_V4F32:
9648 case X86::CMOV_V2F64:
9649 case X86::CMOV_V2I64:
9650 case X86::CMOV_GR16:
9651 case X86::CMOV_GR32:
9652 case X86::CMOV_RFP32:
9653 case X86::CMOV_RFP64:
9654 case X86::CMOV_RFP80:
9655 return EmitLoweredSelect(MI, BB);
9657 case X86::FP32_TO_INT16_IN_MEM:
9658 case X86::FP32_TO_INT32_IN_MEM:
9659 case X86::FP32_TO_INT64_IN_MEM:
9660 case X86::FP64_TO_INT16_IN_MEM:
9661 case X86::FP64_TO_INT32_IN_MEM:
9662 case X86::FP64_TO_INT64_IN_MEM:
9663 case X86::FP80_TO_INT16_IN_MEM:
9664 case X86::FP80_TO_INT32_IN_MEM:
9665 case X86::FP80_TO_INT64_IN_MEM: {
9666 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9667 DebugLoc DL = MI->getDebugLoc();
9669 // Change the floating point control register to use "round towards zero"
9670 // mode when truncating to an integer value.
9671 MachineFunction *F = BB->getParent();
9672 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
9673 addFrameReference(BuildMI(*BB, MI, DL,
9674 TII->get(X86::FNSTCW16m)), CWFrameIdx);
9676 // Load the old value of the high byte of the control word...
9678 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
9679 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
9682 // Set the high part to be round to zero...
9683 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
9686 // Reload the modified control word now...
9687 addFrameReference(BuildMI(*BB, MI, DL,
9688 TII->get(X86::FLDCW16m)), CWFrameIdx);
9690 // Restore the memory image of control word to original value
9691 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
9694 // Get the X86 opcode to use.
9696 switch (MI->getOpcode()) {
9697 default: llvm_unreachable("illegal opcode!");
9698 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
9699 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
9700 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
9701 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
9702 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
9703 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
9704 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
9705 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
9706 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
9710 MachineOperand &Op = MI->getOperand(0);
9712 AM.BaseType = X86AddressMode::RegBase;
9713 AM.Base.Reg = Op.getReg();
9715 AM.BaseType = X86AddressMode::FrameIndexBase;
9716 AM.Base.FrameIndex = Op.getIndex();
9718 Op = MI->getOperand(1);
9720 AM.Scale = Op.getImm();
9721 Op = MI->getOperand(2);
9723 AM.IndexReg = Op.getImm();
9724 Op = MI->getOperand(3);
9725 if (Op.isGlobal()) {
9726 AM.GV = Op.getGlobal();
9728 AM.Disp = Op.getImm();
9730 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
9731 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
9733 // Reload the original control word now.
9734 addFrameReference(BuildMI(*BB, MI, DL,
9735 TII->get(X86::FLDCW16m)), CWFrameIdx);
9737 MI->eraseFromParent(); // The pseudo instruction is gone now.
9740 // String/text processing lowering.
9741 case X86::PCMPISTRM128REG:
9742 case X86::VPCMPISTRM128REG:
9743 return EmitPCMP(MI, BB, 3, false /* in-mem */);
9744 case X86::PCMPISTRM128MEM:
9745 case X86::VPCMPISTRM128MEM:
9746 return EmitPCMP(MI, BB, 3, true /* in-mem */);
9747 case X86::PCMPESTRM128REG:
9748 case X86::VPCMPESTRM128REG:
9749 return EmitPCMP(MI, BB, 5, false /* in mem */);
9750 case X86::PCMPESTRM128MEM:
9751 case X86::VPCMPESTRM128MEM:
9752 return EmitPCMP(MI, BB, 5, true /* in mem */);
9755 case X86::ATOMAND32:
9756 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
9757 X86::AND32ri, X86::MOV32rm,
9759 X86::NOT32r, X86::EAX,
9760 X86::GR32RegisterClass);
9762 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
9763 X86::OR32ri, X86::MOV32rm,
9765 X86::NOT32r, X86::EAX,
9766 X86::GR32RegisterClass);
9767 case X86::ATOMXOR32:
9768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
9769 X86::XOR32ri, X86::MOV32rm,
9771 X86::NOT32r, X86::EAX,
9772 X86::GR32RegisterClass);
9773 case X86::ATOMNAND32:
9774 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
9775 X86::AND32ri, X86::MOV32rm,
9777 X86::NOT32r, X86::EAX,
9778 X86::GR32RegisterClass, true);
9779 case X86::ATOMMIN32:
9780 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
9781 case X86::ATOMMAX32:
9782 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
9783 case X86::ATOMUMIN32:
9784 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
9785 case X86::ATOMUMAX32:
9786 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
9788 case X86::ATOMAND16:
9789 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
9790 X86::AND16ri, X86::MOV16rm,
9792 X86::NOT16r, X86::AX,
9793 X86::GR16RegisterClass);
9795 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
9796 X86::OR16ri, X86::MOV16rm,
9798 X86::NOT16r, X86::AX,
9799 X86::GR16RegisterClass);
9800 case X86::ATOMXOR16:
9801 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
9802 X86::XOR16ri, X86::MOV16rm,
9804 X86::NOT16r, X86::AX,
9805 X86::GR16RegisterClass);
9806 case X86::ATOMNAND16:
9807 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
9808 X86::AND16ri, X86::MOV16rm,
9810 X86::NOT16r, X86::AX,
9811 X86::GR16RegisterClass, true);
9812 case X86::ATOMMIN16:
9813 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
9814 case X86::ATOMMAX16:
9815 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
9816 case X86::ATOMUMIN16:
9817 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
9818 case X86::ATOMUMAX16:
9819 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
9822 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
9823 X86::AND8ri, X86::MOV8rm,
9825 X86::NOT8r, X86::AL,
9826 X86::GR8RegisterClass);
9828 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
9829 X86::OR8ri, X86::MOV8rm,
9831 X86::NOT8r, X86::AL,
9832 X86::GR8RegisterClass);
9834 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
9835 X86::XOR8ri, X86::MOV8rm,
9837 X86::NOT8r, X86::AL,
9838 X86::GR8RegisterClass);
9839 case X86::ATOMNAND8:
9840 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
9841 X86::AND8ri, X86::MOV8rm,
9843 X86::NOT8r, X86::AL,
9844 X86::GR8RegisterClass, true);
9845 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
9846 // This group is for 64-bit host.
9847 case X86::ATOMAND64:
9848 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
9849 X86::AND64ri32, X86::MOV64rm,
9851 X86::NOT64r, X86::RAX,
9852 X86::GR64RegisterClass);
9854 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
9855 X86::OR64ri32, X86::MOV64rm,
9857 X86::NOT64r, X86::RAX,
9858 X86::GR64RegisterClass);
9859 case X86::ATOMXOR64:
9860 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
9861 X86::XOR64ri32, X86::MOV64rm,
9863 X86::NOT64r, X86::RAX,
9864 X86::GR64RegisterClass);
9865 case X86::ATOMNAND64:
9866 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
9867 X86::AND64ri32, X86::MOV64rm,
9869 X86::NOT64r, X86::RAX,
9870 X86::GR64RegisterClass, true);
9871 case X86::ATOMMIN64:
9872 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
9873 case X86::ATOMMAX64:
9874 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
9875 case X86::ATOMUMIN64:
9876 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
9877 case X86::ATOMUMAX64:
9878 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
9880 // This group does 64-bit operations on a 32-bit host.
9881 case X86::ATOMAND6432:
9882 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9883 X86::AND32rr, X86::AND32rr,
9884 X86::AND32ri, X86::AND32ri,
9886 case X86::ATOMOR6432:
9887 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9888 X86::OR32rr, X86::OR32rr,
9889 X86::OR32ri, X86::OR32ri,
9891 case X86::ATOMXOR6432:
9892 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9893 X86::XOR32rr, X86::XOR32rr,
9894 X86::XOR32ri, X86::XOR32ri,
9896 case X86::ATOMNAND6432:
9897 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9898 X86::AND32rr, X86::AND32rr,
9899 X86::AND32ri, X86::AND32ri,
9901 case X86::ATOMADD6432:
9902 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9903 X86::ADD32rr, X86::ADC32rr,
9904 X86::ADD32ri, X86::ADC32ri,
9906 case X86::ATOMSUB6432:
9907 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9908 X86::SUB32rr, X86::SBB32rr,
9909 X86::SUB32ri, X86::SBB32ri,
9911 case X86::ATOMSWAP6432:
9912 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9913 X86::MOV32rr, X86::MOV32rr,
9914 X86::MOV32ri, X86::MOV32ri,
9916 case X86::VASTART_SAVE_XMM_REGS:
9917 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
9921 //===----------------------------------------------------------------------===//
9922 // X86 Optimization Hooks
9923 //===----------------------------------------------------------------------===//
9925 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9929 const SelectionDAG &DAG,
9930 unsigned Depth) const {
9931 unsigned Opc = Op.getOpcode();
9932 assert((Opc >= ISD::BUILTIN_OP_END ||
9933 Opc == ISD::INTRINSIC_WO_CHAIN ||
9934 Opc == ISD::INTRINSIC_W_CHAIN ||
9935 Opc == ISD::INTRINSIC_VOID) &&
9936 "Should use MaskedValueIsZero if you don't know whether Op"
9937 " is a target node!");
9939 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
9951 // These nodes' second result is a boolean.
9952 if (Op.getResNo() == 0)
9956 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
9957 Mask.getBitWidth() - 1);
9962 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
9963 unsigned Depth) const {
9964 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
9965 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
9966 return Op.getValueType().getScalarType().getSizeInBits();
9972 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
9973 /// node is a GlobalAddress + offset.
9974 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
9975 const GlobalValue* &GA,
9976 int64_t &Offset) const {
9977 if (N->getOpcode() == X86ISD::Wrapper) {
9978 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
9979 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
9980 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
9984 return TargetLowering::isGAPlusOffset(N, GA, Offset);
9987 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
9988 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
9989 /// if the load addresses are consecutive, non-overlapping, and in the right
9991 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
9992 const TargetLowering &TLI) {
9993 DebugLoc dl = N->getDebugLoc();
9994 EVT VT = N->getValueType(0);
9996 if (VT.getSizeInBits() != 128)
9999 SmallVector<SDValue, 16> Elts;
10000 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
10001 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
10003 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
10006 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
10007 /// generation and convert it from being a bunch of shuffles and extracts
10008 /// to a simple store and scalar loads to extract the elements.
10009 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
10010 const TargetLowering &TLI) {
10011 SDValue InputVector = N->getOperand(0);
10013 // Only operate on vectors of 4 elements, where the alternative shuffling
10014 // gets to be more expensive.
10015 if (InputVector.getValueType() != MVT::v4i32)
10018 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
10019 // single use which is a sign-extend or zero-extend, and all elements are
10021 SmallVector<SDNode *, 4> Uses;
10022 unsigned ExtractedElements = 0;
10023 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
10024 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
10025 if (UI.getUse().getResNo() != InputVector.getResNo())
10028 SDNode *Extract = *UI;
10029 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10032 if (Extract->getValueType(0) != MVT::i32)
10034 if (!Extract->hasOneUse())
10036 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
10037 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
10039 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
10042 // Record which element was extracted.
10043 ExtractedElements |=
10044 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
10046 Uses.push_back(Extract);
10049 // If not all the elements were used, this may not be worthwhile.
10050 if (ExtractedElements != 15)
10053 // Ok, we've now decided to do the transformation.
10054 DebugLoc dl = InputVector.getDebugLoc();
10056 // Store the value to a temporary stack slot.
10057 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
10058 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
10059 MachinePointerInfo(), false, false, 0);
10061 // Replace each use (extract) with a load of the appropriate element.
10062 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
10063 UE = Uses.end(); UI != UE; ++UI) {
10064 SDNode *Extract = *UI;
10066 // Compute the element's address.
10067 SDValue Idx = Extract->getOperand(1);
10069 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
10070 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
10071 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
10073 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
10074 StackPtr, OffsetVal);
10076 // Load the scalar.
10077 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
10078 ScalarAddr, MachinePointerInfo(),
10081 // Replace the exact with the load.
10082 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
10085 // The replacement was made in place; don't return anything.
10089 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
10090 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
10091 const X86Subtarget *Subtarget) {
10092 DebugLoc DL = N->getDebugLoc();
10093 SDValue Cond = N->getOperand(0);
10094 // Get the LHS/RHS of the select.
10095 SDValue LHS = N->getOperand(1);
10096 SDValue RHS = N->getOperand(2);
10098 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
10099 // instructions match the semantics of the common C idiom x<y?x:y but not
10100 // x<=y?x:y, because of how they handle negative zero (which can be
10101 // ignored in unsafe-math mode).
10102 if (Subtarget->hasSSE2() &&
10103 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
10104 Cond.getOpcode() == ISD::SETCC) {
10105 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
10107 unsigned Opcode = 0;
10108 // Check for x CC y ? x : y.
10109 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
10110 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
10114 // Converting this to a min would handle NaNs incorrectly, and swapping
10115 // the operands would cause it to handle comparisons between positive
10116 // and negative zero incorrectly.
10117 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10118 if (!UnsafeFPMath &&
10119 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10121 std::swap(LHS, RHS);
10123 Opcode = X86ISD::FMIN;
10126 // Converting this to a min would handle comparisons between positive
10127 // and negative zero incorrectly.
10128 if (!UnsafeFPMath &&
10129 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
10131 Opcode = X86ISD::FMIN;
10134 // Converting this to a min would handle both negative zeros and NaNs
10135 // incorrectly, but we can swap the operands to fix both.
10136 std::swap(LHS, RHS);
10140 Opcode = X86ISD::FMIN;
10144 // Converting this to a max would handle comparisons between positive
10145 // and negative zero incorrectly.
10146 if (!UnsafeFPMath &&
10147 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
10149 Opcode = X86ISD::FMAX;
10152 // Converting this to a max would handle NaNs incorrectly, and swapping
10153 // the operands would cause it to handle comparisons between positive
10154 // and negative zero incorrectly.
10155 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10156 if (!UnsafeFPMath &&
10157 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10159 std::swap(LHS, RHS);
10161 Opcode = X86ISD::FMAX;
10164 // Converting this to a max would handle both negative zeros and NaNs
10165 // incorrectly, but we can swap the operands to fix both.
10166 std::swap(LHS, RHS);
10170 Opcode = X86ISD::FMAX;
10173 // Check for x CC y ? y : x -- a min/max with reversed arms.
10174 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10175 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10179 // Converting this to a min would handle comparisons between positive
10180 // and negative zero incorrectly, and swapping the operands would
10181 // cause it to handle NaNs incorrectly.
10182 if (!UnsafeFPMath &&
10183 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10184 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10186 std::swap(LHS, RHS);
10188 Opcode = X86ISD::FMIN;
10191 // Converting this to a min would handle NaNs incorrectly.
10192 if (!UnsafeFPMath &&
10193 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10195 Opcode = X86ISD::FMIN;
10198 // Converting this to a min would handle both negative zeros and NaNs
10199 // incorrectly, but we can swap the operands to fix both.
10200 std::swap(LHS, RHS);
10204 Opcode = X86ISD::FMIN;
10208 // Converting this to a max would handle NaNs incorrectly.
10209 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10211 Opcode = X86ISD::FMAX;
10214 // Converting this to a max would handle comparisons between positive
10215 // and negative zero incorrectly, and swapping the operands would
10216 // cause it to handle NaNs incorrectly.
10217 if (!UnsafeFPMath &&
10218 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10219 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10221 std::swap(LHS, RHS);
10223 Opcode = X86ISD::FMAX;
10226 // Converting this to a max would handle both negative zeros and NaNs
10227 // incorrectly, but we can swap the operands to fix both.
10228 std::swap(LHS, RHS);
10232 Opcode = X86ISD::FMAX;
10238 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10241 // If this is a select between two integer constants, try to do some
10243 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10244 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10245 // Don't do this for crazy integer types.
10246 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10247 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10248 // so that TrueC (the true value) is larger than FalseC.
10249 bool NeedsCondInvert = false;
10251 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10252 // Efficiently invertible.
10253 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10254 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10255 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10256 NeedsCondInvert = true;
10257 std::swap(TrueC, FalseC);
10260 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10261 if (FalseC->getAPIntValue() == 0 &&
10262 TrueC->getAPIntValue().isPowerOf2()) {
10263 if (NeedsCondInvert) // Invert the condition if needed.
10264 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10265 DAG.getConstant(1, Cond.getValueType()));
10267 // Zero extend the condition if needed.
10268 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10270 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10271 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10272 DAG.getConstant(ShAmt, MVT::i8));
10275 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10276 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10277 if (NeedsCondInvert) // Invert the condition if needed.
10278 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10279 DAG.getConstant(1, Cond.getValueType()));
10281 // Zero extend the condition if needed.
10282 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10283 FalseC->getValueType(0), Cond);
10284 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10285 SDValue(FalseC, 0));
10288 // Optimize cases that will turn into an LEA instruction. This requires
10289 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10290 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10291 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10292 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10294 bool isFastMultiplier = false;
10296 switch ((unsigned char)Diff) {
10298 case 1: // result = add base, cond
10299 case 2: // result = lea base( , cond*2)
10300 case 3: // result = lea base(cond, cond*2)
10301 case 4: // result = lea base( , cond*4)
10302 case 5: // result = lea base(cond, cond*4)
10303 case 8: // result = lea base( , cond*8)
10304 case 9: // result = lea base(cond, cond*8)
10305 isFastMultiplier = true;
10310 if (isFastMultiplier) {
10311 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10312 if (NeedsCondInvert) // Invert the condition if needed.
10313 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10314 DAG.getConstant(1, Cond.getValueType()));
10316 // Zero extend the condition if needed.
10317 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10319 // Scale the condition by the difference.
10321 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10322 DAG.getConstant(Diff, Cond.getValueType()));
10324 // Add the base if non-zero.
10325 if (FalseC->getAPIntValue() != 0)
10326 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10327 SDValue(FalseC, 0));
10337 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10338 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10339 TargetLowering::DAGCombinerInfo &DCI) {
10340 DebugLoc DL = N->getDebugLoc();
10342 // If the flag operand isn't dead, don't touch this CMOV.
10343 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10346 // If this is a select between two integer constants, try to do some
10347 // optimizations. Note that the operands are ordered the opposite of SELECT
10349 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10350 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10351 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10352 // larger than FalseC (the false value).
10353 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10355 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10356 CC = X86::GetOppositeBranchCondition(CC);
10357 std::swap(TrueC, FalseC);
10360 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10361 // This is efficient for any integer data type (including i8/i16) and
10363 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10364 SDValue Cond = N->getOperand(3);
10365 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10366 DAG.getConstant(CC, MVT::i8), Cond);
10368 // Zero extend the condition if needed.
10369 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10371 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10372 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10373 DAG.getConstant(ShAmt, MVT::i8));
10374 if (N->getNumValues() == 2) // Dead flag value?
10375 return DCI.CombineTo(N, Cond, SDValue());
10379 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10380 // for any integer data type, including i8/i16.
10381 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10382 SDValue Cond = N->getOperand(3);
10383 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10384 DAG.getConstant(CC, MVT::i8), Cond);
10386 // Zero extend the condition if needed.
10387 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10388 FalseC->getValueType(0), Cond);
10389 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10390 SDValue(FalseC, 0));
10392 if (N->getNumValues() == 2) // Dead flag value?
10393 return DCI.CombineTo(N, Cond, SDValue());
10397 // Optimize cases that will turn into an LEA instruction. This requires
10398 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10399 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10400 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10401 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10403 bool isFastMultiplier = false;
10405 switch ((unsigned char)Diff) {
10407 case 1: // result = add base, cond
10408 case 2: // result = lea base( , cond*2)
10409 case 3: // result = lea base(cond, cond*2)
10410 case 4: // result = lea base( , cond*4)
10411 case 5: // result = lea base(cond, cond*4)
10412 case 8: // result = lea base( , cond*8)
10413 case 9: // result = lea base(cond, cond*8)
10414 isFastMultiplier = true;
10419 if (isFastMultiplier) {
10420 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10421 SDValue Cond = N->getOperand(3);
10422 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10423 DAG.getConstant(CC, MVT::i8), Cond);
10424 // Zero extend the condition if needed.
10425 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10427 // Scale the condition by the difference.
10429 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10430 DAG.getConstant(Diff, Cond.getValueType()));
10432 // Add the base if non-zero.
10433 if (FalseC->getAPIntValue() != 0)
10434 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10435 SDValue(FalseC, 0));
10436 if (N->getNumValues() == 2) // Dead flag value?
10437 return DCI.CombineTo(N, Cond, SDValue());
10447 /// PerformMulCombine - Optimize a single multiply with constant into two
10448 /// in order to implement it with two cheaper instructions, e.g.
10449 /// LEA + SHL, LEA + LEA.
10450 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10451 TargetLowering::DAGCombinerInfo &DCI) {
10452 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10455 EVT VT = N->getValueType(0);
10456 if (VT != MVT::i64)
10459 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10462 uint64_t MulAmt = C->getZExtValue();
10463 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10466 uint64_t MulAmt1 = 0;
10467 uint64_t MulAmt2 = 0;
10468 if ((MulAmt % 9) == 0) {
10470 MulAmt2 = MulAmt / 9;
10471 } else if ((MulAmt % 5) == 0) {
10473 MulAmt2 = MulAmt / 5;
10474 } else if ((MulAmt % 3) == 0) {
10476 MulAmt2 = MulAmt / 3;
10479 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10480 DebugLoc DL = N->getDebugLoc();
10482 if (isPowerOf2_64(MulAmt2) &&
10483 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10484 // If second multiplifer is pow2, issue it first. We want the multiply by
10485 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10487 std::swap(MulAmt1, MulAmt2);
10490 if (isPowerOf2_64(MulAmt1))
10491 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10492 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10494 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10495 DAG.getConstant(MulAmt1, VT));
10497 if (isPowerOf2_64(MulAmt2))
10498 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10499 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10501 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10502 DAG.getConstant(MulAmt2, VT));
10504 // Do not add new nodes to DAG combiner worklist.
10505 DCI.CombineTo(N, NewMul, false);
10510 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10511 SDValue N0 = N->getOperand(0);
10512 SDValue N1 = N->getOperand(1);
10513 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10514 EVT VT = N0.getValueType();
10516 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10517 // since the result of setcc_c is all zero's or all ones.
10518 if (N1C && N0.getOpcode() == ISD::AND &&
10519 N0.getOperand(1).getOpcode() == ISD::Constant) {
10520 SDValue N00 = N0.getOperand(0);
10521 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10522 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10523 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10524 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10525 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10526 APInt ShAmt = N1C->getAPIntValue();
10527 Mask = Mask.shl(ShAmt);
10529 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10530 N00, DAG.getConstant(Mask, VT));
10537 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10539 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10540 const X86Subtarget *Subtarget) {
10541 EVT VT = N->getValueType(0);
10542 if (!VT.isVector() && VT.isInteger() &&
10543 N->getOpcode() == ISD::SHL)
10544 return PerformSHLCombine(N, DAG);
10546 // On X86 with SSE2 support, we can transform this to a vector shift if
10547 // all elements are shifted by the same amount. We can't do this in legalize
10548 // because the a constant vector is typically transformed to a constant pool
10549 // so we have no knowledge of the shift amount.
10550 if (!Subtarget->hasSSE2())
10553 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
10556 SDValue ShAmtOp = N->getOperand(1);
10557 EVT EltVT = VT.getVectorElementType();
10558 DebugLoc DL = N->getDebugLoc();
10559 SDValue BaseShAmt = SDValue();
10560 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
10561 unsigned NumElts = VT.getVectorNumElements();
10563 for (; i != NumElts; ++i) {
10564 SDValue Arg = ShAmtOp.getOperand(i);
10565 if (Arg.getOpcode() == ISD::UNDEF) continue;
10569 for (; i != NumElts; ++i) {
10570 SDValue Arg = ShAmtOp.getOperand(i);
10571 if (Arg.getOpcode() == ISD::UNDEF) continue;
10572 if (Arg != BaseShAmt) {
10576 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
10577 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
10578 SDValue InVec = ShAmtOp.getOperand(0);
10579 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
10580 unsigned NumElts = InVec.getValueType().getVectorNumElements();
10582 for (; i != NumElts; ++i) {
10583 SDValue Arg = InVec.getOperand(i);
10584 if (Arg.getOpcode() == ISD::UNDEF) continue;
10588 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
10589 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
10590 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
10591 if (C->getZExtValue() == SplatIdx)
10592 BaseShAmt = InVec.getOperand(1);
10595 if (BaseShAmt.getNode() == 0)
10596 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
10597 DAG.getIntPtrConstant(0));
10601 // The shift amount is an i32.
10602 if (EltVT.bitsGT(MVT::i32))
10603 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
10604 else if (EltVT.bitsLT(MVT::i32))
10605 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
10607 // The shift amount is identical so we can do a vector shift.
10608 SDValue ValOp = N->getOperand(0);
10609 switch (N->getOpcode()) {
10611 llvm_unreachable("Unknown shift opcode!");
10614 if (VT == MVT::v2i64)
10615 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10616 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10618 if (VT == MVT::v4i32)
10619 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10620 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10622 if (VT == MVT::v8i16)
10623 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10624 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10628 if (VT == MVT::v4i32)
10629 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10630 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10632 if (VT == MVT::v8i16)
10633 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10634 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10638 if (VT == MVT::v2i64)
10639 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10640 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10642 if (VT == MVT::v4i32)
10643 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10644 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10646 if (VT == MVT::v8i16)
10647 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10648 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10655 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
10656 TargetLowering::DAGCombinerInfo &DCI,
10657 const X86Subtarget *Subtarget) {
10658 if (DCI.isBeforeLegalizeOps())
10661 EVT VT = N->getValueType(0);
10662 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
10665 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
10666 SDValue N0 = N->getOperand(0);
10667 SDValue N1 = N->getOperand(1);
10668 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
10670 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
10672 if (!N0.hasOneUse() || !N1.hasOneUse())
10675 SDValue ShAmt0 = N0.getOperand(1);
10676 if (ShAmt0.getValueType() != MVT::i8)
10678 SDValue ShAmt1 = N1.getOperand(1);
10679 if (ShAmt1.getValueType() != MVT::i8)
10681 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
10682 ShAmt0 = ShAmt0.getOperand(0);
10683 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
10684 ShAmt1 = ShAmt1.getOperand(0);
10686 DebugLoc DL = N->getDebugLoc();
10687 unsigned Opc = X86ISD::SHLD;
10688 SDValue Op0 = N0.getOperand(0);
10689 SDValue Op1 = N1.getOperand(0);
10690 if (ShAmt0.getOpcode() == ISD::SUB) {
10691 Opc = X86ISD::SHRD;
10692 std::swap(Op0, Op1);
10693 std::swap(ShAmt0, ShAmt1);
10696 unsigned Bits = VT.getSizeInBits();
10697 if (ShAmt1.getOpcode() == ISD::SUB) {
10698 SDValue Sum = ShAmt1.getOperand(0);
10699 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
10700 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
10701 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
10702 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
10703 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
10704 return DAG.getNode(Opc, DL, VT,
10706 DAG.getNode(ISD::TRUNCATE, DL,
10709 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
10710 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
10712 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
10713 return DAG.getNode(Opc, DL, VT,
10714 N0.getOperand(0), N1.getOperand(0),
10715 DAG.getNode(ISD::TRUNCATE, DL,
10722 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
10723 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
10724 const X86Subtarget *Subtarget) {
10725 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
10726 // the FP state in cases where an emms may be missing.
10727 // A preferable solution to the general problem is to figure out the right
10728 // places to insert EMMS. This qualifies as a quick hack.
10730 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
10731 StoreSDNode *St = cast<StoreSDNode>(N);
10732 EVT VT = St->getValue().getValueType();
10733 if (VT.getSizeInBits() != 64)
10736 const Function *F = DAG.getMachineFunction().getFunction();
10737 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
10738 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
10739 && Subtarget->hasSSE2();
10740 if ((VT.isVector() ||
10741 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
10742 isa<LoadSDNode>(St->getValue()) &&
10743 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
10744 St->getChain().hasOneUse() && !St->isVolatile()) {
10745 SDNode* LdVal = St->getValue().getNode();
10746 LoadSDNode *Ld = 0;
10747 int TokenFactorIndex = -1;
10748 SmallVector<SDValue, 8> Ops;
10749 SDNode* ChainVal = St->getChain().getNode();
10750 // Must be a store of a load. We currently handle two cases: the load
10751 // is a direct child, and it's under an intervening TokenFactor. It is
10752 // possible to dig deeper under nested TokenFactors.
10753 if (ChainVal == LdVal)
10754 Ld = cast<LoadSDNode>(St->getChain());
10755 else if (St->getValue().hasOneUse() &&
10756 ChainVal->getOpcode() == ISD::TokenFactor) {
10757 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
10758 if (ChainVal->getOperand(i).getNode() == LdVal) {
10759 TokenFactorIndex = i;
10760 Ld = cast<LoadSDNode>(St->getValue());
10762 Ops.push_back(ChainVal->getOperand(i));
10766 if (!Ld || !ISD::isNormalLoad(Ld))
10769 // If this is not the MMX case, i.e. we are just turning i64 load/store
10770 // into f64 load/store, avoid the transformation if there are multiple
10771 // uses of the loaded value.
10772 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
10775 DebugLoc LdDL = Ld->getDebugLoc();
10776 DebugLoc StDL = N->getDebugLoc();
10777 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
10778 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
10780 if (Subtarget->is64Bit() || F64IsLegal) {
10781 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
10782 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
10783 Ld->getPointerInfo(), Ld->isVolatile(),
10784 Ld->isNonTemporal(), Ld->getAlignment());
10785 SDValue NewChain = NewLd.getValue(1);
10786 if (TokenFactorIndex != -1) {
10787 Ops.push_back(NewChain);
10788 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
10791 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
10792 St->getPointerInfo(),
10793 St->isVolatile(), St->isNonTemporal(),
10794 St->getAlignment());
10797 // Otherwise, lower to two pairs of 32-bit loads / stores.
10798 SDValue LoAddr = Ld->getBasePtr();
10799 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
10800 DAG.getConstant(4, MVT::i32));
10802 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
10803 Ld->getPointerInfo(),
10804 Ld->isVolatile(), Ld->isNonTemporal(),
10805 Ld->getAlignment());
10806 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
10807 Ld->getPointerInfo().getWithOffset(4),
10808 Ld->isVolatile(), Ld->isNonTemporal(),
10809 MinAlign(Ld->getAlignment(), 4));
10811 SDValue NewChain = LoLd.getValue(1);
10812 if (TokenFactorIndex != -1) {
10813 Ops.push_back(LoLd);
10814 Ops.push_back(HiLd);
10815 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
10819 LoAddr = St->getBasePtr();
10820 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
10821 DAG.getConstant(4, MVT::i32));
10823 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
10824 St->getPointerInfo(),
10825 St->isVolatile(), St->isNonTemporal(),
10826 St->getAlignment());
10827 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
10828 St->getPointerInfo().getWithOffset(4),
10830 St->isNonTemporal(),
10831 MinAlign(St->getAlignment(), 4));
10832 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
10837 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
10838 /// X86ISD::FXOR nodes.
10839 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
10840 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
10841 // F[X]OR(0.0, x) -> x
10842 // F[X]OR(x, 0.0) -> x
10843 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
10844 if (C->getValueAPF().isPosZero())
10845 return N->getOperand(1);
10846 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
10847 if (C->getValueAPF().isPosZero())
10848 return N->getOperand(0);
10852 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
10853 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
10854 // FAND(0.0, x) -> 0.0
10855 // FAND(x, 0.0) -> 0.0
10856 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
10857 if (C->getValueAPF().isPosZero())
10858 return N->getOperand(0);
10859 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
10860 if (C->getValueAPF().isPosZero())
10861 return N->getOperand(1);
10865 static SDValue PerformBTCombine(SDNode *N,
10867 TargetLowering::DAGCombinerInfo &DCI) {
10868 // BT ignores high bits in the bit index operand.
10869 SDValue Op1 = N->getOperand(1);
10870 if (Op1.hasOneUse()) {
10871 unsigned BitWidth = Op1.getValueSizeInBits();
10872 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
10873 APInt KnownZero, KnownOne;
10874 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
10875 !DCI.isBeforeLegalizeOps());
10876 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10877 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
10878 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
10879 DCI.CommitTargetLoweringOpt(TLO);
10884 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
10885 SDValue Op = N->getOperand(0);
10886 if (Op.getOpcode() == ISD::BIT_CONVERT)
10887 Op = Op.getOperand(0);
10888 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
10889 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
10890 VT.getVectorElementType().getSizeInBits() ==
10891 OpVT.getVectorElementType().getSizeInBits()) {
10892 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
10897 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
10898 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
10899 // (and (i32 x86isd::setcc_carry), 1)
10900 // This eliminates the zext. This transformation is necessary because
10901 // ISD::SETCC is always legalized to i8.
10902 DebugLoc dl = N->getDebugLoc();
10903 SDValue N0 = N->getOperand(0);
10904 EVT VT = N->getValueType(0);
10905 if (N0.getOpcode() == ISD::AND &&
10907 N0.getOperand(0).hasOneUse()) {
10908 SDValue N00 = N0.getOperand(0);
10909 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
10911 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
10912 if (!C || C->getZExtValue() != 1)
10914 return DAG.getNode(ISD::AND, dl, VT,
10915 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
10916 N00.getOperand(0), N00.getOperand(1)),
10917 DAG.getConstant(1, VT));
10923 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
10924 DAGCombinerInfo &DCI) const {
10925 SelectionDAG &DAG = DCI.DAG;
10926 switch (N->getOpcode()) {
10928 case ISD::EXTRACT_VECTOR_ELT:
10929 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
10930 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
10931 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
10932 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
10935 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
10936 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
10937 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
10939 case X86ISD::FOR: return PerformFORCombine(N, DAG);
10940 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
10941 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
10942 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
10943 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
10944 case X86ISD::SHUFPS: // Handle all target specific shuffles
10945 case X86ISD::SHUFPD:
10946 case X86ISD::PALIGN:
10947 case X86ISD::PUNPCKHBW:
10948 case X86ISD::PUNPCKHWD:
10949 case X86ISD::PUNPCKHDQ:
10950 case X86ISD::PUNPCKHQDQ:
10951 case X86ISD::UNPCKHPS:
10952 case X86ISD::UNPCKHPD:
10953 case X86ISD::PUNPCKLBW:
10954 case X86ISD::PUNPCKLWD:
10955 case X86ISD::PUNPCKLDQ:
10956 case X86ISD::PUNPCKLQDQ:
10957 case X86ISD::UNPCKLPS:
10958 case X86ISD::UNPCKLPD:
10959 case X86ISD::MOVHLPS:
10960 case X86ISD::MOVLHPS:
10961 case X86ISD::PSHUFD:
10962 case X86ISD::PSHUFHW:
10963 case X86ISD::PSHUFLW:
10964 case X86ISD::MOVSS:
10965 case X86ISD::MOVSD:
10966 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
10972 /// isTypeDesirableForOp - Return true if the target has native support for
10973 /// the specified value type and it is 'desirable' to use the type for the
10974 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
10975 /// instruction encodings are longer and some i16 instructions are slow.
10976 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
10977 if (!isTypeLegal(VT))
10979 if (VT != MVT::i16)
10986 case ISD::SIGN_EXTEND:
10987 case ISD::ZERO_EXTEND:
10988 case ISD::ANY_EXTEND:
11001 /// IsDesirableToPromoteOp - This method query the target whether it is
11002 /// beneficial for dag combiner to promote the specified node. If true, it
11003 /// should return the desired promotion type by reference.
11004 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
11005 EVT VT = Op.getValueType();
11006 if (VT != MVT::i16)
11009 bool Promote = false;
11010 bool Commute = false;
11011 switch (Op.getOpcode()) {
11014 LoadSDNode *LD = cast<LoadSDNode>(Op);
11015 // If the non-extending load has a single use and it's not live out, then it
11016 // might be folded.
11017 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
11018 Op.hasOneUse()*/) {
11019 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11020 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
11021 // The only case where we'd want to promote LOAD (rather then it being
11022 // promoted as an operand is when it's only use is liveout.
11023 if (UI->getOpcode() != ISD::CopyToReg)
11030 case ISD::SIGN_EXTEND:
11031 case ISD::ZERO_EXTEND:
11032 case ISD::ANY_EXTEND:
11037 SDValue N0 = Op.getOperand(0);
11038 // Look out for (store (shl (load), x)).
11039 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
11052 SDValue N0 = Op.getOperand(0);
11053 SDValue N1 = Op.getOperand(1);
11054 if (!Commute && MayFoldLoad(N1))
11056 // Avoid disabling potential load folding opportunities.
11057 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
11059 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
11069 //===----------------------------------------------------------------------===//
11070 // X86 Inline Assembly Support
11071 //===----------------------------------------------------------------------===//
11073 static bool LowerToBSwap(CallInst *CI) {
11074 // FIXME: this should verify that we are targetting a 486 or better. If not,
11075 // we will turn this bswap into something that will be lowered to logical ops
11076 // instead of emitting the bswap asm. For now, we don't support 486 or lower
11077 // so don't worry about this.
11079 // Verify this is a simple bswap.
11080 if (CI->getNumArgOperands() != 1 ||
11081 CI->getType() != CI->getArgOperand(0)->getType() ||
11082 !CI->getType()->isIntegerTy())
11085 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11086 if (!Ty || Ty->getBitWidth() % 16 != 0)
11089 // Okay, we can do this xform, do so now.
11090 const Type *Tys[] = { Ty };
11091 Module *M = CI->getParent()->getParent()->getParent();
11092 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
11094 Value *Op = CI->getArgOperand(0);
11095 Op = CallInst::Create(Int, Op, CI->getName(), CI);
11097 CI->replaceAllUsesWith(Op);
11098 CI->eraseFromParent();
11102 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
11103 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11104 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
11106 std::string AsmStr = IA->getAsmString();
11108 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
11109 SmallVector<StringRef, 4> AsmPieces;
11110 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
11112 switch (AsmPieces.size()) {
11113 default: return false;
11115 AsmStr = AsmPieces[0];
11117 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
11120 if (AsmPieces.size() == 2 &&
11121 (AsmPieces[0] == "bswap" ||
11122 AsmPieces[0] == "bswapq" ||
11123 AsmPieces[0] == "bswapl") &&
11124 (AsmPieces[1] == "$0" ||
11125 AsmPieces[1] == "${0:q}")) {
11126 // No need to check constraints, nothing other than the equivalent of
11127 // "=r,0" would be valid here.
11128 return LowerToBSwap(CI);
11130 // rorw $$8, ${0:w} --> llvm.bswap.i16
11131 if (CI->getType()->isIntegerTy(16) &&
11132 AsmPieces.size() == 3 &&
11133 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
11134 AsmPieces[1] == "$$8," &&
11135 AsmPieces[2] == "${0:w}" &&
11136 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11138 const std::string &Constraints = IA->getConstraintString();
11139 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11140 std::sort(AsmPieces.begin(), AsmPieces.end());
11141 if (AsmPieces.size() == 4 &&
11142 AsmPieces[0] == "~{cc}" &&
11143 AsmPieces[1] == "~{dirflag}" &&
11144 AsmPieces[2] == "~{flags}" &&
11145 AsmPieces[3] == "~{fpsr}") {
11146 return LowerToBSwap(CI);
11151 if (CI->getType()->isIntegerTy(64) &&
11152 Constraints.size() >= 2 &&
11153 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11154 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11155 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11156 SmallVector<StringRef, 4> Words;
11157 SplitString(AsmPieces[0], Words, " \t");
11158 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11160 SplitString(AsmPieces[1], Words, " \t");
11161 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11163 SplitString(AsmPieces[2], Words, " \t,");
11164 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11165 Words[2] == "%edx") {
11166 return LowerToBSwap(CI);
11178 /// getConstraintType - Given a constraint letter, return the type of
11179 /// constraint it is for this target.
11180 X86TargetLowering::ConstraintType
11181 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11182 if (Constraint.size() == 1) {
11183 switch (Constraint[0]) {
11195 return C_RegisterClass;
11203 return TargetLowering::getConstraintType(Constraint);
11206 /// Examine constraint type and operand type and determine a weight value,
11207 /// where: -1 = invalid match, and 0 = so-so match to 3 = good match.
11208 /// This object must already have been set up with the operand type
11209 /// and the current alternative constraint selected.
11210 int X86TargetLowering::getSingleConstraintMatchWeight(
11211 AsmOperandInfo &info, const char *constraint) const {
11213 Value *CallOperandVal = info.CallOperandVal;
11214 // If we don't have a value, we can't do a match,
11215 // but allow it at the lowest weight.
11216 if (CallOperandVal == NULL)
11218 // Look at the constraint type.
11219 switch (*constraint) {
11221 return TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11224 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
11225 if (C->getZExtValue() <= 31)
11234 /// LowerXConstraint - try to replace an X constraint, which matches anything,
11235 /// with another that has more specific requirements based on the type of the
11236 /// corresponding operand.
11237 const char *X86TargetLowering::
11238 LowerXConstraint(EVT ConstraintVT) const {
11239 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
11240 // 'f' like normal targets.
11241 if (ConstraintVT.isFloatingPoint()) {
11242 if (Subtarget->hasSSE2())
11244 if (Subtarget->hasSSE1())
11248 return TargetLowering::LowerXConstraint(ConstraintVT);
11251 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11252 /// vector. If it is invalid, don't add anything to Ops.
11253 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11255 std::vector<SDValue>&Ops,
11256 SelectionDAG &DAG) const {
11257 SDValue Result(0, 0);
11259 switch (Constraint) {
11262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11263 if (C->getZExtValue() <= 31) {
11264 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11270 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11271 if (C->getZExtValue() <= 63) {
11272 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11278 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11279 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
11280 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11287 if (C->getZExtValue() <= 255) {
11288 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11294 // 32-bit signed value
11295 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11296 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11297 C->getSExtValue())) {
11298 // Widen to 64 bits here to get it sign extended.
11299 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
11302 // FIXME gcc accepts some relocatable values here too, but only in certain
11303 // memory models; it's complicated.
11308 // 32-bit unsigned value
11309 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11310 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11311 C->getZExtValue())) {
11312 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11316 // FIXME gcc accepts some relocatable values here too, but only in certain
11317 // memory models; it's complicated.
11321 // Literal immediates are always ok.
11322 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
11323 // Widen to 64 bits here to get it sign extended.
11324 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
11328 // In any sort of PIC mode addresses need to be computed at runtime by
11329 // adding in a register or some sort of table lookup. These can't
11330 // be used as immediates.
11331 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
11334 // If we are in non-pic codegen mode, we allow the address of a global (with
11335 // an optional displacement) to be used with 'i'.
11336 GlobalAddressSDNode *GA = 0;
11337 int64_t Offset = 0;
11339 // Match either (GA), (GA+C), (GA+C1+C2), etc.
11341 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
11342 Offset += GA->getOffset();
11344 } else if (Op.getOpcode() == ISD::ADD) {
11345 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11346 Offset += C->getZExtValue();
11347 Op = Op.getOperand(0);
11350 } else if (Op.getOpcode() == ISD::SUB) {
11351 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11352 Offset += -C->getZExtValue();
11353 Op = Op.getOperand(0);
11358 // Otherwise, this isn't something we can handle, reject it.
11362 const GlobalValue *GV = GA->getGlobal();
11363 // If we require an extra load to get this address, as in PIC mode, we
11364 // can't accept it.
11365 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
11366 getTargetMachine())))
11369 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
11370 GA->getValueType(0), Offset);
11375 if (Result.getNode()) {
11376 Ops.push_back(Result);
11379 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11382 std::vector<unsigned> X86TargetLowering::
11383 getRegClassForInlineAsmConstraint(const std::string &Constraint,
11385 if (Constraint.size() == 1) {
11386 // FIXME: not handling fp-stack yet!
11387 switch (Constraint[0]) { // GCC X86 Constraint Letters
11388 default: break; // Unknown constraint letter
11389 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
11390 if (Subtarget->is64Bit()) {
11391 if (VT == MVT::i32)
11392 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
11393 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
11394 X86::R10D,X86::R11D,X86::R12D,
11395 X86::R13D,X86::R14D,X86::R15D,
11396 X86::EBP, X86::ESP, 0);
11397 else if (VT == MVT::i16)
11398 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
11399 X86::SI, X86::DI, X86::R8W,X86::R9W,
11400 X86::R10W,X86::R11W,X86::R12W,
11401 X86::R13W,X86::R14W,X86::R15W,
11402 X86::BP, X86::SP, 0);
11403 else if (VT == MVT::i8)
11404 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
11405 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
11406 X86::R10B,X86::R11B,X86::R12B,
11407 X86::R13B,X86::R14B,X86::R15B,
11408 X86::BPL, X86::SPL, 0);
11410 else if (VT == MVT::i64)
11411 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
11412 X86::RSI, X86::RDI, X86::R8, X86::R9,
11413 X86::R10, X86::R11, X86::R12,
11414 X86::R13, X86::R14, X86::R15,
11415 X86::RBP, X86::RSP, 0);
11419 // 32-bit fallthrough
11420 case 'Q': // Q_REGS
11421 if (VT == MVT::i32)
11422 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
11423 else if (VT == MVT::i16)
11424 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
11425 else if (VT == MVT::i8)
11426 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
11427 else if (VT == MVT::i64)
11428 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
11433 return std::vector<unsigned>();
11436 std::pair<unsigned, const TargetRegisterClass*>
11437 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
11439 // First, see if this is a constraint that directly corresponds to an LLVM
11441 if (Constraint.size() == 1) {
11442 // GCC Constraint Letters
11443 switch (Constraint[0]) {
11445 case 'r': // GENERAL_REGS
11446 case 'l': // INDEX_REGS
11448 return std::make_pair(0U, X86::GR8RegisterClass);
11449 if (VT == MVT::i16)
11450 return std::make_pair(0U, X86::GR16RegisterClass);
11451 if (VT == MVT::i32 || !Subtarget->is64Bit())
11452 return std::make_pair(0U, X86::GR32RegisterClass);
11453 return std::make_pair(0U, X86::GR64RegisterClass);
11454 case 'R': // LEGACY_REGS
11456 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
11457 if (VT == MVT::i16)
11458 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
11459 if (VT == MVT::i32 || !Subtarget->is64Bit())
11460 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
11461 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
11462 case 'f': // FP Stack registers.
11463 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
11464 // value to the correct fpstack register class.
11465 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
11466 return std::make_pair(0U, X86::RFP32RegisterClass);
11467 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
11468 return std::make_pair(0U, X86::RFP64RegisterClass);
11469 return std::make_pair(0U, X86::RFP80RegisterClass);
11470 case 'y': // MMX_REGS if MMX allowed.
11471 if (!Subtarget->hasMMX()) break;
11472 return std::make_pair(0U, X86::VR64RegisterClass);
11473 case 'Y': // SSE_REGS if SSE2 allowed
11474 if (!Subtarget->hasSSE2()) break;
11476 case 'x': // SSE_REGS if SSE1 allowed
11477 if (!Subtarget->hasSSE1()) break;
11479 switch (VT.getSimpleVT().SimpleTy) {
11481 // Scalar SSE types.
11484 return std::make_pair(0U, X86::FR32RegisterClass);
11487 return std::make_pair(0U, X86::FR64RegisterClass);
11495 return std::make_pair(0U, X86::VR128RegisterClass);
11501 // Use the default implementation in TargetLowering to convert the register
11502 // constraint into a member of a register class.
11503 std::pair<unsigned, const TargetRegisterClass*> Res;
11504 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
11506 // Not found as a standard register?
11507 if (Res.second == 0) {
11508 // Map st(0) -> st(7) -> ST0
11509 if (Constraint.size() == 7 && Constraint[0] == '{' &&
11510 tolower(Constraint[1]) == 's' &&
11511 tolower(Constraint[2]) == 't' &&
11512 Constraint[3] == '(' &&
11513 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
11514 Constraint[5] == ')' &&
11515 Constraint[6] == '}') {
11517 Res.first = X86::ST0+Constraint[4]-'0';
11518 Res.second = X86::RFP80RegisterClass;
11522 // GCC allows "st(0)" to be called just plain "st".
11523 if (StringRef("{st}").equals_lower(Constraint)) {
11524 Res.first = X86::ST0;
11525 Res.second = X86::RFP80RegisterClass;
11530 if (StringRef("{flags}").equals_lower(Constraint)) {
11531 Res.first = X86::EFLAGS;
11532 Res.second = X86::CCRRegisterClass;
11536 // 'A' means EAX + EDX.
11537 if (Constraint == "A") {
11538 Res.first = X86::EAX;
11539 Res.second = X86::GR32_ADRegisterClass;
11545 // Otherwise, check to see if this is a register class of the wrong value
11546 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
11547 // turn into {ax},{dx}.
11548 if (Res.second->hasType(VT))
11549 return Res; // Correct type already, nothing to do.
11551 // All of the single-register GCC register classes map their values onto
11552 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
11553 // really want an 8-bit or 32-bit register, map to the appropriate register
11554 // class and return the appropriate register.
11555 if (Res.second == X86::GR16RegisterClass) {
11556 if (VT == MVT::i8) {
11557 unsigned DestReg = 0;
11558 switch (Res.first) {
11560 case X86::AX: DestReg = X86::AL; break;
11561 case X86::DX: DestReg = X86::DL; break;
11562 case X86::CX: DestReg = X86::CL; break;
11563 case X86::BX: DestReg = X86::BL; break;
11566 Res.first = DestReg;
11567 Res.second = X86::GR8RegisterClass;
11569 } else if (VT == MVT::i32) {
11570 unsigned DestReg = 0;
11571 switch (Res.first) {
11573 case X86::AX: DestReg = X86::EAX; break;
11574 case X86::DX: DestReg = X86::EDX; break;
11575 case X86::CX: DestReg = X86::ECX; break;
11576 case X86::BX: DestReg = X86::EBX; break;
11577 case X86::SI: DestReg = X86::ESI; break;
11578 case X86::DI: DestReg = X86::EDI; break;
11579 case X86::BP: DestReg = X86::EBP; break;
11580 case X86::SP: DestReg = X86::ESP; break;
11583 Res.first = DestReg;
11584 Res.second = X86::GR32RegisterClass;
11586 } else if (VT == MVT::i64) {
11587 unsigned DestReg = 0;
11588 switch (Res.first) {
11590 case X86::AX: DestReg = X86::RAX; break;
11591 case X86::DX: DestReg = X86::RDX; break;
11592 case X86::CX: DestReg = X86::RCX; break;
11593 case X86::BX: DestReg = X86::RBX; break;
11594 case X86::SI: DestReg = X86::RSI; break;
11595 case X86::DI: DestReg = X86::RDI; break;
11596 case X86::BP: DestReg = X86::RBP; break;
11597 case X86::SP: DestReg = X86::RSP; break;
11600 Res.first = DestReg;
11601 Res.second = X86::GR64RegisterClass;
11604 } else if (Res.second == X86::FR32RegisterClass ||
11605 Res.second == X86::FR64RegisterClass ||
11606 Res.second == X86::VR128RegisterClass) {
11607 // Handle references to XMM physical registers that got mapped into the
11608 // wrong class. This can happen with constraints like {xmm0} where the
11609 // target independent register mapper will just pick the first match it can
11610 // find, ignoring the required type.
11611 if (VT == MVT::f32)
11612 Res.second = X86::FR32RegisterClass;
11613 else if (VT == MVT::f64)
11614 Res.second = X86::FR64RegisterClass;
11615 else if (X86::VR128RegisterClass->hasType(VT))
11616 Res.second = X86::VR128RegisterClass;