1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/GlobalAlias.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/VectorExtras.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Forward declarations.
51 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
54 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
55 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
56 default: llvm_unreachable("unknown subtarget type");
57 case X86Subtarget::isDarwin:
58 return new TargetLoweringObjectFileMachO();
59 case X86Subtarget::isELF:
60 return new TargetLoweringObjectFileELF();
61 case X86Subtarget::isMingw:
62 case X86Subtarget::isCygwin:
63 case X86Subtarget::isWindows:
64 return new TargetLoweringObjectFileCOFF();
69 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
70 : TargetLowering(TM, createTLOF(TM)) {
71 Subtarget = &TM.getSubtarget<X86Subtarget>();
72 X86ScalarSSEf64 = Subtarget->hasSSE2();
73 X86ScalarSSEf32 = Subtarget->hasSSE1();
74 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
76 RegInfo = TM.getRegisterInfo();
79 // Set up the TargetLowering object.
81 // X86 is weird, it always uses i8 for shift amounts and setcc results.
82 setShiftAmountType(MVT::i8);
83 setBooleanContents(ZeroOrOneBooleanContent);
84 setSchedulingPreference(SchedulingForRegPressure);
85 setStackPointerRegisterToSaveRestore(X86StackPtr);
87 if (Subtarget->isTargetDarwin()) {
88 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
89 setUseUnderscoreSetJmp(false);
90 setUseUnderscoreLongJmp(false);
91 } else if (Subtarget->isTargetMingw()) {
92 // MS runtime is weird: it exports _setjmp, but longjmp!
93 setUseUnderscoreSetJmp(true);
94 setUseUnderscoreLongJmp(false);
96 setUseUnderscoreSetJmp(true);
97 setUseUnderscoreLongJmp(true);
100 // Set up the register classes.
101 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
102 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
103 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
104 if (Subtarget->is64Bit())
105 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
107 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
109 // We don't accept any truncstore of integer registers.
110 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
111 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
112 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
113 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
114 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
115 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
117 // SETOEQ and SETUNE require checking two conditions.
118 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
119 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
120 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
121 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
122 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
123 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
125 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
127 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
128 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
129 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
131 if (Subtarget->is64Bit()) {
132 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
133 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
134 } else if (!UseSoftFloat) {
135 if (X86ScalarSSEf64) {
136 // We have an impenetrably clever algorithm for ui64->double only.
137 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
139 // We have an algorithm for SSE2, and we turn this into a 64-bit
140 // FILD for other targets.
141 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
144 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
146 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
147 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
150 // SSE has no i16 to fp conversion, only i32
151 if (X86ScalarSSEf32) {
152 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
153 // f32 and f64 cases are Legal, f80 case is not
154 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
156 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
157 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
161 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
164 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
165 // are Legal, f80 is custom lowered.
166 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
169 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
171 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
172 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
174 if (X86ScalarSSEf32) {
175 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
176 // f32 and f64 cases are Legal, f80 case is not
177 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
179 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
180 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
183 // Handle FP_TO_UINT by promoting the destination to a larger signed
185 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
186 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
187 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
189 if (Subtarget->is64Bit()) {
190 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
191 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
192 } else if (!UseSoftFloat) {
193 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
194 // Expand FP_TO_UINT into a select.
195 // FIXME: We would like to use a Custom expander here eventually to do
196 // the optimal thing for SSE vs. the default expansion in the legalizer.
197 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
199 // With SSE3 we can use fisttpll to convert to a signed i64; without
200 // SSE, we're stuck with a fistpll.
201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
204 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
205 if (!X86ScalarSSEf64) {
206 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
207 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
210 // Scalar integer divide and remainder are lowered to use operations that
211 // produce two results, to match the available instructions. This exposes
212 // the two-result form to trivial CSE, which is able to combine x/y and x%y
213 // into a single instruction.
215 // Scalar integer multiply-high is also lowered to use two-result
216 // operations, to match the available instructions. However, plain multiply
217 // (low) operations are left as Legal, as there are single-result
218 // instructions for this in x86. Using the two-result multiply instructions
219 // when both high and low results are needed must be arranged by dagcombine.
220 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
221 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
222 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
223 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
224 setOperationAction(ISD::SREM , MVT::i8 , Expand);
225 setOperationAction(ISD::UREM , MVT::i8 , Expand);
226 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
227 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
228 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
229 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
230 setOperationAction(ISD::SREM , MVT::i16 , Expand);
231 setOperationAction(ISD::UREM , MVT::i16 , Expand);
232 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
233 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
234 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
235 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
236 setOperationAction(ISD::SREM , MVT::i32 , Expand);
237 setOperationAction(ISD::UREM , MVT::i32 , Expand);
238 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
239 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
240 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
241 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
242 setOperationAction(ISD::SREM , MVT::i64 , Expand);
243 setOperationAction(ISD::UREM , MVT::i64 , Expand);
245 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
246 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
247 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
248 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
249 if (Subtarget->is64Bit())
250 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
251 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
252 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
253 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
254 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
255 setOperationAction(ISD::FREM , MVT::f32 , Expand);
256 setOperationAction(ISD::FREM , MVT::f64 , Expand);
257 setOperationAction(ISD::FREM , MVT::f80 , Expand);
258 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
260 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
261 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
262 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
263 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
264 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
265 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
266 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
267 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
268 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
269 if (Subtarget->is64Bit()) {
270 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
271 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
272 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
275 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
276 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
278 // These should be promoted to a larger select which is supported.
279 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
280 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
281 // X86 wants to expand cmov itself.
282 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
283 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
284 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
285 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
286 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
287 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
288 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
289 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
290 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
291 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
292 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
293 if (Subtarget->is64Bit()) {
294 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
295 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
297 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
300 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
301 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
302 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
303 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
304 if (Subtarget->is64Bit())
305 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
306 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
307 if (Subtarget->is64Bit()) {
308 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
309 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
310 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
311 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
313 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
314 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
315 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
316 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
319 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
320 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
323 if (Subtarget->hasSSE1())
324 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
326 if (!Subtarget->hasSSE2())
327 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
329 // Expand certain atomics
330 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
331 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
332 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
333 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
335 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
336 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
337 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
338 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
340 if (!Subtarget->is64Bit()) {
341 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
342 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
343 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
344 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
345 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
346 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
347 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
350 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
351 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
352 // FIXME - use subtarget debug flags
353 if (!Subtarget->isTargetDarwin() &&
354 !Subtarget->isTargetELF() &&
355 !Subtarget->isTargetCygMing()) {
356 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
357 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
360 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
361 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
362 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
363 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
364 if (Subtarget->is64Bit()) {
365 setExceptionPointerRegister(X86::RAX);
366 setExceptionSelectorRegister(X86::RDX);
368 setExceptionPointerRegister(X86::EAX);
369 setExceptionSelectorRegister(X86::EDX);
371 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
372 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
374 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
376 setOperationAction(ISD::TRAP, MVT::Other, Legal);
378 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
379 setOperationAction(ISD::VASTART , MVT::Other, Custom);
380 setOperationAction(ISD::VAEND , MVT::Other, Expand);
381 if (Subtarget->is64Bit()) {
382 setOperationAction(ISD::VAARG , MVT::Other, Custom);
383 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
385 setOperationAction(ISD::VAARG , MVT::Other, Expand);
386 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
389 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
390 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
391 if (Subtarget->is64Bit())
392 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
393 if (Subtarget->isTargetCygMing())
394 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
396 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
398 if (!UseSoftFloat && X86ScalarSSEf64) {
399 // f32 and f64 use SSE.
400 // Set up the FP register classes.
401 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
402 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
404 // Use ANDPD to simulate FABS.
405 setOperationAction(ISD::FABS , MVT::f64, Custom);
406 setOperationAction(ISD::FABS , MVT::f32, Custom);
408 // Use XORP to simulate FNEG.
409 setOperationAction(ISD::FNEG , MVT::f64, Custom);
410 setOperationAction(ISD::FNEG , MVT::f32, Custom);
412 // Use ANDPD and ORPD to simulate FCOPYSIGN.
413 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
414 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
416 // We don't support sin/cos/fmod
417 setOperationAction(ISD::FSIN , MVT::f64, Expand);
418 setOperationAction(ISD::FCOS , MVT::f64, Expand);
419 setOperationAction(ISD::FSIN , MVT::f32, Expand);
420 setOperationAction(ISD::FCOS , MVT::f32, Expand);
422 // Expand FP immediates into loads from the stack, except for the special
424 addLegalFPImmediate(APFloat(+0.0)); // xorpd
425 addLegalFPImmediate(APFloat(+0.0f)); // xorps
426 } else if (!UseSoftFloat && X86ScalarSSEf32) {
427 // Use SSE for f32, x87 for f64.
428 // Set up the FP register classes.
429 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
430 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
432 // Use ANDPS to simulate FABS.
433 setOperationAction(ISD::FABS , MVT::f32, Custom);
435 // Use XORP to simulate FNEG.
436 setOperationAction(ISD::FNEG , MVT::f32, Custom);
438 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
440 // Use ANDPS and ORPS to simulate FCOPYSIGN.
441 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
442 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
444 // We don't support sin/cos/fmod
445 setOperationAction(ISD::FSIN , MVT::f32, Expand);
446 setOperationAction(ISD::FCOS , MVT::f32, Expand);
448 // Special cases we handle for FP constants.
449 addLegalFPImmediate(APFloat(+0.0f)); // xorps
450 addLegalFPImmediate(APFloat(+0.0)); // FLD0
451 addLegalFPImmediate(APFloat(+1.0)); // FLD1
452 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
453 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
456 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
457 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
459 } else if (!UseSoftFloat) {
460 // f32 and f64 in x87.
461 // Set up the FP register classes.
462 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
463 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
465 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
466 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
467 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
471 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
472 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
474 addLegalFPImmediate(APFloat(+0.0)); // FLD0
475 addLegalFPImmediate(APFloat(+1.0)); // FLD1
476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
478 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
479 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
480 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
481 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
484 // Long double always uses X87.
486 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
487 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
488 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
491 APFloat TmpFlt(+0.0);
492 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
494 addLegalFPImmediate(TmpFlt); // FLD0
496 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
497 APFloat TmpFlt2(+1.0);
498 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
500 addLegalFPImmediate(TmpFlt2); // FLD1
501 TmpFlt2.changeSign();
502 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
506 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
507 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
511 // Always use a library call for pow.
512 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
513 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
514 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
516 setOperationAction(ISD::FLOG, MVT::f80, Expand);
517 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
518 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
519 setOperationAction(ISD::FEXP, MVT::f80, Expand);
520 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
522 // First set operation action for all vector types to either promote
523 // (for widening) or expand (for scalarization). Then we will selectively
524 // turn on ones that can be effectively codegen'd.
525 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
526 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
527 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
542 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
543 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
577 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
578 // with -msoft-float, disable use of MMX as well.
579 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
580 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
581 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
582 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
586 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
587 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
588 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
589 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
591 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
592 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
593 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
594 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
596 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
597 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
599 setOperationAction(ISD::AND, MVT::v8i8, Promote);
600 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
601 setOperationAction(ISD::AND, MVT::v4i16, Promote);
602 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
603 setOperationAction(ISD::AND, MVT::v2i32, Promote);
604 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
605 setOperationAction(ISD::AND, MVT::v1i64, Legal);
607 setOperationAction(ISD::OR, MVT::v8i8, Promote);
608 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
609 setOperationAction(ISD::OR, MVT::v4i16, Promote);
610 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
611 setOperationAction(ISD::OR, MVT::v2i32, Promote);
612 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
613 setOperationAction(ISD::OR, MVT::v1i64, Legal);
615 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
616 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
617 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
618 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
619 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
620 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
621 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
623 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
624 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
625 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
626 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
627 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
628 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
629 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
630 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
631 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
633 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
634 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
635 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
636 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
640 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
641 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
644 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
645 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
646 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
649 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
651 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
652 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
653 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
654 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
655 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
656 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
657 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
658 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
659 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
662 if (!UseSoftFloat && Subtarget->hasSSE1()) {
663 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
665 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
666 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
667 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
668 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
669 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
670 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
671 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
675 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
676 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
679 if (!UseSoftFloat && Subtarget->hasSSE2()) {
680 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
682 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
683 // registers cannot be used even for integer operations.
684 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
685 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
686 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
687 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
689 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
690 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
691 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
692 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
693 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
694 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
695 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
696 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
697 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
698 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
699 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
700 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
701 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
702 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
703 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
704 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
707 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
708 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
711 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
712 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
714 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
715 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
717 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
718 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
719 EVT VT = (MVT::SimpleValueType)i;
720 // Do not attempt to custom lower non-power-of-2 vectors
721 if (!isPowerOf2_32(VT.getVectorNumElements()))
723 // Do not attempt to custom lower non-128-bit vectors
724 if (!VT.is128BitVector())
726 setOperationAction(ISD::BUILD_VECTOR,
727 VT.getSimpleVT().SimpleTy, Custom);
728 setOperationAction(ISD::VECTOR_SHUFFLE,
729 VT.getSimpleVT().SimpleTy, Custom);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
731 VT.getSimpleVT().SimpleTy, Custom);
734 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
735 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
736 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
737 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
738 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
739 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
741 if (Subtarget->is64Bit()) {
742 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
743 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
746 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
747 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
748 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
751 // Do not attempt to promote non-128-bit vectors
752 if (!VT.is128BitVector()) {
755 setOperationAction(ISD::AND, SVT, Promote);
756 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
757 setOperationAction(ISD::OR, SVT, Promote);
758 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
759 setOperationAction(ISD::XOR, SVT, Promote);
760 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
761 setOperationAction(ISD::LOAD, SVT, Promote);
762 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
763 setOperationAction(ISD::SELECT, SVT, Promote);
764 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
767 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
769 // Custom lower v2i64 and v2f64 selects.
770 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
771 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
772 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
773 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
775 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
776 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
777 if (!DisableMMX && Subtarget->hasMMX()) {
778 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
779 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
783 if (Subtarget->hasSSE41()) {
784 // FIXME: Do we need to handle scalar-to-vector here?
785 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
787 // i8 and i16 vectors are custom , because the source register and source
788 // source memory operand types are not the same width. f32 vectors are
789 // custom since the immediate controlling the insert encodes additional
791 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
793 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
794 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
797 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
798 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
799 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
801 if (Subtarget->is64Bit()) {
802 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
803 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
807 if (Subtarget->hasSSE42()) {
808 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
811 if (!UseSoftFloat && Subtarget->hasAVX()) {
812 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
813 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
814 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
815 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
817 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
818 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
819 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
820 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
821 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
822 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
823 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
824 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
825 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
826 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
827 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
828 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
829 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
830 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
831 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
833 // Operations to consider commented out -v16i16 v32i8
834 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
835 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
836 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
837 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
838 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
839 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
840 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
841 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
842 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
843 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
844 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
845 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
846 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
847 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
849 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
850 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
851 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
852 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
854 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
855 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
856 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
857 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
858 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
860 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
861 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
862 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
868 // Not sure we want to do this since there are no 256-bit integer
871 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
872 // This includes 256-bit vectors
873 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
876 // Do not attempt to custom lower non-power-of-2 vectors
877 if (!isPowerOf2_32(VT.getVectorNumElements()))
880 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
881 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
885 if (Subtarget->is64Bit()) {
886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
887 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
892 // Not sure we want to do this since there are no 256-bit integer
895 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
896 // Including 256-bit vectors
897 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
898 EVT VT = (MVT::SimpleValueType)i;
900 if (!VT.is256BitVector()) {
903 setOperationAction(ISD::AND, VT, Promote);
904 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
905 setOperationAction(ISD::OR, VT, Promote);
906 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
907 setOperationAction(ISD::XOR, VT, Promote);
908 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
909 setOperationAction(ISD::LOAD, VT, Promote);
910 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
911 setOperationAction(ISD::SELECT, VT, Promote);
912 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
915 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
919 // We want to custom lower some of our intrinsics.
920 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
922 // Add/Sub/Mul with overflow operations are custom lowered.
923 setOperationAction(ISD::SADDO, MVT::i32, Custom);
924 setOperationAction(ISD::SADDO, MVT::i64, Custom);
925 setOperationAction(ISD::UADDO, MVT::i32, Custom);
926 setOperationAction(ISD::UADDO, MVT::i64, Custom);
927 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
928 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
929 setOperationAction(ISD::USUBO, MVT::i32, Custom);
930 setOperationAction(ISD::USUBO, MVT::i64, Custom);
931 setOperationAction(ISD::SMULO, MVT::i32, Custom);
932 setOperationAction(ISD::SMULO, MVT::i64, Custom);
934 if (!Subtarget->is64Bit()) {
935 // These libcalls are not available in 32-bit.
936 setLibcallName(RTLIB::SHL_I128, 0);
937 setLibcallName(RTLIB::SRL_I128, 0);
938 setLibcallName(RTLIB::SRA_I128, 0);
941 // We have target-specific dag combine patterns for the following nodes:
942 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
943 setTargetDAGCombine(ISD::BUILD_VECTOR);
944 setTargetDAGCombine(ISD::SELECT);
945 setTargetDAGCombine(ISD::SHL);
946 setTargetDAGCombine(ISD::SRA);
947 setTargetDAGCombine(ISD::SRL);
948 setTargetDAGCombine(ISD::STORE);
949 setTargetDAGCombine(ISD::MEMBARRIER);
950 if (Subtarget->is64Bit())
951 setTargetDAGCombine(ISD::MUL);
953 computeRegisterProperties();
955 // FIXME: These should be based on subtarget info. Plus, the values should
956 // be smaller when we are in optimizing for size mode.
957 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
958 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
959 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
960 allowUnalignedMemoryAccesses = true; // x86 supports it!
961 setPrefLoopAlignment(16);
962 benefitFromCodePlacementOpt = true;
966 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
971 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
972 /// the desired ByVal argument alignment.
973 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
976 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
977 if (VTy->getBitWidth() == 128)
979 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
980 unsigned EltAlign = 0;
981 getMaxByValAlign(ATy->getElementType(), EltAlign);
982 if (EltAlign > MaxAlign)
984 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
985 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
986 unsigned EltAlign = 0;
987 getMaxByValAlign(STy->getElementType(i), EltAlign);
988 if (EltAlign > MaxAlign)
997 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
998 /// function arguments in the caller parameter area. For X86, aggregates
999 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1000 /// are at 4-byte boundaries.
1001 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1002 if (Subtarget->is64Bit()) {
1003 // Max of 8 and alignment of type.
1004 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1011 if (Subtarget->hasSSE1())
1012 getMaxByValAlign(Ty, Align);
1016 /// getOptimalMemOpType - Returns the target specific optimal type for load
1017 /// and store operations as a result of memset, memcpy, and memmove
1018 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1021 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1022 bool isSrcConst, bool isSrcStr,
1023 SelectionDAG &DAG) const {
1024 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1025 // linux. This is because the stack realignment code can't handle certain
1026 // cases like PR2962. This should be removed when PR2962 is fixed.
1027 const Function *F = DAG.getMachineFunction().getFunction();
1028 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1029 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1030 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1032 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1035 if (Subtarget->is64Bit() && Size >= 8)
1040 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1042 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1043 SelectionDAG &DAG) const {
1044 if (usesGlobalOffsetTable())
1045 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1046 if (!Subtarget->is64Bit())
1047 // This doesn't have DebugLoc associated with it, but is not really the
1048 // same as a Register.
1049 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1054 /// getFunctionAlignment - Return the Log2 alignment of this function.
1055 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1056 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
1059 //===----------------------------------------------------------------------===//
1060 // Return Value Calling Convention Implementation
1061 //===----------------------------------------------------------------------===//
1063 #include "X86GenCallingConv.inc"
1066 X86TargetLowering::LowerReturn(SDValue Chain,
1067 unsigned CallConv, bool isVarArg,
1068 const SmallVectorImpl<ISD::OutputArg> &Outs,
1069 DebugLoc dl, SelectionDAG &DAG) {
1071 SmallVector<CCValAssign, 16> RVLocs;
1072 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1073 RVLocs, *DAG.getContext());
1074 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1076 // If this is the first return lowered for this function, add the regs to the
1077 // liveout set for the function.
1078 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1079 for (unsigned i = 0; i != RVLocs.size(); ++i)
1080 if (RVLocs[i].isRegLoc())
1081 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1086 SmallVector<SDValue, 6> RetOps;
1087 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1088 // Operand #1 = Bytes To Pop
1089 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1091 // Copy the result values into the output registers.
1092 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1093 CCValAssign &VA = RVLocs[i];
1094 assert(VA.isRegLoc() && "Can only return in registers!");
1095 SDValue ValToCopy = Outs[i].Val;
1097 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1098 // the RET instruction and handled by the FP Stackifier.
1099 if (VA.getLocReg() == X86::ST0 ||
1100 VA.getLocReg() == X86::ST1) {
1101 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1102 // change the value to the FP stack register class.
1103 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1104 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1105 RetOps.push_back(ValToCopy);
1106 // Don't emit a copytoreg.
1110 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1111 // which is returned in RAX / RDX.
1112 if (Subtarget->is64Bit()) {
1113 EVT ValVT = ValToCopy.getValueType();
1114 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1115 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1116 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1117 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1121 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1122 Flag = Chain.getValue(1);
1125 // The x86-64 ABI for returning structs by value requires that we copy
1126 // the sret argument into %rax for the return. We saved the argument into
1127 // a virtual register in the entry block, so now we copy the value out
1129 if (Subtarget->is64Bit() &&
1130 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1131 MachineFunction &MF = DAG.getMachineFunction();
1132 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1133 unsigned Reg = FuncInfo->getSRetReturnReg();
1135 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1136 FuncInfo->setSRetReturnReg(Reg);
1138 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1140 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1141 Flag = Chain.getValue(1);
1144 RetOps[0] = Chain; // Update chain.
1146 // Add the flag if we have it.
1148 RetOps.push_back(Flag);
1150 return DAG.getNode(X86ISD::RET_FLAG, dl,
1151 MVT::Other, &RetOps[0], RetOps.size());
1154 /// LowerCallResult - Lower the result values of a call into the
1155 /// appropriate copies out of appropriate physical registers.
1158 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1159 unsigned CallConv, bool isVarArg,
1160 const SmallVectorImpl<ISD::InputArg> &Ins,
1161 DebugLoc dl, SelectionDAG &DAG,
1162 SmallVectorImpl<SDValue> &InVals) {
1164 // Assign locations to each value returned by this call.
1165 SmallVector<CCValAssign, 16> RVLocs;
1166 bool Is64Bit = Subtarget->is64Bit();
1167 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1168 RVLocs, *DAG.getContext());
1169 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1171 // Copy all of the result registers out of their specified physreg.
1172 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1173 CCValAssign &VA = RVLocs[i];
1174 EVT CopyVT = VA.getValVT();
1176 // If this is x86-64, and we disabled SSE, we can't return FP values
1177 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1178 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1179 llvm_report_error("SSE register return with SSE disabled");
1182 // If this is a call to a function that returns an fp value on the floating
1183 // point stack, but where we prefer to use the value in xmm registers, copy
1184 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1185 if ((VA.getLocReg() == X86::ST0 ||
1186 VA.getLocReg() == X86::ST1) &&
1187 isScalarFPTypeInSSEReg(VA.getValVT())) {
1192 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1193 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1194 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1195 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1196 MVT::v2i64, InFlag).getValue(1);
1197 Val = Chain.getValue(0);
1198 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1199 Val, DAG.getConstant(0, MVT::i64));
1201 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1202 MVT::i64, InFlag).getValue(1);
1203 Val = Chain.getValue(0);
1205 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1207 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1208 CopyVT, InFlag).getValue(1);
1209 Val = Chain.getValue(0);
1211 InFlag = Chain.getValue(2);
1213 if (CopyVT != VA.getValVT()) {
1214 // Round the F80 the right size, which also moves to the appropriate xmm
1216 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1217 // This truncation won't change the value.
1218 DAG.getIntPtrConstant(1));
1221 InVals.push_back(Val);
1228 //===----------------------------------------------------------------------===//
1229 // C & StdCall & Fast Calling Convention implementation
1230 //===----------------------------------------------------------------------===//
1231 // StdCall calling convention seems to be standard for many Windows' API
1232 // routines and around. It differs from C calling convention just a little:
1233 // callee should clean up the stack, not caller. Symbols should be also
1234 // decorated in some fancy way :) It doesn't support any vector arguments.
1235 // For info on fast calling convention see Fast Calling Convention (tail call)
1236 // implementation LowerX86_32FastCCCallTo.
1238 /// CallIsStructReturn - Determines whether a call uses struct return
1240 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1244 return Outs[0].Flags.isSRet();
1247 /// ArgsAreStructReturn - Determines whether a function uses struct
1248 /// return semantics.
1250 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1254 return Ins[0].Flags.isSRet();
1257 /// IsCalleePop - Determines whether the callee is required to pop its
1258 /// own arguments. Callee pop is necessary to support tail calls.
1259 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1263 switch (CallingConv) {
1266 case CallingConv::X86_StdCall:
1267 return !Subtarget->is64Bit();
1268 case CallingConv::X86_FastCall:
1269 return !Subtarget->is64Bit();
1270 case CallingConv::Fast:
1271 return PerformTailCallOpt;
1275 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1276 /// given CallingConvention value.
1277 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1278 if (Subtarget->is64Bit()) {
1279 if (Subtarget->isTargetWin64())
1280 return CC_X86_Win64_C;
1285 if (CC == CallingConv::X86_FastCall)
1286 return CC_X86_32_FastCall;
1287 else if (CC == CallingConv::Fast)
1288 return CC_X86_32_FastCC;
1293 /// NameDecorationForCallConv - Selects the appropriate decoration to
1294 /// apply to a MachineFunction containing a given calling convention.
1296 X86TargetLowering::NameDecorationForCallConv(unsigned CallConv) {
1297 if (CallConv == CallingConv::X86_FastCall)
1299 else if (CallConv == CallingConv::X86_StdCall)
1305 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1306 /// by "Src" to address "Dst" with size and alignment information specified by
1307 /// the specific parameter attribute. The copy will be passed as a byval
1308 /// function parameter.
1310 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1311 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1313 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1314 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1315 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1319 X86TargetLowering::LowerMemArgument(SDValue Chain,
1321 const SmallVectorImpl<ISD::InputArg> &Ins,
1322 DebugLoc dl, SelectionDAG &DAG,
1323 const CCValAssign &VA,
1324 MachineFrameInfo *MFI,
1327 // Create the nodes corresponding to a load from this parameter slot.
1328 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1329 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1330 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1332 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1333 // changed with more analysis.
1334 // In case of tail call optimization mark all arguments mutable. Since they
1335 // could be overwritten by lowering of arguments in case of a tail call.
1336 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1337 VA.getLocMemOffset(), isImmutable);
1338 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1339 if (Flags.isByVal())
1341 return DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1342 PseudoSourceValue::getFixedStack(FI), 0);
1346 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1349 const SmallVectorImpl<ISD::InputArg> &Ins,
1352 SmallVectorImpl<SDValue> &InVals) {
1354 MachineFunction &MF = DAG.getMachineFunction();
1355 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1357 const Function* Fn = MF.getFunction();
1358 if (Fn->hasExternalLinkage() &&
1359 Subtarget->isTargetCygMing() &&
1360 Fn->getName() == "main")
1361 FuncInfo->setForceFramePointer(true);
1363 // Decorate the function name.
1364 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1366 MachineFrameInfo *MFI = MF.getFrameInfo();
1367 bool Is64Bit = Subtarget->is64Bit();
1368 bool IsWin64 = Subtarget->isTargetWin64();
1370 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1371 "Var args not supported with calling convention fastcc");
1373 // Assign locations to all of the incoming arguments.
1374 SmallVector<CCValAssign, 16> ArgLocs;
1375 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1376 ArgLocs, *DAG.getContext());
1377 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1379 unsigned LastVal = ~0U;
1381 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1382 CCValAssign &VA = ArgLocs[i];
1383 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1385 assert(VA.getValNo() != LastVal &&
1386 "Don't support value assigned to multiple locs yet");
1387 LastVal = VA.getValNo();
1389 if (VA.isRegLoc()) {
1390 EVT RegVT = VA.getLocVT();
1391 TargetRegisterClass *RC = NULL;
1392 if (RegVT == MVT::i32)
1393 RC = X86::GR32RegisterClass;
1394 else if (Is64Bit && RegVT == MVT::i64)
1395 RC = X86::GR64RegisterClass;
1396 else if (RegVT == MVT::f32)
1397 RC = X86::FR32RegisterClass;
1398 else if (RegVT == MVT::f64)
1399 RC = X86::FR64RegisterClass;
1400 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1401 RC = X86::VR128RegisterClass;
1402 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1403 RC = X86::VR64RegisterClass;
1405 llvm_unreachable("Unknown argument type!");
1407 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1408 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1410 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1411 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1413 if (VA.getLocInfo() == CCValAssign::SExt)
1414 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1415 DAG.getValueType(VA.getValVT()));
1416 else if (VA.getLocInfo() == CCValAssign::ZExt)
1417 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1418 DAG.getValueType(VA.getValVT()));
1419 else if (VA.getLocInfo() == CCValAssign::BCvt)
1420 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1422 if (VA.isExtInLoc()) {
1423 // Handle MMX values passed in XMM regs.
1424 if (RegVT.isVector()) {
1425 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1426 ArgValue, DAG.getConstant(0, MVT::i64));
1427 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1429 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1432 assert(VA.isMemLoc());
1433 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1436 // If value is passed via pointer - do a load.
1437 if (VA.getLocInfo() == CCValAssign::Indirect)
1438 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1440 InVals.push_back(ArgValue);
1443 // The x86-64 ABI for returning structs by value requires that we copy
1444 // the sret argument into %rax for the return. Save the argument into
1445 // a virtual register so that we can access it from the return points.
1446 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1447 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1448 unsigned Reg = FuncInfo->getSRetReturnReg();
1450 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1451 FuncInfo->setSRetReturnReg(Reg);
1453 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1454 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1457 unsigned StackSize = CCInfo.getNextStackOffset();
1458 // align stack specially for tail calls
1459 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1460 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1462 // If the function takes variable number of arguments, make a frame index for
1463 // the start of the first vararg value... for expansion of llvm.va_start.
1465 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1466 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1469 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1471 // FIXME: We should really autogenerate these arrays
1472 static const unsigned GPR64ArgRegsWin64[] = {
1473 X86::RCX, X86::RDX, X86::R8, X86::R9
1475 static const unsigned XMMArgRegsWin64[] = {
1476 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1478 static const unsigned GPR64ArgRegs64Bit[] = {
1479 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1481 static const unsigned XMMArgRegs64Bit[] = {
1482 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1483 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1485 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1488 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1489 GPR64ArgRegs = GPR64ArgRegsWin64;
1490 XMMArgRegs = XMMArgRegsWin64;
1492 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1493 GPR64ArgRegs = GPR64ArgRegs64Bit;
1494 XMMArgRegs = XMMArgRegs64Bit;
1496 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1498 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1501 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1502 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1503 "SSE register cannot be used when SSE is disabled!");
1504 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1505 "SSE register cannot be used when SSE is disabled!");
1506 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1507 // Kernel mode asks for SSE to be disabled, so don't push them
1509 TotalNumXMMRegs = 0;
1511 // For X86-64, if there are vararg parameters that are passed via
1512 // registers, then we must store them to their spots on the stack so they
1513 // may be loaded by deferencing the result of va_next.
1514 VarArgsGPOffset = NumIntRegs * 8;
1515 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1516 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1517 TotalNumXMMRegs * 16, 16);
1519 // Store the integer parameter registers.
1520 SmallVector<SDValue, 8> MemOps;
1521 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1522 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1523 DAG.getIntPtrConstant(VarArgsGPOffset));
1524 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1525 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1526 X86::GR64RegisterClass);
1527 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1529 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1530 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1531 MemOps.push_back(Store);
1532 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1533 DAG.getIntPtrConstant(8));
1536 // Now store the XMM (fp + vector) parameter registers.
1537 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1538 DAG.getIntPtrConstant(VarArgsFPOffset));
1539 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1540 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1541 X86::VR128RegisterClass);
1542 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1544 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1545 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1546 MemOps.push_back(Store);
1547 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1548 DAG.getIntPtrConstant(16));
1550 if (!MemOps.empty())
1551 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1552 &MemOps[0], MemOps.size());
1556 // Some CCs need callee pop.
1557 if (IsCalleePop(isVarArg, CallConv)) {
1558 BytesToPopOnReturn = StackSize; // Callee pops everything.
1559 BytesCallerReserves = 0;
1561 BytesToPopOnReturn = 0; // Callee pops nothing.
1562 // If this is an sret function, the return should pop the hidden pointer.
1563 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1564 BytesToPopOnReturn = 4;
1565 BytesCallerReserves = StackSize;
1569 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1570 if (CallConv == CallingConv::X86_FastCall)
1571 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1574 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1580 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1581 SDValue StackPtr, SDValue Arg,
1582 DebugLoc dl, SelectionDAG &DAG,
1583 const CCValAssign &VA,
1584 ISD::ArgFlagsTy Flags) {
1585 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1586 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1587 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1588 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1589 if (Flags.isByVal()) {
1590 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1592 return DAG.getStore(Chain, dl, Arg, PtrOff,
1593 PseudoSourceValue::getStack(), LocMemOffset);
1596 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1597 /// optimization is performed and it is required.
1599 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1600 SDValue &OutRetAddr,
1606 if (!IsTailCall || FPDiff==0) return Chain;
1608 // Adjust the Return address stack slot.
1609 EVT VT = getPointerTy();
1610 OutRetAddr = getReturnAddressFrameIndex(DAG);
1612 // Load the "old" Return address.
1613 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1614 return SDValue(OutRetAddr.getNode(), 1);
1617 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1618 /// optimization is performed and it is required (FPDiff!=0).
1620 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1621 SDValue Chain, SDValue RetAddrFrIdx,
1622 bool Is64Bit, int FPDiff, DebugLoc dl) {
1623 // Store the return address to the appropriate stack slot.
1624 if (!FPDiff) return Chain;
1625 // Calculate the new stack slot for the return address.
1626 int SlotSize = Is64Bit ? 8 : 4;
1627 int NewReturnAddrFI =
1628 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1629 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1630 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1631 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1632 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1637 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1638 unsigned CallConv, bool isVarArg, bool isTailCall,
1639 const SmallVectorImpl<ISD::OutputArg> &Outs,
1640 const SmallVectorImpl<ISD::InputArg> &Ins,
1641 DebugLoc dl, SelectionDAG &DAG,
1642 SmallVectorImpl<SDValue> &InVals) {
1644 MachineFunction &MF = DAG.getMachineFunction();
1645 bool Is64Bit = Subtarget->is64Bit();
1646 bool IsStructRet = CallIsStructReturn(Outs);
1648 assert((!isTailCall ||
1649 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1650 "IsEligibleForTailCallOptimization missed a case!");
1651 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1652 "Var args not supported with calling convention fastcc");
1654 // Analyze operands of the call, assigning locations to each operand.
1655 SmallVector<CCValAssign, 16> ArgLocs;
1656 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1657 ArgLocs, *DAG.getContext());
1658 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1660 // Get a count of how many bytes are to be pushed on the stack.
1661 unsigned NumBytes = CCInfo.getNextStackOffset();
1662 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1663 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1667 // Lower arguments at fp - stackoffset + fpdiff.
1668 unsigned NumBytesCallerPushed =
1669 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1670 FPDiff = NumBytesCallerPushed - NumBytes;
1672 // Set the delta of movement of the returnaddr stackslot.
1673 // But only set if delta is greater than previous delta.
1674 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1675 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1678 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1680 SDValue RetAddrFrIdx;
1681 // Load return adress for tail calls.
1682 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1685 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1686 SmallVector<SDValue, 8> MemOpChains;
1689 // Walk the register/memloc assignments, inserting copies/loads. In the case
1690 // of tail call optimization arguments are handle later.
1691 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1692 CCValAssign &VA = ArgLocs[i];
1693 EVT RegVT = VA.getLocVT();
1694 SDValue Arg = Outs[i].Val;
1695 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1696 bool isByVal = Flags.isByVal();
1698 // Promote the value if needed.
1699 switch (VA.getLocInfo()) {
1700 default: llvm_unreachable("Unknown loc info!");
1701 case CCValAssign::Full: break;
1702 case CCValAssign::SExt:
1703 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1705 case CCValAssign::ZExt:
1706 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1708 case CCValAssign::AExt:
1709 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1710 // Special case: passing MMX values in XMM registers.
1711 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1712 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1713 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1715 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1717 case CCValAssign::BCvt:
1718 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1720 case CCValAssign::Indirect: {
1721 // Store the argument.
1722 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1723 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1724 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1725 PseudoSourceValue::getFixedStack(FI), 0);
1731 if (VA.isRegLoc()) {
1732 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1734 if (!isTailCall || (isTailCall && isByVal)) {
1735 assert(VA.isMemLoc());
1736 if (StackPtr.getNode() == 0)
1737 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1739 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1740 dl, DAG, VA, Flags));
1745 if (!MemOpChains.empty())
1746 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1747 &MemOpChains[0], MemOpChains.size());
1749 // Build a sequence of copy-to-reg nodes chained together with token chain
1750 // and flag operands which copy the outgoing args into registers.
1752 // Tail call byval lowering might overwrite argument registers so in case of
1753 // tail call optimization the copies to registers are lowered later.
1755 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1756 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1757 RegsToPass[i].second, InFlag);
1758 InFlag = Chain.getValue(1);
1762 if (Subtarget->isPICStyleGOT()) {
1763 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1766 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1767 DAG.getNode(X86ISD::GlobalBaseReg,
1768 DebugLoc::getUnknownLoc(),
1771 InFlag = Chain.getValue(1);
1773 // If we are tail calling and generating PIC/GOT style code load the
1774 // address of the callee into ECX. The value in ecx is used as target of
1775 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1776 // for tail calls on PIC/GOT architectures. Normally we would just put the
1777 // address of GOT into ebx and then call target@PLT. But for tail calls
1778 // ebx would be restored (since ebx is callee saved) before jumping to the
1781 // Note: The actual moving to ECX is done further down.
1782 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1783 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1784 !G->getGlobal()->hasProtectedVisibility())
1785 Callee = LowerGlobalAddress(Callee, DAG);
1786 else if (isa<ExternalSymbolSDNode>(Callee))
1787 Callee = LowerExternalSymbol(Callee, DAG);
1791 if (Is64Bit && isVarArg) {
1792 // From AMD64 ABI document:
1793 // For calls that may call functions that use varargs or stdargs
1794 // (prototype-less calls or calls to functions containing ellipsis (...) in
1795 // the declaration) %al is used as hidden argument to specify the number
1796 // of SSE registers used. The contents of %al do not need to match exactly
1797 // the number of registers, but must be an ubound on the number of SSE
1798 // registers used and is in the range 0 - 8 inclusive.
1800 // FIXME: Verify this on Win64
1801 // Count the number of XMM registers allocated.
1802 static const unsigned XMMArgRegs[] = {
1803 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1804 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1806 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1807 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1808 && "SSE registers cannot be used when SSE is disabled");
1810 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1811 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1812 InFlag = Chain.getValue(1);
1816 // For tail calls lower the arguments to the 'real' stack slot.
1818 // Force all the incoming stack arguments to be loaded from the stack
1819 // before any new outgoing arguments are stored to the stack, because the
1820 // outgoing stack slots may alias the incoming argument stack slots, and
1821 // the alias isn't otherwise explicit. This is slightly more conservative
1822 // than necessary, because it means that each store effectively depends
1823 // on every argument instead of just those arguments it would clobber.
1824 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1826 SmallVector<SDValue, 8> MemOpChains2;
1829 // Do not flag preceeding copytoreg stuff together with the following stuff.
1831 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1832 CCValAssign &VA = ArgLocs[i];
1833 if (!VA.isRegLoc()) {
1834 assert(VA.isMemLoc());
1835 SDValue Arg = Outs[i].Val;
1836 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1837 // Create frame index.
1838 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1839 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1840 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1841 FIN = DAG.getFrameIndex(FI, getPointerTy());
1843 if (Flags.isByVal()) {
1844 // Copy relative to framepointer.
1845 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1846 if (StackPtr.getNode() == 0)
1847 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1849 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1851 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1855 // Store relative to framepointer.
1856 MemOpChains2.push_back(
1857 DAG.getStore(ArgChain, dl, Arg, FIN,
1858 PseudoSourceValue::getFixedStack(FI), 0));
1863 if (!MemOpChains2.empty())
1864 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1865 &MemOpChains2[0], MemOpChains2.size());
1867 // Copy arguments to their registers.
1868 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1869 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1870 RegsToPass[i].second, InFlag);
1871 InFlag = Chain.getValue(1);
1875 // Store the return address to the appropriate stack slot.
1876 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1880 // If the callee is a GlobalAddress node (quite common, every direct call is)
1881 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1882 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1883 // We should use extra load for direct calls to dllimported functions in
1885 GlobalValue *GV = G->getGlobal();
1886 if (!GV->hasDLLImportLinkage()) {
1887 unsigned char OpFlags = 0;
1889 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1890 // external symbols most go through the PLT in PIC mode. If the symbol
1891 // has hidden or protected visibility, or if it is static or local, then
1892 // we don't need to use the PLT - we can directly call it.
1893 if (Subtarget->isTargetELF() &&
1894 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1895 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1896 OpFlags = X86II::MO_PLT;
1897 } else if (Subtarget->isPICStyleStubAny() &&
1898 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1899 Subtarget->getDarwinVers() < 9) {
1900 // PC-relative references to external symbols should go through $stub,
1901 // unless we're building with the leopard linker or later, which
1902 // automatically synthesizes these stubs.
1903 OpFlags = X86II::MO_DARWIN_STUB;
1906 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1907 G->getOffset(), OpFlags);
1909 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1910 unsigned char OpFlags = 0;
1912 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1913 // symbols should go through the PLT.
1914 if (Subtarget->isTargetELF() &&
1915 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1916 OpFlags = X86II::MO_PLT;
1917 } else if (Subtarget->isPICStyleStubAny() &&
1918 Subtarget->getDarwinVers() < 9) {
1919 // PC-relative references to external symbols should go through $stub,
1920 // unless we're building with the leopard linker or later, which
1921 // automatically synthesizes these stubs.
1922 OpFlags = X86II::MO_DARWIN_STUB;
1925 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
1927 } else if (isTailCall) {
1928 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
1930 Chain = DAG.getCopyToReg(Chain, dl,
1931 DAG.getRegister(Opc, getPointerTy()),
1933 Callee = DAG.getRegister(Opc, getPointerTy());
1934 // Add register as live out.
1935 MF.getRegInfo().addLiveOut(Opc);
1938 // Returns a chain & a flag for retval copy to use.
1939 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1940 SmallVector<SDValue, 8> Ops;
1943 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1944 DAG.getIntPtrConstant(0, true), InFlag);
1945 InFlag = Chain.getValue(1);
1948 Ops.push_back(Chain);
1949 Ops.push_back(Callee);
1952 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1954 // Add argument registers to the end of the list so that they are known live
1956 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1957 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1958 RegsToPass[i].second.getValueType()));
1960 // Add an implicit use GOT pointer in EBX.
1961 if (!isTailCall && Subtarget->isPICStyleGOT())
1962 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1964 // Add an implicit use of AL for x86 vararg functions.
1965 if (Is64Bit && isVarArg)
1966 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1968 if (InFlag.getNode())
1969 Ops.push_back(InFlag);
1972 // If this is the first return lowered for this function, add the regs
1973 // to the liveout set for the function.
1974 if (MF.getRegInfo().liveout_empty()) {
1975 SmallVector<CCValAssign, 16> RVLocs;
1976 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1978 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1979 for (unsigned i = 0; i != RVLocs.size(); ++i)
1980 if (RVLocs[i].isRegLoc())
1981 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1984 assert(((Callee.getOpcode() == ISD::Register &&
1985 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
1986 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
1987 Callee.getOpcode() == ISD::TargetExternalSymbol ||
1988 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
1989 "Expecting an global address, external symbol, or register");
1991 return DAG.getNode(X86ISD::TC_RETURN, dl,
1992 NodeTys, &Ops[0], Ops.size());
1995 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
1996 InFlag = Chain.getValue(1);
1998 // Create the CALLSEQ_END node.
1999 unsigned NumBytesForCalleeToPush;
2000 if (IsCalleePop(isVarArg, CallConv))
2001 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2002 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2003 // If this is is a call to a struct-return function, the callee
2004 // pops the hidden struct pointer, so we have to push it back.
2005 // This is common for Darwin/X86, Linux & Mingw32 targets.
2006 NumBytesForCalleeToPush = 4;
2008 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2010 // Returns a flag for retval copy to use.
2011 Chain = DAG.getCALLSEQ_END(Chain,
2012 DAG.getIntPtrConstant(NumBytes, true),
2013 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2016 InFlag = Chain.getValue(1);
2018 // Handle result values, copying them out of physregs into vregs that we
2020 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2021 Ins, dl, DAG, InVals);
2025 //===----------------------------------------------------------------------===//
2026 // Fast Calling Convention (tail call) implementation
2027 //===----------------------------------------------------------------------===//
2029 // Like std call, callee cleans arguments, convention except that ECX is
2030 // reserved for storing the tail called function address. Only 2 registers are
2031 // free for argument passing (inreg). Tail call optimization is performed
2033 // * tailcallopt is enabled
2034 // * caller/callee are fastcc
2035 // On X86_64 architecture with GOT-style position independent code only local
2036 // (within module) calls are supported at the moment.
2037 // To keep the stack aligned according to platform abi the function
2038 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2039 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2040 // If a tail called function callee has more arguments than the caller the
2041 // caller needs to make sure that there is room to move the RETADDR to. This is
2042 // achieved by reserving an area the size of the argument delta right after the
2043 // original REtADDR, but before the saved framepointer or the spilled registers
2044 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2056 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2057 /// for a 16 byte align requirement.
2058 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2059 SelectionDAG& DAG) {
2060 MachineFunction &MF = DAG.getMachineFunction();
2061 const TargetMachine &TM = MF.getTarget();
2062 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2063 unsigned StackAlignment = TFI.getStackAlignment();
2064 uint64_t AlignMask = StackAlignment - 1;
2065 int64_t Offset = StackSize;
2066 uint64_t SlotSize = TD->getPointerSize();
2067 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2068 // Number smaller than 12 so just add the difference.
2069 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2071 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2072 Offset = ((~AlignMask) & Offset) + StackAlignment +
2073 (StackAlignment-SlotSize);
2078 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2079 /// for tail call optimization. Targets which want to do tail call
2080 /// optimization should implement this function.
2082 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2085 const SmallVectorImpl<ISD::InputArg> &Ins,
2086 SelectionDAG& DAG) const {
2087 MachineFunction &MF = DAG.getMachineFunction();
2088 unsigned CallerCC = MF.getFunction()->getCallingConv();
2089 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2093 X86TargetLowering::createFastISel(MachineFunction &mf,
2094 MachineModuleInfo *mmo,
2096 DenseMap<const Value *, unsigned> &vm,
2097 DenseMap<const BasicBlock *,
2098 MachineBasicBlock *> &bm,
2099 DenseMap<const AllocaInst *, int> &am
2101 , SmallSet<Instruction*, 8> &cil
2104 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2112 //===----------------------------------------------------------------------===//
2113 // Other Lowering Hooks
2114 //===----------------------------------------------------------------------===//
2117 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2118 MachineFunction &MF = DAG.getMachineFunction();
2119 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2120 int ReturnAddrIndex = FuncInfo->getRAIndex();
2122 if (ReturnAddrIndex == 0) {
2123 // Set up a frame object for the return address.
2124 uint64_t SlotSize = TD->getPointerSize();
2125 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2126 FuncInfo->setRAIndex(ReturnAddrIndex);
2129 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2133 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2134 bool hasSymbolicDisplacement) {
2135 // Offset should fit into 32 bit immediate field.
2136 if (!isInt32(Offset))
2139 // If we don't have a symbolic displacement - we don't have any extra
2141 if (!hasSymbolicDisplacement)
2144 // FIXME: Some tweaks might be needed for medium code model.
2145 if (M != CodeModel::Small && M != CodeModel::Kernel)
2148 // For small code model we assume that latest object is 16MB before end of 31
2149 // bits boundary. We may also accept pretty large negative constants knowing
2150 // that all objects are in the positive half of address space.
2151 if (M == CodeModel::Small && Offset < 16*1024*1024)
2154 // For kernel code model we know that all object resist in the negative half
2155 // of 32bits address space. We may not accept negative offsets, since they may
2156 // be just off and we may accept pretty large positive ones.
2157 if (M == CodeModel::Kernel && Offset > 0)
2163 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2164 /// specific condition code, returning the condition code and the LHS/RHS of the
2165 /// comparison to make.
2166 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2167 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2169 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2170 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2171 // X > -1 -> X == 0, jump !sign.
2172 RHS = DAG.getConstant(0, RHS.getValueType());
2173 return X86::COND_NS;
2174 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2175 // X < 0 -> X == 0, jump on sign.
2177 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2179 RHS = DAG.getConstant(0, RHS.getValueType());
2180 return X86::COND_LE;
2184 switch (SetCCOpcode) {
2185 default: llvm_unreachable("Invalid integer condition!");
2186 case ISD::SETEQ: return X86::COND_E;
2187 case ISD::SETGT: return X86::COND_G;
2188 case ISD::SETGE: return X86::COND_GE;
2189 case ISD::SETLT: return X86::COND_L;
2190 case ISD::SETLE: return X86::COND_LE;
2191 case ISD::SETNE: return X86::COND_NE;
2192 case ISD::SETULT: return X86::COND_B;
2193 case ISD::SETUGT: return X86::COND_A;
2194 case ISD::SETULE: return X86::COND_BE;
2195 case ISD::SETUGE: return X86::COND_AE;
2199 // First determine if it is required or is profitable to flip the operands.
2201 // If LHS is a foldable load, but RHS is not, flip the condition.
2202 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2203 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2204 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2205 std::swap(LHS, RHS);
2208 switch (SetCCOpcode) {
2214 std::swap(LHS, RHS);
2218 // On a floating point condition, the flags are set as follows:
2220 // 0 | 0 | 0 | X > Y
2221 // 0 | 0 | 1 | X < Y
2222 // 1 | 0 | 0 | X == Y
2223 // 1 | 1 | 1 | unordered
2224 switch (SetCCOpcode) {
2225 default: llvm_unreachable("Condcode should be pre-legalized away");
2227 case ISD::SETEQ: return X86::COND_E;
2228 case ISD::SETOLT: // flipped
2230 case ISD::SETGT: return X86::COND_A;
2231 case ISD::SETOLE: // flipped
2233 case ISD::SETGE: return X86::COND_AE;
2234 case ISD::SETUGT: // flipped
2236 case ISD::SETLT: return X86::COND_B;
2237 case ISD::SETUGE: // flipped
2239 case ISD::SETLE: return X86::COND_BE;
2241 case ISD::SETNE: return X86::COND_NE;
2242 case ISD::SETUO: return X86::COND_P;
2243 case ISD::SETO: return X86::COND_NP;
2247 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2248 /// code. Current x86 isa includes the following FP cmov instructions:
2249 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2250 static bool hasFPCMov(unsigned X86CC) {
2266 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2267 /// the specified range (L, H].
2268 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2269 return (Val < 0) || (Val >= Low && Val < Hi);
2272 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2273 /// specified value.
2274 static bool isUndefOrEqual(int Val, int CmpVal) {
2275 if (Val < 0 || Val == CmpVal)
2280 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2281 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2282 /// the second operand.
2283 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2284 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2285 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2286 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2287 return (Mask[0] < 2 && Mask[1] < 2);
2291 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2292 SmallVector<int, 8> M;
2294 return ::isPSHUFDMask(M, N->getValueType(0));
2297 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2298 /// is suitable for input to PSHUFHW.
2299 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2300 if (VT != MVT::v8i16)
2303 // Lower quadword copied in order or undef.
2304 for (int i = 0; i != 4; ++i)
2305 if (Mask[i] >= 0 && Mask[i] != i)
2308 // Upper quadword shuffled.
2309 for (int i = 4; i != 8; ++i)
2310 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2316 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2317 SmallVector<int, 8> M;
2319 return ::isPSHUFHWMask(M, N->getValueType(0));
2322 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2323 /// is suitable for input to PSHUFLW.
2324 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2325 if (VT != MVT::v8i16)
2328 // Upper quadword copied in order.
2329 for (int i = 4; i != 8; ++i)
2330 if (Mask[i] >= 0 && Mask[i] != i)
2333 // Lower quadword shuffled.
2334 for (int i = 0; i != 4; ++i)
2341 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2342 SmallVector<int, 8> M;
2344 return ::isPSHUFLWMask(M, N->getValueType(0));
2347 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2348 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2349 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2350 int NumElems = VT.getVectorNumElements();
2351 if (NumElems != 2 && NumElems != 4)
2354 int Half = NumElems / 2;
2355 for (int i = 0; i < Half; ++i)
2356 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2358 for (int i = Half; i < NumElems; ++i)
2359 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2365 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2366 SmallVector<int, 8> M;
2368 return ::isSHUFPMask(M, N->getValueType(0));
2371 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2372 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2373 /// half elements to come from vector 1 (which would equal the dest.) and
2374 /// the upper half to come from vector 2.
2375 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2376 int NumElems = VT.getVectorNumElements();
2378 if (NumElems != 2 && NumElems != 4)
2381 int Half = NumElems / 2;
2382 for (int i = 0; i < Half; ++i)
2383 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2385 for (int i = Half; i < NumElems; ++i)
2386 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2391 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2392 SmallVector<int, 8> M;
2394 return isCommutedSHUFPMask(M, N->getValueType(0));
2397 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2398 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2399 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2400 if (N->getValueType(0).getVectorNumElements() != 4)
2403 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2404 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2405 isUndefOrEqual(N->getMaskElt(1), 7) &&
2406 isUndefOrEqual(N->getMaskElt(2), 2) &&
2407 isUndefOrEqual(N->getMaskElt(3), 3);
2410 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2411 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2412 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2413 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2415 if (NumElems != 2 && NumElems != 4)
2418 for (unsigned i = 0; i < NumElems/2; ++i)
2419 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2422 for (unsigned i = NumElems/2; i < NumElems; ++i)
2423 if (!isUndefOrEqual(N->getMaskElt(i), i))
2429 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2430 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2432 bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2433 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2435 if (NumElems != 2 && NumElems != 4)
2438 for (unsigned i = 0; i < NumElems/2; ++i)
2439 if (!isUndefOrEqual(N->getMaskElt(i), i))
2442 for (unsigned i = 0; i < NumElems/2; ++i)
2443 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2449 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2450 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2452 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2453 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2458 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2459 isUndefOrEqual(N->getMaskElt(1), 3) &&
2460 isUndefOrEqual(N->getMaskElt(2), 2) &&
2461 isUndefOrEqual(N->getMaskElt(3), 3);
2464 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2465 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2466 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2467 bool V2IsSplat = false) {
2468 int NumElts = VT.getVectorNumElements();
2469 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2472 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2474 int BitI1 = Mask[i+1];
2475 if (!isUndefOrEqual(BitI, j))
2478 if (!isUndefOrEqual(BitI1, NumElts))
2481 if (!isUndefOrEqual(BitI1, j + NumElts))
2488 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2489 SmallVector<int, 8> M;
2491 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2494 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2495 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2496 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2497 bool V2IsSplat = false) {
2498 int NumElts = VT.getVectorNumElements();
2499 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2502 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2504 int BitI1 = Mask[i+1];
2505 if (!isUndefOrEqual(BitI, j + NumElts/2))
2508 if (isUndefOrEqual(BitI1, NumElts))
2511 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2518 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2519 SmallVector<int, 8> M;
2521 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2524 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2525 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2527 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2528 int NumElems = VT.getVectorNumElements();
2529 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2532 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2534 int BitI1 = Mask[i+1];
2535 if (!isUndefOrEqual(BitI, j))
2537 if (!isUndefOrEqual(BitI1, j))
2543 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2544 SmallVector<int, 8> M;
2546 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2549 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2550 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2552 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2553 int NumElems = VT.getVectorNumElements();
2554 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2557 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2559 int BitI1 = Mask[i+1];
2560 if (!isUndefOrEqual(BitI, j))
2562 if (!isUndefOrEqual(BitI1, j))
2568 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2569 SmallVector<int, 8> M;
2571 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2574 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2575 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2576 /// MOVSD, and MOVD, i.e. setting the lowest element.
2577 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2578 if (VT.getVectorElementType().getSizeInBits() < 32)
2581 int NumElts = VT.getVectorNumElements();
2583 if (!isUndefOrEqual(Mask[0], NumElts))
2586 for (int i = 1; i < NumElts; ++i)
2587 if (!isUndefOrEqual(Mask[i], i))
2593 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2594 SmallVector<int, 8> M;
2596 return ::isMOVLMask(M, N->getValueType(0));
2599 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2600 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2601 /// element of vector 2 and the other elements to come from vector 1 in order.
2602 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2603 bool V2IsSplat = false, bool V2IsUndef = false) {
2604 int NumOps = VT.getVectorNumElements();
2605 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2608 if (!isUndefOrEqual(Mask[0], 0))
2611 for (int i = 1; i < NumOps; ++i)
2612 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2613 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2614 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2620 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2621 bool V2IsUndef = false) {
2622 SmallVector<int, 8> M;
2624 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2627 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2628 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2629 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2630 if (N->getValueType(0).getVectorNumElements() != 4)
2633 // Expect 1, 1, 3, 3
2634 for (unsigned i = 0; i < 2; ++i) {
2635 int Elt = N->getMaskElt(i);
2636 if (Elt >= 0 && Elt != 1)
2641 for (unsigned i = 2; i < 4; ++i) {
2642 int Elt = N->getMaskElt(i);
2643 if (Elt >= 0 && Elt != 3)
2648 // Don't use movshdup if it can be done with a shufps.
2649 // FIXME: verify that matching u, u, 3, 3 is what we want.
2653 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2654 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2655 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2656 if (N->getValueType(0).getVectorNumElements() != 4)
2659 // Expect 0, 0, 2, 2
2660 for (unsigned i = 0; i < 2; ++i)
2661 if (N->getMaskElt(i) > 0)
2665 for (unsigned i = 2; i < 4; ++i) {
2666 int Elt = N->getMaskElt(i);
2667 if (Elt >= 0 && Elt != 2)
2672 // Don't use movsldup if it can be done with a shufps.
2676 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2677 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2678 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2679 int e = N->getValueType(0).getVectorNumElements() / 2;
2681 for (int i = 0; i < e; ++i)
2682 if (!isUndefOrEqual(N->getMaskElt(i), i))
2684 for (int i = 0; i < e; ++i)
2685 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2690 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2691 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2693 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2694 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2695 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2697 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2699 for (int i = 0; i < NumOperands; ++i) {
2700 int Val = SVOp->getMaskElt(NumOperands-i-1);
2701 if (Val < 0) Val = 0;
2702 if (Val >= NumOperands) Val -= NumOperands;
2704 if (i != NumOperands - 1)
2710 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2711 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2713 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2714 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2716 // 8 nodes, but we only care about the last 4.
2717 for (unsigned i = 7; i >= 4; --i) {
2718 int Val = SVOp->getMaskElt(i);
2727 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2728 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2730 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2731 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2733 // 8 nodes, but we only care about the first 4.
2734 for (int i = 3; i >= 0; --i) {
2735 int Val = SVOp->getMaskElt(i);
2744 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2746 bool X86::isZeroNode(SDValue Elt) {
2747 return ((isa<ConstantSDNode>(Elt) &&
2748 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2749 (isa<ConstantFPSDNode>(Elt) &&
2750 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2753 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2754 /// their permute mask.
2755 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2756 SelectionDAG &DAG) {
2757 EVT VT = SVOp->getValueType(0);
2758 unsigned NumElems = VT.getVectorNumElements();
2759 SmallVector<int, 8> MaskVec;
2761 for (unsigned i = 0; i != NumElems; ++i) {
2762 int idx = SVOp->getMaskElt(i);
2764 MaskVec.push_back(idx);
2765 else if (idx < (int)NumElems)
2766 MaskVec.push_back(idx + NumElems);
2768 MaskVec.push_back(idx - NumElems);
2770 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2771 SVOp->getOperand(0), &MaskVec[0]);
2774 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2775 /// the two vector operands have swapped position.
2776 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2777 unsigned NumElems = VT.getVectorNumElements();
2778 for (unsigned i = 0; i != NumElems; ++i) {
2782 else if (idx < (int)NumElems)
2783 Mask[i] = idx + NumElems;
2785 Mask[i] = idx - NumElems;
2789 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2790 /// match movhlps. The lower half elements should come from upper half of
2791 /// V1 (and in order), and the upper half elements should come from the upper
2792 /// half of V2 (and in order).
2793 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2794 if (Op->getValueType(0).getVectorNumElements() != 4)
2796 for (unsigned i = 0, e = 2; i != e; ++i)
2797 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2799 for (unsigned i = 2; i != 4; ++i)
2800 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2805 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2806 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2808 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2809 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2811 N = N->getOperand(0).getNode();
2812 if (!ISD::isNON_EXTLoad(N))
2815 *LD = cast<LoadSDNode>(N);
2819 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2820 /// match movlp{s|d}. The lower half elements should come from lower half of
2821 /// V1 (and in order), and the upper half elements should come from the upper
2822 /// half of V2 (and in order). And since V1 will become the source of the
2823 /// MOVLP, it must be either a vector load or a scalar load to vector.
2824 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2825 ShuffleVectorSDNode *Op) {
2826 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2828 // Is V2 is a vector load, don't do this transformation. We will try to use
2829 // load folding shufps op.
2830 if (ISD::isNON_EXTLoad(V2))
2833 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2835 if (NumElems != 2 && NumElems != 4)
2837 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2838 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2840 for (unsigned i = NumElems/2; i != NumElems; ++i)
2841 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2846 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2848 static bool isSplatVector(SDNode *N) {
2849 if (N->getOpcode() != ISD::BUILD_VECTOR)
2852 SDValue SplatValue = N->getOperand(0);
2853 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2854 if (N->getOperand(i) != SplatValue)
2859 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2860 /// to an zero vector.
2861 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
2862 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
2863 SDValue V1 = N->getOperand(0);
2864 SDValue V2 = N->getOperand(1);
2865 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2866 for (unsigned i = 0; i != NumElems; ++i) {
2867 int Idx = N->getMaskElt(i);
2868 if (Idx >= (int)NumElems) {
2869 unsigned Opc = V2.getOpcode();
2870 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2872 if (Opc != ISD::BUILD_VECTOR ||
2873 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
2875 } else if (Idx >= 0) {
2876 unsigned Opc = V1.getOpcode();
2877 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2879 if (Opc != ISD::BUILD_VECTOR ||
2880 !X86::isZeroNode(V1.getOperand(Idx)))
2887 /// getZeroVector - Returns a vector of specified type with all zero elements.
2889 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
2891 assert(VT.isVector() && "Expected a vector type");
2893 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2894 // type. This ensures they get CSE'd.
2896 if (VT.getSizeInBits() == 64) { // MMX
2897 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2898 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2899 } else if (HasSSE2) { // SSE2
2900 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2901 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2903 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2904 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2906 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2909 /// getOnesVector - Returns a vector of specified type with all bits set.
2911 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2912 assert(VT.isVector() && "Expected a vector type");
2914 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2915 // type. This ensures they get CSE'd.
2916 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2918 if (VT.getSizeInBits() == 64) // MMX
2919 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2921 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2922 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2926 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2927 /// that point to V2 points to its first element.
2928 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
2929 EVT VT = SVOp->getValueType(0);
2930 unsigned NumElems = VT.getVectorNumElements();
2932 bool Changed = false;
2933 SmallVector<int, 8> MaskVec;
2934 SVOp->getMask(MaskVec);
2936 for (unsigned i = 0; i != NumElems; ++i) {
2937 if (MaskVec[i] > (int)NumElems) {
2938 MaskVec[i] = NumElems;
2943 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
2944 SVOp->getOperand(1), &MaskVec[0]);
2945 return SDValue(SVOp, 0);
2948 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2949 /// operation of specified width.
2950 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
2952 unsigned NumElems = VT.getVectorNumElements();
2953 SmallVector<int, 8> Mask;
2954 Mask.push_back(NumElems);
2955 for (unsigned i = 1; i != NumElems; ++i)
2957 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2960 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
2961 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
2963 unsigned NumElems = VT.getVectorNumElements();
2964 SmallVector<int, 8> Mask;
2965 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2967 Mask.push_back(i + NumElems);
2969 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2972 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
2973 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
2975 unsigned NumElems = VT.getVectorNumElements();
2976 unsigned Half = NumElems/2;
2977 SmallVector<int, 8> Mask;
2978 for (unsigned i = 0; i != Half; ++i) {
2979 Mask.push_back(i + Half);
2980 Mask.push_back(i + NumElems + Half);
2982 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2985 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2986 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
2988 if (SV->getValueType(0).getVectorNumElements() <= 4)
2989 return SDValue(SV, 0);
2991 EVT PVT = MVT::v4f32;
2992 EVT VT = SV->getValueType(0);
2993 DebugLoc dl = SV->getDebugLoc();
2994 SDValue V1 = SV->getOperand(0);
2995 int NumElems = VT.getVectorNumElements();
2996 int EltNo = SV->getSplatIndex();
2998 // unpack elements to the correct location
2999 while (NumElems > 4) {
3000 if (EltNo < NumElems/2) {
3001 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3003 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3004 EltNo -= NumElems/2;
3009 // Perform the splat.
3010 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3011 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3012 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3013 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3016 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3017 /// vector of zero or undef vector. This produces a shuffle where the low
3018 /// element of V2 is swizzled into the zero/undef vector, landing at element
3019 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3020 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3021 bool isZero, bool HasSSE2,
3022 SelectionDAG &DAG) {
3023 EVT VT = V2.getValueType();
3025 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3026 unsigned NumElems = VT.getVectorNumElements();
3027 SmallVector<int, 16> MaskVec;
3028 for (unsigned i = 0; i != NumElems; ++i)
3029 // If this is the insertion idx, put the low elt of V2 here.
3030 MaskVec.push_back(i == Idx ? NumElems : i);
3031 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3034 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3035 /// a shuffle that is zero.
3037 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3038 bool Low, SelectionDAG &DAG) {
3039 unsigned NumZeros = 0;
3040 for (int i = 0; i < NumElems; ++i) {
3041 unsigned Index = Low ? i : NumElems-i-1;
3042 int Idx = SVOp->getMaskElt(Index);
3047 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3048 if (Elt.getNode() && X86::isZeroNode(Elt))
3056 /// isVectorShift - Returns true if the shuffle can be implemented as a
3057 /// logical left or right shift of a vector.
3058 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3059 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3060 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3061 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3064 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3067 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3071 bool SeenV1 = false;
3072 bool SeenV2 = false;
3073 for (int i = NumZeros; i < NumElems; ++i) {
3074 int Val = isLeft ? (i - NumZeros) : i;
3075 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3087 if (SeenV1 && SeenV2)
3090 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3096 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3098 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3099 unsigned NumNonZero, unsigned NumZero,
3100 SelectionDAG &DAG, TargetLowering &TLI) {
3104 DebugLoc dl = Op.getDebugLoc();
3107 for (unsigned i = 0; i < 16; ++i) {
3108 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3109 if (ThisIsNonZero && First) {
3111 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3113 V = DAG.getUNDEF(MVT::v8i16);
3118 SDValue ThisElt(0, 0), LastElt(0, 0);
3119 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3120 if (LastIsNonZero) {
3121 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3122 MVT::i16, Op.getOperand(i-1));
3124 if (ThisIsNonZero) {
3125 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3126 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3127 ThisElt, DAG.getConstant(8, MVT::i8));
3129 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3133 if (ThisElt.getNode())
3134 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3135 DAG.getIntPtrConstant(i/2));
3139 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3142 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3144 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3145 unsigned NumNonZero, unsigned NumZero,
3146 SelectionDAG &DAG, TargetLowering &TLI) {
3150 DebugLoc dl = Op.getDebugLoc();
3153 for (unsigned i = 0; i < 8; ++i) {
3154 bool isNonZero = (NonZeros & (1 << i)) != 0;
3158 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3160 V = DAG.getUNDEF(MVT::v8i16);
3163 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3164 MVT::v8i16, V, Op.getOperand(i),
3165 DAG.getIntPtrConstant(i));
3172 /// getVShift - Return a vector logical shift node.
3174 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3175 unsigned NumBits, SelectionDAG &DAG,
3176 const TargetLowering &TLI, DebugLoc dl) {
3177 bool isMMX = VT.getSizeInBits() == 64;
3178 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3179 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3180 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3181 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3182 DAG.getNode(Opc, dl, ShVT, SrcOp,
3183 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3187 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3188 DebugLoc dl = Op.getDebugLoc();
3189 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3190 if (ISD::isBuildVectorAllZeros(Op.getNode())
3191 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3192 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3193 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3194 // eliminated on x86-32 hosts.
3195 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3198 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3199 return getOnesVector(Op.getValueType(), DAG, dl);
3200 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3203 EVT VT = Op.getValueType();
3204 EVT ExtVT = VT.getVectorElementType();
3205 unsigned EVTBits = ExtVT.getSizeInBits();
3207 unsigned NumElems = Op.getNumOperands();
3208 unsigned NumZero = 0;
3209 unsigned NumNonZero = 0;
3210 unsigned NonZeros = 0;
3211 bool IsAllConstants = true;
3212 SmallSet<SDValue, 8> Values;
3213 for (unsigned i = 0; i < NumElems; ++i) {
3214 SDValue Elt = Op.getOperand(i);
3215 if (Elt.getOpcode() == ISD::UNDEF)
3218 if (Elt.getOpcode() != ISD::Constant &&
3219 Elt.getOpcode() != ISD::ConstantFP)
3220 IsAllConstants = false;
3221 if (X86::isZeroNode(Elt))
3224 NonZeros |= (1 << i);
3229 if (NumNonZero == 0) {
3230 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3231 return DAG.getUNDEF(VT);
3234 // Special case for single non-zero, non-undef, element.
3235 if (NumNonZero == 1) {
3236 unsigned Idx = CountTrailingZeros_32(NonZeros);
3237 SDValue Item = Op.getOperand(Idx);
3239 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3240 // the value are obviously zero, truncate the value to i32 and do the
3241 // insertion that way. Only do this if the value is non-constant or if the
3242 // value is a constant being inserted into element 0. It is cheaper to do
3243 // a constant pool load than it is to do a movd + shuffle.
3244 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3245 (!IsAllConstants || Idx == 0)) {
3246 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3247 // Handle MMX and SSE both.
3248 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3249 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3251 // Truncate the value (which may itself be a constant) to i32, and
3252 // convert it to a vector with movd (S2V+shuffle to zero extend).
3253 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3254 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3255 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3256 Subtarget->hasSSE2(), DAG);
3258 // Now we have our 32-bit value zero extended in the low element of
3259 // a vector. If Idx != 0, swizzle it into place.
3261 SmallVector<int, 4> Mask;
3262 Mask.push_back(Idx);
3263 for (unsigned i = 1; i != VecElts; ++i)
3265 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3266 DAG.getUNDEF(Item.getValueType()),
3269 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3273 // If we have a constant or non-constant insertion into the low element of
3274 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3275 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3276 // depending on what the source datatype is.
3279 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3280 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3281 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3282 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3283 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3284 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3286 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3287 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3288 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3289 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3290 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3291 Subtarget->hasSSE2(), DAG);
3292 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3296 // Is it a vector logical left shift?
3297 if (NumElems == 2 && Idx == 1 &&
3298 X86::isZeroNode(Op.getOperand(0)) &&
3299 !X86::isZeroNode(Op.getOperand(1))) {
3300 unsigned NumBits = VT.getSizeInBits();
3301 return getVShift(true, VT,
3302 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3303 VT, Op.getOperand(1)),
3304 NumBits/2, DAG, *this, dl);
3307 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3310 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3311 // is a non-constant being inserted into an element other than the low one,
3312 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3313 // movd/movss) to move this into the low element, then shuffle it into
3315 if (EVTBits == 32) {
3316 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3318 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3319 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3320 Subtarget->hasSSE2(), DAG);
3321 SmallVector<int, 8> MaskVec;
3322 for (unsigned i = 0; i < NumElems; i++)
3323 MaskVec.push_back(i == Idx ? 0 : 1);
3324 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3328 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3329 if (Values.size() == 1)
3332 // A vector full of immediates; various special cases are already
3333 // handled, so this is best done with a single constant-pool load.
3337 // Let legalizer expand 2-wide build_vectors.
3338 if (EVTBits == 64) {
3339 if (NumNonZero == 1) {
3340 // One half is zero or undef.
3341 unsigned Idx = CountTrailingZeros_32(NonZeros);
3342 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3343 Op.getOperand(Idx));
3344 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3345 Subtarget->hasSSE2(), DAG);
3350 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3351 if (EVTBits == 8 && NumElems == 16) {
3352 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3354 if (V.getNode()) return V;
3357 if (EVTBits == 16 && NumElems == 8) {
3358 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3360 if (V.getNode()) return V;
3363 // If element VT is == 32 bits, turn it into a number of shuffles.
3364 SmallVector<SDValue, 8> V;
3366 if (NumElems == 4 && NumZero > 0) {
3367 for (unsigned i = 0; i < 4; ++i) {
3368 bool isZero = !(NonZeros & (1 << i));
3370 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3372 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3375 for (unsigned i = 0; i < 2; ++i) {
3376 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3379 V[i] = V[i*2]; // Must be a zero vector.
3382 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3385 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3388 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3393 SmallVector<int, 8> MaskVec;
3394 bool Reverse = (NonZeros & 0x3) == 2;
3395 for (unsigned i = 0; i < 2; ++i)
3396 MaskVec.push_back(Reverse ? 1-i : i);
3397 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3398 for (unsigned i = 0; i < 2; ++i)
3399 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3400 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3403 if (Values.size() > 2) {
3404 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3405 // values to be inserted is equal to the number of elements, in which case
3406 // use the unpack code below in the hopes of matching the consecutive elts
3407 // load merge pattern for shuffles.
3408 // FIXME: We could probably just check that here directly.
3409 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3410 getSubtarget()->hasSSE41()) {
3411 V[0] = DAG.getUNDEF(VT);
3412 for (unsigned i = 0; i < NumElems; ++i)
3413 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3414 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3415 Op.getOperand(i), DAG.getIntPtrConstant(i));
3418 // Expand into a number of unpckl*.
3420 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3421 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3422 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3423 for (unsigned i = 0; i < NumElems; ++i)
3424 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3426 while (NumElems != 0) {
3427 for (unsigned i = 0; i < NumElems; ++i)
3428 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3437 // v8i16 shuffles - Prefer shuffles in the following order:
3438 // 1. [all] pshuflw, pshufhw, optional move
3439 // 2. [ssse3] 1 x pshufb
3440 // 3. [ssse3] 2 x pshufb + 1 x por
3441 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3443 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3444 SelectionDAG &DAG, X86TargetLowering &TLI) {
3445 SDValue V1 = SVOp->getOperand(0);
3446 SDValue V2 = SVOp->getOperand(1);
3447 DebugLoc dl = SVOp->getDebugLoc();
3448 SmallVector<int, 8> MaskVals;
3450 // Determine if more than 1 of the words in each of the low and high quadwords
3451 // of the result come from the same quadword of one of the two inputs. Undef
3452 // mask values count as coming from any quadword, for better codegen.
3453 SmallVector<unsigned, 4> LoQuad(4);
3454 SmallVector<unsigned, 4> HiQuad(4);
3455 BitVector InputQuads(4);
3456 for (unsigned i = 0; i < 8; ++i) {
3457 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3458 int EltIdx = SVOp->getMaskElt(i);
3459 MaskVals.push_back(EltIdx);
3468 InputQuads.set(EltIdx / 4);
3471 int BestLoQuad = -1;
3472 unsigned MaxQuad = 1;
3473 for (unsigned i = 0; i < 4; ++i) {
3474 if (LoQuad[i] > MaxQuad) {
3476 MaxQuad = LoQuad[i];
3480 int BestHiQuad = -1;
3482 for (unsigned i = 0; i < 4; ++i) {
3483 if (HiQuad[i] > MaxQuad) {
3485 MaxQuad = HiQuad[i];
3489 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3490 // of the two input vectors, shuffle them into one input vector so only a
3491 // single pshufb instruction is necessary. If There are more than 2 input
3492 // quads, disable the next transformation since it does not help SSSE3.
3493 bool V1Used = InputQuads[0] || InputQuads[1];
3494 bool V2Used = InputQuads[2] || InputQuads[3];
3495 if (TLI.getSubtarget()->hasSSSE3()) {
3496 if (InputQuads.count() == 2 && V1Used && V2Used) {
3497 BestLoQuad = InputQuads.find_first();
3498 BestHiQuad = InputQuads.find_next(BestLoQuad);
3500 if (InputQuads.count() > 2) {
3506 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3507 // the shuffle mask. If a quad is scored as -1, that means that it contains
3508 // words from all 4 input quadwords.
3510 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3511 SmallVector<int, 8> MaskV;
3512 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3513 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3514 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3515 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3516 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3517 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3519 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3520 // source words for the shuffle, to aid later transformations.
3521 bool AllWordsInNewV = true;
3522 bool InOrder[2] = { true, true };
3523 for (unsigned i = 0; i != 8; ++i) {
3524 int idx = MaskVals[i];
3526 InOrder[i/4] = false;
3527 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3529 AllWordsInNewV = false;
3533 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3534 if (AllWordsInNewV) {
3535 for (int i = 0; i != 8; ++i) {
3536 int idx = MaskVals[i];
3539 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3540 if ((idx != i) && idx < 4)
3542 if ((idx != i) && idx > 3)
3551 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3552 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3553 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3554 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3555 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3559 // If we have SSSE3, and all words of the result are from 1 input vector,
3560 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3561 // is present, fall back to case 4.
3562 if (TLI.getSubtarget()->hasSSSE3()) {
3563 SmallVector<SDValue,16> pshufbMask;
3565 // If we have elements from both input vectors, set the high bit of the
3566 // shuffle mask element to zero out elements that come from V2 in the V1
3567 // mask, and elements that come from V1 in the V2 mask, so that the two
3568 // results can be OR'd together.
3569 bool TwoInputs = V1Used && V2Used;
3570 for (unsigned i = 0; i != 8; ++i) {
3571 int EltIdx = MaskVals[i] * 2;
3572 if (TwoInputs && (EltIdx >= 16)) {
3573 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3574 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3577 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3578 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3580 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3581 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3582 DAG.getNode(ISD::BUILD_VECTOR, dl,
3583 MVT::v16i8, &pshufbMask[0], 16));
3585 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3587 // Calculate the shuffle mask for the second input, shuffle it, and
3588 // OR it with the first shuffled input.
3590 for (unsigned i = 0; i != 8; ++i) {
3591 int EltIdx = MaskVals[i] * 2;
3593 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3594 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3597 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3598 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3600 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3601 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3602 DAG.getNode(ISD::BUILD_VECTOR, dl,
3603 MVT::v16i8, &pshufbMask[0], 16));
3604 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3605 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3608 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3609 // and update MaskVals with new element order.
3610 BitVector InOrder(8);
3611 if (BestLoQuad >= 0) {
3612 SmallVector<int, 8> MaskV;
3613 for (int i = 0; i != 4; ++i) {
3614 int idx = MaskVals[i];
3616 MaskV.push_back(-1);
3618 } else if ((idx / 4) == BestLoQuad) {
3619 MaskV.push_back(idx & 3);
3622 MaskV.push_back(-1);
3625 for (unsigned i = 4; i != 8; ++i)
3627 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3631 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3632 // and update MaskVals with the new element order.
3633 if (BestHiQuad >= 0) {
3634 SmallVector<int, 8> MaskV;
3635 for (unsigned i = 0; i != 4; ++i)
3637 for (unsigned i = 4; i != 8; ++i) {
3638 int idx = MaskVals[i];
3640 MaskV.push_back(-1);
3642 } else if ((idx / 4) == BestHiQuad) {
3643 MaskV.push_back((idx & 3) + 4);
3646 MaskV.push_back(-1);
3649 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3653 // In case BestHi & BestLo were both -1, which means each quadword has a word
3654 // from each of the four input quadwords, calculate the InOrder bitvector now
3655 // before falling through to the insert/extract cleanup.
3656 if (BestLoQuad == -1 && BestHiQuad == -1) {
3658 for (int i = 0; i != 8; ++i)
3659 if (MaskVals[i] < 0 || MaskVals[i] == i)
3663 // The other elements are put in the right place using pextrw and pinsrw.
3664 for (unsigned i = 0; i != 8; ++i) {
3667 int EltIdx = MaskVals[i];
3670 SDValue ExtOp = (EltIdx < 8)
3671 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3672 DAG.getIntPtrConstant(EltIdx))
3673 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3674 DAG.getIntPtrConstant(EltIdx - 8));
3675 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3676 DAG.getIntPtrConstant(i));
3681 // v16i8 shuffles - Prefer shuffles in the following order:
3682 // 1. [ssse3] 1 x pshufb
3683 // 2. [ssse3] 2 x pshufb + 1 x por
3684 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3686 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3687 SelectionDAG &DAG, X86TargetLowering &TLI) {
3688 SDValue V1 = SVOp->getOperand(0);
3689 SDValue V2 = SVOp->getOperand(1);
3690 DebugLoc dl = SVOp->getDebugLoc();
3691 SmallVector<int, 16> MaskVals;
3692 SVOp->getMask(MaskVals);
3694 // If we have SSSE3, case 1 is generated when all result bytes come from
3695 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3696 // present, fall back to case 3.
3697 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3700 for (unsigned i = 0; i < 16; ++i) {
3701 int EltIdx = MaskVals[i];
3710 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3711 if (TLI.getSubtarget()->hasSSSE3()) {
3712 SmallVector<SDValue,16> pshufbMask;
3714 // If all result elements are from one input vector, then only translate
3715 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3717 // Otherwise, we have elements from both input vectors, and must zero out
3718 // elements that come from V2 in the first mask, and V1 in the second mask
3719 // so that we can OR them together.
3720 bool TwoInputs = !(V1Only || V2Only);
3721 for (unsigned i = 0; i != 16; ++i) {
3722 int EltIdx = MaskVals[i];
3723 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3724 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3727 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3729 // If all the elements are from V2, assign it to V1 and return after
3730 // building the first pshufb.
3733 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3734 DAG.getNode(ISD::BUILD_VECTOR, dl,
3735 MVT::v16i8, &pshufbMask[0], 16));
3739 // Calculate the shuffle mask for the second input, shuffle it, and
3740 // OR it with the first shuffled input.
3742 for (unsigned i = 0; i != 16; ++i) {
3743 int EltIdx = MaskVals[i];
3745 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3748 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3750 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3751 DAG.getNode(ISD::BUILD_VECTOR, dl,
3752 MVT::v16i8, &pshufbMask[0], 16));
3753 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3756 // No SSSE3 - Calculate in place words and then fix all out of place words
3757 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3758 // the 16 different words that comprise the two doublequadword input vectors.
3759 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3760 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3761 SDValue NewV = V2Only ? V2 : V1;
3762 for (int i = 0; i != 8; ++i) {
3763 int Elt0 = MaskVals[i*2];
3764 int Elt1 = MaskVals[i*2+1];
3766 // This word of the result is all undef, skip it.
3767 if (Elt0 < 0 && Elt1 < 0)
3770 // This word of the result is already in the correct place, skip it.
3771 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3773 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3776 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3777 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3780 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3781 // using a single extract together, load it and store it.
3782 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3783 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3784 DAG.getIntPtrConstant(Elt1 / 2));
3785 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3786 DAG.getIntPtrConstant(i));
3790 // If Elt1 is defined, extract it from the appropriate source. If the
3791 // source byte is not also odd, shift the extracted word left 8 bits
3792 // otherwise clear the bottom 8 bits if we need to do an or.
3794 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3795 DAG.getIntPtrConstant(Elt1 / 2));
3796 if ((Elt1 & 1) == 0)
3797 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3798 DAG.getConstant(8, TLI.getShiftAmountTy()));
3800 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3801 DAG.getConstant(0xFF00, MVT::i16));
3803 // If Elt0 is defined, extract it from the appropriate source. If the
3804 // source byte is not also even, shift the extracted word right 8 bits. If
3805 // Elt1 was also defined, OR the extracted values together before
3806 // inserting them in the result.
3808 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3809 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3810 if ((Elt0 & 1) != 0)
3811 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3812 DAG.getConstant(8, TLI.getShiftAmountTy()));
3814 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3815 DAG.getConstant(0x00FF, MVT::i16));
3816 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3819 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3820 DAG.getIntPtrConstant(i));
3822 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3825 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3826 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3827 /// done when every pair / quad of shuffle mask elements point to elements in
3828 /// the right sequence. e.g.
3829 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3831 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3833 TargetLowering &TLI, DebugLoc dl) {
3834 EVT VT = SVOp->getValueType(0);
3835 SDValue V1 = SVOp->getOperand(0);
3836 SDValue V2 = SVOp->getOperand(1);
3837 unsigned NumElems = VT.getVectorNumElements();
3838 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3839 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3840 EVT MaskEltVT = MaskVT.getVectorElementType();
3842 switch (VT.getSimpleVT().SimpleTy) {
3843 default: assert(false && "Unexpected!");
3844 case MVT::v4f32: NewVT = MVT::v2f64; break;
3845 case MVT::v4i32: NewVT = MVT::v2i64; break;
3846 case MVT::v8i16: NewVT = MVT::v4i32; break;
3847 case MVT::v16i8: NewVT = MVT::v4i32; break;
3850 if (NewWidth == 2) {
3856 int Scale = NumElems / NewWidth;
3857 SmallVector<int, 8> MaskVec;
3858 for (unsigned i = 0; i < NumElems; i += Scale) {
3860 for (int j = 0; j < Scale; ++j) {
3861 int EltIdx = SVOp->getMaskElt(i+j);
3865 StartIdx = EltIdx - (EltIdx % Scale);
3866 if (EltIdx != StartIdx + j)
3870 MaskVec.push_back(-1);
3872 MaskVec.push_back(StartIdx / Scale);
3875 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3876 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3877 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
3880 /// getVZextMovL - Return a zero-extending vector move low node.
3882 static SDValue getVZextMovL(EVT VT, EVT OpVT,
3883 SDValue SrcOp, SelectionDAG &DAG,
3884 const X86Subtarget *Subtarget, DebugLoc dl) {
3885 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3886 LoadSDNode *LD = NULL;
3887 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3888 LD = dyn_cast<LoadSDNode>(SrcOp);
3890 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3892 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3893 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
3894 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3895 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3896 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
3898 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3899 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3900 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3901 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3909 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3910 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3911 DAG.getNode(ISD::BIT_CONVERT, dl,
3915 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3918 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3919 SDValue V1 = SVOp->getOperand(0);
3920 SDValue V2 = SVOp->getOperand(1);
3921 DebugLoc dl = SVOp->getDebugLoc();
3922 EVT VT = SVOp->getValueType(0);
3924 SmallVector<std::pair<int, int>, 8> Locs;
3926 SmallVector<int, 8> Mask1(4U, -1);
3927 SmallVector<int, 8> PermMask;
3928 SVOp->getMask(PermMask);
3932 for (unsigned i = 0; i != 4; ++i) {
3933 int Idx = PermMask[i];
3935 Locs[i] = std::make_pair(-1, -1);
3937 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
3939 Locs[i] = std::make_pair(0, NumLo);
3943 Locs[i] = std::make_pair(1, NumHi);
3945 Mask1[2+NumHi] = Idx;
3951 if (NumLo <= 2 && NumHi <= 2) {
3952 // If no more than two elements come from either vector. This can be
3953 // implemented with two shuffles. First shuffle gather the elements.
3954 // The second shuffle, which takes the first shuffle as both of its
3955 // vector operands, put the elements into the right order.
3956 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3958 SmallVector<int, 8> Mask2(4U, -1);
3960 for (unsigned i = 0; i != 4; ++i) {
3961 if (Locs[i].first == -1)
3964 unsigned Idx = (i < 2) ? 0 : 4;
3965 Idx += Locs[i].first * 2 + Locs[i].second;
3970 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
3971 } else if (NumLo == 3 || NumHi == 3) {
3972 // Otherwise, we must have three elements from one vector, call it X, and
3973 // one element from the other, call it Y. First, use a shufps to build an
3974 // intermediate vector with the one element from Y and the element from X
3975 // that will be in the same half in the final destination (the indexes don't
3976 // matter). Then, use a shufps to build the final vector, taking the half
3977 // containing the element from Y from the intermediate, and the other half
3980 // Normalize it so the 3 elements come from V1.
3981 CommuteVectorShuffleMask(PermMask, VT);
3985 // Find the element from V2.
3987 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3988 int Val = PermMask[HiIndex];
3995 Mask1[0] = PermMask[HiIndex];
3997 Mask1[2] = PermMask[HiIndex^1];
3999 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4002 Mask1[0] = PermMask[0];
4003 Mask1[1] = PermMask[1];
4004 Mask1[2] = HiIndex & 1 ? 6 : 4;
4005 Mask1[3] = HiIndex & 1 ? 4 : 6;
4006 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4008 Mask1[0] = HiIndex & 1 ? 2 : 0;
4009 Mask1[1] = HiIndex & 1 ? 0 : 2;
4010 Mask1[2] = PermMask[2];
4011 Mask1[3] = PermMask[3];
4016 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4020 // Break it into (shuffle shuffle_hi, shuffle_lo).
4022 SmallVector<int,8> LoMask(4U, -1);
4023 SmallVector<int,8> HiMask(4U, -1);
4025 SmallVector<int,8> *MaskPtr = &LoMask;
4026 unsigned MaskIdx = 0;
4029 for (unsigned i = 0; i != 4; ++i) {
4036 int Idx = PermMask[i];
4038 Locs[i] = std::make_pair(-1, -1);
4039 } else if (Idx < 4) {
4040 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4041 (*MaskPtr)[LoIdx] = Idx;
4044 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4045 (*MaskPtr)[HiIdx] = Idx;
4050 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4051 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4052 SmallVector<int, 8> MaskOps;
4053 for (unsigned i = 0; i != 4; ++i) {
4054 if (Locs[i].first == -1) {
4055 MaskOps.push_back(-1);
4057 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4058 MaskOps.push_back(Idx);
4061 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4065 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4066 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4067 SDValue V1 = Op.getOperand(0);
4068 SDValue V2 = Op.getOperand(1);
4069 EVT VT = Op.getValueType();
4070 DebugLoc dl = Op.getDebugLoc();
4071 unsigned NumElems = VT.getVectorNumElements();
4072 bool isMMX = VT.getSizeInBits() == 64;
4073 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4074 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4075 bool V1IsSplat = false;
4076 bool V2IsSplat = false;
4078 if (isZeroShuffle(SVOp))
4079 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4081 // Promote splats to v4f32.
4082 if (SVOp->isSplat()) {
4083 if (isMMX || NumElems < 4)
4085 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4088 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4090 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4091 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4092 if (NewOp.getNode())
4093 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4094 LowerVECTOR_SHUFFLE(NewOp, DAG));
4095 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4096 // FIXME: Figure out a cleaner way to do this.
4097 // Try to make use of movq to zero out the top part.
4098 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4099 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4100 if (NewOp.getNode()) {
4101 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4102 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4103 DAG, Subtarget, dl);
4105 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4106 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4107 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4108 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4109 DAG, Subtarget, dl);
4113 if (X86::isPSHUFDMask(SVOp))
4116 // Check if this can be converted into a logical shift.
4117 bool isLeft = false;
4120 bool isShift = getSubtarget()->hasSSE2() &&
4121 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4122 if (isShift && ShVal.hasOneUse()) {
4123 // If the shifted value has multiple uses, it may be cheaper to use
4124 // v_set0 + movlhps or movhlps, etc.
4125 EVT EVT = VT.getVectorElementType();
4126 ShAmt *= EVT.getSizeInBits();
4127 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4130 if (X86::isMOVLMask(SVOp)) {
4133 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4134 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4139 // FIXME: fold these into legal mask.
4140 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4141 X86::isMOVSLDUPMask(SVOp) ||
4142 X86::isMOVHLPSMask(SVOp) ||
4143 X86::isMOVHPMask(SVOp) ||
4144 X86::isMOVLPMask(SVOp)))
4147 if (ShouldXformToMOVHLPS(SVOp) ||
4148 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4149 return CommuteVectorShuffle(SVOp, DAG);
4152 // No better options. Use a vshl / vsrl.
4153 EVT EVT = VT.getVectorElementType();
4154 ShAmt *= EVT.getSizeInBits();
4155 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4158 bool Commuted = false;
4159 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4160 // 1,1,1,1 -> v8i16 though.
4161 V1IsSplat = isSplatVector(V1.getNode());
4162 V2IsSplat = isSplatVector(V2.getNode());
4164 // Canonicalize the splat or undef, if present, to be on the RHS.
4165 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4166 Op = CommuteVectorShuffle(SVOp, DAG);
4167 SVOp = cast<ShuffleVectorSDNode>(Op);
4168 V1 = SVOp->getOperand(0);
4169 V2 = SVOp->getOperand(1);
4170 std::swap(V1IsSplat, V2IsSplat);
4171 std::swap(V1IsUndef, V2IsUndef);
4175 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4176 // Shuffling low element of v1 into undef, just return v1.
4179 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4180 // the instruction selector will not match, so get a canonical MOVL with
4181 // swapped operands to undo the commute.
4182 return getMOVL(DAG, dl, VT, V2, V1);
4185 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4186 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4187 X86::isUNPCKLMask(SVOp) ||
4188 X86::isUNPCKHMask(SVOp))
4192 // Normalize mask so all entries that point to V2 points to its first
4193 // element then try to match unpck{h|l} again. If match, return a
4194 // new vector_shuffle with the corrected mask.
4195 SDValue NewMask = NormalizeMask(SVOp, DAG);
4196 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4197 if (NSVOp != SVOp) {
4198 if (X86::isUNPCKLMask(NSVOp, true)) {
4200 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4207 // Commute is back and try unpck* again.
4208 // FIXME: this seems wrong.
4209 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4210 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4211 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4212 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4213 X86::isUNPCKLMask(NewSVOp) ||
4214 X86::isUNPCKHMask(NewSVOp))
4218 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4220 // Normalize the node to match x86 shuffle ops if needed
4221 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4222 return CommuteVectorShuffle(SVOp, DAG);
4224 // Check for legal shuffle and return?
4225 SmallVector<int, 16> PermMask;
4226 SVOp->getMask(PermMask);
4227 if (isShuffleMaskLegal(PermMask, VT))
4230 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4231 if (VT == MVT::v8i16) {
4232 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4233 if (NewOp.getNode())
4237 if (VT == MVT::v16i8) {
4238 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4239 if (NewOp.getNode())
4243 // Handle all 4 wide cases with a number of shuffles except for MMX.
4244 if (NumElems == 4 && !isMMX)
4245 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4251 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4252 SelectionDAG &DAG) {
4253 EVT VT = Op.getValueType();
4254 DebugLoc dl = Op.getDebugLoc();
4255 if (VT.getSizeInBits() == 8) {
4256 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4257 Op.getOperand(0), Op.getOperand(1));
4258 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4259 DAG.getValueType(VT));
4260 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4261 } else if (VT.getSizeInBits() == 16) {
4262 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4263 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4265 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4266 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4267 DAG.getNode(ISD::BIT_CONVERT, dl,
4271 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4272 Op.getOperand(0), Op.getOperand(1));
4273 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4274 DAG.getValueType(VT));
4275 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4276 } else if (VT == MVT::f32) {
4277 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4278 // the result back to FR32 register. It's only worth matching if the
4279 // result has a single use which is a store or a bitcast to i32. And in
4280 // the case of a store, it's not worth it if the index is a constant 0,
4281 // because a MOVSSmr can be used instead, which is smaller and faster.
4282 if (!Op.hasOneUse())
4284 SDNode *User = *Op.getNode()->use_begin();
4285 if ((User->getOpcode() != ISD::STORE ||
4286 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4287 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4288 (User->getOpcode() != ISD::BIT_CONVERT ||
4289 User->getValueType(0) != MVT::i32))
4291 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4292 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4295 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4296 } else if (VT == MVT::i32) {
4297 // ExtractPS works with constant index.
4298 if (isa<ConstantSDNode>(Op.getOperand(1)))
4306 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4307 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4310 if (Subtarget->hasSSE41()) {
4311 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4316 EVT VT = Op.getValueType();
4317 DebugLoc dl = Op.getDebugLoc();
4318 // TODO: handle v16i8.
4319 if (VT.getSizeInBits() == 16) {
4320 SDValue Vec = Op.getOperand(0);
4321 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4323 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4324 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4325 DAG.getNode(ISD::BIT_CONVERT, dl,
4328 // Transform it so it match pextrw which produces a 32-bit result.
4329 EVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
4330 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4331 Op.getOperand(0), Op.getOperand(1));
4332 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4333 DAG.getValueType(VT));
4334 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4335 } else if (VT.getSizeInBits() == 32) {
4336 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4340 // SHUFPS the element to the lowest double word, then movss.
4341 int Mask[4] = { Idx, -1, -1, -1 };
4342 EVT VVT = Op.getOperand(0).getValueType();
4343 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4344 DAG.getUNDEF(VVT), Mask);
4345 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4346 DAG.getIntPtrConstant(0));
4347 } else if (VT.getSizeInBits() == 64) {
4348 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4349 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4350 // to match extract_elt for f64.
4351 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4355 // UNPCKHPD the element to the lowest double word, then movsd.
4356 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4357 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4358 int Mask[2] = { 1, -1 };
4359 EVT VVT = Op.getOperand(0).getValueType();
4360 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4361 DAG.getUNDEF(VVT), Mask);
4362 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4363 DAG.getIntPtrConstant(0));
4370 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4371 EVT VT = Op.getValueType();
4372 EVT EVT = VT.getVectorElementType();
4373 DebugLoc dl = Op.getDebugLoc();
4375 SDValue N0 = Op.getOperand(0);
4376 SDValue N1 = Op.getOperand(1);
4377 SDValue N2 = Op.getOperand(2);
4379 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4380 isa<ConstantSDNode>(N2)) {
4381 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4383 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4385 if (N1.getValueType() != MVT::i32)
4386 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4387 if (N2.getValueType() != MVT::i32)
4388 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4389 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4390 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4391 // Bits [7:6] of the constant are the source select. This will always be
4392 // zero here. The DAG Combiner may combine an extract_elt index into these
4393 // bits. For example (insert (extract, 3), 2) could be matched by putting
4394 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4395 // Bits [5:4] of the constant are the destination select. This is the
4396 // value of the incoming immediate.
4397 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4398 // combine either bitwise AND or insert of float 0.0 to set these bits.
4399 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4400 // Create this as a scalar to vector..
4401 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4402 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4403 } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4404 // PINSR* works with constant index.
4411 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4412 EVT VT = Op.getValueType();
4413 EVT EVT = VT.getVectorElementType();
4415 if (Subtarget->hasSSE41())
4416 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4421 DebugLoc dl = Op.getDebugLoc();
4422 SDValue N0 = Op.getOperand(0);
4423 SDValue N1 = Op.getOperand(1);
4424 SDValue N2 = Op.getOperand(2);
4426 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4427 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4428 // as its second argument.
4429 if (N1.getValueType() != MVT::i32)
4430 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4431 if (N2.getValueType() != MVT::i32)
4432 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4433 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4439 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4440 DebugLoc dl = Op.getDebugLoc();
4441 if (Op.getValueType() == MVT::v2f32)
4442 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4443 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4444 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4445 Op.getOperand(0))));
4447 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4448 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4450 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4451 EVT VT = MVT::v2i32;
4452 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4459 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4460 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4463 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4464 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4465 // one of the above mentioned nodes. It has to be wrapped because otherwise
4466 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4467 // be used to form addressing mode. These wrapped nodes will be selected
4470 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4471 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4473 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4475 unsigned char OpFlag = 0;
4476 unsigned WrapperKind = X86ISD::Wrapper;
4477 CodeModel::Model M = getTargetMachine().getCodeModel();
4479 if (Subtarget->isPICStyleRIPRel() &&
4480 (M == CodeModel::Small || M == CodeModel::Kernel))
4481 WrapperKind = X86ISD::WrapperRIP;
4482 else if (Subtarget->isPICStyleGOT())
4483 OpFlag = X86II::MO_GOTOFF;
4484 else if (Subtarget->isPICStyleStubPIC())
4485 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4487 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4489 CP->getOffset(), OpFlag);
4490 DebugLoc DL = CP->getDebugLoc();
4491 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4492 // With PIC, the address is actually $g + Offset.
4494 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4495 DAG.getNode(X86ISD::GlobalBaseReg,
4496 DebugLoc::getUnknownLoc(), getPointerTy()),
4503 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4504 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4506 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4508 unsigned char OpFlag = 0;
4509 unsigned WrapperKind = X86ISD::Wrapper;
4510 CodeModel::Model M = getTargetMachine().getCodeModel();
4512 if (Subtarget->isPICStyleRIPRel() &&
4513 (M == CodeModel::Small || M == CodeModel::Kernel))
4514 WrapperKind = X86ISD::WrapperRIP;
4515 else if (Subtarget->isPICStyleGOT())
4516 OpFlag = X86II::MO_GOTOFF;
4517 else if (Subtarget->isPICStyleStubPIC())
4518 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4520 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4522 DebugLoc DL = JT->getDebugLoc();
4523 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4525 // With PIC, the address is actually $g + Offset.
4527 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4528 DAG.getNode(X86ISD::GlobalBaseReg,
4529 DebugLoc::getUnknownLoc(), getPointerTy()),
4537 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4538 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4540 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4542 unsigned char OpFlag = 0;
4543 unsigned WrapperKind = X86ISD::Wrapper;
4544 CodeModel::Model M = getTargetMachine().getCodeModel();
4546 if (Subtarget->isPICStyleRIPRel() &&
4547 (M == CodeModel::Small || M == CodeModel::Kernel))
4548 WrapperKind = X86ISD::WrapperRIP;
4549 else if (Subtarget->isPICStyleGOT())
4550 OpFlag = X86II::MO_GOTOFF;
4551 else if (Subtarget->isPICStyleStubPIC())
4552 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4554 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4556 DebugLoc DL = Op.getDebugLoc();
4557 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4560 // With PIC, the address is actually $g + Offset.
4561 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4562 !Subtarget->is64Bit()) {
4563 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4564 DAG.getNode(X86ISD::GlobalBaseReg,
4565 DebugLoc::getUnknownLoc(),
4574 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4576 SelectionDAG &DAG) const {
4577 // Create the TargetGlobalAddress node, folding in the constant
4578 // offset if it is legal.
4579 unsigned char OpFlags =
4580 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4581 CodeModel::Model M = getTargetMachine().getCodeModel();
4583 if (OpFlags == X86II::MO_NO_FLAG &&
4584 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4585 // A direct static reference to a global.
4586 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4589 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4592 if (Subtarget->isPICStyleRIPRel() &&
4593 (M == CodeModel::Small || M == CodeModel::Kernel))
4594 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4596 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4598 // With PIC, the address is actually $g + Offset.
4599 if (isGlobalRelativeToPICBase(OpFlags)) {
4600 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4601 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4605 // For globals that require a load from a stub to get the address, emit the
4607 if (isGlobalStubReference(OpFlags))
4608 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4609 PseudoSourceValue::getGOT(), 0);
4611 // If there was a non-zero offset that we didn't fold, create an explicit
4614 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4615 DAG.getConstant(Offset, getPointerTy()));
4621 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4622 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4623 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4624 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4628 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4629 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4630 unsigned char OperandFlags) {
4631 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4632 DebugLoc dl = GA->getDebugLoc();
4633 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4634 GA->getValueType(0),
4638 SDValue Ops[] = { Chain, TGA, *InFlag };
4639 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4641 SDValue Ops[] = { Chain, TGA };
4642 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4644 SDValue Flag = Chain.getValue(1);
4645 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4648 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4650 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4653 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4654 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4655 DAG.getNode(X86ISD::GlobalBaseReg,
4656 DebugLoc::getUnknownLoc(),
4658 InFlag = Chain.getValue(1);
4660 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4663 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4665 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4667 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4668 X86::RAX, X86II::MO_TLSGD);
4671 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4672 // "local exec" model.
4673 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4674 const EVT PtrVT, TLSModel::Model model,
4676 DebugLoc dl = GA->getDebugLoc();
4677 // Get the Thread Pointer
4678 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4679 DebugLoc::getUnknownLoc(), PtrVT,
4680 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4683 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4686 unsigned char OperandFlags = 0;
4687 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4689 unsigned WrapperKind = X86ISD::Wrapper;
4690 if (model == TLSModel::LocalExec) {
4691 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4692 } else if (is64Bit) {
4693 assert(model == TLSModel::InitialExec);
4694 OperandFlags = X86II::MO_GOTTPOFF;
4695 WrapperKind = X86ISD::WrapperRIP;
4697 assert(model == TLSModel::InitialExec);
4698 OperandFlags = X86II::MO_INDNTPOFF;
4701 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4703 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4704 GA->getOffset(), OperandFlags);
4705 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4707 if (model == TLSModel::InitialExec)
4708 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4709 PseudoSourceValue::getGOT(), 0);
4711 // The address of the thread local variable is the add of the thread
4712 // pointer with the offset of the variable.
4713 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4717 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4718 // TODO: implement the "local dynamic" model
4719 // TODO: implement the "initial exec"model for pic executables
4720 assert(Subtarget->isTargetELF() &&
4721 "TLS not implemented for non-ELF targets");
4722 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4723 const GlobalValue *GV = GA->getGlobal();
4725 // If GV is an alias then use the aliasee for determining
4726 // thread-localness.
4727 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4728 GV = GA->resolveAliasedGlobal(false);
4730 TLSModel::Model model = getTLSModel(GV,
4731 getTargetMachine().getRelocationModel());
4734 case TLSModel::GeneralDynamic:
4735 case TLSModel::LocalDynamic: // not implemented
4736 if (Subtarget->is64Bit())
4737 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4738 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4740 case TLSModel::InitialExec:
4741 case TLSModel::LocalExec:
4742 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4743 Subtarget->is64Bit());
4746 llvm_unreachable("Unreachable");
4751 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4752 /// take a 2 x i32 value to shift plus a shift amount.
4753 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4754 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4755 EVT VT = Op.getValueType();
4756 unsigned VTBits = VT.getSizeInBits();
4757 DebugLoc dl = Op.getDebugLoc();
4758 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4759 SDValue ShOpLo = Op.getOperand(0);
4760 SDValue ShOpHi = Op.getOperand(1);
4761 SDValue ShAmt = Op.getOperand(2);
4762 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4763 DAG.getConstant(VTBits - 1, MVT::i8))
4764 : DAG.getConstant(0, VT);
4767 if (Op.getOpcode() == ISD::SHL_PARTS) {
4768 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4769 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4771 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4772 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4775 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4776 DAG.getConstant(VTBits, MVT::i8));
4777 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4778 AndNode, DAG.getConstant(0, MVT::i8));
4781 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4782 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4783 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4785 if (Op.getOpcode() == ISD::SHL_PARTS) {
4786 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4787 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4789 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4790 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4793 SDValue Ops[2] = { Lo, Hi };
4794 return DAG.getMergeValues(Ops, 2, dl);
4797 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4798 EVT SrcVT = Op.getOperand(0).getValueType();
4800 if (SrcVT.isVector()) {
4801 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4807 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4808 "Unknown SINT_TO_FP to lower!");
4810 // These are really Legal; return the operand so the caller accepts it as
4812 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4814 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4815 Subtarget->is64Bit()) {
4819 DebugLoc dl = Op.getDebugLoc();
4820 unsigned Size = SrcVT.getSizeInBits()/8;
4821 MachineFunction &MF = DAG.getMachineFunction();
4822 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4823 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4824 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4826 PseudoSourceValue::getFixedStack(SSFI), 0);
4827 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4830 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
4832 SelectionDAG &DAG) {
4834 DebugLoc dl = Op.getDebugLoc();
4836 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4838 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4840 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4841 SmallVector<SDValue, 8> Ops;
4842 Ops.push_back(Chain);
4843 Ops.push_back(StackSlot);
4844 Ops.push_back(DAG.getValueType(SrcVT));
4845 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4846 Tys, &Ops[0], Ops.size());
4849 Chain = Result.getValue(1);
4850 SDValue InFlag = Result.getValue(2);
4852 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4853 // shouldn't be necessary except that RFP cannot be live across
4854 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4855 MachineFunction &MF = DAG.getMachineFunction();
4856 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4857 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4858 Tys = DAG.getVTList(MVT::Other);
4859 SmallVector<SDValue, 8> Ops;
4860 Ops.push_back(Chain);
4861 Ops.push_back(Result);
4862 Ops.push_back(StackSlot);
4863 Ops.push_back(DAG.getValueType(Op.getValueType()));
4864 Ops.push_back(InFlag);
4865 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4866 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4867 PseudoSourceValue::getFixedStack(SSFI), 0);
4873 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4874 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4875 // This algorithm is not obvious. Here it is in C code, more or less:
4877 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4878 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4879 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4881 // Copy ints to xmm registers.
4882 __m128i xh = _mm_cvtsi32_si128( hi );
4883 __m128i xl = _mm_cvtsi32_si128( lo );
4885 // Combine into low half of a single xmm register.
4886 __m128i x = _mm_unpacklo_epi32( xh, xl );
4890 // Merge in appropriate exponents to give the integer bits the right
4892 x = _mm_unpacklo_epi32( x, exp );
4894 // Subtract away the biases to deal with the IEEE-754 double precision
4896 d = _mm_sub_pd( (__m128d) x, bias );
4898 // All conversions up to here are exact. The correctly rounded result is
4899 // calculated using the current rounding mode using the following
4901 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4902 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4903 // store doesn't really need to be here (except
4904 // maybe to zero the other double)
4909 DebugLoc dl = Op.getDebugLoc();
4910 LLVMContext *Context = DAG.getContext();
4912 // Build some magic constants.
4913 std::vector<Constant*> CV0;
4914 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
4915 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
4916 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4917 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4918 Constant *C0 = ConstantVector::get(CV0);
4919 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
4921 std::vector<Constant*> CV1;
4923 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
4925 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
4926 Constant *C1 = ConstantVector::get(CV1);
4927 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
4929 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4930 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4932 DAG.getIntPtrConstant(1)));
4933 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4934 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4936 DAG.getIntPtrConstant(0)));
4937 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
4938 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
4939 PseudoSourceValue::getConstantPool(), 0,
4941 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
4942 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4943 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
4944 PseudoSourceValue::getConstantPool(), 0,
4946 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
4948 // Add the halves; easiest way is to swap them into another reg first.
4949 int ShufMask[2] = { 1, -1 };
4950 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
4951 DAG.getUNDEF(MVT::v2f64), ShufMask);
4952 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4953 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
4954 DAG.getIntPtrConstant(0));
4957 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4958 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4959 DebugLoc dl = Op.getDebugLoc();
4960 // FP constant to bias correct the final result.
4961 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4964 // Load the 32-bit value into an XMM register.
4965 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4966 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4968 DAG.getIntPtrConstant(0)));
4970 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4971 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
4972 DAG.getIntPtrConstant(0));
4974 // Or the load with the bias.
4975 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
4976 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4977 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4979 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4980 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4981 MVT::v2f64, Bias)));
4982 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4983 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
4984 DAG.getIntPtrConstant(0));
4986 // Subtract the bias.
4987 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
4989 // Handle final rounding.
4990 EVT DestVT = Op.getValueType();
4992 if (DestVT.bitsLT(MVT::f64)) {
4993 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
4994 DAG.getIntPtrConstant(0));
4995 } else if (DestVT.bitsGT(MVT::f64)) {
4996 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
4999 // Handle final rounding.
5003 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5004 SDValue N0 = Op.getOperand(0);
5005 DebugLoc dl = Op.getDebugLoc();
5007 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5008 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5009 // the optimization here.
5010 if (DAG.SignBitIsZero(N0))
5011 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5013 EVT SrcVT = N0.getValueType();
5014 if (SrcVT == MVT::i64) {
5015 // We only handle SSE2 f64 target here; caller can expand the rest.
5016 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5019 return LowerUINT_TO_FP_i64(Op, DAG);
5020 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5021 return LowerUINT_TO_FP_i32(Op, DAG);
5024 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5026 // Make a 64-bit buffer, and use it to build an FILD.
5027 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5028 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5029 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5030 getPointerTy(), StackSlot, WordOff);
5031 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5032 StackSlot, NULL, 0);
5033 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5034 OffsetSlot, NULL, 0);
5035 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5038 std::pair<SDValue,SDValue> X86TargetLowering::
5039 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5040 DebugLoc dl = Op.getDebugLoc();
5042 EVT DstTy = Op.getValueType();
5045 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5049 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5050 DstTy.getSimpleVT() >= MVT::i16 &&
5051 "Unknown FP_TO_SINT to lower!");
5053 // These are really Legal.
5054 if (DstTy == MVT::i32 &&
5055 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5056 return std::make_pair(SDValue(), SDValue());
5057 if (Subtarget->is64Bit() &&
5058 DstTy == MVT::i64 &&
5059 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5060 return std::make_pair(SDValue(), SDValue());
5062 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5064 MachineFunction &MF = DAG.getMachineFunction();
5065 unsigned MemSize = DstTy.getSizeInBits()/8;
5066 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5067 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5070 switch (DstTy.getSimpleVT().SimpleTy) {
5071 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5072 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5073 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5074 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5077 SDValue Chain = DAG.getEntryNode();
5078 SDValue Value = Op.getOperand(0);
5079 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5080 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5081 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5082 PseudoSourceValue::getFixedStack(SSFI), 0);
5083 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5085 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5087 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5088 Chain = Value.getValue(1);
5089 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5090 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5093 // Build the FP_TO_INT*_IN_MEM
5094 SDValue Ops[] = { Chain, Value, StackSlot };
5095 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5097 return std::make_pair(FIST, StackSlot);
5100 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5101 if (Op.getValueType().isVector()) {
5102 if (Op.getValueType() == MVT::v2i32 &&
5103 Op.getOperand(0).getValueType() == MVT::v2f64) {
5109 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5110 SDValue FIST = Vals.first, StackSlot = Vals.second;
5111 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5112 if (FIST.getNode() == 0) return Op;
5115 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5116 FIST, StackSlot, NULL, 0);
5119 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5120 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5121 SDValue FIST = Vals.first, StackSlot = Vals.second;
5122 assert(FIST.getNode() && "Unexpected failure");
5125 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5126 FIST, StackSlot, NULL, 0);
5129 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5130 LLVMContext *Context = DAG.getContext();
5131 DebugLoc dl = Op.getDebugLoc();
5132 EVT VT = Op.getValueType();
5135 EltVT = VT.getVectorElementType();
5136 std::vector<Constant*> CV;
5137 if (EltVT == MVT::f64) {
5138 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5142 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5148 Constant *C = ConstantVector::get(CV);
5149 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5150 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5151 PseudoSourceValue::getConstantPool(), 0,
5153 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5156 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5157 LLVMContext *Context = DAG.getContext();
5158 DebugLoc dl = Op.getDebugLoc();
5159 EVT VT = Op.getValueType();
5161 unsigned EltNum = 1;
5162 if (VT.isVector()) {
5163 EltVT = VT.getVectorElementType();
5164 EltNum = VT.getVectorNumElements();
5166 std::vector<Constant*> CV;
5167 if (EltVT == MVT::f64) {
5168 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5172 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5178 Constant *C = ConstantVector::get(CV);
5179 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5180 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5181 PseudoSourceValue::getConstantPool(), 0,
5183 if (VT.isVector()) {
5184 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5185 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5186 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5188 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5190 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5194 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5195 LLVMContext *Context = DAG.getContext();
5196 SDValue Op0 = Op.getOperand(0);
5197 SDValue Op1 = Op.getOperand(1);
5198 DebugLoc dl = Op.getDebugLoc();
5199 EVT VT = Op.getValueType();
5200 EVT SrcVT = Op1.getValueType();
5202 // If second operand is smaller, extend it first.
5203 if (SrcVT.bitsLT(VT)) {
5204 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5207 // And if it is bigger, shrink it first.
5208 if (SrcVT.bitsGT(VT)) {
5209 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5213 // At this point the operands and the result should have the same
5214 // type, and that won't be f80 since that is not custom lowered.
5216 // First get the sign bit of second operand.
5217 std::vector<Constant*> CV;
5218 if (SrcVT == MVT::f64) {
5219 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5220 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5222 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5223 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5224 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5225 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5227 Constant *C = ConstantVector::get(CV);
5228 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5229 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5230 PseudoSourceValue::getConstantPool(), 0,
5232 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5234 // Shift sign bit right or left if the two operands have different types.
5235 if (SrcVT.bitsGT(VT)) {
5236 // Op0 is MVT::f32, Op1 is MVT::f64.
5237 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5238 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5239 DAG.getConstant(32, MVT::i32));
5240 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5241 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5242 DAG.getIntPtrConstant(0));
5245 // Clear first operand sign bit.
5247 if (VT == MVT::f64) {
5248 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5249 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5251 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5252 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5253 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5254 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5256 C = ConstantVector::get(CV);
5257 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5258 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5259 PseudoSourceValue::getConstantPool(), 0,
5261 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5263 // Or the value with the sign bit.
5264 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5267 /// Emit nodes that will be selected as "test Op0,Op0", or something
5269 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5270 SelectionDAG &DAG) {
5271 DebugLoc dl = Op.getDebugLoc();
5273 // CF and OF aren't always set the way we want. Determine which
5274 // of these we need.
5275 bool NeedCF = false;
5276 bool NeedOF = false;
5278 case X86::COND_A: case X86::COND_AE:
5279 case X86::COND_B: case X86::COND_BE:
5282 case X86::COND_G: case X86::COND_GE:
5283 case X86::COND_L: case X86::COND_LE:
5284 case X86::COND_O: case X86::COND_NO:
5290 // See if we can use the EFLAGS value from the operand instead of
5291 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5292 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5293 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5294 unsigned Opcode = 0;
5295 unsigned NumOperands = 0;
5296 switch (Op.getNode()->getOpcode()) {
5298 // Due to an isel shortcoming, be conservative if this add is likely to
5299 // be selected as part of a load-modify-store instruction. When the root
5300 // node in a match is a store, isel doesn't know how to remap non-chain
5301 // non-flag uses of other nodes in the match, such as the ADD in this
5302 // case. This leads to the ADD being left around and reselected, with
5303 // the result being two adds in the output.
5304 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5305 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5306 if (UI->getOpcode() == ISD::STORE)
5308 if (ConstantSDNode *C =
5309 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5310 // An add of one will be selected as an INC.
5311 if (C->getAPIntValue() == 1) {
5312 Opcode = X86ISD::INC;
5316 // An add of negative one (subtract of one) will be selected as a DEC.
5317 if (C->getAPIntValue().isAllOnesValue()) {
5318 Opcode = X86ISD::DEC;
5323 // Otherwise use a regular EFLAGS-setting add.
5324 Opcode = X86ISD::ADD;
5328 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5329 // likely to be selected as part of a load-modify-store instruction.
5330 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5331 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5332 if (UI->getOpcode() == ISD::STORE)
5334 // Otherwise use a regular EFLAGS-setting sub.
5335 Opcode = X86ISD::SUB;
5342 return SDValue(Op.getNode(), 1);
5348 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5349 SmallVector<SDValue, 4> Ops;
5350 for (unsigned i = 0; i != NumOperands; ++i)
5351 Ops.push_back(Op.getOperand(i));
5352 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5353 DAG.ReplaceAllUsesWith(Op, New);
5354 return SDValue(New.getNode(), 1);
5358 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5359 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5360 DAG.getConstant(0, Op.getValueType()));
5363 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5365 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5366 SelectionDAG &DAG) {
5367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5368 if (C->getAPIntValue() == 0)
5369 return EmitTest(Op0, X86CC, DAG);
5371 DebugLoc dl = Op0.getDebugLoc();
5372 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5375 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5376 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5377 SDValue Op0 = Op.getOperand(0);
5378 SDValue Op1 = Op.getOperand(1);
5379 DebugLoc dl = Op.getDebugLoc();
5380 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5382 // Lower (X & (1 << N)) == 0 to BT(X, N).
5383 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5384 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5385 if (Op0.getOpcode() == ISD::AND &&
5387 Op1.getOpcode() == ISD::Constant &&
5388 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5389 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5391 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5392 if (ConstantSDNode *Op010C =
5393 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5394 if (Op010C->getZExtValue() == 1) {
5395 LHS = Op0.getOperand(0);
5396 RHS = Op0.getOperand(1).getOperand(1);
5398 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5399 if (ConstantSDNode *Op000C =
5400 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5401 if (Op000C->getZExtValue() == 1) {
5402 LHS = Op0.getOperand(1);
5403 RHS = Op0.getOperand(0).getOperand(1);
5405 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5406 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5407 SDValue AndLHS = Op0.getOperand(0);
5408 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5409 LHS = AndLHS.getOperand(0);
5410 RHS = AndLHS.getOperand(1);
5414 if (LHS.getNode()) {
5415 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5416 // instruction. Since the shift amount is in-range-or-undefined, we know
5417 // that doing a bittest on the i16 value is ok. We extend to i32 because
5418 // the encoding for the i16 version is larger than the i32 version.
5419 if (LHS.getValueType() == MVT::i8)
5420 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5422 // If the operand types disagree, extend the shift amount to match. Since
5423 // BT ignores high bits (like shifts) we can use anyextend.
5424 if (LHS.getValueType() != RHS.getValueType())
5425 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5427 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5428 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5429 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5430 DAG.getConstant(Cond, MVT::i8), BT);
5434 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5435 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5437 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5438 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5439 DAG.getConstant(X86CC, MVT::i8), Cond);
5442 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5444 SDValue Op0 = Op.getOperand(0);
5445 SDValue Op1 = Op.getOperand(1);
5446 SDValue CC = Op.getOperand(2);
5447 EVT VT = Op.getValueType();
5448 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5449 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5450 DebugLoc dl = Op.getDebugLoc();
5454 EVT VT0 = Op0.getValueType();
5455 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5456 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5459 switch (SetCCOpcode) {
5462 case ISD::SETEQ: SSECC = 0; break;
5464 case ISD::SETGT: Swap = true; // Fallthrough
5466 case ISD::SETOLT: SSECC = 1; break;
5468 case ISD::SETGE: Swap = true; // Fallthrough
5470 case ISD::SETOLE: SSECC = 2; break;
5471 case ISD::SETUO: SSECC = 3; break;
5473 case ISD::SETNE: SSECC = 4; break;
5474 case ISD::SETULE: Swap = true;
5475 case ISD::SETUGE: SSECC = 5; break;
5476 case ISD::SETULT: Swap = true;
5477 case ISD::SETUGT: SSECC = 6; break;
5478 case ISD::SETO: SSECC = 7; break;
5481 std::swap(Op0, Op1);
5483 // In the two special cases we can't handle, emit two comparisons.
5485 if (SetCCOpcode == ISD::SETUEQ) {
5487 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5488 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5489 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5491 else if (SetCCOpcode == ISD::SETONE) {
5493 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5494 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5495 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5497 llvm_unreachable("Illegal FP comparison");
5499 // Handle all other FP comparisons here.
5500 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5503 // We are handling one of the integer comparisons here. Since SSE only has
5504 // GT and EQ comparisons for integer, swapping operands and multiple
5505 // operations may be required for some comparisons.
5506 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5507 bool Swap = false, Invert = false, FlipSigns = false;
5509 switch (VT.getSimpleVT().SimpleTy) {
5512 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5514 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5516 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5517 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5520 switch (SetCCOpcode) {
5522 case ISD::SETNE: Invert = true;
5523 case ISD::SETEQ: Opc = EQOpc; break;
5524 case ISD::SETLT: Swap = true;
5525 case ISD::SETGT: Opc = GTOpc; break;
5526 case ISD::SETGE: Swap = true;
5527 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5528 case ISD::SETULT: Swap = true;
5529 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5530 case ISD::SETUGE: Swap = true;
5531 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5534 std::swap(Op0, Op1);
5536 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5537 // bits of the inputs before performing those operations.
5539 EVT EltVT = VT.getVectorElementType();
5540 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5542 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5543 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5545 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5546 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5549 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5551 // If the logical-not of the result is required, perform that now.
5553 Result = DAG.getNOT(dl, Result, VT);
5558 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5559 static bool isX86LogicalCmp(SDValue Op) {
5560 unsigned Opc = Op.getNode()->getOpcode();
5561 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5563 if (Op.getResNo() == 1 &&
5564 (Opc == X86ISD::ADD ||
5565 Opc == X86ISD::SUB ||
5566 Opc == X86ISD::SMUL ||
5567 Opc == X86ISD::UMUL ||
5568 Opc == X86ISD::INC ||
5569 Opc == X86ISD::DEC))
5575 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5576 bool addTest = true;
5577 SDValue Cond = Op.getOperand(0);
5578 DebugLoc dl = Op.getDebugLoc();
5581 if (Cond.getOpcode() == ISD::SETCC)
5582 Cond = LowerSETCC(Cond, DAG);
5584 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5585 // setting operand in place of the X86ISD::SETCC.
5586 if (Cond.getOpcode() == X86ISD::SETCC) {
5587 CC = Cond.getOperand(0);
5589 SDValue Cmp = Cond.getOperand(1);
5590 unsigned Opc = Cmp.getOpcode();
5591 EVT VT = Op.getValueType();
5593 bool IllegalFPCMov = false;
5594 if (VT.isFloatingPoint() && !VT.isVector() &&
5595 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5596 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5598 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5599 Opc == X86ISD::BT) { // FIXME
5606 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5607 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5610 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5611 SmallVector<SDValue, 4> Ops;
5612 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5613 // condition is true.
5614 Ops.push_back(Op.getOperand(2));
5615 Ops.push_back(Op.getOperand(1));
5617 Ops.push_back(Cond);
5618 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5621 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5622 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5623 // from the AND / OR.
5624 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5625 Opc = Op.getOpcode();
5626 if (Opc != ISD::OR && Opc != ISD::AND)
5628 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5629 Op.getOperand(0).hasOneUse() &&
5630 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5631 Op.getOperand(1).hasOneUse());
5634 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5635 // 1 and that the SETCC node has a single use.
5636 static bool isXor1OfSetCC(SDValue Op) {
5637 if (Op.getOpcode() != ISD::XOR)
5639 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5640 if (N1C && N1C->getAPIntValue() == 1) {
5641 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5642 Op.getOperand(0).hasOneUse();
5647 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5648 bool addTest = true;
5649 SDValue Chain = Op.getOperand(0);
5650 SDValue Cond = Op.getOperand(1);
5651 SDValue Dest = Op.getOperand(2);
5652 DebugLoc dl = Op.getDebugLoc();
5655 if (Cond.getOpcode() == ISD::SETCC)
5656 Cond = LowerSETCC(Cond, DAG);
5658 // FIXME: LowerXALUO doesn't handle these!!
5659 else if (Cond.getOpcode() == X86ISD::ADD ||
5660 Cond.getOpcode() == X86ISD::SUB ||
5661 Cond.getOpcode() == X86ISD::SMUL ||
5662 Cond.getOpcode() == X86ISD::UMUL)
5663 Cond = LowerXALUO(Cond, DAG);
5666 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5667 // setting operand in place of the X86ISD::SETCC.
5668 if (Cond.getOpcode() == X86ISD::SETCC) {
5669 CC = Cond.getOperand(0);
5671 SDValue Cmp = Cond.getOperand(1);
5672 unsigned Opc = Cmp.getOpcode();
5673 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5674 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5678 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5682 // These can only come from an arithmetic instruction with overflow,
5683 // e.g. SADDO, UADDO.
5684 Cond = Cond.getNode()->getOperand(1);
5691 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5692 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5693 if (CondOpc == ISD::OR) {
5694 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5695 // two branches instead of an explicit OR instruction with a
5697 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5698 isX86LogicalCmp(Cmp)) {
5699 CC = Cond.getOperand(0).getOperand(0);
5700 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5701 Chain, Dest, CC, Cmp);
5702 CC = Cond.getOperand(1).getOperand(0);
5706 } else { // ISD::AND
5707 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5708 // two branches instead of an explicit AND instruction with a
5709 // separate test. However, we only do this if this block doesn't
5710 // have a fall-through edge, because this requires an explicit
5711 // jmp when the condition is false.
5712 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5713 isX86LogicalCmp(Cmp) &&
5714 Op.getNode()->hasOneUse()) {
5715 X86::CondCode CCode =
5716 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5717 CCode = X86::GetOppositeBranchCondition(CCode);
5718 CC = DAG.getConstant(CCode, MVT::i8);
5719 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5720 // Look for an unconditional branch following this conditional branch.
5721 // We need this because we need to reverse the successors in order
5722 // to implement FCMP_OEQ.
5723 if (User.getOpcode() == ISD::BR) {
5724 SDValue FalseBB = User.getOperand(1);
5726 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5727 assert(NewBR == User);
5730 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5731 Chain, Dest, CC, Cmp);
5732 X86::CondCode CCode =
5733 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5734 CCode = X86::GetOppositeBranchCondition(CCode);
5735 CC = DAG.getConstant(CCode, MVT::i8);
5741 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5742 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5743 // It should be transformed during dag combiner except when the condition
5744 // is set by a arithmetics with overflow node.
5745 X86::CondCode CCode =
5746 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5747 CCode = X86::GetOppositeBranchCondition(CCode);
5748 CC = DAG.getConstant(CCode, MVT::i8);
5749 Cond = Cond.getOperand(0).getOperand(1);
5755 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5756 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5758 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5759 Chain, Dest, CC, Cond);
5763 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5764 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5765 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5766 // that the guard pages used by the OS virtual memory manager are allocated in
5767 // correct sequence.
5769 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5770 SelectionDAG &DAG) {
5771 assert(Subtarget->isTargetCygMing() &&
5772 "This should be used only on Cygwin/Mingw targets");
5773 DebugLoc dl = Op.getDebugLoc();
5776 SDValue Chain = Op.getOperand(0);
5777 SDValue Size = Op.getOperand(1);
5778 // FIXME: Ensure alignment here
5782 EVT IntPtr = getPointerTy();
5783 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5785 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5787 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5788 Flag = Chain.getValue(1);
5790 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5791 SDValue Ops[] = { Chain,
5792 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5793 DAG.getRegister(X86::EAX, IntPtr),
5794 DAG.getRegister(X86StackPtr, SPTy),
5796 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5797 Flag = Chain.getValue(1);
5799 Chain = DAG.getCALLSEQ_END(Chain,
5800 DAG.getIntPtrConstant(0, true),
5801 DAG.getIntPtrConstant(0, true),
5804 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5806 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5807 return DAG.getMergeValues(Ops1, 2, dl);
5811 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5813 SDValue Dst, SDValue Src,
5814 SDValue Size, unsigned Align,
5816 uint64_t DstSVOff) {
5817 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5819 // If not DWORD aligned or size is more than the threshold, call the library.
5820 // The libc version is likely to be faster for these cases. It can use the
5821 // address value and run time information about the CPU.
5822 if ((Align & 3) != 0 ||
5824 ConstantSize->getZExtValue() >
5825 getSubtarget()->getMaxInlineSizeThreshold()) {
5826 SDValue InFlag(0, 0);
5828 // Check to see if there is a specialized entry-point for memory zeroing.
5829 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5831 if (const char *bzeroEntry = V &&
5832 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5833 EVT IntPtr = getPointerTy();
5834 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
5835 TargetLowering::ArgListTy Args;
5836 TargetLowering::ArgListEntry Entry;
5838 Entry.Ty = IntPtrTy;
5839 Args.push_back(Entry);
5841 Args.push_back(Entry);
5842 std::pair<SDValue,SDValue> CallResult =
5843 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
5844 false, false, false, false,
5845 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
5846 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5847 return CallResult.second;
5850 // Otherwise have the target-independent code call memset.
5854 uint64_t SizeVal = ConstantSize->getZExtValue();
5855 SDValue InFlag(0, 0);
5858 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5859 unsigned BytesLeft = 0;
5860 bool TwoRepStos = false;
5863 uint64_t Val = ValC->getZExtValue() & 255;
5865 // If the value is a constant, then we can potentially use larger sets.
5866 switch (Align & 3) {
5867 case 2: // WORD aligned
5870 Val = (Val << 8) | Val;
5872 case 0: // DWORD aligned
5875 Val = (Val << 8) | Val;
5876 Val = (Val << 16) | Val;
5877 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5880 Val = (Val << 32) | Val;
5883 default: // Byte aligned
5886 Count = DAG.getIntPtrConstant(SizeVal);
5890 if (AVT.bitsGT(MVT::i8)) {
5891 unsigned UBytes = AVT.getSizeInBits() / 8;
5892 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5893 BytesLeft = SizeVal % UBytes;
5896 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5898 InFlag = Chain.getValue(1);
5901 Count = DAG.getIntPtrConstant(SizeVal);
5902 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5903 InFlag = Chain.getValue(1);
5906 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5909 InFlag = Chain.getValue(1);
5910 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5913 InFlag = Chain.getValue(1);
5915 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5916 SmallVector<SDValue, 8> Ops;
5917 Ops.push_back(Chain);
5918 Ops.push_back(DAG.getValueType(AVT));
5919 Ops.push_back(InFlag);
5920 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5923 InFlag = Chain.getValue(1);
5925 EVT CVT = Count.getValueType();
5926 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5927 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5928 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
5931 InFlag = Chain.getValue(1);
5932 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5934 Ops.push_back(Chain);
5935 Ops.push_back(DAG.getValueType(MVT::i8));
5936 Ops.push_back(InFlag);
5937 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5938 } else if (BytesLeft) {
5939 // Handle the last 1 - 7 bytes.
5940 unsigned Offset = SizeVal - BytesLeft;
5941 EVT AddrVT = Dst.getValueType();
5942 EVT SizeVT = Size.getValueType();
5944 Chain = DAG.getMemset(Chain, dl,
5945 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
5946 DAG.getConstant(Offset, AddrVT)),
5948 DAG.getConstant(BytesLeft, SizeVT),
5949 Align, DstSV, DstSVOff + Offset);
5952 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5957 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
5958 SDValue Chain, SDValue Dst, SDValue Src,
5959 SDValue Size, unsigned Align,
5961 const Value *DstSV, uint64_t DstSVOff,
5962 const Value *SrcSV, uint64_t SrcSVOff) {
5963 // This requires the copy size to be a constant, preferrably
5964 // within a subtarget-specific limit.
5965 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5968 uint64_t SizeVal = ConstantSize->getZExtValue();
5969 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5972 /// If not DWORD aligned, call the library.
5973 if ((Align & 3) != 0)
5978 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5981 unsigned UBytes = AVT.getSizeInBits() / 8;
5982 unsigned CountVal = SizeVal / UBytes;
5983 SDValue Count = DAG.getIntPtrConstant(CountVal);
5984 unsigned BytesLeft = SizeVal % UBytes;
5986 SDValue InFlag(0, 0);
5987 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5990 InFlag = Chain.getValue(1);
5991 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5994 InFlag = Chain.getValue(1);
5995 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
5998 InFlag = Chain.getValue(1);
6000 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6001 SmallVector<SDValue, 8> Ops;
6002 Ops.push_back(Chain);
6003 Ops.push_back(DAG.getValueType(AVT));
6004 Ops.push_back(InFlag);
6005 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6007 SmallVector<SDValue, 4> Results;
6008 Results.push_back(RepMovs);
6010 // Handle the last 1 - 7 bytes.
6011 unsigned Offset = SizeVal - BytesLeft;
6012 EVT DstVT = Dst.getValueType();
6013 EVT SrcVT = Src.getValueType();
6014 EVT SizeVT = Size.getValueType();
6015 Results.push_back(DAG.getMemcpy(Chain, dl,
6016 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6017 DAG.getConstant(Offset, DstVT)),
6018 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6019 DAG.getConstant(Offset, SrcVT)),
6020 DAG.getConstant(BytesLeft, SizeVT),
6021 Align, AlwaysInline,
6022 DstSV, DstSVOff + Offset,
6023 SrcSV, SrcSVOff + Offset));
6026 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6027 &Results[0], Results.size());
6030 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6031 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6032 DebugLoc dl = Op.getDebugLoc();
6034 if (!Subtarget->is64Bit()) {
6035 // vastart just stores the address of the VarArgsFrameIndex slot into the
6036 // memory location argument.
6037 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6038 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6042 // gp_offset (0 - 6 * 8)
6043 // fp_offset (48 - 48 + 8 * 16)
6044 // overflow_arg_area (point to parameters coming in memory).
6046 SmallVector<SDValue, 8> MemOps;
6047 SDValue FIN = Op.getOperand(1);
6049 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6050 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6052 MemOps.push_back(Store);
6055 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6056 FIN, DAG.getIntPtrConstant(4));
6057 Store = DAG.getStore(Op.getOperand(0), dl,
6058 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6060 MemOps.push_back(Store);
6062 // Store ptr to overflow_arg_area
6063 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6064 FIN, DAG.getIntPtrConstant(4));
6065 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6066 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6067 MemOps.push_back(Store);
6069 // Store ptr to reg_save_area.
6070 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6071 FIN, DAG.getIntPtrConstant(8));
6072 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6073 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6074 MemOps.push_back(Store);
6075 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6076 &MemOps[0], MemOps.size());
6079 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6080 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6081 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6082 SDValue Chain = Op.getOperand(0);
6083 SDValue SrcPtr = Op.getOperand(1);
6084 SDValue SrcSV = Op.getOperand(2);
6086 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6090 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6091 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6092 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6093 SDValue Chain = Op.getOperand(0);
6094 SDValue DstPtr = Op.getOperand(1);
6095 SDValue SrcPtr = Op.getOperand(2);
6096 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6097 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6098 DebugLoc dl = Op.getDebugLoc();
6100 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6101 DAG.getIntPtrConstant(24), 8, false,
6102 DstSV, 0, SrcSV, 0);
6106 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6107 DebugLoc dl = Op.getDebugLoc();
6108 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6110 default: return SDValue(); // Don't custom lower most intrinsics.
6111 // Comparison intrinsics.
6112 case Intrinsic::x86_sse_comieq_ss:
6113 case Intrinsic::x86_sse_comilt_ss:
6114 case Intrinsic::x86_sse_comile_ss:
6115 case Intrinsic::x86_sse_comigt_ss:
6116 case Intrinsic::x86_sse_comige_ss:
6117 case Intrinsic::x86_sse_comineq_ss:
6118 case Intrinsic::x86_sse_ucomieq_ss:
6119 case Intrinsic::x86_sse_ucomilt_ss:
6120 case Intrinsic::x86_sse_ucomile_ss:
6121 case Intrinsic::x86_sse_ucomigt_ss:
6122 case Intrinsic::x86_sse_ucomige_ss:
6123 case Intrinsic::x86_sse_ucomineq_ss:
6124 case Intrinsic::x86_sse2_comieq_sd:
6125 case Intrinsic::x86_sse2_comilt_sd:
6126 case Intrinsic::x86_sse2_comile_sd:
6127 case Intrinsic::x86_sse2_comigt_sd:
6128 case Intrinsic::x86_sse2_comige_sd:
6129 case Intrinsic::x86_sse2_comineq_sd:
6130 case Intrinsic::x86_sse2_ucomieq_sd:
6131 case Intrinsic::x86_sse2_ucomilt_sd:
6132 case Intrinsic::x86_sse2_ucomile_sd:
6133 case Intrinsic::x86_sse2_ucomigt_sd:
6134 case Intrinsic::x86_sse2_ucomige_sd:
6135 case Intrinsic::x86_sse2_ucomineq_sd: {
6137 ISD::CondCode CC = ISD::SETCC_INVALID;
6140 case Intrinsic::x86_sse_comieq_ss:
6141 case Intrinsic::x86_sse2_comieq_sd:
6145 case Intrinsic::x86_sse_comilt_ss:
6146 case Intrinsic::x86_sse2_comilt_sd:
6150 case Intrinsic::x86_sse_comile_ss:
6151 case Intrinsic::x86_sse2_comile_sd:
6155 case Intrinsic::x86_sse_comigt_ss:
6156 case Intrinsic::x86_sse2_comigt_sd:
6160 case Intrinsic::x86_sse_comige_ss:
6161 case Intrinsic::x86_sse2_comige_sd:
6165 case Intrinsic::x86_sse_comineq_ss:
6166 case Intrinsic::x86_sse2_comineq_sd:
6170 case Intrinsic::x86_sse_ucomieq_ss:
6171 case Intrinsic::x86_sse2_ucomieq_sd:
6172 Opc = X86ISD::UCOMI;
6175 case Intrinsic::x86_sse_ucomilt_ss:
6176 case Intrinsic::x86_sse2_ucomilt_sd:
6177 Opc = X86ISD::UCOMI;
6180 case Intrinsic::x86_sse_ucomile_ss:
6181 case Intrinsic::x86_sse2_ucomile_sd:
6182 Opc = X86ISD::UCOMI;
6185 case Intrinsic::x86_sse_ucomigt_ss:
6186 case Intrinsic::x86_sse2_ucomigt_sd:
6187 Opc = X86ISD::UCOMI;
6190 case Intrinsic::x86_sse_ucomige_ss:
6191 case Intrinsic::x86_sse2_ucomige_sd:
6192 Opc = X86ISD::UCOMI;
6195 case Intrinsic::x86_sse_ucomineq_ss:
6196 case Intrinsic::x86_sse2_ucomineq_sd:
6197 Opc = X86ISD::UCOMI;
6202 SDValue LHS = Op.getOperand(1);
6203 SDValue RHS = Op.getOperand(2);
6204 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6205 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6206 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6207 DAG.getConstant(X86CC, MVT::i8), Cond);
6208 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6210 // ptest intrinsics. The intrinsic these come from are designed to return
6211 // an integer value, not just an instruction so lower it to the ptest
6212 // pattern and a setcc for the result.
6213 case Intrinsic::x86_sse41_ptestz:
6214 case Intrinsic::x86_sse41_ptestc:
6215 case Intrinsic::x86_sse41_ptestnzc:{
6218 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6219 case Intrinsic::x86_sse41_ptestz:
6221 X86CC = X86::COND_E;
6223 case Intrinsic::x86_sse41_ptestc:
6225 X86CC = X86::COND_B;
6227 case Intrinsic::x86_sse41_ptestnzc:
6229 X86CC = X86::COND_A;
6233 SDValue LHS = Op.getOperand(1);
6234 SDValue RHS = Op.getOperand(2);
6235 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6236 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6237 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6238 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6241 // Fix vector shift instructions where the last operand is a non-immediate
6243 case Intrinsic::x86_sse2_pslli_w:
6244 case Intrinsic::x86_sse2_pslli_d:
6245 case Intrinsic::x86_sse2_pslli_q:
6246 case Intrinsic::x86_sse2_psrli_w:
6247 case Intrinsic::x86_sse2_psrli_d:
6248 case Intrinsic::x86_sse2_psrli_q:
6249 case Intrinsic::x86_sse2_psrai_w:
6250 case Intrinsic::x86_sse2_psrai_d:
6251 case Intrinsic::x86_mmx_pslli_w:
6252 case Intrinsic::x86_mmx_pslli_d:
6253 case Intrinsic::x86_mmx_pslli_q:
6254 case Intrinsic::x86_mmx_psrli_w:
6255 case Intrinsic::x86_mmx_psrli_d:
6256 case Intrinsic::x86_mmx_psrli_q:
6257 case Intrinsic::x86_mmx_psrai_w:
6258 case Intrinsic::x86_mmx_psrai_d: {
6259 SDValue ShAmt = Op.getOperand(2);
6260 if (isa<ConstantSDNode>(ShAmt))
6263 unsigned NewIntNo = 0;
6264 EVT ShAmtVT = MVT::v4i32;
6266 case Intrinsic::x86_sse2_pslli_w:
6267 NewIntNo = Intrinsic::x86_sse2_psll_w;
6269 case Intrinsic::x86_sse2_pslli_d:
6270 NewIntNo = Intrinsic::x86_sse2_psll_d;
6272 case Intrinsic::x86_sse2_pslli_q:
6273 NewIntNo = Intrinsic::x86_sse2_psll_q;
6275 case Intrinsic::x86_sse2_psrli_w:
6276 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6278 case Intrinsic::x86_sse2_psrli_d:
6279 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6281 case Intrinsic::x86_sse2_psrli_q:
6282 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6284 case Intrinsic::x86_sse2_psrai_w:
6285 NewIntNo = Intrinsic::x86_sse2_psra_w;
6287 case Intrinsic::x86_sse2_psrai_d:
6288 NewIntNo = Intrinsic::x86_sse2_psra_d;
6291 ShAmtVT = MVT::v2i32;
6293 case Intrinsic::x86_mmx_pslli_w:
6294 NewIntNo = Intrinsic::x86_mmx_psll_w;
6296 case Intrinsic::x86_mmx_pslli_d:
6297 NewIntNo = Intrinsic::x86_mmx_psll_d;
6299 case Intrinsic::x86_mmx_pslli_q:
6300 NewIntNo = Intrinsic::x86_mmx_psll_q;
6302 case Intrinsic::x86_mmx_psrli_w:
6303 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6305 case Intrinsic::x86_mmx_psrli_d:
6306 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6308 case Intrinsic::x86_mmx_psrli_q:
6309 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6311 case Intrinsic::x86_mmx_psrai_w:
6312 NewIntNo = Intrinsic::x86_mmx_psra_w;
6314 case Intrinsic::x86_mmx_psrai_d:
6315 NewIntNo = Intrinsic::x86_mmx_psra_d;
6317 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6322 EVT VT = Op.getValueType();
6323 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6324 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6325 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6326 DAG.getConstant(NewIntNo, MVT::i32),
6327 Op.getOperand(1), ShAmt);
6332 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6333 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6334 DebugLoc dl = Op.getDebugLoc();
6337 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6339 DAG.getConstant(TD->getPointerSize(),
6340 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6341 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6342 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6347 // Just load the return address.
6348 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6349 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6350 RetAddrFI, NULL, 0);
6353 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6354 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6355 MFI->setFrameAddressIsTaken(true);
6356 EVT VT = Op.getValueType();
6357 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6358 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6359 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6360 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6362 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6366 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6367 SelectionDAG &DAG) {
6368 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6371 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6373 MachineFunction &MF = DAG.getMachineFunction();
6374 SDValue Chain = Op.getOperand(0);
6375 SDValue Offset = Op.getOperand(1);
6376 SDValue Handler = Op.getOperand(2);
6377 DebugLoc dl = Op.getDebugLoc();
6379 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6381 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6383 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6384 DAG.getIntPtrConstant(-TD->getPointerSize()));
6385 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6386 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6387 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6388 MF.getRegInfo().addLiveOut(StoreAddrReg);
6390 return DAG.getNode(X86ISD::EH_RETURN, dl,
6392 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6395 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6396 SelectionDAG &DAG) {
6397 SDValue Root = Op.getOperand(0);
6398 SDValue Trmp = Op.getOperand(1); // trampoline
6399 SDValue FPtr = Op.getOperand(2); // nested function
6400 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6401 DebugLoc dl = Op.getDebugLoc();
6403 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6405 const X86InstrInfo *TII =
6406 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6408 if (Subtarget->is64Bit()) {
6409 SDValue OutChains[6];
6411 // Large code-model.
6413 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6414 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6416 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6417 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6419 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6421 // Load the pointer to the nested function into R11.
6422 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6423 SDValue Addr = Trmp;
6424 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6427 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6428 DAG.getConstant(2, MVT::i64));
6429 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6431 // Load the 'nest' parameter value into R10.
6432 // R10 is specified in X86CallingConv.td
6433 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6434 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6435 DAG.getConstant(10, MVT::i64));
6436 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6437 Addr, TrmpAddr, 10);
6439 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6440 DAG.getConstant(12, MVT::i64));
6441 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6443 // Jump to the nested function.
6444 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6445 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6446 DAG.getConstant(20, MVT::i64));
6447 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6448 Addr, TrmpAddr, 20);
6450 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6451 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6452 DAG.getConstant(22, MVT::i64));
6453 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6457 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6458 return DAG.getMergeValues(Ops, 2, dl);
6460 const Function *Func =
6461 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6462 unsigned CC = Func->getCallingConv();
6467 llvm_unreachable("Unsupported calling convention");
6468 case CallingConv::C:
6469 case CallingConv::X86_StdCall: {
6470 // Pass 'nest' parameter in ECX.
6471 // Must be kept in sync with X86CallingConv.td
6474 // Check that ECX wasn't needed by an 'inreg' parameter.
6475 const FunctionType *FTy = Func->getFunctionType();
6476 const AttrListPtr &Attrs = Func->getAttributes();
6478 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6479 unsigned InRegCount = 0;
6482 for (FunctionType::param_iterator I = FTy->param_begin(),
6483 E = FTy->param_end(); I != E; ++I, ++Idx)
6484 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6485 // FIXME: should only count parameters that are lowered to integers.
6486 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6488 if (InRegCount > 2) {
6489 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6494 case CallingConv::X86_FastCall:
6495 case CallingConv::Fast:
6496 // Pass 'nest' parameter in EAX.
6497 // Must be kept in sync with X86CallingConv.td
6502 SDValue OutChains[4];
6505 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6506 DAG.getConstant(10, MVT::i32));
6507 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6509 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6510 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6511 OutChains[0] = DAG.getStore(Root, dl,
6512 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6515 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6516 DAG.getConstant(1, MVT::i32));
6517 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6519 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6520 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6521 DAG.getConstant(5, MVT::i32));
6522 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6523 TrmpAddr, 5, false, 1);
6525 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6526 DAG.getConstant(6, MVT::i32));
6527 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6530 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6531 return DAG.getMergeValues(Ops, 2, dl);
6535 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6537 The rounding mode is in bits 11:10 of FPSR, and has the following
6544 FLT_ROUNDS, on the other hand, expects the following:
6551 To perform the conversion, we do:
6552 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6555 MachineFunction &MF = DAG.getMachineFunction();
6556 const TargetMachine &TM = MF.getTarget();
6557 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6558 unsigned StackAlignment = TFI.getStackAlignment();
6559 EVT VT = Op.getValueType();
6560 DebugLoc dl = Op.getDebugLoc();
6562 // Save FP Control Word to stack slot
6563 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6564 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6566 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6567 DAG.getEntryNode(), StackSlot);
6569 // Load FP Control Word from stack slot
6570 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6572 // Transform as necessary
6574 DAG.getNode(ISD::SRL, dl, MVT::i16,
6575 DAG.getNode(ISD::AND, dl, MVT::i16,
6576 CWD, DAG.getConstant(0x800, MVT::i16)),
6577 DAG.getConstant(11, MVT::i8));
6579 DAG.getNode(ISD::SRL, dl, MVT::i16,
6580 DAG.getNode(ISD::AND, dl, MVT::i16,
6581 CWD, DAG.getConstant(0x400, MVT::i16)),
6582 DAG.getConstant(9, MVT::i8));
6585 DAG.getNode(ISD::AND, dl, MVT::i16,
6586 DAG.getNode(ISD::ADD, dl, MVT::i16,
6587 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6588 DAG.getConstant(1, MVT::i16)),
6589 DAG.getConstant(3, MVT::i16));
6592 return DAG.getNode((VT.getSizeInBits() < 16 ?
6593 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6596 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6597 EVT VT = Op.getValueType();
6599 unsigned NumBits = VT.getSizeInBits();
6600 DebugLoc dl = Op.getDebugLoc();
6602 Op = Op.getOperand(0);
6603 if (VT == MVT::i8) {
6604 // Zero extend to i32 since there is not an i8 bsr.
6606 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6609 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6610 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6611 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6613 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6614 SmallVector<SDValue, 4> Ops;
6616 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6617 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6618 Ops.push_back(Op.getValue(1));
6619 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6621 // Finally xor with NumBits-1.
6622 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6625 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6629 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6630 EVT VT = Op.getValueType();
6632 unsigned NumBits = VT.getSizeInBits();
6633 DebugLoc dl = Op.getDebugLoc();
6635 Op = Op.getOperand(0);
6636 if (VT == MVT::i8) {
6638 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6641 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6642 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6643 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6645 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6646 SmallVector<SDValue, 4> Ops;
6648 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6649 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6650 Ops.push_back(Op.getValue(1));
6651 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6654 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6658 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6659 EVT VT = Op.getValueType();
6660 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6661 DebugLoc dl = Op.getDebugLoc();
6663 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6664 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6665 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6666 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6667 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6669 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6670 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6671 // return AloBlo + AloBhi + AhiBlo;
6673 SDValue A = Op.getOperand(0);
6674 SDValue B = Op.getOperand(1);
6676 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6677 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6678 A, DAG.getConstant(32, MVT::i32));
6679 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6680 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6681 B, DAG.getConstant(32, MVT::i32));
6682 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6683 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6685 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6686 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6688 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6689 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6691 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6692 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6693 AloBhi, DAG.getConstant(32, MVT::i32));
6694 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6695 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6696 AhiBlo, DAG.getConstant(32, MVT::i32));
6697 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6698 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6703 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6704 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6705 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6706 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6707 // has only one use.
6708 SDNode *N = Op.getNode();
6709 SDValue LHS = N->getOperand(0);
6710 SDValue RHS = N->getOperand(1);
6711 unsigned BaseOp = 0;
6713 DebugLoc dl = Op.getDebugLoc();
6715 switch (Op.getOpcode()) {
6716 default: llvm_unreachable("Unknown ovf instruction!");
6718 // A subtract of one will be selected as a INC. Note that INC doesn't
6719 // set CF, so we can't do this for UADDO.
6720 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6721 if (C->getAPIntValue() == 1) {
6722 BaseOp = X86ISD::INC;
6726 BaseOp = X86ISD::ADD;
6730 BaseOp = X86ISD::ADD;
6734 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6735 // set CF, so we can't do this for USUBO.
6736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6737 if (C->getAPIntValue() == 1) {
6738 BaseOp = X86ISD::DEC;
6742 BaseOp = X86ISD::SUB;
6746 BaseOp = X86ISD::SUB;
6750 BaseOp = X86ISD::SMUL;
6754 BaseOp = X86ISD::UMUL;
6759 // Also sets EFLAGS.
6760 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6761 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6764 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6765 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6767 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6771 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6772 EVT T = Op.getValueType();
6773 DebugLoc dl = Op.getDebugLoc();
6776 switch(T.getSimpleVT().SimpleTy) {
6778 assert(false && "Invalid value type!");
6779 case MVT::i8: Reg = X86::AL; size = 1; break;
6780 case MVT::i16: Reg = X86::AX; size = 2; break;
6781 case MVT::i32: Reg = X86::EAX; size = 4; break;
6783 assert(Subtarget->is64Bit() && "Node not type legal!");
6784 Reg = X86::RAX; size = 8;
6787 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6788 Op.getOperand(2), SDValue());
6789 SDValue Ops[] = { cpIn.getValue(0),
6792 DAG.getTargetConstant(size, MVT::i8),
6794 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6795 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6797 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6801 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6802 SelectionDAG &DAG) {
6803 assert(Subtarget->is64Bit() && "Result not type legalized?");
6804 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6805 SDValue TheChain = Op.getOperand(0);
6806 DebugLoc dl = Op.getDebugLoc();
6807 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6808 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6809 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6811 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6812 DAG.getConstant(32, MVT::i8));
6814 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6817 return DAG.getMergeValues(Ops, 2, dl);
6820 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6821 SDNode *Node = Op.getNode();
6822 DebugLoc dl = Node->getDebugLoc();
6823 EVT T = Node->getValueType(0);
6824 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6825 DAG.getConstant(0, T), Node->getOperand(2));
6826 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6827 cast<AtomicSDNode>(Node)->getMemoryVT(),
6828 Node->getOperand(0),
6829 Node->getOperand(1), negOp,
6830 cast<AtomicSDNode>(Node)->getSrcValue(),
6831 cast<AtomicSDNode>(Node)->getAlignment());
6834 /// LowerOperation - Provide custom lowering hooks for some operations.
6836 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6837 switch (Op.getOpcode()) {
6838 default: llvm_unreachable("Should not custom lower this!");
6839 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6840 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6841 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6842 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6843 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6844 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6845 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6846 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6847 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6848 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6849 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6850 case ISD::SHL_PARTS:
6851 case ISD::SRA_PARTS:
6852 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6853 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6854 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6855 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6856 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
6857 case ISD::FABS: return LowerFABS(Op, DAG);
6858 case ISD::FNEG: return LowerFNEG(Op, DAG);
6859 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6860 case ISD::SETCC: return LowerSETCC(Op, DAG);
6861 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6862 case ISD::SELECT: return LowerSELECT(Op, DAG);
6863 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6864 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6865 case ISD::VASTART: return LowerVASTART(Op, DAG);
6866 case ISD::VAARG: return LowerVAARG(Op, DAG);
6867 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6868 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6869 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6870 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6871 case ISD::FRAME_TO_ARGS_OFFSET:
6872 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6873 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6874 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6875 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6876 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6877 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6878 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6879 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6885 case ISD::UMULO: return LowerXALUO(Op, DAG);
6886 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6890 void X86TargetLowering::
6891 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6892 SelectionDAG &DAG, unsigned NewOp) {
6893 EVT T = Node->getValueType(0);
6894 DebugLoc dl = Node->getDebugLoc();
6895 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6897 SDValue Chain = Node->getOperand(0);
6898 SDValue In1 = Node->getOperand(1);
6899 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6900 Node->getOperand(2), DAG.getIntPtrConstant(0));
6901 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6902 Node->getOperand(2), DAG.getIntPtrConstant(1));
6903 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6904 // have a MemOperand. Pass the info through as a normal operand.
6905 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6906 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6907 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6908 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6909 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6910 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6911 Results.push_back(Result.getValue(2));
6914 /// ReplaceNodeResults - Replace a node with an illegal result type
6915 /// with a new node built out of custom code.
6916 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6917 SmallVectorImpl<SDValue>&Results,
6918 SelectionDAG &DAG) {
6919 DebugLoc dl = N->getDebugLoc();
6920 switch (N->getOpcode()) {
6922 assert(false && "Do not know how to custom type legalize this operation!");
6924 case ISD::FP_TO_SINT: {
6925 std::pair<SDValue,SDValue> Vals =
6926 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
6927 SDValue FIST = Vals.first, StackSlot = Vals.second;
6928 if (FIST.getNode() != 0) {
6929 EVT VT = N->getValueType(0);
6930 // Return a load from the stack slot.
6931 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
6935 case ISD::READCYCLECOUNTER: {
6936 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6937 SDValue TheChain = N->getOperand(0);
6938 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6939 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
6941 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
6943 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6944 SDValue Ops[] = { eax, edx };
6945 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
6946 Results.push_back(edx.getValue(1));
6949 case ISD::ATOMIC_CMP_SWAP: {
6950 EVT T = N->getValueType(0);
6951 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6952 SDValue cpInL, cpInH;
6953 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6954 DAG.getConstant(0, MVT::i32));
6955 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6956 DAG.getConstant(1, MVT::i32));
6957 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
6958 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
6960 SDValue swapInL, swapInH;
6961 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6962 DAG.getConstant(0, MVT::i32));
6963 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6964 DAG.getConstant(1, MVT::i32));
6965 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
6967 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
6968 swapInL.getValue(1));
6969 SDValue Ops[] = { swapInH.getValue(0),
6971 swapInH.getValue(1) };
6972 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6973 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
6974 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
6975 MVT::i32, Result.getValue(1));
6976 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
6977 MVT::i32, cpOutL.getValue(2));
6978 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6979 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6980 Results.push_back(cpOutH.getValue(1));
6983 case ISD::ATOMIC_LOAD_ADD:
6984 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6986 case ISD::ATOMIC_LOAD_AND:
6987 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6989 case ISD::ATOMIC_LOAD_NAND:
6990 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6992 case ISD::ATOMIC_LOAD_OR:
6993 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6995 case ISD::ATOMIC_LOAD_SUB:
6996 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6998 case ISD::ATOMIC_LOAD_XOR:
6999 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7001 case ISD::ATOMIC_SWAP:
7002 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7007 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7009 default: return NULL;
7010 case X86ISD::BSF: return "X86ISD::BSF";
7011 case X86ISD::BSR: return "X86ISD::BSR";
7012 case X86ISD::SHLD: return "X86ISD::SHLD";
7013 case X86ISD::SHRD: return "X86ISD::SHRD";
7014 case X86ISD::FAND: return "X86ISD::FAND";
7015 case X86ISD::FOR: return "X86ISD::FOR";
7016 case X86ISD::FXOR: return "X86ISD::FXOR";
7017 case X86ISD::FSRL: return "X86ISD::FSRL";
7018 case X86ISD::FILD: return "X86ISD::FILD";
7019 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7020 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7021 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7022 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7023 case X86ISD::FLD: return "X86ISD::FLD";
7024 case X86ISD::FST: return "X86ISD::FST";
7025 case X86ISD::CALL: return "X86ISD::CALL";
7026 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7027 case X86ISD::BT: return "X86ISD::BT";
7028 case X86ISD::CMP: return "X86ISD::CMP";
7029 case X86ISD::COMI: return "X86ISD::COMI";
7030 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7031 case X86ISD::SETCC: return "X86ISD::SETCC";
7032 case X86ISD::CMOV: return "X86ISD::CMOV";
7033 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7034 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7035 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7036 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7037 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7038 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7039 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7040 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7041 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7042 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7043 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7044 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7045 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7046 case X86ISD::FMAX: return "X86ISD::FMAX";
7047 case X86ISD::FMIN: return "X86ISD::FMIN";
7048 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7049 case X86ISD::FRCP: return "X86ISD::FRCP";
7050 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7051 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7052 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7053 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7054 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7055 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7056 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7057 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7058 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7059 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7060 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7061 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7062 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7063 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7064 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7065 case X86ISD::VSHL: return "X86ISD::VSHL";
7066 case X86ISD::VSRL: return "X86ISD::VSRL";
7067 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7068 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7069 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7070 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7071 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7072 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7073 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7074 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7075 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7076 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7077 case X86ISD::ADD: return "X86ISD::ADD";
7078 case X86ISD::SUB: return "X86ISD::SUB";
7079 case X86ISD::SMUL: return "X86ISD::SMUL";
7080 case X86ISD::UMUL: return "X86ISD::UMUL";
7081 case X86ISD::INC: return "X86ISD::INC";
7082 case X86ISD::DEC: return "X86ISD::DEC";
7083 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7084 case X86ISD::PTEST: return "X86ISD::PTEST";
7088 // isLegalAddressingMode - Return true if the addressing mode represented
7089 // by AM is legal for this target, for a load/store of the specified type.
7090 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7091 const Type *Ty) const {
7092 // X86 supports extremely general addressing modes.
7093 CodeModel::Model M = getTargetMachine().getCodeModel();
7095 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7096 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7101 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7103 // If a reference to this global requires an extra load, we can't fold it.
7104 if (isGlobalStubReference(GVFlags))
7107 // If BaseGV requires a register for the PIC base, we cannot also have a
7108 // BaseReg specified.
7109 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7112 // If lower 4G is not available, then we must use rip-relative addressing.
7113 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7123 // These scales always work.
7128 // These scales are formed with basereg+scalereg. Only accept if there is
7133 default: // Other stuff never works.
7141 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7142 if (!Ty1->isInteger() || !Ty2->isInteger())
7144 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7145 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7146 if (NumBits1 <= NumBits2)
7148 return Subtarget->is64Bit() || NumBits1 < 64;
7151 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7152 if (!VT1.isInteger() || !VT2.isInteger())
7154 unsigned NumBits1 = VT1.getSizeInBits();
7155 unsigned NumBits2 = VT2.getSizeInBits();
7156 if (NumBits1 <= NumBits2)
7158 return Subtarget->is64Bit() || NumBits1 < 64;
7161 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7162 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7163 return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
7164 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
7167 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7168 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7169 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7172 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7173 // i16 instructions are longer (0x66 prefix) and potentially slower.
7174 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7177 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7178 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7179 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7180 /// are assumed to be legal.
7182 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7184 // Only do shuffles on 128-bit vector types for now.
7185 if (VT.getSizeInBits() == 64)
7188 // FIXME: pshufb, blends, palignr, shifts.
7189 return (VT.getVectorNumElements() == 2 ||
7190 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7191 isMOVLMask(M, VT) ||
7192 isSHUFPMask(M, VT) ||
7193 isPSHUFDMask(M, VT) ||
7194 isPSHUFHWMask(M, VT) ||
7195 isPSHUFLWMask(M, VT) ||
7196 isUNPCKLMask(M, VT) ||
7197 isUNPCKHMask(M, VT) ||
7198 isUNPCKL_v_undef_Mask(M, VT) ||
7199 isUNPCKH_v_undef_Mask(M, VT));
7203 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7205 unsigned NumElts = VT.getVectorNumElements();
7206 // FIXME: This collection of masks seems suspect.
7209 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7210 return (isMOVLMask(Mask, VT) ||
7211 isCommutedMOVLMask(Mask, VT, true) ||
7212 isSHUFPMask(Mask, VT) ||
7213 isCommutedSHUFPMask(Mask, VT));
7218 //===----------------------------------------------------------------------===//
7219 // X86 Scheduler Hooks
7220 //===----------------------------------------------------------------------===//
7222 // private utility function
7224 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7225 MachineBasicBlock *MBB,
7233 TargetRegisterClass *RC,
7234 bool invSrc) const {
7235 // For the atomic bitwise operator, we generate
7238 // ld t1 = [bitinstr.addr]
7239 // op t2 = t1, [bitinstr.val]
7241 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7243 // fallthrough -->nextMBB
7244 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7245 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7246 MachineFunction::iterator MBBIter = MBB;
7249 /// First build the CFG
7250 MachineFunction *F = MBB->getParent();
7251 MachineBasicBlock *thisMBB = MBB;
7252 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7253 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7254 F->insert(MBBIter, newMBB);
7255 F->insert(MBBIter, nextMBB);
7257 // Move all successors to thisMBB to nextMBB
7258 nextMBB->transferSuccessors(thisMBB);
7260 // Update thisMBB to fall through to newMBB
7261 thisMBB->addSuccessor(newMBB);
7263 // newMBB jumps to itself and fall through to nextMBB
7264 newMBB->addSuccessor(nextMBB);
7265 newMBB->addSuccessor(newMBB);
7267 // Insert instructions into newMBB based on incoming instruction
7268 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7269 "unexpected number of operands");
7270 DebugLoc dl = bInstr->getDebugLoc();
7271 MachineOperand& destOper = bInstr->getOperand(0);
7272 MachineOperand* argOpers[2 + X86AddrNumOperands];
7273 int numArgs = bInstr->getNumOperands() - 1;
7274 for (int i=0; i < numArgs; ++i)
7275 argOpers[i] = &bInstr->getOperand(i+1);
7277 // x86 address has 4 operands: base, index, scale, and displacement
7278 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7279 int valArgIndx = lastAddrIndx + 1;
7281 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7282 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7283 for (int i=0; i <= lastAddrIndx; ++i)
7284 (*MIB).addOperand(*argOpers[i]);
7286 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7288 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7293 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7294 assert((argOpers[valArgIndx]->isReg() ||
7295 argOpers[valArgIndx]->isImm()) &&
7297 if (argOpers[valArgIndx]->isReg())
7298 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7300 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7302 (*MIB).addOperand(*argOpers[valArgIndx]);
7304 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7307 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7308 for (int i=0; i <= lastAddrIndx; ++i)
7309 (*MIB).addOperand(*argOpers[i]);
7311 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7312 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7314 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7318 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7320 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7324 // private utility function: 64 bit atomics on 32 bit host.
7326 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7327 MachineBasicBlock *MBB,
7332 bool invSrc) const {
7333 // For the atomic bitwise operator, we generate
7334 // thisMBB (instructions are in pairs, except cmpxchg8b)
7335 // ld t1,t2 = [bitinstr.addr]
7337 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7338 // op t5, t6 <- out1, out2, [bitinstr.val]
7339 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7340 // mov ECX, EBX <- t5, t6
7341 // mov EAX, EDX <- t1, t2
7342 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7343 // mov t3, t4 <- EAX, EDX
7345 // result in out1, out2
7346 // fallthrough -->nextMBB
7348 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7349 const unsigned LoadOpc = X86::MOV32rm;
7350 const unsigned copyOpc = X86::MOV32rr;
7351 const unsigned NotOpc = X86::NOT32r;
7352 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7353 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7354 MachineFunction::iterator MBBIter = MBB;
7357 /// First build the CFG
7358 MachineFunction *F = MBB->getParent();
7359 MachineBasicBlock *thisMBB = MBB;
7360 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7361 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7362 F->insert(MBBIter, newMBB);
7363 F->insert(MBBIter, nextMBB);
7365 // Move all successors to thisMBB to nextMBB
7366 nextMBB->transferSuccessors(thisMBB);
7368 // Update thisMBB to fall through to newMBB
7369 thisMBB->addSuccessor(newMBB);
7371 // newMBB jumps to itself and fall through to nextMBB
7372 newMBB->addSuccessor(nextMBB);
7373 newMBB->addSuccessor(newMBB);
7375 DebugLoc dl = bInstr->getDebugLoc();
7376 // Insert instructions into newMBB based on incoming instruction
7377 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7378 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7379 "unexpected number of operands");
7380 MachineOperand& dest1Oper = bInstr->getOperand(0);
7381 MachineOperand& dest2Oper = bInstr->getOperand(1);
7382 MachineOperand* argOpers[2 + X86AddrNumOperands];
7383 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7384 argOpers[i] = &bInstr->getOperand(i+2);
7386 // x86 address has 4 operands: base, index, scale, and displacement
7387 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7389 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7390 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7391 for (int i=0; i <= lastAddrIndx; ++i)
7392 (*MIB).addOperand(*argOpers[i]);
7393 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7394 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7395 // add 4 to displacement.
7396 for (int i=0; i <= lastAddrIndx-2; ++i)
7397 (*MIB).addOperand(*argOpers[i]);
7398 MachineOperand newOp3 = *(argOpers[3]);
7400 newOp3.setImm(newOp3.getImm()+4);
7402 newOp3.setOffset(newOp3.getOffset()+4);
7403 (*MIB).addOperand(newOp3);
7404 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7406 // t3/4 are defined later, at the bottom of the loop
7407 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7408 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7409 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7410 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7411 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7412 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7414 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7415 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7417 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7418 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7424 int valArgIndx = lastAddrIndx + 1;
7425 assert((argOpers[valArgIndx]->isReg() ||
7426 argOpers[valArgIndx]->isImm()) &&
7428 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7429 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7430 if (argOpers[valArgIndx]->isReg())
7431 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7433 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7434 if (regOpcL != X86::MOV32rr)
7436 (*MIB).addOperand(*argOpers[valArgIndx]);
7437 assert(argOpers[valArgIndx + 1]->isReg() ==
7438 argOpers[valArgIndx]->isReg());
7439 assert(argOpers[valArgIndx + 1]->isImm() ==
7440 argOpers[valArgIndx]->isImm());
7441 if (argOpers[valArgIndx + 1]->isReg())
7442 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7444 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7445 if (regOpcH != X86::MOV32rr)
7447 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7449 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7451 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7454 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7456 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7459 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7460 for (int i=0; i <= lastAddrIndx; ++i)
7461 (*MIB).addOperand(*argOpers[i]);
7463 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7464 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7466 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7467 MIB.addReg(X86::EAX);
7468 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7469 MIB.addReg(X86::EDX);
7472 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7474 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7478 // private utility function
7480 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7481 MachineBasicBlock *MBB,
7482 unsigned cmovOpc) const {
7483 // For the atomic min/max operator, we generate
7486 // ld t1 = [min/max.addr]
7487 // mov t2 = [min/max.val]
7489 // cmov[cond] t2 = t1
7491 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7493 // fallthrough -->nextMBB
7495 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7496 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7497 MachineFunction::iterator MBBIter = MBB;
7500 /// First build the CFG
7501 MachineFunction *F = MBB->getParent();
7502 MachineBasicBlock *thisMBB = MBB;
7503 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7504 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7505 F->insert(MBBIter, newMBB);
7506 F->insert(MBBIter, nextMBB);
7508 // Move all successors to thisMBB to nextMBB
7509 nextMBB->transferSuccessors(thisMBB);
7511 // Update thisMBB to fall through to newMBB
7512 thisMBB->addSuccessor(newMBB);
7514 // newMBB jumps to newMBB and fall through to nextMBB
7515 newMBB->addSuccessor(nextMBB);
7516 newMBB->addSuccessor(newMBB);
7518 DebugLoc dl = mInstr->getDebugLoc();
7519 // Insert instructions into newMBB based on incoming instruction
7520 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7521 "unexpected number of operands");
7522 MachineOperand& destOper = mInstr->getOperand(0);
7523 MachineOperand* argOpers[2 + X86AddrNumOperands];
7524 int numArgs = mInstr->getNumOperands() - 1;
7525 for (int i=0; i < numArgs; ++i)
7526 argOpers[i] = &mInstr->getOperand(i+1);
7528 // x86 address has 4 operands: base, index, scale, and displacement
7529 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7530 int valArgIndx = lastAddrIndx + 1;
7532 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7533 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7534 for (int i=0; i <= lastAddrIndx; ++i)
7535 (*MIB).addOperand(*argOpers[i]);
7537 // We only support register and immediate values
7538 assert((argOpers[valArgIndx]->isReg() ||
7539 argOpers[valArgIndx]->isImm()) &&
7542 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7543 if (argOpers[valArgIndx]->isReg())
7544 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7546 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7547 (*MIB).addOperand(*argOpers[valArgIndx]);
7549 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7552 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7557 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7558 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7562 // Cmp and exchange if none has modified the memory location
7563 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7564 for (int i=0; i <= lastAddrIndx; ++i)
7565 (*MIB).addOperand(*argOpers[i]);
7567 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7568 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7570 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7571 MIB.addReg(X86::EAX);
7574 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7576 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7582 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7583 MachineBasicBlock *BB) const {
7584 DebugLoc dl = MI->getDebugLoc();
7585 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7586 switch (MI->getOpcode()) {
7587 default: assert(false && "Unexpected instr type to insert");
7588 case X86::CMOV_V1I64:
7589 case X86::CMOV_FR32:
7590 case X86::CMOV_FR64:
7591 case X86::CMOV_V4F32:
7592 case X86::CMOV_V2F64:
7593 case X86::CMOV_V2I64: {
7594 // To "insert" a SELECT_CC instruction, we actually have to insert the
7595 // diamond control-flow pattern. The incoming instruction knows the
7596 // destination vreg to set, the condition code register to branch on, the
7597 // true/false values to select between, and a branch opcode to use.
7598 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7599 MachineFunction::iterator It = BB;
7605 // cmpTY ccX, r1, r2
7607 // fallthrough --> copy0MBB
7608 MachineBasicBlock *thisMBB = BB;
7609 MachineFunction *F = BB->getParent();
7610 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7611 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7613 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7614 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
7615 F->insert(It, copy0MBB);
7616 F->insert(It, sinkMBB);
7617 // Update machine-CFG edges by transferring all successors of the current
7618 // block to the new block which will contain the Phi node for the select.
7619 sinkMBB->transferSuccessors(BB);
7621 // Add the true and fallthrough blocks as its successors.
7622 BB->addSuccessor(copy0MBB);
7623 BB->addSuccessor(sinkMBB);
7626 // %FalseValue = ...
7627 // # fallthrough to sinkMBB
7630 // Update machine-CFG edges
7631 BB->addSuccessor(sinkMBB);
7634 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7637 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
7638 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7639 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7641 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7645 case X86::FP32_TO_INT16_IN_MEM:
7646 case X86::FP32_TO_INT32_IN_MEM:
7647 case X86::FP32_TO_INT64_IN_MEM:
7648 case X86::FP64_TO_INT16_IN_MEM:
7649 case X86::FP64_TO_INT32_IN_MEM:
7650 case X86::FP64_TO_INT64_IN_MEM:
7651 case X86::FP80_TO_INT16_IN_MEM:
7652 case X86::FP80_TO_INT32_IN_MEM:
7653 case X86::FP80_TO_INT64_IN_MEM: {
7654 // Change the floating point control register to use "round towards zero"
7655 // mode when truncating to an integer value.
7656 MachineFunction *F = BB->getParent();
7657 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7658 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7660 // Load the old value of the high byte of the control word...
7662 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7663 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
7666 // Set the high part to be round to zero...
7667 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
7670 // Reload the modified control word now...
7671 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7673 // Restore the memory image of control word to original value
7674 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
7677 // Get the X86 opcode to use.
7679 switch (MI->getOpcode()) {
7680 default: llvm_unreachable("illegal opcode!");
7681 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7682 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7683 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7684 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7685 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7686 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7687 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7688 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7689 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7693 MachineOperand &Op = MI->getOperand(0);
7695 AM.BaseType = X86AddressMode::RegBase;
7696 AM.Base.Reg = Op.getReg();
7698 AM.BaseType = X86AddressMode::FrameIndexBase;
7699 AM.Base.FrameIndex = Op.getIndex();
7701 Op = MI->getOperand(1);
7703 AM.Scale = Op.getImm();
7704 Op = MI->getOperand(2);
7706 AM.IndexReg = Op.getImm();
7707 Op = MI->getOperand(3);
7708 if (Op.isGlobal()) {
7709 AM.GV = Op.getGlobal();
7711 AM.Disp = Op.getImm();
7713 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
7714 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
7716 // Reload the original control word now.
7717 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7719 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7722 case X86::ATOMAND32:
7723 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7724 X86::AND32ri, X86::MOV32rm,
7725 X86::LCMPXCHG32, X86::MOV32rr,
7726 X86::NOT32r, X86::EAX,
7727 X86::GR32RegisterClass);
7729 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7730 X86::OR32ri, X86::MOV32rm,
7731 X86::LCMPXCHG32, X86::MOV32rr,
7732 X86::NOT32r, X86::EAX,
7733 X86::GR32RegisterClass);
7734 case X86::ATOMXOR32:
7735 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7736 X86::XOR32ri, X86::MOV32rm,
7737 X86::LCMPXCHG32, X86::MOV32rr,
7738 X86::NOT32r, X86::EAX,
7739 X86::GR32RegisterClass);
7740 case X86::ATOMNAND32:
7741 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7742 X86::AND32ri, X86::MOV32rm,
7743 X86::LCMPXCHG32, X86::MOV32rr,
7744 X86::NOT32r, X86::EAX,
7745 X86::GR32RegisterClass, true);
7746 case X86::ATOMMIN32:
7747 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7748 case X86::ATOMMAX32:
7749 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7750 case X86::ATOMUMIN32:
7751 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7752 case X86::ATOMUMAX32:
7753 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7755 case X86::ATOMAND16:
7756 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7757 X86::AND16ri, X86::MOV16rm,
7758 X86::LCMPXCHG16, X86::MOV16rr,
7759 X86::NOT16r, X86::AX,
7760 X86::GR16RegisterClass);
7762 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7763 X86::OR16ri, X86::MOV16rm,
7764 X86::LCMPXCHG16, X86::MOV16rr,
7765 X86::NOT16r, X86::AX,
7766 X86::GR16RegisterClass);
7767 case X86::ATOMXOR16:
7768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7769 X86::XOR16ri, X86::MOV16rm,
7770 X86::LCMPXCHG16, X86::MOV16rr,
7771 X86::NOT16r, X86::AX,
7772 X86::GR16RegisterClass);
7773 case X86::ATOMNAND16:
7774 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7775 X86::AND16ri, X86::MOV16rm,
7776 X86::LCMPXCHG16, X86::MOV16rr,
7777 X86::NOT16r, X86::AX,
7778 X86::GR16RegisterClass, true);
7779 case X86::ATOMMIN16:
7780 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7781 case X86::ATOMMAX16:
7782 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7783 case X86::ATOMUMIN16:
7784 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7785 case X86::ATOMUMAX16:
7786 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7789 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7790 X86::AND8ri, X86::MOV8rm,
7791 X86::LCMPXCHG8, X86::MOV8rr,
7792 X86::NOT8r, X86::AL,
7793 X86::GR8RegisterClass);
7795 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7796 X86::OR8ri, X86::MOV8rm,
7797 X86::LCMPXCHG8, X86::MOV8rr,
7798 X86::NOT8r, X86::AL,
7799 X86::GR8RegisterClass);
7801 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7802 X86::XOR8ri, X86::MOV8rm,
7803 X86::LCMPXCHG8, X86::MOV8rr,
7804 X86::NOT8r, X86::AL,
7805 X86::GR8RegisterClass);
7806 case X86::ATOMNAND8:
7807 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7808 X86::AND8ri, X86::MOV8rm,
7809 X86::LCMPXCHG8, X86::MOV8rr,
7810 X86::NOT8r, X86::AL,
7811 X86::GR8RegisterClass, true);
7812 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7813 // This group is for 64-bit host.
7814 case X86::ATOMAND64:
7815 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7816 X86::AND64ri32, X86::MOV64rm,
7817 X86::LCMPXCHG64, X86::MOV64rr,
7818 X86::NOT64r, X86::RAX,
7819 X86::GR64RegisterClass);
7821 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7822 X86::OR64ri32, X86::MOV64rm,
7823 X86::LCMPXCHG64, X86::MOV64rr,
7824 X86::NOT64r, X86::RAX,
7825 X86::GR64RegisterClass);
7826 case X86::ATOMXOR64:
7827 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7828 X86::XOR64ri32, X86::MOV64rm,
7829 X86::LCMPXCHG64, X86::MOV64rr,
7830 X86::NOT64r, X86::RAX,
7831 X86::GR64RegisterClass);
7832 case X86::ATOMNAND64:
7833 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7834 X86::AND64ri32, X86::MOV64rm,
7835 X86::LCMPXCHG64, X86::MOV64rr,
7836 X86::NOT64r, X86::RAX,
7837 X86::GR64RegisterClass, true);
7838 case X86::ATOMMIN64:
7839 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7840 case X86::ATOMMAX64:
7841 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7842 case X86::ATOMUMIN64:
7843 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7844 case X86::ATOMUMAX64:
7845 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7847 // This group does 64-bit operations on a 32-bit host.
7848 case X86::ATOMAND6432:
7849 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7850 X86::AND32rr, X86::AND32rr,
7851 X86::AND32ri, X86::AND32ri,
7853 case X86::ATOMOR6432:
7854 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7855 X86::OR32rr, X86::OR32rr,
7856 X86::OR32ri, X86::OR32ri,
7858 case X86::ATOMXOR6432:
7859 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7860 X86::XOR32rr, X86::XOR32rr,
7861 X86::XOR32ri, X86::XOR32ri,
7863 case X86::ATOMNAND6432:
7864 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7865 X86::AND32rr, X86::AND32rr,
7866 X86::AND32ri, X86::AND32ri,
7868 case X86::ATOMADD6432:
7869 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7870 X86::ADD32rr, X86::ADC32rr,
7871 X86::ADD32ri, X86::ADC32ri,
7873 case X86::ATOMSUB6432:
7874 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7875 X86::SUB32rr, X86::SBB32rr,
7876 X86::SUB32ri, X86::SBB32ri,
7878 case X86::ATOMSWAP6432:
7879 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7880 X86::MOV32rr, X86::MOV32rr,
7881 X86::MOV32ri, X86::MOV32ri,
7886 //===----------------------------------------------------------------------===//
7887 // X86 Optimization Hooks
7888 //===----------------------------------------------------------------------===//
7890 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7894 const SelectionDAG &DAG,
7895 unsigned Depth) const {
7896 unsigned Opc = Op.getOpcode();
7897 assert((Opc >= ISD::BUILTIN_OP_END ||
7898 Opc == ISD::INTRINSIC_WO_CHAIN ||
7899 Opc == ISD::INTRINSIC_W_CHAIN ||
7900 Opc == ISD::INTRINSIC_VOID) &&
7901 "Should use MaskedValueIsZero if you don't know whether Op"
7902 " is a target node!");
7904 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7913 // These nodes' second result is a boolean.
7914 if (Op.getResNo() == 0)
7918 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7919 Mask.getBitWidth() - 1);
7924 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7925 /// node is a GlobalAddress + offset.
7926 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7927 GlobalValue* &GA, int64_t &Offset) const{
7928 if (N->getOpcode() == X86ISD::Wrapper) {
7929 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7930 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7931 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7935 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7938 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7939 const TargetLowering &TLI) {
7942 if (TLI.isGAPlusOffset(Base, GV, Offset))
7943 return (GV->getAlignment() >= N && (Offset % N) == 0);
7944 // DAG combine handles the stack object case.
7948 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
7949 EVT EVT, LoadSDNode *&LDBase,
7950 unsigned &LastLoadedElt,
7951 SelectionDAG &DAG, MachineFrameInfo *MFI,
7952 const TargetLowering &TLI) {
7954 LastLoadedElt = -1U;
7955 for (unsigned i = 0; i < NumElems; ++i) {
7956 if (N->getMaskElt(i) < 0) {
7962 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7963 if (!Elt.getNode() ||
7964 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7967 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
7969 LDBase = cast<LoadSDNode>(Elt.getNode());
7973 if (Elt.getOpcode() == ISD::UNDEF)
7976 LoadSDNode *LD = cast<LoadSDNode>(Elt);
7977 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
7984 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7985 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7986 /// if the load addresses are consecutive, non-overlapping, and in the right
7987 /// order. In the case of v2i64, it will see if it can rewrite the
7988 /// shuffle to be an appropriate build vector so it can take advantage of
7989 // performBuildVectorCombine.
7990 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7991 const TargetLowering &TLI) {
7992 DebugLoc dl = N->getDebugLoc();
7993 EVT VT = N->getValueType(0);
7994 EVT EVT = VT.getVectorElementType();
7995 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7996 unsigned NumElems = VT.getVectorNumElements();
7998 if (VT.getSizeInBits() != 128)
8001 // Try to combine a vector_shuffle into a 128-bit load.
8002 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8003 LoadSDNode *LD = NULL;
8004 unsigned LastLoadedElt;
8005 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
8009 if (LastLoadedElt == NumElems - 1) {
8010 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
8011 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8012 LD->getSrcValue(), LD->getSrcValueOffset(),
8014 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8015 LD->getSrcValue(), LD->getSrcValueOffset(),
8016 LD->isVolatile(), LD->getAlignment());
8017 } else if (NumElems == 4 && LastLoadedElt == 1) {
8018 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8019 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8020 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8021 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8026 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8027 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8028 const X86Subtarget *Subtarget) {
8029 DebugLoc DL = N->getDebugLoc();
8030 SDValue Cond = N->getOperand(0);
8031 // Get the LHS/RHS of the select.
8032 SDValue LHS = N->getOperand(1);
8033 SDValue RHS = N->getOperand(2);
8035 // If we have SSE[12] support, try to form min/max nodes.
8036 if (Subtarget->hasSSE2() &&
8037 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8038 Cond.getOpcode() == ISD::SETCC) {
8039 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8041 unsigned Opcode = 0;
8042 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8045 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
8048 if (!UnsafeFPMath) break;
8050 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
8052 Opcode = X86ISD::FMIN;
8055 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8058 if (!UnsafeFPMath) break;
8060 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8062 Opcode = X86ISD::FMAX;
8065 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8068 case ISD::SETOGT: // (X > Y) ? Y : X -> min
8071 if (!UnsafeFPMath) break;
8073 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8075 Opcode = X86ISD::FMIN;
8078 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8081 if (!UnsafeFPMath) break;
8083 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8085 Opcode = X86ISD::FMAX;
8091 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8094 // If this is a select between two integer constants, try to do some
8096 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8097 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8098 // Don't do this for crazy integer types.
8099 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8100 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8101 // so that TrueC (the true value) is larger than FalseC.
8102 bool NeedsCondInvert = false;
8104 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8105 // Efficiently invertible.
8106 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8107 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8108 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8109 NeedsCondInvert = true;
8110 std::swap(TrueC, FalseC);
8113 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8114 if (FalseC->getAPIntValue() == 0 &&
8115 TrueC->getAPIntValue().isPowerOf2()) {
8116 if (NeedsCondInvert) // Invert the condition if needed.
8117 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8118 DAG.getConstant(1, Cond.getValueType()));
8120 // Zero extend the condition if needed.
8121 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8123 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8124 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8125 DAG.getConstant(ShAmt, MVT::i8));
8128 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8129 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8130 if (NeedsCondInvert) // Invert the condition if needed.
8131 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8132 DAG.getConstant(1, Cond.getValueType()));
8134 // Zero extend the condition if needed.
8135 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8136 FalseC->getValueType(0), Cond);
8137 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8138 SDValue(FalseC, 0));
8141 // Optimize cases that will turn into an LEA instruction. This requires
8142 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8143 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8144 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8145 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8147 bool isFastMultiplier = false;
8149 switch ((unsigned char)Diff) {
8151 case 1: // result = add base, cond
8152 case 2: // result = lea base( , cond*2)
8153 case 3: // result = lea base(cond, cond*2)
8154 case 4: // result = lea base( , cond*4)
8155 case 5: // result = lea base(cond, cond*4)
8156 case 8: // result = lea base( , cond*8)
8157 case 9: // result = lea base(cond, cond*8)
8158 isFastMultiplier = true;
8163 if (isFastMultiplier) {
8164 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8165 if (NeedsCondInvert) // Invert the condition if needed.
8166 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8167 DAG.getConstant(1, Cond.getValueType()));
8169 // Zero extend the condition if needed.
8170 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8172 // Scale the condition by the difference.
8174 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8175 DAG.getConstant(Diff, Cond.getValueType()));
8177 // Add the base if non-zero.
8178 if (FalseC->getAPIntValue() != 0)
8179 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8180 SDValue(FalseC, 0));
8190 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8191 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8192 TargetLowering::DAGCombinerInfo &DCI) {
8193 DebugLoc DL = N->getDebugLoc();
8195 // If the flag operand isn't dead, don't touch this CMOV.
8196 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8199 // If this is a select between two integer constants, try to do some
8200 // optimizations. Note that the operands are ordered the opposite of SELECT
8202 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8203 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8204 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8205 // larger than FalseC (the false value).
8206 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8208 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8209 CC = X86::GetOppositeBranchCondition(CC);
8210 std::swap(TrueC, FalseC);
8213 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8214 // This is efficient for any integer data type (including i8/i16) and
8216 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8217 SDValue Cond = N->getOperand(3);
8218 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8219 DAG.getConstant(CC, MVT::i8), Cond);
8221 // Zero extend the condition if needed.
8222 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8224 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8225 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8226 DAG.getConstant(ShAmt, MVT::i8));
8227 if (N->getNumValues() == 2) // Dead flag value?
8228 return DCI.CombineTo(N, Cond, SDValue());
8232 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8233 // for any integer data type, including i8/i16.
8234 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8235 SDValue Cond = N->getOperand(3);
8236 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8237 DAG.getConstant(CC, MVT::i8), Cond);
8239 // Zero extend the condition if needed.
8240 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8241 FalseC->getValueType(0), Cond);
8242 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8243 SDValue(FalseC, 0));
8245 if (N->getNumValues() == 2) // Dead flag value?
8246 return DCI.CombineTo(N, Cond, SDValue());
8250 // Optimize cases that will turn into an LEA instruction. This requires
8251 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8252 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8253 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8254 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8256 bool isFastMultiplier = false;
8258 switch ((unsigned char)Diff) {
8260 case 1: // result = add base, cond
8261 case 2: // result = lea base( , cond*2)
8262 case 3: // result = lea base(cond, cond*2)
8263 case 4: // result = lea base( , cond*4)
8264 case 5: // result = lea base(cond, cond*4)
8265 case 8: // result = lea base( , cond*8)
8266 case 9: // result = lea base(cond, cond*8)
8267 isFastMultiplier = true;
8272 if (isFastMultiplier) {
8273 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8274 SDValue Cond = N->getOperand(3);
8275 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8276 DAG.getConstant(CC, MVT::i8), Cond);
8277 // Zero extend the condition if needed.
8278 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8280 // Scale the condition by the difference.
8282 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8283 DAG.getConstant(Diff, Cond.getValueType()));
8285 // Add the base if non-zero.
8286 if (FalseC->getAPIntValue() != 0)
8287 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8288 SDValue(FalseC, 0));
8289 if (N->getNumValues() == 2) // Dead flag value?
8290 return DCI.CombineTo(N, Cond, SDValue());
8300 /// PerformMulCombine - Optimize a single multiply with constant into two
8301 /// in order to implement it with two cheaper instructions, e.g.
8302 /// LEA + SHL, LEA + LEA.
8303 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8304 TargetLowering::DAGCombinerInfo &DCI) {
8305 if (DAG.getMachineFunction().
8306 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8309 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8312 EVT VT = N->getValueType(0);
8316 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8319 uint64_t MulAmt = C->getZExtValue();
8320 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8323 uint64_t MulAmt1 = 0;
8324 uint64_t MulAmt2 = 0;
8325 if ((MulAmt % 9) == 0) {
8327 MulAmt2 = MulAmt / 9;
8328 } else if ((MulAmt % 5) == 0) {
8330 MulAmt2 = MulAmt / 5;
8331 } else if ((MulAmt % 3) == 0) {
8333 MulAmt2 = MulAmt / 3;
8336 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8337 DebugLoc DL = N->getDebugLoc();
8339 if (isPowerOf2_64(MulAmt2) &&
8340 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8341 // If second multiplifer is pow2, issue it first. We want the multiply by
8342 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8344 std::swap(MulAmt1, MulAmt2);
8347 if (isPowerOf2_64(MulAmt1))
8348 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8349 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8351 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8352 DAG.getConstant(MulAmt1, VT));
8354 if (isPowerOf2_64(MulAmt2))
8355 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8356 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8358 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8359 DAG.getConstant(MulAmt2, VT));
8361 // Do not add new nodes to DAG combiner worklist.
8362 DCI.CombineTo(N, NewMul, false);
8368 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8370 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8371 const X86Subtarget *Subtarget) {
8372 // On X86 with SSE2 support, we can transform this to a vector shift if
8373 // all elements are shifted by the same amount. We can't do this in legalize
8374 // because the a constant vector is typically transformed to a constant pool
8375 // so we have no knowledge of the shift amount.
8376 if (!Subtarget->hasSSE2())
8379 EVT VT = N->getValueType(0);
8380 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8383 SDValue ShAmtOp = N->getOperand(1);
8384 EVT EltVT = VT.getVectorElementType();
8385 DebugLoc DL = N->getDebugLoc();
8387 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8388 unsigned NumElts = VT.getVectorNumElements();
8390 for (; i != NumElts; ++i) {
8391 SDValue Arg = ShAmtOp.getOperand(i);
8392 if (Arg.getOpcode() == ISD::UNDEF) continue;
8396 for (; i != NumElts; ++i) {
8397 SDValue Arg = ShAmtOp.getOperand(i);
8398 if (Arg.getOpcode() == ISD::UNDEF) continue;
8399 if (Arg != BaseShAmt) {
8403 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8404 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8405 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8406 DAG.getIntPtrConstant(0));
8410 if (EltVT.bitsGT(MVT::i32))
8411 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8412 else if (EltVT.bitsLT(MVT::i32))
8413 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
8415 // The shift amount is identical so we can do a vector shift.
8416 SDValue ValOp = N->getOperand(0);
8417 switch (N->getOpcode()) {
8419 llvm_unreachable("Unknown shift opcode!");
8422 if (VT == MVT::v2i64)
8423 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8424 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8426 if (VT == MVT::v4i32)
8427 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8428 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8430 if (VT == MVT::v8i16)
8431 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8432 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8436 if (VT == MVT::v4i32)
8437 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8438 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8440 if (VT == MVT::v8i16)
8441 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8442 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8446 if (VT == MVT::v2i64)
8447 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8448 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8450 if (VT == MVT::v4i32)
8451 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8452 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8454 if (VT == MVT::v8i16)
8455 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8456 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8463 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8464 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8465 const X86Subtarget *Subtarget) {
8466 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8467 // the FP state in cases where an emms may be missing.
8468 // A preferable solution to the general problem is to figure out the right
8469 // places to insert EMMS. This qualifies as a quick hack.
8471 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8472 StoreSDNode *St = cast<StoreSDNode>(N);
8473 EVT VT = St->getValue().getValueType();
8474 if (VT.getSizeInBits() != 64)
8477 const Function *F = DAG.getMachineFunction().getFunction();
8478 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8479 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8480 && Subtarget->hasSSE2();
8481 if ((VT.isVector() ||
8482 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8483 isa<LoadSDNode>(St->getValue()) &&
8484 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8485 St->getChain().hasOneUse() && !St->isVolatile()) {
8486 SDNode* LdVal = St->getValue().getNode();
8488 int TokenFactorIndex = -1;
8489 SmallVector<SDValue, 8> Ops;
8490 SDNode* ChainVal = St->getChain().getNode();
8491 // Must be a store of a load. We currently handle two cases: the load
8492 // is a direct child, and it's under an intervening TokenFactor. It is
8493 // possible to dig deeper under nested TokenFactors.
8494 if (ChainVal == LdVal)
8495 Ld = cast<LoadSDNode>(St->getChain());
8496 else if (St->getValue().hasOneUse() &&
8497 ChainVal->getOpcode() == ISD::TokenFactor) {
8498 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8499 if (ChainVal->getOperand(i).getNode() == LdVal) {
8500 TokenFactorIndex = i;
8501 Ld = cast<LoadSDNode>(St->getValue());
8503 Ops.push_back(ChainVal->getOperand(i));
8507 if (!Ld || !ISD::isNormalLoad(Ld))
8510 // If this is not the MMX case, i.e. we are just turning i64 load/store
8511 // into f64 load/store, avoid the transformation if there are multiple
8512 // uses of the loaded value.
8513 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8516 DebugLoc LdDL = Ld->getDebugLoc();
8517 DebugLoc StDL = N->getDebugLoc();
8518 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8519 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8521 if (Subtarget->is64Bit() || F64IsLegal) {
8522 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8523 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8524 Ld->getBasePtr(), Ld->getSrcValue(),
8525 Ld->getSrcValueOffset(), Ld->isVolatile(),
8526 Ld->getAlignment());
8527 SDValue NewChain = NewLd.getValue(1);
8528 if (TokenFactorIndex != -1) {
8529 Ops.push_back(NewChain);
8530 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8533 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8534 St->getSrcValue(), St->getSrcValueOffset(),
8535 St->isVolatile(), St->getAlignment());
8538 // Otherwise, lower to two pairs of 32-bit loads / stores.
8539 SDValue LoAddr = Ld->getBasePtr();
8540 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8541 DAG.getConstant(4, MVT::i32));
8543 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8544 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8545 Ld->isVolatile(), Ld->getAlignment());
8546 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8547 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8549 MinAlign(Ld->getAlignment(), 4));
8551 SDValue NewChain = LoLd.getValue(1);
8552 if (TokenFactorIndex != -1) {
8553 Ops.push_back(LoLd);
8554 Ops.push_back(HiLd);
8555 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8559 LoAddr = St->getBasePtr();
8560 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8561 DAG.getConstant(4, MVT::i32));
8563 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8564 St->getSrcValue(), St->getSrcValueOffset(),
8565 St->isVolatile(), St->getAlignment());
8566 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8568 St->getSrcValueOffset() + 4,
8570 MinAlign(St->getAlignment(), 4));
8571 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
8576 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8577 /// X86ISD::FXOR nodes.
8578 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8579 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8580 // F[X]OR(0.0, x) -> x
8581 // F[X]OR(x, 0.0) -> x
8582 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8583 if (C->getValueAPF().isPosZero())
8584 return N->getOperand(1);
8585 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8586 if (C->getValueAPF().isPosZero())
8587 return N->getOperand(0);
8591 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8592 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8593 // FAND(0.0, x) -> 0.0
8594 // FAND(x, 0.0) -> 0.0
8595 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8596 if (C->getValueAPF().isPosZero())
8597 return N->getOperand(0);
8598 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8599 if (C->getValueAPF().isPosZero())
8600 return N->getOperand(1);
8604 static SDValue PerformBTCombine(SDNode *N,
8606 TargetLowering::DAGCombinerInfo &DCI) {
8607 // BT ignores high bits in the bit index operand.
8608 SDValue Op1 = N->getOperand(1);
8609 if (Op1.hasOneUse()) {
8610 unsigned BitWidth = Op1.getValueSizeInBits();
8611 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8612 APInt KnownZero, KnownOne;
8613 TargetLowering::TargetLoweringOpt TLO(DAG);
8614 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8615 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8616 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8617 DCI.CommitTargetLoweringOpt(TLO);
8622 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8623 SDValue Op = N->getOperand(0);
8624 if (Op.getOpcode() == ISD::BIT_CONVERT)
8625 Op = Op.getOperand(0);
8626 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
8627 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8628 VT.getVectorElementType().getSizeInBits() ==
8629 OpVT.getVectorElementType().getSizeInBits()) {
8630 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8635 // On X86 and X86-64, atomic operations are lowered to locked instructions.
8636 // Locked instructions, in turn, have implicit fence semantics (all memory
8637 // operations are flushed before issuing the locked instruction, and the
8638 // are not buffered), so we can fold away the common pattern of
8639 // fence-atomic-fence.
8640 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
8641 SDValue atomic = N->getOperand(0);
8642 switch (atomic.getOpcode()) {
8643 case ISD::ATOMIC_CMP_SWAP:
8644 case ISD::ATOMIC_SWAP:
8645 case ISD::ATOMIC_LOAD_ADD:
8646 case ISD::ATOMIC_LOAD_SUB:
8647 case ISD::ATOMIC_LOAD_AND:
8648 case ISD::ATOMIC_LOAD_OR:
8649 case ISD::ATOMIC_LOAD_XOR:
8650 case ISD::ATOMIC_LOAD_NAND:
8651 case ISD::ATOMIC_LOAD_MIN:
8652 case ISD::ATOMIC_LOAD_MAX:
8653 case ISD::ATOMIC_LOAD_UMIN:
8654 case ISD::ATOMIC_LOAD_UMAX:
8660 SDValue fence = atomic.getOperand(0);
8661 if (fence.getOpcode() != ISD::MEMBARRIER)
8664 switch (atomic.getOpcode()) {
8665 case ISD::ATOMIC_CMP_SWAP:
8666 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8667 atomic.getOperand(1), atomic.getOperand(2),
8668 atomic.getOperand(3));
8669 case ISD::ATOMIC_SWAP:
8670 case ISD::ATOMIC_LOAD_ADD:
8671 case ISD::ATOMIC_LOAD_SUB:
8672 case ISD::ATOMIC_LOAD_AND:
8673 case ISD::ATOMIC_LOAD_OR:
8674 case ISD::ATOMIC_LOAD_XOR:
8675 case ISD::ATOMIC_LOAD_NAND:
8676 case ISD::ATOMIC_LOAD_MIN:
8677 case ISD::ATOMIC_LOAD_MAX:
8678 case ISD::ATOMIC_LOAD_UMIN:
8679 case ISD::ATOMIC_LOAD_UMAX:
8680 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8681 atomic.getOperand(1), atomic.getOperand(2));
8687 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8688 DAGCombinerInfo &DCI) const {
8689 SelectionDAG &DAG = DCI.DAG;
8690 switch (N->getOpcode()) {
8692 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8693 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8694 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8695 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8698 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8699 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8701 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8702 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8703 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8704 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
8705 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
8711 //===----------------------------------------------------------------------===//
8712 // X86 Inline Assembly Support
8713 //===----------------------------------------------------------------------===//
8715 static bool LowerToBSwap(CallInst *CI) {
8716 // FIXME: this should verify that we are targetting a 486 or better. If not,
8717 // we will turn this bswap into something that will be lowered to logical ops
8718 // instead of emitting the bswap asm. For now, we don't support 486 or lower
8719 // so don't worry about this.
8721 // Verify this is a simple bswap.
8722 if (CI->getNumOperands() != 2 ||
8723 CI->getType() != CI->getOperand(1)->getType() ||
8724 !CI->getType()->isInteger())
8727 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8728 if (!Ty || Ty->getBitWidth() % 16 != 0)
8731 // Okay, we can do this xform, do so now.
8732 const Type *Tys[] = { Ty };
8733 Module *M = CI->getParent()->getParent()->getParent();
8734 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
8736 Value *Op = CI->getOperand(1);
8737 Op = CallInst::Create(Int, Op, CI->getName(), CI);
8739 CI->replaceAllUsesWith(Op);
8740 CI->eraseFromParent();
8744 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
8745 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8746 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
8748 std::string AsmStr = IA->getAsmString();
8750 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
8751 std::vector<std::string> AsmPieces;
8752 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
8754 switch (AsmPieces.size()) {
8755 default: return false;
8757 AsmStr = AsmPieces[0];
8759 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
8762 if (AsmPieces.size() == 2 &&
8763 (AsmPieces[0] == "bswap" ||
8764 AsmPieces[0] == "bswapq" ||
8765 AsmPieces[0] == "bswapl") &&
8766 (AsmPieces[1] == "$0" ||
8767 AsmPieces[1] == "${0:q}")) {
8768 // No need to check constraints, nothing other than the equivalent of
8769 // "=r,0" would be valid here.
8770 return LowerToBSwap(CI);
8772 // rorw $$8, ${0:w} --> llvm.bswap.i16
8773 if (CI->getType() == Type::getInt16Ty(CI->getContext()) &&
8774 AsmPieces.size() == 3 &&
8775 AsmPieces[0] == "rorw" &&
8776 AsmPieces[1] == "$$8," &&
8777 AsmPieces[2] == "${0:w}" &&
8778 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
8779 return LowerToBSwap(CI);
8783 if (CI->getType() == Type::getInt64Ty(CI->getContext()) &&
8784 Constraints.size() >= 2 &&
8785 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
8786 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
8787 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
8788 std::vector<std::string> Words;
8789 SplitString(AsmPieces[0], Words, " \t");
8790 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
8792 SplitString(AsmPieces[1], Words, " \t");
8793 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
8795 SplitString(AsmPieces[2], Words, " \t,");
8796 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
8797 Words[2] == "%edx") {
8798 return LowerToBSwap(CI);
8810 /// getConstraintType - Given a constraint letter, return the type of
8811 /// constraint it is for this target.
8812 X86TargetLowering::ConstraintType
8813 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8814 if (Constraint.size() == 1) {
8815 switch (Constraint[0]) {
8827 return C_RegisterClass;
8835 return TargetLowering::getConstraintType(Constraint);
8838 /// LowerXConstraint - try to replace an X constraint, which matches anything,
8839 /// with another that has more specific requirements based on the type of the
8840 /// corresponding operand.
8841 const char *X86TargetLowering::
8842 LowerXConstraint(EVT ConstraintVT) const {
8843 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8844 // 'f' like normal targets.
8845 if (ConstraintVT.isFloatingPoint()) {
8846 if (Subtarget->hasSSE2())
8848 if (Subtarget->hasSSE1())
8852 return TargetLowering::LowerXConstraint(ConstraintVT);
8855 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8856 /// vector. If it is invalid, don't add anything to Ops.
8857 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8860 std::vector<SDValue>&Ops,
8861 SelectionDAG &DAG) const {
8862 SDValue Result(0, 0);
8864 switch (Constraint) {
8867 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8868 if (C->getZExtValue() <= 31) {
8869 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8875 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8876 if (C->getZExtValue() <= 63) {
8877 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8883 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8884 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
8885 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8891 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8892 if (C->getZExtValue() <= 255) {
8893 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8899 // 32-bit signed value
8900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8901 const ConstantInt *CI = C->getConstantIntValue();
8902 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
8903 C->getSExtValue())) {
8904 // Widen to 64 bits here to get it sign extended.
8905 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
8908 // FIXME gcc accepts some relocatable values here too, but only in certain
8909 // memory models; it's complicated.
8914 // 32-bit unsigned value
8915 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8916 const ConstantInt *CI = C->getConstantIntValue();
8917 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
8918 C->getZExtValue())) {
8919 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8923 // FIXME gcc accepts some relocatable values here too, but only in certain
8924 // memory models; it's complicated.
8928 // Literal immediates are always ok.
8929 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8930 // Widen to 64 bits here to get it sign extended.
8931 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
8935 // If we are in non-pic codegen mode, we allow the address of a global (with
8936 // an optional displacement) to be used with 'i'.
8937 GlobalAddressSDNode *GA = 0;
8940 // Match either (GA), (GA+C), (GA+C1+C2), etc.
8942 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
8943 Offset += GA->getOffset();
8945 } else if (Op.getOpcode() == ISD::ADD) {
8946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8947 Offset += C->getZExtValue();
8948 Op = Op.getOperand(0);
8951 } else if (Op.getOpcode() == ISD::SUB) {
8952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8953 Offset += -C->getZExtValue();
8954 Op = Op.getOperand(0);
8959 // Otherwise, this isn't something we can handle, reject it.
8963 GlobalValue *GV = GA->getGlobal();
8964 // If we require an extra load to get this address, as in PIC mode, we
8966 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
8967 getTargetMachine())))
8971 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
8973 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
8979 if (Result.getNode()) {
8980 Ops.push_back(Result);
8983 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8987 std::vector<unsigned> X86TargetLowering::
8988 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8990 if (Constraint.size() == 1) {
8991 // FIXME: not handling fp-stack yet!
8992 switch (Constraint[0]) { // GCC X86 Constraint Letters
8993 default: break; // Unknown constraint letter
8994 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
8995 if (Subtarget->is64Bit()) {
8997 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
8998 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
8999 X86::R10D,X86::R11D,X86::R12D,
9000 X86::R13D,X86::R14D,X86::R15D,
9001 X86::EBP, X86::ESP, 0);
9002 else if (VT == MVT::i16)
9003 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9004 X86::SI, X86::DI, X86::R8W,X86::R9W,
9005 X86::R10W,X86::R11W,X86::R12W,
9006 X86::R13W,X86::R14W,X86::R15W,
9007 X86::BP, X86::SP, 0);
9008 else if (VT == MVT::i8)
9009 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9010 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9011 X86::R10B,X86::R11B,X86::R12B,
9012 X86::R13B,X86::R14B,X86::R15B,
9013 X86::BPL, X86::SPL, 0);
9015 else if (VT == MVT::i64)
9016 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9017 X86::RSI, X86::RDI, X86::R8, X86::R9,
9018 X86::R10, X86::R11, X86::R12,
9019 X86::R13, X86::R14, X86::R15,
9020 X86::RBP, X86::RSP, 0);
9024 // 32-bit fallthrough
9027 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9028 else if (VT == MVT::i16)
9029 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9030 else if (VT == MVT::i8)
9031 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9032 else if (VT == MVT::i64)
9033 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9038 return std::vector<unsigned>();
9041 std::pair<unsigned, const TargetRegisterClass*>
9042 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9044 // First, see if this is a constraint that directly corresponds to an LLVM
9046 if (Constraint.size() == 1) {
9047 // GCC Constraint Letters
9048 switch (Constraint[0]) {
9050 case 'r': // GENERAL_REGS
9051 case 'R': // LEGACY_REGS
9052 case 'l': // INDEX_REGS
9054 return std::make_pair(0U, X86::GR8RegisterClass);
9056 return std::make_pair(0U, X86::GR16RegisterClass);
9057 if (VT == MVT::i32 || !Subtarget->is64Bit())
9058 return std::make_pair(0U, X86::GR32RegisterClass);
9059 return std::make_pair(0U, X86::GR64RegisterClass);
9060 case 'f': // FP Stack registers.
9061 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9062 // value to the correct fpstack register class.
9063 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9064 return std::make_pair(0U, X86::RFP32RegisterClass);
9065 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9066 return std::make_pair(0U, X86::RFP64RegisterClass);
9067 return std::make_pair(0U, X86::RFP80RegisterClass);
9068 case 'y': // MMX_REGS if MMX allowed.
9069 if (!Subtarget->hasMMX()) break;
9070 return std::make_pair(0U, X86::VR64RegisterClass);
9071 case 'Y': // SSE_REGS if SSE2 allowed
9072 if (!Subtarget->hasSSE2()) break;
9074 case 'x': // SSE_REGS if SSE1 allowed
9075 if (!Subtarget->hasSSE1()) break;
9077 switch (VT.getSimpleVT().SimpleTy) {
9079 // Scalar SSE types.
9082 return std::make_pair(0U, X86::FR32RegisterClass);
9085 return std::make_pair(0U, X86::FR64RegisterClass);
9093 return std::make_pair(0U, X86::VR128RegisterClass);
9099 // Use the default implementation in TargetLowering to convert the register
9100 // constraint into a member of a register class.
9101 std::pair<unsigned, const TargetRegisterClass*> Res;
9102 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9104 // Not found as a standard register?
9105 if (Res.second == 0) {
9106 // GCC calls "st(0)" just plain "st".
9107 if (StringsEqualNoCase("{st}", Constraint)) {
9108 Res.first = X86::ST0;
9109 Res.second = X86::RFP80RegisterClass;
9111 // 'A' means EAX + EDX.
9112 if (Constraint == "A") {
9113 Res.first = X86::EAX;
9114 Res.second = X86::GR32_ADRegisterClass;
9119 // Otherwise, check to see if this is a register class of the wrong value
9120 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9121 // turn into {ax},{dx}.
9122 if (Res.second->hasType(VT))
9123 return Res; // Correct type already, nothing to do.
9125 // All of the single-register GCC register classes map their values onto
9126 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9127 // really want an 8-bit or 32-bit register, map to the appropriate register
9128 // class and return the appropriate register.
9129 if (Res.second == X86::GR16RegisterClass) {
9130 if (VT == MVT::i8) {
9131 unsigned DestReg = 0;
9132 switch (Res.first) {
9134 case X86::AX: DestReg = X86::AL; break;
9135 case X86::DX: DestReg = X86::DL; break;
9136 case X86::CX: DestReg = X86::CL; break;
9137 case X86::BX: DestReg = X86::BL; break;
9140 Res.first = DestReg;
9141 Res.second = X86::GR8RegisterClass;
9143 } else if (VT == MVT::i32) {
9144 unsigned DestReg = 0;
9145 switch (Res.first) {
9147 case X86::AX: DestReg = X86::EAX; break;
9148 case X86::DX: DestReg = X86::EDX; break;
9149 case X86::CX: DestReg = X86::ECX; break;
9150 case X86::BX: DestReg = X86::EBX; break;
9151 case X86::SI: DestReg = X86::ESI; break;
9152 case X86::DI: DestReg = X86::EDI; break;
9153 case X86::BP: DestReg = X86::EBP; break;
9154 case X86::SP: DestReg = X86::ESP; break;
9157 Res.first = DestReg;
9158 Res.second = X86::GR32RegisterClass;
9160 } else if (VT == MVT::i64) {
9161 unsigned DestReg = 0;
9162 switch (Res.first) {
9164 case X86::AX: DestReg = X86::RAX; break;
9165 case X86::DX: DestReg = X86::RDX; break;
9166 case X86::CX: DestReg = X86::RCX; break;
9167 case X86::BX: DestReg = X86::RBX; break;
9168 case X86::SI: DestReg = X86::RSI; break;
9169 case X86::DI: DestReg = X86::RDI; break;
9170 case X86::BP: DestReg = X86::RBP; break;
9171 case X86::SP: DestReg = X86::RSP; break;
9174 Res.first = DestReg;
9175 Res.second = X86::GR64RegisterClass;
9178 } else if (Res.second == X86::FR32RegisterClass ||
9179 Res.second == X86::FR64RegisterClass ||
9180 Res.second == X86::VR128RegisterClass) {
9181 // Handle references to XMM physical registers that got mapped into the
9182 // wrong class. This can happen with constraints like {xmm0} where the
9183 // target independent register mapper will just pick the first match it can
9184 // find, ignoring the required type.
9186 Res.second = X86::FR32RegisterClass;
9187 else if (VT == MVT::f64)
9188 Res.second = X86::FR64RegisterClass;
9189 else if (X86::VR128RegisterClass->hasType(VT))
9190 Res.second = X86::VR128RegisterClass;
9196 //===----------------------------------------------------------------------===//
9197 // X86 Widen vector type
9198 //===----------------------------------------------------------------------===//
9200 /// getWidenVectorType: given a vector type, returns the type to widen
9201 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9202 /// If there is no vector type that we want to widen to, returns MVT::Other
9203 /// When and where to widen is target dependent based on the cost of
9204 /// scalarizing vs using the wider vector type.
9206 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9207 assert(VT.isVector());
9208 if (isTypeLegal(VT))
9211 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9212 // type based on element type. This would speed up our search (though
9213 // it may not be worth it since the size of the list is relatively
9215 EVT EltVT = VT.getVectorElementType();
9216 unsigned NElts = VT.getVectorNumElements();
9218 // On X86, it make sense to widen any vector wider than 1
9222 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9223 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9224 EVT SVT = (MVT::SimpleValueType)nVT;
9226 if (isTypeLegal(SVT) &&
9227 SVT.getVectorElementType() == EltVT &&
9228 SVT.getVectorNumElements() > NElts)