1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "X86TargetObjectFile.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalAlias.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/VectorExtras.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Disable16Bit - 16-bit operations typically have a larger encoding than
51 // corresponding 32-bit instructions, and 16-bit code is slow on some
52 // processors. This is an experimental flag to disable 16-bit operations
53 // (which forces them to be Legalized to 32-bit operations).
55 Disable16Bit("disable-16bit", cl::Hidden,
56 cl::desc("Disable use of 16-bit instructions"));
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64 default: llvm_unreachable("unknown subtarget type");
65 case X86Subtarget::isDarwin:
66 if (TM.getSubtarget<X86Subtarget>().is64Bit())
67 return new X8664_MachoTargetObjectFile();
68 return new X8632_MachoTargetObjectFile();
69 case X86Subtarget::isELF:
70 return new TargetLoweringObjectFileELF();
71 case X86Subtarget::isMingw:
72 case X86Subtarget::isCygwin:
73 case X86Subtarget::isWindows:
74 return new TargetLoweringObjectFileCOFF();
79 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(TM)) {
81 Subtarget = &TM.getSubtarget<X86Subtarget>();
82 X86ScalarSSEf64 = Subtarget->hasSSE2();
83 X86ScalarSSEf32 = Subtarget->hasSSE1();
84 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
86 RegInfo = TM.getRegisterInfo();
89 // Set up the TargetLowering object.
91 // X86 is weird, it always uses i8 for shift amounts and setcc results.
92 setShiftAmountType(MVT::i8);
93 setBooleanContents(ZeroOrOneBooleanContent);
94 setSchedulingPreference(SchedulingForRegPressure);
95 setStackPointerRegisterToSaveRestore(X86StackPtr);
97 if (Subtarget->isTargetDarwin()) {
98 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
99 setUseUnderscoreSetJmp(false);
100 setUseUnderscoreLongJmp(false);
101 } else if (Subtarget->isTargetMingw()) {
102 // MS runtime is weird: it exports _setjmp, but longjmp!
103 setUseUnderscoreSetJmp(true);
104 setUseUnderscoreLongJmp(false);
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(true);
110 // Set up the register classes.
111 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 if (X86ScalarSSEf64) {
149 // We have an impenetrably clever algorithm for ui64->double only.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
152 // We have an algorithm for SSE2, and we turn this into a 64-bit
153 // FILD for other targets.
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
157 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
159 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
163 // SSE has no i16 to fp conversion, only i32
164 if (X86ScalarSSEf32) {
165 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
166 // f32 and f64 cases are Legal, f80 case is not
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
177 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
178 // are Legal, f80 is custom lowered.
179 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
182 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
184 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
185 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
187 if (X86ScalarSSEf32) {
188 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
189 // f32 and f64 cases are Legal, f80 case is not
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
196 // Handle FP_TO_UINT by promoting the destination to a larger signed
198 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
200 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
202 if (Subtarget->is64Bit()) {
203 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
204 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
205 } else if (!UseSoftFloat) {
206 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
207 // Expand FP_TO_UINT into a select.
208 // FIXME: We would like to use a Custom expander here eventually to do
209 // the optimal thing for SSE vs. the default expansion in the legalizer.
210 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
212 // With SSE3 we can use fisttpll to convert to a signed i64; without
213 // SSE, we're stuck with a fistpll.
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
217 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
218 if (!X86ScalarSSEf64) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
220 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
223 // Scalar integer divide and remainder are lowered to use operations that
224 // produce two results, to match the available instructions. This exposes
225 // the two-result form to trivial CSE, which is able to combine x/y and x%y
226 // into a single instruction.
228 // Scalar integer multiply-high is also lowered to use two-result
229 // operations, to match the available instructions. However, plain multiply
230 // (low) operations are left as Legal, as there are single-result
231 // instructions for this in x86. Using the two-result multiply instructions
232 // when both high and low results are needed must be arranged by dagcombine.
233 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
234 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
235 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
236 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
237 setOperationAction(ISD::SREM , MVT::i8 , Expand);
238 setOperationAction(ISD::UREM , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
243 setOperationAction(ISD::SREM , MVT::i16 , Expand);
244 setOperationAction(ISD::UREM , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
249 setOperationAction(ISD::SREM , MVT::i32 , Expand);
250 setOperationAction(ISD::UREM , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
255 setOperationAction(ISD::SREM , MVT::i64 , Expand);
256 setOperationAction(ISD::UREM , MVT::i64 , Expand);
258 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
259 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
260 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
261 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
262 if (Subtarget->is64Bit())
263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
267 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
268 setOperationAction(ISD::FREM , MVT::f32 , Expand);
269 setOperationAction(ISD::FREM , MVT::f64 , Expand);
270 setOperationAction(ISD::FREM , MVT::f80 , Expand);
271 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
273 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
274 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
275 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
276 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
278 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
279 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
303 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
304 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
307 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
310 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
312 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
314 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
315 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
316 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
321 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
324 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
325 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
326 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
327 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
328 if (Subtarget->is64Bit())
329 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
330 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
333 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
334 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
335 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
337 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
338 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
339 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
340 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
341 if (Subtarget->is64Bit()) {
342 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
343 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
344 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
347 if (Subtarget->hasSSE1())
348 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
350 if (!Subtarget->hasSSE2())
351 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
353 // Expand certain atomics
354 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
355 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
359 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
360 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
364 if (!Subtarget->is64Bit()) {
365 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
366 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
367 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
374 // Use the default ISD::DBG_STOPPOINT.
375 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
376 // FIXME - use subtarget debug flags
377 if (!Subtarget->isTargetDarwin() &&
378 !Subtarget->isTargetELF() &&
379 !Subtarget->isTargetCygMing()) {
380 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
381 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
385 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
387 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
388 if (Subtarget->is64Bit()) {
389 setExceptionPointerRegister(X86::RAX);
390 setExceptionSelectorRegister(X86::RDX);
392 setExceptionPointerRegister(X86::EAX);
393 setExceptionSelectorRegister(X86::EDX);
395 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
398 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
400 setOperationAction(ISD::TRAP, MVT::Other, Legal);
402 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
403 setOperationAction(ISD::VASTART , MVT::Other, Custom);
404 setOperationAction(ISD::VAEND , MVT::Other, Expand);
405 if (Subtarget->is64Bit()) {
406 setOperationAction(ISD::VAARG , MVT::Other, Custom);
407 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
409 setOperationAction(ISD::VAARG , MVT::Other, Expand);
410 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
413 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
414 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
415 if (Subtarget->is64Bit())
416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
417 if (Subtarget->isTargetCygMing())
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
422 if (!UseSoftFloat && X86ScalarSSEf64) {
423 // f32 and f64 use SSE.
424 // Set up the FP register classes.
425 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
426 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
428 // Use ANDPD to simulate FABS.
429 setOperationAction(ISD::FABS , MVT::f64, Custom);
430 setOperationAction(ISD::FABS , MVT::f32, Custom);
432 // Use XORP to simulate FNEG.
433 setOperationAction(ISD::FNEG , MVT::f64, Custom);
434 setOperationAction(ISD::FNEG , MVT::f32, Custom);
436 // Use ANDPD and ORPD to simulate FCOPYSIGN.
437 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
438 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
440 // We don't support sin/cos/fmod
441 setOperationAction(ISD::FSIN , MVT::f64, Expand);
442 setOperationAction(ISD::FCOS , MVT::f64, Expand);
443 setOperationAction(ISD::FSIN , MVT::f32, Expand);
444 setOperationAction(ISD::FCOS , MVT::f32, Expand);
446 // Expand FP immediates into loads from the stack, except for the special
448 addLegalFPImmediate(APFloat(+0.0)); // xorpd
449 addLegalFPImmediate(APFloat(+0.0f)); // xorps
450 } else if (!UseSoftFloat && X86ScalarSSEf32) {
451 // Use SSE for f32, x87 for f64.
452 // Set up the FP register classes.
453 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
454 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
456 // Use ANDPS to simulate FABS.
457 setOperationAction(ISD::FABS , MVT::f32, Custom);
459 // Use XORP to simulate FNEG.
460 setOperationAction(ISD::FNEG , MVT::f32, Custom);
462 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
464 // Use ANDPS and ORPS to simulate FCOPYSIGN.
465 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
466 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
468 // We don't support sin/cos/fmod
469 setOperationAction(ISD::FSIN , MVT::f32, Expand);
470 setOperationAction(ISD::FCOS , MVT::f32, Expand);
472 // Special cases we handle for FP constants.
473 addLegalFPImmediate(APFloat(+0.0f)); // xorps
474 addLegalFPImmediate(APFloat(+0.0)); // FLD0
475 addLegalFPImmediate(APFloat(+1.0)); // FLD1
476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
480 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
481 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
483 } else if (!UseSoftFloat) {
484 // f32 and f64 in x87.
485 // Set up the FP register classes.
486 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
487 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
489 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
490 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
492 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
495 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
496 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
498 addLegalFPImmediate(APFloat(+0.0)); // FLD0
499 addLegalFPImmediate(APFloat(+1.0)); // FLD1
500 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
501 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
502 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
503 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
504 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
505 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
508 // Long double always uses X87.
510 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
511 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
512 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
515 APFloat TmpFlt(+0.0);
516 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
518 addLegalFPImmediate(TmpFlt); // FLD0
520 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
521 APFloat TmpFlt2(+1.0);
522 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
524 addLegalFPImmediate(TmpFlt2); // FLD1
525 TmpFlt2.changeSign();
526 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
530 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
531 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
535 // Always use a library call for pow.
536 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
537 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
538 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
540 setOperationAction(ISD::FLOG, MVT::f80, Expand);
541 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
542 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
543 setOperationAction(ISD::FEXP, MVT::f80, Expand);
544 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
546 // First set operation action for all vector types to either promote
547 // (for widening) or expand (for scalarization). Then we will selectively
548 // turn on ones that can be effectively codegen'd.
549 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
550 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
551 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
566 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
567 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
601 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
602 // with -msoft-float, disable use of MMX as well.
603 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
604 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
605 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
606 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
607 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
608 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
610 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
611 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
612 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
613 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
615 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
616 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
617 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
618 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
620 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
621 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
623 setOperationAction(ISD::AND, MVT::v8i8, Promote);
624 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
625 setOperationAction(ISD::AND, MVT::v4i16, Promote);
626 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
627 setOperationAction(ISD::AND, MVT::v2i32, Promote);
628 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
629 setOperationAction(ISD::AND, MVT::v1i64, Legal);
631 setOperationAction(ISD::OR, MVT::v8i8, Promote);
632 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
633 setOperationAction(ISD::OR, MVT::v4i16, Promote);
634 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
635 setOperationAction(ISD::OR, MVT::v2i32, Promote);
636 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
637 setOperationAction(ISD::OR, MVT::v1i64, Legal);
639 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
640 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
641 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
642 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
643 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
644 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
645 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
647 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
648 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
649 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
650 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
651 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
652 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
653 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
654 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
655 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
657 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
658 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
659 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
660 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
661 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
663 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
664 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
665 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
668 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
669 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
670 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
671 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
673 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
675 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
676 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
677 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
678 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
679 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
680 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
681 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
682 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
683 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
686 if (!UseSoftFloat && Subtarget->hasSSE1()) {
687 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
689 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
690 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
691 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
692 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
693 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
694 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
695 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
696 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
697 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
698 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
699 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
700 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
703 if (!UseSoftFloat && Subtarget->hasSSE2()) {
704 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
706 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
707 // registers cannot be used even for integer operations.
708 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
709 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
710 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
711 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
713 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
714 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
715 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
716 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
717 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
718 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
719 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
720 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
721 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
722 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
723 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
724 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
725 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
726 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
727 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
728 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
730 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
731 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
732 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
733 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
735 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
736 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
737 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
738 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
739 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
741 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
742 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
743 EVT VT = (MVT::SimpleValueType)i;
744 // Do not attempt to custom lower non-power-of-2 vectors
745 if (!isPowerOf2_32(VT.getVectorNumElements()))
747 // Do not attempt to custom lower non-128-bit vectors
748 if (!VT.is128BitVector())
750 setOperationAction(ISD::BUILD_VECTOR,
751 VT.getSimpleVT().SimpleTy, Custom);
752 setOperationAction(ISD::VECTOR_SHUFFLE,
753 VT.getSimpleVT().SimpleTy, Custom);
754 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
755 VT.getSimpleVT().SimpleTy, Custom);
758 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
759 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
760 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
761 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
762 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
763 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
765 if (Subtarget->is64Bit()) {
766 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
767 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
770 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
771 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
772 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
775 // Do not attempt to promote non-128-bit vectors
776 if (!VT.is128BitVector()) {
779 setOperationAction(ISD::AND, SVT, Promote);
780 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
781 setOperationAction(ISD::OR, SVT, Promote);
782 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
783 setOperationAction(ISD::XOR, SVT, Promote);
784 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
785 setOperationAction(ISD::LOAD, SVT, Promote);
786 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
787 setOperationAction(ISD::SELECT, SVT, Promote);
788 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
791 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
793 // Custom lower v2i64 and v2f64 selects.
794 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
795 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
796 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
797 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
799 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
800 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
801 if (!DisableMMX && Subtarget->hasMMX()) {
802 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
803 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
807 if (Subtarget->hasSSE41()) {
808 // FIXME: Do we need to handle scalar-to-vector here?
809 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
811 // i8 and i16 vectors are custom , because the source register and source
812 // source memory operand types are not the same width. f32 vectors are
813 // custom since the immediate controlling the insert encodes additional
815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
818 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
820 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
825 if (Subtarget->is64Bit()) {
826 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
831 if (Subtarget->hasSSE42()) {
832 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
835 if (!UseSoftFloat && Subtarget->hasAVX()) {
836 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
837 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
838 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
839 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
841 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
842 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
843 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
844 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
845 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
846 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
847 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
848 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
849 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
850 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
851 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
852 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
853 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
854 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
855 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
857 // Operations to consider commented out -v16i16 v32i8
858 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
859 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
860 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
861 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
862 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
863 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
864 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
865 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
866 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
867 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
868 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
869 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
870 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
871 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
873 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
874 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
875 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
876 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
878 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
879 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
880 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
882 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
884 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
885 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
886 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
888 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
889 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
892 // Not sure we want to do this since there are no 256-bit integer
895 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
896 // This includes 256-bit vectors
897 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
898 EVT VT = (MVT::SimpleValueType)i;
900 // Do not attempt to custom lower non-power-of-2 vectors
901 if (!isPowerOf2_32(VT.getVectorNumElements()))
904 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
905 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
906 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
909 if (Subtarget->is64Bit()) {
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
911 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
916 // Not sure we want to do this since there are no 256-bit integer
919 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
920 // Including 256-bit vectors
921 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
922 EVT VT = (MVT::SimpleValueType)i;
924 if (!VT.is256BitVector()) {
927 setOperationAction(ISD::AND, VT, Promote);
928 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
929 setOperationAction(ISD::OR, VT, Promote);
930 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
931 setOperationAction(ISD::XOR, VT, Promote);
932 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
933 setOperationAction(ISD::LOAD, VT, Promote);
934 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
935 setOperationAction(ISD::SELECT, VT, Promote);
936 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
939 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
943 // We want to custom lower some of our intrinsics.
944 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
946 // Add/Sub/Mul with overflow operations are custom lowered.
947 setOperationAction(ISD::SADDO, MVT::i32, Custom);
948 setOperationAction(ISD::SADDO, MVT::i64, Custom);
949 setOperationAction(ISD::UADDO, MVT::i32, Custom);
950 setOperationAction(ISD::UADDO, MVT::i64, Custom);
951 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
952 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
953 setOperationAction(ISD::USUBO, MVT::i32, Custom);
954 setOperationAction(ISD::USUBO, MVT::i64, Custom);
955 setOperationAction(ISD::SMULO, MVT::i32, Custom);
956 setOperationAction(ISD::SMULO, MVT::i64, Custom);
958 if (!Subtarget->is64Bit()) {
959 // These libcalls are not available in 32-bit.
960 setLibcallName(RTLIB::SHL_I128, 0);
961 setLibcallName(RTLIB::SRL_I128, 0);
962 setLibcallName(RTLIB::SRA_I128, 0);
965 // We have target-specific dag combine patterns for the following nodes:
966 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
967 setTargetDAGCombine(ISD::BUILD_VECTOR);
968 setTargetDAGCombine(ISD::SELECT);
969 setTargetDAGCombine(ISD::SHL);
970 setTargetDAGCombine(ISD::SRA);
971 setTargetDAGCombine(ISD::SRL);
972 setTargetDAGCombine(ISD::STORE);
973 setTargetDAGCombine(ISD::MEMBARRIER);
974 if (Subtarget->is64Bit())
975 setTargetDAGCombine(ISD::MUL);
977 computeRegisterProperties();
979 // FIXME: These should be based on subtarget info. Plus, the values should
980 // be smaller when we are in optimizing for size mode.
981 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
982 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
983 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
984 setPrefLoopAlignment(16);
985 benefitFromCodePlacementOpt = true;
989 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
994 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
995 /// the desired ByVal argument alignment.
996 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
999 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1000 if (VTy->getBitWidth() == 128)
1002 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1003 unsigned EltAlign = 0;
1004 getMaxByValAlign(ATy->getElementType(), EltAlign);
1005 if (EltAlign > MaxAlign)
1006 MaxAlign = EltAlign;
1007 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1008 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1009 unsigned EltAlign = 0;
1010 getMaxByValAlign(STy->getElementType(i), EltAlign);
1011 if (EltAlign > MaxAlign)
1012 MaxAlign = EltAlign;
1020 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1021 /// function arguments in the caller parameter area. For X86, aggregates
1022 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1023 /// are at 4-byte boundaries.
1024 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1025 if (Subtarget->is64Bit()) {
1026 // Max of 8 and alignment of type.
1027 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1034 if (Subtarget->hasSSE1())
1035 getMaxByValAlign(Ty, Align);
1039 /// getOptimalMemOpType - Returns the target specific optimal type for load
1040 /// and store operations as a result of memset, memcpy, and memmove
1041 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1044 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1045 bool isSrcConst, bool isSrcStr,
1046 SelectionDAG &DAG) const {
1047 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1048 // linux. This is because the stack realignment code can't handle certain
1049 // cases like PR2962. This should be removed when PR2962 is fixed.
1050 const Function *F = DAG.getMachineFunction().getFunction();
1051 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1052 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1053 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1055 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1058 if (Subtarget->is64Bit() && Size >= 8)
1063 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1065 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1066 SelectionDAG &DAG) const {
1067 if (usesGlobalOffsetTable())
1068 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1069 if (!Subtarget->is64Bit())
1070 // This doesn't have DebugLoc associated with it, but is not really the
1071 // same as a Register.
1072 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1077 /// getFunctionAlignment - Return the Log2 alignment of this function.
1078 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1079 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1082 //===----------------------------------------------------------------------===//
1083 // Return Value Calling Convention Implementation
1084 //===----------------------------------------------------------------------===//
1086 #include "X86GenCallingConv.inc"
1089 X86TargetLowering::LowerReturn(SDValue Chain,
1090 CallingConv::ID CallConv, bool isVarArg,
1091 const SmallVectorImpl<ISD::OutputArg> &Outs,
1092 DebugLoc dl, SelectionDAG &DAG) {
1094 SmallVector<CCValAssign, 16> RVLocs;
1095 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1096 RVLocs, *DAG.getContext());
1097 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1099 // If this is the first return lowered for this function, add the regs to the
1100 // liveout set for the function.
1101 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1102 for (unsigned i = 0; i != RVLocs.size(); ++i)
1103 if (RVLocs[i].isRegLoc())
1104 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1109 SmallVector<SDValue, 6> RetOps;
1110 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1111 // Operand #1 = Bytes To Pop
1112 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1114 // Copy the result values into the output registers.
1115 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1116 CCValAssign &VA = RVLocs[i];
1117 assert(VA.isRegLoc() && "Can only return in registers!");
1118 SDValue ValToCopy = Outs[i].Val;
1120 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1121 // the RET instruction and handled by the FP Stackifier.
1122 if (VA.getLocReg() == X86::ST0 ||
1123 VA.getLocReg() == X86::ST1) {
1124 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1125 // change the value to the FP stack register class.
1126 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1127 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1128 RetOps.push_back(ValToCopy);
1129 // Don't emit a copytoreg.
1133 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1134 // which is returned in RAX / RDX.
1135 if (Subtarget->is64Bit()) {
1136 EVT ValVT = ValToCopy.getValueType();
1137 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1138 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1139 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1140 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1144 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1145 Flag = Chain.getValue(1);
1148 // The x86-64 ABI for returning structs by value requires that we copy
1149 // the sret argument into %rax for the return. We saved the argument into
1150 // a virtual register in the entry block, so now we copy the value out
1152 if (Subtarget->is64Bit() &&
1153 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1154 MachineFunction &MF = DAG.getMachineFunction();
1155 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1156 unsigned Reg = FuncInfo->getSRetReturnReg();
1158 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1159 FuncInfo->setSRetReturnReg(Reg);
1161 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1163 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1164 Flag = Chain.getValue(1);
1167 RetOps[0] = Chain; // Update chain.
1169 // Add the flag if we have it.
1171 RetOps.push_back(Flag);
1173 return DAG.getNode(X86ISD::RET_FLAG, dl,
1174 MVT::Other, &RetOps[0], RetOps.size());
1177 /// LowerCallResult - Lower the result values of a call into the
1178 /// appropriate copies out of appropriate physical registers.
1181 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1182 CallingConv::ID CallConv, bool isVarArg,
1183 const SmallVectorImpl<ISD::InputArg> &Ins,
1184 DebugLoc dl, SelectionDAG &DAG,
1185 SmallVectorImpl<SDValue> &InVals) {
1187 // Assign locations to each value returned by this call.
1188 SmallVector<CCValAssign, 16> RVLocs;
1189 bool Is64Bit = Subtarget->is64Bit();
1190 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1191 RVLocs, *DAG.getContext());
1192 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1194 // Copy all of the result registers out of their specified physreg.
1195 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1196 CCValAssign &VA = RVLocs[i];
1197 EVT CopyVT = VA.getValVT();
1199 // If this is x86-64, and we disabled SSE, we can't return FP values
1200 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1201 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1202 llvm_report_error("SSE register return with SSE disabled");
1205 // If this is a call to a function that returns an fp value on the floating
1206 // point stack, but where we prefer to use the value in xmm registers, copy
1207 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1208 if ((VA.getLocReg() == X86::ST0 ||
1209 VA.getLocReg() == X86::ST1) &&
1210 isScalarFPTypeInSSEReg(VA.getValVT())) {
1215 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1216 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1217 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1218 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1219 MVT::v2i64, InFlag).getValue(1);
1220 Val = Chain.getValue(0);
1221 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1222 Val, DAG.getConstant(0, MVT::i64));
1224 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1225 MVT::i64, InFlag).getValue(1);
1226 Val = Chain.getValue(0);
1228 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1230 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1231 CopyVT, InFlag).getValue(1);
1232 Val = Chain.getValue(0);
1234 InFlag = Chain.getValue(2);
1236 if (CopyVT != VA.getValVT()) {
1237 // Round the F80 the right size, which also moves to the appropriate xmm
1239 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1240 // This truncation won't change the value.
1241 DAG.getIntPtrConstant(1));
1244 InVals.push_back(Val);
1251 //===----------------------------------------------------------------------===//
1252 // C & StdCall & Fast Calling Convention implementation
1253 //===----------------------------------------------------------------------===//
1254 // StdCall calling convention seems to be standard for many Windows' API
1255 // routines and around. It differs from C calling convention just a little:
1256 // callee should clean up the stack, not caller. Symbols should be also
1257 // decorated in some fancy way :) It doesn't support any vector arguments.
1258 // For info on fast calling convention see Fast Calling Convention (tail call)
1259 // implementation LowerX86_32FastCCCallTo.
1261 /// CallIsStructReturn - Determines whether a call uses struct return
1263 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1267 return Outs[0].Flags.isSRet();
1270 /// ArgsAreStructReturn - Determines whether a function uses struct
1271 /// return semantics.
1273 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1277 return Ins[0].Flags.isSRet();
1280 /// IsCalleePop - Determines whether the callee is required to pop its
1281 /// own arguments. Callee pop is necessary to support tail calls.
1282 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1286 switch (CallingConv) {
1289 case CallingConv::X86_StdCall:
1290 return !Subtarget->is64Bit();
1291 case CallingConv::X86_FastCall:
1292 return !Subtarget->is64Bit();
1293 case CallingConv::Fast:
1294 return PerformTailCallOpt;
1298 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1299 /// given CallingConvention value.
1300 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1301 if (Subtarget->is64Bit()) {
1302 if (Subtarget->isTargetWin64())
1303 return CC_X86_Win64_C;
1308 if (CC == CallingConv::X86_FastCall)
1309 return CC_X86_32_FastCall;
1310 else if (CC == CallingConv::Fast)
1311 return CC_X86_32_FastCC;
1316 /// NameDecorationForCallConv - Selects the appropriate decoration to
1317 /// apply to a MachineFunction containing a given calling convention.
1319 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1320 if (CallConv == CallingConv::X86_FastCall)
1322 else if (CallConv == CallingConv::X86_StdCall)
1328 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1329 /// by "Src" to address "Dst" with size and alignment information specified by
1330 /// the specific parameter attribute. The copy will be passed as a byval
1331 /// function parameter.
1333 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1334 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1336 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1337 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1338 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1342 X86TargetLowering::LowerMemArgument(SDValue Chain,
1343 CallingConv::ID CallConv,
1344 const SmallVectorImpl<ISD::InputArg> &Ins,
1345 DebugLoc dl, SelectionDAG &DAG,
1346 const CCValAssign &VA,
1347 MachineFrameInfo *MFI,
1350 // Create the nodes corresponding to a load from this parameter slot.
1351 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1352 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1353 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1356 // If value is passed by pointer we have address passed instead of the value
1358 if (VA.getLocInfo() == CCValAssign::Indirect)
1359 ValVT = VA.getLocVT();
1361 ValVT = VA.getValVT();
1363 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1364 // changed with more analysis.
1365 // In case of tail call optimization mark all arguments mutable. Since they
1366 // could be overwritten by lowering of arguments in case of a tail call.
1367 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1368 VA.getLocMemOffset(), isImmutable);
1369 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1370 if (Flags.isByVal())
1372 return DAG.getLoad(ValVT, dl, Chain, FIN,
1373 PseudoSourceValue::getFixedStack(FI), 0);
1377 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1378 CallingConv::ID CallConv,
1380 const SmallVectorImpl<ISD::InputArg> &Ins,
1383 SmallVectorImpl<SDValue> &InVals) {
1385 MachineFunction &MF = DAG.getMachineFunction();
1386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1388 const Function* Fn = MF.getFunction();
1389 if (Fn->hasExternalLinkage() &&
1390 Subtarget->isTargetCygMing() &&
1391 Fn->getName() == "main")
1392 FuncInfo->setForceFramePointer(true);
1394 // Decorate the function name.
1395 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1397 MachineFrameInfo *MFI = MF.getFrameInfo();
1398 bool Is64Bit = Subtarget->is64Bit();
1399 bool IsWin64 = Subtarget->isTargetWin64();
1401 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1402 "Var args not supported with calling convention fastcc");
1404 // Assign locations to all of the incoming arguments.
1405 SmallVector<CCValAssign, 16> ArgLocs;
1406 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1407 ArgLocs, *DAG.getContext());
1408 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1410 unsigned LastVal = ~0U;
1412 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1413 CCValAssign &VA = ArgLocs[i];
1414 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1416 assert(VA.getValNo() != LastVal &&
1417 "Don't support value assigned to multiple locs yet");
1418 LastVal = VA.getValNo();
1420 if (VA.isRegLoc()) {
1421 EVT RegVT = VA.getLocVT();
1422 TargetRegisterClass *RC = NULL;
1423 if (RegVT == MVT::i32)
1424 RC = X86::GR32RegisterClass;
1425 else if (Is64Bit && RegVT == MVT::i64)
1426 RC = X86::GR64RegisterClass;
1427 else if (RegVT == MVT::f32)
1428 RC = X86::FR32RegisterClass;
1429 else if (RegVT == MVT::f64)
1430 RC = X86::FR64RegisterClass;
1431 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1432 RC = X86::VR128RegisterClass;
1433 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1434 RC = X86::VR64RegisterClass;
1436 llvm_unreachable("Unknown argument type!");
1438 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1439 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1441 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1442 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1444 if (VA.getLocInfo() == CCValAssign::SExt)
1445 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1446 DAG.getValueType(VA.getValVT()));
1447 else if (VA.getLocInfo() == CCValAssign::ZExt)
1448 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1449 DAG.getValueType(VA.getValVT()));
1450 else if (VA.getLocInfo() == CCValAssign::BCvt)
1451 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1453 if (VA.isExtInLoc()) {
1454 // Handle MMX values passed in XMM regs.
1455 if (RegVT.isVector()) {
1456 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1457 ArgValue, DAG.getConstant(0, MVT::i64));
1458 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1460 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1463 assert(VA.isMemLoc());
1464 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1467 // If value is passed via pointer - do a load.
1468 if (VA.getLocInfo() == CCValAssign::Indirect)
1469 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1471 InVals.push_back(ArgValue);
1474 // The x86-64 ABI for returning structs by value requires that we copy
1475 // the sret argument into %rax for the return. Save the argument into
1476 // a virtual register so that we can access it from the return points.
1477 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1478 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1479 unsigned Reg = FuncInfo->getSRetReturnReg();
1481 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1482 FuncInfo->setSRetReturnReg(Reg);
1484 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1485 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1488 unsigned StackSize = CCInfo.getNextStackOffset();
1489 // align stack specially for tail calls
1490 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1491 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1493 // If the function takes variable number of arguments, make a frame index for
1494 // the start of the first vararg value... for expansion of llvm.va_start.
1496 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1497 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1500 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1502 // FIXME: We should really autogenerate these arrays
1503 static const unsigned GPR64ArgRegsWin64[] = {
1504 X86::RCX, X86::RDX, X86::R8, X86::R9
1506 static const unsigned XMMArgRegsWin64[] = {
1507 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1509 static const unsigned GPR64ArgRegs64Bit[] = {
1510 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1512 static const unsigned XMMArgRegs64Bit[] = {
1513 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1514 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1516 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1519 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1520 GPR64ArgRegs = GPR64ArgRegsWin64;
1521 XMMArgRegs = XMMArgRegsWin64;
1523 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1524 GPR64ArgRegs = GPR64ArgRegs64Bit;
1525 XMMArgRegs = XMMArgRegs64Bit;
1527 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1529 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1532 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1533 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1534 "SSE register cannot be used when SSE is disabled!");
1535 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1536 "SSE register cannot be used when SSE is disabled!");
1537 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1538 // Kernel mode asks for SSE to be disabled, so don't push them
1540 TotalNumXMMRegs = 0;
1542 // For X86-64, if there are vararg parameters that are passed via
1543 // registers, then we must store them to their spots on the stack so they
1544 // may be loaded by deferencing the result of va_next.
1545 VarArgsGPOffset = NumIntRegs * 8;
1546 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1547 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1548 TotalNumXMMRegs * 16, 16);
1550 // Store the integer parameter registers.
1551 SmallVector<SDValue, 8> MemOps;
1552 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1553 unsigned Offset = VarArgsGPOffset;
1554 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1555 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1556 DAG.getIntPtrConstant(Offset));
1557 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1558 X86::GR64RegisterClass);
1559 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1561 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1562 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1564 MemOps.push_back(Store);
1568 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1569 // Now store the XMM (fp + vector) parameter registers.
1570 SmallVector<SDValue, 11> SaveXMMOps;
1571 SaveXMMOps.push_back(Chain);
1573 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1574 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1575 SaveXMMOps.push_back(ALVal);
1577 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1578 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1580 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1581 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1582 X86::VR128RegisterClass);
1583 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1584 SaveXMMOps.push_back(Val);
1586 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1588 &SaveXMMOps[0], SaveXMMOps.size()));
1591 if (!MemOps.empty())
1592 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1593 &MemOps[0], MemOps.size());
1597 // Some CCs need callee pop.
1598 if (IsCalleePop(isVarArg, CallConv)) {
1599 BytesToPopOnReturn = StackSize; // Callee pops everything.
1600 BytesCallerReserves = 0;
1602 BytesToPopOnReturn = 0; // Callee pops nothing.
1603 // If this is an sret function, the return should pop the hidden pointer.
1604 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1605 BytesToPopOnReturn = 4;
1606 BytesCallerReserves = StackSize;
1610 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1611 if (CallConv == CallingConv::X86_FastCall)
1612 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1615 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1621 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1622 SDValue StackPtr, SDValue Arg,
1623 DebugLoc dl, SelectionDAG &DAG,
1624 const CCValAssign &VA,
1625 ISD::ArgFlagsTy Flags) {
1626 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1627 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1628 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1629 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1630 if (Flags.isByVal()) {
1631 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1633 return DAG.getStore(Chain, dl, Arg, PtrOff,
1634 PseudoSourceValue::getStack(), LocMemOffset);
1637 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1638 /// optimization is performed and it is required.
1640 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1641 SDValue &OutRetAddr,
1647 if (!IsTailCall || FPDiff==0) return Chain;
1649 // Adjust the Return address stack slot.
1650 EVT VT = getPointerTy();
1651 OutRetAddr = getReturnAddressFrameIndex(DAG);
1653 // Load the "old" Return address.
1654 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1655 return SDValue(OutRetAddr.getNode(), 1);
1658 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1659 /// optimization is performed and it is required (FPDiff!=0).
1661 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1662 SDValue Chain, SDValue RetAddrFrIdx,
1663 bool Is64Bit, int FPDiff, DebugLoc dl) {
1664 // Store the return address to the appropriate stack slot.
1665 if (!FPDiff) return Chain;
1666 // Calculate the new stack slot for the return address.
1667 int SlotSize = Is64Bit ? 8 : 4;
1668 int NewReturnAddrFI =
1669 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1670 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1671 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1672 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1673 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1678 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1679 CallingConv::ID CallConv, bool isVarArg,
1681 const SmallVectorImpl<ISD::OutputArg> &Outs,
1682 const SmallVectorImpl<ISD::InputArg> &Ins,
1683 DebugLoc dl, SelectionDAG &DAG,
1684 SmallVectorImpl<SDValue> &InVals) {
1686 MachineFunction &MF = DAG.getMachineFunction();
1687 bool Is64Bit = Subtarget->is64Bit();
1688 bool IsStructRet = CallIsStructReturn(Outs);
1690 assert((!isTailCall ||
1691 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1692 "IsEligibleForTailCallOptimization missed a case!");
1693 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1694 "Var args not supported with calling convention fastcc");
1696 // Analyze operands of the call, assigning locations to each operand.
1697 SmallVector<CCValAssign, 16> ArgLocs;
1698 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1699 ArgLocs, *DAG.getContext());
1700 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1702 // Get a count of how many bytes are to be pushed on the stack.
1703 unsigned NumBytes = CCInfo.getNextStackOffset();
1704 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1705 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1709 // Lower arguments at fp - stackoffset + fpdiff.
1710 unsigned NumBytesCallerPushed =
1711 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1712 FPDiff = NumBytesCallerPushed - NumBytes;
1714 // Set the delta of movement of the returnaddr stackslot.
1715 // But only set if delta is greater than previous delta.
1716 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1717 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1720 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1722 SDValue RetAddrFrIdx;
1723 // Load return adress for tail calls.
1724 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1727 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1728 SmallVector<SDValue, 8> MemOpChains;
1731 // Walk the register/memloc assignments, inserting copies/loads. In the case
1732 // of tail call optimization arguments are handle later.
1733 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1734 CCValAssign &VA = ArgLocs[i];
1735 EVT RegVT = VA.getLocVT();
1736 SDValue Arg = Outs[i].Val;
1737 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1738 bool isByVal = Flags.isByVal();
1740 // Promote the value if needed.
1741 switch (VA.getLocInfo()) {
1742 default: llvm_unreachable("Unknown loc info!");
1743 case CCValAssign::Full: break;
1744 case CCValAssign::SExt:
1745 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1747 case CCValAssign::ZExt:
1748 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1750 case CCValAssign::AExt:
1751 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1752 // Special case: passing MMX values in XMM registers.
1753 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1754 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1755 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1757 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1759 case CCValAssign::BCvt:
1760 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1762 case CCValAssign::Indirect: {
1763 // Store the argument.
1764 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1765 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1766 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1767 PseudoSourceValue::getFixedStack(FI), 0);
1773 if (VA.isRegLoc()) {
1774 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1776 if (!isTailCall || (isTailCall && isByVal)) {
1777 assert(VA.isMemLoc());
1778 if (StackPtr.getNode() == 0)
1779 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1781 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1782 dl, DAG, VA, Flags));
1787 if (!MemOpChains.empty())
1788 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1789 &MemOpChains[0], MemOpChains.size());
1791 // Build a sequence of copy-to-reg nodes chained together with token chain
1792 // and flag operands which copy the outgoing args into registers.
1794 // Tail call byval lowering might overwrite argument registers so in case of
1795 // tail call optimization the copies to registers are lowered later.
1797 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1798 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1799 RegsToPass[i].second, InFlag);
1800 InFlag = Chain.getValue(1);
1804 if (Subtarget->isPICStyleGOT()) {
1805 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1808 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1809 DAG.getNode(X86ISD::GlobalBaseReg,
1810 DebugLoc::getUnknownLoc(),
1813 InFlag = Chain.getValue(1);
1815 // If we are tail calling and generating PIC/GOT style code load the
1816 // address of the callee into ECX. The value in ecx is used as target of
1817 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1818 // for tail calls on PIC/GOT architectures. Normally we would just put the
1819 // address of GOT into ebx and then call target@PLT. But for tail calls
1820 // ebx would be restored (since ebx is callee saved) before jumping to the
1823 // Note: The actual moving to ECX is done further down.
1824 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1825 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1826 !G->getGlobal()->hasProtectedVisibility())
1827 Callee = LowerGlobalAddress(Callee, DAG);
1828 else if (isa<ExternalSymbolSDNode>(Callee))
1829 Callee = LowerExternalSymbol(Callee, DAG);
1833 if (Is64Bit && isVarArg) {
1834 // From AMD64 ABI document:
1835 // For calls that may call functions that use varargs or stdargs
1836 // (prototype-less calls or calls to functions containing ellipsis (...) in
1837 // the declaration) %al is used as hidden argument to specify the number
1838 // of SSE registers used. The contents of %al do not need to match exactly
1839 // the number of registers, but must be an ubound on the number of SSE
1840 // registers used and is in the range 0 - 8 inclusive.
1842 // FIXME: Verify this on Win64
1843 // Count the number of XMM registers allocated.
1844 static const unsigned XMMArgRegs[] = {
1845 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1846 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1848 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1849 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1850 && "SSE registers cannot be used when SSE is disabled");
1852 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1853 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1854 InFlag = Chain.getValue(1);
1858 // For tail calls lower the arguments to the 'real' stack slot.
1860 // Force all the incoming stack arguments to be loaded from the stack
1861 // before any new outgoing arguments are stored to the stack, because the
1862 // outgoing stack slots may alias the incoming argument stack slots, and
1863 // the alias isn't otherwise explicit. This is slightly more conservative
1864 // than necessary, because it means that each store effectively depends
1865 // on every argument instead of just those arguments it would clobber.
1866 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1868 SmallVector<SDValue, 8> MemOpChains2;
1871 // Do not flag preceeding copytoreg stuff together with the following stuff.
1873 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1874 CCValAssign &VA = ArgLocs[i];
1875 if (!VA.isRegLoc()) {
1876 assert(VA.isMemLoc());
1877 SDValue Arg = Outs[i].Val;
1878 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1879 // Create frame index.
1880 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1881 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1882 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1883 FIN = DAG.getFrameIndex(FI, getPointerTy());
1885 if (Flags.isByVal()) {
1886 // Copy relative to framepointer.
1887 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1888 if (StackPtr.getNode() == 0)
1889 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1891 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1893 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1897 // Store relative to framepointer.
1898 MemOpChains2.push_back(
1899 DAG.getStore(ArgChain, dl, Arg, FIN,
1900 PseudoSourceValue::getFixedStack(FI), 0));
1905 if (!MemOpChains2.empty())
1906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1907 &MemOpChains2[0], MemOpChains2.size());
1909 // Copy arguments to their registers.
1910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1911 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1912 RegsToPass[i].second, InFlag);
1913 InFlag = Chain.getValue(1);
1917 // Store the return address to the appropriate stack slot.
1918 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1922 // If the callee is a GlobalAddress node (quite common, every direct call is)
1923 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1924 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1925 // We should use extra load for direct calls to dllimported functions in
1927 GlobalValue *GV = G->getGlobal();
1928 if (!GV->hasDLLImportLinkage()) {
1929 unsigned char OpFlags = 0;
1931 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1932 // external symbols most go through the PLT in PIC mode. If the symbol
1933 // has hidden or protected visibility, or if it is static or local, then
1934 // we don't need to use the PLT - we can directly call it.
1935 if (Subtarget->isTargetELF() &&
1936 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1937 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1938 OpFlags = X86II::MO_PLT;
1939 } else if (Subtarget->isPICStyleStubAny() &&
1940 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1941 Subtarget->getDarwinVers() < 9) {
1942 // PC-relative references to external symbols should go through $stub,
1943 // unless we're building with the leopard linker or later, which
1944 // automatically synthesizes these stubs.
1945 OpFlags = X86II::MO_DARWIN_STUB;
1948 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1949 G->getOffset(), OpFlags);
1951 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1952 unsigned char OpFlags = 0;
1954 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1955 // symbols should go through the PLT.
1956 if (Subtarget->isTargetELF() &&
1957 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1958 OpFlags = X86II::MO_PLT;
1959 } else if (Subtarget->isPICStyleStubAny() &&
1960 Subtarget->getDarwinVers() < 9) {
1961 // PC-relative references to external symbols should go through $stub,
1962 // unless we're building with the leopard linker or later, which
1963 // automatically synthesizes these stubs.
1964 OpFlags = X86II::MO_DARWIN_STUB;
1967 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
1969 } else if (isTailCall) {
1970 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
1972 Chain = DAG.getCopyToReg(Chain, dl,
1973 DAG.getRegister(Opc, getPointerTy()),
1975 Callee = DAG.getRegister(Opc, getPointerTy());
1976 // Add register as live out.
1977 MF.getRegInfo().addLiveOut(Opc);
1980 // Returns a chain & a flag for retval copy to use.
1981 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1982 SmallVector<SDValue, 8> Ops;
1985 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1986 DAG.getIntPtrConstant(0, true), InFlag);
1987 InFlag = Chain.getValue(1);
1990 Ops.push_back(Chain);
1991 Ops.push_back(Callee);
1994 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1996 // Add argument registers to the end of the list so that they are known live
1998 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1999 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2000 RegsToPass[i].second.getValueType()));
2002 // Add an implicit use GOT pointer in EBX.
2003 if (!isTailCall && Subtarget->isPICStyleGOT())
2004 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2006 // Add an implicit use of AL for x86 vararg functions.
2007 if (Is64Bit && isVarArg)
2008 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2010 if (InFlag.getNode())
2011 Ops.push_back(InFlag);
2014 // If this is the first return lowered for this function, add the regs
2015 // to the liveout set for the function.
2016 if (MF.getRegInfo().liveout_empty()) {
2017 SmallVector<CCValAssign, 16> RVLocs;
2018 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2020 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2021 for (unsigned i = 0; i != RVLocs.size(); ++i)
2022 if (RVLocs[i].isRegLoc())
2023 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2026 assert(((Callee.getOpcode() == ISD::Register &&
2027 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2028 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2029 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2030 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2031 "Expecting an global address, external symbol, or register");
2033 return DAG.getNode(X86ISD::TC_RETURN, dl,
2034 NodeTys, &Ops[0], Ops.size());
2037 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2038 InFlag = Chain.getValue(1);
2040 // Create the CALLSEQ_END node.
2041 unsigned NumBytesForCalleeToPush;
2042 if (IsCalleePop(isVarArg, CallConv))
2043 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2044 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2045 // If this is is a call to a struct-return function, the callee
2046 // pops the hidden struct pointer, so we have to push it back.
2047 // This is common for Darwin/X86, Linux & Mingw32 targets.
2048 NumBytesForCalleeToPush = 4;
2050 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2052 // Returns a flag for retval copy to use.
2053 Chain = DAG.getCALLSEQ_END(Chain,
2054 DAG.getIntPtrConstant(NumBytes, true),
2055 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2058 InFlag = Chain.getValue(1);
2060 // Handle result values, copying them out of physregs into vregs that we
2062 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2063 Ins, dl, DAG, InVals);
2067 //===----------------------------------------------------------------------===//
2068 // Fast Calling Convention (tail call) implementation
2069 //===----------------------------------------------------------------------===//
2071 // Like std call, callee cleans arguments, convention except that ECX is
2072 // reserved for storing the tail called function address. Only 2 registers are
2073 // free for argument passing (inreg). Tail call optimization is performed
2075 // * tailcallopt is enabled
2076 // * caller/callee are fastcc
2077 // On X86_64 architecture with GOT-style position independent code only local
2078 // (within module) calls are supported at the moment.
2079 // To keep the stack aligned according to platform abi the function
2080 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2081 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2082 // If a tail called function callee has more arguments than the caller the
2083 // caller needs to make sure that there is room to move the RETADDR to. This is
2084 // achieved by reserving an area the size of the argument delta right after the
2085 // original REtADDR, but before the saved framepointer or the spilled registers
2086 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2098 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2099 /// for a 16 byte align requirement.
2100 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2101 SelectionDAG& DAG) {
2102 MachineFunction &MF = DAG.getMachineFunction();
2103 const TargetMachine &TM = MF.getTarget();
2104 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2105 unsigned StackAlignment = TFI.getStackAlignment();
2106 uint64_t AlignMask = StackAlignment - 1;
2107 int64_t Offset = StackSize;
2108 uint64_t SlotSize = TD->getPointerSize();
2109 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2110 // Number smaller than 12 so just add the difference.
2111 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2113 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2114 Offset = ((~AlignMask) & Offset) + StackAlignment +
2115 (StackAlignment-SlotSize);
2120 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2121 /// for tail call optimization. Targets which want to do tail call
2122 /// optimization should implement this function.
2124 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2125 CallingConv::ID CalleeCC,
2127 const SmallVectorImpl<ISD::InputArg> &Ins,
2128 SelectionDAG& DAG) const {
2129 MachineFunction &MF = DAG.getMachineFunction();
2130 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2131 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2135 X86TargetLowering::createFastISel(MachineFunction &mf,
2136 MachineModuleInfo *mmo,
2138 DenseMap<const Value *, unsigned> &vm,
2139 DenseMap<const BasicBlock *,
2140 MachineBasicBlock *> &bm,
2141 DenseMap<const AllocaInst *, int> &am
2143 , SmallSet<Instruction*, 8> &cil
2146 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2154 //===----------------------------------------------------------------------===//
2155 // Other Lowering Hooks
2156 //===----------------------------------------------------------------------===//
2159 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2160 MachineFunction &MF = DAG.getMachineFunction();
2161 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2162 int ReturnAddrIndex = FuncInfo->getRAIndex();
2164 if (ReturnAddrIndex == 0) {
2165 // Set up a frame object for the return address.
2166 uint64_t SlotSize = TD->getPointerSize();
2167 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2168 FuncInfo->setRAIndex(ReturnAddrIndex);
2171 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2175 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2176 bool hasSymbolicDisplacement) {
2177 // Offset should fit into 32 bit immediate field.
2178 if (!isInt32(Offset))
2181 // If we don't have a symbolic displacement - we don't have any extra
2183 if (!hasSymbolicDisplacement)
2186 // FIXME: Some tweaks might be needed for medium code model.
2187 if (M != CodeModel::Small && M != CodeModel::Kernel)
2190 // For small code model we assume that latest object is 16MB before end of 31
2191 // bits boundary. We may also accept pretty large negative constants knowing
2192 // that all objects are in the positive half of address space.
2193 if (M == CodeModel::Small && Offset < 16*1024*1024)
2196 // For kernel code model we know that all object resist in the negative half
2197 // of 32bits address space. We may not accept negative offsets, since they may
2198 // be just off and we may accept pretty large positive ones.
2199 if (M == CodeModel::Kernel && Offset > 0)
2205 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2206 /// specific condition code, returning the condition code and the LHS/RHS of the
2207 /// comparison to make.
2208 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2209 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2211 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2212 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2213 // X > -1 -> X == 0, jump !sign.
2214 RHS = DAG.getConstant(0, RHS.getValueType());
2215 return X86::COND_NS;
2216 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2217 // X < 0 -> X == 0, jump on sign.
2219 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2221 RHS = DAG.getConstant(0, RHS.getValueType());
2222 return X86::COND_LE;
2226 switch (SetCCOpcode) {
2227 default: llvm_unreachable("Invalid integer condition!");
2228 case ISD::SETEQ: return X86::COND_E;
2229 case ISD::SETGT: return X86::COND_G;
2230 case ISD::SETGE: return X86::COND_GE;
2231 case ISD::SETLT: return X86::COND_L;
2232 case ISD::SETLE: return X86::COND_LE;
2233 case ISD::SETNE: return X86::COND_NE;
2234 case ISD::SETULT: return X86::COND_B;
2235 case ISD::SETUGT: return X86::COND_A;
2236 case ISD::SETULE: return X86::COND_BE;
2237 case ISD::SETUGE: return X86::COND_AE;
2241 // First determine if it is required or is profitable to flip the operands.
2243 // If LHS is a foldable load, but RHS is not, flip the condition.
2244 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2245 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2246 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2247 std::swap(LHS, RHS);
2250 switch (SetCCOpcode) {
2256 std::swap(LHS, RHS);
2260 // On a floating point condition, the flags are set as follows:
2262 // 0 | 0 | 0 | X > Y
2263 // 0 | 0 | 1 | X < Y
2264 // 1 | 0 | 0 | X == Y
2265 // 1 | 1 | 1 | unordered
2266 switch (SetCCOpcode) {
2267 default: llvm_unreachable("Condcode should be pre-legalized away");
2269 case ISD::SETEQ: return X86::COND_E;
2270 case ISD::SETOLT: // flipped
2272 case ISD::SETGT: return X86::COND_A;
2273 case ISD::SETOLE: // flipped
2275 case ISD::SETGE: return X86::COND_AE;
2276 case ISD::SETUGT: // flipped
2278 case ISD::SETLT: return X86::COND_B;
2279 case ISD::SETUGE: // flipped
2281 case ISD::SETLE: return X86::COND_BE;
2283 case ISD::SETNE: return X86::COND_NE;
2284 case ISD::SETUO: return X86::COND_P;
2285 case ISD::SETO: return X86::COND_NP;
2289 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2290 /// code. Current x86 isa includes the following FP cmov instructions:
2291 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2292 static bool hasFPCMov(unsigned X86CC) {
2308 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2309 /// the specified range (L, H].
2310 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2311 return (Val < 0) || (Val >= Low && Val < Hi);
2314 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2315 /// specified value.
2316 static bool isUndefOrEqual(int Val, int CmpVal) {
2317 if (Val < 0 || Val == CmpVal)
2322 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2323 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2324 /// the second operand.
2325 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2326 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2327 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2328 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2329 return (Mask[0] < 2 && Mask[1] < 2);
2333 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2334 SmallVector<int, 8> M;
2336 return ::isPSHUFDMask(M, N->getValueType(0));
2339 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2340 /// is suitable for input to PSHUFHW.
2341 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2342 if (VT != MVT::v8i16)
2345 // Lower quadword copied in order or undef.
2346 for (int i = 0; i != 4; ++i)
2347 if (Mask[i] >= 0 && Mask[i] != i)
2350 // Upper quadword shuffled.
2351 for (int i = 4; i != 8; ++i)
2352 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2358 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2359 SmallVector<int, 8> M;
2361 return ::isPSHUFHWMask(M, N->getValueType(0));
2364 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2365 /// is suitable for input to PSHUFLW.
2366 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2367 if (VT != MVT::v8i16)
2370 // Upper quadword copied in order.
2371 for (int i = 4; i != 8; ++i)
2372 if (Mask[i] >= 0 && Mask[i] != i)
2375 // Lower quadword shuffled.
2376 for (int i = 0; i != 4; ++i)
2383 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2384 SmallVector<int, 8> M;
2386 return ::isPSHUFLWMask(M, N->getValueType(0));
2389 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2390 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2391 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2392 int NumElems = VT.getVectorNumElements();
2393 if (NumElems != 2 && NumElems != 4)
2396 int Half = NumElems / 2;
2397 for (int i = 0; i < Half; ++i)
2398 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2400 for (int i = Half; i < NumElems; ++i)
2401 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2407 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2408 SmallVector<int, 8> M;
2410 return ::isSHUFPMask(M, N->getValueType(0));
2413 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2414 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2415 /// half elements to come from vector 1 (which would equal the dest.) and
2416 /// the upper half to come from vector 2.
2417 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2418 int NumElems = VT.getVectorNumElements();
2420 if (NumElems != 2 && NumElems != 4)
2423 int Half = NumElems / 2;
2424 for (int i = 0; i < Half; ++i)
2425 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2427 for (int i = Half; i < NumElems; ++i)
2428 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2433 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2434 SmallVector<int, 8> M;
2436 return isCommutedSHUFPMask(M, N->getValueType(0));
2439 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2440 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2441 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2442 if (N->getValueType(0).getVectorNumElements() != 4)
2445 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2446 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2447 isUndefOrEqual(N->getMaskElt(1), 7) &&
2448 isUndefOrEqual(N->getMaskElt(2), 2) &&
2449 isUndefOrEqual(N->getMaskElt(3), 3);
2452 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2453 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2454 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2455 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2457 if (NumElems != 2 && NumElems != 4)
2460 for (unsigned i = 0; i < NumElems/2; ++i)
2461 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2464 for (unsigned i = NumElems/2; i < NumElems; ++i)
2465 if (!isUndefOrEqual(N->getMaskElt(i), i))
2471 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2472 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2474 bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2475 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2477 if (NumElems != 2 && NumElems != 4)
2480 for (unsigned i = 0; i < NumElems/2; ++i)
2481 if (!isUndefOrEqual(N->getMaskElt(i), i))
2484 for (unsigned i = 0; i < NumElems/2; ++i)
2485 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2491 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2492 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2494 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2495 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2500 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2501 isUndefOrEqual(N->getMaskElt(1), 3) &&
2502 isUndefOrEqual(N->getMaskElt(2), 2) &&
2503 isUndefOrEqual(N->getMaskElt(3), 3);
2506 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2507 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2508 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2509 bool V2IsSplat = false) {
2510 int NumElts = VT.getVectorNumElements();
2511 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2514 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2516 int BitI1 = Mask[i+1];
2517 if (!isUndefOrEqual(BitI, j))
2520 if (!isUndefOrEqual(BitI1, NumElts))
2523 if (!isUndefOrEqual(BitI1, j + NumElts))
2530 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2531 SmallVector<int, 8> M;
2533 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2536 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2537 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2538 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2539 bool V2IsSplat = false) {
2540 int NumElts = VT.getVectorNumElements();
2541 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2544 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2546 int BitI1 = Mask[i+1];
2547 if (!isUndefOrEqual(BitI, j + NumElts/2))
2550 if (isUndefOrEqual(BitI1, NumElts))
2553 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2560 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2561 SmallVector<int, 8> M;
2563 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2566 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2567 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2569 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2570 int NumElems = VT.getVectorNumElements();
2571 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2574 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2576 int BitI1 = Mask[i+1];
2577 if (!isUndefOrEqual(BitI, j))
2579 if (!isUndefOrEqual(BitI1, j))
2585 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2586 SmallVector<int, 8> M;
2588 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2591 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2592 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2594 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2595 int NumElems = VT.getVectorNumElements();
2596 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2599 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2601 int BitI1 = Mask[i+1];
2602 if (!isUndefOrEqual(BitI, j))
2604 if (!isUndefOrEqual(BitI1, j))
2610 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2611 SmallVector<int, 8> M;
2613 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2616 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2617 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2618 /// MOVSD, and MOVD, i.e. setting the lowest element.
2619 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2620 if (VT.getVectorElementType().getSizeInBits() < 32)
2623 int NumElts = VT.getVectorNumElements();
2625 if (!isUndefOrEqual(Mask[0], NumElts))
2628 for (int i = 1; i < NumElts; ++i)
2629 if (!isUndefOrEqual(Mask[i], i))
2635 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2636 SmallVector<int, 8> M;
2638 return ::isMOVLMask(M, N->getValueType(0));
2641 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2642 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2643 /// element of vector 2 and the other elements to come from vector 1 in order.
2644 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2645 bool V2IsSplat = false, bool V2IsUndef = false) {
2646 int NumOps = VT.getVectorNumElements();
2647 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2650 if (!isUndefOrEqual(Mask[0], 0))
2653 for (int i = 1; i < NumOps; ++i)
2654 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2655 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2656 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2662 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2663 bool V2IsUndef = false) {
2664 SmallVector<int, 8> M;
2666 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2669 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2670 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2671 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2672 if (N->getValueType(0).getVectorNumElements() != 4)
2675 // Expect 1, 1, 3, 3
2676 for (unsigned i = 0; i < 2; ++i) {
2677 int Elt = N->getMaskElt(i);
2678 if (Elt >= 0 && Elt != 1)
2683 for (unsigned i = 2; i < 4; ++i) {
2684 int Elt = N->getMaskElt(i);
2685 if (Elt >= 0 && Elt != 3)
2690 // Don't use movshdup if it can be done with a shufps.
2691 // FIXME: verify that matching u, u, 3, 3 is what we want.
2695 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2696 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2697 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2698 if (N->getValueType(0).getVectorNumElements() != 4)
2701 // Expect 0, 0, 2, 2
2702 for (unsigned i = 0; i < 2; ++i)
2703 if (N->getMaskElt(i) > 0)
2707 for (unsigned i = 2; i < 4; ++i) {
2708 int Elt = N->getMaskElt(i);
2709 if (Elt >= 0 && Elt != 2)
2714 // Don't use movsldup if it can be done with a shufps.
2718 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2719 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2720 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2721 int e = N->getValueType(0).getVectorNumElements() / 2;
2723 for (int i = 0; i < e; ++i)
2724 if (!isUndefOrEqual(N->getMaskElt(i), i))
2726 for (int i = 0; i < e; ++i)
2727 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2732 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2733 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2735 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2736 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2737 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2739 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2741 for (int i = 0; i < NumOperands; ++i) {
2742 int Val = SVOp->getMaskElt(NumOperands-i-1);
2743 if (Val < 0) Val = 0;
2744 if (Val >= NumOperands) Val -= NumOperands;
2746 if (i != NumOperands - 1)
2752 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2753 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2755 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2756 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2758 // 8 nodes, but we only care about the last 4.
2759 for (unsigned i = 7; i >= 4; --i) {
2760 int Val = SVOp->getMaskElt(i);
2769 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2770 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2772 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2773 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2775 // 8 nodes, but we only care about the first 4.
2776 for (int i = 3; i >= 0; --i) {
2777 int Val = SVOp->getMaskElt(i);
2786 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2788 bool X86::isZeroNode(SDValue Elt) {
2789 return ((isa<ConstantSDNode>(Elt) &&
2790 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2791 (isa<ConstantFPSDNode>(Elt) &&
2792 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2795 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2796 /// their permute mask.
2797 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2798 SelectionDAG &DAG) {
2799 EVT VT = SVOp->getValueType(0);
2800 unsigned NumElems = VT.getVectorNumElements();
2801 SmallVector<int, 8> MaskVec;
2803 for (unsigned i = 0; i != NumElems; ++i) {
2804 int idx = SVOp->getMaskElt(i);
2806 MaskVec.push_back(idx);
2807 else if (idx < (int)NumElems)
2808 MaskVec.push_back(idx + NumElems);
2810 MaskVec.push_back(idx - NumElems);
2812 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2813 SVOp->getOperand(0), &MaskVec[0]);
2816 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2817 /// the two vector operands have swapped position.
2818 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2819 unsigned NumElems = VT.getVectorNumElements();
2820 for (unsigned i = 0; i != NumElems; ++i) {
2824 else if (idx < (int)NumElems)
2825 Mask[i] = idx + NumElems;
2827 Mask[i] = idx - NumElems;
2831 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2832 /// match movhlps. The lower half elements should come from upper half of
2833 /// V1 (and in order), and the upper half elements should come from the upper
2834 /// half of V2 (and in order).
2835 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2836 if (Op->getValueType(0).getVectorNumElements() != 4)
2838 for (unsigned i = 0, e = 2; i != e; ++i)
2839 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2841 for (unsigned i = 2; i != 4; ++i)
2842 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2847 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2848 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2850 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2851 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2853 N = N->getOperand(0).getNode();
2854 if (!ISD::isNON_EXTLoad(N))
2857 *LD = cast<LoadSDNode>(N);
2861 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2862 /// match movlp{s|d}. The lower half elements should come from lower half of
2863 /// V1 (and in order), and the upper half elements should come from the upper
2864 /// half of V2 (and in order). And since V1 will become the source of the
2865 /// MOVLP, it must be either a vector load or a scalar load to vector.
2866 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2867 ShuffleVectorSDNode *Op) {
2868 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2870 // Is V2 is a vector load, don't do this transformation. We will try to use
2871 // load folding shufps op.
2872 if (ISD::isNON_EXTLoad(V2))
2875 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2877 if (NumElems != 2 && NumElems != 4)
2879 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2880 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2882 for (unsigned i = NumElems/2; i != NumElems; ++i)
2883 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2888 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2890 static bool isSplatVector(SDNode *N) {
2891 if (N->getOpcode() != ISD::BUILD_VECTOR)
2894 SDValue SplatValue = N->getOperand(0);
2895 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2896 if (N->getOperand(i) != SplatValue)
2901 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2902 /// to an zero vector.
2903 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
2904 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
2905 SDValue V1 = N->getOperand(0);
2906 SDValue V2 = N->getOperand(1);
2907 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2908 for (unsigned i = 0; i != NumElems; ++i) {
2909 int Idx = N->getMaskElt(i);
2910 if (Idx >= (int)NumElems) {
2911 unsigned Opc = V2.getOpcode();
2912 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2914 if (Opc != ISD::BUILD_VECTOR ||
2915 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
2917 } else if (Idx >= 0) {
2918 unsigned Opc = V1.getOpcode();
2919 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2921 if (Opc != ISD::BUILD_VECTOR ||
2922 !X86::isZeroNode(V1.getOperand(Idx)))
2929 /// getZeroVector - Returns a vector of specified type with all zero elements.
2931 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
2933 assert(VT.isVector() && "Expected a vector type");
2935 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2936 // type. This ensures they get CSE'd.
2938 if (VT.getSizeInBits() == 64) { // MMX
2939 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2940 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2941 } else if (HasSSE2) { // SSE2
2942 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2943 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2945 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2946 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2948 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2951 /// getOnesVector - Returns a vector of specified type with all bits set.
2953 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2954 assert(VT.isVector() && "Expected a vector type");
2956 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2957 // type. This ensures they get CSE'd.
2958 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2960 if (VT.getSizeInBits() == 64) // MMX
2961 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2963 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2964 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2968 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2969 /// that point to V2 points to its first element.
2970 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
2971 EVT VT = SVOp->getValueType(0);
2972 unsigned NumElems = VT.getVectorNumElements();
2974 bool Changed = false;
2975 SmallVector<int, 8> MaskVec;
2976 SVOp->getMask(MaskVec);
2978 for (unsigned i = 0; i != NumElems; ++i) {
2979 if (MaskVec[i] > (int)NumElems) {
2980 MaskVec[i] = NumElems;
2985 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
2986 SVOp->getOperand(1), &MaskVec[0]);
2987 return SDValue(SVOp, 0);
2990 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2991 /// operation of specified width.
2992 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
2994 unsigned NumElems = VT.getVectorNumElements();
2995 SmallVector<int, 8> Mask;
2996 Mask.push_back(NumElems);
2997 for (unsigned i = 1; i != NumElems; ++i)
2999 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3002 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3003 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3005 unsigned NumElems = VT.getVectorNumElements();
3006 SmallVector<int, 8> Mask;
3007 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3009 Mask.push_back(i + NumElems);
3011 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3014 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3015 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3017 unsigned NumElems = VT.getVectorNumElements();
3018 unsigned Half = NumElems/2;
3019 SmallVector<int, 8> Mask;
3020 for (unsigned i = 0; i != Half; ++i) {
3021 Mask.push_back(i + Half);
3022 Mask.push_back(i + NumElems + Half);
3024 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3027 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3028 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3030 if (SV->getValueType(0).getVectorNumElements() <= 4)
3031 return SDValue(SV, 0);
3033 EVT PVT = MVT::v4f32;
3034 EVT VT = SV->getValueType(0);
3035 DebugLoc dl = SV->getDebugLoc();
3036 SDValue V1 = SV->getOperand(0);
3037 int NumElems = VT.getVectorNumElements();
3038 int EltNo = SV->getSplatIndex();
3040 // unpack elements to the correct location
3041 while (NumElems > 4) {
3042 if (EltNo < NumElems/2) {
3043 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3045 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3046 EltNo -= NumElems/2;
3051 // Perform the splat.
3052 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3053 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3054 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3055 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3058 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3059 /// vector of zero or undef vector. This produces a shuffle where the low
3060 /// element of V2 is swizzled into the zero/undef vector, landing at element
3061 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3062 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3063 bool isZero, bool HasSSE2,
3064 SelectionDAG &DAG) {
3065 EVT VT = V2.getValueType();
3067 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3068 unsigned NumElems = VT.getVectorNumElements();
3069 SmallVector<int, 16> MaskVec;
3070 for (unsigned i = 0; i != NumElems; ++i)
3071 // If this is the insertion idx, put the low elt of V2 here.
3072 MaskVec.push_back(i == Idx ? NumElems : i);
3073 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3076 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3077 /// a shuffle that is zero.
3079 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3080 bool Low, SelectionDAG &DAG) {
3081 unsigned NumZeros = 0;
3082 for (int i = 0; i < NumElems; ++i) {
3083 unsigned Index = Low ? i : NumElems-i-1;
3084 int Idx = SVOp->getMaskElt(Index);
3089 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3090 if (Elt.getNode() && X86::isZeroNode(Elt))
3098 /// isVectorShift - Returns true if the shuffle can be implemented as a
3099 /// logical left or right shift of a vector.
3100 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3101 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3102 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3103 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3106 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3109 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3113 bool SeenV1 = false;
3114 bool SeenV2 = false;
3115 for (int i = NumZeros; i < NumElems; ++i) {
3116 int Val = isLeft ? (i - NumZeros) : i;
3117 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3129 if (SeenV1 && SeenV2)
3132 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3138 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3140 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3141 unsigned NumNonZero, unsigned NumZero,
3142 SelectionDAG &DAG, TargetLowering &TLI) {
3146 DebugLoc dl = Op.getDebugLoc();
3149 for (unsigned i = 0; i < 16; ++i) {
3150 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3151 if (ThisIsNonZero && First) {
3153 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3155 V = DAG.getUNDEF(MVT::v8i16);
3160 SDValue ThisElt(0, 0), LastElt(0, 0);
3161 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3162 if (LastIsNonZero) {
3163 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3164 MVT::i16, Op.getOperand(i-1));
3166 if (ThisIsNonZero) {
3167 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3168 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3169 ThisElt, DAG.getConstant(8, MVT::i8));
3171 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3175 if (ThisElt.getNode())
3176 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3177 DAG.getIntPtrConstant(i/2));
3181 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3184 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3186 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3187 unsigned NumNonZero, unsigned NumZero,
3188 SelectionDAG &DAG, TargetLowering &TLI) {
3192 DebugLoc dl = Op.getDebugLoc();
3195 for (unsigned i = 0; i < 8; ++i) {
3196 bool isNonZero = (NonZeros & (1 << i)) != 0;
3200 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3202 V = DAG.getUNDEF(MVT::v8i16);
3205 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3206 MVT::v8i16, V, Op.getOperand(i),
3207 DAG.getIntPtrConstant(i));
3214 /// getVShift - Return a vector logical shift node.
3216 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3217 unsigned NumBits, SelectionDAG &DAG,
3218 const TargetLowering &TLI, DebugLoc dl) {
3219 bool isMMX = VT.getSizeInBits() == 64;
3220 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3221 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3222 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3223 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3224 DAG.getNode(Opc, dl, ShVT, SrcOp,
3225 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3229 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3230 DebugLoc dl = Op.getDebugLoc();
3231 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3232 if (ISD::isBuildVectorAllZeros(Op.getNode())
3233 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3234 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3235 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3236 // eliminated on x86-32 hosts.
3237 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3240 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3241 return getOnesVector(Op.getValueType(), DAG, dl);
3242 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3245 EVT VT = Op.getValueType();
3246 EVT ExtVT = VT.getVectorElementType();
3247 unsigned EVTBits = ExtVT.getSizeInBits();
3249 unsigned NumElems = Op.getNumOperands();
3250 unsigned NumZero = 0;
3251 unsigned NumNonZero = 0;
3252 unsigned NonZeros = 0;
3253 bool IsAllConstants = true;
3254 SmallSet<SDValue, 8> Values;
3255 for (unsigned i = 0; i < NumElems; ++i) {
3256 SDValue Elt = Op.getOperand(i);
3257 if (Elt.getOpcode() == ISD::UNDEF)
3260 if (Elt.getOpcode() != ISD::Constant &&
3261 Elt.getOpcode() != ISD::ConstantFP)
3262 IsAllConstants = false;
3263 if (X86::isZeroNode(Elt))
3266 NonZeros |= (1 << i);
3271 if (NumNonZero == 0) {
3272 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3273 return DAG.getUNDEF(VT);
3276 // Special case for single non-zero, non-undef, element.
3277 if (NumNonZero == 1) {
3278 unsigned Idx = CountTrailingZeros_32(NonZeros);
3279 SDValue Item = Op.getOperand(Idx);
3281 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3282 // the value are obviously zero, truncate the value to i32 and do the
3283 // insertion that way. Only do this if the value is non-constant or if the
3284 // value is a constant being inserted into element 0. It is cheaper to do
3285 // a constant pool load than it is to do a movd + shuffle.
3286 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3287 (!IsAllConstants || Idx == 0)) {
3288 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3289 // Handle MMX and SSE both.
3290 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3291 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3293 // Truncate the value (which may itself be a constant) to i32, and
3294 // convert it to a vector with movd (S2V+shuffle to zero extend).
3295 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3296 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3297 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3298 Subtarget->hasSSE2(), DAG);
3300 // Now we have our 32-bit value zero extended in the low element of
3301 // a vector. If Idx != 0, swizzle it into place.
3303 SmallVector<int, 4> Mask;
3304 Mask.push_back(Idx);
3305 for (unsigned i = 1; i != VecElts; ++i)
3307 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3308 DAG.getUNDEF(Item.getValueType()),
3311 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3315 // If we have a constant or non-constant insertion into the low element of
3316 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3317 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3318 // depending on what the source datatype is.
3321 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3322 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3323 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3324 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3325 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3326 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3328 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3329 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3330 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3331 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3332 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3333 Subtarget->hasSSE2(), DAG);
3334 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3338 // Is it a vector logical left shift?
3339 if (NumElems == 2 && Idx == 1 &&
3340 X86::isZeroNode(Op.getOperand(0)) &&
3341 !X86::isZeroNode(Op.getOperand(1))) {
3342 unsigned NumBits = VT.getSizeInBits();
3343 return getVShift(true, VT,
3344 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3345 VT, Op.getOperand(1)),
3346 NumBits/2, DAG, *this, dl);
3349 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3352 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3353 // is a non-constant being inserted into an element other than the low one,
3354 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3355 // movd/movss) to move this into the low element, then shuffle it into
3357 if (EVTBits == 32) {
3358 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3360 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3361 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3362 Subtarget->hasSSE2(), DAG);
3363 SmallVector<int, 8> MaskVec;
3364 for (unsigned i = 0; i < NumElems; i++)
3365 MaskVec.push_back(i == Idx ? 0 : 1);
3366 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3370 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3371 if (Values.size() == 1)
3374 // A vector full of immediates; various special cases are already
3375 // handled, so this is best done with a single constant-pool load.
3379 // Let legalizer expand 2-wide build_vectors.
3380 if (EVTBits == 64) {
3381 if (NumNonZero == 1) {
3382 // One half is zero or undef.
3383 unsigned Idx = CountTrailingZeros_32(NonZeros);
3384 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3385 Op.getOperand(Idx));
3386 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3387 Subtarget->hasSSE2(), DAG);
3392 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3393 if (EVTBits == 8 && NumElems == 16) {
3394 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3396 if (V.getNode()) return V;
3399 if (EVTBits == 16 && NumElems == 8) {
3400 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3402 if (V.getNode()) return V;
3405 // If element VT is == 32 bits, turn it into a number of shuffles.
3406 SmallVector<SDValue, 8> V;
3408 if (NumElems == 4 && NumZero > 0) {
3409 for (unsigned i = 0; i < 4; ++i) {
3410 bool isZero = !(NonZeros & (1 << i));
3412 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3414 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3417 for (unsigned i = 0; i < 2; ++i) {
3418 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3421 V[i] = V[i*2]; // Must be a zero vector.
3424 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3427 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3430 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3435 SmallVector<int, 8> MaskVec;
3436 bool Reverse = (NonZeros & 0x3) == 2;
3437 for (unsigned i = 0; i < 2; ++i)
3438 MaskVec.push_back(Reverse ? 1-i : i);
3439 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3440 for (unsigned i = 0; i < 2; ++i)
3441 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3442 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3445 if (Values.size() > 2) {
3446 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3447 // values to be inserted is equal to the number of elements, in which case
3448 // use the unpack code below in the hopes of matching the consecutive elts
3449 // load merge pattern for shuffles.
3450 // FIXME: We could probably just check that here directly.
3451 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3452 getSubtarget()->hasSSE41()) {
3453 V[0] = DAG.getUNDEF(VT);
3454 for (unsigned i = 0; i < NumElems; ++i)
3455 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3456 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3457 Op.getOperand(i), DAG.getIntPtrConstant(i));
3460 // Expand into a number of unpckl*.
3462 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3463 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3464 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3465 for (unsigned i = 0; i < NumElems; ++i)
3466 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3468 while (NumElems != 0) {
3469 for (unsigned i = 0; i < NumElems; ++i)
3470 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3479 // v8i16 shuffles - Prefer shuffles in the following order:
3480 // 1. [all] pshuflw, pshufhw, optional move
3481 // 2. [ssse3] 1 x pshufb
3482 // 3. [ssse3] 2 x pshufb + 1 x por
3483 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3485 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3486 SelectionDAG &DAG, X86TargetLowering &TLI) {
3487 SDValue V1 = SVOp->getOperand(0);
3488 SDValue V2 = SVOp->getOperand(1);
3489 DebugLoc dl = SVOp->getDebugLoc();
3490 SmallVector<int, 8> MaskVals;
3492 // Determine if more than 1 of the words in each of the low and high quadwords
3493 // of the result come from the same quadword of one of the two inputs. Undef
3494 // mask values count as coming from any quadword, for better codegen.
3495 SmallVector<unsigned, 4> LoQuad(4);
3496 SmallVector<unsigned, 4> HiQuad(4);
3497 BitVector InputQuads(4);
3498 for (unsigned i = 0; i < 8; ++i) {
3499 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3500 int EltIdx = SVOp->getMaskElt(i);
3501 MaskVals.push_back(EltIdx);
3510 InputQuads.set(EltIdx / 4);
3513 int BestLoQuad = -1;
3514 unsigned MaxQuad = 1;
3515 for (unsigned i = 0; i < 4; ++i) {
3516 if (LoQuad[i] > MaxQuad) {
3518 MaxQuad = LoQuad[i];
3522 int BestHiQuad = -1;
3524 for (unsigned i = 0; i < 4; ++i) {
3525 if (HiQuad[i] > MaxQuad) {
3527 MaxQuad = HiQuad[i];
3531 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3532 // of the two input vectors, shuffle them into one input vector so only a
3533 // single pshufb instruction is necessary. If There are more than 2 input
3534 // quads, disable the next transformation since it does not help SSSE3.
3535 bool V1Used = InputQuads[0] || InputQuads[1];
3536 bool V2Used = InputQuads[2] || InputQuads[3];
3537 if (TLI.getSubtarget()->hasSSSE3()) {
3538 if (InputQuads.count() == 2 && V1Used && V2Used) {
3539 BestLoQuad = InputQuads.find_first();
3540 BestHiQuad = InputQuads.find_next(BestLoQuad);
3542 if (InputQuads.count() > 2) {
3548 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3549 // the shuffle mask. If a quad is scored as -1, that means that it contains
3550 // words from all 4 input quadwords.
3552 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3553 SmallVector<int, 8> MaskV;
3554 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3555 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3556 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3557 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3558 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3559 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3561 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3562 // source words for the shuffle, to aid later transformations.
3563 bool AllWordsInNewV = true;
3564 bool InOrder[2] = { true, true };
3565 for (unsigned i = 0; i != 8; ++i) {
3566 int idx = MaskVals[i];
3568 InOrder[i/4] = false;
3569 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3571 AllWordsInNewV = false;
3575 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3576 if (AllWordsInNewV) {
3577 for (int i = 0; i != 8; ++i) {
3578 int idx = MaskVals[i];
3581 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3582 if ((idx != i) && idx < 4)
3584 if ((idx != i) && idx > 3)
3593 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3594 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3595 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3596 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3597 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3601 // If we have SSSE3, and all words of the result are from 1 input vector,
3602 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3603 // is present, fall back to case 4.
3604 if (TLI.getSubtarget()->hasSSSE3()) {
3605 SmallVector<SDValue,16> pshufbMask;
3607 // If we have elements from both input vectors, set the high bit of the
3608 // shuffle mask element to zero out elements that come from V2 in the V1
3609 // mask, and elements that come from V1 in the V2 mask, so that the two
3610 // results can be OR'd together.
3611 bool TwoInputs = V1Used && V2Used;
3612 for (unsigned i = 0; i != 8; ++i) {
3613 int EltIdx = MaskVals[i] * 2;
3614 if (TwoInputs && (EltIdx >= 16)) {
3615 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3616 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3619 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3620 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3622 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3623 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3624 DAG.getNode(ISD::BUILD_VECTOR, dl,
3625 MVT::v16i8, &pshufbMask[0], 16));
3627 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3629 // Calculate the shuffle mask for the second input, shuffle it, and
3630 // OR it with the first shuffled input.
3632 for (unsigned i = 0; i != 8; ++i) {
3633 int EltIdx = MaskVals[i] * 2;
3635 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3636 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3639 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3640 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3642 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3643 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3644 DAG.getNode(ISD::BUILD_VECTOR, dl,
3645 MVT::v16i8, &pshufbMask[0], 16));
3646 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3647 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3650 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3651 // and update MaskVals with new element order.
3652 BitVector InOrder(8);
3653 if (BestLoQuad >= 0) {
3654 SmallVector<int, 8> MaskV;
3655 for (int i = 0; i != 4; ++i) {
3656 int idx = MaskVals[i];
3658 MaskV.push_back(-1);
3660 } else if ((idx / 4) == BestLoQuad) {
3661 MaskV.push_back(idx & 3);
3664 MaskV.push_back(-1);
3667 for (unsigned i = 4; i != 8; ++i)
3669 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3673 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3674 // and update MaskVals with the new element order.
3675 if (BestHiQuad >= 0) {
3676 SmallVector<int, 8> MaskV;
3677 for (unsigned i = 0; i != 4; ++i)
3679 for (unsigned i = 4; i != 8; ++i) {
3680 int idx = MaskVals[i];
3682 MaskV.push_back(-1);
3684 } else if ((idx / 4) == BestHiQuad) {
3685 MaskV.push_back((idx & 3) + 4);
3688 MaskV.push_back(-1);
3691 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3695 // In case BestHi & BestLo were both -1, which means each quadword has a word
3696 // from each of the four input quadwords, calculate the InOrder bitvector now
3697 // before falling through to the insert/extract cleanup.
3698 if (BestLoQuad == -1 && BestHiQuad == -1) {
3700 for (int i = 0; i != 8; ++i)
3701 if (MaskVals[i] < 0 || MaskVals[i] == i)
3705 // The other elements are put in the right place using pextrw and pinsrw.
3706 for (unsigned i = 0; i != 8; ++i) {
3709 int EltIdx = MaskVals[i];
3712 SDValue ExtOp = (EltIdx < 8)
3713 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3714 DAG.getIntPtrConstant(EltIdx))
3715 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3716 DAG.getIntPtrConstant(EltIdx - 8));
3717 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3718 DAG.getIntPtrConstant(i));
3723 // v16i8 shuffles - Prefer shuffles in the following order:
3724 // 1. [ssse3] 1 x pshufb
3725 // 2. [ssse3] 2 x pshufb + 1 x por
3726 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3728 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3729 SelectionDAG &DAG, X86TargetLowering &TLI) {
3730 SDValue V1 = SVOp->getOperand(0);
3731 SDValue V2 = SVOp->getOperand(1);
3732 DebugLoc dl = SVOp->getDebugLoc();
3733 SmallVector<int, 16> MaskVals;
3734 SVOp->getMask(MaskVals);
3736 // If we have SSSE3, case 1 is generated when all result bytes come from
3737 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3738 // present, fall back to case 3.
3739 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3742 for (unsigned i = 0; i < 16; ++i) {
3743 int EltIdx = MaskVals[i];
3752 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3753 if (TLI.getSubtarget()->hasSSSE3()) {
3754 SmallVector<SDValue,16> pshufbMask;
3756 // If all result elements are from one input vector, then only translate
3757 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3759 // Otherwise, we have elements from both input vectors, and must zero out
3760 // elements that come from V2 in the first mask, and V1 in the second mask
3761 // so that we can OR them together.
3762 bool TwoInputs = !(V1Only || V2Only);
3763 for (unsigned i = 0; i != 16; ++i) {
3764 int EltIdx = MaskVals[i];
3765 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3766 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3769 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3771 // If all the elements are from V2, assign it to V1 and return after
3772 // building the first pshufb.
3775 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3776 DAG.getNode(ISD::BUILD_VECTOR, dl,
3777 MVT::v16i8, &pshufbMask[0], 16));
3781 // Calculate the shuffle mask for the second input, shuffle it, and
3782 // OR it with the first shuffled input.
3784 for (unsigned i = 0; i != 16; ++i) {
3785 int EltIdx = MaskVals[i];
3787 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3790 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3792 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3793 DAG.getNode(ISD::BUILD_VECTOR, dl,
3794 MVT::v16i8, &pshufbMask[0], 16));
3795 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3798 // No SSSE3 - Calculate in place words and then fix all out of place words
3799 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3800 // the 16 different words that comprise the two doublequadword input vectors.
3801 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3802 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3803 SDValue NewV = V2Only ? V2 : V1;
3804 for (int i = 0; i != 8; ++i) {
3805 int Elt0 = MaskVals[i*2];
3806 int Elt1 = MaskVals[i*2+1];
3808 // This word of the result is all undef, skip it.
3809 if (Elt0 < 0 && Elt1 < 0)
3812 // This word of the result is already in the correct place, skip it.
3813 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3815 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3818 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3819 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3822 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3823 // using a single extract together, load it and store it.
3824 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3825 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3826 DAG.getIntPtrConstant(Elt1 / 2));
3827 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3828 DAG.getIntPtrConstant(i));
3832 // If Elt1 is defined, extract it from the appropriate source. If the
3833 // source byte is not also odd, shift the extracted word left 8 bits
3834 // otherwise clear the bottom 8 bits if we need to do an or.
3836 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3837 DAG.getIntPtrConstant(Elt1 / 2));
3838 if ((Elt1 & 1) == 0)
3839 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3840 DAG.getConstant(8, TLI.getShiftAmountTy()));
3842 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3843 DAG.getConstant(0xFF00, MVT::i16));
3845 // If Elt0 is defined, extract it from the appropriate source. If the
3846 // source byte is not also even, shift the extracted word right 8 bits. If
3847 // Elt1 was also defined, OR the extracted values together before
3848 // inserting them in the result.
3850 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3851 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3852 if ((Elt0 & 1) != 0)
3853 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3854 DAG.getConstant(8, TLI.getShiftAmountTy()));
3856 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3857 DAG.getConstant(0x00FF, MVT::i16));
3858 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3861 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3862 DAG.getIntPtrConstant(i));
3864 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3867 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3868 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3869 /// done when every pair / quad of shuffle mask elements point to elements in
3870 /// the right sequence. e.g.
3871 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3873 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3875 TargetLowering &TLI, DebugLoc dl) {
3876 EVT VT = SVOp->getValueType(0);
3877 SDValue V1 = SVOp->getOperand(0);
3878 SDValue V2 = SVOp->getOperand(1);
3879 unsigned NumElems = VT.getVectorNumElements();
3880 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3881 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3882 EVT MaskEltVT = MaskVT.getVectorElementType();
3884 switch (VT.getSimpleVT().SimpleTy) {
3885 default: assert(false && "Unexpected!");
3886 case MVT::v4f32: NewVT = MVT::v2f64; break;
3887 case MVT::v4i32: NewVT = MVT::v2i64; break;
3888 case MVT::v8i16: NewVT = MVT::v4i32; break;
3889 case MVT::v16i8: NewVT = MVT::v4i32; break;
3892 if (NewWidth == 2) {
3898 int Scale = NumElems / NewWidth;
3899 SmallVector<int, 8> MaskVec;
3900 for (unsigned i = 0; i < NumElems; i += Scale) {
3902 for (int j = 0; j < Scale; ++j) {
3903 int EltIdx = SVOp->getMaskElt(i+j);
3907 StartIdx = EltIdx - (EltIdx % Scale);
3908 if (EltIdx != StartIdx + j)
3912 MaskVec.push_back(-1);
3914 MaskVec.push_back(StartIdx / Scale);
3917 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3918 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3919 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
3922 /// getVZextMovL - Return a zero-extending vector move low node.
3924 static SDValue getVZextMovL(EVT VT, EVT OpVT,
3925 SDValue SrcOp, SelectionDAG &DAG,
3926 const X86Subtarget *Subtarget, DebugLoc dl) {
3927 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3928 LoadSDNode *LD = NULL;
3929 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3930 LD = dyn_cast<LoadSDNode>(SrcOp);
3932 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3934 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3935 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
3936 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3937 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3938 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
3940 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3941 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3942 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3943 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3951 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3952 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3953 DAG.getNode(ISD::BIT_CONVERT, dl,
3957 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3960 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3961 SDValue V1 = SVOp->getOperand(0);
3962 SDValue V2 = SVOp->getOperand(1);
3963 DebugLoc dl = SVOp->getDebugLoc();
3964 EVT VT = SVOp->getValueType(0);
3966 SmallVector<std::pair<int, int>, 8> Locs;
3968 SmallVector<int, 8> Mask1(4U, -1);
3969 SmallVector<int, 8> PermMask;
3970 SVOp->getMask(PermMask);
3974 for (unsigned i = 0; i != 4; ++i) {
3975 int Idx = PermMask[i];
3977 Locs[i] = std::make_pair(-1, -1);
3979 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
3981 Locs[i] = std::make_pair(0, NumLo);
3985 Locs[i] = std::make_pair(1, NumHi);
3987 Mask1[2+NumHi] = Idx;
3993 if (NumLo <= 2 && NumHi <= 2) {
3994 // If no more than two elements come from either vector. This can be
3995 // implemented with two shuffles. First shuffle gather the elements.
3996 // The second shuffle, which takes the first shuffle as both of its
3997 // vector operands, put the elements into the right order.
3998 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4000 SmallVector<int, 8> Mask2(4U, -1);
4002 for (unsigned i = 0; i != 4; ++i) {
4003 if (Locs[i].first == -1)
4006 unsigned Idx = (i < 2) ? 0 : 4;
4007 Idx += Locs[i].first * 2 + Locs[i].second;
4012 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4013 } else if (NumLo == 3 || NumHi == 3) {
4014 // Otherwise, we must have three elements from one vector, call it X, and
4015 // one element from the other, call it Y. First, use a shufps to build an
4016 // intermediate vector with the one element from Y and the element from X
4017 // that will be in the same half in the final destination (the indexes don't
4018 // matter). Then, use a shufps to build the final vector, taking the half
4019 // containing the element from Y from the intermediate, and the other half
4022 // Normalize it so the 3 elements come from V1.
4023 CommuteVectorShuffleMask(PermMask, VT);
4027 // Find the element from V2.
4029 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4030 int Val = PermMask[HiIndex];
4037 Mask1[0] = PermMask[HiIndex];
4039 Mask1[2] = PermMask[HiIndex^1];
4041 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4044 Mask1[0] = PermMask[0];
4045 Mask1[1] = PermMask[1];
4046 Mask1[2] = HiIndex & 1 ? 6 : 4;
4047 Mask1[3] = HiIndex & 1 ? 4 : 6;
4048 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4050 Mask1[0] = HiIndex & 1 ? 2 : 0;
4051 Mask1[1] = HiIndex & 1 ? 0 : 2;
4052 Mask1[2] = PermMask[2];
4053 Mask1[3] = PermMask[3];
4058 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4062 // Break it into (shuffle shuffle_hi, shuffle_lo).
4064 SmallVector<int,8> LoMask(4U, -1);
4065 SmallVector<int,8> HiMask(4U, -1);
4067 SmallVector<int,8> *MaskPtr = &LoMask;
4068 unsigned MaskIdx = 0;
4071 for (unsigned i = 0; i != 4; ++i) {
4078 int Idx = PermMask[i];
4080 Locs[i] = std::make_pair(-1, -1);
4081 } else if (Idx < 4) {
4082 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4083 (*MaskPtr)[LoIdx] = Idx;
4086 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4087 (*MaskPtr)[HiIdx] = Idx;
4092 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4093 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4094 SmallVector<int, 8> MaskOps;
4095 for (unsigned i = 0; i != 4; ++i) {
4096 if (Locs[i].first == -1) {
4097 MaskOps.push_back(-1);
4099 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4100 MaskOps.push_back(Idx);
4103 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4107 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4108 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4109 SDValue V1 = Op.getOperand(0);
4110 SDValue V2 = Op.getOperand(1);
4111 EVT VT = Op.getValueType();
4112 DebugLoc dl = Op.getDebugLoc();
4113 unsigned NumElems = VT.getVectorNumElements();
4114 bool isMMX = VT.getSizeInBits() == 64;
4115 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4116 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4117 bool V1IsSplat = false;
4118 bool V2IsSplat = false;
4120 if (isZeroShuffle(SVOp))
4121 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4123 // Promote splats to v4f32.
4124 if (SVOp->isSplat()) {
4125 if (isMMX || NumElems < 4)
4127 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4130 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4132 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4133 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4134 if (NewOp.getNode())
4135 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4136 LowerVECTOR_SHUFFLE(NewOp, DAG));
4137 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4138 // FIXME: Figure out a cleaner way to do this.
4139 // Try to make use of movq to zero out the top part.
4140 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4141 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4142 if (NewOp.getNode()) {
4143 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4144 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4145 DAG, Subtarget, dl);
4147 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4148 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4149 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4150 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4151 DAG, Subtarget, dl);
4155 if (X86::isPSHUFDMask(SVOp))
4158 // Check if this can be converted into a logical shift.
4159 bool isLeft = false;
4162 bool isShift = getSubtarget()->hasSSE2() &&
4163 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4164 if (isShift && ShVal.hasOneUse()) {
4165 // If the shifted value has multiple uses, it may be cheaper to use
4166 // v_set0 + movlhps or movhlps, etc.
4167 EVT EVT = VT.getVectorElementType();
4168 ShAmt *= EVT.getSizeInBits();
4169 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4172 if (X86::isMOVLMask(SVOp)) {
4175 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4176 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4181 // FIXME: fold these into legal mask.
4182 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4183 X86::isMOVSLDUPMask(SVOp) ||
4184 X86::isMOVHLPSMask(SVOp) ||
4185 X86::isMOVHPMask(SVOp) ||
4186 X86::isMOVLPMask(SVOp)))
4189 if (ShouldXformToMOVHLPS(SVOp) ||
4190 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4191 return CommuteVectorShuffle(SVOp, DAG);
4194 // No better options. Use a vshl / vsrl.
4195 EVT EVT = VT.getVectorElementType();
4196 ShAmt *= EVT.getSizeInBits();
4197 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4200 bool Commuted = false;
4201 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4202 // 1,1,1,1 -> v8i16 though.
4203 V1IsSplat = isSplatVector(V1.getNode());
4204 V2IsSplat = isSplatVector(V2.getNode());
4206 // Canonicalize the splat or undef, if present, to be on the RHS.
4207 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4208 Op = CommuteVectorShuffle(SVOp, DAG);
4209 SVOp = cast<ShuffleVectorSDNode>(Op);
4210 V1 = SVOp->getOperand(0);
4211 V2 = SVOp->getOperand(1);
4212 std::swap(V1IsSplat, V2IsSplat);
4213 std::swap(V1IsUndef, V2IsUndef);
4217 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4218 // Shuffling low element of v1 into undef, just return v1.
4221 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4222 // the instruction selector will not match, so get a canonical MOVL with
4223 // swapped operands to undo the commute.
4224 return getMOVL(DAG, dl, VT, V2, V1);
4227 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4228 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4229 X86::isUNPCKLMask(SVOp) ||
4230 X86::isUNPCKHMask(SVOp))
4234 // Normalize mask so all entries that point to V2 points to its first
4235 // element then try to match unpck{h|l} again. If match, return a
4236 // new vector_shuffle with the corrected mask.
4237 SDValue NewMask = NormalizeMask(SVOp, DAG);
4238 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4239 if (NSVOp != SVOp) {
4240 if (X86::isUNPCKLMask(NSVOp, true)) {
4242 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4249 // Commute is back and try unpck* again.
4250 // FIXME: this seems wrong.
4251 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4252 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4253 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4254 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4255 X86::isUNPCKLMask(NewSVOp) ||
4256 X86::isUNPCKHMask(NewSVOp))
4260 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4262 // Normalize the node to match x86 shuffle ops if needed
4263 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4264 return CommuteVectorShuffle(SVOp, DAG);
4266 // Check for legal shuffle and return?
4267 SmallVector<int, 16> PermMask;
4268 SVOp->getMask(PermMask);
4269 if (isShuffleMaskLegal(PermMask, VT))
4272 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4273 if (VT == MVT::v8i16) {
4274 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4275 if (NewOp.getNode())
4279 if (VT == MVT::v16i8) {
4280 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4281 if (NewOp.getNode())
4285 // Handle all 4 wide cases with a number of shuffles except for MMX.
4286 if (NumElems == 4 && !isMMX)
4287 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4293 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4294 SelectionDAG &DAG) {
4295 EVT VT = Op.getValueType();
4296 DebugLoc dl = Op.getDebugLoc();
4297 if (VT.getSizeInBits() == 8) {
4298 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4299 Op.getOperand(0), Op.getOperand(1));
4300 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4301 DAG.getValueType(VT));
4302 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4303 } else if (VT.getSizeInBits() == 16) {
4304 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4305 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4307 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4308 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4309 DAG.getNode(ISD::BIT_CONVERT, dl,
4313 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4314 Op.getOperand(0), Op.getOperand(1));
4315 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4316 DAG.getValueType(VT));
4317 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4318 } else if (VT == MVT::f32) {
4319 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4320 // the result back to FR32 register. It's only worth matching if the
4321 // result has a single use which is a store or a bitcast to i32. And in
4322 // the case of a store, it's not worth it if the index is a constant 0,
4323 // because a MOVSSmr can be used instead, which is smaller and faster.
4324 if (!Op.hasOneUse())
4326 SDNode *User = *Op.getNode()->use_begin();
4327 if ((User->getOpcode() != ISD::STORE ||
4328 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4329 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4330 (User->getOpcode() != ISD::BIT_CONVERT ||
4331 User->getValueType(0) != MVT::i32))
4333 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4334 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4337 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4338 } else if (VT == MVT::i32) {
4339 // ExtractPS works with constant index.
4340 if (isa<ConstantSDNode>(Op.getOperand(1)))
4348 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4349 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4352 if (Subtarget->hasSSE41()) {
4353 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4358 EVT VT = Op.getValueType();
4359 DebugLoc dl = Op.getDebugLoc();
4360 // TODO: handle v16i8.
4361 if (VT.getSizeInBits() == 16) {
4362 SDValue Vec = Op.getOperand(0);
4363 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4365 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4366 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4367 DAG.getNode(ISD::BIT_CONVERT, dl,
4370 // Transform it so it match pextrw which produces a 32-bit result.
4371 EVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
4372 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4373 Op.getOperand(0), Op.getOperand(1));
4374 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4375 DAG.getValueType(VT));
4376 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4377 } else if (VT.getSizeInBits() == 32) {
4378 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4382 // SHUFPS the element to the lowest double word, then movss.
4383 int Mask[4] = { Idx, -1, -1, -1 };
4384 EVT VVT = Op.getOperand(0).getValueType();
4385 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4386 DAG.getUNDEF(VVT), Mask);
4387 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4388 DAG.getIntPtrConstant(0));
4389 } else if (VT.getSizeInBits() == 64) {
4390 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4391 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4392 // to match extract_elt for f64.
4393 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4397 // UNPCKHPD the element to the lowest double word, then movsd.
4398 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4399 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4400 int Mask[2] = { 1, -1 };
4401 EVT VVT = Op.getOperand(0).getValueType();
4402 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4403 DAG.getUNDEF(VVT), Mask);
4404 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4405 DAG.getIntPtrConstant(0));
4412 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4413 EVT VT = Op.getValueType();
4414 EVT EVT = VT.getVectorElementType();
4415 DebugLoc dl = Op.getDebugLoc();
4417 SDValue N0 = Op.getOperand(0);
4418 SDValue N1 = Op.getOperand(1);
4419 SDValue N2 = Op.getOperand(2);
4421 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4422 isa<ConstantSDNode>(N2)) {
4423 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4425 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4427 if (N1.getValueType() != MVT::i32)
4428 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4429 if (N2.getValueType() != MVT::i32)
4430 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4431 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4432 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4433 // Bits [7:6] of the constant are the source select. This will always be
4434 // zero here. The DAG Combiner may combine an extract_elt index into these
4435 // bits. For example (insert (extract, 3), 2) could be matched by putting
4436 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4437 // Bits [5:4] of the constant are the destination select. This is the
4438 // value of the incoming immediate.
4439 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4440 // combine either bitwise AND or insert of float 0.0 to set these bits.
4441 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4442 // Create this as a scalar to vector..
4443 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4444 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4445 } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4446 // PINSR* works with constant index.
4453 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4454 EVT VT = Op.getValueType();
4455 EVT EVT = VT.getVectorElementType();
4457 if (Subtarget->hasSSE41())
4458 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4463 DebugLoc dl = Op.getDebugLoc();
4464 SDValue N0 = Op.getOperand(0);
4465 SDValue N1 = Op.getOperand(1);
4466 SDValue N2 = Op.getOperand(2);
4468 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4469 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4470 // as its second argument.
4471 if (N1.getValueType() != MVT::i32)
4472 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4473 if (N2.getValueType() != MVT::i32)
4474 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4475 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4481 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4482 DebugLoc dl = Op.getDebugLoc();
4483 if (Op.getValueType() == MVT::v2f32)
4484 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4485 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4486 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4487 Op.getOperand(0))));
4489 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4490 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4492 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4493 EVT VT = MVT::v2i32;
4494 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4501 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4502 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4505 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4506 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4507 // one of the above mentioned nodes. It has to be wrapped because otherwise
4508 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4509 // be used to form addressing mode. These wrapped nodes will be selected
4512 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4513 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4515 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4517 unsigned char OpFlag = 0;
4518 unsigned WrapperKind = X86ISD::Wrapper;
4519 CodeModel::Model M = getTargetMachine().getCodeModel();
4521 if (Subtarget->isPICStyleRIPRel() &&
4522 (M == CodeModel::Small || M == CodeModel::Kernel))
4523 WrapperKind = X86ISD::WrapperRIP;
4524 else if (Subtarget->isPICStyleGOT())
4525 OpFlag = X86II::MO_GOTOFF;
4526 else if (Subtarget->isPICStyleStubPIC())
4527 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4529 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4531 CP->getOffset(), OpFlag);
4532 DebugLoc DL = CP->getDebugLoc();
4533 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4534 // With PIC, the address is actually $g + Offset.
4536 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4537 DAG.getNode(X86ISD::GlobalBaseReg,
4538 DebugLoc::getUnknownLoc(), getPointerTy()),
4545 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4546 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4548 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4550 unsigned char OpFlag = 0;
4551 unsigned WrapperKind = X86ISD::Wrapper;
4552 CodeModel::Model M = getTargetMachine().getCodeModel();
4554 if (Subtarget->isPICStyleRIPRel() &&
4555 (M == CodeModel::Small || M == CodeModel::Kernel))
4556 WrapperKind = X86ISD::WrapperRIP;
4557 else if (Subtarget->isPICStyleGOT())
4558 OpFlag = X86II::MO_GOTOFF;
4559 else if (Subtarget->isPICStyleStubPIC())
4560 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4562 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4564 DebugLoc DL = JT->getDebugLoc();
4565 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4567 // With PIC, the address is actually $g + Offset.
4569 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4570 DAG.getNode(X86ISD::GlobalBaseReg,
4571 DebugLoc::getUnknownLoc(), getPointerTy()),
4579 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4580 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4582 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4584 unsigned char OpFlag = 0;
4585 unsigned WrapperKind = X86ISD::Wrapper;
4586 CodeModel::Model M = getTargetMachine().getCodeModel();
4588 if (Subtarget->isPICStyleRIPRel() &&
4589 (M == CodeModel::Small || M == CodeModel::Kernel))
4590 WrapperKind = X86ISD::WrapperRIP;
4591 else if (Subtarget->isPICStyleGOT())
4592 OpFlag = X86II::MO_GOTOFF;
4593 else if (Subtarget->isPICStyleStubPIC())
4594 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4596 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4598 DebugLoc DL = Op.getDebugLoc();
4599 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4602 // With PIC, the address is actually $g + Offset.
4603 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4604 !Subtarget->is64Bit()) {
4605 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4606 DAG.getNode(X86ISD::GlobalBaseReg,
4607 DebugLoc::getUnknownLoc(),
4616 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4618 SelectionDAG &DAG) const {
4619 // Create the TargetGlobalAddress node, folding in the constant
4620 // offset if it is legal.
4621 unsigned char OpFlags =
4622 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4623 CodeModel::Model M = getTargetMachine().getCodeModel();
4625 if (OpFlags == X86II::MO_NO_FLAG &&
4626 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4627 // A direct static reference to a global.
4628 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4631 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4634 if (Subtarget->isPICStyleRIPRel() &&
4635 (M == CodeModel::Small || M == CodeModel::Kernel))
4636 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4638 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4640 // With PIC, the address is actually $g + Offset.
4641 if (isGlobalRelativeToPICBase(OpFlags)) {
4642 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4643 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4647 // For globals that require a load from a stub to get the address, emit the
4649 if (isGlobalStubReference(OpFlags))
4650 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4651 PseudoSourceValue::getGOT(), 0);
4653 // If there was a non-zero offset that we didn't fold, create an explicit
4656 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4657 DAG.getConstant(Offset, getPointerTy()));
4663 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4664 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4665 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4666 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4670 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4671 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4672 unsigned char OperandFlags) {
4673 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4674 DebugLoc dl = GA->getDebugLoc();
4675 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4676 GA->getValueType(0),
4680 SDValue Ops[] = { Chain, TGA, *InFlag };
4681 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4683 SDValue Ops[] = { Chain, TGA };
4684 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4686 SDValue Flag = Chain.getValue(1);
4687 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4690 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4692 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4695 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4696 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4697 DAG.getNode(X86ISD::GlobalBaseReg,
4698 DebugLoc::getUnknownLoc(),
4700 InFlag = Chain.getValue(1);
4702 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4705 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4707 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4709 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4710 X86::RAX, X86II::MO_TLSGD);
4713 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4714 // "local exec" model.
4715 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4716 const EVT PtrVT, TLSModel::Model model,
4718 DebugLoc dl = GA->getDebugLoc();
4719 // Get the Thread Pointer
4720 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4721 DebugLoc::getUnknownLoc(), PtrVT,
4722 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4725 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4728 unsigned char OperandFlags = 0;
4729 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4731 unsigned WrapperKind = X86ISD::Wrapper;
4732 if (model == TLSModel::LocalExec) {
4733 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4734 } else if (is64Bit) {
4735 assert(model == TLSModel::InitialExec);
4736 OperandFlags = X86II::MO_GOTTPOFF;
4737 WrapperKind = X86ISD::WrapperRIP;
4739 assert(model == TLSModel::InitialExec);
4740 OperandFlags = X86II::MO_INDNTPOFF;
4743 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4745 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4746 GA->getOffset(), OperandFlags);
4747 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4749 if (model == TLSModel::InitialExec)
4750 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4751 PseudoSourceValue::getGOT(), 0);
4753 // The address of the thread local variable is the add of the thread
4754 // pointer with the offset of the variable.
4755 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4759 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4760 // TODO: implement the "local dynamic" model
4761 // TODO: implement the "initial exec"model for pic executables
4762 assert(Subtarget->isTargetELF() &&
4763 "TLS not implemented for non-ELF targets");
4764 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4765 const GlobalValue *GV = GA->getGlobal();
4767 // If GV is an alias then use the aliasee for determining
4768 // thread-localness.
4769 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4770 GV = GA->resolveAliasedGlobal(false);
4772 TLSModel::Model model = getTLSModel(GV,
4773 getTargetMachine().getRelocationModel());
4776 case TLSModel::GeneralDynamic:
4777 case TLSModel::LocalDynamic: // not implemented
4778 if (Subtarget->is64Bit())
4779 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4780 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4782 case TLSModel::InitialExec:
4783 case TLSModel::LocalExec:
4784 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4785 Subtarget->is64Bit());
4788 llvm_unreachable("Unreachable");
4793 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4794 /// take a 2 x i32 value to shift plus a shift amount.
4795 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4796 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4797 EVT VT = Op.getValueType();
4798 unsigned VTBits = VT.getSizeInBits();
4799 DebugLoc dl = Op.getDebugLoc();
4800 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4801 SDValue ShOpLo = Op.getOperand(0);
4802 SDValue ShOpHi = Op.getOperand(1);
4803 SDValue ShAmt = Op.getOperand(2);
4804 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4805 DAG.getConstant(VTBits - 1, MVT::i8))
4806 : DAG.getConstant(0, VT);
4809 if (Op.getOpcode() == ISD::SHL_PARTS) {
4810 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4811 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4813 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4814 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4817 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4818 DAG.getConstant(VTBits, MVT::i8));
4819 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4820 AndNode, DAG.getConstant(0, MVT::i8));
4823 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4824 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4825 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4827 if (Op.getOpcode() == ISD::SHL_PARTS) {
4828 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4829 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4831 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4832 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4835 SDValue Ops[2] = { Lo, Hi };
4836 return DAG.getMergeValues(Ops, 2, dl);
4839 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4840 EVT SrcVT = Op.getOperand(0).getValueType();
4842 if (SrcVT.isVector()) {
4843 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4849 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4850 "Unknown SINT_TO_FP to lower!");
4852 // These are really Legal; return the operand so the caller accepts it as
4854 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4856 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4857 Subtarget->is64Bit()) {
4861 DebugLoc dl = Op.getDebugLoc();
4862 unsigned Size = SrcVT.getSizeInBits()/8;
4863 MachineFunction &MF = DAG.getMachineFunction();
4864 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4865 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4866 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4868 PseudoSourceValue::getFixedStack(SSFI), 0);
4869 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4872 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
4874 SelectionDAG &DAG) {
4876 DebugLoc dl = Op.getDebugLoc();
4878 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4880 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4882 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4883 SmallVector<SDValue, 8> Ops;
4884 Ops.push_back(Chain);
4885 Ops.push_back(StackSlot);
4886 Ops.push_back(DAG.getValueType(SrcVT));
4887 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4888 Tys, &Ops[0], Ops.size());
4891 Chain = Result.getValue(1);
4892 SDValue InFlag = Result.getValue(2);
4894 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4895 // shouldn't be necessary except that RFP cannot be live across
4896 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4897 MachineFunction &MF = DAG.getMachineFunction();
4898 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4899 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4900 Tys = DAG.getVTList(MVT::Other);
4901 SmallVector<SDValue, 8> Ops;
4902 Ops.push_back(Chain);
4903 Ops.push_back(Result);
4904 Ops.push_back(StackSlot);
4905 Ops.push_back(DAG.getValueType(Op.getValueType()));
4906 Ops.push_back(InFlag);
4907 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4908 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4909 PseudoSourceValue::getFixedStack(SSFI), 0);
4915 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4916 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4917 // This algorithm is not obvious. Here it is in C code, more or less:
4919 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4920 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4921 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4923 // Copy ints to xmm registers.
4924 __m128i xh = _mm_cvtsi32_si128( hi );
4925 __m128i xl = _mm_cvtsi32_si128( lo );
4927 // Combine into low half of a single xmm register.
4928 __m128i x = _mm_unpacklo_epi32( xh, xl );
4932 // Merge in appropriate exponents to give the integer bits the right
4934 x = _mm_unpacklo_epi32( x, exp );
4936 // Subtract away the biases to deal with the IEEE-754 double precision
4938 d = _mm_sub_pd( (__m128d) x, bias );
4940 // All conversions up to here are exact. The correctly rounded result is
4941 // calculated using the current rounding mode using the following
4943 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4944 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4945 // store doesn't really need to be here (except
4946 // maybe to zero the other double)
4951 DebugLoc dl = Op.getDebugLoc();
4952 LLVMContext *Context = DAG.getContext();
4954 // Build some magic constants.
4955 std::vector<Constant*> CV0;
4956 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
4957 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
4958 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4959 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4960 Constant *C0 = ConstantVector::get(CV0);
4961 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
4963 std::vector<Constant*> CV1;
4965 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
4967 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
4968 Constant *C1 = ConstantVector::get(CV1);
4969 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
4971 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4972 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4974 DAG.getIntPtrConstant(1)));
4975 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4976 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4978 DAG.getIntPtrConstant(0)));
4979 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
4980 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
4981 PseudoSourceValue::getConstantPool(), 0,
4983 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
4984 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4985 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
4986 PseudoSourceValue::getConstantPool(), 0,
4988 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
4990 // Add the halves; easiest way is to swap them into another reg first.
4991 int ShufMask[2] = { 1, -1 };
4992 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
4993 DAG.getUNDEF(MVT::v2f64), ShufMask);
4994 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4995 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
4996 DAG.getIntPtrConstant(0));
4999 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5000 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5001 DebugLoc dl = Op.getDebugLoc();
5002 // FP constant to bias correct the final result.
5003 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5006 // Load the 32-bit value into an XMM register.
5007 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5008 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5010 DAG.getIntPtrConstant(0)));
5012 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5013 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5014 DAG.getIntPtrConstant(0));
5016 // Or the load with the bias.
5017 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5018 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5019 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5021 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5022 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5023 MVT::v2f64, Bias)));
5024 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5025 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5026 DAG.getIntPtrConstant(0));
5028 // Subtract the bias.
5029 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5031 // Handle final rounding.
5032 EVT DestVT = Op.getValueType();
5034 if (DestVT.bitsLT(MVT::f64)) {
5035 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5036 DAG.getIntPtrConstant(0));
5037 } else if (DestVT.bitsGT(MVT::f64)) {
5038 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5041 // Handle final rounding.
5045 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5046 SDValue N0 = Op.getOperand(0);
5047 DebugLoc dl = Op.getDebugLoc();
5049 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5050 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5051 // the optimization here.
5052 if (DAG.SignBitIsZero(N0))
5053 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5055 EVT SrcVT = N0.getValueType();
5056 if (SrcVT == MVT::i64) {
5057 // We only handle SSE2 f64 target here; caller can expand the rest.
5058 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5061 return LowerUINT_TO_FP_i64(Op, DAG);
5062 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5063 return LowerUINT_TO_FP_i32(Op, DAG);
5066 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5068 // Make a 64-bit buffer, and use it to build an FILD.
5069 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5070 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5071 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5072 getPointerTy(), StackSlot, WordOff);
5073 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5074 StackSlot, NULL, 0);
5075 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5076 OffsetSlot, NULL, 0);
5077 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5080 std::pair<SDValue,SDValue> X86TargetLowering::
5081 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5082 DebugLoc dl = Op.getDebugLoc();
5084 EVT DstTy = Op.getValueType();
5087 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5091 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5092 DstTy.getSimpleVT() >= MVT::i16 &&
5093 "Unknown FP_TO_SINT to lower!");
5095 // These are really Legal.
5096 if (DstTy == MVT::i32 &&
5097 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5098 return std::make_pair(SDValue(), SDValue());
5099 if (Subtarget->is64Bit() &&
5100 DstTy == MVT::i64 &&
5101 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5102 return std::make_pair(SDValue(), SDValue());
5104 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5106 MachineFunction &MF = DAG.getMachineFunction();
5107 unsigned MemSize = DstTy.getSizeInBits()/8;
5108 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5109 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5112 switch (DstTy.getSimpleVT().SimpleTy) {
5113 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5114 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5115 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5116 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5119 SDValue Chain = DAG.getEntryNode();
5120 SDValue Value = Op.getOperand(0);
5121 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5122 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5123 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5124 PseudoSourceValue::getFixedStack(SSFI), 0);
5125 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5127 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5129 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5130 Chain = Value.getValue(1);
5131 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5132 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5135 // Build the FP_TO_INT*_IN_MEM
5136 SDValue Ops[] = { Chain, Value, StackSlot };
5137 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5139 return std::make_pair(FIST, StackSlot);
5142 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5143 if (Op.getValueType().isVector()) {
5144 if (Op.getValueType() == MVT::v2i32 &&
5145 Op.getOperand(0).getValueType() == MVT::v2f64) {
5151 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5152 SDValue FIST = Vals.first, StackSlot = Vals.second;
5153 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5154 if (FIST.getNode() == 0) return Op;
5157 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5158 FIST, StackSlot, NULL, 0);
5161 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5162 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5163 SDValue FIST = Vals.first, StackSlot = Vals.second;
5164 assert(FIST.getNode() && "Unexpected failure");
5167 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5168 FIST, StackSlot, NULL, 0);
5171 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5172 LLVMContext *Context = DAG.getContext();
5173 DebugLoc dl = Op.getDebugLoc();
5174 EVT VT = Op.getValueType();
5177 EltVT = VT.getVectorElementType();
5178 std::vector<Constant*> CV;
5179 if (EltVT == MVT::f64) {
5180 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5184 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5190 Constant *C = ConstantVector::get(CV);
5191 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5192 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5193 PseudoSourceValue::getConstantPool(), 0,
5195 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5198 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5199 LLVMContext *Context = DAG.getContext();
5200 DebugLoc dl = Op.getDebugLoc();
5201 EVT VT = Op.getValueType();
5204 EltVT = VT.getVectorElementType();
5205 std::vector<Constant*> CV;
5206 if (EltVT == MVT::f64) {
5207 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5211 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5217 Constant *C = ConstantVector::get(CV);
5218 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5219 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5220 PseudoSourceValue::getConstantPool(), 0,
5222 if (VT.isVector()) {
5223 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5224 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5225 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5227 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5229 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5233 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5234 LLVMContext *Context = DAG.getContext();
5235 SDValue Op0 = Op.getOperand(0);
5236 SDValue Op1 = Op.getOperand(1);
5237 DebugLoc dl = Op.getDebugLoc();
5238 EVT VT = Op.getValueType();
5239 EVT SrcVT = Op1.getValueType();
5241 // If second operand is smaller, extend it first.
5242 if (SrcVT.bitsLT(VT)) {
5243 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5246 // And if it is bigger, shrink it first.
5247 if (SrcVT.bitsGT(VT)) {
5248 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5252 // At this point the operands and the result should have the same
5253 // type, and that won't be f80 since that is not custom lowered.
5255 // First get the sign bit of second operand.
5256 std::vector<Constant*> CV;
5257 if (SrcVT == MVT::f64) {
5258 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5259 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5261 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5262 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5263 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5264 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5266 Constant *C = ConstantVector::get(CV);
5267 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5268 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5269 PseudoSourceValue::getConstantPool(), 0,
5271 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5273 // Shift sign bit right or left if the two operands have different types.
5274 if (SrcVT.bitsGT(VT)) {
5275 // Op0 is MVT::f32, Op1 is MVT::f64.
5276 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5277 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5278 DAG.getConstant(32, MVT::i32));
5279 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5280 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5281 DAG.getIntPtrConstant(0));
5284 // Clear first operand sign bit.
5286 if (VT == MVT::f64) {
5287 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5288 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5290 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5291 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5292 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5293 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5295 C = ConstantVector::get(CV);
5296 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5297 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5298 PseudoSourceValue::getConstantPool(), 0,
5300 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5302 // Or the value with the sign bit.
5303 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5306 /// Emit nodes that will be selected as "test Op0,Op0", or something
5308 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5309 SelectionDAG &DAG) {
5310 DebugLoc dl = Op.getDebugLoc();
5312 // CF and OF aren't always set the way we want. Determine which
5313 // of these we need.
5314 bool NeedCF = false;
5315 bool NeedOF = false;
5317 case X86::COND_A: case X86::COND_AE:
5318 case X86::COND_B: case X86::COND_BE:
5321 case X86::COND_G: case X86::COND_GE:
5322 case X86::COND_L: case X86::COND_LE:
5323 case X86::COND_O: case X86::COND_NO:
5329 // See if we can use the EFLAGS value from the operand instead of
5330 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5331 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5332 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5333 unsigned Opcode = 0;
5334 unsigned NumOperands = 0;
5335 switch (Op.getNode()->getOpcode()) {
5337 // Due to an isel shortcoming, be conservative if this add is likely to
5338 // be selected as part of a load-modify-store instruction. When the root
5339 // node in a match is a store, isel doesn't know how to remap non-chain
5340 // non-flag uses of other nodes in the match, such as the ADD in this
5341 // case. This leads to the ADD being left around and reselected, with
5342 // the result being two adds in the output.
5343 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5344 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5345 if (UI->getOpcode() == ISD::STORE)
5347 if (ConstantSDNode *C =
5348 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5349 // An add of one will be selected as an INC.
5350 if (C->getAPIntValue() == 1) {
5351 Opcode = X86ISD::INC;
5355 // An add of negative one (subtract of one) will be selected as a DEC.
5356 if (C->getAPIntValue().isAllOnesValue()) {
5357 Opcode = X86ISD::DEC;
5362 // Otherwise use a regular EFLAGS-setting add.
5363 Opcode = X86ISD::ADD;
5367 // If the primary and result isn't used, don't bother using X86ISD::AND,
5368 // because a TEST instruction will be better.
5369 bool NonFlagUse = false;
5370 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5371 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5372 if (UI->getOpcode() != ISD::BRCOND &&
5373 UI->getOpcode() != ISD::SELECT &&
5374 UI->getOpcode() != ISD::SETCC) {
5385 // Due to the ISEL shortcoming noted above, be conservative if this op is
5386 // likely to be selected as part of a load-modify-store instruction.
5387 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5388 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5389 if (UI->getOpcode() == ISD::STORE)
5391 // Otherwise use a regular EFLAGS-setting instruction.
5392 switch (Op.getNode()->getOpcode()) {
5393 case ISD::SUB: Opcode = X86ISD::SUB; break;
5394 case ISD::OR: Opcode = X86ISD::OR; break;
5395 case ISD::XOR: Opcode = X86ISD::XOR; break;
5396 case ISD::AND: Opcode = X86ISD::AND; break;
5397 default: llvm_unreachable("unexpected operator!");
5408 return SDValue(Op.getNode(), 1);
5414 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5415 SmallVector<SDValue, 4> Ops;
5416 for (unsigned i = 0; i != NumOperands; ++i)
5417 Ops.push_back(Op.getOperand(i));
5418 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5419 DAG.ReplaceAllUsesWith(Op, New);
5420 return SDValue(New.getNode(), 1);
5424 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5425 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5426 DAG.getConstant(0, Op.getValueType()));
5429 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5431 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5432 SelectionDAG &DAG) {
5433 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5434 if (C->getAPIntValue() == 0)
5435 return EmitTest(Op0, X86CC, DAG);
5437 DebugLoc dl = Op0.getDebugLoc();
5438 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5441 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5442 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5443 SDValue Op0 = Op.getOperand(0);
5444 SDValue Op1 = Op.getOperand(1);
5445 DebugLoc dl = Op.getDebugLoc();
5446 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5448 // Lower (X & (1 << N)) == 0 to BT(X, N).
5449 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5450 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5451 if (Op0.getOpcode() == ISD::AND &&
5453 Op1.getOpcode() == ISD::Constant &&
5454 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5455 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5457 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5458 if (ConstantSDNode *Op010C =
5459 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5460 if (Op010C->getZExtValue() == 1) {
5461 LHS = Op0.getOperand(0);
5462 RHS = Op0.getOperand(1).getOperand(1);
5464 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5465 if (ConstantSDNode *Op000C =
5466 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5467 if (Op000C->getZExtValue() == 1) {
5468 LHS = Op0.getOperand(1);
5469 RHS = Op0.getOperand(0).getOperand(1);
5471 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5472 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5473 SDValue AndLHS = Op0.getOperand(0);
5474 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5475 LHS = AndLHS.getOperand(0);
5476 RHS = AndLHS.getOperand(1);
5480 if (LHS.getNode()) {
5481 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5482 // instruction. Since the shift amount is in-range-or-undefined, we know
5483 // that doing a bittest on the i16 value is ok. We extend to i32 because
5484 // the encoding for the i16 version is larger than the i32 version.
5485 if (LHS.getValueType() == MVT::i8)
5486 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5488 // If the operand types disagree, extend the shift amount to match. Since
5489 // BT ignores high bits (like shifts) we can use anyextend.
5490 if (LHS.getValueType() != RHS.getValueType())
5491 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5493 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5494 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5495 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5496 DAG.getConstant(Cond, MVT::i8), BT);
5500 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5501 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5503 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5504 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5505 DAG.getConstant(X86CC, MVT::i8), Cond);
5508 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5510 SDValue Op0 = Op.getOperand(0);
5511 SDValue Op1 = Op.getOperand(1);
5512 SDValue CC = Op.getOperand(2);
5513 EVT VT = Op.getValueType();
5514 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5515 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5516 DebugLoc dl = Op.getDebugLoc();
5520 EVT VT0 = Op0.getValueType();
5521 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5522 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5525 switch (SetCCOpcode) {
5528 case ISD::SETEQ: SSECC = 0; break;
5530 case ISD::SETGT: Swap = true; // Fallthrough
5532 case ISD::SETOLT: SSECC = 1; break;
5534 case ISD::SETGE: Swap = true; // Fallthrough
5536 case ISD::SETOLE: SSECC = 2; break;
5537 case ISD::SETUO: SSECC = 3; break;
5539 case ISD::SETNE: SSECC = 4; break;
5540 case ISD::SETULE: Swap = true;
5541 case ISD::SETUGE: SSECC = 5; break;
5542 case ISD::SETULT: Swap = true;
5543 case ISD::SETUGT: SSECC = 6; break;
5544 case ISD::SETO: SSECC = 7; break;
5547 std::swap(Op0, Op1);
5549 // In the two special cases we can't handle, emit two comparisons.
5551 if (SetCCOpcode == ISD::SETUEQ) {
5553 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5554 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5555 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5557 else if (SetCCOpcode == ISD::SETONE) {
5559 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5560 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5561 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5563 llvm_unreachable("Illegal FP comparison");
5565 // Handle all other FP comparisons here.
5566 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5569 // We are handling one of the integer comparisons here. Since SSE only has
5570 // GT and EQ comparisons for integer, swapping operands and multiple
5571 // operations may be required for some comparisons.
5572 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5573 bool Swap = false, Invert = false, FlipSigns = false;
5575 switch (VT.getSimpleVT().SimpleTy) {
5578 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5580 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5582 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5583 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5586 switch (SetCCOpcode) {
5588 case ISD::SETNE: Invert = true;
5589 case ISD::SETEQ: Opc = EQOpc; break;
5590 case ISD::SETLT: Swap = true;
5591 case ISD::SETGT: Opc = GTOpc; break;
5592 case ISD::SETGE: Swap = true;
5593 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5594 case ISD::SETULT: Swap = true;
5595 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5596 case ISD::SETUGE: Swap = true;
5597 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5600 std::swap(Op0, Op1);
5602 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5603 // bits of the inputs before performing those operations.
5605 EVT EltVT = VT.getVectorElementType();
5606 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5608 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5609 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5611 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5612 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5615 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5617 // If the logical-not of the result is required, perform that now.
5619 Result = DAG.getNOT(dl, Result, VT);
5624 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5625 static bool isX86LogicalCmp(SDValue Op) {
5626 unsigned Opc = Op.getNode()->getOpcode();
5627 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5629 if (Op.getResNo() == 1 &&
5630 (Opc == X86ISD::ADD ||
5631 Opc == X86ISD::SUB ||
5632 Opc == X86ISD::SMUL ||
5633 Opc == X86ISD::UMUL ||
5634 Opc == X86ISD::INC ||
5635 Opc == X86ISD::DEC ||
5636 Opc == X86ISD::OR ||
5637 Opc == X86ISD::XOR ||
5638 Opc == X86ISD::AND))
5644 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5645 bool addTest = true;
5646 SDValue Cond = Op.getOperand(0);
5647 DebugLoc dl = Op.getDebugLoc();
5650 if (Cond.getOpcode() == ISD::SETCC)
5651 Cond = LowerSETCC(Cond, DAG);
5653 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5654 // setting operand in place of the X86ISD::SETCC.
5655 if (Cond.getOpcode() == X86ISD::SETCC) {
5656 CC = Cond.getOperand(0);
5658 SDValue Cmp = Cond.getOperand(1);
5659 unsigned Opc = Cmp.getOpcode();
5660 EVT VT = Op.getValueType();
5662 bool IllegalFPCMov = false;
5663 if (VT.isFloatingPoint() && !VT.isVector() &&
5664 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5665 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5667 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5668 Opc == X86ISD::BT) { // FIXME
5675 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5676 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5679 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5680 SmallVector<SDValue, 4> Ops;
5681 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5682 // condition is true.
5683 Ops.push_back(Op.getOperand(2));
5684 Ops.push_back(Op.getOperand(1));
5686 Ops.push_back(Cond);
5687 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5690 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5691 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5692 // from the AND / OR.
5693 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5694 Opc = Op.getOpcode();
5695 if (Opc != ISD::OR && Opc != ISD::AND)
5697 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5698 Op.getOperand(0).hasOneUse() &&
5699 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5700 Op.getOperand(1).hasOneUse());
5703 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5704 // 1 and that the SETCC node has a single use.
5705 static bool isXor1OfSetCC(SDValue Op) {
5706 if (Op.getOpcode() != ISD::XOR)
5708 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5709 if (N1C && N1C->getAPIntValue() == 1) {
5710 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5711 Op.getOperand(0).hasOneUse();
5716 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5717 bool addTest = true;
5718 SDValue Chain = Op.getOperand(0);
5719 SDValue Cond = Op.getOperand(1);
5720 SDValue Dest = Op.getOperand(2);
5721 DebugLoc dl = Op.getDebugLoc();
5724 if (Cond.getOpcode() == ISD::SETCC)
5725 Cond = LowerSETCC(Cond, DAG);
5727 // FIXME: LowerXALUO doesn't handle these!!
5728 else if (Cond.getOpcode() == X86ISD::ADD ||
5729 Cond.getOpcode() == X86ISD::SUB ||
5730 Cond.getOpcode() == X86ISD::SMUL ||
5731 Cond.getOpcode() == X86ISD::UMUL)
5732 Cond = LowerXALUO(Cond, DAG);
5735 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5736 // setting operand in place of the X86ISD::SETCC.
5737 if (Cond.getOpcode() == X86ISD::SETCC) {
5738 CC = Cond.getOperand(0);
5740 SDValue Cmp = Cond.getOperand(1);
5741 unsigned Opc = Cmp.getOpcode();
5742 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5743 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5747 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5751 // These can only come from an arithmetic instruction with overflow,
5752 // e.g. SADDO, UADDO.
5753 Cond = Cond.getNode()->getOperand(1);
5760 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5761 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5762 if (CondOpc == ISD::OR) {
5763 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5764 // two branches instead of an explicit OR instruction with a
5766 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5767 isX86LogicalCmp(Cmp)) {
5768 CC = Cond.getOperand(0).getOperand(0);
5769 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5770 Chain, Dest, CC, Cmp);
5771 CC = Cond.getOperand(1).getOperand(0);
5775 } else { // ISD::AND
5776 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5777 // two branches instead of an explicit AND instruction with a
5778 // separate test. However, we only do this if this block doesn't
5779 // have a fall-through edge, because this requires an explicit
5780 // jmp when the condition is false.
5781 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5782 isX86LogicalCmp(Cmp) &&
5783 Op.getNode()->hasOneUse()) {
5784 X86::CondCode CCode =
5785 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5786 CCode = X86::GetOppositeBranchCondition(CCode);
5787 CC = DAG.getConstant(CCode, MVT::i8);
5788 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5789 // Look for an unconditional branch following this conditional branch.
5790 // We need this because we need to reverse the successors in order
5791 // to implement FCMP_OEQ.
5792 if (User.getOpcode() == ISD::BR) {
5793 SDValue FalseBB = User.getOperand(1);
5795 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5796 assert(NewBR == User);
5799 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5800 Chain, Dest, CC, Cmp);
5801 X86::CondCode CCode =
5802 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5803 CCode = X86::GetOppositeBranchCondition(CCode);
5804 CC = DAG.getConstant(CCode, MVT::i8);
5810 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5811 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5812 // It should be transformed during dag combiner except when the condition
5813 // is set by a arithmetics with overflow node.
5814 X86::CondCode CCode =
5815 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5816 CCode = X86::GetOppositeBranchCondition(CCode);
5817 CC = DAG.getConstant(CCode, MVT::i8);
5818 Cond = Cond.getOperand(0).getOperand(1);
5824 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5825 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5827 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5828 Chain, Dest, CC, Cond);
5832 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5833 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5834 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5835 // that the guard pages used by the OS virtual memory manager are allocated in
5836 // correct sequence.
5838 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5839 SelectionDAG &DAG) {
5840 assert(Subtarget->isTargetCygMing() &&
5841 "This should be used only on Cygwin/Mingw targets");
5842 DebugLoc dl = Op.getDebugLoc();
5845 SDValue Chain = Op.getOperand(0);
5846 SDValue Size = Op.getOperand(1);
5847 // FIXME: Ensure alignment here
5851 EVT IntPtr = getPointerTy();
5852 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5854 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5856 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5857 Flag = Chain.getValue(1);
5859 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5860 SDValue Ops[] = { Chain,
5861 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5862 DAG.getRegister(X86::EAX, IntPtr),
5863 DAG.getRegister(X86StackPtr, SPTy),
5865 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5866 Flag = Chain.getValue(1);
5868 Chain = DAG.getCALLSEQ_END(Chain,
5869 DAG.getIntPtrConstant(0, true),
5870 DAG.getIntPtrConstant(0, true),
5873 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5875 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5876 return DAG.getMergeValues(Ops1, 2, dl);
5880 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5882 SDValue Dst, SDValue Src,
5883 SDValue Size, unsigned Align,
5885 uint64_t DstSVOff) {
5886 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5888 // If not DWORD aligned or size is more than the threshold, call the library.
5889 // The libc version is likely to be faster for these cases. It can use the
5890 // address value and run time information about the CPU.
5891 if ((Align & 3) != 0 ||
5893 ConstantSize->getZExtValue() >
5894 getSubtarget()->getMaxInlineSizeThreshold()) {
5895 SDValue InFlag(0, 0);
5897 // Check to see if there is a specialized entry-point for memory zeroing.
5898 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5900 if (const char *bzeroEntry = V &&
5901 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5902 EVT IntPtr = getPointerTy();
5903 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
5904 TargetLowering::ArgListTy Args;
5905 TargetLowering::ArgListEntry Entry;
5907 Entry.Ty = IntPtrTy;
5908 Args.push_back(Entry);
5910 Args.push_back(Entry);
5911 std::pair<SDValue,SDValue> CallResult =
5912 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
5913 false, false, false, false,
5914 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
5915 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5916 return CallResult.second;
5919 // Otherwise have the target-independent code call memset.
5923 uint64_t SizeVal = ConstantSize->getZExtValue();
5924 SDValue InFlag(0, 0);
5927 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5928 unsigned BytesLeft = 0;
5929 bool TwoRepStos = false;
5932 uint64_t Val = ValC->getZExtValue() & 255;
5934 // If the value is a constant, then we can potentially use larger sets.
5935 switch (Align & 3) {
5936 case 2: // WORD aligned
5939 Val = (Val << 8) | Val;
5941 case 0: // DWORD aligned
5944 Val = (Val << 8) | Val;
5945 Val = (Val << 16) | Val;
5946 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5949 Val = (Val << 32) | Val;
5952 default: // Byte aligned
5955 Count = DAG.getIntPtrConstant(SizeVal);
5959 if (AVT.bitsGT(MVT::i8)) {
5960 unsigned UBytes = AVT.getSizeInBits() / 8;
5961 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5962 BytesLeft = SizeVal % UBytes;
5965 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5967 InFlag = Chain.getValue(1);
5970 Count = DAG.getIntPtrConstant(SizeVal);
5971 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5972 InFlag = Chain.getValue(1);
5975 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5978 InFlag = Chain.getValue(1);
5979 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5982 InFlag = Chain.getValue(1);
5984 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5985 SmallVector<SDValue, 8> Ops;
5986 Ops.push_back(Chain);
5987 Ops.push_back(DAG.getValueType(AVT));
5988 Ops.push_back(InFlag);
5989 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5992 InFlag = Chain.getValue(1);
5994 EVT CVT = Count.getValueType();
5995 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5996 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5997 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6000 InFlag = Chain.getValue(1);
6001 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6003 Ops.push_back(Chain);
6004 Ops.push_back(DAG.getValueType(MVT::i8));
6005 Ops.push_back(InFlag);
6006 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6007 } else if (BytesLeft) {
6008 // Handle the last 1 - 7 bytes.
6009 unsigned Offset = SizeVal - BytesLeft;
6010 EVT AddrVT = Dst.getValueType();
6011 EVT SizeVT = Size.getValueType();
6013 Chain = DAG.getMemset(Chain, dl,
6014 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6015 DAG.getConstant(Offset, AddrVT)),
6017 DAG.getConstant(BytesLeft, SizeVT),
6018 Align, DstSV, DstSVOff + Offset);
6021 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6026 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6027 SDValue Chain, SDValue Dst, SDValue Src,
6028 SDValue Size, unsigned Align,
6030 const Value *DstSV, uint64_t DstSVOff,
6031 const Value *SrcSV, uint64_t SrcSVOff) {
6032 // This requires the copy size to be a constant, preferrably
6033 // within a subtarget-specific limit.
6034 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6037 uint64_t SizeVal = ConstantSize->getZExtValue();
6038 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6041 /// If not DWORD aligned, call the library.
6042 if ((Align & 3) != 0)
6047 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6050 unsigned UBytes = AVT.getSizeInBits() / 8;
6051 unsigned CountVal = SizeVal / UBytes;
6052 SDValue Count = DAG.getIntPtrConstant(CountVal);
6053 unsigned BytesLeft = SizeVal % UBytes;
6055 SDValue InFlag(0, 0);
6056 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6059 InFlag = Chain.getValue(1);
6060 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6063 InFlag = Chain.getValue(1);
6064 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6067 InFlag = Chain.getValue(1);
6069 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6070 SmallVector<SDValue, 8> Ops;
6071 Ops.push_back(Chain);
6072 Ops.push_back(DAG.getValueType(AVT));
6073 Ops.push_back(InFlag);
6074 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6076 SmallVector<SDValue, 4> Results;
6077 Results.push_back(RepMovs);
6079 // Handle the last 1 - 7 bytes.
6080 unsigned Offset = SizeVal - BytesLeft;
6081 EVT DstVT = Dst.getValueType();
6082 EVT SrcVT = Src.getValueType();
6083 EVT SizeVT = Size.getValueType();
6084 Results.push_back(DAG.getMemcpy(Chain, dl,
6085 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6086 DAG.getConstant(Offset, DstVT)),
6087 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6088 DAG.getConstant(Offset, SrcVT)),
6089 DAG.getConstant(BytesLeft, SizeVT),
6090 Align, AlwaysInline,
6091 DstSV, DstSVOff + Offset,
6092 SrcSV, SrcSVOff + Offset));
6095 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6096 &Results[0], Results.size());
6099 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6100 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6101 DebugLoc dl = Op.getDebugLoc();
6103 if (!Subtarget->is64Bit()) {
6104 // vastart just stores the address of the VarArgsFrameIndex slot into the
6105 // memory location argument.
6106 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6107 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6111 // gp_offset (0 - 6 * 8)
6112 // fp_offset (48 - 48 + 8 * 16)
6113 // overflow_arg_area (point to parameters coming in memory).
6115 SmallVector<SDValue, 8> MemOps;
6116 SDValue FIN = Op.getOperand(1);
6118 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6119 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6121 MemOps.push_back(Store);
6124 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6125 FIN, DAG.getIntPtrConstant(4));
6126 Store = DAG.getStore(Op.getOperand(0), dl,
6127 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6129 MemOps.push_back(Store);
6131 // Store ptr to overflow_arg_area
6132 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6133 FIN, DAG.getIntPtrConstant(4));
6134 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6135 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6136 MemOps.push_back(Store);
6138 // Store ptr to reg_save_area.
6139 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6140 FIN, DAG.getIntPtrConstant(8));
6141 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6142 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6143 MemOps.push_back(Store);
6144 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6145 &MemOps[0], MemOps.size());
6148 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6149 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6150 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6151 SDValue Chain = Op.getOperand(0);
6152 SDValue SrcPtr = Op.getOperand(1);
6153 SDValue SrcSV = Op.getOperand(2);
6155 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6159 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6160 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6161 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6162 SDValue Chain = Op.getOperand(0);
6163 SDValue DstPtr = Op.getOperand(1);
6164 SDValue SrcPtr = Op.getOperand(2);
6165 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6166 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6167 DebugLoc dl = Op.getDebugLoc();
6169 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6170 DAG.getIntPtrConstant(24), 8, false,
6171 DstSV, 0, SrcSV, 0);
6175 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6176 DebugLoc dl = Op.getDebugLoc();
6177 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6179 default: return SDValue(); // Don't custom lower most intrinsics.
6180 // Comparison intrinsics.
6181 case Intrinsic::x86_sse_comieq_ss:
6182 case Intrinsic::x86_sse_comilt_ss:
6183 case Intrinsic::x86_sse_comile_ss:
6184 case Intrinsic::x86_sse_comigt_ss:
6185 case Intrinsic::x86_sse_comige_ss:
6186 case Intrinsic::x86_sse_comineq_ss:
6187 case Intrinsic::x86_sse_ucomieq_ss:
6188 case Intrinsic::x86_sse_ucomilt_ss:
6189 case Intrinsic::x86_sse_ucomile_ss:
6190 case Intrinsic::x86_sse_ucomigt_ss:
6191 case Intrinsic::x86_sse_ucomige_ss:
6192 case Intrinsic::x86_sse_ucomineq_ss:
6193 case Intrinsic::x86_sse2_comieq_sd:
6194 case Intrinsic::x86_sse2_comilt_sd:
6195 case Intrinsic::x86_sse2_comile_sd:
6196 case Intrinsic::x86_sse2_comigt_sd:
6197 case Intrinsic::x86_sse2_comige_sd:
6198 case Intrinsic::x86_sse2_comineq_sd:
6199 case Intrinsic::x86_sse2_ucomieq_sd:
6200 case Intrinsic::x86_sse2_ucomilt_sd:
6201 case Intrinsic::x86_sse2_ucomile_sd:
6202 case Intrinsic::x86_sse2_ucomigt_sd:
6203 case Intrinsic::x86_sse2_ucomige_sd:
6204 case Intrinsic::x86_sse2_ucomineq_sd: {
6206 ISD::CondCode CC = ISD::SETCC_INVALID;
6209 case Intrinsic::x86_sse_comieq_ss:
6210 case Intrinsic::x86_sse2_comieq_sd:
6214 case Intrinsic::x86_sse_comilt_ss:
6215 case Intrinsic::x86_sse2_comilt_sd:
6219 case Intrinsic::x86_sse_comile_ss:
6220 case Intrinsic::x86_sse2_comile_sd:
6224 case Intrinsic::x86_sse_comigt_ss:
6225 case Intrinsic::x86_sse2_comigt_sd:
6229 case Intrinsic::x86_sse_comige_ss:
6230 case Intrinsic::x86_sse2_comige_sd:
6234 case Intrinsic::x86_sse_comineq_ss:
6235 case Intrinsic::x86_sse2_comineq_sd:
6239 case Intrinsic::x86_sse_ucomieq_ss:
6240 case Intrinsic::x86_sse2_ucomieq_sd:
6241 Opc = X86ISD::UCOMI;
6244 case Intrinsic::x86_sse_ucomilt_ss:
6245 case Intrinsic::x86_sse2_ucomilt_sd:
6246 Opc = X86ISD::UCOMI;
6249 case Intrinsic::x86_sse_ucomile_ss:
6250 case Intrinsic::x86_sse2_ucomile_sd:
6251 Opc = X86ISD::UCOMI;
6254 case Intrinsic::x86_sse_ucomigt_ss:
6255 case Intrinsic::x86_sse2_ucomigt_sd:
6256 Opc = X86ISD::UCOMI;
6259 case Intrinsic::x86_sse_ucomige_ss:
6260 case Intrinsic::x86_sse2_ucomige_sd:
6261 Opc = X86ISD::UCOMI;
6264 case Intrinsic::x86_sse_ucomineq_ss:
6265 case Intrinsic::x86_sse2_ucomineq_sd:
6266 Opc = X86ISD::UCOMI;
6271 SDValue LHS = Op.getOperand(1);
6272 SDValue RHS = Op.getOperand(2);
6273 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6274 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6275 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6276 DAG.getConstant(X86CC, MVT::i8), Cond);
6277 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6279 // ptest intrinsics. The intrinsic these come from are designed to return
6280 // an integer value, not just an instruction so lower it to the ptest
6281 // pattern and a setcc for the result.
6282 case Intrinsic::x86_sse41_ptestz:
6283 case Intrinsic::x86_sse41_ptestc:
6284 case Intrinsic::x86_sse41_ptestnzc:{
6287 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6288 case Intrinsic::x86_sse41_ptestz:
6290 X86CC = X86::COND_E;
6292 case Intrinsic::x86_sse41_ptestc:
6294 X86CC = X86::COND_B;
6296 case Intrinsic::x86_sse41_ptestnzc:
6298 X86CC = X86::COND_A;
6302 SDValue LHS = Op.getOperand(1);
6303 SDValue RHS = Op.getOperand(2);
6304 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6305 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6306 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6307 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6310 // Fix vector shift instructions where the last operand is a non-immediate
6312 case Intrinsic::x86_sse2_pslli_w:
6313 case Intrinsic::x86_sse2_pslli_d:
6314 case Intrinsic::x86_sse2_pslli_q:
6315 case Intrinsic::x86_sse2_psrli_w:
6316 case Intrinsic::x86_sse2_psrli_d:
6317 case Intrinsic::x86_sse2_psrli_q:
6318 case Intrinsic::x86_sse2_psrai_w:
6319 case Intrinsic::x86_sse2_psrai_d:
6320 case Intrinsic::x86_mmx_pslli_w:
6321 case Intrinsic::x86_mmx_pslli_d:
6322 case Intrinsic::x86_mmx_pslli_q:
6323 case Intrinsic::x86_mmx_psrli_w:
6324 case Intrinsic::x86_mmx_psrli_d:
6325 case Intrinsic::x86_mmx_psrli_q:
6326 case Intrinsic::x86_mmx_psrai_w:
6327 case Intrinsic::x86_mmx_psrai_d: {
6328 SDValue ShAmt = Op.getOperand(2);
6329 if (isa<ConstantSDNode>(ShAmt))
6332 unsigned NewIntNo = 0;
6333 EVT ShAmtVT = MVT::v4i32;
6335 case Intrinsic::x86_sse2_pslli_w:
6336 NewIntNo = Intrinsic::x86_sse2_psll_w;
6338 case Intrinsic::x86_sse2_pslli_d:
6339 NewIntNo = Intrinsic::x86_sse2_psll_d;
6341 case Intrinsic::x86_sse2_pslli_q:
6342 NewIntNo = Intrinsic::x86_sse2_psll_q;
6344 case Intrinsic::x86_sse2_psrli_w:
6345 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6347 case Intrinsic::x86_sse2_psrli_d:
6348 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6350 case Intrinsic::x86_sse2_psrli_q:
6351 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6353 case Intrinsic::x86_sse2_psrai_w:
6354 NewIntNo = Intrinsic::x86_sse2_psra_w;
6356 case Intrinsic::x86_sse2_psrai_d:
6357 NewIntNo = Intrinsic::x86_sse2_psra_d;
6360 ShAmtVT = MVT::v2i32;
6362 case Intrinsic::x86_mmx_pslli_w:
6363 NewIntNo = Intrinsic::x86_mmx_psll_w;
6365 case Intrinsic::x86_mmx_pslli_d:
6366 NewIntNo = Intrinsic::x86_mmx_psll_d;
6368 case Intrinsic::x86_mmx_pslli_q:
6369 NewIntNo = Intrinsic::x86_mmx_psll_q;
6371 case Intrinsic::x86_mmx_psrli_w:
6372 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6374 case Intrinsic::x86_mmx_psrli_d:
6375 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6377 case Intrinsic::x86_mmx_psrli_q:
6378 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6380 case Intrinsic::x86_mmx_psrai_w:
6381 NewIntNo = Intrinsic::x86_mmx_psra_w;
6383 case Intrinsic::x86_mmx_psrai_d:
6384 NewIntNo = Intrinsic::x86_mmx_psra_d;
6386 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6392 // The vector shift intrinsics with scalars uses 32b shift amounts but
6393 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6397 ShOps[1] = DAG.getConstant(0, MVT::i32);
6398 if (ShAmtVT == MVT::v4i32) {
6399 ShOps[2] = DAG.getUNDEF(MVT::i32);
6400 ShOps[3] = DAG.getUNDEF(MVT::i32);
6401 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6403 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6406 EVT VT = Op.getValueType();
6407 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6408 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6409 DAG.getConstant(NewIntNo, MVT::i32),
6410 Op.getOperand(1), ShAmt);
6415 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6416 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6417 DebugLoc dl = Op.getDebugLoc();
6420 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6422 DAG.getConstant(TD->getPointerSize(),
6423 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6424 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6425 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6430 // Just load the return address.
6431 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6432 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6433 RetAddrFI, NULL, 0);
6436 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6437 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6438 MFI->setFrameAddressIsTaken(true);
6439 EVT VT = Op.getValueType();
6440 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6441 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6442 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6443 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6445 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6449 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6450 SelectionDAG &DAG) {
6451 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6454 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6456 MachineFunction &MF = DAG.getMachineFunction();
6457 SDValue Chain = Op.getOperand(0);
6458 SDValue Offset = Op.getOperand(1);
6459 SDValue Handler = Op.getOperand(2);
6460 DebugLoc dl = Op.getDebugLoc();
6462 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6464 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6466 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6467 DAG.getIntPtrConstant(-TD->getPointerSize()));
6468 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6469 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6470 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6471 MF.getRegInfo().addLiveOut(StoreAddrReg);
6473 return DAG.getNode(X86ISD::EH_RETURN, dl,
6475 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6478 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6479 SelectionDAG &DAG) {
6480 SDValue Root = Op.getOperand(0);
6481 SDValue Trmp = Op.getOperand(1); // trampoline
6482 SDValue FPtr = Op.getOperand(2); // nested function
6483 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6484 DebugLoc dl = Op.getDebugLoc();
6486 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6488 const X86InstrInfo *TII =
6489 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6491 if (Subtarget->is64Bit()) {
6492 SDValue OutChains[6];
6494 // Large code-model.
6496 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6497 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6499 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6500 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6502 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6504 // Load the pointer to the nested function into R11.
6505 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6506 SDValue Addr = Trmp;
6507 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6510 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6511 DAG.getConstant(2, MVT::i64));
6512 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6514 // Load the 'nest' parameter value into R10.
6515 // R10 is specified in X86CallingConv.td
6516 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6517 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6518 DAG.getConstant(10, MVT::i64));
6519 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6520 Addr, TrmpAddr, 10);
6522 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6523 DAG.getConstant(12, MVT::i64));
6524 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6526 // Jump to the nested function.
6527 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6528 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6529 DAG.getConstant(20, MVT::i64));
6530 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6531 Addr, TrmpAddr, 20);
6533 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6534 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6535 DAG.getConstant(22, MVT::i64));
6536 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6540 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6541 return DAG.getMergeValues(Ops, 2, dl);
6543 const Function *Func =
6544 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6545 CallingConv::ID CC = Func->getCallingConv();
6550 llvm_unreachable("Unsupported calling convention");
6551 case CallingConv::C:
6552 case CallingConv::X86_StdCall: {
6553 // Pass 'nest' parameter in ECX.
6554 // Must be kept in sync with X86CallingConv.td
6557 // Check that ECX wasn't needed by an 'inreg' parameter.
6558 const FunctionType *FTy = Func->getFunctionType();
6559 const AttrListPtr &Attrs = Func->getAttributes();
6561 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6562 unsigned InRegCount = 0;
6565 for (FunctionType::param_iterator I = FTy->param_begin(),
6566 E = FTy->param_end(); I != E; ++I, ++Idx)
6567 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6568 // FIXME: should only count parameters that are lowered to integers.
6569 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6571 if (InRegCount > 2) {
6572 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6577 case CallingConv::X86_FastCall:
6578 case CallingConv::Fast:
6579 // Pass 'nest' parameter in EAX.
6580 // Must be kept in sync with X86CallingConv.td
6585 SDValue OutChains[4];
6588 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6589 DAG.getConstant(10, MVT::i32));
6590 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6592 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6593 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6594 OutChains[0] = DAG.getStore(Root, dl,
6595 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6598 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6599 DAG.getConstant(1, MVT::i32));
6600 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6602 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6603 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6604 DAG.getConstant(5, MVT::i32));
6605 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6606 TrmpAddr, 5, false, 1);
6608 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6609 DAG.getConstant(6, MVT::i32));
6610 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6613 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6614 return DAG.getMergeValues(Ops, 2, dl);
6618 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6620 The rounding mode is in bits 11:10 of FPSR, and has the following
6627 FLT_ROUNDS, on the other hand, expects the following:
6634 To perform the conversion, we do:
6635 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6638 MachineFunction &MF = DAG.getMachineFunction();
6639 const TargetMachine &TM = MF.getTarget();
6640 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6641 unsigned StackAlignment = TFI.getStackAlignment();
6642 EVT VT = Op.getValueType();
6643 DebugLoc dl = Op.getDebugLoc();
6645 // Save FP Control Word to stack slot
6646 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6647 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6649 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6650 DAG.getEntryNode(), StackSlot);
6652 // Load FP Control Word from stack slot
6653 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6655 // Transform as necessary
6657 DAG.getNode(ISD::SRL, dl, MVT::i16,
6658 DAG.getNode(ISD::AND, dl, MVT::i16,
6659 CWD, DAG.getConstant(0x800, MVT::i16)),
6660 DAG.getConstant(11, MVT::i8));
6662 DAG.getNode(ISD::SRL, dl, MVT::i16,
6663 DAG.getNode(ISD::AND, dl, MVT::i16,
6664 CWD, DAG.getConstant(0x400, MVT::i16)),
6665 DAG.getConstant(9, MVT::i8));
6668 DAG.getNode(ISD::AND, dl, MVT::i16,
6669 DAG.getNode(ISD::ADD, dl, MVT::i16,
6670 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6671 DAG.getConstant(1, MVT::i16)),
6672 DAG.getConstant(3, MVT::i16));
6675 return DAG.getNode((VT.getSizeInBits() < 16 ?
6676 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6679 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6680 EVT VT = Op.getValueType();
6682 unsigned NumBits = VT.getSizeInBits();
6683 DebugLoc dl = Op.getDebugLoc();
6685 Op = Op.getOperand(0);
6686 if (VT == MVT::i8) {
6687 // Zero extend to i32 since there is not an i8 bsr.
6689 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6692 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6693 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6694 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6696 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6697 SmallVector<SDValue, 4> Ops;
6699 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6700 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6701 Ops.push_back(Op.getValue(1));
6702 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6704 // Finally xor with NumBits-1.
6705 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6708 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6712 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6713 EVT VT = Op.getValueType();
6715 unsigned NumBits = VT.getSizeInBits();
6716 DebugLoc dl = Op.getDebugLoc();
6718 Op = Op.getOperand(0);
6719 if (VT == MVT::i8) {
6721 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6724 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6725 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6726 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6728 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6729 SmallVector<SDValue, 4> Ops;
6731 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6732 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6733 Ops.push_back(Op.getValue(1));
6734 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6737 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6741 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6742 EVT VT = Op.getValueType();
6743 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6744 DebugLoc dl = Op.getDebugLoc();
6746 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6747 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6748 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6749 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6750 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6752 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6753 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6754 // return AloBlo + AloBhi + AhiBlo;
6756 SDValue A = Op.getOperand(0);
6757 SDValue B = Op.getOperand(1);
6759 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6760 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6761 A, DAG.getConstant(32, MVT::i32));
6762 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6763 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6764 B, DAG.getConstant(32, MVT::i32));
6765 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6766 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6768 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6769 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6771 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6772 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6774 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6775 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6776 AloBhi, DAG.getConstant(32, MVT::i32));
6777 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6778 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6779 AhiBlo, DAG.getConstant(32, MVT::i32));
6780 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6781 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6786 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6787 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6788 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6789 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6790 // has only one use.
6791 SDNode *N = Op.getNode();
6792 SDValue LHS = N->getOperand(0);
6793 SDValue RHS = N->getOperand(1);
6794 unsigned BaseOp = 0;
6796 DebugLoc dl = Op.getDebugLoc();
6798 switch (Op.getOpcode()) {
6799 default: llvm_unreachable("Unknown ovf instruction!");
6801 // A subtract of one will be selected as a INC. Note that INC doesn't
6802 // set CF, so we can't do this for UADDO.
6803 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6804 if (C->getAPIntValue() == 1) {
6805 BaseOp = X86ISD::INC;
6809 BaseOp = X86ISD::ADD;
6813 BaseOp = X86ISD::ADD;
6817 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6818 // set CF, so we can't do this for USUBO.
6819 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6820 if (C->getAPIntValue() == 1) {
6821 BaseOp = X86ISD::DEC;
6825 BaseOp = X86ISD::SUB;
6829 BaseOp = X86ISD::SUB;
6833 BaseOp = X86ISD::SMUL;
6837 BaseOp = X86ISD::UMUL;
6842 // Also sets EFLAGS.
6843 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6844 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6847 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6848 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6850 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6854 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6855 EVT T = Op.getValueType();
6856 DebugLoc dl = Op.getDebugLoc();
6859 switch(T.getSimpleVT().SimpleTy) {
6861 assert(false && "Invalid value type!");
6862 case MVT::i8: Reg = X86::AL; size = 1; break;
6863 case MVT::i16: Reg = X86::AX; size = 2; break;
6864 case MVT::i32: Reg = X86::EAX; size = 4; break;
6866 assert(Subtarget->is64Bit() && "Node not type legal!");
6867 Reg = X86::RAX; size = 8;
6870 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6871 Op.getOperand(2), SDValue());
6872 SDValue Ops[] = { cpIn.getValue(0),
6875 DAG.getTargetConstant(size, MVT::i8),
6877 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6878 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6880 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6884 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6885 SelectionDAG &DAG) {
6886 assert(Subtarget->is64Bit() && "Result not type legalized?");
6887 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6888 SDValue TheChain = Op.getOperand(0);
6889 DebugLoc dl = Op.getDebugLoc();
6890 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6891 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6892 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6894 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6895 DAG.getConstant(32, MVT::i8));
6897 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6900 return DAG.getMergeValues(Ops, 2, dl);
6903 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6904 SDNode *Node = Op.getNode();
6905 DebugLoc dl = Node->getDebugLoc();
6906 EVT T = Node->getValueType(0);
6907 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6908 DAG.getConstant(0, T), Node->getOperand(2));
6909 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6910 cast<AtomicSDNode>(Node)->getMemoryVT(),
6911 Node->getOperand(0),
6912 Node->getOperand(1), negOp,
6913 cast<AtomicSDNode>(Node)->getSrcValue(),
6914 cast<AtomicSDNode>(Node)->getAlignment());
6917 /// LowerOperation - Provide custom lowering hooks for some operations.
6919 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6920 switch (Op.getOpcode()) {
6921 default: llvm_unreachable("Should not custom lower this!");
6922 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6923 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6924 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6925 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6926 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6927 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6928 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6929 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6930 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6931 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6932 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6933 case ISD::SHL_PARTS:
6934 case ISD::SRA_PARTS:
6935 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6936 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6937 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6938 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6939 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
6940 case ISD::FABS: return LowerFABS(Op, DAG);
6941 case ISD::FNEG: return LowerFNEG(Op, DAG);
6942 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6943 case ISD::SETCC: return LowerSETCC(Op, DAG);
6944 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6945 case ISD::SELECT: return LowerSELECT(Op, DAG);
6946 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6947 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6948 case ISD::VASTART: return LowerVASTART(Op, DAG);
6949 case ISD::VAARG: return LowerVAARG(Op, DAG);
6950 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6951 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6952 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6953 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6954 case ISD::FRAME_TO_ARGS_OFFSET:
6955 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6956 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6957 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6958 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6959 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6960 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6961 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6962 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6968 case ISD::UMULO: return LowerXALUO(Op, DAG);
6969 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6973 void X86TargetLowering::
6974 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6975 SelectionDAG &DAG, unsigned NewOp) {
6976 EVT T = Node->getValueType(0);
6977 DebugLoc dl = Node->getDebugLoc();
6978 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6980 SDValue Chain = Node->getOperand(0);
6981 SDValue In1 = Node->getOperand(1);
6982 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6983 Node->getOperand(2), DAG.getIntPtrConstant(0));
6984 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6985 Node->getOperand(2), DAG.getIntPtrConstant(1));
6986 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6987 // have a MemOperand. Pass the info through as a normal operand.
6988 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6989 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6990 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6991 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6992 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6993 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6994 Results.push_back(Result.getValue(2));
6997 /// ReplaceNodeResults - Replace a node with an illegal result type
6998 /// with a new node built out of custom code.
6999 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7000 SmallVectorImpl<SDValue>&Results,
7001 SelectionDAG &DAG) {
7002 DebugLoc dl = N->getDebugLoc();
7003 switch (N->getOpcode()) {
7005 assert(false && "Do not know how to custom type legalize this operation!");
7007 case ISD::FP_TO_SINT: {
7008 std::pair<SDValue,SDValue> Vals =
7009 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7010 SDValue FIST = Vals.first, StackSlot = Vals.second;
7011 if (FIST.getNode() != 0) {
7012 EVT VT = N->getValueType(0);
7013 // Return a load from the stack slot.
7014 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7018 case ISD::READCYCLECOUNTER: {
7019 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7020 SDValue TheChain = N->getOperand(0);
7021 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7022 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7024 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7026 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7027 SDValue Ops[] = { eax, edx };
7028 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7029 Results.push_back(edx.getValue(1));
7032 case ISD::ATOMIC_CMP_SWAP: {
7033 EVT T = N->getValueType(0);
7034 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7035 SDValue cpInL, cpInH;
7036 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7037 DAG.getConstant(0, MVT::i32));
7038 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7039 DAG.getConstant(1, MVT::i32));
7040 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7041 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7043 SDValue swapInL, swapInH;
7044 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7045 DAG.getConstant(0, MVT::i32));
7046 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7047 DAG.getConstant(1, MVT::i32));
7048 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7050 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7051 swapInL.getValue(1));
7052 SDValue Ops[] = { swapInH.getValue(0),
7054 swapInH.getValue(1) };
7055 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7056 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7057 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7058 MVT::i32, Result.getValue(1));
7059 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7060 MVT::i32, cpOutL.getValue(2));
7061 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7062 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7063 Results.push_back(cpOutH.getValue(1));
7066 case ISD::ATOMIC_LOAD_ADD:
7067 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7069 case ISD::ATOMIC_LOAD_AND:
7070 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7072 case ISD::ATOMIC_LOAD_NAND:
7073 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7075 case ISD::ATOMIC_LOAD_OR:
7076 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7078 case ISD::ATOMIC_LOAD_SUB:
7079 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7081 case ISD::ATOMIC_LOAD_XOR:
7082 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7084 case ISD::ATOMIC_SWAP:
7085 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7090 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7092 default: return NULL;
7093 case X86ISD::BSF: return "X86ISD::BSF";
7094 case X86ISD::BSR: return "X86ISD::BSR";
7095 case X86ISD::SHLD: return "X86ISD::SHLD";
7096 case X86ISD::SHRD: return "X86ISD::SHRD";
7097 case X86ISD::FAND: return "X86ISD::FAND";
7098 case X86ISD::FOR: return "X86ISD::FOR";
7099 case X86ISD::FXOR: return "X86ISD::FXOR";
7100 case X86ISD::FSRL: return "X86ISD::FSRL";
7101 case X86ISD::FILD: return "X86ISD::FILD";
7102 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7103 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7104 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7105 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7106 case X86ISD::FLD: return "X86ISD::FLD";
7107 case X86ISD::FST: return "X86ISD::FST";
7108 case X86ISD::CALL: return "X86ISD::CALL";
7109 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7110 case X86ISD::BT: return "X86ISD::BT";
7111 case X86ISD::CMP: return "X86ISD::CMP";
7112 case X86ISD::COMI: return "X86ISD::COMI";
7113 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7114 case X86ISD::SETCC: return "X86ISD::SETCC";
7115 case X86ISD::CMOV: return "X86ISD::CMOV";
7116 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7117 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7118 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7119 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7120 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7121 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7122 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7123 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7124 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7125 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7126 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7127 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7128 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7129 case X86ISD::FMAX: return "X86ISD::FMAX";
7130 case X86ISD::FMIN: return "X86ISD::FMIN";
7131 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7132 case X86ISD::FRCP: return "X86ISD::FRCP";
7133 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7134 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7135 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7136 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7137 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7138 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7139 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7140 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7141 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7142 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7143 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7144 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7145 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7146 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7147 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7148 case X86ISD::VSHL: return "X86ISD::VSHL";
7149 case X86ISD::VSRL: return "X86ISD::VSRL";
7150 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7151 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7152 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7153 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7154 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7155 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7156 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7157 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7158 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7159 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7160 case X86ISD::ADD: return "X86ISD::ADD";
7161 case X86ISD::SUB: return "X86ISD::SUB";
7162 case X86ISD::SMUL: return "X86ISD::SMUL";
7163 case X86ISD::UMUL: return "X86ISD::UMUL";
7164 case X86ISD::INC: return "X86ISD::INC";
7165 case X86ISD::DEC: return "X86ISD::DEC";
7166 case X86ISD::OR: return "X86ISD::OR";
7167 case X86ISD::XOR: return "X86ISD::XOR";
7168 case X86ISD::AND: return "X86ISD::AND";
7169 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7170 case X86ISD::PTEST: return "X86ISD::PTEST";
7171 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7175 // isLegalAddressingMode - Return true if the addressing mode represented
7176 // by AM is legal for this target, for a load/store of the specified type.
7177 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7178 const Type *Ty) const {
7179 // X86 supports extremely general addressing modes.
7180 CodeModel::Model M = getTargetMachine().getCodeModel();
7182 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7183 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7188 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7190 // If a reference to this global requires an extra load, we can't fold it.
7191 if (isGlobalStubReference(GVFlags))
7194 // If BaseGV requires a register for the PIC base, we cannot also have a
7195 // BaseReg specified.
7196 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7199 // If lower 4G is not available, then we must use rip-relative addressing.
7200 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7210 // These scales always work.
7215 // These scales are formed with basereg+scalereg. Only accept if there is
7220 default: // Other stuff never works.
7228 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7229 if (!Ty1->isInteger() || !Ty2->isInteger())
7231 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7232 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7233 if (NumBits1 <= NumBits2)
7235 return Subtarget->is64Bit() || NumBits1 < 64;
7238 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7239 if (!VT1.isInteger() || !VT2.isInteger())
7241 unsigned NumBits1 = VT1.getSizeInBits();
7242 unsigned NumBits2 = VT2.getSizeInBits();
7243 if (NumBits1 <= NumBits2)
7245 return Subtarget->is64Bit() || NumBits1 < 64;
7248 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7249 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7250 return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
7251 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
7254 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7255 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7256 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7259 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7260 // i16 instructions are longer (0x66 prefix) and potentially slower.
7261 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7264 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7265 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7266 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7267 /// are assumed to be legal.
7269 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7271 // Only do shuffles on 128-bit vector types for now.
7272 if (VT.getSizeInBits() == 64)
7275 // FIXME: pshufb, blends, palignr, shifts.
7276 return (VT.getVectorNumElements() == 2 ||
7277 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7278 isMOVLMask(M, VT) ||
7279 isSHUFPMask(M, VT) ||
7280 isPSHUFDMask(M, VT) ||
7281 isPSHUFHWMask(M, VT) ||
7282 isPSHUFLWMask(M, VT) ||
7283 isUNPCKLMask(M, VT) ||
7284 isUNPCKHMask(M, VT) ||
7285 isUNPCKL_v_undef_Mask(M, VT) ||
7286 isUNPCKH_v_undef_Mask(M, VT));
7290 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7292 unsigned NumElts = VT.getVectorNumElements();
7293 // FIXME: This collection of masks seems suspect.
7296 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7297 return (isMOVLMask(Mask, VT) ||
7298 isCommutedMOVLMask(Mask, VT, true) ||
7299 isSHUFPMask(Mask, VT) ||
7300 isCommutedSHUFPMask(Mask, VT));
7305 //===----------------------------------------------------------------------===//
7306 // X86 Scheduler Hooks
7307 //===----------------------------------------------------------------------===//
7309 // private utility function
7311 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7312 MachineBasicBlock *MBB,
7320 TargetRegisterClass *RC,
7321 bool invSrc) const {
7322 // For the atomic bitwise operator, we generate
7325 // ld t1 = [bitinstr.addr]
7326 // op t2 = t1, [bitinstr.val]
7328 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7330 // fallthrough -->nextMBB
7331 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7332 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7333 MachineFunction::iterator MBBIter = MBB;
7336 /// First build the CFG
7337 MachineFunction *F = MBB->getParent();
7338 MachineBasicBlock *thisMBB = MBB;
7339 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7340 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7341 F->insert(MBBIter, newMBB);
7342 F->insert(MBBIter, nextMBB);
7344 // Move all successors to thisMBB to nextMBB
7345 nextMBB->transferSuccessors(thisMBB);
7347 // Update thisMBB to fall through to newMBB
7348 thisMBB->addSuccessor(newMBB);
7350 // newMBB jumps to itself and fall through to nextMBB
7351 newMBB->addSuccessor(nextMBB);
7352 newMBB->addSuccessor(newMBB);
7354 // Insert instructions into newMBB based on incoming instruction
7355 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7356 "unexpected number of operands");
7357 DebugLoc dl = bInstr->getDebugLoc();
7358 MachineOperand& destOper = bInstr->getOperand(0);
7359 MachineOperand* argOpers[2 + X86AddrNumOperands];
7360 int numArgs = bInstr->getNumOperands() - 1;
7361 for (int i=0; i < numArgs; ++i)
7362 argOpers[i] = &bInstr->getOperand(i+1);
7364 // x86 address has 4 operands: base, index, scale, and displacement
7365 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7366 int valArgIndx = lastAddrIndx + 1;
7368 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7369 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7370 for (int i=0; i <= lastAddrIndx; ++i)
7371 (*MIB).addOperand(*argOpers[i]);
7373 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7375 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7380 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7381 assert((argOpers[valArgIndx]->isReg() ||
7382 argOpers[valArgIndx]->isImm()) &&
7384 if (argOpers[valArgIndx]->isReg())
7385 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7387 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7389 (*MIB).addOperand(*argOpers[valArgIndx]);
7391 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7394 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7395 for (int i=0; i <= lastAddrIndx; ++i)
7396 (*MIB).addOperand(*argOpers[i]);
7398 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7399 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7401 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7405 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7407 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7411 // private utility function: 64 bit atomics on 32 bit host.
7413 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7414 MachineBasicBlock *MBB,
7419 bool invSrc) const {
7420 // For the atomic bitwise operator, we generate
7421 // thisMBB (instructions are in pairs, except cmpxchg8b)
7422 // ld t1,t2 = [bitinstr.addr]
7424 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7425 // op t5, t6 <- out1, out2, [bitinstr.val]
7426 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7427 // mov ECX, EBX <- t5, t6
7428 // mov EAX, EDX <- t1, t2
7429 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7430 // mov t3, t4 <- EAX, EDX
7432 // result in out1, out2
7433 // fallthrough -->nextMBB
7435 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7436 const unsigned LoadOpc = X86::MOV32rm;
7437 const unsigned copyOpc = X86::MOV32rr;
7438 const unsigned NotOpc = X86::NOT32r;
7439 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7440 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7441 MachineFunction::iterator MBBIter = MBB;
7444 /// First build the CFG
7445 MachineFunction *F = MBB->getParent();
7446 MachineBasicBlock *thisMBB = MBB;
7447 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7448 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7449 F->insert(MBBIter, newMBB);
7450 F->insert(MBBIter, nextMBB);
7452 // Move all successors to thisMBB to nextMBB
7453 nextMBB->transferSuccessors(thisMBB);
7455 // Update thisMBB to fall through to newMBB
7456 thisMBB->addSuccessor(newMBB);
7458 // newMBB jumps to itself and fall through to nextMBB
7459 newMBB->addSuccessor(nextMBB);
7460 newMBB->addSuccessor(newMBB);
7462 DebugLoc dl = bInstr->getDebugLoc();
7463 // Insert instructions into newMBB based on incoming instruction
7464 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7465 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7466 "unexpected number of operands");
7467 MachineOperand& dest1Oper = bInstr->getOperand(0);
7468 MachineOperand& dest2Oper = bInstr->getOperand(1);
7469 MachineOperand* argOpers[2 + X86AddrNumOperands];
7470 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7471 argOpers[i] = &bInstr->getOperand(i+2);
7473 // x86 address has 4 operands: base, index, scale, and displacement
7474 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7476 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7477 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7478 for (int i=0; i <= lastAddrIndx; ++i)
7479 (*MIB).addOperand(*argOpers[i]);
7480 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7481 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7482 // add 4 to displacement.
7483 for (int i=0; i <= lastAddrIndx-2; ++i)
7484 (*MIB).addOperand(*argOpers[i]);
7485 MachineOperand newOp3 = *(argOpers[3]);
7487 newOp3.setImm(newOp3.getImm()+4);
7489 newOp3.setOffset(newOp3.getOffset()+4);
7490 (*MIB).addOperand(newOp3);
7491 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7493 // t3/4 are defined later, at the bottom of the loop
7494 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7495 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7496 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7497 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7498 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7499 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7501 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7502 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7504 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7505 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7511 int valArgIndx = lastAddrIndx + 1;
7512 assert((argOpers[valArgIndx]->isReg() ||
7513 argOpers[valArgIndx]->isImm()) &&
7515 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7516 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7517 if (argOpers[valArgIndx]->isReg())
7518 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7520 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7521 if (regOpcL != X86::MOV32rr)
7523 (*MIB).addOperand(*argOpers[valArgIndx]);
7524 assert(argOpers[valArgIndx + 1]->isReg() ==
7525 argOpers[valArgIndx]->isReg());
7526 assert(argOpers[valArgIndx + 1]->isImm() ==
7527 argOpers[valArgIndx]->isImm());
7528 if (argOpers[valArgIndx + 1]->isReg())
7529 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7531 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7532 if (regOpcH != X86::MOV32rr)
7534 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7536 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7538 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7541 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7543 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7546 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7547 for (int i=0; i <= lastAddrIndx; ++i)
7548 (*MIB).addOperand(*argOpers[i]);
7550 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7551 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7553 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7554 MIB.addReg(X86::EAX);
7555 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7556 MIB.addReg(X86::EDX);
7559 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7561 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7565 // private utility function
7567 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7568 MachineBasicBlock *MBB,
7569 unsigned cmovOpc) const {
7570 // For the atomic min/max operator, we generate
7573 // ld t1 = [min/max.addr]
7574 // mov t2 = [min/max.val]
7576 // cmov[cond] t2 = t1
7578 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7580 // fallthrough -->nextMBB
7582 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7583 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7584 MachineFunction::iterator MBBIter = MBB;
7587 /// First build the CFG
7588 MachineFunction *F = MBB->getParent();
7589 MachineBasicBlock *thisMBB = MBB;
7590 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7591 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7592 F->insert(MBBIter, newMBB);
7593 F->insert(MBBIter, nextMBB);
7595 // Move all successors of thisMBB to nextMBB
7596 nextMBB->transferSuccessors(thisMBB);
7598 // Update thisMBB to fall through to newMBB
7599 thisMBB->addSuccessor(newMBB);
7601 // newMBB jumps to newMBB and fall through to nextMBB
7602 newMBB->addSuccessor(nextMBB);
7603 newMBB->addSuccessor(newMBB);
7605 DebugLoc dl = mInstr->getDebugLoc();
7606 // Insert instructions into newMBB based on incoming instruction
7607 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7608 "unexpected number of operands");
7609 MachineOperand& destOper = mInstr->getOperand(0);
7610 MachineOperand* argOpers[2 + X86AddrNumOperands];
7611 int numArgs = mInstr->getNumOperands() - 1;
7612 for (int i=0; i < numArgs; ++i)
7613 argOpers[i] = &mInstr->getOperand(i+1);
7615 // x86 address has 4 operands: base, index, scale, and displacement
7616 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7617 int valArgIndx = lastAddrIndx + 1;
7619 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7620 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7621 for (int i=0; i <= lastAddrIndx; ++i)
7622 (*MIB).addOperand(*argOpers[i]);
7624 // We only support register and immediate values
7625 assert((argOpers[valArgIndx]->isReg() ||
7626 argOpers[valArgIndx]->isImm()) &&
7629 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7630 if (argOpers[valArgIndx]->isReg())
7631 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7633 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7634 (*MIB).addOperand(*argOpers[valArgIndx]);
7636 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7639 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7644 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7645 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7649 // Cmp and exchange if none has modified the memory location
7650 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7651 for (int i=0; i <= lastAddrIndx; ++i)
7652 (*MIB).addOperand(*argOpers[i]);
7654 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7655 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7657 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7658 MIB.addReg(X86::EAX);
7661 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7663 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7667 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7668 // all of this code can be replaced with that in the .td file.
7670 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7671 unsigned numArgs, bool memArg) const {
7673 MachineFunction *F = BB->getParent();
7674 DebugLoc dl = MI->getDebugLoc();
7675 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7680 Opc = numArgs == 3 ?
7681 X86::PCMPISTRM128rm :
7682 X86::PCMPESTRM128rm;
7684 Opc = numArgs == 3 ?
7685 X86::PCMPISTRM128rr :
7686 X86::PCMPESTRM128rr;
7689 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
7691 for (unsigned i = 0; i < numArgs; ++i) {
7692 MachineOperand &Op = MI->getOperand(i+1);
7694 if (!(Op.isReg() && Op.isImplicit()))
7698 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
7701 F->DeleteMachineInstr(MI);
7707 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
7709 MachineBasicBlock *MBB) const {
7710 // Emit code to save XMM registers to the stack. The ABI says that the
7711 // number of registers to save is given in %al, so it's theoretically
7712 // possible to do an indirect jump trick to avoid saving all of them,
7713 // however this code takes a simpler approach and just executes all
7714 // of the stores if %al is non-zero. It's less code, and it's probably
7715 // easier on the hardware branch predictor, and stores aren't all that
7716 // expensive anyway.
7718 // Create the new basic blocks. One block contains all the XMM stores,
7719 // and one block is the final destination regardless of whether any
7720 // stores were performed.
7721 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7722 MachineFunction *F = MBB->getParent();
7723 MachineFunction::iterator MBBIter = MBB;
7725 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
7726 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
7727 F->insert(MBBIter, XMMSaveMBB);
7728 F->insert(MBBIter, EndMBB);
7731 // Move any original successors of MBB to the end block.
7732 EndMBB->transferSuccessors(MBB);
7733 // The original block will now fall through to the XMM save block.
7734 MBB->addSuccessor(XMMSaveMBB);
7735 // The XMMSaveMBB will fall through to the end block.
7736 XMMSaveMBB->addSuccessor(EndMBB);
7738 // Now add the instructions.
7739 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7740 DebugLoc DL = MI->getDebugLoc();
7742 unsigned CountReg = MI->getOperand(0).getReg();
7743 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
7744 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
7746 if (!Subtarget->isTargetWin64()) {
7747 // If %al is 0, branch around the XMM save block.
7748 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
7749 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
7750 MBB->addSuccessor(EndMBB);
7753 // In the XMM save block, save all the XMM argument registers.
7754 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
7755 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
7756 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
7757 .addFrameIndex(RegSaveFrameIndex)
7758 .addImm(/*Scale=*/1)
7759 .addReg(/*IndexReg=*/0)
7760 .addImm(/*Disp=*/Offset)
7761 .addReg(/*Segment=*/0)
7762 .addReg(MI->getOperand(i).getReg())
7763 .addMemOperand(MachineMemOperand(
7764 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
7765 MachineMemOperand::MOStore, Offset,
7766 /*Size=*/16, /*Align=*/16));
7769 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7775 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
7776 MachineBasicBlock *BB) const {
7777 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7778 DebugLoc DL = MI->getDebugLoc();
7780 // To "insert" a SELECT_CC instruction, we actually have to insert the
7781 // diamond control-flow pattern. The incoming instruction knows the
7782 // destination vreg to set, the condition code register to branch on, the
7783 // true/false values to select between, and a branch opcode to use.
7784 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7785 MachineFunction::iterator It = BB;
7791 // cmpTY ccX, r1, r2
7793 // fallthrough --> copy0MBB
7794 MachineBasicBlock *thisMBB = BB;
7795 MachineFunction *F = BB->getParent();
7796 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7797 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7799 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7800 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
7801 F->insert(It, copy0MBB);
7802 F->insert(It, sinkMBB);
7803 // Update machine-CFG edges by transferring all successors of the current
7804 // block to the new block which will contain the Phi node for the select.
7805 sinkMBB->transferSuccessors(BB);
7807 // Add the true and fallthrough blocks as its successors.
7808 BB->addSuccessor(copy0MBB);
7809 BB->addSuccessor(sinkMBB);
7812 // %FalseValue = ...
7813 // # fallthrough to sinkMBB
7816 // Update machine-CFG edges
7817 BB->addSuccessor(sinkMBB);
7820 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7823 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
7824 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7825 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7827 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7833 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7834 MachineBasicBlock *BB) const {
7835 switch (MI->getOpcode()) {
7836 default: assert(false && "Unexpected instr type to insert");
7838 case X86::CMOV_V1I64:
7839 case X86::CMOV_FR32:
7840 case X86::CMOV_FR64:
7841 case X86::CMOV_V4F32:
7842 case X86::CMOV_V2F64:
7843 case X86::CMOV_V2I64:
7844 return EmitLoweredSelect(MI, BB);
7846 case X86::FP32_TO_INT16_IN_MEM:
7847 case X86::FP32_TO_INT32_IN_MEM:
7848 case X86::FP32_TO_INT64_IN_MEM:
7849 case X86::FP64_TO_INT16_IN_MEM:
7850 case X86::FP64_TO_INT32_IN_MEM:
7851 case X86::FP64_TO_INT64_IN_MEM:
7852 case X86::FP80_TO_INT16_IN_MEM:
7853 case X86::FP80_TO_INT32_IN_MEM:
7854 case X86::FP80_TO_INT64_IN_MEM: {
7855 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7856 DebugLoc DL = MI->getDebugLoc();
7858 // Change the floating point control register to use "round towards zero"
7859 // mode when truncating to an integer value.
7860 MachineFunction *F = BB->getParent();
7861 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7862 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7864 // Load the old value of the high byte of the control word...
7866 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7867 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
7870 // Set the high part to be round to zero...
7871 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
7874 // Reload the modified control word now...
7875 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
7877 // Restore the memory image of control word to original value
7878 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
7881 // Get the X86 opcode to use.
7883 switch (MI->getOpcode()) {
7884 default: llvm_unreachable("illegal opcode!");
7885 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7886 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7887 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7888 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7889 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7890 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7891 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7892 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7893 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7897 MachineOperand &Op = MI->getOperand(0);
7899 AM.BaseType = X86AddressMode::RegBase;
7900 AM.Base.Reg = Op.getReg();
7902 AM.BaseType = X86AddressMode::FrameIndexBase;
7903 AM.Base.FrameIndex = Op.getIndex();
7905 Op = MI->getOperand(1);
7907 AM.Scale = Op.getImm();
7908 Op = MI->getOperand(2);
7910 AM.IndexReg = Op.getImm();
7911 Op = MI->getOperand(3);
7912 if (Op.isGlobal()) {
7913 AM.GV = Op.getGlobal();
7915 AM.Disp = Op.getImm();
7917 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
7918 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
7920 // Reload the original control word now.
7921 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
7923 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7926 // String/text processing lowering.
7927 case X86::PCMPISTRM128REG:
7928 return EmitPCMP(MI, BB, 3, false /* in-mem */);
7929 case X86::PCMPISTRM128MEM:
7930 return EmitPCMP(MI, BB, 3, true /* in-mem */);
7931 case X86::PCMPESTRM128REG:
7932 return EmitPCMP(MI, BB, 5, false /* in mem */);
7933 case X86::PCMPESTRM128MEM:
7934 return EmitPCMP(MI, BB, 5, true /* in mem */);
7937 case X86::ATOMAND32:
7938 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7939 X86::AND32ri, X86::MOV32rm,
7940 X86::LCMPXCHG32, X86::MOV32rr,
7941 X86::NOT32r, X86::EAX,
7942 X86::GR32RegisterClass);
7944 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7945 X86::OR32ri, X86::MOV32rm,
7946 X86::LCMPXCHG32, X86::MOV32rr,
7947 X86::NOT32r, X86::EAX,
7948 X86::GR32RegisterClass);
7949 case X86::ATOMXOR32:
7950 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7951 X86::XOR32ri, X86::MOV32rm,
7952 X86::LCMPXCHG32, X86::MOV32rr,
7953 X86::NOT32r, X86::EAX,
7954 X86::GR32RegisterClass);
7955 case X86::ATOMNAND32:
7956 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7957 X86::AND32ri, X86::MOV32rm,
7958 X86::LCMPXCHG32, X86::MOV32rr,
7959 X86::NOT32r, X86::EAX,
7960 X86::GR32RegisterClass, true);
7961 case X86::ATOMMIN32:
7962 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7963 case X86::ATOMMAX32:
7964 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7965 case X86::ATOMUMIN32:
7966 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7967 case X86::ATOMUMAX32:
7968 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7970 case X86::ATOMAND16:
7971 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7972 X86::AND16ri, X86::MOV16rm,
7973 X86::LCMPXCHG16, X86::MOV16rr,
7974 X86::NOT16r, X86::AX,
7975 X86::GR16RegisterClass);
7977 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7978 X86::OR16ri, X86::MOV16rm,
7979 X86::LCMPXCHG16, X86::MOV16rr,
7980 X86::NOT16r, X86::AX,
7981 X86::GR16RegisterClass);
7982 case X86::ATOMXOR16:
7983 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7984 X86::XOR16ri, X86::MOV16rm,
7985 X86::LCMPXCHG16, X86::MOV16rr,
7986 X86::NOT16r, X86::AX,
7987 X86::GR16RegisterClass);
7988 case X86::ATOMNAND16:
7989 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7990 X86::AND16ri, X86::MOV16rm,
7991 X86::LCMPXCHG16, X86::MOV16rr,
7992 X86::NOT16r, X86::AX,
7993 X86::GR16RegisterClass, true);
7994 case X86::ATOMMIN16:
7995 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7996 case X86::ATOMMAX16:
7997 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7998 case X86::ATOMUMIN16:
7999 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8000 case X86::ATOMUMAX16:
8001 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8004 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8005 X86::AND8ri, X86::MOV8rm,
8006 X86::LCMPXCHG8, X86::MOV8rr,
8007 X86::NOT8r, X86::AL,
8008 X86::GR8RegisterClass);
8010 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8011 X86::OR8ri, X86::MOV8rm,
8012 X86::LCMPXCHG8, X86::MOV8rr,
8013 X86::NOT8r, X86::AL,
8014 X86::GR8RegisterClass);
8016 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8017 X86::XOR8ri, X86::MOV8rm,
8018 X86::LCMPXCHG8, X86::MOV8rr,
8019 X86::NOT8r, X86::AL,
8020 X86::GR8RegisterClass);
8021 case X86::ATOMNAND8:
8022 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8023 X86::AND8ri, X86::MOV8rm,
8024 X86::LCMPXCHG8, X86::MOV8rr,
8025 X86::NOT8r, X86::AL,
8026 X86::GR8RegisterClass, true);
8027 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8028 // This group is for 64-bit host.
8029 case X86::ATOMAND64:
8030 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8031 X86::AND64ri32, X86::MOV64rm,
8032 X86::LCMPXCHG64, X86::MOV64rr,
8033 X86::NOT64r, X86::RAX,
8034 X86::GR64RegisterClass);
8036 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8037 X86::OR64ri32, X86::MOV64rm,
8038 X86::LCMPXCHG64, X86::MOV64rr,
8039 X86::NOT64r, X86::RAX,
8040 X86::GR64RegisterClass);
8041 case X86::ATOMXOR64:
8042 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8043 X86::XOR64ri32, X86::MOV64rm,
8044 X86::LCMPXCHG64, X86::MOV64rr,
8045 X86::NOT64r, X86::RAX,
8046 X86::GR64RegisterClass);
8047 case X86::ATOMNAND64:
8048 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8049 X86::AND64ri32, X86::MOV64rm,
8050 X86::LCMPXCHG64, X86::MOV64rr,
8051 X86::NOT64r, X86::RAX,
8052 X86::GR64RegisterClass, true);
8053 case X86::ATOMMIN64:
8054 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8055 case X86::ATOMMAX64:
8056 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8057 case X86::ATOMUMIN64:
8058 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8059 case X86::ATOMUMAX64:
8060 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8062 // This group does 64-bit operations on a 32-bit host.
8063 case X86::ATOMAND6432:
8064 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8065 X86::AND32rr, X86::AND32rr,
8066 X86::AND32ri, X86::AND32ri,
8068 case X86::ATOMOR6432:
8069 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8070 X86::OR32rr, X86::OR32rr,
8071 X86::OR32ri, X86::OR32ri,
8073 case X86::ATOMXOR6432:
8074 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8075 X86::XOR32rr, X86::XOR32rr,
8076 X86::XOR32ri, X86::XOR32ri,
8078 case X86::ATOMNAND6432:
8079 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8080 X86::AND32rr, X86::AND32rr,
8081 X86::AND32ri, X86::AND32ri,
8083 case X86::ATOMADD6432:
8084 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8085 X86::ADD32rr, X86::ADC32rr,
8086 X86::ADD32ri, X86::ADC32ri,
8088 case X86::ATOMSUB6432:
8089 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8090 X86::SUB32rr, X86::SBB32rr,
8091 X86::SUB32ri, X86::SBB32ri,
8093 case X86::ATOMSWAP6432:
8094 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8095 X86::MOV32rr, X86::MOV32rr,
8096 X86::MOV32ri, X86::MOV32ri,
8098 case X86::VASTART_SAVE_XMM_REGS:
8099 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8103 //===----------------------------------------------------------------------===//
8104 // X86 Optimization Hooks
8105 //===----------------------------------------------------------------------===//
8107 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8111 const SelectionDAG &DAG,
8112 unsigned Depth) const {
8113 unsigned Opc = Op.getOpcode();
8114 assert((Opc >= ISD::BUILTIN_OP_END ||
8115 Opc == ISD::INTRINSIC_WO_CHAIN ||
8116 Opc == ISD::INTRINSIC_W_CHAIN ||
8117 Opc == ISD::INTRINSIC_VOID) &&
8118 "Should use MaskedValueIsZero if you don't know whether Op"
8119 " is a target node!");
8121 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8133 // These nodes' second result is a boolean.
8134 if (Op.getResNo() == 0)
8138 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8139 Mask.getBitWidth() - 1);
8144 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8145 /// node is a GlobalAddress + offset.
8146 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8147 GlobalValue* &GA, int64_t &Offset) const{
8148 if (N->getOpcode() == X86ISD::Wrapper) {
8149 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8150 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8151 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8155 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8158 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
8159 const TargetLowering &TLI) {
8162 if (TLI.isGAPlusOffset(Base, GV, Offset))
8163 return (GV->getAlignment() >= N && (Offset % N) == 0);
8164 // DAG combine handles the stack object case.
8168 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8169 EVT EVT, LoadSDNode *&LDBase,
8170 unsigned &LastLoadedElt,
8171 SelectionDAG &DAG, MachineFrameInfo *MFI,
8172 const TargetLowering &TLI) {
8174 LastLoadedElt = -1U;
8175 for (unsigned i = 0; i < NumElems; ++i) {
8176 if (N->getMaskElt(i) < 0) {
8182 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8183 if (!Elt.getNode() ||
8184 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8187 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8189 LDBase = cast<LoadSDNode>(Elt.getNode());
8193 if (Elt.getOpcode() == ISD::UNDEF)
8196 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8197 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
8204 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8205 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8206 /// if the load addresses are consecutive, non-overlapping, and in the right
8207 /// order. In the case of v2i64, it will see if it can rewrite the
8208 /// shuffle to be an appropriate build vector so it can take advantage of
8209 // performBuildVectorCombine.
8210 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8211 const TargetLowering &TLI) {
8212 DebugLoc dl = N->getDebugLoc();
8213 EVT VT = N->getValueType(0);
8214 EVT EVT = VT.getVectorElementType();
8215 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8216 unsigned NumElems = VT.getVectorNumElements();
8218 if (VT.getSizeInBits() != 128)
8221 // Try to combine a vector_shuffle into a 128-bit load.
8222 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8223 LoadSDNode *LD = NULL;
8224 unsigned LastLoadedElt;
8225 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
8229 if (LastLoadedElt == NumElems - 1) {
8230 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
8231 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8232 LD->getSrcValue(), LD->getSrcValueOffset(),
8234 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8235 LD->getSrcValue(), LD->getSrcValueOffset(),
8236 LD->isVolatile(), LD->getAlignment());
8237 } else if (NumElems == 4 && LastLoadedElt == 1) {
8238 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8239 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8240 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8241 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8246 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8247 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8248 const X86Subtarget *Subtarget) {
8249 DebugLoc DL = N->getDebugLoc();
8250 SDValue Cond = N->getOperand(0);
8251 // Get the LHS/RHS of the select.
8252 SDValue LHS = N->getOperand(1);
8253 SDValue RHS = N->getOperand(2);
8255 // If we have SSE[12] support, try to form min/max nodes.
8256 if (Subtarget->hasSSE2() &&
8257 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8258 Cond.getOpcode() == ISD::SETCC) {
8259 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8261 unsigned Opcode = 0;
8262 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8265 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
8268 if (!UnsafeFPMath) break;
8270 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
8272 Opcode = X86ISD::FMIN;
8275 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8278 if (!UnsafeFPMath) break;
8280 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8282 Opcode = X86ISD::FMAX;
8285 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8289 // This can use a min only if the LHS isn't NaN.
8290 if (DAG.isKnownNeverNaN(LHS))
8291 Opcode = X86ISD::FMIN;
8292 else if (DAG.isKnownNeverNaN(RHS)) {
8293 Opcode = X86ISD::FMIN;
8294 // Put the potential NaN in the RHS so that SSE will preserve it.
8295 std::swap(LHS, RHS);
8299 case ISD::SETUGT: // (X > Y) ? Y : X -> min
8301 if (!UnsafeFPMath) break;
8303 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8305 Opcode = X86ISD::FMIN;
8309 // This can use a max only if the LHS isn't NaN.
8310 if (DAG.isKnownNeverNaN(LHS))
8311 Opcode = X86ISD::FMAX;
8312 else if (DAG.isKnownNeverNaN(RHS)) {
8313 Opcode = X86ISD::FMAX;
8314 // Put the potential NaN in the RHS so that SSE will preserve it.
8315 std::swap(LHS, RHS);
8319 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8321 if (!UnsafeFPMath) break;
8323 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8325 Opcode = X86ISD::FMAX;
8331 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8334 // If this is a select between two integer constants, try to do some
8336 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8337 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8338 // Don't do this for crazy integer types.
8339 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8340 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8341 // so that TrueC (the true value) is larger than FalseC.
8342 bool NeedsCondInvert = false;
8344 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8345 // Efficiently invertible.
8346 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8347 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8348 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8349 NeedsCondInvert = true;
8350 std::swap(TrueC, FalseC);
8353 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8354 if (FalseC->getAPIntValue() == 0 &&
8355 TrueC->getAPIntValue().isPowerOf2()) {
8356 if (NeedsCondInvert) // Invert the condition if needed.
8357 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8358 DAG.getConstant(1, Cond.getValueType()));
8360 // Zero extend the condition if needed.
8361 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8363 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8364 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8365 DAG.getConstant(ShAmt, MVT::i8));
8368 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8369 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8370 if (NeedsCondInvert) // Invert the condition if needed.
8371 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8372 DAG.getConstant(1, Cond.getValueType()));
8374 // Zero extend the condition if needed.
8375 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8376 FalseC->getValueType(0), Cond);
8377 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8378 SDValue(FalseC, 0));
8381 // Optimize cases that will turn into an LEA instruction. This requires
8382 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8383 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8384 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8385 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8387 bool isFastMultiplier = false;
8389 switch ((unsigned char)Diff) {
8391 case 1: // result = add base, cond
8392 case 2: // result = lea base( , cond*2)
8393 case 3: // result = lea base(cond, cond*2)
8394 case 4: // result = lea base( , cond*4)
8395 case 5: // result = lea base(cond, cond*4)
8396 case 8: // result = lea base( , cond*8)
8397 case 9: // result = lea base(cond, cond*8)
8398 isFastMultiplier = true;
8403 if (isFastMultiplier) {
8404 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8405 if (NeedsCondInvert) // Invert the condition if needed.
8406 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8407 DAG.getConstant(1, Cond.getValueType()));
8409 // Zero extend the condition if needed.
8410 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8412 // Scale the condition by the difference.
8414 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8415 DAG.getConstant(Diff, Cond.getValueType()));
8417 // Add the base if non-zero.
8418 if (FalseC->getAPIntValue() != 0)
8419 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8420 SDValue(FalseC, 0));
8430 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8431 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8432 TargetLowering::DAGCombinerInfo &DCI) {
8433 DebugLoc DL = N->getDebugLoc();
8435 // If the flag operand isn't dead, don't touch this CMOV.
8436 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8439 // If this is a select between two integer constants, try to do some
8440 // optimizations. Note that the operands are ordered the opposite of SELECT
8442 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8443 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8444 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8445 // larger than FalseC (the false value).
8446 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8448 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8449 CC = X86::GetOppositeBranchCondition(CC);
8450 std::swap(TrueC, FalseC);
8453 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8454 // This is efficient for any integer data type (including i8/i16) and
8456 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8457 SDValue Cond = N->getOperand(3);
8458 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8459 DAG.getConstant(CC, MVT::i8), Cond);
8461 // Zero extend the condition if needed.
8462 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8464 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8465 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8466 DAG.getConstant(ShAmt, MVT::i8));
8467 if (N->getNumValues() == 2) // Dead flag value?
8468 return DCI.CombineTo(N, Cond, SDValue());
8472 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8473 // for any integer data type, including i8/i16.
8474 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8475 SDValue Cond = N->getOperand(3);
8476 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8477 DAG.getConstant(CC, MVT::i8), Cond);
8479 // Zero extend the condition if needed.
8480 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8481 FalseC->getValueType(0), Cond);
8482 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8483 SDValue(FalseC, 0));
8485 if (N->getNumValues() == 2) // Dead flag value?
8486 return DCI.CombineTo(N, Cond, SDValue());
8490 // Optimize cases that will turn into an LEA instruction. This requires
8491 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8492 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8493 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8494 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8496 bool isFastMultiplier = false;
8498 switch ((unsigned char)Diff) {
8500 case 1: // result = add base, cond
8501 case 2: // result = lea base( , cond*2)
8502 case 3: // result = lea base(cond, cond*2)
8503 case 4: // result = lea base( , cond*4)
8504 case 5: // result = lea base(cond, cond*4)
8505 case 8: // result = lea base( , cond*8)
8506 case 9: // result = lea base(cond, cond*8)
8507 isFastMultiplier = true;
8512 if (isFastMultiplier) {
8513 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8514 SDValue Cond = N->getOperand(3);
8515 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8516 DAG.getConstant(CC, MVT::i8), Cond);
8517 // Zero extend the condition if needed.
8518 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8520 // Scale the condition by the difference.
8522 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8523 DAG.getConstant(Diff, Cond.getValueType()));
8525 // Add the base if non-zero.
8526 if (FalseC->getAPIntValue() != 0)
8527 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8528 SDValue(FalseC, 0));
8529 if (N->getNumValues() == 2) // Dead flag value?
8530 return DCI.CombineTo(N, Cond, SDValue());
8540 /// PerformMulCombine - Optimize a single multiply with constant into two
8541 /// in order to implement it with two cheaper instructions, e.g.
8542 /// LEA + SHL, LEA + LEA.
8543 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8544 TargetLowering::DAGCombinerInfo &DCI) {
8545 if (DAG.getMachineFunction().
8546 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8549 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8552 EVT VT = N->getValueType(0);
8556 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8559 uint64_t MulAmt = C->getZExtValue();
8560 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8563 uint64_t MulAmt1 = 0;
8564 uint64_t MulAmt2 = 0;
8565 if ((MulAmt % 9) == 0) {
8567 MulAmt2 = MulAmt / 9;
8568 } else if ((MulAmt % 5) == 0) {
8570 MulAmt2 = MulAmt / 5;
8571 } else if ((MulAmt % 3) == 0) {
8573 MulAmt2 = MulAmt / 3;
8576 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8577 DebugLoc DL = N->getDebugLoc();
8579 if (isPowerOf2_64(MulAmt2) &&
8580 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8581 // If second multiplifer is pow2, issue it first. We want the multiply by
8582 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8584 std::swap(MulAmt1, MulAmt2);
8587 if (isPowerOf2_64(MulAmt1))
8588 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8589 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8591 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8592 DAG.getConstant(MulAmt1, VT));
8594 if (isPowerOf2_64(MulAmt2))
8595 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8596 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8598 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8599 DAG.getConstant(MulAmt2, VT));
8601 // Do not add new nodes to DAG combiner worklist.
8602 DCI.CombineTo(N, NewMul, false);
8608 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8610 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8611 const X86Subtarget *Subtarget) {
8612 // On X86 with SSE2 support, we can transform this to a vector shift if
8613 // all elements are shifted by the same amount. We can't do this in legalize
8614 // because the a constant vector is typically transformed to a constant pool
8615 // so we have no knowledge of the shift amount.
8616 if (!Subtarget->hasSSE2())
8619 EVT VT = N->getValueType(0);
8620 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8623 SDValue ShAmtOp = N->getOperand(1);
8624 EVT EltVT = VT.getVectorElementType();
8625 DebugLoc DL = N->getDebugLoc();
8626 SDValue BaseShAmt = SDValue();
8627 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8628 unsigned NumElts = VT.getVectorNumElements();
8630 for (; i != NumElts; ++i) {
8631 SDValue Arg = ShAmtOp.getOperand(i);
8632 if (Arg.getOpcode() == ISD::UNDEF) continue;
8636 for (; i != NumElts; ++i) {
8637 SDValue Arg = ShAmtOp.getOperand(i);
8638 if (Arg.getOpcode() == ISD::UNDEF) continue;
8639 if (Arg != BaseShAmt) {
8643 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8644 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8645 SDValue InVec = ShAmtOp.getOperand(0);
8646 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8647 unsigned NumElts = InVec.getValueType().getVectorNumElements();
8649 for (; i != NumElts; ++i) {
8650 SDValue Arg = InVec.getOperand(i);
8651 if (Arg.getOpcode() == ISD::UNDEF) continue;
8655 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
8656 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
8657 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
8658 if (C->getZExtValue() == SplatIdx)
8659 BaseShAmt = InVec.getOperand(1);
8662 if (BaseShAmt.getNode() == 0)
8663 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8664 DAG.getIntPtrConstant(0));
8668 // The shift amount is an i32.
8669 if (EltVT.bitsGT(MVT::i32))
8670 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8671 else if (EltVT.bitsLT(MVT::i32))
8672 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
8674 // The shift amount is identical so we can do a vector shift.
8675 SDValue ValOp = N->getOperand(0);
8676 switch (N->getOpcode()) {
8678 llvm_unreachable("Unknown shift opcode!");
8681 if (VT == MVT::v2i64)
8682 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8683 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8685 if (VT == MVT::v4i32)
8686 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8687 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8689 if (VT == MVT::v8i16)
8690 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8691 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8695 if (VT == MVT::v4i32)
8696 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8697 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8699 if (VT == MVT::v8i16)
8700 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8701 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8705 if (VT == MVT::v2i64)
8706 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8707 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8709 if (VT == MVT::v4i32)
8710 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8711 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8713 if (VT == MVT::v8i16)
8714 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8715 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8722 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8723 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8724 const X86Subtarget *Subtarget) {
8725 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8726 // the FP state in cases where an emms may be missing.
8727 // A preferable solution to the general problem is to figure out the right
8728 // places to insert EMMS. This qualifies as a quick hack.
8730 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8731 StoreSDNode *St = cast<StoreSDNode>(N);
8732 EVT VT = St->getValue().getValueType();
8733 if (VT.getSizeInBits() != 64)
8736 const Function *F = DAG.getMachineFunction().getFunction();
8737 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8738 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8739 && Subtarget->hasSSE2();
8740 if ((VT.isVector() ||
8741 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8742 isa<LoadSDNode>(St->getValue()) &&
8743 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8744 St->getChain().hasOneUse() && !St->isVolatile()) {
8745 SDNode* LdVal = St->getValue().getNode();
8747 int TokenFactorIndex = -1;
8748 SmallVector<SDValue, 8> Ops;
8749 SDNode* ChainVal = St->getChain().getNode();
8750 // Must be a store of a load. We currently handle two cases: the load
8751 // is a direct child, and it's under an intervening TokenFactor. It is
8752 // possible to dig deeper under nested TokenFactors.
8753 if (ChainVal == LdVal)
8754 Ld = cast<LoadSDNode>(St->getChain());
8755 else if (St->getValue().hasOneUse() &&
8756 ChainVal->getOpcode() == ISD::TokenFactor) {
8757 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8758 if (ChainVal->getOperand(i).getNode() == LdVal) {
8759 TokenFactorIndex = i;
8760 Ld = cast<LoadSDNode>(St->getValue());
8762 Ops.push_back(ChainVal->getOperand(i));
8766 if (!Ld || !ISD::isNormalLoad(Ld))
8769 // If this is not the MMX case, i.e. we are just turning i64 load/store
8770 // into f64 load/store, avoid the transformation if there are multiple
8771 // uses of the loaded value.
8772 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8775 DebugLoc LdDL = Ld->getDebugLoc();
8776 DebugLoc StDL = N->getDebugLoc();
8777 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8778 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8780 if (Subtarget->is64Bit() || F64IsLegal) {
8781 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8782 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8783 Ld->getBasePtr(), Ld->getSrcValue(),
8784 Ld->getSrcValueOffset(), Ld->isVolatile(),
8785 Ld->getAlignment());
8786 SDValue NewChain = NewLd.getValue(1);
8787 if (TokenFactorIndex != -1) {
8788 Ops.push_back(NewChain);
8789 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8792 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8793 St->getSrcValue(), St->getSrcValueOffset(),
8794 St->isVolatile(), St->getAlignment());
8797 // Otherwise, lower to two pairs of 32-bit loads / stores.
8798 SDValue LoAddr = Ld->getBasePtr();
8799 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8800 DAG.getConstant(4, MVT::i32));
8802 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8803 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8804 Ld->isVolatile(), Ld->getAlignment());
8805 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8806 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8808 MinAlign(Ld->getAlignment(), 4));
8810 SDValue NewChain = LoLd.getValue(1);
8811 if (TokenFactorIndex != -1) {
8812 Ops.push_back(LoLd);
8813 Ops.push_back(HiLd);
8814 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8818 LoAddr = St->getBasePtr();
8819 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8820 DAG.getConstant(4, MVT::i32));
8822 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8823 St->getSrcValue(), St->getSrcValueOffset(),
8824 St->isVolatile(), St->getAlignment());
8825 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8827 St->getSrcValueOffset() + 4,
8829 MinAlign(St->getAlignment(), 4));
8830 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
8835 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8836 /// X86ISD::FXOR nodes.
8837 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8838 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8839 // F[X]OR(0.0, x) -> x
8840 // F[X]OR(x, 0.0) -> x
8841 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8842 if (C->getValueAPF().isPosZero())
8843 return N->getOperand(1);
8844 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8845 if (C->getValueAPF().isPosZero())
8846 return N->getOperand(0);
8850 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8851 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8852 // FAND(0.0, x) -> 0.0
8853 // FAND(x, 0.0) -> 0.0
8854 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8855 if (C->getValueAPF().isPosZero())
8856 return N->getOperand(0);
8857 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8858 if (C->getValueAPF().isPosZero())
8859 return N->getOperand(1);
8863 static SDValue PerformBTCombine(SDNode *N,
8865 TargetLowering::DAGCombinerInfo &DCI) {
8866 // BT ignores high bits in the bit index operand.
8867 SDValue Op1 = N->getOperand(1);
8868 if (Op1.hasOneUse()) {
8869 unsigned BitWidth = Op1.getValueSizeInBits();
8870 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8871 APInt KnownZero, KnownOne;
8872 TargetLowering::TargetLoweringOpt TLO(DAG);
8873 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8874 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8875 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8876 DCI.CommitTargetLoweringOpt(TLO);
8881 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8882 SDValue Op = N->getOperand(0);
8883 if (Op.getOpcode() == ISD::BIT_CONVERT)
8884 Op = Op.getOperand(0);
8885 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
8886 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8887 VT.getVectorElementType().getSizeInBits() ==
8888 OpVT.getVectorElementType().getSizeInBits()) {
8889 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8894 // On X86 and X86-64, atomic operations are lowered to locked instructions.
8895 // Locked instructions, in turn, have implicit fence semantics (all memory
8896 // operations are flushed before issuing the locked instruction, and the
8897 // are not buffered), so we can fold away the common pattern of
8898 // fence-atomic-fence.
8899 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
8900 SDValue atomic = N->getOperand(0);
8901 switch (atomic.getOpcode()) {
8902 case ISD::ATOMIC_CMP_SWAP:
8903 case ISD::ATOMIC_SWAP:
8904 case ISD::ATOMIC_LOAD_ADD:
8905 case ISD::ATOMIC_LOAD_SUB:
8906 case ISD::ATOMIC_LOAD_AND:
8907 case ISD::ATOMIC_LOAD_OR:
8908 case ISD::ATOMIC_LOAD_XOR:
8909 case ISD::ATOMIC_LOAD_NAND:
8910 case ISD::ATOMIC_LOAD_MIN:
8911 case ISD::ATOMIC_LOAD_MAX:
8912 case ISD::ATOMIC_LOAD_UMIN:
8913 case ISD::ATOMIC_LOAD_UMAX:
8919 SDValue fence = atomic.getOperand(0);
8920 if (fence.getOpcode() != ISD::MEMBARRIER)
8923 switch (atomic.getOpcode()) {
8924 case ISD::ATOMIC_CMP_SWAP:
8925 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8926 atomic.getOperand(1), atomic.getOperand(2),
8927 atomic.getOperand(3));
8928 case ISD::ATOMIC_SWAP:
8929 case ISD::ATOMIC_LOAD_ADD:
8930 case ISD::ATOMIC_LOAD_SUB:
8931 case ISD::ATOMIC_LOAD_AND:
8932 case ISD::ATOMIC_LOAD_OR:
8933 case ISD::ATOMIC_LOAD_XOR:
8934 case ISD::ATOMIC_LOAD_NAND:
8935 case ISD::ATOMIC_LOAD_MIN:
8936 case ISD::ATOMIC_LOAD_MAX:
8937 case ISD::ATOMIC_LOAD_UMIN:
8938 case ISD::ATOMIC_LOAD_UMAX:
8939 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8940 atomic.getOperand(1), atomic.getOperand(2));
8946 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8947 DAGCombinerInfo &DCI) const {
8948 SelectionDAG &DAG = DCI.DAG;
8949 switch (N->getOpcode()) {
8951 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8952 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8953 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8954 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8957 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8958 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8960 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8961 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8962 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8963 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
8964 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
8970 //===----------------------------------------------------------------------===//
8971 // X86 Inline Assembly Support
8972 //===----------------------------------------------------------------------===//
8974 static bool LowerToBSwap(CallInst *CI) {
8975 // FIXME: this should verify that we are targetting a 486 or better. If not,
8976 // we will turn this bswap into something that will be lowered to logical ops
8977 // instead of emitting the bswap asm. For now, we don't support 486 or lower
8978 // so don't worry about this.
8980 // Verify this is a simple bswap.
8981 if (CI->getNumOperands() != 2 ||
8982 CI->getType() != CI->getOperand(1)->getType() ||
8983 !CI->getType()->isInteger())
8986 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8987 if (!Ty || Ty->getBitWidth() % 16 != 0)
8990 // Okay, we can do this xform, do so now.
8991 const Type *Tys[] = { Ty };
8992 Module *M = CI->getParent()->getParent()->getParent();
8993 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
8995 Value *Op = CI->getOperand(1);
8996 Op = CallInst::Create(Int, Op, CI->getName(), CI);
8998 CI->replaceAllUsesWith(Op);
8999 CI->eraseFromParent();
9003 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9004 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9005 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9007 std::string AsmStr = IA->getAsmString();
9009 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9010 std::vector<std::string> AsmPieces;
9011 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9013 switch (AsmPieces.size()) {
9014 default: return false;
9016 AsmStr = AsmPieces[0];
9018 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9021 if (AsmPieces.size() == 2 &&
9022 (AsmPieces[0] == "bswap" ||
9023 AsmPieces[0] == "bswapq" ||
9024 AsmPieces[0] == "bswapl") &&
9025 (AsmPieces[1] == "$0" ||
9026 AsmPieces[1] == "${0:q}")) {
9027 // No need to check constraints, nothing other than the equivalent of
9028 // "=r,0" would be valid here.
9029 return LowerToBSwap(CI);
9031 // rorw $$8, ${0:w} --> llvm.bswap.i16
9032 if (CI->getType() == Type::getInt16Ty(CI->getContext()) &&
9033 AsmPieces.size() == 3 &&
9034 AsmPieces[0] == "rorw" &&
9035 AsmPieces[1] == "$$8," &&
9036 AsmPieces[2] == "${0:w}" &&
9037 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9038 return LowerToBSwap(CI);
9042 if (CI->getType() == Type::getInt64Ty(CI->getContext()) &&
9043 Constraints.size() >= 2 &&
9044 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9045 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9046 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9047 std::vector<std::string> Words;
9048 SplitString(AsmPieces[0], Words, " \t");
9049 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9051 SplitString(AsmPieces[1], Words, " \t");
9052 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9054 SplitString(AsmPieces[2], Words, " \t,");
9055 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9056 Words[2] == "%edx") {
9057 return LowerToBSwap(CI);
9069 /// getConstraintType - Given a constraint letter, return the type of
9070 /// constraint it is for this target.
9071 X86TargetLowering::ConstraintType
9072 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9073 if (Constraint.size() == 1) {
9074 switch (Constraint[0]) {
9086 return C_RegisterClass;
9094 return TargetLowering::getConstraintType(Constraint);
9097 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9098 /// with another that has more specific requirements based on the type of the
9099 /// corresponding operand.
9100 const char *X86TargetLowering::
9101 LowerXConstraint(EVT ConstraintVT) const {
9102 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9103 // 'f' like normal targets.
9104 if (ConstraintVT.isFloatingPoint()) {
9105 if (Subtarget->hasSSE2())
9107 if (Subtarget->hasSSE1())
9111 return TargetLowering::LowerXConstraint(ConstraintVT);
9114 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9115 /// vector. If it is invalid, don't add anything to Ops.
9116 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9119 std::vector<SDValue>&Ops,
9120 SelectionDAG &DAG) const {
9121 SDValue Result(0, 0);
9123 switch (Constraint) {
9126 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9127 if (C->getZExtValue() <= 31) {
9128 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9134 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9135 if (C->getZExtValue() <= 63) {
9136 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9143 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9144 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9151 if (C->getZExtValue() <= 255) {
9152 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9158 // 32-bit signed value
9159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9160 const ConstantInt *CI = C->getConstantIntValue();
9161 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9162 C->getSExtValue())) {
9163 // Widen to 64 bits here to get it sign extended.
9164 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9167 // FIXME gcc accepts some relocatable values here too, but only in certain
9168 // memory models; it's complicated.
9173 // 32-bit unsigned value
9174 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9175 const ConstantInt *CI = C->getConstantIntValue();
9176 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9177 C->getZExtValue())) {
9178 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9182 // FIXME gcc accepts some relocatable values here too, but only in certain
9183 // memory models; it's complicated.
9187 // Literal immediates are always ok.
9188 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9189 // Widen to 64 bits here to get it sign extended.
9190 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9194 // If we are in non-pic codegen mode, we allow the address of a global (with
9195 // an optional displacement) to be used with 'i'.
9196 GlobalAddressSDNode *GA = 0;
9199 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9201 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9202 Offset += GA->getOffset();
9204 } else if (Op.getOpcode() == ISD::ADD) {
9205 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9206 Offset += C->getZExtValue();
9207 Op = Op.getOperand(0);
9210 } else if (Op.getOpcode() == ISD::SUB) {
9211 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9212 Offset += -C->getZExtValue();
9213 Op = Op.getOperand(0);
9218 // Otherwise, this isn't something we can handle, reject it.
9222 GlobalValue *GV = GA->getGlobal();
9223 // If we require an extra load to get this address, as in PIC mode, we
9225 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9226 getTargetMachine())))
9230 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9232 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9238 if (Result.getNode()) {
9239 Ops.push_back(Result);
9242 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9246 std::vector<unsigned> X86TargetLowering::
9247 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9249 if (Constraint.size() == 1) {
9250 // FIXME: not handling fp-stack yet!
9251 switch (Constraint[0]) { // GCC X86 Constraint Letters
9252 default: break; // Unknown constraint letter
9253 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9254 if (Subtarget->is64Bit()) {
9256 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9257 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9258 X86::R10D,X86::R11D,X86::R12D,
9259 X86::R13D,X86::R14D,X86::R15D,
9260 X86::EBP, X86::ESP, 0);
9261 else if (VT == MVT::i16)
9262 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9263 X86::SI, X86::DI, X86::R8W,X86::R9W,
9264 X86::R10W,X86::R11W,X86::R12W,
9265 X86::R13W,X86::R14W,X86::R15W,
9266 X86::BP, X86::SP, 0);
9267 else if (VT == MVT::i8)
9268 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9269 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9270 X86::R10B,X86::R11B,X86::R12B,
9271 X86::R13B,X86::R14B,X86::R15B,
9272 X86::BPL, X86::SPL, 0);
9274 else if (VT == MVT::i64)
9275 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9276 X86::RSI, X86::RDI, X86::R8, X86::R9,
9277 X86::R10, X86::R11, X86::R12,
9278 X86::R13, X86::R14, X86::R15,
9279 X86::RBP, X86::RSP, 0);
9283 // 32-bit fallthrough
9286 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9287 else if (VT == MVT::i16)
9288 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9289 else if (VT == MVT::i8)
9290 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9291 else if (VT == MVT::i64)
9292 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9297 return std::vector<unsigned>();
9300 std::pair<unsigned, const TargetRegisterClass*>
9301 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9303 // First, see if this is a constraint that directly corresponds to an LLVM
9305 if (Constraint.size() == 1) {
9306 // GCC Constraint Letters
9307 switch (Constraint[0]) {
9309 case 'r': // GENERAL_REGS
9310 case 'R': // LEGACY_REGS
9311 case 'l': // INDEX_REGS
9313 return std::make_pair(0U, X86::GR8RegisterClass);
9315 return std::make_pair(0U, X86::GR16RegisterClass);
9316 if (VT == MVT::i32 || !Subtarget->is64Bit())
9317 return std::make_pair(0U, X86::GR32RegisterClass);
9318 return std::make_pair(0U, X86::GR64RegisterClass);
9319 case 'f': // FP Stack registers.
9320 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9321 // value to the correct fpstack register class.
9322 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9323 return std::make_pair(0U, X86::RFP32RegisterClass);
9324 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9325 return std::make_pair(0U, X86::RFP64RegisterClass);
9326 return std::make_pair(0U, X86::RFP80RegisterClass);
9327 case 'y': // MMX_REGS if MMX allowed.
9328 if (!Subtarget->hasMMX()) break;
9329 return std::make_pair(0U, X86::VR64RegisterClass);
9330 case 'Y': // SSE_REGS if SSE2 allowed
9331 if (!Subtarget->hasSSE2()) break;
9333 case 'x': // SSE_REGS if SSE1 allowed
9334 if (!Subtarget->hasSSE1()) break;
9336 switch (VT.getSimpleVT().SimpleTy) {
9338 // Scalar SSE types.
9341 return std::make_pair(0U, X86::FR32RegisterClass);
9344 return std::make_pair(0U, X86::FR64RegisterClass);
9352 return std::make_pair(0U, X86::VR128RegisterClass);
9358 // Use the default implementation in TargetLowering to convert the register
9359 // constraint into a member of a register class.
9360 std::pair<unsigned, const TargetRegisterClass*> Res;
9361 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9363 // Not found as a standard register?
9364 if (Res.second == 0) {
9365 // Map st(0) -> st(7) -> ST0
9366 if (Constraint.size() == 7 && Constraint[0] == '{' &&
9367 tolower(Constraint[1]) == 's' &&
9368 tolower(Constraint[2]) == 't' &&
9369 Constraint[3] == '(' &&
9370 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
9371 Constraint[5] == ')' &&
9372 Constraint[6] == '}') {
9374 Res.first = X86::ST0+Constraint[4]-'0';
9375 Res.second = X86::RFP80RegisterClass;
9379 // GCC allows "st(0)" to be called just plain "st".
9380 if (StringsEqualNoCase("{st}", Constraint)) {
9381 Res.first = X86::ST0;
9382 Res.second = X86::RFP80RegisterClass;
9387 if (StringsEqualNoCase("{flags}", Constraint)) {
9388 Res.first = X86::EFLAGS;
9389 Res.second = X86::CCRRegisterClass;
9393 // 'A' means EAX + EDX.
9394 if (Constraint == "A") {
9395 Res.first = X86::EAX;
9396 Res.second = X86::GR32_ADRegisterClass;
9402 // Otherwise, check to see if this is a register class of the wrong value
9403 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9404 // turn into {ax},{dx}.
9405 if (Res.second->hasType(VT))
9406 return Res; // Correct type already, nothing to do.
9408 // All of the single-register GCC register classes map their values onto
9409 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9410 // really want an 8-bit or 32-bit register, map to the appropriate register
9411 // class and return the appropriate register.
9412 if (Res.second == X86::GR16RegisterClass) {
9413 if (VT == MVT::i8) {
9414 unsigned DestReg = 0;
9415 switch (Res.first) {
9417 case X86::AX: DestReg = X86::AL; break;
9418 case X86::DX: DestReg = X86::DL; break;
9419 case X86::CX: DestReg = X86::CL; break;
9420 case X86::BX: DestReg = X86::BL; break;
9423 Res.first = DestReg;
9424 Res.second = X86::GR8RegisterClass;
9426 } else if (VT == MVT::i32) {
9427 unsigned DestReg = 0;
9428 switch (Res.first) {
9430 case X86::AX: DestReg = X86::EAX; break;
9431 case X86::DX: DestReg = X86::EDX; break;
9432 case X86::CX: DestReg = X86::ECX; break;
9433 case X86::BX: DestReg = X86::EBX; break;
9434 case X86::SI: DestReg = X86::ESI; break;
9435 case X86::DI: DestReg = X86::EDI; break;
9436 case X86::BP: DestReg = X86::EBP; break;
9437 case X86::SP: DestReg = X86::ESP; break;
9440 Res.first = DestReg;
9441 Res.second = X86::GR32RegisterClass;
9443 } else if (VT == MVT::i64) {
9444 unsigned DestReg = 0;
9445 switch (Res.first) {
9447 case X86::AX: DestReg = X86::RAX; break;
9448 case X86::DX: DestReg = X86::RDX; break;
9449 case X86::CX: DestReg = X86::RCX; break;
9450 case X86::BX: DestReg = X86::RBX; break;
9451 case X86::SI: DestReg = X86::RSI; break;
9452 case X86::DI: DestReg = X86::RDI; break;
9453 case X86::BP: DestReg = X86::RBP; break;
9454 case X86::SP: DestReg = X86::RSP; break;
9457 Res.first = DestReg;
9458 Res.second = X86::GR64RegisterClass;
9461 } else if (Res.second == X86::FR32RegisterClass ||
9462 Res.second == X86::FR64RegisterClass ||
9463 Res.second == X86::VR128RegisterClass) {
9464 // Handle references to XMM physical registers that got mapped into the
9465 // wrong class. This can happen with constraints like {xmm0} where the
9466 // target independent register mapper will just pick the first match it can
9467 // find, ignoring the required type.
9469 Res.second = X86::FR32RegisterClass;
9470 else if (VT == MVT::f64)
9471 Res.second = X86::FR64RegisterClass;
9472 else if (X86::VR128RegisterClass->hasType(VT))
9473 Res.second = X86::VR128RegisterClass;
9479 //===----------------------------------------------------------------------===//
9480 // X86 Widen vector type
9481 //===----------------------------------------------------------------------===//
9483 /// getWidenVectorType: given a vector type, returns the type to widen
9484 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9485 /// If there is no vector type that we want to widen to, returns MVT::Other
9486 /// When and where to widen is target dependent based on the cost of
9487 /// scalarizing vs using the wider vector type.
9489 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9490 assert(VT.isVector());
9491 if (isTypeLegal(VT))
9494 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9495 // type based on element type. This would speed up our search (though
9496 // it may not be worth it since the size of the list is relatively
9498 EVT EltVT = VT.getVectorElementType();
9499 unsigned NElts = VT.getVectorNumElements();
9501 // On X86, it make sense to widen any vector wider than 1
9505 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9506 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9507 EVT SVT = (MVT::SimpleValueType)nVT;
9509 if (isTypeLegal(SVT) &&
9510 SVT.getVectorElementType() == EltVT &&
9511 SVT.getVectorNumElements() > NElts)