1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
54 using namespace dwarf;
56 STATISTIC(NumTailCalls, "Number of tail calls");
59 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
61 // Forward declarations.
62 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
65 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
67 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
69 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
70 if (is64Bit) return new X8664_MachoTargetObjectFile();
71 return new TargetLoweringObjectFileMachO();
72 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
73 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
74 return new X8632_ELFTargetObjectFile(TM);
75 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
76 return new TargetLoweringObjectFileCOFF();
78 llvm_unreachable("unknown subtarget type");
81 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
82 : TargetLowering(TM, createTLOF(TM)) {
83 Subtarget = &TM.getSubtarget<X86Subtarget>();
84 X86ScalarSSEf64 = Subtarget->hasSSE2();
85 X86ScalarSSEf32 = Subtarget->hasSSE1();
86 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
88 RegInfo = TM.getRegisterInfo();
91 // Set up the TargetLowering object.
93 // X86 is weird, it always uses i8 for shift amounts and setcc results.
94 setShiftAmountType(MVT::i8);
95 setBooleanContents(ZeroOrOneBooleanContent);
96 setSchedulingPreference(Sched::RegPressure);
97 setStackPointerRegisterToSaveRestore(X86StackPtr);
99 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
100 // Setup Windows compiler runtime calls.
101 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
102 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
103 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
104 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
105 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
106 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
107 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
108 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
111 if (Subtarget->isTargetDarwin()) {
112 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
113 setUseUnderscoreSetJmp(false);
114 setUseUnderscoreLongJmp(false);
115 } else if (Subtarget->isTargetMingw()) {
116 // MS runtime is weird: it exports _setjmp, but longjmp!
117 setUseUnderscoreSetJmp(true);
118 setUseUnderscoreLongJmp(false);
120 setUseUnderscoreSetJmp(true);
121 setUseUnderscoreLongJmp(true);
124 // Set up the register classes.
125 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
126 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
127 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
128 if (Subtarget->is64Bit())
129 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
133 // We don't accept any truncstore of integer registers.
134 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
135 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
136 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
137 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
138 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
139 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
141 // SETOEQ and SETUNE require checking two conditions.
142 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
143 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
144 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
145 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
146 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
147 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
149 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
151 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
152 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
153 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
155 if (Subtarget->is64Bit()) {
156 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
157 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
158 } else if (!UseSoftFloat) {
159 // We have an algorithm for SSE2->double, and we turn this into a
160 // 64-bit FILD followed by conditional FADD for other targets.
161 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
162 // We have an algorithm for SSE2, and we turn this into a 64-bit
163 // FILD for other targets.
164 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
167 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
169 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
173 // SSE has no i16 to fp conversion, only i32
174 if (X86ScalarSSEf32) {
175 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
176 // f32 and f64 cases are Legal, f80 case is not
177 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
179 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
183 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
184 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
187 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
188 // are Legal, f80 is custom lowered.
189 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
190 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
192 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
194 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
195 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
197 if (X86ScalarSSEf32) {
198 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
199 // f32 and f64 cases are Legal, f80 case is not
200 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
202 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
203 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
206 // Handle FP_TO_UINT by promoting the destination to a larger signed
208 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
209 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
210 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
212 if (Subtarget->is64Bit()) {
213 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
215 } else if (!UseSoftFloat) {
216 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
217 // Expand FP_TO_UINT into a select.
218 // FIXME: We would like to use a Custom expander here eventually to do
219 // the optimal thing for SSE vs. the default expansion in the legalizer.
220 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
222 // With SSE3 we can use fisttpll to convert to a signed i64; without
223 // SSE, we're stuck with a fistpll.
224 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
227 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
228 if (!X86ScalarSSEf64) {
229 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
230 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
231 if (Subtarget->is64Bit()) {
232 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
233 // Without SSE, i64->f64 goes through memory.
234 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
238 // Scalar integer divide and remainder are lowered to use operations that
239 // produce two results, to match the available instructions. This exposes
240 // the two-result form to trivial CSE, which is able to combine x/y and x%y
241 // into a single instruction.
243 // Scalar integer multiply-high is also lowered to use two-result
244 // operations, to match the available instructions. However, plain multiply
245 // (low) operations are left as Legal, as there are single-result
246 // instructions for this in x86. Using the two-result multiply instructions
247 // when both high and low results are needed must be arranged by dagcombine.
248 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
249 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
250 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
251 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
252 setOperationAction(ISD::SREM , MVT::i8 , Expand);
253 setOperationAction(ISD::UREM , MVT::i8 , Expand);
254 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
255 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
256 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
257 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
258 setOperationAction(ISD::SREM , MVT::i16 , Expand);
259 setOperationAction(ISD::UREM , MVT::i16 , Expand);
260 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
261 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
262 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
263 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
264 setOperationAction(ISD::SREM , MVT::i32 , Expand);
265 setOperationAction(ISD::UREM , MVT::i32 , Expand);
266 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
267 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
268 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
269 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
270 setOperationAction(ISD::SREM , MVT::i64 , Expand);
271 setOperationAction(ISD::UREM , MVT::i64 , Expand);
273 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
274 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
275 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
276 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
277 if (Subtarget->is64Bit())
278 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
279 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
280 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
281 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
282 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
283 setOperationAction(ISD::FREM , MVT::f32 , Expand);
284 setOperationAction(ISD::FREM , MVT::f64 , Expand);
285 setOperationAction(ISD::FREM , MVT::f80 , Expand);
286 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
288 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
291 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
292 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
293 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
294 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
295 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
296 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
297 if (Subtarget->is64Bit()) {
298 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
299 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
300 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
303 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
304 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
306 // These should be promoted to a larger select which is supported.
307 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
308 // X86 wants to expand cmov itself.
309 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
310 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
311 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
312 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
313 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
314 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
316 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
317 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
318 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
319 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
320 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
323 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
325 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
328 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
329 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
330 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
331 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
332 if (Subtarget->is64Bit())
333 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
334 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
335 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
338 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
339 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
340 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
341 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
343 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
344 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
347 if (Subtarget->is64Bit()) {
348 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
349 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
350 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
353 if (Subtarget->hasSSE1())
354 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
356 // We may not have a libcall for MEMBARRIER so we should lower this.
357 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
359 // On X86 and X86-64, atomic operations are lowered to locked instructions.
360 // Locked instructions, in turn, have implicit fence semantics (all memory
361 // operations are flushed before issuing the locked instruction, and they
362 // are not buffered), so we can fold away the common pattern of
363 // fence-atomic-fence.
364 setShouldFoldAtomicFences(true);
366 // Expand certain atomics
367 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
369 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
370 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
375 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
377 if (!Subtarget->is64Bit()) {
378 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
380 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
381 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
382 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
383 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
384 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
387 // FIXME - use subtarget debug flags
388 if (!Subtarget->isTargetDarwin() &&
389 !Subtarget->isTargetELF() &&
390 !Subtarget->isTargetCygMing()) {
391 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
394 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
395 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
396 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
397 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
398 if (Subtarget->is64Bit()) {
399 setExceptionPointerRegister(X86::RAX);
400 setExceptionSelectorRegister(X86::RDX);
402 setExceptionPointerRegister(X86::EAX);
403 setExceptionSelectorRegister(X86::EDX);
405 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
406 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
408 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
410 setOperationAction(ISD::TRAP, MVT::Other, Legal);
412 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
413 setOperationAction(ISD::VASTART , MVT::Other, Custom);
414 setOperationAction(ISD::VAEND , MVT::Other, Expand);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::VAARG , MVT::Other, Custom);
417 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
419 setOperationAction(ISD::VAARG , MVT::Other, Expand);
420 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
423 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
424 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
425 if (Subtarget->is64Bit())
426 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
427 if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows())
428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
430 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
432 if (!UseSoftFloat && X86ScalarSSEf64) {
433 // f32 and f64 use SSE.
434 // Set up the FP register classes.
435 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
436 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
438 // Use ANDPD to simulate FABS.
439 setOperationAction(ISD::FABS , MVT::f64, Custom);
440 setOperationAction(ISD::FABS , MVT::f32, Custom);
442 // Use XORP to simulate FNEG.
443 setOperationAction(ISD::FNEG , MVT::f64, Custom);
444 setOperationAction(ISD::FNEG , MVT::f32, Custom);
446 // Use ANDPD and ORPD to simulate FCOPYSIGN.
447 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
448 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
450 // We don't support sin/cos/fmod
451 setOperationAction(ISD::FSIN , MVT::f64, Expand);
452 setOperationAction(ISD::FCOS , MVT::f64, Expand);
453 setOperationAction(ISD::FSIN , MVT::f32, Expand);
454 setOperationAction(ISD::FCOS , MVT::f32, Expand);
456 // Expand FP immediates into loads from the stack, except for the special
458 addLegalFPImmediate(APFloat(+0.0)); // xorpd
459 addLegalFPImmediate(APFloat(+0.0f)); // xorps
460 } else if (!UseSoftFloat && X86ScalarSSEf32) {
461 // Use SSE for f32, x87 for f64.
462 // Set up the FP register classes.
463 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
466 // Use ANDPS to simulate FABS.
467 setOperationAction(ISD::FABS , MVT::f32, Custom);
469 // Use XORP to simulate FNEG.
470 setOperationAction(ISD::FNEG , MVT::f32, Custom);
472 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
474 // Use ANDPS and ORPS to simulate FCOPYSIGN.
475 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
476 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
478 // We don't support sin/cos/fmod
479 setOperationAction(ISD::FSIN , MVT::f32, Expand);
480 setOperationAction(ISD::FCOS , MVT::f32, Expand);
482 // Special cases we handle for FP constants.
483 addLegalFPImmediate(APFloat(+0.0f)); // xorps
484 addLegalFPImmediate(APFloat(+0.0)); // FLD0
485 addLegalFPImmediate(APFloat(+1.0)); // FLD1
486 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
487 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
490 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
491 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
493 } else if (!UseSoftFloat) {
494 // f32 and f64 in x87.
495 // Set up the FP register classes.
496 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
497 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
499 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
500 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
501 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
502 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
505 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
506 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
508 addLegalFPImmediate(APFloat(+0.0)); // FLD0
509 addLegalFPImmediate(APFloat(+1.0)); // FLD1
510 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
511 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
512 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
513 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
514 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
515 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
518 // Long double always uses X87.
520 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
521 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
522 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
525 APFloat TmpFlt(+0.0);
526 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
528 addLegalFPImmediate(TmpFlt); // FLD0
530 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
531 APFloat TmpFlt2(+1.0);
532 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
534 addLegalFPImmediate(TmpFlt2); // FLD1
535 TmpFlt2.changeSign();
536 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
540 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
541 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
545 // Always use a library call for pow.
546 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
547 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
548 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
550 setOperationAction(ISD::FLOG, MVT::f80, Expand);
551 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
552 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
553 setOperationAction(ISD::FEXP, MVT::f80, Expand);
554 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
556 // First set operation action for all vector types to either promote
557 // (for widening) or expand (for scalarization). Then we will selectively
558 // turn on ones that can be effectively codegen'd.
559 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
560 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
561 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
576 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
577 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
608 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
610 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
611 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
612 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
613 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
614 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
615 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
616 setTruncStoreAction((MVT::SimpleValueType)VT,
617 (MVT::SimpleValueType)InnerVT, Expand);
618 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
619 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
620 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
623 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
624 // with -msoft-float, disable use of MMX as well.
625 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
626 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
627 // No operations on x86mmx supported, everything uses intrinsics.
630 // MMX-sized vectors (other than x86mmx) are expected to be expanded
631 // into smaller operations.
632 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
633 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
634 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
635 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
636 setOperationAction(ISD::AND, MVT::v8i8, Expand);
637 setOperationAction(ISD::AND, MVT::v4i16, Expand);
638 setOperationAction(ISD::AND, MVT::v2i32, Expand);
639 setOperationAction(ISD::AND, MVT::v1i64, Expand);
640 setOperationAction(ISD::OR, MVT::v8i8, Expand);
641 setOperationAction(ISD::OR, MVT::v4i16, Expand);
642 setOperationAction(ISD::OR, MVT::v2i32, Expand);
643 setOperationAction(ISD::OR, MVT::v1i64, Expand);
644 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
645 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
646 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
647 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
652 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
653 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
654 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
655 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
656 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
657 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
658 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
659 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
660 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
662 if (!UseSoftFloat && Subtarget->hasSSE1()) {
663 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
665 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
666 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
667 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
668 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
669 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
670 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
671 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
675 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
676 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
679 if (!UseSoftFloat && Subtarget->hasSSE2()) {
680 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
682 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
683 // registers cannot be used even for integer operations.
684 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
685 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
686 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
687 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
689 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
690 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
691 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
692 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
693 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
694 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
695 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
696 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
697 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
698 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
699 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
700 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
701 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
702 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
703 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
704 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
707 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
708 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
711 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
712 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
714 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
715 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
717 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
718 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
719 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
720 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
721 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
723 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
724 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
725 EVT VT = (MVT::SimpleValueType)i;
726 // Do not attempt to custom lower non-power-of-2 vectors
727 if (!isPowerOf2_32(VT.getVectorNumElements()))
729 // Do not attempt to custom lower non-128-bit vectors
730 if (!VT.is128BitVector())
732 setOperationAction(ISD::BUILD_VECTOR,
733 VT.getSimpleVT().SimpleTy, Custom);
734 setOperationAction(ISD::VECTOR_SHUFFLE,
735 VT.getSimpleVT().SimpleTy, Custom);
736 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
737 VT.getSimpleVT().SimpleTy, Custom);
740 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
741 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
742 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
743 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
744 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
747 if (Subtarget->is64Bit()) {
748 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
749 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
752 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
753 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
754 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
757 // Do not attempt to promote non-128-bit vectors
758 if (!VT.is128BitVector())
761 setOperationAction(ISD::AND, SVT, Promote);
762 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
763 setOperationAction(ISD::OR, SVT, Promote);
764 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
765 setOperationAction(ISD::XOR, SVT, Promote);
766 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
767 setOperationAction(ISD::LOAD, SVT, Promote);
768 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
769 setOperationAction(ISD::SELECT, SVT, Promote);
770 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
773 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
775 // Custom lower v2i64 and v2f64 selects.
776 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
777 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
778 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
779 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
781 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
782 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
785 if (Subtarget->hasSSE41()) {
786 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
787 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
788 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
789 setOperationAction(ISD::FRINT, MVT::f32, Legal);
790 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
791 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
792 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
793 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
794 setOperationAction(ISD::FRINT, MVT::f64, Legal);
795 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
797 // FIXME: Do we need to handle scalar-to-vector here?
798 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
800 // Can turn SHL into an integer multiply.
801 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
802 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
804 // i8 and i16 vectors are custom , because the source register and source
805 // source memory operand types are not the same width. f32 vectors are
806 // custom since the immediate controlling the insert encodes additional
808 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
809 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
810 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
811 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
813 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
814 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
815 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
816 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
818 if (Subtarget->is64Bit()) {
819 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
820 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
824 if (Subtarget->hasSSE42()) {
825 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
828 if (!UseSoftFloat && Subtarget->hasAVX()) {
829 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
830 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
831 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
832 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
833 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
835 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
836 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
837 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
838 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
839 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
840 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
841 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
842 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
843 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
844 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
845 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
846 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
847 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
848 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
849 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
851 // Operations to consider commented out -v16i16 v32i8
852 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
853 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
854 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
855 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
856 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
857 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
858 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
859 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
860 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
861 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
862 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
863 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
864 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
865 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
867 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
868 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
869 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
870 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
872 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
873 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
874 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
876 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
878 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
879 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
880 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
881 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
882 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
883 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
886 // Not sure we want to do this since there are no 256-bit integer
889 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
890 // This includes 256-bit vectors
891 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
892 EVT VT = (MVT::SimpleValueType)i;
894 // Do not attempt to custom lower non-power-of-2 vectors
895 if (!isPowerOf2_32(VT.getVectorNumElements()))
898 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
899 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
900 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
910 // Not sure we want to do this since there are no 256-bit integer
913 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
914 // Including 256-bit vectors
915 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
916 EVT VT = (MVT::SimpleValueType)i;
918 if (!VT.is256BitVector()) {
921 setOperationAction(ISD::AND, VT, Promote);
922 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
923 setOperationAction(ISD::OR, VT, Promote);
924 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
925 setOperationAction(ISD::XOR, VT, Promote);
926 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
927 setOperationAction(ISD::LOAD, VT, Promote);
928 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
929 setOperationAction(ISD::SELECT, VT, Promote);
930 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
933 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
937 // We want to custom lower some of our intrinsics.
938 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
940 // Add/Sub/Mul with overflow operations are custom lowered.
941 setOperationAction(ISD::SADDO, MVT::i32, Custom);
942 setOperationAction(ISD::UADDO, MVT::i32, Custom);
943 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
944 setOperationAction(ISD::USUBO, MVT::i32, Custom);
945 setOperationAction(ISD::SMULO, MVT::i32, Custom);
947 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
948 // handle type legalization for these operations here.
950 // FIXME: We really should do custom legalization for addition and
951 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
952 // than generic legalization for 64-bit multiplication-with-overflow, though.
953 if (Subtarget->is64Bit()) {
954 setOperationAction(ISD::SADDO, MVT::i64, Custom);
955 setOperationAction(ISD::UADDO, MVT::i64, Custom);
956 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
957 setOperationAction(ISD::USUBO, MVT::i64, Custom);
958 setOperationAction(ISD::SMULO, MVT::i64, Custom);
961 if (!Subtarget->is64Bit()) {
962 // These libcalls are not available in 32-bit.
963 setLibcallName(RTLIB::SHL_I128, 0);
964 setLibcallName(RTLIB::SRL_I128, 0);
965 setLibcallName(RTLIB::SRA_I128, 0);
968 // We have target-specific dag combine patterns for the following nodes:
969 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
970 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
971 setTargetDAGCombine(ISD::BUILD_VECTOR);
972 setTargetDAGCombine(ISD::SELECT);
973 setTargetDAGCombine(ISD::SHL);
974 setTargetDAGCombine(ISD::SRA);
975 setTargetDAGCombine(ISD::SRL);
976 setTargetDAGCombine(ISD::OR);
977 setTargetDAGCombine(ISD::STORE);
978 setTargetDAGCombine(ISD::ZERO_EXTEND);
979 if (Subtarget->is64Bit())
980 setTargetDAGCombine(ISD::MUL);
982 computeRegisterProperties();
984 // FIXME: These should be based on subtarget info. Plus, the values should
985 // be smaller when we are in optimizing for size mode.
986 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
987 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
988 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
989 setPrefLoopAlignment(16);
990 benefitFromCodePlacementOpt = true;
994 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
999 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1000 /// the desired ByVal argument alignment.
1001 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1004 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1005 if (VTy->getBitWidth() == 128)
1007 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1008 unsigned EltAlign = 0;
1009 getMaxByValAlign(ATy->getElementType(), EltAlign);
1010 if (EltAlign > MaxAlign)
1011 MaxAlign = EltAlign;
1012 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1013 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1014 unsigned EltAlign = 0;
1015 getMaxByValAlign(STy->getElementType(i), EltAlign);
1016 if (EltAlign > MaxAlign)
1017 MaxAlign = EltAlign;
1025 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1026 /// function arguments in the caller parameter area. For X86, aggregates
1027 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1028 /// are at 4-byte boundaries.
1029 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1030 if (Subtarget->is64Bit()) {
1031 // Max of 8 and alignment of type.
1032 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1039 if (Subtarget->hasSSE1())
1040 getMaxByValAlign(Ty, Align);
1044 /// getOptimalMemOpType - Returns the target specific optimal type for load
1045 /// and store operations as a result of memset, memcpy, and memmove
1046 /// lowering. If DstAlign is zero that means it's safe to destination
1047 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1048 /// means there isn't a need to check it against alignment requirement,
1049 /// probably because the source does not need to be loaded. If
1050 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1051 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1052 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1053 /// constant so it does not need to be loaded.
1054 /// It returns EVT::Other if the type should be determined using generic
1055 /// target-independent logic.
1057 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1058 unsigned DstAlign, unsigned SrcAlign,
1059 bool NonScalarIntSafe,
1061 MachineFunction &MF) const {
1062 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1063 // linux. This is because the stack realignment code can't handle certain
1064 // cases like PR2962. This should be removed when PR2962 is fixed.
1065 const Function *F = MF.getFunction();
1066 if (NonScalarIntSafe &&
1067 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1069 (Subtarget->isUnalignedMemAccessFast() ||
1070 ((DstAlign == 0 || DstAlign >= 16) &&
1071 (SrcAlign == 0 || SrcAlign >= 16))) &&
1072 Subtarget->getStackAlignment() >= 16) {
1073 if (Subtarget->hasSSE2())
1075 if (Subtarget->hasSSE1())
1077 } else if (!MemcpyStrSrc && Size >= 8 &&
1078 !Subtarget->is64Bit() &&
1079 Subtarget->getStackAlignment() >= 8 &&
1080 Subtarget->hasSSE2()) {
1081 // Do not use f64 to lower memcpy if source is string constant. It's
1082 // better to use i32 to avoid the loads.
1086 if (Subtarget->is64Bit() && Size >= 8)
1091 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1092 /// current function. The returned value is a member of the
1093 /// MachineJumpTableInfo::JTEntryKind enum.
1094 unsigned X86TargetLowering::getJumpTableEncoding() const {
1095 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1097 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1098 Subtarget->isPICStyleGOT())
1099 return MachineJumpTableInfo::EK_Custom32;
1101 // Otherwise, use the normal jump table encoding heuristics.
1102 return TargetLowering::getJumpTableEncoding();
1106 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1107 const MachineBasicBlock *MBB,
1108 unsigned uid,MCContext &Ctx) const{
1109 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1110 Subtarget->isPICStyleGOT());
1111 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1113 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1114 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1117 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1119 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1120 SelectionDAG &DAG) const {
1121 if (!Subtarget->is64Bit())
1122 // This doesn't have DebugLoc associated with it, but is not really the
1123 // same as a Register.
1124 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1128 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1129 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1131 const MCExpr *X86TargetLowering::
1132 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1133 MCContext &Ctx) const {
1134 // X86-64 uses RIP relative addressing based on the jump table label.
1135 if (Subtarget->isPICStyleRIPRel())
1136 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1138 // Otherwise, the reference is relative to the PIC base.
1139 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1142 /// getFunctionAlignment - Return the Log2 alignment of this function.
1143 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1144 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1147 std::pair<const TargetRegisterClass*, uint8_t>
1148 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1149 const TargetRegisterClass *RRC = 0;
1151 switch (VT.getSimpleVT().SimpleTy) {
1153 return TargetLowering::findRepresentativeClass(VT);
1154 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1155 RRC = (Subtarget->is64Bit()
1156 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1159 RRC = X86::VR64RegisterClass;
1161 case MVT::f32: case MVT::f64:
1162 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1163 case MVT::v4f32: case MVT::v2f64:
1164 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1166 RRC = X86::VR128RegisterClass;
1169 return std::make_pair(RRC, Cost);
1173 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1174 MachineFunction &MF) const {
1175 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1177 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
1178 switch (RC->getID()) {
1181 case X86::GR32RegClassID:
1183 case X86::GR64RegClassID:
1185 case X86::VR128RegClassID:
1186 return Subtarget->is64Bit() ? 10 : 4;
1187 case X86::VR64RegClassID:
1192 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1193 unsigned &Offset) const {
1194 if (!Subtarget->isTargetLinux())
1197 if (Subtarget->is64Bit()) {
1198 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1200 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1213 //===----------------------------------------------------------------------===//
1214 // Return Value Calling Convention Implementation
1215 //===----------------------------------------------------------------------===//
1217 #include "X86GenCallingConv.inc"
1220 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1221 const SmallVectorImpl<ISD::OutputArg> &Outs,
1222 LLVMContext &Context) const {
1223 SmallVector<CCValAssign, 16> RVLocs;
1224 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1226 return CCInfo.CheckReturn(Outs, RetCC_X86);
1230 X86TargetLowering::LowerReturn(SDValue Chain,
1231 CallingConv::ID CallConv, bool isVarArg,
1232 const SmallVectorImpl<ISD::OutputArg> &Outs,
1233 const SmallVectorImpl<SDValue> &OutVals,
1234 DebugLoc dl, SelectionDAG &DAG) const {
1235 MachineFunction &MF = DAG.getMachineFunction();
1236 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1238 SmallVector<CCValAssign, 16> RVLocs;
1239 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1240 RVLocs, *DAG.getContext());
1241 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1243 // Add the regs to the liveout set for the function.
1244 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1245 for (unsigned i = 0; i != RVLocs.size(); ++i)
1246 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1247 MRI.addLiveOut(RVLocs[i].getLocReg());
1251 SmallVector<SDValue, 6> RetOps;
1252 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1253 // Operand #1 = Bytes To Pop
1254 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1257 // Copy the result values into the output registers.
1258 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1259 CCValAssign &VA = RVLocs[i];
1260 assert(VA.isRegLoc() && "Can only return in registers!");
1261 SDValue ValToCopy = OutVals[i];
1262 EVT ValVT = ValToCopy.getValueType();
1264 // If this is x86-64, and we disabled SSE, we can't return FP values,
1265 // or SSE or MMX vectors.
1266 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1267 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1268 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1269 report_fatal_error("SSE register return with SSE disabled");
1271 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1272 // llvm-gcc has never done it right and no one has noticed, so this
1273 // should be OK for now.
1274 if (ValVT == MVT::f64 &&
1275 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1276 report_fatal_error("SSE2 register return with SSE2 disabled");
1278 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1279 // the RET instruction and handled by the FP Stackifier.
1280 if (VA.getLocReg() == X86::ST0 ||
1281 VA.getLocReg() == X86::ST1) {
1282 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1283 // change the value to the FP stack register class.
1284 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1285 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1286 RetOps.push_back(ValToCopy);
1287 // Don't emit a copytoreg.
1291 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1292 // which is returned in RAX / RDX.
1293 if (Subtarget->is64Bit()) {
1294 if (ValVT == MVT::x86mmx) {
1295 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1296 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1297 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1299 // If we don't have SSE2 available, convert to v4f32 so the generated
1300 // register is legal.
1301 if (!Subtarget->hasSSE2())
1302 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1307 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1308 Flag = Chain.getValue(1);
1311 // The x86-64 ABI for returning structs by value requires that we copy
1312 // the sret argument into %rax for the return. We saved the argument into
1313 // a virtual register in the entry block, so now we copy the value out
1315 if (Subtarget->is64Bit() &&
1316 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1317 MachineFunction &MF = DAG.getMachineFunction();
1318 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1319 unsigned Reg = FuncInfo->getSRetReturnReg();
1321 "SRetReturnReg should have been set in LowerFormalArguments().");
1322 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1324 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1325 Flag = Chain.getValue(1);
1327 // RAX now acts like a return value.
1328 MRI.addLiveOut(X86::RAX);
1331 RetOps[0] = Chain; // Update chain.
1333 // Add the flag if we have it.
1335 RetOps.push_back(Flag);
1337 return DAG.getNode(X86ISD::RET_FLAG, dl,
1338 MVT::Other, &RetOps[0], RetOps.size());
1341 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1342 // Temporarily disabled.
1344 if (N->getNumValues() != 1)
1346 if (!N->hasNUsesOfValue(1, 0))
1349 SDNode *Copy = *N->use_begin();
1350 if (Copy->getOpcode() != ISD::CopyToReg)
1352 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1354 if (UI->getOpcode() != X86ISD::RET_FLAG)
1360 /// LowerCallResult - Lower the result values of a call into the
1361 /// appropriate copies out of appropriate physical registers.
1364 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1365 CallingConv::ID CallConv, bool isVarArg,
1366 const SmallVectorImpl<ISD::InputArg> &Ins,
1367 DebugLoc dl, SelectionDAG &DAG,
1368 SmallVectorImpl<SDValue> &InVals) const {
1370 // Assign locations to each value returned by this call.
1371 SmallVector<CCValAssign, 16> RVLocs;
1372 bool Is64Bit = Subtarget->is64Bit();
1373 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1374 RVLocs, *DAG.getContext());
1375 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1377 // Copy all of the result registers out of their specified physreg.
1378 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1379 CCValAssign &VA = RVLocs[i];
1380 EVT CopyVT = VA.getValVT();
1382 // If this is x86-64, and we disabled SSE, we can't return FP values
1383 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1384 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1385 report_fatal_error("SSE register return with SSE disabled");
1390 // If this is a call to a function that returns an fp value on the floating
1391 // point stack, we must guarantee the the value is popped from the stack, so
1392 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1393 // if the return value is not used. We use the FpGET_ST0 instructions
1395 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1396 // If we prefer to use the value in xmm registers, copy it out as f80 and
1397 // use a truncate to move it from fp stack reg to xmm reg.
1398 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1399 bool isST0 = VA.getLocReg() == X86::ST0;
1401 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1402 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1403 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1404 SDValue Ops[] = { Chain, InFlag };
1405 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1407 Val = Chain.getValue(0);
1409 // Round the f80 to the right size, which also moves it to the appropriate
1411 if (CopyVT != VA.getValVT())
1412 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1413 // This truncation won't change the value.
1414 DAG.getIntPtrConstant(1));
1415 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1416 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1417 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1418 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1419 MVT::v2i64, InFlag).getValue(1);
1420 Val = Chain.getValue(0);
1421 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1422 Val, DAG.getConstant(0, MVT::i64));
1424 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1425 MVT::i64, InFlag).getValue(1);
1426 Val = Chain.getValue(0);
1428 Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val);
1430 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1431 CopyVT, InFlag).getValue(1);
1432 Val = Chain.getValue(0);
1434 InFlag = Chain.getValue(2);
1435 InVals.push_back(Val);
1442 //===----------------------------------------------------------------------===//
1443 // C & StdCall & Fast Calling Convention implementation
1444 //===----------------------------------------------------------------------===//
1445 // StdCall calling convention seems to be standard for many Windows' API
1446 // routines and around. It differs from C calling convention just a little:
1447 // callee should clean up the stack, not caller. Symbols should be also
1448 // decorated in some fancy way :) It doesn't support any vector arguments.
1449 // For info on fast calling convention see Fast Calling Convention (tail call)
1450 // implementation LowerX86_32FastCCCallTo.
1452 /// CallIsStructReturn - Determines whether a call uses struct return
1454 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1458 return Outs[0].Flags.isSRet();
1461 /// ArgsAreStructReturn - Determines whether a function uses struct
1462 /// return semantics.
1464 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1468 return Ins[0].Flags.isSRet();
1471 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1472 /// by "Src" to address "Dst" with size and alignment information specified by
1473 /// the specific parameter attribute. The copy will be passed as a byval
1474 /// function parameter.
1476 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1477 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1479 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1481 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1482 /*isVolatile*/false, /*AlwaysInline=*/true,
1483 MachinePointerInfo(), MachinePointerInfo());
1486 /// IsTailCallConvention - Return true if the calling convention is one that
1487 /// supports tail call optimization.
1488 static bool IsTailCallConvention(CallingConv::ID CC) {
1489 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1492 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1493 /// a tailcall target by changing its ABI.
1494 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1495 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1499 X86TargetLowering::LowerMemArgument(SDValue Chain,
1500 CallingConv::ID CallConv,
1501 const SmallVectorImpl<ISD::InputArg> &Ins,
1502 DebugLoc dl, SelectionDAG &DAG,
1503 const CCValAssign &VA,
1504 MachineFrameInfo *MFI,
1506 // Create the nodes corresponding to a load from this parameter slot.
1507 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1508 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1509 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1512 // If value is passed by pointer we have address passed instead of the value
1514 if (VA.getLocInfo() == CCValAssign::Indirect)
1515 ValVT = VA.getLocVT();
1517 ValVT = VA.getValVT();
1519 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1520 // changed with more analysis.
1521 // In case of tail call optimization mark all arguments mutable. Since they
1522 // could be overwritten by lowering of arguments in case of a tail call.
1523 if (Flags.isByVal()) {
1524 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1525 VA.getLocMemOffset(), isImmutable);
1526 return DAG.getFrameIndex(FI, getPointerTy());
1528 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1529 VA.getLocMemOffset(), isImmutable);
1530 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1531 return DAG.getLoad(ValVT, dl, Chain, FIN,
1532 MachinePointerInfo::getFixedStack(FI),
1538 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1539 CallingConv::ID CallConv,
1541 const SmallVectorImpl<ISD::InputArg> &Ins,
1544 SmallVectorImpl<SDValue> &InVals)
1546 MachineFunction &MF = DAG.getMachineFunction();
1547 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1549 const Function* Fn = MF.getFunction();
1550 if (Fn->hasExternalLinkage() &&
1551 Subtarget->isTargetCygMing() &&
1552 Fn->getName() == "main")
1553 FuncInfo->setForceFramePointer(true);
1555 MachineFrameInfo *MFI = MF.getFrameInfo();
1556 bool Is64Bit = Subtarget->is64Bit();
1557 bool IsWin64 = Subtarget->isTargetWin64();
1559 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1560 "Var args not supported with calling convention fastcc or ghc");
1562 // Assign locations to all of the incoming arguments.
1563 SmallVector<CCValAssign, 16> ArgLocs;
1564 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1565 ArgLocs, *DAG.getContext());
1566 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1568 unsigned LastVal = ~0U;
1570 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1571 CCValAssign &VA = ArgLocs[i];
1572 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1574 assert(VA.getValNo() != LastVal &&
1575 "Don't support value assigned to multiple locs yet");
1576 LastVal = VA.getValNo();
1578 if (VA.isRegLoc()) {
1579 EVT RegVT = VA.getLocVT();
1580 TargetRegisterClass *RC = NULL;
1581 if (RegVT == MVT::i32)
1582 RC = X86::GR32RegisterClass;
1583 else if (Is64Bit && RegVT == MVT::i64)
1584 RC = X86::GR64RegisterClass;
1585 else if (RegVT == MVT::f32)
1586 RC = X86::FR32RegisterClass;
1587 else if (RegVT == MVT::f64)
1588 RC = X86::FR64RegisterClass;
1589 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1590 RC = X86::VR256RegisterClass;
1591 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1592 RC = X86::VR128RegisterClass;
1593 else if (RegVT == MVT::x86mmx)
1594 RC = X86::VR64RegisterClass;
1596 llvm_unreachable("Unknown argument type!");
1598 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1599 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1601 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1602 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1604 if (VA.getLocInfo() == CCValAssign::SExt)
1605 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1606 DAG.getValueType(VA.getValVT()));
1607 else if (VA.getLocInfo() == CCValAssign::ZExt)
1608 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1609 DAG.getValueType(VA.getValVT()));
1610 else if (VA.getLocInfo() == CCValAssign::BCvt)
1611 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1613 if (VA.isExtInLoc()) {
1614 // Handle MMX values passed in XMM regs.
1615 if (RegVT.isVector()) {
1616 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1619 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1622 assert(VA.isMemLoc());
1623 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1626 // If value is passed via pointer - do a load.
1627 if (VA.getLocInfo() == CCValAssign::Indirect)
1628 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1629 MachinePointerInfo(), false, false, 0);
1631 InVals.push_back(ArgValue);
1634 // The x86-64 ABI for returning structs by value requires that we copy
1635 // the sret argument into %rax for the return. Save the argument into
1636 // a virtual register so that we can access it from the return points.
1637 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1638 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1639 unsigned Reg = FuncInfo->getSRetReturnReg();
1641 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1642 FuncInfo->setSRetReturnReg(Reg);
1644 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1645 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1648 unsigned StackSize = CCInfo.getNextStackOffset();
1649 // Align stack specially for tail calls.
1650 if (FuncIsMadeTailCallSafe(CallConv))
1651 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1653 // If the function takes variable number of arguments, make a frame index for
1654 // the start of the first vararg value... for expansion of llvm.va_start.
1656 if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1657 CallConv != CallingConv::X86_ThisCall))) {
1658 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1661 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1663 // FIXME: We should really autogenerate these arrays
1664 static const unsigned GPR64ArgRegsWin64[] = {
1665 X86::RCX, X86::RDX, X86::R8, X86::R9
1667 static const unsigned GPR64ArgRegs64Bit[] = {
1668 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1670 static const unsigned XMMArgRegs64Bit[] = {
1671 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1672 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1674 const unsigned *GPR64ArgRegs;
1675 unsigned NumXMMRegs = 0;
1678 // The XMM registers which might contain var arg parameters are shadowed
1679 // in their paired GPR. So we only need to save the GPR to their home
1681 TotalNumIntRegs = 4;
1682 GPR64ArgRegs = GPR64ArgRegsWin64;
1684 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1685 GPR64ArgRegs = GPR64ArgRegs64Bit;
1687 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1689 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1692 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1693 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1694 "SSE register cannot be used when SSE is disabled!");
1695 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1696 "SSE register cannot be used when SSE is disabled!");
1697 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1698 // Kernel mode asks for SSE to be disabled, so don't push them
1700 TotalNumXMMRegs = 0;
1703 const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo();
1704 // Get to the caller-allocated home save location. Add 8 to account
1705 // for the return address.
1706 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1707 FuncInfo->setRegSaveFrameIndex(
1708 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1709 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1711 // For X86-64, if there are vararg parameters that are passed via
1712 // registers, then we must store them to their spots on the stack so they
1713 // may be loaded by deferencing the result of va_next.
1714 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1715 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1716 FuncInfo->setRegSaveFrameIndex(
1717 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1721 // Store the integer parameter registers.
1722 SmallVector<SDValue, 8> MemOps;
1723 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1725 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1726 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1727 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1728 DAG.getIntPtrConstant(Offset));
1729 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1730 X86::GR64RegisterClass);
1731 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1733 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1734 MachinePointerInfo::getFixedStack(
1735 FuncInfo->getRegSaveFrameIndex(), Offset),
1737 MemOps.push_back(Store);
1741 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1742 // Now store the XMM (fp + vector) parameter registers.
1743 SmallVector<SDValue, 11> SaveXMMOps;
1744 SaveXMMOps.push_back(Chain);
1746 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1747 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1748 SaveXMMOps.push_back(ALVal);
1750 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1751 FuncInfo->getRegSaveFrameIndex()));
1752 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1753 FuncInfo->getVarArgsFPOffset()));
1755 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1756 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1757 X86::VR128RegisterClass);
1758 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1759 SaveXMMOps.push_back(Val);
1761 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1763 &SaveXMMOps[0], SaveXMMOps.size()));
1766 if (!MemOps.empty())
1767 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1768 &MemOps[0], MemOps.size());
1772 // Some CCs need callee pop.
1773 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1774 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1776 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1777 // If this is an sret function, the return should pop the hidden pointer.
1778 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1779 FuncInfo->setBytesToPopOnReturn(4);
1783 // RegSaveFrameIndex is X86-64 only.
1784 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1785 if (CallConv == CallingConv::X86_FastCall ||
1786 CallConv == CallingConv::X86_ThisCall)
1787 // fastcc functions can't have varargs.
1788 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1795 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1796 SDValue StackPtr, SDValue Arg,
1797 DebugLoc dl, SelectionDAG &DAG,
1798 const CCValAssign &VA,
1799 ISD::ArgFlagsTy Flags) const {
1800 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1801 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1802 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1803 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1804 if (Flags.isByVal())
1805 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1807 return DAG.getStore(Chain, dl, Arg, PtrOff,
1808 MachinePointerInfo::getStack(LocMemOffset),
1812 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1813 /// optimization is performed and it is required.
1815 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1816 SDValue &OutRetAddr, SDValue Chain,
1817 bool IsTailCall, bool Is64Bit,
1818 int FPDiff, DebugLoc dl) const {
1819 // Adjust the Return address stack slot.
1820 EVT VT = getPointerTy();
1821 OutRetAddr = getReturnAddressFrameIndex(DAG);
1823 // Load the "old" Return address.
1824 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1826 return SDValue(OutRetAddr.getNode(), 1);
1829 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1830 /// optimization is performed and it is required (FPDiff!=0).
1832 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1833 SDValue Chain, SDValue RetAddrFrIdx,
1834 bool Is64Bit, int FPDiff, DebugLoc dl) {
1835 // Store the return address to the appropriate stack slot.
1836 if (!FPDiff) return Chain;
1837 // Calculate the new stack slot for the return address.
1838 int SlotSize = Is64Bit ? 8 : 4;
1839 int NewReturnAddrFI =
1840 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1841 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1842 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1843 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1844 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1850 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1851 CallingConv::ID CallConv, bool isVarArg,
1853 const SmallVectorImpl<ISD::OutputArg> &Outs,
1854 const SmallVectorImpl<SDValue> &OutVals,
1855 const SmallVectorImpl<ISD::InputArg> &Ins,
1856 DebugLoc dl, SelectionDAG &DAG,
1857 SmallVectorImpl<SDValue> &InVals) const {
1858 MachineFunction &MF = DAG.getMachineFunction();
1859 bool Is64Bit = Subtarget->is64Bit();
1860 bool IsStructRet = CallIsStructReturn(Outs);
1861 bool IsSibcall = false;
1864 // Check if it's really possible to do a tail call.
1865 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1866 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1867 Outs, OutVals, Ins, DAG);
1869 // Sibcalls are automatically detected tailcalls which do not require
1871 if (!GuaranteedTailCallOpt && isTailCall)
1878 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1879 "Var args not supported with calling convention fastcc or ghc");
1881 // Analyze operands of the call, assigning locations to each operand.
1882 SmallVector<CCValAssign, 16> ArgLocs;
1883 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1884 ArgLocs, *DAG.getContext());
1885 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
1887 // Get a count of how many bytes are to be pushed on the stack.
1888 unsigned NumBytes = CCInfo.getNextStackOffset();
1890 // This is a sibcall. The memory operands are available in caller's
1891 // own caller's stack.
1893 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1894 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1897 if (isTailCall && !IsSibcall) {
1898 // Lower arguments at fp - stackoffset + fpdiff.
1899 unsigned NumBytesCallerPushed =
1900 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1901 FPDiff = NumBytesCallerPushed - NumBytes;
1903 // Set the delta of movement of the returnaddr stackslot.
1904 // But only set if delta is greater than previous delta.
1905 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1906 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1910 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1912 SDValue RetAddrFrIdx;
1913 // Load return adress for tail calls.
1914 if (isTailCall && FPDiff)
1915 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1916 Is64Bit, FPDiff, dl);
1918 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1919 SmallVector<SDValue, 8> MemOpChains;
1922 // Walk the register/memloc assignments, inserting copies/loads. In the case
1923 // of tail call optimization arguments are handle later.
1924 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1925 CCValAssign &VA = ArgLocs[i];
1926 EVT RegVT = VA.getLocVT();
1927 SDValue Arg = OutVals[i];
1928 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1929 bool isByVal = Flags.isByVal();
1931 // Promote the value if needed.
1932 switch (VA.getLocInfo()) {
1933 default: llvm_unreachable("Unknown loc info!");
1934 case CCValAssign::Full: break;
1935 case CCValAssign::SExt:
1936 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1938 case CCValAssign::ZExt:
1939 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1941 case CCValAssign::AExt:
1942 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1943 // Special case: passing MMX values in XMM registers.
1944 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
1945 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1946 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1948 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1950 case CCValAssign::BCvt:
1951 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
1953 case CCValAssign::Indirect: {
1954 // Store the argument.
1955 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1956 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1957 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1958 MachinePointerInfo::getFixedStack(FI),
1965 if (VA.isRegLoc()) {
1966 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1967 if (isVarArg && Subtarget->isTargetWin64()) {
1968 // Win64 ABI requires argument XMM reg to be copied to the corresponding
1969 // shadow reg if callee is a varargs function.
1970 unsigned ShadowReg = 0;
1971 switch (VA.getLocReg()) {
1972 case X86::XMM0: ShadowReg = X86::RCX; break;
1973 case X86::XMM1: ShadowReg = X86::RDX; break;
1974 case X86::XMM2: ShadowReg = X86::R8; break;
1975 case X86::XMM3: ShadowReg = X86::R9; break;
1978 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
1980 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1981 assert(VA.isMemLoc());
1982 if (StackPtr.getNode() == 0)
1983 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1984 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1985 dl, DAG, VA, Flags));
1989 if (!MemOpChains.empty())
1990 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1991 &MemOpChains[0], MemOpChains.size());
1993 // Build a sequence of copy-to-reg nodes chained together with token chain
1994 // and flag operands which copy the outgoing args into registers.
1996 // Tail call byval lowering might overwrite argument registers so in case of
1997 // tail call optimization the copies to registers are lowered later.
1999 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2000 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2001 RegsToPass[i].second, InFlag);
2002 InFlag = Chain.getValue(1);
2005 if (Subtarget->isPICStyleGOT()) {
2006 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2009 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2010 DAG.getNode(X86ISD::GlobalBaseReg,
2011 DebugLoc(), getPointerTy()),
2013 InFlag = Chain.getValue(1);
2015 // If we are tail calling and generating PIC/GOT style code load the
2016 // address of the callee into ECX. The value in ecx is used as target of
2017 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2018 // for tail calls on PIC/GOT architectures. Normally we would just put the
2019 // address of GOT into ebx and then call target@PLT. But for tail calls
2020 // ebx would be restored (since ebx is callee saved) before jumping to the
2023 // Note: The actual moving to ECX is done further down.
2024 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2025 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2026 !G->getGlobal()->hasProtectedVisibility())
2027 Callee = LowerGlobalAddress(Callee, DAG);
2028 else if (isa<ExternalSymbolSDNode>(Callee))
2029 Callee = LowerExternalSymbol(Callee, DAG);
2033 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2034 // From AMD64 ABI document:
2035 // For calls that may call functions that use varargs or stdargs
2036 // (prototype-less calls or calls to functions containing ellipsis (...) in
2037 // the declaration) %al is used as hidden argument to specify the number
2038 // of SSE registers used. The contents of %al do not need to match exactly
2039 // the number of registers, but must be an ubound on the number of SSE
2040 // registers used and is in the range 0 - 8 inclusive.
2042 // Count the number of XMM registers allocated.
2043 static const unsigned XMMArgRegs[] = {
2044 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2045 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2047 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2048 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2049 && "SSE registers cannot be used when SSE is disabled");
2051 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2052 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2053 InFlag = Chain.getValue(1);
2057 // For tail calls lower the arguments to the 'real' stack slot.
2059 // Force all the incoming stack arguments to be loaded from the stack
2060 // before any new outgoing arguments are stored to the stack, because the
2061 // outgoing stack slots may alias the incoming argument stack slots, and
2062 // the alias isn't otherwise explicit. This is slightly more conservative
2063 // than necessary, because it means that each store effectively depends
2064 // on every argument instead of just those arguments it would clobber.
2065 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2067 SmallVector<SDValue, 8> MemOpChains2;
2070 // Do not flag preceeding copytoreg stuff together with the following stuff.
2072 if (GuaranteedTailCallOpt) {
2073 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2074 CCValAssign &VA = ArgLocs[i];
2077 assert(VA.isMemLoc());
2078 SDValue Arg = OutVals[i];
2079 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2080 // Create frame index.
2081 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2082 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2083 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2084 FIN = DAG.getFrameIndex(FI, getPointerTy());
2086 if (Flags.isByVal()) {
2087 // Copy relative to framepointer.
2088 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2089 if (StackPtr.getNode() == 0)
2090 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2092 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2094 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2098 // Store relative to framepointer.
2099 MemOpChains2.push_back(
2100 DAG.getStore(ArgChain, dl, Arg, FIN,
2101 MachinePointerInfo::getFixedStack(FI),
2107 if (!MemOpChains2.empty())
2108 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2109 &MemOpChains2[0], MemOpChains2.size());
2111 // Copy arguments to their registers.
2112 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2113 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2114 RegsToPass[i].second, InFlag);
2115 InFlag = Chain.getValue(1);
2119 // Store the return address to the appropriate stack slot.
2120 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2124 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2125 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2126 // In the 64-bit large code model, we have to make all calls
2127 // through a register, since the call instruction's 32-bit
2128 // pc-relative offset may not be large enough to hold the whole
2130 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2131 // If the callee is a GlobalAddress node (quite common, every direct call
2132 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2135 // We should use extra load for direct calls to dllimported functions in
2137 const GlobalValue *GV = G->getGlobal();
2138 if (!GV->hasDLLImportLinkage()) {
2139 unsigned char OpFlags = 0;
2141 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2142 // external symbols most go through the PLT in PIC mode. If the symbol
2143 // has hidden or protected visibility, or if it is static or local, then
2144 // we don't need to use the PLT - we can directly call it.
2145 if (Subtarget->isTargetELF() &&
2146 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2147 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2148 OpFlags = X86II::MO_PLT;
2149 } else if (Subtarget->isPICStyleStubAny() &&
2150 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2151 Subtarget->getDarwinVers() < 9) {
2152 // PC-relative references to external symbols should go through $stub,
2153 // unless we're building with the leopard linker or later, which
2154 // automatically synthesizes these stubs.
2155 OpFlags = X86II::MO_DARWIN_STUB;
2158 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2159 G->getOffset(), OpFlags);
2161 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2162 unsigned char OpFlags = 0;
2165 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2166 // external symbols should go through the PLT.
2167 if (Subtarget->isTargetELF() &&
2168 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2169 OpFlags = X86II::MO_PLT;
2170 } else if (Subtarget->isPICStyleStubAny() &&
2171 Subtarget->getDarwinVers() < 9) {
2172 // PC-relative references to external symbols should go through $stub,
2173 // unless we're building with the leopard linker or later, which
2174 // automatically synthesizes these stubs.
2175 OpFlags = X86II::MO_DARWIN_STUB;
2179 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2183 // Returns a chain & a flag for retval copy to use.
2184 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2185 SmallVector<SDValue, 8> Ops;
2187 if (!IsSibcall && isTailCall) {
2188 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2189 DAG.getIntPtrConstant(0, true), InFlag);
2190 InFlag = Chain.getValue(1);
2193 Ops.push_back(Chain);
2194 Ops.push_back(Callee);
2197 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2199 // Add argument registers to the end of the list so that they are known live
2201 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2202 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2203 RegsToPass[i].second.getValueType()));
2205 // Add an implicit use GOT pointer in EBX.
2206 if (!isTailCall && Subtarget->isPICStyleGOT())
2207 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2209 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2210 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2211 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2213 if (InFlag.getNode())
2214 Ops.push_back(InFlag);
2218 //// If this is the first return lowered for this function, add the regs
2219 //// to the liveout set for the function.
2220 // This isn't right, although it's probably harmless on x86; liveouts
2221 // should be computed from returns not tail calls. Consider a void
2222 // function making a tail call to a function returning int.
2223 return DAG.getNode(X86ISD::TC_RETURN, dl,
2224 NodeTys, &Ops[0], Ops.size());
2227 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2228 InFlag = Chain.getValue(1);
2230 // Create the CALLSEQ_END node.
2231 unsigned NumBytesForCalleeToPush;
2232 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2233 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2234 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2235 // If this is a call to a struct-return function, the callee
2236 // pops the hidden struct pointer, so we have to push it back.
2237 // This is common for Darwin/X86, Linux & Mingw32 targets.
2238 NumBytesForCalleeToPush = 4;
2240 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2242 // Returns a flag for retval copy to use.
2244 Chain = DAG.getCALLSEQ_END(Chain,
2245 DAG.getIntPtrConstant(NumBytes, true),
2246 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2249 InFlag = Chain.getValue(1);
2252 // Handle result values, copying them out of physregs into vregs that we
2254 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2255 Ins, dl, DAG, InVals);
2259 //===----------------------------------------------------------------------===//
2260 // Fast Calling Convention (tail call) implementation
2261 //===----------------------------------------------------------------------===//
2263 // Like std call, callee cleans arguments, convention except that ECX is
2264 // reserved for storing the tail called function address. Only 2 registers are
2265 // free for argument passing (inreg). Tail call optimization is performed
2267 // * tailcallopt is enabled
2268 // * caller/callee are fastcc
2269 // On X86_64 architecture with GOT-style position independent code only local
2270 // (within module) calls are supported at the moment.
2271 // To keep the stack aligned according to platform abi the function
2272 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2273 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2274 // If a tail called function callee has more arguments than the caller the
2275 // caller needs to make sure that there is room to move the RETADDR to. This is
2276 // achieved by reserving an area the size of the argument delta right after the
2277 // original REtADDR, but before the saved framepointer or the spilled registers
2278 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2290 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2291 /// for a 16 byte align requirement.
2293 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2294 SelectionDAG& DAG) const {
2295 MachineFunction &MF = DAG.getMachineFunction();
2296 const TargetMachine &TM = MF.getTarget();
2297 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2298 unsigned StackAlignment = TFI.getStackAlignment();
2299 uint64_t AlignMask = StackAlignment - 1;
2300 int64_t Offset = StackSize;
2301 uint64_t SlotSize = TD->getPointerSize();
2302 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2303 // Number smaller than 12 so just add the difference.
2304 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2306 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2307 Offset = ((~AlignMask) & Offset) + StackAlignment +
2308 (StackAlignment-SlotSize);
2313 /// MatchingStackOffset - Return true if the given stack call argument is
2314 /// already available in the same position (relatively) of the caller's
2315 /// incoming argument stack.
2317 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2318 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2319 const X86InstrInfo *TII) {
2320 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2322 if (Arg.getOpcode() == ISD::CopyFromReg) {
2323 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2324 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2326 MachineInstr *Def = MRI->getVRegDef(VR);
2329 if (!Flags.isByVal()) {
2330 if (!TII->isLoadFromStackSlot(Def, FI))
2333 unsigned Opcode = Def->getOpcode();
2334 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2335 Def->getOperand(1).isFI()) {
2336 FI = Def->getOperand(1).getIndex();
2337 Bytes = Flags.getByValSize();
2341 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2342 if (Flags.isByVal())
2343 // ByVal argument is passed in as a pointer but it's now being
2344 // dereferenced. e.g.
2345 // define @foo(%struct.X* %A) {
2346 // tail call @bar(%struct.X* byval %A)
2349 SDValue Ptr = Ld->getBasePtr();
2350 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2353 FI = FINode->getIndex();
2357 assert(FI != INT_MAX);
2358 if (!MFI->isFixedObjectIndex(FI))
2360 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2363 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2364 /// for tail call optimization. Targets which want to do tail call
2365 /// optimization should implement this function.
2367 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2368 CallingConv::ID CalleeCC,
2370 bool isCalleeStructRet,
2371 bool isCallerStructRet,
2372 const SmallVectorImpl<ISD::OutputArg> &Outs,
2373 const SmallVectorImpl<SDValue> &OutVals,
2374 const SmallVectorImpl<ISD::InputArg> &Ins,
2375 SelectionDAG& DAG) const {
2376 if (!IsTailCallConvention(CalleeCC) &&
2377 CalleeCC != CallingConv::C)
2380 // If -tailcallopt is specified, make fastcc functions tail-callable.
2381 const MachineFunction &MF = DAG.getMachineFunction();
2382 const Function *CallerF = DAG.getMachineFunction().getFunction();
2383 CallingConv::ID CallerCC = CallerF->getCallingConv();
2384 bool CCMatch = CallerCC == CalleeCC;
2386 if (GuaranteedTailCallOpt) {
2387 if (IsTailCallConvention(CalleeCC) && CCMatch)
2392 // Look for obvious safe cases to perform tail call optimization that do not
2393 // require ABI changes. This is what gcc calls sibcall.
2395 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2396 // emit a special epilogue.
2397 if (RegInfo->needsStackRealignment(MF))
2400 // Do not sibcall optimize vararg calls unless the call site is not passing
2402 if (isVarArg && !Outs.empty())
2405 // Also avoid sibcall optimization if either caller or callee uses struct
2406 // return semantics.
2407 if (isCalleeStructRet || isCallerStructRet)
2410 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2411 // Therefore if it's not used by the call it is not safe to optimize this into
2413 bool Unused = false;
2414 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2421 SmallVector<CCValAssign, 16> RVLocs;
2422 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2423 RVLocs, *DAG.getContext());
2424 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2425 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2426 CCValAssign &VA = RVLocs[i];
2427 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2432 // If the calling conventions do not match, then we'd better make sure the
2433 // results are returned in the same way as what the caller expects.
2435 SmallVector<CCValAssign, 16> RVLocs1;
2436 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2437 RVLocs1, *DAG.getContext());
2438 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2440 SmallVector<CCValAssign, 16> RVLocs2;
2441 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2442 RVLocs2, *DAG.getContext());
2443 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2445 if (RVLocs1.size() != RVLocs2.size())
2447 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2448 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2450 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2452 if (RVLocs1[i].isRegLoc()) {
2453 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2456 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2462 // If the callee takes no arguments then go on to check the results of the
2464 if (!Outs.empty()) {
2465 // Check if stack adjustment is needed. For now, do not do this if any
2466 // argument is passed on the stack.
2467 SmallVector<CCValAssign, 16> ArgLocs;
2468 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2469 ArgLocs, *DAG.getContext());
2470 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2471 if (CCInfo.getNextStackOffset()) {
2472 MachineFunction &MF = DAG.getMachineFunction();
2473 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2475 if (Subtarget->isTargetWin64())
2476 // Win64 ABI has additional complications.
2479 // Check if the arguments are already laid out in the right way as
2480 // the caller's fixed stack objects.
2481 MachineFrameInfo *MFI = MF.getFrameInfo();
2482 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2483 const X86InstrInfo *TII =
2484 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2485 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2486 CCValAssign &VA = ArgLocs[i];
2487 SDValue Arg = OutVals[i];
2488 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2489 if (VA.getLocInfo() == CCValAssign::Indirect)
2491 if (!VA.isRegLoc()) {
2492 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2499 // If the tailcall address may be in a register, then make sure it's
2500 // possible to register allocate for it. In 32-bit, the call address can
2501 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2502 // callee-saved registers are restored. These happen to be the same
2503 // registers used to pass 'inreg' arguments so watch out for those.
2504 if (!Subtarget->is64Bit() &&
2505 !isa<GlobalAddressSDNode>(Callee) &&
2506 !isa<ExternalSymbolSDNode>(Callee)) {
2507 unsigned NumInRegs = 0;
2508 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2509 CCValAssign &VA = ArgLocs[i];
2512 unsigned Reg = VA.getLocReg();
2515 case X86::EAX: case X86::EDX: case X86::ECX:
2516 if (++NumInRegs == 3)
2524 // An stdcall caller is expected to clean up its arguments; the callee
2525 // isn't going to do that.
2526 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2533 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2534 return X86::createFastISel(funcInfo);
2538 //===----------------------------------------------------------------------===//
2539 // Other Lowering Hooks
2540 //===----------------------------------------------------------------------===//
2542 static bool MayFoldLoad(SDValue Op) {
2543 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2546 static bool MayFoldIntoStore(SDValue Op) {
2547 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2550 static bool isTargetShuffle(unsigned Opcode) {
2552 default: return false;
2553 case X86ISD::PSHUFD:
2554 case X86ISD::PSHUFHW:
2555 case X86ISD::PSHUFLW:
2556 case X86ISD::SHUFPD:
2557 case X86ISD::PALIGN:
2558 case X86ISD::SHUFPS:
2559 case X86ISD::MOVLHPS:
2560 case X86ISD::MOVLHPD:
2561 case X86ISD::MOVHLPS:
2562 case X86ISD::MOVLPS:
2563 case X86ISD::MOVLPD:
2564 case X86ISD::MOVSHDUP:
2565 case X86ISD::MOVSLDUP:
2566 case X86ISD::MOVDDUP:
2569 case X86ISD::UNPCKLPS:
2570 case X86ISD::UNPCKLPD:
2571 case X86ISD::PUNPCKLWD:
2572 case X86ISD::PUNPCKLBW:
2573 case X86ISD::PUNPCKLDQ:
2574 case X86ISD::PUNPCKLQDQ:
2575 case X86ISD::UNPCKHPS:
2576 case X86ISD::UNPCKHPD:
2577 case X86ISD::PUNPCKHWD:
2578 case X86ISD::PUNPCKHBW:
2579 case X86ISD::PUNPCKHDQ:
2580 case X86ISD::PUNPCKHQDQ:
2586 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2587 SDValue V1, SelectionDAG &DAG) {
2589 default: llvm_unreachable("Unknown x86 shuffle node");
2590 case X86ISD::MOVSHDUP:
2591 case X86ISD::MOVSLDUP:
2592 case X86ISD::MOVDDUP:
2593 return DAG.getNode(Opc, dl, VT, V1);
2599 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2600 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2602 default: llvm_unreachable("Unknown x86 shuffle node");
2603 case X86ISD::PSHUFD:
2604 case X86ISD::PSHUFHW:
2605 case X86ISD::PSHUFLW:
2606 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2612 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2613 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2615 default: llvm_unreachable("Unknown x86 shuffle node");
2616 case X86ISD::PALIGN:
2617 case X86ISD::SHUFPD:
2618 case X86ISD::SHUFPS:
2619 return DAG.getNode(Opc, dl, VT, V1, V2,
2620 DAG.getConstant(TargetMask, MVT::i8));
2625 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2626 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2628 default: llvm_unreachable("Unknown x86 shuffle node");
2629 case X86ISD::MOVLHPS:
2630 case X86ISD::MOVLHPD:
2631 case X86ISD::MOVHLPS:
2632 case X86ISD::MOVLPS:
2633 case X86ISD::MOVLPD:
2636 case X86ISD::UNPCKLPS:
2637 case X86ISD::UNPCKLPD:
2638 case X86ISD::PUNPCKLWD:
2639 case X86ISD::PUNPCKLBW:
2640 case X86ISD::PUNPCKLDQ:
2641 case X86ISD::PUNPCKLQDQ:
2642 case X86ISD::UNPCKHPS:
2643 case X86ISD::UNPCKHPD:
2644 case X86ISD::PUNPCKHWD:
2645 case X86ISD::PUNPCKHBW:
2646 case X86ISD::PUNPCKHDQ:
2647 case X86ISD::PUNPCKHQDQ:
2648 return DAG.getNode(Opc, dl, VT, V1, V2);
2653 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2654 MachineFunction &MF = DAG.getMachineFunction();
2655 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2656 int ReturnAddrIndex = FuncInfo->getRAIndex();
2658 if (ReturnAddrIndex == 0) {
2659 // Set up a frame object for the return address.
2660 uint64_t SlotSize = TD->getPointerSize();
2661 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2663 FuncInfo->setRAIndex(ReturnAddrIndex);
2666 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2670 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2671 bool hasSymbolicDisplacement) {
2672 // Offset should fit into 32 bit immediate field.
2673 if (!isInt<32>(Offset))
2676 // If we don't have a symbolic displacement - we don't have any extra
2678 if (!hasSymbolicDisplacement)
2681 // FIXME: Some tweaks might be needed for medium code model.
2682 if (M != CodeModel::Small && M != CodeModel::Kernel)
2685 // For small code model we assume that latest object is 16MB before end of 31
2686 // bits boundary. We may also accept pretty large negative constants knowing
2687 // that all objects are in the positive half of address space.
2688 if (M == CodeModel::Small && Offset < 16*1024*1024)
2691 // For kernel code model we know that all object resist in the negative half
2692 // of 32bits address space. We may not accept negative offsets, since they may
2693 // be just off and we may accept pretty large positive ones.
2694 if (M == CodeModel::Kernel && Offset > 0)
2700 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2701 /// specific condition code, returning the condition code and the LHS/RHS of the
2702 /// comparison to make.
2703 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2704 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2706 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2707 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2708 // X > -1 -> X == 0, jump !sign.
2709 RHS = DAG.getConstant(0, RHS.getValueType());
2710 return X86::COND_NS;
2711 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2712 // X < 0 -> X == 0, jump on sign.
2714 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2716 RHS = DAG.getConstant(0, RHS.getValueType());
2717 return X86::COND_LE;
2721 switch (SetCCOpcode) {
2722 default: llvm_unreachable("Invalid integer condition!");
2723 case ISD::SETEQ: return X86::COND_E;
2724 case ISD::SETGT: return X86::COND_G;
2725 case ISD::SETGE: return X86::COND_GE;
2726 case ISD::SETLT: return X86::COND_L;
2727 case ISD::SETLE: return X86::COND_LE;
2728 case ISD::SETNE: return X86::COND_NE;
2729 case ISD::SETULT: return X86::COND_B;
2730 case ISD::SETUGT: return X86::COND_A;
2731 case ISD::SETULE: return X86::COND_BE;
2732 case ISD::SETUGE: return X86::COND_AE;
2736 // First determine if it is required or is profitable to flip the operands.
2738 // If LHS is a foldable load, but RHS is not, flip the condition.
2739 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2740 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2741 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2742 std::swap(LHS, RHS);
2745 switch (SetCCOpcode) {
2751 std::swap(LHS, RHS);
2755 // On a floating point condition, the flags are set as follows:
2757 // 0 | 0 | 0 | X > Y
2758 // 0 | 0 | 1 | X < Y
2759 // 1 | 0 | 0 | X == Y
2760 // 1 | 1 | 1 | unordered
2761 switch (SetCCOpcode) {
2762 default: llvm_unreachable("Condcode should be pre-legalized away");
2764 case ISD::SETEQ: return X86::COND_E;
2765 case ISD::SETOLT: // flipped
2767 case ISD::SETGT: return X86::COND_A;
2768 case ISD::SETOLE: // flipped
2770 case ISD::SETGE: return X86::COND_AE;
2771 case ISD::SETUGT: // flipped
2773 case ISD::SETLT: return X86::COND_B;
2774 case ISD::SETUGE: // flipped
2776 case ISD::SETLE: return X86::COND_BE;
2778 case ISD::SETNE: return X86::COND_NE;
2779 case ISD::SETUO: return X86::COND_P;
2780 case ISD::SETO: return X86::COND_NP;
2782 case ISD::SETUNE: return X86::COND_INVALID;
2786 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2787 /// code. Current x86 isa includes the following FP cmov instructions:
2788 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2789 static bool hasFPCMov(unsigned X86CC) {
2805 /// isFPImmLegal - Returns true if the target can instruction select the
2806 /// specified FP immediate natively. If false, the legalizer will
2807 /// materialize the FP immediate as a load from a constant pool.
2808 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2809 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2810 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2816 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2817 /// the specified range (L, H].
2818 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2819 return (Val < 0) || (Val >= Low && Val < Hi);
2822 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2823 /// specified value.
2824 static bool isUndefOrEqual(int Val, int CmpVal) {
2825 if (Val < 0 || Val == CmpVal)
2830 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2831 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2832 /// the second operand.
2833 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2834 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
2835 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2836 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2837 return (Mask[0] < 2 && Mask[1] < 2);
2841 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2842 SmallVector<int, 8> M;
2844 return ::isPSHUFDMask(M, N->getValueType(0));
2847 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2848 /// is suitable for input to PSHUFHW.
2849 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2850 if (VT != MVT::v8i16)
2853 // Lower quadword copied in order or undef.
2854 for (int i = 0; i != 4; ++i)
2855 if (Mask[i] >= 0 && Mask[i] != i)
2858 // Upper quadword shuffled.
2859 for (int i = 4; i != 8; ++i)
2860 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2866 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2867 SmallVector<int, 8> M;
2869 return ::isPSHUFHWMask(M, N->getValueType(0));
2872 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2873 /// is suitable for input to PSHUFLW.
2874 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2875 if (VT != MVT::v8i16)
2878 // Upper quadword copied in order.
2879 for (int i = 4; i != 8; ++i)
2880 if (Mask[i] >= 0 && Mask[i] != i)
2883 // Lower quadword shuffled.
2884 for (int i = 0; i != 4; ++i)
2891 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2892 SmallVector<int, 8> M;
2894 return ::isPSHUFLWMask(M, N->getValueType(0));
2897 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2898 /// is suitable for input to PALIGNR.
2899 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2901 int i, e = VT.getVectorNumElements();
2903 // Do not handle v2i64 / v2f64 shuffles with palignr.
2904 if (e < 4 || !hasSSSE3)
2907 for (i = 0; i != e; ++i)
2911 // All undef, not a palignr.
2915 // Determine if it's ok to perform a palignr with only the LHS, since we
2916 // don't have access to the actual shuffle elements to see if RHS is undef.
2917 bool Unary = Mask[i] < (int)e;
2918 bool NeedsUnary = false;
2920 int s = Mask[i] - i;
2922 // Check the rest of the elements to see if they are consecutive.
2923 for (++i; i != e; ++i) {
2928 Unary = Unary && (m < (int)e);
2929 NeedsUnary = NeedsUnary || (m < s);
2931 if (NeedsUnary && !Unary)
2933 if (Unary && m != ((s+i) & (e-1)))
2935 if (!Unary && m != (s+i))
2941 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2942 SmallVector<int, 8> M;
2944 return ::isPALIGNRMask(M, N->getValueType(0), true);
2947 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2948 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2949 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2950 int NumElems = VT.getVectorNumElements();
2951 if (NumElems != 2 && NumElems != 4)
2954 int Half = NumElems / 2;
2955 for (int i = 0; i < Half; ++i)
2956 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2958 for (int i = Half; i < NumElems; ++i)
2959 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2965 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2966 SmallVector<int, 8> M;
2968 return ::isSHUFPMask(M, N->getValueType(0));
2971 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2972 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2973 /// half elements to come from vector 1 (which would equal the dest.) and
2974 /// the upper half to come from vector 2.
2975 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2976 int NumElems = VT.getVectorNumElements();
2978 if (NumElems != 2 && NumElems != 4)
2981 int Half = NumElems / 2;
2982 for (int i = 0; i < Half; ++i)
2983 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2985 for (int i = Half; i < NumElems; ++i)
2986 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2991 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2992 SmallVector<int, 8> M;
2994 return isCommutedSHUFPMask(M, N->getValueType(0));
2997 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2998 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2999 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3000 if (N->getValueType(0).getVectorNumElements() != 4)
3003 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3004 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3005 isUndefOrEqual(N->getMaskElt(1), 7) &&
3006 isUndefOrEqual(N->getMaskElt(2), 2) &&
3007 isUndefOrEqual(N->getMaskElt(3), 3);
3010 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3011 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3013 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3014 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3019 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3020 isUndefOrEqual(N->getMaskElt(1), 3) &&
3021 isUndefOrEqual(N->getMaskElt(2), 2) &&
3022 isUndefOrEqual(N->getMaskElt(3), 3);
3025 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3026 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3027 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3028 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3030 if (NumElems != 2 && NumElems != 4)
3033 for (unsigned i = 0; i < NumElems/2; ++i)
3034 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3037 for (unsigned i = NumElems/2; i < NumElems; ++i)
3038 if (!isUndefOrEqual(N->getMaskElt(i), i))
3044 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3045 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3046 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3047 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3049 if (NumElems != 2 && NumElems != 4)
3052 for (unsigned i = 0; i < NumElems/2; ++i)
3053 if (!isUndefOrEqual(N->getMaskElt(i), i))
3056 for (unsigned i = 0; i < NumElems/2; ++i)
3057 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3063 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3064 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3065 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3066 bool V2IsSplat = false) {
3067 int NumElts = VT.getVectorNumElements();
3068 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3071 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3073 int BitI1 = Mask[i+1];
3074 if (!isUndefOrEqual(BitI, j))
3077 if (!isUndefOrEqual(BitI1, NumElts))
3080 if (!isUndefOrEqual(BitI1, j + NumElts))
3087 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3088 SmallVector<int, 8> M;
3090 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3093 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3094 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3095 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3096 bool V2IsSplat = false) {
3097 int NumElts = VT.getVectorNumElements();
3098 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3101 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3103 int BitI1 = Mask[i+1];
3104 if (!isUndefOrEqual(BitI, j + NumElts/2))
3107 if (isUndefOrEqual(BitI1, NumElts))
3110 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3117 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3118 SmallVector<int, 8> M;
3120 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3123 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3124 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3126 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3127 int NumElems = VT.getVectorNumElements();
3128 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3131 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3133 int BitI1 = Mask[i+1];
3134 if (!isUndefOrEqual(BitI, j))
3136 if (!isUndefOrEqual(BitI1, j))
3142 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3143 SmallVector<int, 8> M;
3145 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3148 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3149 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3151 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3152 int NumElems = VT.getVectorNumElements();
3153 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3156 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3158 int BitI1 = Mask[i+1];
3159 if (!isUndefOrEqual(BitI, j))
3161 if (!isUndefOrEqual(BitI1, j))
3167 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3168 SmallVector<int, 8> M;
3170 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3173 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3174 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3175 /// MOVSD, and MOVD, i.e. setting the lowest element.
3176 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3177 if (VT.getVectorElementType().getSizeInBits() < 32)
3180 int NumElts = VT.getVectorNumElements();
3182 if (!isUndefOrEqual(Mask[0], NumElts))
3185 for (int i = 1; i < NumElts; ++i)
3186 if (!isUndefOrEqual(Mask[i], i))
3192 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3193 SmallVector<int, 8> M;
3195 return ::isMOVLMask(M, N->getValueType(0));
3198 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3199 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3200 /// element of vector 2 and the other elements to come from vector 1 in order.
3201 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3202 bool V2IsSplat = false, bool V2IsUndef = false) {
3203 int NumOps = VT.getVectorNumElements();
3204 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3207 if (!isUndefOrEqual(Mask[0], 0))
3210 for (int i = 1; i < NumOps; ++i)
3211 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3212 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3213 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3219 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3220 bool V2IsUndef = false) {
3221 SmallVector<int, 8> M;
3223 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3226 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3227 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3228 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3229 if (N->getValueType(0).getVectorNumElements() != 4)
3232 // Expect 1, 1, 3, 3
3233 for (unsigned i = 0; i < 2; ++i) {
3234 int Elt = N->getMaskElt(i);
3235 if (Elt >= 0 && Elt != 1)
3240 for (unsigned i = 2; i < 4; ++i) {
3241 int Elt = N->getMaskElt(i);
3242 if (Elt >= 0 && Elt != 3)
3247 // Don't use movshdup if it can be done with a shufps.
3248 // FIXME: verify that matching u, u, 3, 3 is what we want.
3252 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3253 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3254 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3255 if (N->getValueType(0).getVectorNumElements() != 4)
3258 // Expect 0, 0, 2, 2
3259 for (unsigned i = 0; i < 2; ++i)
3260 if (N->getMaskElt(i) > 0)
3264 for (unsigned i = 2; i < 4; ++i) {
3265 int Elt = N->getMaskElt(i);
3266 if (Elt >= 0 && Elt != 2)
3271 // Don't use movsldup if it can be done with a shufps.
3275 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3276 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3277 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3278 int e = N->getValueType(0).getVectorNumElements() / 2;
3280 for (int i = 0; i < e; ++i)
3281 if (!isUndefOrEqual(N->getMaskElt(i), i))
3283 for (int i = 0; i < e; ++i)
3284 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3289 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3290 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3291 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3293 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3295 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3297 for (int i = 0; i < NumOperands; ++i) {
3298 int Val = SVOp->getMaskElt(NumOperands-i-1);
3299 if (Val < 0) Val = 0;
3300 if (Val >= NumOperands) Val -= NumOperands;
3302 if (i != NumOperands - 1)
3308 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3309 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3310 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3313 // 8 nodes, but we only care about the last 4.
3314 for (unsigned i = 7; i >= 4; --i) {
3315 int Val = SVOp->getMaskElt(i);
3324 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3325 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3326 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3327 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3329 // 8 nodes, but we only care about the first 4.
3330 for (int i = 3; i >= 0; --i) {
3331 int Val = SVOp->getMaskElt(i);
3340 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3341 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3342 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3343 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3344 EVT VVT = N->getValueType(0);
3345 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3349 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3350 Val = SVOp->getMaskElt(i);
3354 return (Val - i) * EltSize;
3357 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3359 bool X86::isZeroNode(SDValue Elt) {
3360 return ((isa<ConstantSDNode>(Elt) &&
3361 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3362 (isa<ConstantFPSDNode>(Elt) &&
3363 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3366 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3367 /// their permute mask.
3368 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3369 SelectionDAG &DAG) {
3370 EVT VT = SVOp->getValueType(0);
3371 unsigned NumElems = VT.getVectorNumElements();
3372 SmallVector<int, 8> MaskVec;
3374 for (unsigned i = 0; i != NumElems; ++i) {
3375 int idx = SVOp->getMaskElt(i);
3377 MaskVec.push_back(idx);
3378 else if (idx < (int)NumElems)
3379 MaskVec.push_back(idx + NumElems);
3381 MaskVec.push_back(idx - NumElems);
3383 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3384 SVOp->getOperand(0), &MaskVec[0]);
3387 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3388 /// the two vector operands have swapped position.
3389 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3390 unsigned NumElems = VT.getVectorNumElements();
3391 for (unsigned i = 0; i != NumElems; ++i) {
3395 else if (idx < (int)NumElems)
3396 Mask[i] = idx + NumElems;
3398 Mask[i] = idx - NumElems;
3402 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3403 /// match movhlps. The lower half elements should come from upper half of
3404 /// V1 (and in order), and the upper half elements should come from the upper
3405 /// half of V2 (and in order).
3406 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3407 if (Op->getValueType(0).getVectorNumElements() != 4)
3409 for (unsigned i = 0, e = 2; i != e; ++i)
3410 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3412 for (unsigned i = 2; i != 4; ++i)
3413 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3418 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3419 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3421 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3422 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3424 N = N->getOperand(0).getNode();
3425 if (!ISD::isNON_EXTLoad(N))
3428 *LD = cast<LoadSDNode>(N);
3432 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3433 /// match movlp{s|d}. The lower half elements should come from lower half of
3434 /// V1 (and in order), and the upper half elements should come from the upper
3435 /// half of V2 (and in order). And since V1 will become the source of the
3436 /// MOVLP, it must be either a vector load or a scalar load to vector.
3437 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3438 ShuffleVectorSDNode *Op) {
3439 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3441 // Is V2 is a vector load, don't do this transformation. We will try to use
3442 // load folding shufps op.
3443 if (ISD::isNON_EXTLoad(V2))
3446 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3448 if (NumElems != 2 && NumElems != 4)
3450 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3451 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3453 for (unsigned i = NumElems/2; i != NumElems; ++i)
3454 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3459 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3461 static bool isSplatVector(SDNode *N) {
3462 if (N->getOpcode() != ISD::BUILD_VECTOR)
3465 SDValue SplatValue = N->getOperand(0);
3466 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3467 if (N->getOperand(i) != SplatValue)
3472 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3473 /// to an zero vector.
3474 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3475 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3476 SDValue V1 = N->getOperand(0);
3477 SDValue V2 = N->getOperand(1);
3478 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3479 for (unsigned i = 0; i != NumElems; ++i) {
3480 int Idx = N->getMaskElt(i);
3481 if (Idx >= (int)NumElems) {
3482 unsigned Opc = V2.getOpcode();
3483 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3485 if (Opc != ISD::BUILD_VECTOR ||
3486 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3488 } else if (Idx >= 0) {
3489 unsigned Opc = V1.getOpcode();
3490 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3492 if (Opc != ISD::BUILD_VECTOR ||
3493 !X86::isZeroNode(V1.getOperand(Idx)))
3500 /// getZeroVector - Returns a vector of specified type with all zero elements.
3502 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3504 assert(VT.isVector() && "Expected a vector type");
3506 // Always build SSE zero vectors as <4 x i32> bitcasted
3507 // to their dest type. This ensures they get CSE'd.
3509 if (VT.getSizeInBits() == 128) { // SSE
3510 if (HasSSE2) { // SSE2
3511 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3512 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3514 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3515 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3517 } else if (VT.getSizeInBits() == 256) { // AVX
3518 // 256-bit logic and arithmetic instructions in AVX are
3519 // all floating-point, no support for integer ops. Default
3520 // to emitting fp zeroed vectors then.
3521 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3522 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3523 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3525 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3528 /// getOnesVector - Returns a vector of specified type with all bits set.
3530 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3531 assert(VT.isVector() && "Expected a vector type");
3533 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3534 // type. This ensures they get CSE'd.
3535 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3537 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3538 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3542 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3543 /// that point to V2 points to its first element.
3544 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3545 EVT VT = SVOp->getValueType(0);
3546 unsigned NumElems = VT.getVectorNumElements();
3548 bool Changed = false;
3549 SmallVector<int, 8> MaskVec;
3550 SVOp->getMask(MaskVec);
3552 for (unsigned i = 0; i != NumElems; ++i) {
3553 if (MaskVec[i] > (int)NumElems) {
3554 MaskVec[i] = NumElems;
3559 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3560 SVOp->getOperand(1), &MaskVec[0]);
3561 return SDValue(SVOp, 0);
3564 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3565 /// operation of specified width.
3566 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3568 unsigned NumElems = VT.getVectorNumElements();
3569 SmallVector<int, 8> Mask;
3570 Mask.push_back(NumElems);
3571 for (unsigned i = 1; i != NumElems; ++i)
3573 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3576 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3577 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3579 unsigned NumElems = VT.getVectorNumElements();
3580 SmallVector<int, 8> Mask;
3581 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3583 Mask.push_back(i + NumElems);
3585 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3588 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3589 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3591 unsigned NumElems = VT.getVectorNumElements();
3592 unsigned Half = NumElems/2;
3593 SmallVector<int, 8> Mask;
3594 for (unsigned i = 0; i != Half; ++i) {
3595 Mask.push_back(i + Half);
3596 Mask.push_back(i + NumElems + Half);
3598 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3601 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3602 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3603 EVT PVT = MVT::v4f32;
3604 EVT VT = SV->getValueType(0);
3605 DebugLoc dl = SV->getDebugLoc();
3606 SDValue V1 = SV->getOperand(0);
3607 int NumElems = VT.getVectorNumElements();
3608 int EltNo = SV->getSplatIndex();
3610 // unpack elements to the correct location
3611 while (NumElems > 4) {
3612 if (EltNo < NumElems/2) {
3613 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3615 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3616 EltNo -= NumElems/2;
3621 // Perform the splat.
3622 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3623 V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1);
3624 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3625 return DAG.getNode(ISD::BITCAST, dl, VT, V1);
3628 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3629 /// vector of zero or undef vector. This produces a shuffle where the low
3630 /// element of V2 is swizzled into the zero/undef vector, landing at element
3631 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3632 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3633 bool isZero, bool HasSSE2,
3634 SelectionDAG &DAG) {
3635 EVT VT = V2.getValueType();
3637 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3638 unsigned NumElems = VT.getVectorNumElements();
3639 SmallVector<int, 16> MaskVec;
3640 for (unsigned i = 0; i != NumElems; ++i)
3641 // If this is the insertion idx, put the low elt of V2 here.
3642 MaskVec.push_back(i == Idx ? NumElems : i);
3643 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3646 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3647 /// element of the result of the vector shuffle.
3648 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3651 return SDValue(); // Limit search depth.
3653 SDValue V = SDValue(N, 0);
3654 EVT VT = V.getValueType();
3655 unsigned Opcode = V.getOpcode();
3657 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3658 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3659 Index = SV->getMaskElt(Index);
3662 return DAG.getUNDEF(VT.getVectorElementType());
3664 int NumElems = VT.getVectorNumElements();
3665 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3666 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3669 // Recurse into target specific vector shuffles to find scalars.
3670 if (isTargetShuffle(Opcode)) {
3671 int NumElems = VT.getVectorNumElements();
3672 SmallVector<unsigned, 16> ShuffleMask;
3676 case X86ISD::SHUFPS:
3677 case X86ISD::SHUFPD:
3678 ImmN = N->getOperand(N->getNumOperands()-1);
3679 DecodeSHUFPSMask(NumElems,
3680 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3683 case X86ISD::PUNPCKHBW:
3684 case X86ISD::PUNPCKHWD:
3685 case X86ISD::PUNPCKHDQ:
3686 case X86ISD::PUNPCKHQDQ:
3687 DecodePUNPCKHMask(NumElems, ShuffleMask);
3689 case X86ISD::UNPCKHPS:
3690 case X86ISD::UNPCKHPD:
3691 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3693 case X86ISD::PUNPCKLBW:
3694 case X86ISD::PUNPCKLWD:
3695 case X86ISD::PUNPCKLDQ:
3696 case X86ISD::PUNPCKLQDQ:
3697 DecodePUNPCKLMask(NumElems, ShuffleMask);
3699 case X86ISD::UNPCKLPS:
3700 case X86ISD::UNPCKLPD:
3701 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3703 case X86ISD::MOVHLPS:
3704 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3706 case X86ISD::MOVLHPS:
3707 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3709 case X86ISD::PSHUFD:
3710 ImmN = N->getOperand(N->getNumOperands()-1);
3711 DecodePSHUFMask(NumElems,
3712 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3715 case X86ISD::PSHUFHW:
3716 ImmN = N->getOperand(N->getNumOperands()-1);
3717 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3720 case X86ISD::PSHUFLW:
3721 ImmN = N->getOperand(N->getNumOperands()-1);
3722 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3726 case X86ISD::MOVSD: {
3727 // The index 0 always comes from the first element of the second source,
3728 // this is why MOVSS and MOVSD are used in the first place. The other
3729 // elements come from the other positions of the first source vector.
3730 unsigned OpNum = (Index == 0) ? 1 : 0;
3731 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3735 assert("not implemented for target shuffle node");
3739 Index = ShuffleMask[Index];
3741 return DAG.getUNDEF(VT.getVectorElementType());
3743 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3744 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3748 // Actual nodes that may contain scalar elements
3749 if (Opcode == ISD::BITCAST) {
3750 V = V.getOperand(0);
3751 EVT SrcVT = V.getValueType();
3752 unsigned NumElems = VT.getVectorNumElements();
3754 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3758 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3759 return (Index == 0) ? V.getOperand(0)
3760 : DAG.getUNDEF(VT.getVectorElementType());
3762 if (V.getOpcode() == ISD::BUILD_VECTOR)
3763 return V.getOperand(Index);
3768 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3769 /// shuffle operation which come from a consecutively from a zero. The
3770 /// search can start in two diferent directions, from left or right.
3772 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3773 bool ZerosFromLeft, SelectionDAG &DAG) {
3776 while (i < NumElems) {
3777 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3778 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3779 if (!(Elt.getNode() &&
3780 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3788 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3789 /// MaskE correspond consecutively to elements from one of the vector operands,
3790 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3792 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3793 int OpIdx, int NumElems, unsigned &OpNum) {
3794 bool SeenV1 = false;
3795 bool SeenV2 = false;
3797 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3798 int Idx = SVOp->getMaskElt(i);
3799 // Ignore undef indicies
3808 // Only accept consecutive elements from the same vector
3809 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3813 OpNum = SeenV1 ? 0 : 1;
3817 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3818 /// logical left shift of a vector.
3819 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3820 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3821 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3822 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3823 false /* check zeros from right */, DAG);
3829 // Considering the elements in the mask that are not consecutive zeros,
3830 // check if they consecutively come from only one of the source vectors.
3832 // V1 = {X, A, B, C} 0
3834 // vector_shuffle V1, V2 <1, 2, 3, X>
3836 if (!isShuffleMaskConsecutive(SVOp,
3837 0, // Mask Start Index
3838 NumElems-NumZeros-1, // Mask End Index
3839 NumZeros, // Where to start looking in the src vector
3840 NumElems, // Number of elements in vector
3841 OpSrc)) // Which source operand ?
3846 ShVal = SVOp->getOperand(OpSrc);
3850 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3851 /// logical left shift of a vector.
3852 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3853 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3854 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3855 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3856 true /* check zeros from left */, DAG);
3862 // Considering the elements in the mask that are not consecutive zeros,
3863 // check if they consecutively come from only one of the source vectors.
3865 // 0 { A, B, X, X } = V2
3867 // vector_shuffle V1, V2 <X, X, 4, 5>
3869 if (!isShuffleMaskConsecutive(SVOp,
3870 NumZeros, // Mask Start Index
3871 NumElems-1, // Mask End Index
3872 0, // Where to start looking in the src vector
3873 NumElems, // Number of elements in vector
3874 OpSrc)) // Which source operand ?
3879 ShVal = SVOp->getOperand(OpSrc);
3883 /// isVectorShift - Returns true if the shuffle can be implemented as a
3884 /// logical left or right shift of a vector.
3885 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3886 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3887 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3888 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3894 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3896 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3897 unsigned NumNonZero, unsigned NumZero,
3899 const TargetLowering &TLI) {
3903 DebugLoc dl = Op.getDebugLoc();
3906 for (unsigned i = 0; i < 16; ++i) {
3907 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3908 if (ThisIsNonZero && First) {
3910 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3912 V = DAG.getUNDEF(MVT::v8i16);
3917 SDValue ThisElt(0, 0), LastElt(0, 0);
3918 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3919 if (LastIsNonZero) {
3920 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3921 MVT::i16, Op.getOperand(i-1));
3923 if (ThisIsNonZero) {
3924 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3925 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3926 ThisElt, DAG.getConstant(8, MVT::i8));
3928 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3932 if (ThisElt.getNode())
3933 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3934 DAG.getIntPtrConstant(i/2));
3938 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
3941 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3943 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3944 unsigned NumNonZero, unsigned NumZero,
3946 const TargetLowering &TLI) {
3950 DebugLoc dl = Op.getDebugLoc();
3953 for (unsigned i = 0; i < 8; ++i) {
3954 bool isNonZero = (NonZeros & (1 << i)) != 0;
3958 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3960 V = DAG.getUNDEF(MVT::v8i16);
3963 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3964 MVT::v8i16, V, Op.getOperand(i),
3965 DAG.getIntPtrConstant(i));
3972 /// getVShift - Return a vector logical shift node.
3974 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3975 unsigned NumBits, SelectionDAG &DAG,
3976 const TargetLowering &TLI, DebugLoc dl) {
3977 EVT ShVT = MVT::v2i64;
3978 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3979 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
3980 return DAG.getNode(ISD::BITCAST, dl, VT,
3981 DAG.getNode(Opc, dl, ShVT, SrcOp,
3982 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3986 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3987 SelectionDAG &DAG) const {
3989 // Check if the scalar load can be widened into a vector load. And if
3990 // the address is "base + cst" see if the cst can be "absorbed" into
3991 // the shuffle mask.
3992 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3993 SDValue Ptr = LD->getBasePtr();
3994 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3996 EVT PVT = LD->getValueType(0);
3997 if (PVT != MVT::i32 && PVT != MVT::f32)
4002 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4003 FI = FINode->getIndex();
4005 } else if (Ptr.getOpcode() == ISD::ADD &&
4006 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4007 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4008 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4009 Offset = Ptr.getConstantOperandVal(1);
4010 Ptr = Ptr.getOperand(0);
4015 SDValue Chain = LD->getChain();
4016 // Make sure the stack object alignment is at least 16.
4017 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4018 if (DAG.InferPtrAlignment(Ptr) < 16) {
4019 if (MFI->isFixedObjectIndex(FI)) {
4020 // Can't change the alignment. FIXME: It's possible to compute
4021 // the exact stack offset and reference FI + adjust offset instead.
4022 // If someone *really* cares about this. That's the way to implement it.
4025 MFI->setObjectAlignment(FI, 16);
4029 // (Offset % 16) must be multiple of 4. Then address is then
4030 // Ptr + (Offset & ~15).
4033 if ((Offset % 16) & 3)
4035 int64_t StartOffset = Offset & ~15;
4037 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4038 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4040 int EltNo = (Offset - StartOffset) >> 2;
4041 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4042 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4043 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4044 LD->getPointerInfo().getWithOffset(StartOffset),
4046 // Canonicalize it to a v4i32 shuffle.
4047 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
4048 return DAG.getNode(ISD::BITCAST, dl, VT,
4049 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4050 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4056 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4057 /// vector of type 'VT', see if the elements can be replaced by a single large
4058 /// load which has the same value as a build_vector whose operands are 'elts'.
4060 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4062 /// FIXME: we'd also like to handle the case where the last elements are zero
4063 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4064 /// There's even a handy isZeroNode for that purpose.
4065 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4066 DebugLoc &DL, SelectionDAG &DAG) {
4067 EVT EltVT = VT.getVectorElementType();
4068 unsigned NumElems = Elts.size();
4070 LoadSDNode *LDBase = NULL;
4071 unsigned LastLoadedElt = -1U;
4073 // For each element in the initializer, see if we've found a load or an undef.
4074 // If we don't find an initial load element, or later load elements are
4075 // non-consecutive, bail out.
4076 for (unsigned i = 0; i < NumElems; ++i) {
4077 SDValue Elt = Elts[i];
4079 if (!Elt.getNode() ||
4080 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4083 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4085 LDBase = cast<LoadSDNode>(Elt.getNode());
4089 if (Elt.getOpcode() == ISD::UNDEF)
4092 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4093 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4098 // If we have found an entire vector of loads and undefs, then return a large
4099 // load of the entire vector width starting at the base pointer. If we found
4100 // consecutive loads for the low half, generate a vzext_load node.
4101 if (LastLoadedElt == NumElems - 1) {
4102 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4103 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4104 LDBase->getPointerInfo(),
4105 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4106 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4107 LDBase->getPointerInfo(),
4108 LDBase->isVolatile(), LDBase->isNonTemporal(),
4109 LDBase->getAlignment());
4110 } else if (NumElems == 4 && LastLoadedElt == 1) {
4111 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4112 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4113 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4115 LDBase->getMemOperand());
4116 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4122 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4123 DebugLoc dl = Op.getDebugLoc();
4124 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4125 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4126 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4127 // is present, so AllOnes is ignored.
4128 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4129 (Op.getValueType().getSizeInBits() != 256 &&
4130 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4131 // Canonicalize this to <4 x i32> (SSE) to
4132 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4133 // eliminated on x86-32 hosts.
4134 if (Op.getValueType() == MVT::v4i32)
4137 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4138 return getOnesVector(Op.getValueType(), DAG, dl);
4139 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4142 EVT VT = Op.getValueType();
4143 EVT ExtVT = VT.getVectorElementType();
4144 unsigned EVTBits = ExtVT.getSizeInBits();
4146 unsigned NumElems = Op.getNumOperands();
4147 unsigned NumZero = 0;
4148 unsigned NumNonZero = 0;
4149 unsigned NonZeros = 0;
4150 bool IsAllConstants = true;
4151 SmallSet<SDValue, 8> Values;
4152 for (unsigned i = 0; i < NumElems; ++i) {
4153 SDValue Elt = Op.getOperand(i);
4154 if (Elt.getOpcode() == ISD::UNDEF)
4157 if (Elt.getOpcode() != ISD::Constant &&
4158 Elt.getOpcode() != ISD::ConstantFP)
4159 IsAllConstants = false;
4160 if (X86::isZeroNode(Elt))
4163 NonZeros |= (1 << i);
4168 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4169 if (NumNonZero == 0)
4170 return DAG.getUNDEF(VT);
4172 // Special case for single non-zero, non-undef, element.
4173 if (NumNonZero == 1) {
4174 unsigned Idx = CountTrailingZeros_32(NonZeros);
4175 SDValue Item = Op.getOperand(Idx);
4177 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4178 // the value are obviously zero, truncate the value to i32 and do the
4179 // insertion that way. Only do this if the value is non-constant or if the
4180 // value is a constant being inserted into element 0. It is cheaper to do
4181 // a constant pool load than it is to do a movd + shuffle.
4182 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4183 (!IsAllConstants || Idx == 0)) {
4184 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4186 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4187 EVT VecVT = MVT::v4i32;
4188 unsigned VecElts = 4;
4190 // Truncate the value (which may itself be a constant) to i32, and
4191 // convert it to a vector with movd (S2V+shuffle to zero extend).
4192 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4193 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4194 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4195 Subtarget->hasSSE2(), DAG);
4197 // Now we have our 32-bit value zero extended in the low element of
4198 // a vector. If Idx != 0, swizzle it into place.
4200 SmallVector<int, 4> Mask;
4201 Mask.push_back(Idx);
4202 for (unsigned i = 1; i != VecElts; ++i)
4204 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4205 DAG.getUNDEF(Item.getValueType()),
4208 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4212 // If we have a constant or non-constant insertion into the low element of
4213 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4214 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4215 // depending on what the source datatype is.
4218 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4219 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4220 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4221 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4222 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4223 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4225 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4226 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4227 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4228 EVT MiddleVT = MVT::v4i32;
4229 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4230 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4231 Subtarget->hasSSE2(), DAG);
4232 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4236 // Is it a vector logical left shift?
4237 if (NumElems == 2 && Idx == 1 &&
4238 X86::isZeroNode(Op.getOperand(0)) &&
4239 !X86::isZeroNode(Op.getOperand(1))) {
4240 unsigned NumBits = VT.getSizeInBits();
4241 return getVShift(true, VT,
4242 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4243 VT, Op.getOperand(1)),
4244 NumBits/2, DAG, *this, dl);
4247 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4250 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4251 // is a non-constant being inserted into an element other than the low one,
4252 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4253 // movd/movss) to move this into the low element, then shuffle it into
4255 if (EVTBits == 32) {
4256 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4258 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4259 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4260 Subtarget->hasSSE2(), DAG);
4261 SmallVector<int, 8> MaskVec;
4262 for (unsigned i = 0; i < NumElems; i++)
4263 MaskVec.push_back(i == Idx ? 0 : 1);
4264 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4268 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4269 if (Values.size() == 1) {
4270 if (EVTBits == 32) {
4271 // Instead of a shuffle like this:
4272 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4273 // Check if it's possible to issue this instead.
4274 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4275 unsigned Idx = CountTrailingZeros_32(NonZeros);
4276 SDValue Item = Op.getOperand(Idx);
4277 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4278 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4283 // A vector full of immediates; various special cases are already
4284 // handled, so this is best done with a single constant-pool load.
4288 // Let legalizer expand 2-wide build_vectors.
4289 if (EVTBits == 64) {
4290 if (NumNonZero == 1) {
4291 // One half is zero or undef.
4292 unsigned Idx = CountTrailingZeros_32(NonZeros);
4293 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4294 Op.getOperand(Idx));
4295 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4296 Subtarget->hasSSE2(), DAG);
4301 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4302 if (EVTBits == 8 && NumElems == 16) {
4303 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4305 if (V.getNode()) return V;
4308 if (EVTBits == 16 && NumElems == 8) {
4309 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4311 if (V.getNode()) return V;
4314 // If element VT is == 32 bits, turn it into a number of shuffles.
4315 SmallVector<SDValue, 8> V;
4317 if (NumElems == 4 && NumZero > 0) {
4318 for (unsigned i = 0; i < 4; ++i) {
4319 bool isZero = !(NonZeros & (1 << i));
4321 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4323 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4326 for (unsigned i = 0; i < 2; ++i) {
4327 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4330 V[i] = V[i*2]; // Must be a zero vector.
4333 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4336 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4339 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4344 SmallVector<int, 8> MaskVec;
4345 bool Reverse = (NonZeros & 0x3) == 2;
4346 for (unsigned i = 0; i < 2; ++i)
4347 MaskVec.push_back(Reverse ? 1-i : i);
4348 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4349 for (unsigned i = 0; i < 2; ++i)
4350 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4351 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4354 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4355 // Check for a build vector of consecutive loads.
4356 for (unsigned i = 0; i < NumElems; ++i)
4357 V[i] = Op.getOperand(i);
4359 // Check for elements which are consecutive loads.
4360 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4364 // For SSE 4.1, use insertps to put the high elements into the low element.
4365 if (getSubtarget()->hasSSE41()) {
4367 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4368 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4370 Result = DAG.getUNDEF(VT);
4372 for (unsigned i = 1; i < NumElems; ++i) {
4373 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4374 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4375 Op.getOperand(i), DAG.getIntPtrConstant(i));
4380 // Otherwise, expand into a number of unpckl*, start by extending each of
4381 // our (non-undef) elements to the full vector width with the element in the
4382 // bottom slot of the vector (which generates no code for SSE).
4383 for (unsigned i = 0; i < NumElems; ++i) {
4384 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4385 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4387 V[i] = DAG.getUNDEF(VT);
4390 // Next, we iteratively mix elements, e.g. for v4f32:
4391 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4392 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4393 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4394 unsigned EltStride = NumElems >> 1;
4395 while (EltStride != 0) {
4396 for (unsigned i = 0; i < EltStride; ++i) {
4397 // If V[i+EltStride] is undef and this is the first round of mixing,
4398 // then it is safe to just drop this shuffle: V[i] is already in the
4399 // right place, the one element (since it's the first round) being
4400 // inserted as undef can be dropped. This isn't safe for successive
4401 // rounds because they will permute elements within both vectors.
4402 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4403 EltStride == NumElems/2)
4406 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4416 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4417 // We support concatenate two MMX registers and place them in a MMX
4418 // register. This is better than doing a stack convert.
4419 DebugLoc dl = Op.getDebugLoc();
4420 EVT ResVT = Op.getValueType();
4421 assert(Op.getNumOperands() == 2);
4422 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4423 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4425 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
4426 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4427 InVec = Op.getOperand(1);
4428 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4429 unsigned NumElts = ResVT.getVectorNumElements();
4430 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4431 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4432 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4434 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
4435 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4436 Mask[0] = 0; Mask[1] = 2;
4437 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4439 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4442 // v8i16 shuffles - Prefer shuffles in the following order:
4443 // 1. [all] pshuflw, pshufhw, optional move
4444 // 2. [ssse3] 1 x pshufb
4445 // 3. [ssse3] 2 x pshufb + 1 x por
4446 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4448 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4449 SelectionDAG &DAG) const {
4450 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4451 SDValue V1 = SVOp->getOperand(0);
4452 SDValue V2 = SVOp->getOperand(1);
4453 DebugLoc dl = SVOp->getDebugLoc();
4454 SmallVector<int, 8> MaskVals;
4456 // Determine if more than 1 of the words in each of the low and high quadwords
4457 // of the result come from the same quadword of one of the two inputs. Undef
4458 // mask values count as coming from any quadword, for better codegen.
4459 SmallVector<unsigned, 4> LoQuad(4);
4460 SmallVector<unsigned, 4> HiQuad(4);
4461 BitVector InputQuads(4);
4462 for (unsigned i = 0; i < 8; ++i) {
4463 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4464 int EltIdx = SVOp->getMaskElt(i);
4465 MaskVals.push_back(EltIdx);
4474 InputQuads.set(EltIdx / 4);
4477 int BestLoQuad = -1;
4478 unsigned MaxQuad = 1;
4479 for (unsigned i = 0; i < 4; ++i) {
4480 if (LoQuad[i] > MaxQuad) {
4482 MaxQuad = LoQuad[i];
4486 int BestHiQuad = -1;
4488 for (unsigned i = 0; i < 4; ++i) {
4489 if (HiQuad[i] > MaxQuad) {
4491 MaxQuad = HiQuad[i];
4495 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4496 // of the two input vectors, shuffle them into one input vector so only a
4497 // single pshufb instruction is necessary. If There are more than 2 input
4498 // quads, disable the next transformation since it does not help SSSE3.
4499 bool V1Used = InputQuads[0] || InputQuads[1];
4500 bool V2Used = InputQuads[2] || InputQuads[3];
4501 if (Subtarget->hasSSSE3()) {
4502 if (InputQuads.count() == 2 && V1Used && V2Used) {
4503 BestLoQuad = InputQuads.find_first();
4504 BestHiQuad = InputQuads.find_next(BestLoQuad);
4506 if (InputQuads.count() > 2) {
4512 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4513 // the shuffle mask. If a quad is scored as -1, that means that it contains
4514 // words from all 4 input quadwords.
4516 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4517 SmallVector<int, 8> MaskV;
4518 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4519 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4520 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4521 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
4522 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
4523 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
4525 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4526 // source words for the shuffle, to aid later transformations.
4527 bool AllWordsInNewV = true;
4528 bool InOrder[2] = { true, true };
4529 for (unsigned i = 0; i != 8; ++i) {
4530 int idx = MaskVals[i];
4532 InOrder[i/4] = false;
4533 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4535 AllWordsInNewV = false;
4539 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4540 if (AllWordsInNewV) {
4541 for (int i = 0; i != 8; ++i) {
4542 int idx = MaskVals[i];
4545 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4546 if ((idx != i) && idx < 4)
4548 if ((idx != i) && idx > 3)
4557 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4558 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4559 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4560 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4561 unsigned TargetMask = 0;
4562 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4563 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4564 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4565 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4566 V1 = NewV.getOperand(0);
4567 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4571 // If we have SSSE3, and all words of the result are from 1 input vector,
4572 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4573 // is present, fall back to case 4.
4574 if (Subtarget->hasSSSE3()) {
4575 SmallVector<SDValue,16> pshufbMask;
4577 // If we have elements from both input vectors, set the high bit of the
4578 // shuffle mask element to zero out elements that come from V2 in the V1
4579 // mask, and elements that come from V1 in the V2 mask, so that the two
4580 // results can be OR'd together.
4581 bool TwoInputs = V1Used && V2Used;
4582 for (unsigned i = 0; i != 8; ++i) {
4583 int EltIdx = MaskVals[i] * 2;
4584 if (TwoInputs && (EltIdx >= 16)) {
4585 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4586 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4589 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4590 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4592 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
4593 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4594 DAG.getNode(ISD::BUILD_VECTOR, dl,
4595 MVT::v16i8, &pshufbMask[0], 16));
4597 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4599 // Calculate the shuffle mask for the second input, shuffle it, and
4600 // OR it with the first shuffled input.
4602 for (unsigned i = 0; i != 8; ++i) {
4603 int EltIdx = MaskVals[i] * 2;
4605 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4606 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4609 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4610 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4612 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
4613 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4614 DAG.getNode(ISD::BUILD_VECTOR, dl,
4615 MVT::v16i8, &pshufbMask[0], 16));
4616 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4617 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4620 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4621 // and update MaskVals with new element order.
4622 BitVector InOrder(8);
4623 if (BestLoQuad >= 0) {
4624 SmallVector<int, 8> MaskV;
4625 for (int i = 0; i != 4; ++i) {
4626 int idx = MaskVals[i];
4628 MaskV.push_back(-1);
4630 } else if ((idx / 4) == BestLoQuad) {
4631 MaskV.push_back(idx & 3);
4634 MaskV.push_back(-1);
4637 for (unsigned i = 4; i != 8; ++i)
4639 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4642 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4643 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4645 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4649 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4650 // and update MaskVals with the new element order.
4651 if (BestHiQuad >= 0) {
4652 SmallVector<int, 8> MaskV;
4653 for (unsigned i = 0; i != 4; ++i)
4655 for (unsigned i = 4; i != 8; ++i) {
4656 int idx = MaskVals[i];
4658 MaskV.push_back(-1);
4660 } else if ((idx / 4) == BestHiQuad) {
4661 MaskV.push_back((idx & 3) + 4);
4664 MaskV.push_back(-1);
4667 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4670 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4671 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4673 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4677 // In case BestHi & BestLo were both -1, which means each quadword has a word
4678 // from each of the four input quadwords, calculate the InOrder bitvector now
4679 // before falling through to the insert/extract cleanup.
4680 if (BestLoQuad == -1 && BestHiQuad == -1) {
4682 for (int i = 0; i != 8; ++i)
4683 if (MaskVals[i] < 0 || MaskVals[i] == i)
4687 // The other elements are put in the right place using pextrw and pinsrw.
4688 for (unsigned i = 0; i != 8; ++i) {
4691 int EltIdx = MaskVals[i];
4694 SDValue ExtOp = (EltIdx < 8)
4695 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4696 DAG.getIntPtrConstant(EltIdx))
4697 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4698 DAG.getIntPtrConstant(EltIdx - 8));
4699 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4700 DAG.getIntPtrConstant(i));
4705 // v16i8 shuffles - Prefer shuffles in the following order:
4706 // 1. [ssse3] 1 x pshufb
4707 // 2. [ssse3] 2 x pshufb + 1 x por
4708 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4710 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4712 const X86TargetLowering &TLI) {
4713 SDValue V1 = SVOp->getOperand(0);
4714 SDValue V2 = SVOp->getOperand(1);
4715 DebugLoc dl = SVOp->getDebugLoc();
4716 SmallVector<int, 16> MaskVals;
4717 SVOp->getMask(MaskVals);
4719 // If we have SSSE3, case 1 is generated when all result bytes come from
4720 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4721 // present, fall back to case 3.
4722 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4725 for (unsigned i = 0; i < 16; ++i) {
4726 int EltIdx = MaskVals[i];
4735 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4736 if (TLI.getSubtarget()->hasSSSE3()) {
4737 SmallVector<SDValue,16> pshufbMask;
4739 // If all result elements are from one input vector, then only translate
4740 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4742 // Otherwise, we have elements from both input vectors, and must zero out
4743 // elements that come from V2 in the first mask, and V1 in the second mask
4744 // so that we can OR them together.
4745 bool TwoInputs = !(V1Only || V2Only);
4746 for (unsigned i = 0; i != 16; ++i) {
4747 int EltIdx = MaskVals[i];
4748 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4749 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4752 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4754 // If all the elements are from V2, assign it to V1 and return after
4755 // building the first pshufb.
4758 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4759 DAG.getNode(ISD::BUILD_VECTOR, dl,
4760 MVT::v16i8, &pshufbMask[0], 16));
4764 // Calculate the shuffle mask for the second input, shuffle it, and
4765 // OR it with the first shuffled input.
4767 for (unsigned i = 0; i != 16; ++i) {
4768 int EltIdx = MaskVals[i];
4770 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4773 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4775 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4776 DAG.getNode(ISD::BUILD_VECTOR, dl,
4777 MVT::v16i8, &pshufbMask[0], 16));
4778 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4781 // No SSSE3 - Calculate in place words and then fix all out of place words
4782 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4783 // the 16 different words that comprise the two doublequadword input vectors.
4784 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4785 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
4786 SDValue NewV = V2Only ? V2 : V1;
4787 for (int i = 0; i != 8; ++i) {
4788 int Elt0 = MaskVals[i*2];
4789 int Elt1 = MaskVals[i*2+1];
4791 // This word of the result is all undef, skip it.
4792 if (Elt0 < 0 && Elt1 < 0)
4795 // This word of the result is already in the correct place, skip it.
4796 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4798 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4801 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4802 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4805 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4806 // using a single extract together, load it and store it.
4807 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4808 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4809 DAG.getIntPtrConstant(Elt1 / 2));
4810 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4811 DAG.getIntPtrConstant(i));
4815 // If Elt1 is defined, extract it from the appropriate source. If the
4816 // source byte is not also odd, shift the extracted word left 8 bits
4817 // otherwise clear the bottom 8 bits if we need to do an or.
4819 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4820 DAG.getIntPtrConstant(Elt1 / 2));
4821 if ((Elt1 & 1) == 0)
4822 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4823 DAG.getConstant(8, TLI.getShiftAmountTy()));
4825 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4826 DAG.getConstant(0xFF00, MVT::i16));
4828 // If Elt0 is defined, extract it from the appropriate source. If the
4829 // source byte is not also even, shift the extracted word right 8 bits. If
4830 // Elt1 was also defined, OR the extracted values together before
4831 // inserting them in the result.
4833 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4834 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4835 if ((Elt0 & 1) != 0)
4836 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4837 DAG.getConstant(8, TLI.getShiftAmountTy()));
4839 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4840 DAG.getConstant(0x00FF, MVT::i16));
4841 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4844 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4845 DAG.getIntPtrConstant(i));
4847 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
4850 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4851 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
4852 /// done when every pair / quad of shuffle mask elements point to elements in
4853 /// the right sequence. e.g.
4854 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
4856 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4857 SelectionDAG &DAG, DebugLoc dl) {
4858 EVT VT = SVOp->getValueType(0);
4859 SDValue V1 = SVOp->getOperand(0);
4860 SDValue V2 = SVOp->getOperand(1);
4861 unsigned NumElems = VT.getVectorNumElements();
4862 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4864 switch (VT.getSimpleVT().SimpleTy) {
4865 default: assert(false && "Unexpected!");
4866 case MVT::v4f32: NewVT = MVT::v2f64; break;
4867 case MVT::v4i32: NewVT = MVT::v2i64; break;
4868 case MVT::v8i16: NewVT = MVT::v4i32; break;
4869 case MVT::v16i8: NewVT = MVT::v4i32; break;
4872 int Scale = NumElems / NewWidth;
4873 SmallVector<int, 8> MaskVec;
4874 for (unsigned i = 0; i < NumElems; i += Scale) {
4876 for (int j = 0; j < Scale; ++j) {
4877 int EltIdx = SVOp->getMaskElt(i+j);
4881 StartIdx = EltIdx - (EltIdx % Scale);
4882 if (EltIdx != StartIdx + j)
4886 MaskVec.push_back(-1);
4888 MaskVec.push_back(StartIdx / Scale);
4891 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
4892 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
4893 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4896 /// getVZextMovL - Return a zero-extending vector move low node.
4898 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4899 SDValue SrcOp, SelectionDAG &DAG,
4900 const X86Subtarget *Subtarget, DebugLoc dl) {
4901 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4902 LoadSDNode *LD = NULL;
4903 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4904 LD = dyn_cast<LoadSDNode>(SrcOp);
4906 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4908 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4909 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
4910 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4911 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
4912 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4914 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4915 return DAG.getNode(ISD::BITCAST, dl, VT,
4916 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4917 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4925 return DAG.getNode(ISD::BITCAST, dl, VT,
4926 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4927 DAG.getNode(ISD::BITCAST, dl,
4931 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4934 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4935 SDValue V1 = SVOp->getOperand(0);
4936 SDValue V2 = SVOp->getOperand(1);
4937 DebugLoc dl = SVOp->getDebugLoc();
4938 EVT VT = SVOp->getValueType(0);
4940 SmallVector<std::pair<int, int>, 8> Locs;
4942 SmallVector<int, 8> Mask1(4U, -1);
4943 SmallVector<int, 8> PermMask;
4944 SVOp->getMask(PermMask);
4948 for (unsigned i = 0; i != 4; ++i) {
4949 int Idx = PermMask[i];
4951 Locs[i] = std::make_pair(-1, -1);
4953 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4955 Locs[i] = std::make_pair(0, NumLo);
4959 Locs[i] = std::make_pair(1, NumHi);
4961 Mask1[2+NumHi] = Idx;
4967 if (NumLo <= 2 && NumHi <= 2) {
4968 // If no more than two elements come from either vector. This can be
4969 // implemented with two shuffles. First shuffle gather the elements.
4970 // The second shuffle, which takes the first shuffle as both of its
4971 // vector operands, put the elements into the right order.
4972 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4974 SmallVector<int, 8> Mask2(4U, -1);
4976 for (unsigned i = 0; i != 4; ++i) {
4977 if (Locs[i].first == -1)
4980 unsigned Idx = (i < 2) ? 0 : 4;
4981 Idx += Locs[i].first * 2 + Locs[i].second;
4986 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4987 } else if (NumLo == 3 || NumHi == 3) {
4988 // Otherwise, we must have three elements from one vector, call it X, and
4989 // one element from the other, call it Y. First, use a shufps to build an
4990 // intermediate vector with the one element from Y and the element from X
4991 // that will be in the same half in the final destination (the indexes don't
4992 // matter). Then, use a shufps to build the final vector, taking the half
4993 // containing the element from Y from the intermediate, and the other half
4996 // Normalize it so the 3 elements come from V1.
4997 CommuteVectorShuffleMask(PermMask, VT);
5001 // Find the element from V2.
5003 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5004 int Val = PermMask[HiIndex];
5011 Mask1[0] = PermMask[HiIndex];
5013 Mask1[2] = PermMask[HiIndex^1];
5015 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5018 Mask1[0] = PermMask[0];
5019 Mask1[1] = PermMask[1];
5020 Mask1[2] = HiIndex & 1 ? 6 : 4;
5021 Mask1[3] = HiIndex & 1 ? 4 : 6;
5022 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5024 Mask1[0] = HiIndex & 1 ? 2 : 0;
5025 Mask1[1] = HiIndex & 1 ? 0 : 2;
5026 Mask1[2] = PermMask[2];
5027 Mask1[3] = PermMask[3];
5032 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5036 // Break it into (shuffle shuffle_hi, shuffle_lo).
5038 SmallVector<int,8> LoMask(4U, -1);
5039 SmallVector<int,8> HiMask(4U, -1);
5041 SmallVector<int,8> *MaskPtr = &LoMask;
5042 unsigned MaskIdx = 0;
5045 for (unsigned i = 0; i != 4; ++i) {
5052 int Idx = PermMask[i];
5054 Locs[i] = std::make_pair(-1, -1);
5055 } else if (Idx < 4) {
5056 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5057 (*MaskPtr)[LoIdx] = Idx;
5060 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5061 (*MaskPtr)[HiIdx] = Idx;
5066 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5067 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5068 SmallVector<int, 8> MaskOps;
5069 for (unsigned i = 0; i != 4; ++i) {
5070 if (Locs[i].first == -1) {
5071 MaskOps.push_back(-1);
5073 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5074 MaskOps.push_back(Idx);
5077 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5080 static bool MayFoldVectorLoad(SDValue V) {
5081 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5082 V = V.getOperand(0);
5083 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5084 V = V.getOperand(0);
5090 // FIXME: the version above should always be used. Since there's
5091 // a bug where several vector shuffles can't be folded because the
5092 // DAG is not updated during lowering and a node claims to have two
5093 // uses while it only has one, use this version, and let isel match
5094 // another instruction if the load really happens to have more than
5095 // one use. Remove this version after this bug get fixed.
5096 // rdar://8434668, PR8156
5097 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5098 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5099 V = V.getOperand(0);
5100 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5101 V = V.getOperand(0);
5102 if (ISD::isNormalLoad(V.getNode()))
5107 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5108 /// a vector extract, and if both can be later optimized into a single load.
5109 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5110 /// here because otherwise a target specific shuffle node is going to be
5111 /// emitted for this shuffle, and the optimization not done.
5112 /// FIXME: This is probably not the best approach, but fix the problem
5113 /// until the right path is decided.
5115 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5116 const TargetLowering &TLI) {
5117 EVT VT = V.getValueType();
5118 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5120 // Be sure that the vector shuffle is present in a pattern like this:
5121 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5125 SDNode *N = *V.getNode()->use_begin();
5126 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5129 SDValue EltNo = N->getOperand(1);
5130 if (!isa<ConstantSDNode>(EltNo))
5133 // If the bit convert changed the number of elements, it is unsafe
5134 // to examine the mask.
5135 bool HasShuffleIntoBitcast = false;
5136 if (V.getOpcode() == ISD::BITCAST) {
5137 EVT SrcVT = V.getOperand(0).getValueType();
5138 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5140 V = V.getOperand(0);
5141 HasShuffleIntoBitcast = true;
5144 // Select the input vector, guarding against out of range extract vector.
5145 unsigned NumElems = VT.getVectorNumElements();
5146 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5147 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5148 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5150 // Skip one more bit_convert if necessary
5151 if (V.getOpcode() == ISD::BITCAST)
5152 V = V.getOperand(0);
5154 if (ISD::isNormalLoad(V.getNode())) {
5155 // Is the original load suitable?
5156 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5158 // FIXME: avoid the multi-use bug that is preventing lots of
5159 // of foldings to be detected, this is still wrong of course, but
5160 // give the temporary desired behavior, and if it happens that
5161 // the load has real more uses, during isel it will not fold, and
5162 // will generate poor code.
5163 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5166 if (!HasShuffleIntoBitcast)
5169 // If there's a bitcast before the shuffle, check if the load type and
5170 // alignment is valid.
5171 unsigned Align = LN0->getAlignment();
5173 TLI.getTargetData()->getABITypeAlignment(
5174 VT.getTypeForEVT(*DAG.getContext()));
5176 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5184 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5185 EVT VT = Op.getValueType();
5187 // Canonizalize to v2f64.
5188 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
5189 return DAG.getNode(ISD::BITCAST, dl, VT,
5190 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5195 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5197 SDValue V1 = Op.getOperand(0);
5198 SDValue V2 = Op.getOperand(1);
5199 EVT VT = Op.getValueType();
5201 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5203 if (HasSSE2 && VT == MVT::v2f64)
5204 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5207 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5211 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5212 SDValue V1 = Op.getOperand(0);
5213 SDValue V2 = Op.getOperand(1);
5214 EVT VT = Op.getValueType();
5216 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5217 "unsupported shuffle type");
5219 if (V2.getOpcode() == ISD::UNDEF)
5223 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5227 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5228 SDValue V1 = Op.getOperand(0);
5229 SDValue V2 = Op.getOperand(1);
5230 EVT VT = Op.getValueType();
5231 unsigned NumElems = VT.getVectorNumElements();
5233 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5234 // operand of these instructions is only memory, so check if there's a
5235 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5237 bool CanFoldLoad = false;
5239 // Trivial case, when V2 comes from a load.
5240 if (MayFoldVectorLoad(V2))
5243 // When V1 is a load, it can be folded later into a store in isel, example:
5244 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5246 // (MOVLPSmr addr:$src1, VR128:$src2)
5247 // So, recognize this potential and also use MOVLPS or MOVLPD
5248 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5252 if (HasSSE2 && NumElems == 2)
5253 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5256 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5259 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5260 // movl and movlp will both match v2i64, but v2i64 is never matched by
5261 // movl earlier because we make it strict to avoid messing with the movlp load
5262 // folding logic (see the code above getMOVLP call). Match it here then,
5263 // this is horrible, but will stay like this until we move all shuffle
5264 // matching to x86 specific nodes. Note that for the 1st condition all
5265 // types are matched with movsd.
5266 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5267 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5269 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5272 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5274 // Invert the operand order and use SHUFPS to match it.
5275 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5276 X86::getShuffleSHUFImmediate(SVOp), DAG);
5279 static inline unsigned getUNPCKLOpcode(EVT VT) {
5280 switch(VT.getSimpleVT().SimpleTy) {
5281 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5282 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5283 case MVT::v4f32: return X86ISD::UNPCKLPS;
5284 case MVT::v2f64: return X86ISD::UNPCKLPD;
5285 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5286 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5288 llvm_unreachable("Unknow type for unpckl");
5293 static inline unsigned getUNPCKHOpcode(EVT VT) {
5294 switch(VT.getSimpleVT().SimpleTy) {
5295 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5296 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5297 case MVT::v4f32: return X86ISD::UNPCKHPS;
5298 case MVT::v2f64: return X86ISD::UNPCKHPD;
5299 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5300 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5302 llvm_unreachable("Unknow type for unpckh");
5308 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5309 const TargetLowering &TLI,
5310 const X86Subtarget *Subtarget) {
5311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5312 EVT VT = Op.getValueType();
5313 DebugLoc dl = Op.getDebugLoc();
5314 SDValue V1 = Op.getOperand(0);
5315 SDValue V2 = Op.getOperand(1);
5317 if (isZeroShuffle(SVOp))
5318 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5320 // Handle splat operations
5321 if (SVOp->isSplat()) {
5322 // Special case, this is the only place now where it's
5323 // allowed to return a vector_shuffle operation without
5324 // using a target specific node, because *hopefully* it
5325 // will be optimized away by the dag combiner.
5326 if (VT.getVectorNumElements() <= 4 &&
5327 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5330 // Handle splats by matching through known masks
5331 if (VT.getVectorNumElements() <= 4)
5334 // Canonicalize all of the remaining to v4f32.
5335 return PromoteSplat(SVOp, DAG);
5338 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5340 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5341 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5342 if (NewOp.getNode())
5343 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
5344 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5345 // FIXME: Figure out a cleaner way to do this.
5346 // Try to make use of movq to zero out the top part.
5347 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5348 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5349 if (NewOp.getNode()) {
5350 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5351 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5352 DAG, Subtarget, dl);
5354 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5355 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5356 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5357 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5358 DAG, Subtarget, dl);
5365 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5366 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5367 SDValue V1 = Op.getOperand(0);
5368 SDValue V2 = Op.getOperand(1);
5369 EVT VT = Op.getValueType();
5370 DebugLoc dl = Op.getDebugLoc();
5371 unsigned NumElems = VT.getVectorNumElements();
5372 bool isMMX = VT.getSizeInBits() == 64;
5373 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5374 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5375 bool V1IsSplat = false;
5376 bool V2IsSplat = false;
5377 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5378 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5379 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5380 MachineFunction &MF = DAG.getMachineFunction();
5381 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5383 // Shuffle operations on MMX not supported.
5387 // Vector shuffle lowering takes 3 steps:
5389 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5390 // narrowing and commutation of operands should be handled.
5391 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5393 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5394 // so the shuffle can be broken into other shuffles and the legalizer can
5395 // try the lowering again.
5397 // The general ideia is that no vector_shuffle operation should be left to
5398 // be matched during isel, all of them must be converted to a target specific
5401 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5402 // narrowing and commutation of operands should be handled. The actual code
5403 // doesn't include all of those, work in progress...
5404 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5405 if (NewOp.getNode())
5408 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5409 // unpckh_undef). Only use pshufd if speed is more important than size.
5410 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5411 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5412 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5413 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5414 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5415 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5417 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5418 RelaxedMayFoldVectorLoad(V1))
5419 return getMOVDDup(Op, dl, V1, DAG);
5421 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5422 return getMOVHighToLow(Op, dl, DAG);
5424 // Use to match splats
5425 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5426 (VT == MVT::v2f64 || VT == MVT::v2i64))
5427 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5429 if (X86::isPSHUFDMask(SVOp)) {
5430 // The actual implementation will match the mask in the if above and then
5431 // during isel it can match several different instructions, not only pshufd
5432 // as its name says, sad but true, emulate the behavior for now...
5433 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5434 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5436 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5438 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5439 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5441 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5442 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5445 if (VT == MVT::v4f32)
5446 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5450 // Check if this can be converted into a logical shift.
5451 bool isLeft = false;
5454 bool isShift = getSubtarget()->hasSSE2() &&
5455 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5456 if (isShift && ShVal.hasOneUse()) {
5457 // If the shifted value has multiple uses, it may be cheaper to use
5458 // v_set0 + movlhps or movhlps, etc.
5459 EVT EltVT = VT.getVectorElementType();
5460 ShAmt *= EltVT.getSizeInBits();
5461 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5464 if (X86::isMOVLMask(SVOp)) {
5467 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5468 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5469 if (!X86::isMOVLPMask(SVOp)) {
5470 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5471 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5473 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5474 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5478 // FIXME: fold these into legal mask.
5479 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5480 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5482 if (X86::isMOVHLPSMask(SVOp))
5483 return getMOVHighToLow(Op, dl, DAG);
5485 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5486 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5488 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5489 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5491 if (X86::isMOVLPMask(SVOp))
5492 return getMOVLP(Op, dl, DAG, HasSSE2);
5494 if (ShouldXformToMOVHLPS(SVOp) ||
5495 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5496 return CommuteVectorShuffle(SVOp, DAG);
5499 // No better options. Use a vshl / vsrl.
5500 EVT EltVT = VT.getVectorElementType();
5501 ShAmt *= EltVT.getSizeInBits();
5502 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5505 bool Commuted = false;
5506 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5507 // 1,1,1,1 -> v8i16 though.
5508 V1IsSplat = isSplatVector(V1.getNode());
5509 V2IsSplat = isSplatVector(V2.getNode());
5511 // Canonicalize the splat or undef, if present, to be on the RHS.
5512 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5513 Op = CommuteVectorShuffle(SVOp, DAG);
5514 SVOp = cast<ShuffleVectorSDNode>(Op);
5515 V1 = SVOp->getOperand(0);
5516 V2 = SVOp->getOperand(1);
5517 std::swap(V1IsSplat, V2IsSplat);
5518 std::swap(V1IsUndef, V2IsUndef);
5522 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5523 // Shuffling low element of v1 into undef, just return v1.
5526 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5527 // the instruction selector will not match, so get a canonical MOVL with
5528 // swapped operands to undo the commute.
5529 return getMOVL(DAG, dl, VT, V2, V1);
5532 if (X86::isUNPCKLMask(SVOp))
5533 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5535 if (X86::isUNPCKHMask(SVOp))
5536 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5539 // Normalize mask so all entries that point to V2 points to its first
5540 // element then try to match unpck{h|l} again. If match, return a
5541 // new vector_shuffle with the corrected mask.
5542 SDValue NewMask = NormalizeMask(SVOp, DAG);
5543 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5544 if (NSVOp != SVOp) {
5545 if (X86::isUNPCKLMask(NSVOp, true)) {
5547 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5554 // Commute is back and try unpck* again.
5555 // FIXME: this seems wrong.
5556 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5557 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5559 if (X86::isUNPCKLMask(NewSVOp))
5560 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5562 if (X86::isUNPCKHMask(NewSVOp))
5563 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5566 // Normalize the node to match x86 shuffle ops if needed
5567 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5568 return CommuteVectorShuffle(SVOp, DAG);
5570 // The checks below are all present in isShuffleMaskLegal, but they are
5571 // inlined here right now to enable us to directly emit target specific
5572 // nodes, and remove one by one until they don't return Op anymore.
5573 SmallVector<int, 16> M;
5576 if (isPALIGNRMask(M, VT, HasSSSE3))
5577 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5578 X86::getShufflePALIGNRImmediate(SVOp),
5581 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5582 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5583 if (VT == MVT::v2f64)
5584 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5585 if (VT == MVT::v2i64)
5586 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5589 if (isPSHUFHWMask(M, VT))
5590 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5591 X86::getShufflePSHUFHWImmediate(SVOp),
5594 if (isPSHUFLWMask(M, VT))
5595 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5596 X86::getShufflePSHUFLWImmediate(SVOp),
5599 if (isSHUFPMask(M, VT)) {
5600 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5601 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5602 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5604 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5605 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5609 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5610 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5611 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5612 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5613 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5614 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5616 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5617 if (VT == MVT::v8i16) {
5618 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5619 if (NewOp.getNode())
5623 if (VT == MVT::v16i8) {
5624 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5625 if (NewOp.getNode())
5629 // Handle all 4 wide cases with a number of shuffles.
5631 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5637 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5638 SelectionDAG &DAG) const {
5639 EVT VT = Op.getValueType();
5640 DebugLoc dl = Op.getDebugLoc();
5641 if (VT.getSizeInBits() == 8) {
5642 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5643 Op.getOperand(0), Op.getOperand(1));
5644 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5645 DAG.getValueType(VT));
5646 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5647 } else if (VT.getSizeInBits() == 16) {
5648 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5649 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5651 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5653 DAG.getNode(ISD::BITCAST, dl,
5657 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5658 Op.getOperand(0), Op.getOperand(1));
5659 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5660 DAG.getValueType(VT));
5661 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5662 } else if (VT == MVT::f32) {
5663 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5664 // the result back to FR32 register. It's only worth matching if the
5665 // result has a single use which is a store or a bitcast to i32. And in
5666 // the case of a store, it's not worth it if the index is a constant 0,
5667 // because a MOVSSmr can be used instead, which is smaller and faster.
5668 if (!Op.hasOneUse())
5670 SDNode *User = *Op.getNode()->use_begin();
5671 if ((User->getOpcode() != ISD::STORE ||
5672 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5673 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5674 (User->getOpcode() != ISD::BITCAST ||
5675 User->getValueType(0) != MVT::i32))
5677 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5678 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
5681 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
5682 } else if (VT == MVT::i32) {
5683 // ExtractPS works with constant index.
5684 if (isa<ConstantSDNode>(Op.getOperand(1)))
5692 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5693 SelectionDAG &DAG) const {
5694 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5697 if (Subtarget->hasSSE41()) {
5698 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5703 EVT VT = Op.getValueType();
5704 DebugLoc dl = Op.getDebugLoc();
5705 // TODO: handle v16i8.
5706 if (VT.getSizeInBits() == 16) {
5707 SDValue Vec = Op.getOperand(0);
5708 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5710 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5711 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5712 DAG.getNode(ISD::BITCAST, dl,
5715 // Transform it so it match pextrw which produces a 32-bit result.
5716 EVT EltVT = MVT::i32;
5717 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5718 Op.getOperand(0), Op.getOperand(1));
5719 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5720 DAG.getValueType(VT));
5721 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5722 } else if (VT.getSizeInBits() == 32) {
5723 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5727 // SHUFPS the element to the lowest double word, then movss.
5728 int Mask[4] = { Idx, -1, -1, -1 };
5729 EVT VVT = Op.getOperand(0).getValueType();
5730 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5731 DAG.getUNDEF(VVT), Mask);
5732 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5733 DAG.getIntPtrConstant(0));
5734 } else if (VT.getSizeInBits() == 64) {
5735 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5736 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5737 // to match extract_elt for f64.
5738 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5742 // UNPCKHPD the element to the lowest double word, then movsd.
5743 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5744 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5745 int Mask[2] = { 1, -1 };
5746 EVT VVT = Op.getOperand(0).getValueType();
5747 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5748 DAG.getUNDEF(VVT), Mask);
5749 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5750 DAG.getIntPtrConstant(0));
5757 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5758 SelectionDAG &DAG) const {
5759 EVT VT = Op.getValueType();
5760 EVT EltVT = VT.getVectorElementType();
5761 DebugLoc dl = Op.getDebugLoc();
5763 SDValue N0 = Op.getOperand(0);
5764 SDValue N1 = Op.getOperand(1);
5765 SDValue N2 = Op.getOperand(2);
5767 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5768 isa<ConstantSDNode>(N2)) {
5770 if (VT == MVT::v8i16)
5771 Opc = X86ISD::PINSRW;
5772 else if (VT == MVT::v16i8)
5773 Opc = X86ISD::PINSRB;
5775 Opc = X86ISD::PINSRB;
5777 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5779 if (N1.getValueType() != MVT::i32)
5780 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5781 if (N2.getValueType() != MVT::i32)
5782 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5783 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5784 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5785 // Bits [7:6] of the constant are the source select. This will always be
5786 // zero here. The DAG Combiner may combine an extract_elt index into these
5787 // bits. For example (insert (extract, 3), 2) could be matched by putting
5788 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5789 // Bits [5:4] of the constant are the destination select. This is the
5790 // value of the incoming immediate.
5791 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5792 // combine either bitwise AND or insert of float 0.0 to set these bits.
5793 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5794 // Create this as a scalar to vector..
5795 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5796 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5797 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5798 // PINSR* works with constant index.
5805 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5806 EVT VT = Op.getValueType();
5807 EVT EltVT = VT.getVectorElementType();
5809 if (Subtarget->hasSSE41())
5810 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5812 if (EltVT == MVT::i8)
5815 DebugLoc dl = Op.getDebugLoc();
5816 SDValue N0 = Op.getOperand(0);
5817 SDValue N1 = Op.getOperand(1);
5818 SDValue N2 = Op.getOperand(2);
5820 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5821 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5822 // as its second argument.
5823 if (N1.getValueType() != MVT::i32)
5824 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5825 if (N2.getValueType() != MVT::i32)
5826 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5827 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
5833 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5834 DebugLoc dl = Op.getDebugLoc();
5836 if (Op.getValueType() == MVT::v1i64 &&
5837 Op.getOperand(0).getValueType() == MVT::i64)
5838 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5840 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5841 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
5842 "Expected an SSE type!");
5843 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
5844 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
5847 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5848 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5849 // one of the above mentioned nodes. It has to be wrapped because otherwise
5850 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5851 // be used to form addressing mode. These wrapped nodes will be selected
5854 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5855 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5857 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5859 unsigned char OpFlag = 0;
5860 unsigned WrapperKind = X86ISD::Wrapper;
5861 CodeModel::Model M = getTargetMachine().getCodeModel();
5863 if (Subtarget->isPICStyleRIPRel() &&
5864 (M == CodeModel::Small || M == CodeModel::Kernel))
5865 WrapperKind = X86ISD::WrapperRIP;
5866 else if (Subtarget->isPICStyleGOT())
5867 OpFlag = X86II::MO_GOTOFF;
5868 else if (Subtarget->isPICStyleStubPIC())
5869 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5871 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5873 CP->getOffset(), OpFlag);
5874 DebugLoc DL = CP->getDebugLoc();
5875 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5876 // With PIC, the address is actually $g + Offset.
5878 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5879 DAG.getNode(X86ISD::GlobalBaseReg,
5880 DebugLoc(), getPointerTy()),
5887 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5888 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5890 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5892 unsigned char OpFlag = 0;
5893 unsigned WrapperKind = X86ISD::Wrapper;
5894 CodeModel::Model M = getTargetMachine().getCodeModel();
5896 if (Subtarget->isPICStyleRIPRel() &&
5897 (M == CodeModel::Small || M == CodeModel::Kernel))
5898 WrapperKind = X86ISD::WrapperRIP;
5899 else if (Subtarget->isPICStyleGOT())
5900 OpFlag = X86II::MO_GOTOFF;
5901 else if (Subtarget->isPICStyleStubPIC())
5902 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5904 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5906 DebugLoc DL = JT->getDebugLoc();
5907 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5909 // With PIC, the address is actually $g + Offset.
5911 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5912 DAG.getNode(X86ISD::GlobalBaseReg,
5913 DebugLoc(), getPointerTy()),
5920 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5921 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5923 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5925 unsigned char OpFlag = 0;
5926 unsigned WrapperKind = X86ISD::Wrapper;
5927 CodeModel::Model M = getTargetMachine().getCodeModel();
5929 if (Subtarget->isPICStyleRIPRel() &&
5930 (M == CodeModel::Small || M == CodeModel::Kernel))
5931 WrapperKind = X86ISD::WrapperRIP;
5932 else if (Subtarget->isPICStyleGOT())
5933 OpFlag = X86II::MO_GOTOFF;
5934 else if (Subtarget->isPICStyleStubPIC())
5935 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5937 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5939 DebugLoc DL = Op.getDebugLoc();
5940 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5943 // With PIC, the address is actually $g + Offset.
5944 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5945 !Subtarget->is64Bit()) {
5946 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5947 DAG.getNode(X86ISD::GlobalBaseReg,
5948 DebugLoc(), getPointerTy()),
5956 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5957 // Create the TargetBlockAddressAddress node.
5958 unsigned char OpFlags =
5959 Subtarget->ClassifyBlockAddressReference();
5960 CodeModel::Model M = getTargetMachine().getCodeModel();
5961 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5962 DebugLoc dl = Op.getDebugLoc();
5963 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5964 /*isTarget=*/true, OpFlags);
5966 if (Subtarget->isPICStyleRIPRel() &&
5967 (M == CodeModel::Small || M == CodeModel::Kernel))
5968 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5970 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5972 // With PIC, the address is actually $g + Offset.
5973 if (isGlobalRelativeToPICBase(OpFlags)) {
5974 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5975 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5983 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5985 SelectionDAG &DAG) const {
5986 // Create the TargetGlobalAddress node, folding in the constant
5987 // offset if it is legal.
5988 unsigned char OpFlags =
5989 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5990 CodeModel::Model M = getTargetMachine().getCodeModel();
5992 if (OpFlags == X86II::MO_NO_FLAG &&
5993 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5994 // A direct static reference to a global.
5995 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5998 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6001 if (Subtarget->isPICStyleRIPRel() &&
6002 (M == CodeModel::Small || M == CodeModel::Kernel))
6003 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6005 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6007 // With PIC, the address is actually $g + Offset.
6008 if (isGlobalRelativeToPICBase(OpFlags)) {
6009 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6010 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6014 // For globals that require a load from a stub to get the address, emit the
6016 if (isGlobalStubReference(OpFlags))
6017 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6018 MachinePointerInfo::getGOT(), false, false, 0);
6020 // If there was a non-zero offset that we didn't fold, create an explicit
6023 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6024 DAG.getConstant(Offset, getPointerTy()));
6030 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6031 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6032 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6033 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6037 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6038 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6039 unsigned char OperandFlags) {
6040 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6041 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6042 DebugLoc dl = GA->getDebugLoc();
6043 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6044 GA->getValueType(0),
6048 SDValue Ops[] = { Chain, TGA, *InFlag };
6049 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6051 SDValue Ops[] = { Chain, TGA };
6052 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6055 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6056 MFI->setAdjustsStack(true);
6058 SDValue Flag = Chain.getValue(1);
6059 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6062 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6064 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6067 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6068 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6069 DAG.getNode(X86ISD::GlobalBaseReg,
6070 DebugLoc(), PtrVT), InFlag);
6071 InFlag = Chain.getValue(1);
6073 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6076 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6078 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6080 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6081 X86::RAX, X86II::MO_TLSGD);
6084 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6085 // "local exec" model.
6086 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6087 const EVT PtrVT, TLSModel::Model model,
6089 DebugLoc dl = GA->getDebugLoc();
6091 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6092 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6093 is64Bit ? 257 : 256));
6095 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6096 DAG.getIntPtrConstant(0),
6097 MachinePointerInfo(Ptr), false, false, 0);
6099 unsigned char OperandFlags = 0;
6100 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6102 unsigned WrapperKind = X86ISD::Wrapper;
6103 if (model == TLSModel::LocalExec) {
6104 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6105 } else if (is64Bit) {
6106 assert(model == TLSModel::InitialExec);
6107 OperandFlags = X86II::MO_GOTTPOFF;
6108 WrapperKind = X86ISD::WrapperRIP;
6110 assert(model == TLSModel::InitialExec);
6111 OperandFlags = X86II::MO_INDNTPOFF;
6114 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6116 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6117 GA->getValueType(0),
6118 GA->getOffset(), OperandFlags);
6119 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6121 if (model == TLSModel::InitialExec)
6122 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6123 MachinePointerInfo::getGOT(), false, false, 0);
6125 // The address of the thread local variable is the add of the thread
6126 // pointer with the offset of the variable.
6127 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6131 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6133 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6134 const GlobalValue *GV = GA->getGlobal();
6136 if (Subtarget->isTargetELF()) {
6137 // TODO: implement the "local dynamic" model
6138 // TODO: implement the "initial exec"model for pic executables
6140 // If GV is an alias then use the aliasee for determining
6141 // thread-localness.
6142 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6143 GV = GA->resolveAliasedGlobal(false);
6145 TLSModel::Model model
6146 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6149 case TLSModel::GeneralDynamic:
6150 case TLSModel::LocalDynamic: // not implemented
6151 if (Subtarget->is64Bit())
6152 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6153 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6155 case TLSModel::InitialExec:
6156 case TLSModel::LocalExec:
6157 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6158 Subtarget->is64Bit());
6160 } else if (Subtarget->isTargetDarwin()) {
6161 // Darwin only has one model of TLS. Lower to that.
6162 unsigned char OpFlag = 0;
6163 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6164 X86ISD::WrapperRIP : X86ISD::Wrapper;
6166 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6168 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6169 !Subtarget->is64Bit();
6171 OpFlag = X86II::MO_TLVP_PIC_BASE;
6173 OpFlag = X86II::MO_TLVP;
6174 DebugLoc DL = Op.getDebugLoc();
6175 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6177 GA->getOffset(), OpFlag);
6178 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6180 // With PIC32, the address is actually $g + Offset.
6182 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6183 DAG.getNode(X86ISD::GlobalBaseReg,
6184 DebugLoc(), getPointerTy()),
6187 // Lowering the machine isd will make sure everything is in the right
6189 SDValue Args[] = { Offset };
6190 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
6192 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6193 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6194 MFI->setAdjustsStack(true);
6196 // And our return value (tls address) is in the standard call return value
6198 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6199 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6203 "TLS not implemented for this target.");
6205 llvm_unreachable("Unreachable");
6210 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6211 /// take a 2 x i32 value to shift plus a shift amount.
6212 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6213 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6214 EVT VT = Op.getValueType();
6215 unsigned VTBits = VT.getSizeInBits();
6216 DebugLoc dl = Op.getDebugLoc();
6217 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6218 SDValue ShOpLo = Op.getOperand(0);
6219 SDValue ShOpHi = Op.getOperand(1);
6220 SDValue ShAmt = Op.getOperand(2);
6221 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6222 DAG.getConstant(VTBits - 1, MVT::i8))
6223 : DAG.getConstant(0, VT);
6226 if (Op.getOpcode() == ISD::SHL_PARTS) {
6227 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6228 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6230 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6231 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6234 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6235 DAG.getConstant(VTBits, MVT::i8));
6236 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6237 AndNode, DAG.getConstant(0, MVT::i8));
6240 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6241 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6242 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6244 if (Op.getOpcode() == ISD::SHL_PARTS) {
6245 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6246 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6248 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6249 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6252 SDValue Ops[2] = { Lo, Hi };
6253 return DAG.getMergeValues(Ops, 2, dl);
6256 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6257 SelectionDAG &DAG) const {
6258 EVT SrcVT = Op.getOperand(0).getValueType();
6260 if (SrcVT.isVector())
6263 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6264 "Unknown SINT_TO_FP to lower!");
6266 // These are really Legal; return the operand so the caller accepts it as
6268 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6270 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6271 Subtarget->is64Bit()) {
6275 DebugLoc dl = Op.getDebugLoc();
6276 unsigned Size = SrcVT.getSizeInBits()/8;
6277 MachineFunction &MF = DAG.getMachineFunction();
6278 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6279 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6280 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6282 MachinePointerInfo::getFixedStack(SSFI),
6284 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6287 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6289 SelectionDAG &DAG) const {
6291 DebugLoc DL = Op.getDebugLoc();
6293 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6295 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
6297 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6299 unsigned ByteSize = SrcVT.getSizeInBits()/8;
6301 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6302 MachineMemOperand *MMO =
6303 DAG.getMachineFunction()
6304 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6305 MachineMemOperand::MOLoad, ByteSize, ByteSize);
6307 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6308 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
6310 Tys, Ops, array_lengthof(Ops),
6314 Chain = Result.getValue(1);
6315 SDValue InFlag = Result.getValue(2);
6317 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6318 // shouldn't be necessary except that RFP cannot be live across
6319 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6320 MachineFunction &MF = DAG.getMachineFunction();
6321 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
6322 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
6323 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6324 Tys = DAG.getVTList(MVT::Other);
6326 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6328 MachineMemOperand *MMO =
6329 DAG.getMachineFunction()
6330 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6331 MachineMemOperand::MOStore, SSFISize, SSFISize);
6333 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
6334 Ops, array_lengthof(Ops),
6335 Op.getValueType(), MMO);
6336 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
6337 MachinePointerInfo::getFixedStack(SSFI),
6344 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6345 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6346 SelectionDAG &DAG) const {
6347 // This algorithm is not obvious. Here it is in C code, more or less:
6349 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6350 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6351 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6353 // Copy ints to xmm registers.
6354 __m128i xh = _mm_cvtsi32_si128( hi );
6355 __m128i xl = _mm_cvtsi32_si128( lo );
6357 // Combine into low half of a single xmm register.
6358 __m128i x = _mm_unpacklo_epi32( xh, xl );
6362 // Merge in appropriate exponents to give the integer bits the right
6364 x = _mm_unpacklo_epi32( x, exp );
6366 // Subtract away the biases to deal with the IEEE-754 double precision
6368 d = _mm_sub_pd( (__m128d) x, bias );
6370 // All conversions up to here are exact. The correctly rounded result is
6371 // calculated using the current rounding mode using the following
6373 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6374 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6375 // store doesn't really need to be here (except
6376 // maybe to zero the other double)
6381 DebugLoc dl = Op.getDebugLoc();
6382 LLVMContext *Context = DAG.getContext();
6384 // Build some magic constants.
6385 std::vector<Constant*> CV0;
6386 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6387 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6388 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6389 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6390 Constant *C0 = ConstantVector::get(CV0);
6391 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6393 std::vector<Constant*> CV1;
6395 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6397 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6398 Constant *C1 = ConstantVector::get(CV1);
6399 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6401 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6402 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6404 DAG.getIntPtrConstant(1)));
6405 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6406 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6408 DAG.getIntPtrConstant(0)));
6409 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6410 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6411 MachinePointerInfo::getConstantPool(),
6413 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6414 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
6415 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6416 MachinePointerInfo::getConstantPool(),
6418 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6420 // Add the halves; easiest way is to swap them into another reg first.
6421 int ShufMask[2] = { 1, -1 };
6422 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6423 DAG.getUNDEF(MVT::v2f64), ShufMask);
6424 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6425 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6426 DAG.getIntPtrConstant(0));
6429 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6430 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6431 SelectionDAG &DAG) const {
6432 DebugLoc dl = Op.getDebugLoc();
6433 // FP constant to bias correct the final result.
6434 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6437 // Load the 32-bit value into an XMM register.
6438 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6439 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6441 DAG.getIntPtrConstant(0)));
6443 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6444 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
6445 DAG.getIntPtrConstant(0));
6447 // Or the load with the bias.
6448 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6449 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6450 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6452 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6453 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6454 MVT::v2f64, Bias)));
6455 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6456 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
6457 DAG.getIntPtrConstant(0));
6459 // Subtract the bias.
6460 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6462 // Handle final rounding.
6463 EVT DestVT = Op.getValueType();
6465 if (DestVT.bitsLT(MVT::f64)) {
6466 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6467 DAG.getIntPtrConstant(0));
6468 } else if (DestVT.bitsGT(MVT::f64)) {
6469 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6472 // Handle final rounding.
6476 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6477 SelectionDAG &DAG) const {
6478 SDValue N0 = Op.getOperand(0);
6479 DebugLoc dl = Op.getDebugLoc();
6481 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6482 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6483 // the optimization here.
6484 if (DAG.SignBitIsZero(N0))
6485 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6487 EVT SrcVT = N0.getValueType();
6488 EVT DstVT = Op.getValueType();
6489 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6490 return LowerUINT_TO_FP_i64(Op, DAG);
6491 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6492 return LowerUINT_TO_FP_i32(Op, DAG);
6494 // Make a 64-bit buffer, and use it to build an FILD.
6495 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6496 if (SrcVT == MVT::i32) {
6497 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6498 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6499 getPointerTy(), StackSlot, WordOff);
6500 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6501 StackSlot, MachinePointerInfo(),
6503 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6504 OffsetSlot, MachinePointerInfo(),
6506 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6510 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6511 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6512 StackSlot, MachinePointerInfo(),
6514 // For i64 source, we need to add the appropriate power of 2 if the input
6515 // was negative. This is the same as the optimization in
6516 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6517 // we must be careful to do the computation in x87 extended precision, not
6518 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6519 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6520 MachineMemOperand *MMO =
6521 DAG.getMachineFunction()
6522 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6523 MachineMemOperand::MOLoad, 8, 8);
6525 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6526 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6527 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
6530 APInt FF(32, 0x5F800000ULL);
6532 // Check whether the sign bit is set.
6533 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6534 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6537 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6538 SDValue FudgePtr = DAG.getConstantPool(
6539 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6542 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6543 SDValue Zero = DAG.getIntPtrConstant(0);
6544 SDValue Four = DAG.getIntPtrConstant(4);
6545 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6547 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6549 // Load the value out, extending it from f32 to f80.
6550 // FIXME: Avoid the extend by constructing the right constant pool?
6551 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6552 FudgePtr, MachinePointerInfo::getConstantPool(),
6553 MVT::f32, false, false, 4);
6554 // Extend everything to 80 bits to force it to be done on x87.
6555 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6556 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6559 std::pair<SDValue,SDValue> X86TargetLowering::
6560 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6561 DebugLoc DL = Op.getDebugLoc();
6563 EVT DstTy = Op.getValueType();
6566 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6570 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6571 DstTy.getSimpleVT() >= MVT::i16 &&
6572 "Unknown FP_TO_SINT to lower!");
6574 // These are really Legal.
6575 if (DstTy == MVT::i32 &&
6576 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6577 return std::make_pair(SDValue(), SDValue());
6578 if (Subtarget->is64Bit() &&
6579 DstTy == MVT::i64 &&
6580 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6581 return std::make_pair(SDValue(), SDValue());
6583 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6585 MachineFunction &MF = DAG.getMachineFunction();
6586 unsigned MemSize = DstTy.getSizeInBits()/8;
6587 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6588 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6593 switch (DstTy.getSimpleVT().SimpleTy) {
6594 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6595 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6596 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6597 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6600 SDValue Chain = DAG.getEntryNode();
6601 SDValue Value = Op.getOperand(0);
6602 EVT TheVT = Op.getOperand(0).getValueType();
6603 if (isScalarFPTypeInSSEReg(TheVT)) {
6604 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6605 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
6606 MachinePointerInfo::getFixedStack(SSFI),
6608 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6610 Chain, StackSlot, DAG.getValueType(TheVT)
6613 MachineMemOperand *MMO =
6614 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6615 MachineMemOperand::MOLoad, MemSize, MemSize);
6616 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
6618 Chain = Value.getValue(1);
6619 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6620 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6623 MachineMemOperand *MMO =
6624 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6625 MachineMemOperand::MOStore, MemSize, MemSize);
6627 // Build the FP_TO_INT*_IN_MEM
6628 SDValue Ops[] = { Chain, Value, StackSlot };
6629 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
6630 Ops, 3, DstTy, MMO);
6632 return std::make_pair(FIST, StackSlot);
6635 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6636 SelectionDAG &DAG) const {
6637 if (Op.getValueType().isVector())
6640 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6641 SDValue FIST = Vals.first, StackSlot = Vals.second;
6642 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6643 if (FIST.getNode() == 0) return Op;
6646 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6647 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6650 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6651 SelectionDAG &DAG) const {
6652 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6653 SDValue FIST = Vals.first, StackSlot = Vals.second;
6654 assert(FIST.getNode() && "Unexpected failure");
6657 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6658 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6661 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6662 SelectionDAG &DAG) const {
6663 LLVMContext *Context = DAG.getContext();
6664 DebugLoc dl = Op.getDebugLoc();
6665 EVT VT = Op.getValueType();
6668 EltVT = VT.getVectorElementType();
6669 std::vector<Constant*> CV;
6670 if (EltVT == MVT::f64) {
6671 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6675 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6681 Constant *C = ConstantVector::get(CV);
6682 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6683 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6684 MachinePointerInfo::getConstantPool(),
6686 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6689 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6690 LLVMContext *Context = DAG.getContext();
6691 DebugLoc dl = Op.getDebugLoc();
6692 EVT VT = Op.getValueType();
6695 EltVT = VT.getVectorElementType();
6696 std::vector<Constant*> CV;
6697 if (EltVT == MVT::f64) {
6698 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6702 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6708 Constant *C = ConstantVector::get(CV);
6709 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6710 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6711 MachinePointerInfo::getConstantPool(),
6713 if (VT.isVector()) {
6714 return DAG.getNode(ISD::BITCAST, dl, VT,
6715 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6716 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6718 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
6720 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6724 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6725 LLVMContext *Context = DAG.getContext();
6726 SDValue Op0 = Op.getOperand(0);
6727 SDValue Op1 = Op.getOperand(1);
6728 DebugLoc dl = Op.getDebugLoc();
6729 EVT VT = Op.getValueType();
6730 EVT SrcVT = Op1.getValueType();
6732 // If second operand is smaller, extend it first.
6733 if (SrcVT.bitsLT(VT)) {
6734 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6737 // And if it is bigger, shrink it first.
6738 if (SrcVT.bitsGT(VT)) {
6739 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6743 // At this point the operands and the result should have the same
6744 // type, and that won't be f80 since that is not custom lowered.
6746 // First get the sign bit of second operand.
6747 std::vector<Constant*> CV;
6748 if (SrcVT == MVT::f64) {
6749 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6750 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6752 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6753 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6754 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6755 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6757 Constant *C = ConstantVector::get(CV);
6758 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6759 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6760 MachinePointerInfo::getConstantPool(),
6762 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6764 // Shift sign bit right or left if the two operands have different types.
6765 if (SrcVT.bitsGT(VT)) {
6766 // Op0 is MVT::f32, Op1 is MVT::f64.
6767 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6768 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6769 DAG.getConstant(32, MVT::i32));
6770 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
6771 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6772 DAG.getIntPtrConstant(0));
6775 // Clear first operand sign bit.
6777 if (VT == MVT::f64) {
6778 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6779 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6781 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6782 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6783 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6784 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6786 C = ConstantVector::get(CV);
6787 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6788 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6789 MachinePointerInfo::getConstantPool(),
6791 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6793 // Or the value with the sign bit.
6794 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6797 /// Emit nodes that will be selected as "test Op0,Op0", or something
6799 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6800 SelectionDAG &DAG) const {
6801 DebugLoc dl = Op.getDebugLoc();
6803 // CF and OF aren't always set the way we want. Determine which
6804 // of these we need.
6805 bool NeedCF = false;
6806 bool NeedOF = false;
6809 case X86::COND_A: case X86::COND_AE:
6810 case X86::COND_B: case X86::COND_BE:
6813 case X86::COND_G: case X86::COND_GE:
6814 case X86::COND_L: case X86::COND_LE:
6815 case X86::COND_O: case X86::COND_NO:
6820 // See if we can use the EFLAGS value from the operand instead of
6821 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6822 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6823 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6824 // Emit a CMP with 0, which is the TEST pattern.
6825 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6826 DAG.getConstant(0, Op.getValueType()));
6828 unsigned Opcode = 0;
6829 unsigned NumOperands = 0;
6830 switch (Op.getNode()->getOpcode()) {
6832 // Due to an isel shortcoming, be conservative if this add is likely to be
6833 // selected as part of a load-modify-store instruction. When the root node
6834 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6835 // uses of other nodes in the match, such as the ADD in this case. This
6836 // leads to the ADD being left around and reselected, with the result being
6837 // two adds in the output. Alas, even if none our users are stores, that
6838 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6839 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6840 // climbing the DAG back to the root, and it doesn't seem to be worth the
6842 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6843 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6844 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6847 if (ConstantSDNode *C =
6848 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6849 // An add of one will be selected as an INC.
6850 if (C->getAPIntValue() == 1) {
6851 Opcode = X86ISD::INC;
6856 // An add of negative one (subtract of one) will be selected as a DEC.
6857 if (C->getAPIntValue().isAllOnesValue()) {
6858 Opcode = X86ISD::DEC;
6864 // Otherwise use a regular EFLAGS-setting add.
6865 Opcode = X86ISD::ADD;
6869 // If the primary and result isn't used, don't bother using X86ISD::AND,
6870 // because a TEST instruction will be better.
6871 bool NonFlagUse = false;
6872 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6873 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6875 unsigned UOpNo = UI.getOperandNo();
6876 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6877 // Look pass truncate.
6878 UOpNo = User->use_begin().getOperandNo();
6879 User = *User->use_begin();
6882 if (User->getOpcode() != ISD::BRCOND &&
6883 User->getOpcode() != ISD::SETCC &&
6884 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6897 // Due to the ISEL shortcoming noted above, be conservative if this op is
6898 // likely to be selected as part of a load-modify-store instruction.
6899 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6900 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6901 if (UI->getOpcode() == ISD::STORE)
6904 // Otherwise use a regular EFLAGS-setting instruction.
6905 switch (Op.getNode()->getOpcode()) {
6906 default: llvm_unreachable("unexpected operator!");
6907 case ISD::SUB: Opcode = X86ISD::SUB; break;
6908 case ISD::OR: Opcode = X86ISD::OR; break;
6909 case ISD::XOR: Opcode = X86ISD::XOR; break;
6910 case ISD::AND: Opcode = X86ISD::AND; break;
6922 return SDValue(Op.getNode(), 1);
6929 // Emit a CMP with 0, which is the TEST pattern.
6930 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6931 DAG.getConstant(0, Op.getValueType()));
6933 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6934 SmallVector<SDValue, 4> Ops;
6935 for (unsigned i = 0; i != NumOperands; ++i)
6936 Ops.push_back(Op.getOperand(i));
6938 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6939 DAG.ReplaceAllUsesWith(Op, New);
6940 return SDValue(New.getNode(), 1);
6943 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6945 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6946 SelectionDAG &DAG) const {
6947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6948 if (C->getAPIntValue() == 0)
6949 return EmitTest(Op0, X86CC, DAG);
6951 DebugLoc dl = Op0.getDebugLoc();
6952 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6955 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6956 /// if it's possible.
6957 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6958 DebugLoc dl, SelectionDAG &DAG) const {
6959 SDValue Op0 = And.getOperand(0);
6960 SDValue Op1 = And.getOperand(1);
6961 if (Op0.getOpcode() == ISD::TRUNCATE)
6962 Op0 = Op0.getOperand(0);
6963 if (Op1.getOpcode() == ISD::TRUNCATE)
6964 Op1 = Op1.getOperand(0);
6967 if (Op1.getOpcode() == ISD::SHL)
6968 std::swap(Op0, Op1);
6969 if (Op0.getOpcode() == ISD::SHL) {
6970 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6971 if (And00C->getZExtValue() == 1) {
6972 // If we looked past a truncate, check that it's only truncating away
6974 unsigned BitWidth = Op0.getValueSizeInBits();
6975 unsigned AndBitWidth = And.getValueSizeInBits();
6976 if (BitWidth > AndBitWidth) {
6977 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6978 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6979 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6983 RHS = Op0.getOperand(1);
6985 } else if (Op1.getOpcode() == ISD::Constant) {
6986 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6987 SDValue AndLHS = Op0;
6988 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6989 LHS = AndLHS.getOperand(0);
6990 RHS = AndLHS.getOperand(1);
6994 if (LHS.getNode()) {
6995 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6996 // instruction. Since the shift amount is in-range-or-undefined, we know
6997 // that doing a bittest on the i32 value is ok. We extend to i32 because
6998 // the encoding for the i16 version is larger than the i32 version.
6999 // Also promote i16 to i32 for performance / code size reason.
7000 if (LHS.getValueType() == MVT::i8 ||
7001 LHS.getValueType() == MVT::i16)
7002 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7004 // If the operand types disagree, extend the shift amount to match. Since
7005 // BT ignores high bits (like shifts) we can use anyextend.
7006 if (LHS.getValueType() != RHS.getValueType())
7007 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7009 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7010 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7011 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7012 DAG.getConstant(Cond, MVT::i8), BT);
7018 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7019 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7020 SDValue Op0 = Op.getOperand(0);
7021 SDValue Op1 = Op.getOperand(1);
7022 DebugLoc dl = Op.getDebugLoc();
7023 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7025 // Optimize to BT if possible.
7026 // Lower (X & (1 << N)) == 0 to BT(X, N).
7027 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7028 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7029 if (Op0.getOpcode() == ISD::AND &&
7031 Op1.getOpcode() == ISD::Constant &&
7032 cast<ConstantSDNode>(Op1)->isNullValue() &&
7033 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7034 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7035 if (NewSetCC.getNode())
7039 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
7040 if (Op0.getOpcode() == X86ISD::SETCC &&
7041 Op1.getOpcode() == ISD::Constant &&
7042 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7043 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7044 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7045 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7046 bool Invert = (CC == ISD::SETNE) ^
7047 cast<ConstantSDNode>(Op1)->isNullValue();
7049 CCode = X86::GetOppositeBranchCondition(CCode);
7050 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7051 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7054 bool isFP = Op1.getValueType().isFloatingPoint();
7055 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7056 if (X86CC == X86::COND_INVALID)
7059 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
7061 // Use sbb x, x to materialize carry bit into a GPR.
7062 if (X86CC == X86::COND_B)
7063 return DAG.getNode(ISD::AND, dl, MVT::i8,
7064 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
7065 DAG.getConstant(X86CC, MVT::i8), Cond),
7066 DAG.getConstant(1, MVT::i8));
7068 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7069 DAG.getConstant(X86CC, MVT::i8), Cond);
7072 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7074 SDValue Op0 = Op.getOperand(0);
7075 SDValue Op1 = Op.getOperand(1);
7076 SDValue CC = Op.getOperand(2);
7077 EVT VT = Op.getValueType();
7078 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7079 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7080 DebugLoc dl = Op.getDebugLoc();
7084 EVT VT0 = Op0.getValueType();
7085 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7086 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7089 switch (SetCCOpcode) {
7092 case ISD::SETEQ: SSECC = 0; break;
7094 case ISD::SETGT: Swap = true; // Fallthrough
7096 case ISD::SETOLT: SSECC = 1; break;
7098 case ISD::SETGE: Swap = true; // Fallthrough
7100 case ISD::SETOLE: SSECC = 2; break;
7101 case ISD::SETUO: SSECC = 3; break;
7103 case ISD::SETNE: SSECC = 4; break;
7104 case ISD::SETULE: Swap = true;
7105 case ISD::SETUGE: SSECC = 5; break;
7106 case ISD::SETULT: Swap = true;
7107 case ISD::SETUGT: SSECC = 6; break;
7108 case ISD::SETO: SSECC = 7; break;
7111 std::swap(Op0, Op1);
7113 // In the two special cases we can't handle, emit two comparisons.
7115 if (SetCCOpcode == ISD::SETUEQ) {
7117 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7118 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7119 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7121 else if (SetCCOpcode == ISD::SETONE) {
7123 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7124 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7125 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7127 llvm_unreachable("Illegal FP comparison");
7129 // Handle all other FP comparisons here.
7130 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7133 // We are handling one of the integer comparisons here. Since SSE only has
7134 // GT and EQ comparisons for integer, swapping operands and multiple
7135 // operations may be required for some comparisons.
7136 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7137 bool Swap = false, Invert = false, FlipSigns = false;
7139 switch (VT.getSimpleVT().SimpleTy) {
7141 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7142 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7143 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7144 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7147 switch (SetCCOpcode) {
7149 case ISD::SETNE: Invert = true;
7150 case ISD::SETEQ: Opc = EQOpc; break;
7151 case ISD::SETLT: Swap = true;
7152 case ISD::SETGT: Opc = GTOpc; break;
7153 case ISD::SETGE: Swap = true;
7154 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7155 case ISD::SETULT: Swap = true;
7156 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7157 case ISD::SETUGE: Swap = true;
7158 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7161 std::swap(Op0, Op1);
7163 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7164 // bits of the inputs before performing those operations.
7166 EVT EltVT = VT.getVectorElementType();
7167 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7169 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7170 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7172 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7173 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7176 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7178 // If the logical-not of the result is required, perform that now.
7180 Result = DAG.getNOT(dl, Result, VT);
7185 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7186 static bool isX86LogicalCmp(SDValue Op) {
7187 unsigned Opc = Op.getNode()->getOpcode();
7188 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7190 if (Op.getResNo() == 1 &&
7191 (Opc == X86ISD::ADD ||
7192 Opc == X86ISD::SUB ||
7193 Opc == X86ISD::SMUL ||
7194 Opc == X86ISD::UMUL ||
7195 Opc == X86ISD::INC ||
7196 Opc == X86ISD::DEC ||
7197 Opc == X86ISD::OR ||
7198 Opc == X86ISD::XOR ||
7199 Opc == X86ISD::AND))
7205 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7206 bool addTest = true;
7207 SDValue Cond = Op.getOperand(0);
7208 DebugLoc dl = Op.getDebugLoc();
7211 if (Cond.getOpcode() == ISD::SETCC) {
7212 SDValue NewCond = LowerSETCC(Cond, DAG);
7213 if (NewCond.getNode())
7217 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
7218 SDValue Op1 = Op.getOperand(1);
7219 SDValue Op2 = Op.getOperand(2);
7220 if (Cond.getOpcode() == X86ISD::SETCC &&
7221 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
7222 SDValue Cmp = Cond.getOperand(1);
7223 if (Cmp.getOpcode() == X86ISD::CMP) {
7224 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
7225 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7226 ConstantSDNode *RHSC =
7227 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
7228 if (N1C && N1C->isAllOnesValue() &&
7229 N2C && N2C->isNullValue() &&
7230 RHSC && RHSC->isNullValue()) {
7231 SDValue CmpOp0 = Cmp.getOperand(0);
7232 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7233 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7234 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
7235 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7240 // Look pass (and (setcc_carry (cmp ...)), 1).
7241 if (Cond.getOpcode() == ISD::AND &&
7242 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7243 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7244 if (C && C->getAPIntValue() == 1)
7245 Cond = Cond.getOperand(0);
7248 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7249 // setting operand in place of the X86ISD::SETCC.
7250 if (Cond.getOpcode() == X86ISD::SETCC ||
7251 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7252 CC = Cond.getOperand(0);
7254 SDValue Cmp = Cond.getOperand(1);
7255 unsigned Opc = Cmp.getOpcode();
7256 EVT VT = Op.getValueType();
7258 bool IllegalFPCMov = false;
7259 if (VT.isFloatingPoint() && !VT.isVector() &&
7260 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7261 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7263 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7264 Opc == X86ISD::BT) { // FIXME
7271 // Look pass the truncate.
7272 if (Cond.getOpcode() == ISD::TRUNCATE)
7273 Cond = Cond.getOperand(0);
7275 // We know the result of AND is compared against zero. Try to match
7277 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7278 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7279 if (NewSetCC.getNode()) {
7280 CC = NewSetCC.getOperand(0);
7281 Cond = NewSetCC.getOperand(1);
7288 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7289 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7292 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7293 // condition is true.
7294 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
7295 SDValue Ops[] = { Op2, Op1, CC, Cond };
7296 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
7299 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7300 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7301 // from the AND / OR.
7302 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7303 Opc = Op.getOpcode();
7304 if (Opc != ISD::OR && Opc != ISD::AND)
7306 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7307 Op.getOperand(0).hasOneUse() &&
7308 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7309 Op.getOperand(1).hasOneUse());
7312 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7313 // 1 and that the SETCC node has a single use.
7314 static bool isXor1OfSetCC(SDValue Op) {
7315 if (Op.getOpcode() != ISD::XOR)
7317 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7318 if (N1C && N1C->getAPIntValue() == 1) {
7319 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7320 Op.getOperand(0).hasOneUse();
7325 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7326 bool addTest = true;
7327 SDValue Chain = Op.getOperand(0);
7328 SDValue Cond = Op.getOperand(1);
7329 SDValue Dest = Op.getOperand(2);
7330 DebugLoc dl = Op.getDebugLoc();
7333 if (Cond.getOpcode() == ISD::SETCC) {
7334 SDValue NewCond = LowerSETCC(Cond, DAG);
7335 if (NewCond.getNode())
7339 // FIXME: LowerXALUO doesn't handle these!!
7340 else if (Cond.getOpcode() == X86ISD::ADD ||
7341 Cond.getOpcode() == X86ISD::SUB ||
7342 Cond.getOpcode() == X86ISD::SMUL ||
7343 Cond.getOpcode() == X86ISD::UMUL)
7344 Cond = LowerXALUO(Cond, DAG);
7347 // Look pass (and (setcc_carry (cmp ...)), 1).
7348 if (Cond.getOpcode() == ISD::AND &&
7349 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7350 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7351 if (C && C->getAPIntValue() == 1)
7352 Cond = Cond.getOperand(0);
7355 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7356 // setting operand in place of the X86ISD::SETCC.
7357 if (Cond.getOpcode() == X86ISD::SETCC ||
7358 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7359 CC = Cond.getOperand(0);
7361 SDValue Cmp = Cond.getOperand(1);
7362 unsigned Opc = Cmp.getOpcode();
7363 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7364 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7368 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7372 // These can only come from an arithmetic instruction with overflow,
7373 // e.g. SADDO, UADDO.
7374 Cond = Cond.getNode()->getOperand(1);
7381 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7382 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7383 if (CondOpc == ISD::OR) {
7384 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7385 // two branches instead of an explicit OR instruction with a
7387 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7388 isX86LogicalCmp(Cmp)) {
7389 CC = Cond.getOperand(0).getOperand(0);
7390 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7391 Chain, Dest, CC, Cmp);
7392 CC = Cond.getOperand(1).getOperand(0);
7396 } else { // ISD::AND
7397 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7398 // two branches instead of an explicit AND instruction with a
7399 // separate test. However, we only do this if this block doesn't
7400 // have a fall-through edge, because this requires an explicit
7401 // jmp when the condition is false.
7402 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7403 isX86LogicalCmp(Cmp) &&
7404 Op.getNode()->hasOneUse()) {
7405 X86::CondCode CCode =
7406 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7407 CCode = X86::GetOppositeBranchCondition(CCode);
7408 CC = DAG.getConstant(CCode, MVT::i8);
7409 SDNode *User = *Op.getNode()->use_begin();
7410 // Look for an unconditional branch following this conditional branch.
7411 // We need this because we need to reverse the successors in order
7412 // to implement FCMP_OEQ.
7413 if (User->getOpcode() == ISD::BR) {
7414 SDValue FalseBB = User->getOperand(1);
7416 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7417 assert(NewBR == User);
7421 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7422 Chain, Dest, CC, Cmp);
7423 X86::CondCode CCode =
7424 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7425 CCode = X86::GetOppositeBranchCondition(CCode);
7426 CC = DAG.getConstant(CCode, MVT::i8);
7432 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7433 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7434 // It should be transformed during dag combiner except when the condition
7435 // is set by a arithmetics with overflow node.
7436 X86::CondCode CCode =
7437 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7438 CCode = X86::GetOppositeBranchCondition(CCode);
7439 CC = DAG.getConstant(CCode, MVT::i8);
7440 Cond = Cond.getOperand(0).getOperand(1);
7446 // Look pass the truncate.
7447 if (Cond.getOpcode() == ISD::TRUNCATE)
7448 Cond = Cond.getOperand(0);
7450 // We know the result of AND is compared against zero. Try to match
7452 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7453 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7454 if (NewSetCC.getNode()) {
7455 CC = NewSetCC.getOperand(0);
7456 Cond = NewSetCC.getOperand(1);
7463 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7464 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7466 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7467 Chain, Dest, CC, Cond);
7471 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7472 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7473 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7474 // that the guard pages used by the OS virtual memory manager are allocated in
7475 // correct sequence.
7477 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7478 SelectionDAG &DAG) const {
7479 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
7480 "This should be used only on Windows targets");
7481 DebugLoc dl = Op.getDebugLoc();
7484 SDValue Chain = Op.getOperand(0);
7485 SDValue Size = Op.getOperand(1);
7486 // FIXME: Ensure alignment here
7490 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7492 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7493 Flag = Chain.getValue(1);
7495 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
7497 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
7498 Flag = Chain.getValue(1);
7500 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7502 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7503 return DAG.getMergeValues(Ops1, 2, dl);
7506 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7507 MachineFunction &MF = DAG.getMachineFunction();
7508 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7510 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7511 DebugLoc DL = Op.getDebugLoc();
7513 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
7514 // vastart just stores the address of the VarArgsFrameIndex slot into the
7515 // memory location argument.
7516 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7518 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7519 MachinePointerInfo(SV), false, false, 0);
7523 // gp_offset (0 - 6 * 8)
7524 // fp_offset (48 - 48 + 8 * 16)
7525 // overflow_arg_area (point to parameters coming in memory).
7527 SmallVector<SDValue, 8> MemOps;
7528 SDValue FIN = Op.getOperand(1);
7530 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7531 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7533 FIN, MachinePointerInfo(SV), false, false, 0);
7534 MemOps.push_back(Store);
7537 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7538 FIN, DAG.getIntPtrConstant(4));
7539 Store = DAG.getStore(Op.getOperand(0), DL,
7540 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7542 FIN, MachinePointerInfo(SV, 4), false, false, 0);
7543 MemOps.push_back(Store);
7545 // Store ptr to overflow_arg_area
7546 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7547 FIN, DAG.getIntPtrConstant(4));
7548 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7550 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
7551 MachinePointerInfo(SV, 8),
7553 MemOps.push_back(Store);
7555 // Store ptr to reg_save_area.
7556 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7557 FIN, DAG.getIntPtrConstant(8));
7558 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7560 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
7561 MachinePointerInfo(SV, 16), false, false, 0);
7562 MemOps.push_back(Store);
7563 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
7564 &MemOps[0], MemOps.size());
7567 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7568 assert(Subtarget->is64Bit() &&
7569 "LowerVAARG only handles 64-bit va_arg!");
7570 assert((Subtarget->isTargetLinux() ||
7571 Subtarget->isTargetDarwin()) &&
7572 "Unhandled target in LowerVAARG");
7573 assert(Op.getNode()->getNumOperands() == 4);
7574 SDValue Chain = Op.getOperand(0);
7575 SDValue SrcPtr = Op.getOperand(1);
7576 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7577 unsigned Align = Op.getConstantOperandVal(3);
7578 DebugLoc dl = Op.getDebugLoc();
7580 EVT ArgVT = Op.getNode()->getValueType(0);
7581 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
7582 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
7585 // Decide which area this value should be read from.
7586 // TODO: Implement the AMD64 ABI in its entirety. This simple
7587 // selection mechanism works only for the basic types.
7588 if (ArgVT == MVT::f80) {
7589 llvm_unreachable("va_arg for f80 not yet implemented");
7590 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
7591 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
7592 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
7593 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
7595 llvm_unreachable("Unhandled argument type in LowerVAARG");
7599 // Sanity Check: Make sure using fp_offset makes sense.
7600 assert(!UseSoftFloat &&
7601 !(DAG.getMachineFunction()
7602 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
7603 Subtarget->hasSSE1());
7606 // Insert VAARG_64 node into the DAG
7607 // VAARG_64 returns two values: Variable Argument Address, Chain
7608 SmallVector<SDValue, 11> InstOps;
7609 InstOps.push_back(Chain);
7610 InstOps.push_back(SrcPtr);
7611 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
7612 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
7613 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
7614 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
7615 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
7616 VTs, &InstOps[0], InstOps.size(),
7618 MachinePointerInfo(SV),
7623 Chain = VAARG.getValue(1);
7625 // Load the next argument and return it
7626 return DAG.getLoad(ArgVT, dl,
7629 MachinePointerInfo(),
7633 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7634 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7635 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7636 SDValue Chain = Op.getOperand(0);
7637 SDValue DstPtr = Op.getOperand(1);
7638 SDValue SrcPtr = Op.getOperand(2);
7639 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7640 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7641 DebugLoc DL = Op.getDebugLoc();
7643 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
7644 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7646 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
7650 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7651 DebugLoc dl = Op.getDebugLoc();
7652 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7654 default: return SDValue(); // Don't custom lower most intrinsics.
7655 // Comparison intrinsics.
7656 case Intrinsic::x86_sse_comieq_ss:
7657 case Intrinsic::x86_sse_comilt_ss:
7658 case Intrinsic::x86_sse_comile_ss:
7659 case Intrinsic::x86_sse_comigt_ss:
7660 case Intrinsic::x86_sse_comige_ss:
7661 case Intrinsic::x86_sse_comineq_ss:
7662 case Intrinsic::x86_sse_ucomieq_ss:
7663 case Intrinsic::x86_sse_ucomilt_ss:
7664 case Intrinsic::x86_sse_ucomile_ss:
7665 case Intrinsic::x86_sse_ucomigt_ss:
7666 case Intrinsic::x86_sse_ucomige_ss:
7667 case Intrinsic::x86_sse_ucomineq_ss:
7668 case Intrinsic::x86_sse2_comieq_sd:
7669 case Intrinsic::x86_sse2_comilt_sd:
7670 case Intrinsic::x86_sse2_comile_sd:
7671 case Intrinsic::x86_sse2_comigt_sd:
7672 case Intrinsic::x86_sse2_comige_sd:
7673 case Intrinsic::x86_sse2_comineq_sd:
7674 case Intrinsic::x86_sse2_ucomieq_sd:
7675 case Intrinsic::x86_sse2_ucomilt_sd:
7676 case Intrinsic::x86_sse2_ucomile_sd:
7677 case Intrinsic::x86_sse2_ucomigt_sd:
7678 case Intrinsic::x86_sse2_ucomige_sd:
7679 case Intrinsic::x86_sse2_ucomineq_sd: {
7681 ISD::CondCode CC = ISD::SETCC_INVALID;
7684 case Intrinsic::x86_sse_comieq_ss:
7685 case Intrinsic::x86_sse2_comieq_sd:
7689 case Intrinsic::x86_sse_comilt_ss:
7690 case Intrinsic::x86_sse2_comilt_sd:
7694 case Intrinsic::x86_sse_comile_ss:
7695 case Intrinsic::x86_sse2_comile_sd:
7699 case Intrinsic::x86_sse_comigt_ss:
7700 case Intrinsic::x86_sse2_comigt_sd:
7704 case Intrinsic::x86_sse_comige_ss:
7705 case Intrinsic::x86_sse2_comige_sd:
7709 case Intrinsic::x86_sse_comineq_ss:
7710 case Intrinsic::x86_sse2_comineq_sd:
7714 case Intrinsic::x86_sse_ucomieq_ss:
7715 case Intrinsic::x86_sse2_ucomieq_sd:
7716 Opc = X86ISD::UCOMI;
7719 case Intrinsic::x86_sse_ucomilt_ss:
7720 case Intrinsic::x86_sse2_ucomilt_sd:
7721 Opc = X86ISD::UCOMI;
7724 case Intrinsic::x86_sse_ucomile_ss:
7725 case Intrinsic::x86_sse2_ucomile_sd:
7726 Opc = X86ISD::UCOMI;
7729 case Intrinsic::x86_sse_ucomigt_ss:
7730 case Intrinsic::x86_sse2_ucomigt_sd:
7731 Opc = X86ISD::UCOMI;
7734 case Intrinsic::x86_sse_ucomige_ss:
7735 case Intrinsic::x86_sse2_ucomige_sd:
7736 Opc = X86ISD::UCOMI;
7739 case Intrinsic::x86_sse_ucomineq_ss:
7740 case Intrinsic::x86_sse2_ucomineq_sd:
7741 Opc = X86ISD::UCOMI;
7746 SDValue LHS = Op.getOperand(1);
7747 SDValue RHS = Op.getOperand(2);
7748 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7749 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7750 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7751 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7752 DAG.getConstant(X86CC, MVT::i8), Cond);
7753 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7755 // ptest and testp intrinsics. The intrinsic these come from are designed to
7756 // return an integer value, not just an instruction so lower it to the ptest
7757 // or testp pattern and a setcc for the result.
7758 case Intrinsic::x86_sse41_ptestz:
7759 case Intrinsic::x86_sse41_ptestc:
7760 case Intrinsic::x86_sse41_ptestnzc:
7761 case Intrinsic::x86_avx_ptestz_256:
7762 case Intrinsic::x86_avx_ptestc_256:
7763 case Intrinsic::x86_avx_ptestnzc_256:
7764 case Intrinsic::x86_avx_vtestz_ps:
7765 case Intrinsic::x86_avx_vtestc_ps:
7766 case Intrinsic::x86_avx_vtestnzc_ps:
7767 case Intrinsic::x86_avx_vtestz_pd:
7768 case Intrinsic::x86_avx_vtestc_pd:
7769 case Intrinsic::x86_avx_vtestnzc_pd:
7770 case Intrinsic::x86_avx_vtestz_ps_256:
7771 case Intrinsic::x86_avx_vtestc_ps_256:
7772 case Intrinsic::x86_avx_vtestnzc_ps_256:
7773 case Intrinsic::x86_avx_vtestz_pd_256:
7774 case Intrinsic::x86_avx_vtestc_pd_256:
7775 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7776 bool IsTestPacked = false;
7779 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7780 case Intrinsic::x86_avx_vtestz_ps:
7781 case Intrinsic::x86_avx_vtestz_pd:
7782 case Intrinsic::x86_avx_vtestz_ps_256:
7783 case Intrinsic::x86_avx_vtestz_pd_256:
7784 IsTestPacked = true; // Fallthrough
7785 case Intrinsic::x86_sse41_ptestz:
7786 case Intrinsic::x86_avx_ptestz_256:
7788 X86CC = X86::COND_E;
7790 case Intrinsic::x86_avx_vtestc_ps:
7791 case Intrinsic::x86_avx_vtestc_pd:
7792 case Intrinsic::x86_avx_vtestc_ps_256:
7793 case Intrinsic::x86_avx_vtestc_pd_256:
7794 IsTestPacked = true; // Fallthrough
7795 case Intrinsic::x86_sse41_ptestc:
7796 case Intrinsic::x86_avx_ptestc_256:
7798 X86CC = X86::COND_B;
7800 case Intrinsic::x86_avx_vtestnzc_ps:
7801 case Intrinsic::x86_avx_vtestnzc_pd:
7802 case Intrinsic::x86_avx_vtestnzc_ps_256:
7803 case Intrinsic::x86_avx_vtestnzc_pd_256:
7804 IsTestPacked = true; // Fallthrough
7805 case Intrinsic::x86_sse41_ptestnzc:
7806 case Intrinsic::x86_avx_ptestnzc_256:
7808 X86CC = X86::COND_A;
7812 SDValue LHS = Op.getOperand(1);
7813 SDValue RHS = Op.getOperand(2);
7814 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7815 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7816 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7817 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7818 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7821 // Fix vector shift instructions where the last operand is a non-immediate
7823 case Intrinsic::x86_sse2_pslli_w:
7824 case Intrinsic::x86_sse2_pslli_d:
7825 case Intrinsic::x86_sse2_pslli_q:
7826 case Intrinsic::x86_sse2_psrli_w:
7827 case Intrinsic::x86_sse2_psrli_d:
7828 case Intrinsic::x86_sse2_psrli_q:
7829 case Intrinsic::x86_sse2_psrai_w:
7830 case Intrinsic::x86_sse2_psrai_d:
7831 case Intrinsic::x86_mmx_pslli_w:
7832 case Intrinsic::x86_mmx_pslli_d:
7833 case Intrinsic::x86_mmx_pslli_q:
7834 case Intrinsic::x86_mmx_psrli_w:
7835 case Intrinsic::x86_mmx_psrli_d:
7836 case Intrinsic::x86_mmx_psrli_q:
7837 case Intrinsic::x86_mmx_psrai_w:
7838 case Intrinsic::x86_mmx_psrai_d: {
7839 SDValue ShAmt = Op.getOperand(2);
7840 if (isa<ConstantSDNode>(ShAmt))
7843 unsigned NewIntNo = 0;
7844 EVT ShAmtVT = MVT::v4i32;
7846 case Intrinsic::x86_sse2_pslli_w:
7847 NewIntNo = Intrinsic::x86_sse2_psll_w;
7849 case Intrinsic::x86_sse2_pslli_d:
7850 NewIntNo = Intrinsic::x86_sse2_psll_d;
7852 case Intrinsic::x86_sse2_pslli_q:
7853 NewIntNo = Intrinsic::x86_sse2_psll_q;
7855 case Intrinsic::x86_sse2_psrli_w:
7856 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7858 case Intrinsic::x86_sse2_psrli_d:
7859 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7861 case Intrinsic::x86_sse2_psrli_q:
7862 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7864 case Intrinsic::x86_sse2_psrai_w:
7865 NewIntNo = Intrinsic::x86_sse2_psra_w;
7867 case Intrinsic::x86_sse2_psrai_d:
7868 NewIntNo = Intrinsic::x86_sse2_psra_d;
7871 ShAmtVT = MVT::v2i32;
7873 case Intrinsic::x86_mmx_pslli_w:
7874 NewIntNo = Intrinsic::x86_mmx_psll_w;
7876 case Intrinsic::x86_mmx_pslli_d:
7877 NewIntNo = Intrinsic::x86_mmx_psll_d;
7879 case Intrinsic::x86_mmx_pslli_q:
7880 NewIntNo = Intrinsic::x86_mmx_psll_q;
7882 case Intrinsic::x86_mmx_psrli_w:
7883 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7885 case Intrinsic::x86_mmx_psrli_d:
7886 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7888 case Intrinsic::x86_mmx_psrli_q:
7889 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7891 case Intrinsic::x86_mmx_psrai_w:
7892 NewIntNo = Intrinsic::x86_mmx_psra_w;
7894 case Intrinsic::x86_mmx_psrai_d:
7895 NewIntNo = Intrinsic::x86_mmx_psra_d;
7897 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7903 // The vector shift intrinsics with scalars uses 32b shift amounts but
7904 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7908 ShOps[1] = DAG.getConstant(0, MVT::i32);
7909 if (ShAmtVT == MVT::v4i32) {
7910 ShOps[2] = DAG.getUNDEF(MVT::i32);
7911 ShOps[3] = DAG.getUNDEF(MVT::i32);
7912 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7914 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7915 // FIXME this must be lowered to get rid of the invalid type.
7918 EVT VT = Op.getValueType();
7919 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
7920 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7921 DAG.getConstant(NewIntNo, MVT::i32),
7922 Op.getOperand(1), ShAmt);
7927 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7928 SelectionDAG &DAG) const {
7929 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7930 MFI->setReturnAddressIsTaken(true);
7932 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7933 DebugLoc dl = Op.getDebugLoc();
7936 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7938 DAG.getConstant(TD->getPointerSize(),
7939 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7940 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7941 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7943 MachinePointerInfo(), false, false, 0);
7946 // Just load the return address.
7947 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7948 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7949 RetAddrFI, MachinePointerInfo(), false, false, 0);
7952 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7953 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7954 MFI->setFrameAddressIsTaken(true);
7956 EVT VT = Op.getValueType();
7957 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7958 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7959 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7960 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7962 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
7963 MachinePointerInfo(),
7968 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7969 SelectionDAG &DAG) const {
7970 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7973 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7974 MachineFunction &MF = DAG.getMachineFunction();
7975 SDValue Chain = Op.getOperand(0);
7976 SDValue Offset = Op.getOperand(1);
7977 SDValue Handler = Op.getOperand(2);
7978 DebugLoc dl = Op.getDebugLoc();
7980 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
7981 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7983 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7985 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
7986 DAG.getIntPtrConstant(TD->getPointerSize()));
7987 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7988 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
7990 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7991 MF.getRegInfo().addLiveOut(StoreAddrReg);
7993 return DAG.getNode(X86ISD::EH_RETURN, dl,
7995 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7998 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7999 SelectionDAG &DAG) const {
8000 SDValue Root = Op.getOperand(0);
8001 SDValue Trmp = Op.getOperand(1); // trampoline
8002 SDValue FPtr = Op.getOperand(2); // nested function
8003 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
8004 DebugLoc dl = Op.getDebugLoc();
8006 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8008 if (Subtarget->is64Bit()) {
8009 SDValue OutChains[6];
8011 // Large code-model.
8012 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
8013 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
8015 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
8016 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
8018 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
8020 // Load the pointer to the nested function into R11.
8021 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
8022 SDValue Addr = Trmp;
8023 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8024 Addr, MachinePointerInfo(TrmpAddr),
8027 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8028 DAG.getConstant(2, MVT::i64));
8029 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8030 MachinePointerInfo(TrmpAddr, 2),
8033 // Load the 'nest' parameter value into R10.
8034 // R10 is specified in X86CallingConv.td
8035 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8036 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8037 DAG.getConstant(10, MVT::i64));
8038 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8039 Addr, MachinePointerInfo(TrmpAddr, 10),
8042 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8043 DAG.getConstant(12, MVT::i64));
8044 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8045 MachinePointerInfo(TrmpAddr, 12),
8048 // Jump to the nested function.
8049 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8050 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8051 DAG.getConstant(20, MVT::i64));
8052 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8053 Addr, MachinePointerInfo(TrmpAddr, 20),
8056 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8057 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8058 DAG.getConstant(22, MVT::i64));
8059 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8060 MachinePointerInfo(TrmpAddr, 22),
8064 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8065 return DAG.getMergeValues(Ops, 2, dl);
8067 const Function *Func =
8068 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8069 CallingConv::ID CC = Func->getCallingConv();
8074 llvm_unreachable("Unsupported calling convention");
8075 case CallingConv::C:
8076 case CallingConv::X86_StdCall: {
8077 // Pass 'nest' parameter in ECX.
8078 // Must be kept in sync with X86CallingConv.td
8081 // Check that ECX wasn't needed by an 'inreg' parameter.
8082 const FunctionType *FTy = Func->getFunctionType();
8083 const AttrListPtr &Attrs = Func->getAttributes();
8085 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8086 unsigned InRegCount = 0;
8089 for (FunctionType::param_iterator I = FTy->param_begin(),
8090 E = FTy->param_end(); I != E; ++I, ++Idx)
8091 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8092 // FIXME: should only count parameters that are lowered to integers.
8093 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8095 if (InRegCount > 2) {
8096 report_fatal_error("Nest register in use - reduce number of inreg"
8102 case CallingConv::X86_FastCall:
8103 case CallingConv::X86_ThisCall:
8104 case CallingConv::Fast:
8105 // Pass 'nest' parameter in EAX.
8106 // Must be kept in sync with X86CallingConv.td
8111 SDValue OutChains[4];
8114 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8115 DAG.getConstant(10, MVT::i32));
8116 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8118 // This is storing the opcode for MOV32ri.
8119 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8120 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8121 OutChains[0] = DAG.getStore(Root, dl,
8122 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8123 Trmp, MachinePointerInfo(TrmpAddr),
8126 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8127 DAG.getConstant(1, MVT::i32));
8128 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8129 MachinePointerInfo(TrmpAddr, 1),
8132 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8133 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8134 DAG.getConstant(5, MVT::i32));
8135 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8136 MachinePointerInfo(TrmpAddr, 5),
8139 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8140 DAG.getConstant(6, MVT::i32));
8141 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8142 MachinePointerInfo(TrmpAddr, 6),
8146 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8147 return DAG.getMergeValues(Ops, 2, dl);
8151 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8152 SelectionDAG &DAG) const {
8154 The rounding mode is in bits 11:10 of FPSR, and has the following
8161 FLT_ROUNDS, on the other hand, expects the following:
8168 To perform the conversion, we do:
8169 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8172 MachineFunction &MF = DAG.getMachineFunction();
8173 const TargetMachine &TM = MF.getTarget();
8174 const TargetFrameInfo &TFI = *TM.getFrameInfo();
8175 unsigned StackAlignment = TFI.getStackAlignment();
8176 EVT VT = Op.getValueType();
8177 DebugLoc DL = Op.getDebugLoc();
8179 // Save FP Control Word to stack slot
8180 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8181 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8184 MachineMemOperand *MMO =
8185 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8186 MachineMemOperand::MOStore, 2, 2);
8188 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8189 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8190 DAG.getVTList(MVT::Other),
8191 Ops, 2, MVT::i16, MMO);
8193 // Load FP Control Word from stack slot
8194 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8195 MachinePointerInfo(), false, false, 0);
8197 // Transform as necessary
8199 DAG.getNode(ISD::SRL, DL, MVT::i16,
8200 DAG.getNode(ISD::AND, DL, MVT::i16,
8201 CWD, DAG.getConstant(0x800, MVT::i16)),
8202 DAG.getConstant(11, MVT::i8));
8204 DAG.getNode(ISD::SRL, DL, MVT::i16,
8205 DAG.getNode(ISD::AND, DL, MVT::i16,
8206 CWD, DAG.getConstant(0x400, MVT::i16)),
8207 DAG.getConstant(9, MVT::i8));
8210 DAG.getNode(ISD::AND, DL, MVT::i16,
8211 DAG.getNode(ISD::ADD, DL, MVT::i16,
8212 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8213 DAG.getConstant(1, MVT::i16)),
8214 DAG.getConstant(3, MVT::i16));
8217 return DAG.getNode((VT.getSizeInBits() < 16 ?
8218 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8221 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8222 EVT VT = Op.getValueType();
8224 unsigned NumBits = VT.getSizeInBits();
8225 DebugLoc dl = Op.getDebugLoc();
8227 Op = Op.getOperand(0);
8228 if (VT == MVT::i8) {
8229 // Zero extend to i32 since there is not an i8 bsr.
8231 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8234 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8235 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8236 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8238 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8241 DAG.getConstant(NumBits+NumBits-1, OpVT),
8242 DAG.getConstant(X86::COND_E, MVT::i8),
8245 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8247 // Finally xor with NumBits-1.
8248 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8251 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8255 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8256 EVT VT = Op.getValueType();
8258 unsigned NumBits = VT.getSizeInBits();
8259 DebugLoc dl = Op.getDebugLoc();
8261 Op = Op.getOperand(0);
8262 if (VT == MVT::i8) {
8264 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8267 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8268 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8269 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8271 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8274 DAG.getConstant(NumBits, OpVT),
8275 DAG.getConstant(X86::COND_E, MVT::i8),
8278 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8281 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8285 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8286 EVT VT = Op.getValueType();
8287 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8288 DebugLoc dl = Op.getDebugLoc();
8290 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8291 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8292 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8293 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8294 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8296 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8297 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8298 // return AloBlo + AloBhi + AhiBlo;
8300 SDValue A = Op.getOperand(0);
8301 SDValue B = Op.getOperand(1);
8303 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8304 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8305 A, DAG.getConstant(32, MVT::i32));
8306 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8307 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8308 B, DAG.getConstant(32, MVT::i32));
8309 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8310 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8312 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8313 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8315 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8316 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8318 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8319 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8320 AloBhi, DAG.getConstant(32, MVT::i32));
8321 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8322 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8323 AhiBlo, DAG.getConstant(32, MVT::i32));
8324 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8325 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8329 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8330 EVT VT = Op.getValueType();
8331 DebugLoc dl = Op.getDebugLoc();
8332 SDValue R = Op.getOperand(0);
8334 LLVMContext *Context = DAG.getContext();
8336 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8338 if (VT == MVT::v4i32) {
8339 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8340 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8341 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8343 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8345 std::vector<Constant*> CV(4, CI);
8346 Constant *C = ConstantVector::get(CV);
8347 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8348 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8349 MachinePointerInfo::getConstantPool(),
8352 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8353 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
8354 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8355 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8357 if (VT == MVT::v16i8) {
8359 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8360 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8361 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8363 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8364 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8366 std::vector<Constant*> CVM1(16, CM1);
8367 std::vector<Constant*> CVM2(16, CM2);
8368 Constant *C = ConstantVector::get(CVM1);
8369 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8370 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8371 MachinePointerInfo::getConstantPool(),
8374 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8375 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8376 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8377 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8378 DAG.getConstant(4, MVT::i32));
8379 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8380 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8383 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8385 C = ConstantVector::get(CVM2);
8386 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8387 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8388 MachinePointerInfo::getConstantPool(),
8391 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8392 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8393 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8394 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8395 DAG.getConstant(2, MVT::i32));
8396 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8397 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8400 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8402 // return pblendv(r, r+r, a);
8403 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8404 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8405 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8411 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8412 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8413 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8414 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8415 // has only one use.
8416 SDNode *N = Op.getNode();
8417 SDValue LHS = N->getOperand(0);
8418 SDValue RHS = N->getOperand(1);
8419 unsigned BaseOp = 0;
8421 DebugLoc dl = Op.getDebugLoc();
8423 switch (Op.getOpcode()) {
8424 default: llvm_unreachable("Unknown ovf instruction!");
8426 // A subtract of one will be selected as a INC. Note that INC doesn't
8427 // set CF, so we can't do this for UADDO.
8428 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8429 if (C->getAPIntValue() == 1) {
8430 BaseOp = X86ISD::INC;
8434 BaseOp = X86ISD::ADD;
8438 BaseOp = X86ISD::ADD;
8442 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8443 // set CF, so we can't do this for USUBO.
8444 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8445 if (C->getAPIntValue() == 1) {
8446 BaseOp = X86ISD::DEC;
8450 BaseOp = X86ISD::SUB;
8454 BaseOp = X86ISD::SUB;
8458 BaseOp = X86ISD::SMUL;
8462 BaseOp = X86ISD::UMUL;
8467 // Also sets EFLAGS.
8468 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8469 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
8472 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
8473 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
8475 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8479 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8480 DebugLoc dl = Op.getDebugLoc();
8482 if (!Subtarget->hasSSE2()) {
8483 SDValue Chain = Op.getOperand(0);
8484 SDValue Zero = DAG.getConstant(0,
8485 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8487 DAG.getRegister(X86::ESP, MVT::i32), // Base
8488 DAG.getTargetConstant(1, MVT::i8), // Scale
8489 DAG.getRegister(0, MVT::i32), // Index
8490 DAG.getTargetConstant(0, MVT::i32), // Disp
8491 DAG.getRegister(0, MVT::i32), // Segment.
8496 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8497 array_lengthof(Ops));
8498 return SDValue(Res, 0);
8501 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8503 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8505 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8506 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8507 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8508 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8510 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8511 if (!Op1 && !Op2 && !Op3 && Op4)
8512 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8514 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8515 if (Op1 && !Op2 && !Op3 && !Op4)
8516 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8518 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8520 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8523 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8524 EVT T = Op.getValueType();
8525 DebugLoc DL = Op.getDebugLoc();
8528 switch(T.getSimpleVT().SimpleTy) {
8530 assert(false && "Invalid value type!");
8531 case MVT::i8: Reg = X86::AL; size = 1; break;
8532 case MVT::i16: Reg = X86::AX; size = 2; break;
8533 case MVT::i32: Reg = X86::EAX; size = 4; break;
8535 assert(Subtarget->is64Bit() && "Node not type legal!");
8536 Reg = X86::RAX; size = 8;
8539 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
8540 Op.getOperand(2), SDValue());
8541 SDValue Ops[] = { cpIn.getValue(0),
8544 DAG.getTargetConstant(size, MVT::i8),
8546 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8547 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
8548 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
8551 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
8555 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8556 SelectionDAG &DAG) const {
8557 assert(Subtarget->is64Bit() && "Result not type legalized?");
8558 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8559 SDValue TheChain = Op.getOperand(0);
8560 DebugLoc dl = Op.getDebugLoc();
8561 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8562 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8563 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8565 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8566 DAG.getConstant(32, MVT::i8));
8568 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8571 return DAG.getMergeValues(Ops, 2, dl);
8574 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
8575 SelectionDAG &DAG) const {
8576 EVT SrcVT = Op.getOperand(0).getValueType();
8577 EVT DstVT = Op.getValueType();
8578 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8579 Subtarget->hasMMX() && !DisableMMX) &&
8580 "Unexpected custom BITCAST");
8581 assert((DstVT == MVT::i64 ||
8582 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8583 "Unexpected custom BITCAST");
8584 // i64 <=> MMX conversions are Legal.
8585 if (SrcVT==MVT::i64 && DstVT.isVector())
8587 if (DstVT==MVT::i64 && SrcVT.isVector())
8589 // MMX <=> MMX conversions are Legal.
8590 if (SrcVT.isVector() && DstVT.isVector())
8592 // All other conversions need to be expanded.
8595 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8596 SDNode *Node = Op.getNode();
8597 DebugLoc dl = Node->getDebugLoc();
8598 EVT T = Node->getValueType(0);
8599 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8600 DAG.getConstant(0, T), Node->getOperand(2));
8601 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8602 cast<AtomicSDNode>(Node)->getMemoryVT(),
8603 Node->getOperand(0),
8604 Node->getOperand(1), negOp,
8605 cast<AtomicSDNode>(Node)->getSrcValue(),
8606 cast<AtomicSDNode>(Node)->getAlignment());
8609 /// LowerOperation - Provide custom lowering hooks for some operations.
8611 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8612 switch (Op.getOpcode()) {
8613 default: llvm_unreachable("Should not custom lower this!");
8614 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8615 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8616 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8617 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8618 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8619 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8620 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8621 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8622 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8623 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8624 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8625 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8626 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8627 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8628 case ISD::SHL_PARTS:
8629 case ISD::SRA_PARTS:
8630 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8631 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8632 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8633 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8634 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8635 case ISD::FABS: return LowerFABS(Op, DAG);
8636 case ISD::FNEG: return LowerFNEG(Op, DAG);
8637 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8638 case ISD::SETCC: return LowerSETCC(Op, DAG);
8639 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8640 case ISD::SELECT: return LowerSELECT(Op, DAG);
8641 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8642 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8643 case ISD::VASTART: return LowerVASTART(Op, DAG);
8644 case ISD::VAARG: return LowerVAARG(Op, DAG);
8645 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8646 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8647 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8648 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8649 case ISD::FRAME_TO_ARGS_OFFSET:
8650 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8651 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8652 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8653 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8654 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8655 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8656 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8657 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8658 case ISD::SHL: return LowerSHL(Op, DAG);
8664 case ISD::UMULO: return LowerXALUO(Op, DAG);
8665 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8666 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
8670 void X86TargetLowering::
8671 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8672 SelectionDAG &DAG, unsigned NewOp) const {
8673 EVT T = Node->getValueType(0);
8674 DebugLoc dl = Node->getDebugLoc();
8675 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8677 SDValue Chain = Node->getOperand(0);
8678 SDValue In1 = Node->getOperand(1);
8679 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8680 Node->getOperand(2), DAG.getIntPtrConstant(0));
8681 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8682 Node->getOperand(2), DAG.getIntPtrConstant(1));
8683 SDValue Ops[] = { Chain, In1, In2L, In2H };
8684 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8686 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8687 cast<MemSDNode>(Node)->getMemOperand());
8688 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8689 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8690 Results.push_back(Result.getValue(2));
8693 /// ReplaceNodeResults - Replace a node with an illegal result type
8694 /// with a new node built out of custom code.
8695 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8696 SmallVectorImpl<SDValue>&Results,
8697 SelectionDAG &DAG) const {
8698 DebugLoc dl = N->getDebugLoc();
8699 switch (N->getOpcode()) {
8701 assert(false && "Do not know how to custom type legalize this operation!");
8703 case ISD::FP_TO_SINT: {
8704 std::pair<SDValue,SDValue> Vals =
8705 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8706 SDValue FIST = Vals.first, StackSlot = Vals.second;
8707 if (FIST.getNode() != 0) {
8708 EVT VT = N->getValueType(0);
8709 // Return a load from the stack slot.
8710 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
8711 MachinePointerInfo(), false, false, 0));
8715 case ISD::READCYCLECOUNTER: {
8716 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8717 SDValue TheChain = N->getOperand(0);
8718 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8719 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8721 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8723 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8724 SDValue Ops[] = { eax, edx };
8725 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8726 Results.push_back(edx.getValue(1));
8729 case ISD::ATOMIC_CMP_SWAP: {
8730 EVT T = N->getValueType(0);
8731 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8732 SDValue cpInL, cpInH;
8733 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8734 DAG.getConstant(0, MVT::i32));
8735 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8736 DAG.getConstant(1, MVT::i32));
8737 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8738 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8740 SDValue swapInL, swapInH;
8741 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8742 DAG.getConstant(0, MVT::i32));
8743 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8744 DAG.getConstant(1, MVT::i32));
8745 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8747 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8748 swapInL.getValue(1));
8749 SDValue Ops[] = { swapInH.getValue(0),
8751 swapInH.getValue(1) };
8752 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8753 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
8754 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
8756 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8757 MVT::i32, Result.getValue(1));
8758 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8759 MVT::i32, cpOutL.getValue(2));
8760 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8761 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8762 Results.push_back(cpOutH.getValue(1));
8765 case ISD::ATOMIC_LOAD_ADD:
8766 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8768 case ISD::ATOMIC_LOAD_AND:
8769 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8771 case ISD::ATOMIC_LOAD_NAND:
8772 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8774 case ISD::ATOMIC_LOAD_OR:
8775 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8777 case ISD::ATOMIC_LOAD_SUB:
8778 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8780 case ISD::ATOMIC_LOAD_XOR:
8781 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8783 case ISD::ATOMIC_SWAP:
8784 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8789 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8791 default: return NULL;
8792 case X86ISD::BSF: return "X86ISD::BSF";
8793 case X86ISD::BSR: return "X86ISD::BSR";
8794 case X86ISD::SHLD: return "X86ISD::SHLD";
8795 case X86ISD::SHRD: return "X86ISD::SHRD";
8796 case X86ISD::FAND: return "X86ISD::FAND";
8797 case X86ISD::FOR: return "X86ISD::FOR";
8798 case X86ISD::FXOR: return "X86ISD::FXOR";
8799 case X86ISD::FSRL: return "X86ISD::FSRL";
8800 case X86ISD::FILD: return "X86ISD::FILD";
8801 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8802 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8803 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8804 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8805 case X86ISD::FLD: return "X86ISD::FLD";
8806 case X86ISD::FST: return "X86ISD::FST";
8807 case X86ISD::CALL: return "X86ISD::CALL";
8808 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8809 case X86ISD::BT: return "X86ISD::BT";
8810 case X86ISD::CMP: return "X86ISD::CMP";
8811 case X86ISD::COMI: return "X86ISD::COMI";
8812 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8813 case X86ISD::SETCC: return "X86ISD::SETCC";
8814 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8815 case X86ISD::CMOV: return "X86ISD::CMOV";
8816 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8817 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8818 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8819 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8820 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8821 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8822 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8823 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8824 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8825 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8826 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8827 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8828 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8829 case X86ISD::FMAX: return "X86ISD::FMAX";
8830 case X86ISD::FMIN: return "X86ISD::FMIN";
8831 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8832 case X86ISD::FRCP: return "X86ISD::FRCP";
8833 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8834 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8835 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8836 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8837 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8838 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8839 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8840 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8841 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8842 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8843 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8844 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8845 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8846 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8847 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8848 case X86ISD::VSHL: return "X86ISD::VSHL";
8849 case X86ISD::VSRL: return "X86ISD::VSRL";
8850 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8851 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8852 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8853 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8854 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8855 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8856 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8857 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8858 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8859 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8860 case X86ISD::ADD: return "X86ISD::ADD";
8861 case X86ISD::SUB: return "X86ISD::SUB";
8862 case X86ISD::SMUL: return "X86ISD::SMUL";
8863 case X86ISD::UMUL: return "X86ISD::UMUL";
8864 case X86ISD::INC: return "X86ISD::INC";
8865 case X86ISD::DEC: return "X86ISD::DEC";
8866 case X86ISD::OR: return "X86ISD::OR";
8867 case X86ISD::XOR: return "X86ISD::XOR";
8868 case X86ISD::AND: return "X86ISD::AND";
8869 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8870 case X86ISD::PTEST: return "X86ISD::PTEST";
8871 case X86ISD::TESTP: return "X86ISD::TESTP";
8872 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8873 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8874 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8875 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8876 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8877 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8878 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8879 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8880 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8881 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8882 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8883 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8884 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8885 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8886 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8887 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8888 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8889 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8890 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8891 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8892 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8893 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8894 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8895 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8896 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8897 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8898 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8899 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8900 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8901 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8902 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8903 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8904 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8905 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8906 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
8907 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
8911 // isLegalAddressingMode - Return true if the addressing mode represented
8912 // by AM is legal for this target, for a load/store of the specified type.
8913 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
8914 const Type *Ty) const {
8915 // X86 supports extremely general addressing modes.
8916 CodeModel::Model M = getTargetMachine().getCodeModel();
8917 Reloc::Model R = getTargetMachine().getRelocationModel();
8919 // X86 allows a sign-extended 32-bit immediate field as a displacement.
8920 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
8925 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
8927 // If a reference to this global requires an extra load, we can't fold it.
8928 if (isGlobalStubReference(GVFlags))
8931 // If BaseGV requires a register for the PIC base, we cannot also have a
8932 // BaseReg specified.
8933 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
8936 // If lower 4G is not available, then we must use rip-relative addressing.
8937 if ((M != CodeModel::Small || R != Reloc::Static) &&
8938 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
8948 // These scales always work.
8953 // These scales are formed with basereg+scalereg. Only accept if there is
8958 default: // Other stuff never works.
8966 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
8967 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8969 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8970 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8971 if (NumBits1 <= NumBits2)
8976 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8977 if (!VT1.isInteger() || !VT2.isInteger())
8979 unsigned NumBits1 = VT1.getSizeInBits();
8980 unsigned NumBits2 = VT2.getSizeInBits();
8981 if (NumBits1 <= NumBits2)
8986 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
8987 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8988 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
8991 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
8992 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8993 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
8996 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
8997 // i16 instructions are longer (0x66 prefix) and potentially slower.
8998 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
9001 /// isShuffleMaskLegal - Targets can use this to indicate that they only
9002 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
9003 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
9004 /// are assumed to be legal.
9006 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
9008 // Very little shuffling can be done for 64-bit vectors right now.
9009 if (VT.getSizeInBits() == 64)
9010 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
9012 // FIXME: pshufb, blends, shifts.
9013 return (VT.getVectorNumElements() == 2 ||
9014 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
9015 isMOVLMask(M, VT) ||
9016 isSHUFPMask(M, VT) ||
9017 isPSHUFDMask(M, VT) ||
9018 isPSHUFHWMask(M, VT) ||
9019 isPSHUFLWMask(M, VT) ||
9020 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
9021 isUNPCKLMask(M, VT) ||
9022 isUNPCKHMask(M, VT) ||
9023 isUNPCKL_v_undef_Mask(M, VT) ||
9024 isUNPCKH_v_undef_Mask(M, VT));
9028 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
9030 unsigned NumElts = VT.getVectorNumElements();
9031 // FIXME: This collection of masks seems suspect.
9034 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9035 return (isMOVLMask(Mask, VT) ||
9036 isCommutedMOVLMask(Mask, VT, true) ||
9037 isSHUFPMask(Mask, VT) ||
9038 isCommutedSHUFPMask(Mask, VT));
9043 //===----------------------------------------------------------------------===//
9044 // X86 Scheduler Hooks
9045 //===----------------------------------------------------------------------===//
9047 // private utility function
9049 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9050 MachineBasicBlock *MBB,
9057 TargetRegisterClass *RC,
9058 bool invSrc) const {
9059 // For the atomic bitwise operator, we generate
9062 // ld t1 = [bitinstr.addr]
9063 // op t2 = t1, [bitinstr.val]
9065 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9067 // fallthrough -->nextMBB
9068 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9069 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9070 MachineFunction::iterator MBBIter = MBB;
9073 /// First build the CFG
9074 MachineFunction *F = MBB->getParent();
9075 MachineBasicBlock *thisMBB = MBB;
9076 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9077 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9078 F->insert(MBBIter, newMBB);
9079 F->insert(MBBIter, nextMBB);
9081 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9082 nextMBB->splice(nextMBB->begin(), thisMBB,
9083 llvm::next(MachineBasicBlock::iterator(bInstr)),
9085 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9087 // Update thisMBB to fall through to newMBB
9088 thisMBB->addSuccessor(newMBB);
9090 // newMBB jumps to itself and fall through to nextMBB
9091 newMBB->addSuccessor(nextMBB);
9092 newMBB->addSuccessor(newMBB);
9094 // Insert instructions into newMBB based on incoming instruction
9095 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9096 "unexpected number of operands");
9097 DebugLoc dl = bInstr->getDebugLoc();
9098 MachineOperand& destOper = bInstr->getOperand(0);
9099 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9100 int numArgs = bInstr->getNumOperands() - 1;
9101 for (int i=0; i < numArgs; ++i)
9102 argOpers[i] = &bInstr->getOperand(i+1);
9104 // x86 address has 4 operands: base, index, scale, and displacement
9105 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9106 int valArgIndx = lastAddrIndx + 1;
9108 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9109 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9110 for (int i=0; i <= lastAddrIndx; ++i)
9111 (*MIB).addOperand(*argOpers[i]);
9113 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9115 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9120 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9121 assert((argOpers[valArgIndx]->isReg() ||
9122 argOpers[valArgIndx]->isImm()) &&
9124 if (argOpers[valArgIndx]->isReg())
9125 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9127 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9129 (*MIB).addOperand(*argOpers[valArgIndx]);
9131 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9134 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9135 for (int i=0; i <= lastAddrIndx; ++i)
9136 (*MIB).addOperand(*argOpers[i]);
9138 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9139 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9140 bInstr->memoperands_end());
9142 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9146 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9148 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9152 // private utility function: 64 bit atomics on 32 bit host.
9154 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9155 MachineBasicBlock *MBB,
9160 bool invSrc) const {
9161 // For the atomic bitwise operator, we generate
9162 // thisMBB (instructions are in pairs, except cmpxchg8b)
9163 // ld t1,t2 = [bitinstr.addr]
9165 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9166 // op t5, t6 <- out1, out2, [bitinstr.val]
9167 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9168 // mov ECX, EBX <- t5, t6
9169 // mov EAX, EDX <- t1, t2
9170 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9171 // mov t3, t4 <- EAX, EDX
9173 // result in out1, out2
9174 // fallthrough -->nextMBB
9176 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9177 const unsigned LoadOpc = X86::MOV32rm;
9178 const unsigned NotOpc = X86::NOT32r;
9179 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9180 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9181 MachineFunction::iterator MBBIter = MBB;
9184 /// First build the CFG
9185 MachineFunction *F = MBB->getParent();
9186 MachineBasicBlock *thisMBB = MBB;
9187 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9188 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9189 F->insert(MBBIter, newMBB);
9190 F->insert(MBBIter, nextMBB);
9192 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9193 nextMBB->splice(nextMBB->begin(), thisMBB,
9194 llvm::next(MachineBasicBlock::iterator(bInstr)),
9196 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9198 // Update thisMBB to fall through to newMBB
9199 thisMBB->addSuccessor(newMBB);
9201 // newMBB jumps to itself and fall through to nextMBB
9202 newMBB->addSuccessor(nextMBB);
9203 newMBB->addSuccessor(newMBB);
9205 DebugLoc dl = bInstr->getDebugLoc();
9206 // Insert instructions into newMBB based on incoming instruction
9207 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9208 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9209 "unexpected number of operands");
9210 MachineOperand& dest1Oper = bInstr->getOperand(0);
9211 MachineOperand& dest2Oper = bInstr->getOperand(1);
9212 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9213 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9214 argOpers[i] = &bInstr->getOperand(i+2);
9216 // We use some of the operands multiple times, so conservatively just
9217 // clear any kill flags that might be present.
9218 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9219 argOpers[i]->setIsKill(false);
9222 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9223 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9225 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9226 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9227 for (int i=0; i <= lastAddrIndx; ++i)
9228 (*MIB).addOperand(*argOpers[i]);
9229 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9230 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9231 // add 4 to displacement.
9232 for (int i=0; i <= lastAddrIndx-2; ++i)
9233 (*MIB).addOperand(*argOpers[i]);
9234 MachineOperand newOp3 = *(argOpers[3]);
9236 newOp3.setImm(newOp3.getImm()+4);
9238 newOp3.setOffset(newOp3.getOffset()+4);
9239 (*MIB).addOperand(newOp3);
9240 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9242 // t3/4 are defined later, at the bottom of the loop
9243 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9244 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9245 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9246 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9247 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9248 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9250 // The subsequent operations should be using the destination registers of
9251 //the PHI instructions.
9253 t1 = F->getRegInfo().createVirtualRegister(RC);
9254 t2 = F->getRegInfo().createVirtualRegister(RC);
9255 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9256 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9258 t1 = dest1Oper.getReg();
9259 t2 = dest2Oper.getReg();
9262 int valArgIndx = lastAddrIndx + 1;
9263 assert((argOpers[valArgIndx]->isReg() ||
9264 argOpers[valArgIndx]->isImm()) &&
9266 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9267 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9268 if (argOpers[valArgIndx]->isReg())
9269 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9271 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9272 if (regOpcL != X86::MOV32rr)
9274 (*MIB).addOperand(*argOpers[valArgIndx]);
9275 assert(argOpers[valArgIndx + 1]->isReg() ==
9276 argOpers[valArgIndx]->isReg());
9277 assert(argOpers[valArgIndx + 1]->isImm() ==
9278 argOpers[valArgIndx]->isImm());
9279 if (argOpers[valArgIndx + 1]->isReg())
9280 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9282 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9283 if (regOpcH != X86::MOV32rr)
9285 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9287 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9289 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9292 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9294 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9297 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9298 for (int i=0; i <= lastAddrIndx; ++i)
9299 (*MIB).addOperand(*argOpers[i]);
9301 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9302 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9303 bInstr->memoperands_end());
9305 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9306 MIB.addReg(X86::EAX);
9307 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9308 MIB.addReg(X86::EDX);
9311 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9313 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9317 // private utility function
9319 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9320 MachineBasicBlock *MBB,
9321 unsigned cmovOpc) const {
9322 // For the atomic min/max operator, we generate
9325 // ld t1 = [min/max.addr]
9326 // mov t2 = [min/max.val]
9328 // cmov[cond] t2 = t1
9330 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9332 // fallthrough -->nextMBB
9334 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9335 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9336 MachineFunction::iterator MBBIter = MBB;
9339 /// First build the CFG
9340 MachineFunction *F = MBB->getParent();
9341 MachineBasicBlock *thisMBB = MBB;
9342 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9343 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9344 F->insert(MBBIter, newMBB);
9345 F->insert(MBBIter, nextMBB);
9347 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9348 nextMBB->splice(nextMBB->begin(), thisMBB,
9349 llvm::next(MachineBasicBlock::iterator(mInstr)),
9351 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9353 // Update thisMBB to fall through to newMBB
9354 thisMBB->addSuccessor(newMBB);
9356 // newMBB jumps to newMBB and fall through to nextMBB
9357 newMBB->addSuccessor(nextMBB);
9358 newMBB->addSuccessor(newMBB);
9360 DebugLoc dl = mInstr->getDebugLoc();
9361 // Insert instructions into newMBB based on incoming instruction
9362 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9363 "unexpected number of operands");
9364 MachineOperand& destOper = mInstr->getOperand(0);
9365 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9366 int numArgs = mInstr->getNumOperands() - 1;
9367 for (int i=0; i < numArgs; ++i)
9368 argOpers[i] = &mInstr->getOperand(i+1);
9370 // x86 address has 4 operands: base, index, scale, and displacement
9371 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9372 int valArgIndx = lastAddrIndx + 1;
9374 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9375 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9376 for (int i=0; i <= lastAddrIndx; ++i)
9377 (*MIB).addOperand(*argOpers[i]);
9379 // We only support register and immediate values
9380 assert((argOpers[valArgIndx]->isReg() ||
9381 argOpers[valArgIndx]->isImm()) &&
9384 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9385 if (argOpers[valArgIndx]->isReg())
9386 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9388 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9389 (*MIB).addOperand(*argOpers[valArgIndx]);
9391 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9394 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9399 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9400 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9404 // Cmp and exchange if none has modified the memory location
9405 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9406 for (int i=0; i <= lastAddrIndx; ++i)
9407 (*MIB).addOperand(*argOpers[i]);
9409 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9410 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9411 mInstr->memoperands_end());
9413 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9414 MIB.addReg(X86::EAX);
9417 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9419 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9423 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9424 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9427 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9428 unsigned numArgs, bool memArg) const {
9429 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9430 "Target must have SSE4.2 or AVX features enabled");
9432 DebugLoc dl = MI->getDebugLoc();
9433 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9435 if (!Subtarget->hasAVX()) {
9437 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9439 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9442 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9444 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9447 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
9448 for (unsigned i = 0; i < numArgs; ++i) {
9449 MachineOperand &Op = MI->getOperand(i+1);
9450 if (!(Op.isReg() && Op.isImplicit()))
9453 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9456 MI->eraseFromParent();
9461 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
9462 assert(Subtarget->hasSSE3() && "Target must have SSE3 features enabled");
9464 DebugLoc dl = MI->getDebugLoc();
9465 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9467 // Address into RAX/EAX, other two args into ECX, EDX.
9468 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
9469 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
9470 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
9471 for (int i = 0; i < X86::AddrNumOperands; ++i)
9472 MIB.addOperand(MI->getOperand(i));
9474 unsigned ValOps = X86::AddrNumOperands;
9475 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9476 .addReg(MI->getOperand(ValOps).getReg());
9477 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
9478 .addReg(MI->getOperand(ValOps+1).getReg());
9480 // The instruction doesn't actually take any operands though.
9481 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
9483 MI->eraseFromParent(); // The pseudo is gone now.
9488 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
9489 assert(Subtarget->hasSSE3() && "Target must have SSE3 features enabled");
9491 DebugLoc dl = MI->getDebugLoc();
9492 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9494 // First arg in ECX, the second in EAX.
9495 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9496 .addReg(MI->getOperand(0).getReg());
9497 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
9498 .addReg(MI->getOperand(1).getReg());
9500 // The instruction doesn't actually take any operands though.
9501 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
9503 MI->eraseFromParent(); // The pseudo is gone now.
9508 X86TargetLowering::EmitVAARG64WithCustomInserter(
9510 MachineBasicBlock *MBB) const {
9511 // Emit va_arg instruction on X86-64.
9513 // Operands to this pseudo-instruction:
9514 // 0 ) Output : destination address (reg)
9515 // 1-5) Input : va_list address (addr, i64mem)
9516 // 6 ) ArgSize : Size (in bytes) of vararg type
9517 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
9518 // 8 ) Align : Alignment of type
9519 // 9 ) EFLAGS (implicit-def)
9521 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
9522 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
9524 unsigned DestReg = MI->getOperand(0).getReg();
9525 MachineOperand &Base = MI->getOperand(1);
9526 MachineOperand &Scale = MI->getOperand(2);
9527 MachineOperand &Index = MI->getOperand(3);
9528 MachineOperand &Disp = MI->getOperand(4);
9529 MachineOperand &Segment = MI->getOperand(5);
9530 unsigned ArgSize = MI->getOperand(6).getImm();
9531 unsigned ArgMode = MI->getOperand(7).getImm();
9532 unsigned Align = MI->getOperand(8).getImm();
9535 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
9536 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
9537 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
9539 // Machine Information
9540 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9541 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
9542 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
9543 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
9544 DebugLoc DL = MI->getDebugLoc();
9549 // i64 overflow_area (address)
9550 // i64 reg_save_area (address)
9552 // sizeof(va_list) = 24
9553 // alignment(va_list) = 8
9555 unsigned TotalNumIntRegs = 6;
9556 unsigned TotalNumXMMRegs = 8;
9557 bool UseGPOffset = (ArgMode == 1);
9558 bool UseFPOffset = (ArgMode == 2);
9559 unsigned MaxOffset = TotalNumIntRegs * 8 +
9560 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
9562 /* Align ArgSize to a multiple of 8 */
9563 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
9564 bool NeedsAlign = (Align > 8);
9566 MachineBasicBlock *thisMBB = MBB;
9567 MachineBasicBlock *overflowMBB;
9568 MachineBasicBlock *offsetMBB;
9569 MachineBasicBlock *endMBB;
9571 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
9572 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
9573 unsigned OffsetReg = 0;
9575 if (!UseGPOffset && !UseFPOffset) {
9576 // If we only pull from the overflow region, we don't create a branch.
9577 // We don't need to alter control flow.
9578 OffsetDestReg = 0; // unused
9579 OverflowDestReg = DestReg;
9582 overflowMBB = thisMBB;
9585 // First emit code to check if gp_offset (or fp_offset) is below the bound.
9586 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
9587 // If not, pull from overflow_area. (branch to overflowMBB)
9592 // offsetMBB overflowMBB
9597 // Registers for the PHI in endMBB
9598 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
9599 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
9601 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9602 MachineFunction *MF = MBB->getParent();
9603 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9604 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9605 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9607 MachineFunction::iterator MBBIter = MBB;
9610 // Insert the new basic blocks
9611 MF->insert(MBBIter, offsetMBB);
9612 MF->insert(MBBIter, overflowMBB);
9613 MF->insert(MBBIter, endMBB);
9615 // Transfer the remainder of MBB and its successor edges to endMBB.
9616 endMBB->splice(endMBB->begin(), thisMBB,
9617 llvm::next(MachineBasicBlock::iterator(MI)),
9619 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9621 // Make offsetMBB and overflowMBB successors of thisMBB
9622 thisMBB->addSuccessor(offsetMBB);
9623 thisMBB->addSuccessor(overflowMBB);
9625 // endMBB is a successor of both offsetMBB and overflowMBB
9626 offsetMBB->addSuccessor(endMBB);
9627 overflowMBB->addSuccessor(endMBB);
9629 // Load the offset value into a register
9630 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9631 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
9635 .addDisp(Disp, UseFPOffset ? 4 : 0)
9636 .addOperand(Segment)
9637 .setMemRefs(MMOBegin, MMOEnd);
9639 // Check if there is enough room left to pull this argument.
9640 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
9642 .addImm(MaxOffset + 8 - ArgSizeA8);
9644 // Branch to "overflowMBB" if offset >= max
9645 // Fall through to "offsetMBB" otherwise
9646 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
9647 .addMBB(overflowMBB);
9650 // In offsetMBB, emit code to use the reg_save_area.
9652 assert(OffsetReg != 0);
9654 // Read the reg_save_area address.
9655 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
9656 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
9661 .addOperand(Segment)
9662 .setMemRefs(MMOBegin, MMOEnd);
9664 // Zero-extend the offset
9665 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
9666 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
9669 .addImm(X86::sub_32bit);
9671 // Add the offset to the reg_save_area to get the final address.
9672 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
9673 .addReg(OffsetReg64)
9674 .addReg(RegSaveReg);
9676 // Compute the offset for the next argument
9677 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9678 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
9680 .addImm(UseFPOffset ? 16 : 8);
9682 // Store it back into the va_list.
9683 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
9687 .addDisp(Disp, UseFPOffset ? 4 : 0)
9688 .addOperand(Segment)
9689 .addReg(NextOffsetReg)
9690 .setMemRefs(MMOBegin, MMOEnd);
9693 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
9698 // Emit code to use overflow area
9701 // Load the overflow_area address into a register.
9702 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
9703 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
9708 .addOperand(Segment)
9709 .setMemRefs(MMOBegin, MMOEnd);
9711 // If we need to align it, do so. Otherwise, just copy the address
9712 // to OverflowDestReg.
9714 // Align the overflow address
9715 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
9716 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
9718 // aligned_addr = (addr + (align-1)) & ~(align-1)
9719 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
9720 .addReg(OverflowAddrReg)
9723 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
9725 .addImm(~(uint64_t)(Align-1));
9727 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
9728 .addReg(OverflowAddrReg);
9731 // Compute the next overflow address after this argument.
9732 // (the overflow address should be kept 8-byte aligned)
9733 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
9734 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
9735 .addReg(OverflowDestReg)
9738 // Store the new overflow address.
9739 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
9744 .addOperand(Segment)
9745 .addReg(NextAddrReg)
9746 .setMemRefs(MMOBegin, MMOEnd);
9748 // If we branched, emit the PHI to the front of endMBB.
9750 BuildMI(*endMBB, endMBB->begin(), DL,
9751 TII->get(X86::PHI), DestReg)
9752 .addReg(OffsetDestReg).addMBB(offsetMBB)
9753 .addReg(OverflowDestReg).addMBB(overflowMBB);
9756 // Erase the pseudo instruction
9757 MI->eraseFromParent();
9763 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9765 MachineBasicBlock *MBB) const {
9766 // Emit code to save XMM registers to the stack. The ABI says that the
9767 // number of registers to save is given in %al, so it's theoretically
9768 // possible to do an indirect jump trick to avoid saving all of them,
9769 // however this code takes a simpler approach and just executes all
9770 // of the stores if %al is non-zero. It's less code, and it's probably
9771 // easier on the hardware branch predictor, and stores aren't all that
9772 // expensive anyway.
9774 // Create the new basic blocks. One block contains all the XMM stores,
9775 // and one block is the final destination regardless of whether any
9776 // stores were performed.
9777 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9778 MachineFunction *F = MBB->getParent();
9779 MachineFunction::iterator MBBIter = MBB;
9781 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9782 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9783 F->insert(MBBIter, XMMSaveMBB);
9784 F->insert(MBBIter, EndMBB);
9786 // Transfer the remainder of MBB and its successor edges to EndMBB.
9787 EndMBB->splice(EndMBB->begin(), MBB,
9788 llvm::next(MachineBasicBlock::iterator(MI)),
9790 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9792 // The original block will now fall through to the XMM save block.
9793 MBB->addSuccessor(XMMSaveMBB);
9794 // The XMMSaveMBB will fall through to the end block.
9795 XMMSaveMBB->addSuccessor(EndMBB);
9797 // Now add the instructions.
9798 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9799 DebugLoc DL = MI->getDebugLoc();
9801 unsigned CountReg = MI->getOperand(0).getReg();
9802 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9803 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9805 if (!Subtarget->isTargetWin64()) {
9806 // If %al is 0, branch around the XMM save block.
9807 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9808 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9809 MBB->addSuccessor(EndMBB);
9812 // In the XMM save block, save all the XMM argument registers.
9813 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9814 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9815 MachineMemOperand *MMO =
9816 F->getMachineMemOperand(
9817 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
9818 MachineMemOperand::MOStore,
9819 /*Size=*/16, /*Align=*/16);
9820 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9821 .addFrameIndex(RegSaveFrameIndex)
9822 .addImm(/*Scale=*/1)
9823 .addReg(/*IndexReg=*/0)
9824 .addImm(/*Disp=*/Offset)
9825 .addReg(/*Segment=*/0)
9826 .addReg(MI->getOperand(i).getReg())
9827 .addMemOperand(MMO);
9830 MI->eraseFromParent(); // The pseudo instruction is gone now.
9836 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9837 MachineBasicBlock *BB) const {
9838 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9839 DebugLoc DL = MI->getDebugLoc();
9841 // To "insert" a SELECT_CC instruction, we actually have to insert the
9842 // diamond control-flow pattern. The incoming instruction knows the
9843 // destination vreg to set, the condition code register to branch on, the
9844 // true/false values to select between, and a branch opcode to use.
9845 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9846 MachineFunction::iterator It = BB;
9852 // cmpTY ccX, r1, r2
9854 // fallthrough --> copy0MBB
9855 MachineBasicBlock *thisMBB = BB;
9856 MachineFunction *F = BB->getParent();
9857 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9858 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9859 F->insert(It, copy0MBB);
9860 F->insert(It, sinkMBB);
9862 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9863 // live into the sink and copy blocks.
9864 const MachineFunction *MF = BB->getParent();
9865 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9866 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9868 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9869 const MachineOperand &MO = MI->getOperand(I);
9870 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9871 unsigned Reg = MO.getReg();
9872 if (Reg != X86::EFLAGS) continue;
9873 copy0MBB->addLiveIn(Reg);
9874 sinkMBB->addLiveIn(Reg);
9877 // Transfer the remainder of BB and its successor edges to sinkMBB.
9878 sinkMBB->splice(sinkMBB->begin(), BB,
9879 llvm::next(MachineBasicBlock::iterator(MI)),
9881 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9883 // Add the true and fallthrough blocks as its successors.
9884 BB->addSuccessor(copy0MBB);
9885 BB->addSuccessor(sinkMBB);
9887 // Create the conditional branch instruction.
9889 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9890 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9893 // %FalseValue = ...
9894 // # fallthrough to sinkMBB
9895 copy0MBB->addSuccessor(sinkMBB);
9898 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9900 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9901 TII->get(X86::PHI), MI->getOperand(0).getReg())
9902 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9903 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9905 MI->eraseFromParent(); // The pseudo instruction is gone now.
9910 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
9911 MachineBasicBlock *BB) const {
9912 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9913 DebugLoc DL = MI->getDebugLoc();
9915 // The lowering is pretty easy: we're just emitting the call to _alloca. The
9916 // non-trivial part is impdef of ESP.
9917 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
9920 const char *StackProbeSymbol =
9921 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
9923 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
9924 .addExternalSymbol(StackProbeSymbol)
9925 .addReg(X86::EAX, RegState::Implicit)
9926 .addReg(X86::ESP, RegState::Implicit)
9927 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
9928 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
9929 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
9931 MI->eraseFromParent(); // The pseudo instruction is gone now.
9936 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
9937 MachineBasicBlock *BB) const {
9938 // This is pretty easy. We're taking the value that we received from
9939 // our load from the relocation, sticking it in either RDI (x86-64)
9940 // or EAX and doing an indirect call. The return value will then
9941 // be in the normal return register.
9942 const X86InstrInfo *TII
9943 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
9944 DebugLoc DL = MI->getDebugLoc();
9945 MachineFunction *F = BB->getParent();
9947 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
9948 assert(MI->getOperand(3).isGlobal() && "This should be a global");
9950 if (Subtarget->is64Bit()) {
9951 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9952 TII->get(X86::MOV64rm), X86::RDI)
9954 .addImm(0).addReg(0)
9955 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9956 MI->getOperand(3).getTargetFlags())
9958 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
9959 addDirectMem(MIB, X86::RDI);
9960 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
9961 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9962 TII->get(X86::MOV32rm), X86::EAX)
9964 .addImm(0).addReg(0)
9965 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9966 MI->getOperand(3).getTargetFlags())
9968 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9969 addDirectMem(MIB, X86::EAX);
9971 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9972 TII->get(X86::MOV32rm), X86::EAX)
9973 .addReg(TII->getGlobalBaseReg(F))
9974 .addImm(0).addReg(0)
9975 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9976 MI->getOperand(3).getTargetFlags())
9978 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9979 addDirectMem(MIB, X86::EAX);
9982 MI->eraseFromParent(); // The pseudo instruction is gone now.
9987 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
9988 MachineBasicBlock *BB) const {
9989 switch (MI->getOpcode()) {
9990 default: assert(false && "Unexpected instr type to insert");
9991 case X86::WIN_ALLOCA:
9992 return EmitLoweredWinAlloca(MI, BB);
9993 case X86::TLSCall_32:
9994 case X86::TLSCall_64:
9995 return EmitLoweredTLSCall(MI, BB);
9997 case X86::CMOV_FR32:
9998 case X86::CMOV_FR64:
9999 case X86::CMOV_V4F32:
10000 case X86::CMOV_V2F64:
10001 case X86::CMOV_V2I64:
10002 case X86::CMOV_GR16:
10003 case X86::CMOV_GR32:
10004 case X86::CMOV_RFP32:
10005 case X86::CMOV_RFP64:
10006 case X86::CMOV_RFP80:
10007 return EmitLoweredSelect(MI, BB);
10009 case X86::FP32_TO_INT16_IN_MEM:
10010 case X86::FP32_TO_INT32_IN_MEM:
10011 case X86::FP32_TO_INT64_IN_MEM:
10012 case X86::FP64_TO_INT16_IN_MEM:
10013 case X86::FP64_TO_INT32_IN_MEM:
10014 case X86::FP64_TO_INT64_IN_MEM:
10015 case X86::FP80_TO_INT16_IN_MEM:
10016 case X86::FP80_TO_INT32_IN_MEM:
10017 case X86::FP80_TO_INT64_IN_MEM: {
10018 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10019 DebugLoc DL = MI->getDebugLoc();
10021 // Change the floating point control register to use "round towards zero"
10022 // mode when truncating to an integer value.
10023 MachineFunction *F = BB->getParent();
10024 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
10025 addFrameReference(BuildMI(*BB, MI, DL,
10026 TII->get(X86::FNSTCW16m)), CWFrameIdx);
10028 // Load the old value of the high byte of the control word...
10030 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
10031 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
10034 // Set the high part to be round to zero...
10035 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
10038 // Reload the modified control word now...
10039 addFrameReference(BuildMI(*BB, MI, DL,
10040 TII->get(X86::FLDCW16m)), CWFrameIdx);
10042 // Restore the memory image of control word to original value
10043 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
10046 // Get the X86 opcode to use.
10048 switch (MI->getOpcode()) {
10049 default: llvm_unreachable("illegal opcode!");
10050 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
10051 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
10052 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
10053 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
10054 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
10055 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
10056 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
10057 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
10058 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
10062 MachineOperand &Op = MI->getOperand(0);
10064 AM.BaseType = X86AddressMode::RegBase;
10065 AM.Base.Reg = Op.getReg();
10067 AM.BaseType = X86AddressMode::FrameIndexBase;
10068 AM.Base.FrameIndex = Op.getIndex();
10070 Op = MI->getOperand(1);
10072 AM.Scale = Op.getImm();
10073 Op = MI->getOperand(2);
10075 AM.IndexReg = Op.getImm();
10076 Op = MI->getOperand(3);
10077 if (Op.isGlobal()) {
10078 AM.GV = Op.getGlobal();
10080 AM.Disp = Op.getImm();
10082 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
10083 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
10085 // Reload the original control word now.
10086 addFrameReference(BuildMI(*BB, MI, DL,
10087 TII->get(X86::FLDCW16m)), CWFrameIdx);
10089 MI->eraseFromParent(); // The pseudo instruction is gone now.
10092 // String/text processing lowering.
10093 case X86::PCMPISTRM128REG:
10094 case X86::VPCMPISTRM128REG:
10095 return EmitPCMP(MI, BB, 3, false /* in-mem */);
10096 case X86::PCMPISTRM128MEM:
10097 case X86::VPCMPISTRM128MEM:
10098 return EmitPCMP(MI, BB, 3, true /* in-mem */);
10099 case X86::PCMPESTRM128REG:
10100 case X86::VPCMPESTRM128REG:
10101 return EmitPCMP(MI, BB, 5, false /* in mem */);
10102 case X86::PCMPESTRM128MEM:
10103 case X86::VPCMPESTRM128MEM:
10104 return EmitPCMP(MI, BB, 5, true /* in mem */);
10106 // Thread synchronization.
10108 return EmitMonitor(MI, BB);
10110 return EmitMwait(MI, BB);
10112 // Atomic Lowering.
10113 case X86::ATOMAND32:
10114 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10115 X86::AND32ri, X86::MOV32rm,
10117 X86::NOT32r, X86::EAX,
10118 X86::GR32RegisterClass);
10119 case X86::ATOMOR32:
10120 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
10121 X86::OR32ri, X86::MOV32rm,
10123 X86::NOT32r, X86::EAX,
10124 X86::GR32RegisterClass);
10125 case X86::ATOMXOR32:
10126 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
10127 X86::XOR32ri, X86::MOV32rm,
10129 X86::NOT32r, X86::EAX,
10130 X86::GR32RegisterClass);
10131 case X86::ATOMNAND32:
10132 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10133 X86::AND32ri, X86::MOV32rm,
10135 X86::NOT32r, X86::EAX,
10136 X86::GR32RegisterClass, true);
10137 case X86::ATOMMIN32:
10138 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
10139 case X86::ATOMMAX32:
10140 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
10141 case X86::ATOMUMIN32:
10142 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
10143 case X86::ATOMUMAX32:
10144 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
10146 case X86::ATOMAND16:
10147 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10148 X86::AND16ri, X86::MOV16rm,
10150 X86::NOT16r, X86::AX,
10151 X86::GR16RegisterClass);
10152 case X86::ATOMOR16:
10153 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
10154 X86::OR16ri, X86::MOV16rm,
10156 X86::NOT16r, X86::AX,
10157 X86::GR16RegisterClass);
10158 case X86::ATOMXOR16:
10159 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
10160 X86::XOR16ri, X86::MOV16rm,
10162 X86::NOT16r, X86::AX,
10163 X86::GR16RegisterClass);
10164 case X86::ATOMNAND16:
10165 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10166 X86::AND16ri, X86::MOV16rm,
10168 X86::NOT16r, X86::AX,
10169 X86::GR16RegisterClass, true);
10170 case X86::ATOMMIN16:
10171 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
10172 case X86::ATOMMAX16:
10173 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
10174 case X86::ATOMUMIN16:
10175 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
10176 case X86::ATOMUMAX16:
10177 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
10179 case X86::ATOMAND8:
10180 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10181 X86::AND8ri, X86::MOV8rm,
10183 X86::NOT8r, X86::AL,
10184 X86::GR8RegisterClass);
10186 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
10187 X86::OR8ri, X86::MOV8rm,
10189 X86::NOT8r, X86::AL,
10190 X86::GR8RegisterClass);
10191 case X86::ATOMXOR8:
10192 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
10193 X86::XOR8ri, X86::MOV8rm,
10195 X86::NOT8r, X86::AL,
10196 X86::GR8RegisterClass);
10197 case X86::ATOMNAND8:
10198 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10199 X86::AND8ri, X86::MOV8rm,
10201 X86::NOT8r, X86::AL,
10202 X86::GR8RegisterClass, true);
10203 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
10204 // This group is for 64-bit host.
10205 case X86::ATOMAND64:
10206 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10207 X86::AND64ri32, X86::MOV64rm,
10209 X86::NOT64r, X86::RAX,
10210 X86::GR64RegisterClass);
10211 case X86::ATOMOR64:
10212 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
10213 X86::OR64ri32, X86::MOV64rm,
10215 X86::NOT64r, X86::RAX,
10216 X86::GR64RegisterClass);
10217 case X86::ATOMXOR64:
10218 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
10219 X86::XOR64ri32, X86::MOV64rm,
10221 X86::NOT64r, X86::RAX,
10222 X86::GR64RegisterClass);
10223 case X86::ATOMNAND64:
10224 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10225 X86::AND64ri32, X86::MOV64rm,
10227 X86::NOT64r, X86::RAX,
10228 X86::GR64RegisterClass, true);
10229 case X86::ATOMMIN64:
10230 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
10231 case X86::ATOMMAX64:
10232 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
10233 case X86::ATOMUMIN64:
10234 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
10235 case X86::ATOMUMAX64:
10236 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
10238 // This group does 64-bit operations on a 32-bit host.
10239 case X86::ATOMAND6432:
10240 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10241 X86::AND32rr, X86::AND32rr,
10242 X86::AND32ri, X86::AND32ri,
10244 case X86::ATOMOR6432:
10245 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10246 X86::OR32rr, X86::OR32rr,
10247 X86::OR32ri, X86::OR32ri,
10249 case X86::ATOMXOR6432:
10250 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10251 X86::XOR32rr, X86::XOR32rr,
10252 X86::XOR32ri, X86::XOR32ri,
10254 case X86::ATOMNAND6432:
10255 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10256 X86::AND32rr, X86::AND32rr,
10257 X86::AND32ri, X86::AND32ri,
10259 case X86::ATOMADD6432:
10260 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10261 X86::ADD32rr, X86::ADC32rr,
10262 X86::ADD32ri, X86::ADC32ri,
10264 case X86::ATOMSUB6432:
10265 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10266 X86::SUB32rr, X86::SBB32rr,
10267 X86::SUB32ri, X86::SBB32ri,
10269 case X86::ATOMSWAP6432:
10270 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10271 X86::MOV32rr, X86::MOV32rr,
10272 X86::MOV32ri, X86::MOV32ri,
10274 case X86::VASTART_SAVE_XMM_REGS:
10275 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
10277 case X86::VAARG_64:
10278 return EmitVAARG64WithCustomInserter(MI, BB);
10282 //===----------------------------------------------------------------------===//
10283 // X86 Optimization Hooks
10284 //===----------------------------------------------------------------------===//
10286 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10290 const SelectionDAG &DAG,
10291 unsigned Depth) const {
10292 unsigned Opc = Op.getOpcode();
10293 assert((Opc >= ISD::BUILTIN_OP_END ||
10294 Opc == ISD::INTRINSIC_WO_CHAIN ||
10295 Opc == ISD::INTRINSIC_W_CHAIN ||
10296 Opc == ISD::INTRINSIC_VOID) &&
10297 "Should use MaskedValueIsZero if you don't know whether Op"
10298 " is a target node!");
10300 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
10312 // These nodes' second result is a boolean.
10313 if (Op.getResNo() == 0)
10316 case X86ISD::SETCC:
10317 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
10318 Mask.getBitWidth() - 1);
10323 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
10324 unsigned Depth) const {
10325 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
10326 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
10327 return Op.getValueType().getScalarType().getSizeInBits();
10333 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
10334 /// node is a GlobalAddress + offset.
10335 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
10336 const GlobalValue* &GA,
10337 int64_t &Offset) const {
10338 if (N->getOpcode() == X86ISD::Wrapper) {
10339 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
10340 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
10341 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
10345 return TargetLowering::isGAPlusOffset(N, GA, Offset);
10348 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
10349 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
10350 /// if the load addresses are consecutive, non-overlapping, and in the right
10352 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
10353 const TargetLowering &TLI) {
10354 DebugLoc dl = N->getDebugLoc();
10355 EVT VT = N->getValueType(0);
10357 if (VT.getSizeInBits() != 128)
10360 SmallVector<SDValue, 16> Elts;
10361 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
10362 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
10364 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
10367 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
10368 /// generation and convert it from being a bunch of shuffles and extracts
10369 /// to a simple store and scalar loads to extract the elements.
10370 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
10371 const TargetLowering &TLI) {
10372 SDValue InputVector = N->getOperand(0);
10374 // Only operate on vectors of 4 elements, where the alternative shuffling
10375 // gets to be more expensive.
10376 if (InputVector.getValueType() != MVT::v4i32)
10379 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
10380 // single use which is a sign-extend or zero-extend, and all elements are
10382 SmallVector<SDNode *, 4> Uses;
10383 unsigned ExtractedElements = 0;
10384 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
10385 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
10386 if (UI.getUse().getResNo() != InputVector.getResNo())
10389 SDNode *Extract = *UI;
10390 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10393 if (Extract->getValueType(0) != MVT::i32)
10395 if (!Extract->hasOneUse())
10397 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
10398 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
10400 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
10403 // Record which element was extracted.
10404 ExtractedElements |=
10405 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
10407 Uses.push_back(Extract);
10410 // If not all the elements were used, this may not be worthwhile.
10411 if (ExtractedElements != 15)
10414 // Ok, we've now decided to do the transformation.
10415 DebugLoc dl = InputVector.getDebugLoc();
10417 // Store the value to a temporary stack slot.
10418 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
10419 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
10420 MachinePointerInfo(), false, false, 0);
10422 // Replace each use (extract) with a load of the appropriate element.
10423 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
10424 UE = Uses.end(); UI != UE; ++UI) {
10425 SDNode *Extract = *UI;
10427 // Compute the element's address.
10428 SDValue Idx = Extract->getOperand(1);
10430 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
10431 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
10432 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
10434 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
10435 StackPtr, OffsetVal);
10437 // Load the scalar.
10438 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
10439 ScalarAddr, MachinePointerInfo(),
10442 // Replace the exact with the load.
10443 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
10446 // The replacement was made in place; don't return anything.
10450 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
10451 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
10452 const X86Subtarget *Subtarget) {
10453 DebugLoc DL = N->getDebugLoc();
10454 SDValue Cond = N->getOperand(0);
10455 // Get the LHS/RHS of the select.
10456 SDValue LHS = N->getOperand(1);
10457 SDValue RHS = N->getOperand(2);
10459 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
10460 // instructions match the semantics of the common C idiom x<y?x:y but not
10461 // x<=y?x:y, because of how they handle negative zero (which can be
10462 // ignored in unsafe-math mode).
10463 if (Subtarget->hasSSE2() &&
10464 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
10465 Cond.getOpcode() == ISD::SETCC) {
10466 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
10468 unsigned Opcode = 0;
10469 // Check for x CC y ? x : y.
10470 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
10471 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
10475 // Converting this to a min would handle NaNs incorrectly, and swapping
10476 // the operands would cause it to handle comparisons between positive
10477 // and negative zero incorrectly.
10478 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10479 if (!UnsafeFPMath &&
10480 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10482 std::swap(LHS, RHS);
10484 Opcode = X86ISD::FMIN;
10487 // Converting this to a min would handle comparisons between positive
10488 // and negative zero incorrectly.
10489 if (!UnsafeFPMath &&
10490 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
10492 Opcode = X86ISD::FMIN;
10495 // Converting this to a min would handle both negative zeros and NaNs
10496 // incorrectly, but we can swap the operands to fix both.
10497 std::swap(LHS, RHS);
10501 Opcode = X86ISD::FMIN;
10505 // Converting this to a max would handle comparisons between positive
10506 // and negative zero incorrectly.
10507 if (!UnsafeFPMath &&
10508 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
10510 Opcode = X86ISD::FMAX;
10513 // Converting this to a max would handle NaNs incorrectly, and swapping
10514 // the operands would cause it to handle comparisons between positive
10515 // and negative zero incorrectly.
10516 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10517 if (!UnsafeFPMath &&
10518 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10520 std::swap(LHS, RHS);
10522 Opcode = X86ISD::FMAX;
10525 // Converting this to a max would handle both negative zeros and NaNs
10526 // incorrectly, but we can swap the operands to fix both.
10527 std::swap(LHS, RHS);
10531 Opcode = X86ISD::FMAX;
10534 // Check for x CC y ? y : x -- a min/max with reversed arms.
10535 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10536 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10540 // Converting this to a min would handle comparisons between positive
10541 // and negative zero incorrectly, and swapping the operands would
10542 // cause it to handle NaNs incorrectly.
10543 if (!UnsafeFPMath &&
10544 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10545 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10547 std::swap(LHS, RHS);
10549 Opcode = X86ISD::FMIN;
10552 // Converting this to a min would handle NaNs incorrectly.
10553 if (!UnsafeFPMath &&
10554 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10556 Opcode = X86ISD::FMIN;
10559 // Converting this to a min would handle both negative zeros and NaNs
10560 // incorrectly, but we can swap the operands to fix both.
10561 std::swap(LHS, RHS);
10565 Opcode = X86ISD::FMIN;
10569 // Converting this to a max would handle NaNs incorrectly.
10570 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10572 Opcode = X86ISD::FMAX;
10575 // Converting this to a max would handle comparisons between positive
10576 // and negative zero incorrectly, and swapping the operands would
10577 // cause it to handle NaNs incorrectly.
10578 if (!UnsafeFPMath &&
10579 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10580 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10582 std::swap(LHS, RHS);
10584 Opcode = X86ISD::FMAX;
10587 // Converting this to a max would handle both negative zeros and NaNs
10588 // incorrectly, but we can swap the operands to fix both.
10589 std::swap(LHS, RHS);
10593 Opcode = X86ISD::FMAX;
10599 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10602 // If this is a select between two integer constants, try to do some
10604 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10605 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10606 // Don't do this for crazy integer types.
10607 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10608 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10609 // so that TrueC (the true value) is larger than FalseC.
10610 bool NeedsCondInvert = false;
10612 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10613 // Efficiently invertible.
10614 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10615 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10616 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10617 NeedsCondInvert = true;
10618 std::swap(TrueC, FalseC);
10621 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10622 if (FalseC->getAPIntValue() == 0 &&
10623 TrueC->getAPIntValue().isPowerOf2()) {
10624 if (NeedsCondInvert) // Invert the condition if needed.
10625 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10626 DAG.getConstant(1, Cond.getValueType()));
10628 // Zero extend the condition if needed.
10629 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10631 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10632 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10633 DAG.getConstant(ShAmt, MVT::i8));
10636 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10637 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10638 if (NeedsCondInvert) // Invert the condition if needed.
10639 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10640 DAG.getConstant(1, Cond.getValueType()));
10642 // Zero extend the condition if needed.
10643 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10644 FalseC->getValueType(0), Cond);
10645 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10646 SDValue(FalseC, 0));
10649 // Optimize cases that will turn into an LEA instruction. This requires
10650 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10651 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10652 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10653 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10655 bool isFastMultiplier = false;
10657 switch ((unsigned char)Diff) {
10659 case 1: // result = add base, cond
10660 case 2: // result = lea base( , cond*2)
10661 case 3: // result = lea base(cond, cond*2)
10662 case 4: // result = lea base( , cond*4)
10663 case 5: // result = lea base(cond, cond*4)
10664 case 8: // result = lea base( , cond*8)
10665 case 9: // result = lea base(cond, cond*8)
10666 isFastMultiplier = true;
10671 if (isFastMultiplier) {
10672 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10673 if (NeedsCondInvert) // Invert the condition if needed.
10674 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10675 DAG.getConstant(1, Cond.getValueType()));
10677 // Zero extend the condition if needed.
10678 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10680 // Scale the condition by the difference.
10682 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10683 DAG.getConstant(Diff, Cond.getValueType()));
10685 // Add the base if non-zero.
10686 if (FalseC->getAPIntValue() != 0)
10687 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10688 SDValue(FalseC, 0));
10698 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10699 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10700 TargetLowering::DAGCombinerInfo &DCI) {
10701 DebugLoc DL = N->getDebugLoc();
10703 // If the flag operand isn't dead, don't touch this CMOV.
10704 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10707 // If this is a select between two integer constants, try to do some
10708 // optimizations. Note that the operands are ordered the opposite of SELECT
10710 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10711 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10712 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10713 // larger than FalseC (the false value).
10714 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10716 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10717 CC = X86::GetOppositeBranchCondition(CC);
10718 std::swap(TrueC, FalseC);
10721 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10722 // This is efficient for any integer data type (including i8/i16) and
10724 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10725 SDValue Cond = N->getOperand(3);
10726 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10727 DAG.getConstant(CC, MVT::i8), Cond);
10729 // Zero extend the condition if needed.
10730 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10732 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10733 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10734 DAG.getConstant(ShAmt, MVT::i8));
10735 if (N->getNumValues() == 2) // Dead flag value?
10736 return DCI.CombineTo(N, Cond, SDValue());
10740 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10741 // for any integer data type, including i8/i16.
10742 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10743 SDValue Cond = N->getOperand(3);
10744 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10745 DAG.getConstant(CC, MVT::i8), Cond);
10747 // Zero extend the condition if needed.
10748 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10749 FalseC->getValueType(0), Cond);
10750 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10751 SDValue(FalseC, 0));
10753 if (N->getNumValues() == 2) // Dead flag value?
10754 return DCI.CombineTo(N, Cond, SDValue());
10758 // Optimize cases that will turn into an LEA instruction. This requires
10759 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10760 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10761 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10762 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10764 bool isFastMultiplier = false;
10766 switch ((unsigned char)Diff) {
10768 case 1: // result = add base, cond
10769 case 2: // result = lea base( , cond*2)
10770 case 3: // result = lea base(cond, cond*2)
10771 case 4: // result = lea base( , cond*4)
10772 case 5: // result = lea base(cond, cond*4)
10773 case 8: // result = lea base( , cond*8)
10774 case 9: // result = lea base(cond, cond*8)
10775 isFastMultiplier = true;
10780 if (isFastMultiplier) {
10781 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10782 SDValue Cond = N->getOperand(3);
10783 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10784 DAG.getConstant(CC, MVT::i8), Cond);
10785 // Zero extend the condition if needed.
10786 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10788 // Scale the condition by the difference.
10790 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10791 DAG.getConstant(Diff, Cond.getValueType()));
10793 // Add the base if non-zero.
10794 if (FalseC->getAPIntValue() != 0)
10795 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10796 SDValue(FalseC, 0));
10797 if (N->getNumValues() == 2) // Dead flag value?
10798 return DCI.CombineTo(N, Cond, SDValue());
10808 /// PerformMulCombine - Optimize a single multiply with constant into two
10809 /// in order to implement it with two cheaper instructions, e.g.
10810 /// LEA + SHL, LEA + LEA.
10811 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10812 TargetLowering::DAGCombinerInfo &DCI) {
10813 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10816 EVT VT = N->getValueType(0);
10817 if (VT != MVT::i64)
10820 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10823 uint64_t MulAmt = C->getZExtValue();
10824 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10827 uint64_t MulAmt1 = 0;
10828 uint64_t MulAmt2 = 0;
10829 if ((MulAmt % 9) == 0) {
10831 MulAmt2 = MulAmt / 9;
10832 } else if ((MulAmt % 5) == 0) {
10834 MulAmt2 = MulAmt / 5;
10835 } else if ((MulAmt % 3) == 0) {
10837 MulAmt2 = MulAmt / 3;
10840 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10841 DebugLoc DL = N->getDebugLoc();
10843 if (isPowerOf2_64(MulAmt2) &&
10844 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10845 // If second multiplifer is pow2, issue it first. We want the multiply by
10846 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10848 std::swap(MulAmt1, MulAmt2);
10851 if (isPowerOf2_64(MulAmt1))
10852 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10853 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10855 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10856 DAG.getConstant(MulAmt1, VT));
10858 if (isPowerOf2_64(MulAmt2))
10859 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10860 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10862 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10863 DAG.getConstant(MulAmt2, VT));
10865 // Do not add new nodes to DAG combiner worklist.
10866 DCI.CombineTo(N, NewMul, false);
10871 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10872 SDValue N0 = N->getOperand(0);
10873 SDValue N1 = N->getOperand(1);
10874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10875 EVT VT = N0.getValueType();
10877 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10878 // since the result of setcc_c is all zero's or all ones.
10879 if (N1C && N0.getOpcode() == ISD::AND &&
10880 N0.getOperand(1).getOpcode() == ISD::Constant) {
10881 SDValue N00 = N0.getOperand(0);
10882 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10883 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10884 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10885 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10886 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10887 APInt ShAmt = N1C->getAPIntValue();
10888 Mask = Mask.shl(ShAmt);
10890 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10891 N00, DAG.getConstant(Mask, VT));
10898 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10900 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10901 const X86Subtarget *Subtarget) {
10902 EVT VT = N->getValueType(0);
10903 if (!VT.isVector() && VT.isInteger() &&
10904 N->getOpcode() == ISD::SHL)
10905 return PerformSHLCombine(N, DAG);
10907 // On X86 with SSE2 support, we can transform this to a vector shift if
10908 // all elements are shifted by the same amount. We can't do this in legalize
10909 // because the a constant vector is typically transformed to a constant pool
10910 // so we have no knowledge of the shift amount.
10911 if (!Subtarget->hasSSE2())
10914 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
10917 SDValue ShAmtOp = N->getOperand(1);
10918 EVT EltVT = VT.getVectorElementType();
10919 DebugLoc DL = N->getDebugLoc();
10920 SDValue BaseShAmt = SDValue();
10921 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
10922 unsigned NumElts = VT.getVectorNumElements();
10924 for (; i != NumElts; ++i) {
10925 SDValue Arg = ShAmtOp.getOperand(i);
10926 if (Arg.getOpcode() == ISD::UNDEF) continue;
10930 for (; i != NumElts; ++i) {
10931 SDValue Arg = ShAmtOp.getOperand(i);
10932 if (Arg.getOpcode() == ISD::UNDEF) continue;
10933 if (Arg != BaseShAmt) {
10937 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
10938 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
10939 SDValue InVec = ShAmtOp.getOperand(0);
10940 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
10941 unsigned NumElts = InVec.getValueType().getVectorNumElements();
10943 for (; i != NumElts; ++i) {
10944 SDValue Arg = InVec.getOperand(i);
10945 if (Arg.getOpcode() == ISD::UNDEF) continue;
10949 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
10950 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
10951 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
10952 if (C->getZExtValue() == SplatIdx)
10953 BaseShAmt = InVec.getOperand(1);
10956 if (BaseShAmt.getNode() == 0)
10957 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
10958 DAG.getIntPtrConstant(0));
10962 // The shift amount is an i32.
10963 if (EltVT.bitsGT(MVT::i32))
10964 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
10965 else if (EltVT.bitsLT(MVT::i32))
10966 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
10968 // The shift amount is identical so we can do a vector shift.
10969 SDValue ValOp = N->getOperand(0);
10970 switch (N->getOpcode()) {
10972 llvm_unreachable("Unknown shift opcode!");
10975 if (VT == MVT::v2i64)
10976 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10977 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10979 if (VT == MVT::v4i32)
10980 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10981 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10983 if (VT == MVT::v8i16)
10984 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10985 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10989 if (VT == MVT::v4i32)
10990 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10991 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10993 if (VT == MVT::v8i16)
10994 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10995 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10999 if (VT == MVT::v2i64)
11000 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11001 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
11003 if (VT == MVT::v4i32)
11004 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11005 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
11007 if (VT == MVT::v8i16)
11008 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11009 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
11016 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
11017 TargetLowering::DAGCombinerInfo &DCI,
11018 const X86Subtarget *Subtarget) {
11019 if (DCI.isBeforeLegalizeOps())
11022 EVT VT = N->getValueType(0);
11023 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
11026 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
11027 SDValue N0 = N->getOperand(0);
11028 SDValue N1 = N->getOperand(1);
11029 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
11031 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
11033 if (!N0.hasOneUse() || !N1.hasOneUse())
11036 SDValue ShAmt0 = N0.getOperand(1);
11037 if (ShAmt0.getValueType() != MVT::i8)
11039 SDValue ShAmt1 = N1.getOperand(1);
11040 if (ShAmt1.getValueType() != MVT::i8)
11042 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
11043 ShAmt0 = ShAmt0.getOperand(0);
11044 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
11045 ShAmt1 = ShAmt1.getOperand(0);
11047 DebugLoc DL = N->getDebugLoc();
11048 unsigned Opc = X86ISD::SHLD;
11049 SDValue Op0 = N0.getOperand(0);
11050 SDValue Op1 = N1.getOperand(0);
11051 if (ShAmt0.getOpcode() == ISD::SUB) {
11052 Opc = X86ISD::SHRD;
11053 std::swap(Op0, Op1);
11054 std::swap(ShAmt0, ShAmt1);
11057 unsigned Bits = VT.getSizeInBits();
11058 if (ShAmt1.getOpcode() == ISD::SUB) {
11059 SDValue Sum = ShAmt1.getOperand(0);
11060 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
11061 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
11062 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
11063 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
11064 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
11065 return DAG.getNode(Opc, DL, VT,
11067 DAG.getNode(ISD::TRUNCATE, DL,
11070 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
11071 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
11073 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
11074 return DAG.getNode(Opc, DL, VT,
11075 N0.getOperand(0), N1.getOperand(0),
11076 DAG.getNode(ISD::TRUNCATE, DL,
11083 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
11084 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
11085 const X86Subtarget *Subtarget) {
11086 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
11087 // the FP state in cases where an emms may be missing.
11088 // A preferable solution to the general problem is to figure out the right
11089 // places to insert EMMS. This qualifies as a quick hack.
11091 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
11092 StoreSDNode *St = cast<StoreSDNode>(N);
11093 EVT VT = St->getValue().getValueType();
11094 if (VT.getSizeInBits() != 64)
11097 const Function *F = DAG.getMachineFunction().getFunction();
11098 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
11099 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
11100 && Subtarget->hasSSE2();
11101 if ((VT.isVector() ||
11102 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
11103 isa<LoadSDNode>(St->getValue()) &&
11104 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
11105 St->getChain().hasOneUse() && !St->isVolatile()) {
11106 SDNode* LdVal = St->getValue().getNode();
11107 LoadSDNode *Ld = 0;
11108 int TokenFactorIndex = -1;
11109 SmallVector<SDValue, 8> Ops;
11110 SDNode* ChainVal = St->getChain().getNode();
11111 // Must be a store of a load. We currently handle two cases: the load
11112 // is a direct child, and it's under an intervening TokenFactor. It is
11113 // possible to dig deeper under nested TokenFactors.
11114 if (ChainVal == LdVal)
11115 Ld = cast<LoadSDNode>(St->getChain());
11116 else if (St->getValue().hasOneUse() &&
11117 ChainVal->getOpcode() == ISD::TokenFactor) {
11118 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
11119 if (ChainVal->getOperand(i).getNode() == LdVal) {
11120 TokenFactorIndex = i;
11121 Ld = cast<LoadSDNode>(St->getValue());
11123 Ops.push_back(ChainVal->getOperand(i));
11127 if (!Ld || !ISD::isNormalLoad(Ld))
11130 // If this is not the MMX case, i.e. we are just turning i64 load/store
11131 // into f64 load/store, avoid the transformation if there are multiple
11132 // uses of the loaded value.
11133 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
11136 DebugLoc LdDL = Ld->getDebugLoc();
11137 DebugLoc StDL = N->getDebugLoc();
11138 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
11139 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
11141 if (Subtarget->is64Bit() || F64IsLegal) {
11142 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
11143 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
11144 Ld->getPointerInfo(), Ld->isVolatile(),
11145 Ld->isNonTemporal(), Ld->getAlignment());
11146 SDValue NewChain = NewLd.getValue(1);
11147 if (TokenFactorIndex != -1) {
11148 Ops.push_back(NewChain);
11149 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11152 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
11153 St->getPointerInfo(),
11154 St->isVolatile(), St->isNonTemporal(),
11155 St->getAlignment());
11158 // Otherwise, lower to two pairs of 32-bit loads / stores.
11159 SDValue LoAddr = Ld->getBasePtr();
11160 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
11161 DAG.getConstant(4, MVT::i32));
11163 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
11164 Ld->getPointerInfo(),
11165 Ld->isVolatile(), Ld->isNonTemporal(),
11166 Ld->getAlignment());
11167 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
11168 Ld->getPointerInfo().getWithOffset(4),
11169 Ld->isVolatile(), Ld->isNonTemporal(),
11170 MinAlign(Ld->getAlignment(), 4));
11172 SDValue NewChain = LoLd.getValue(1);
11173 if (TokenFactorIndex != -1) {
11174 Ops.push_back(LoLd);
11175 Ops.push_back(HiLd);
11176 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11180 LoAddr = St->getBasePtr();
11181 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
11182 DAG.getConstant(4, MVT::i32));
11184 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
11185 St->getPointerInfo(),
11186 St->isVolatile(), St->isNonTemporal(),
11187 St->getAlignment());
11188 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
11189 St->getPointerInfo().getWithOffset(4),
11191 St->isNonTemporal(),
11192 MinAlign(St->getAlignment(), 4));
11193 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
11198 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
11199 /// X86ISD::FXOR nodes.
11200 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
11201 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
11202 // F[X]OR(0.0, x) -> x
11203 // F[X]OR(x, 0.0) -> x
11204 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11205 if (C->getValueAPF().isPosZero())
11206 return N->getOperand(1);
11207 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11208 if (C->getValueAPF().isPosZero())
11209 return N->getOperand(0);
11213 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
11214 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
11215 // FAND(0.0, x) -> 0.0
11216 // FAND(x, 0.0) -> 0.0
11217 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11218 if (C->getValueAPF().isPosZero())
11219 return N->getOperand(0);
11220 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11221 if (C->getValueAPF().isPosZero())
11222 return N->getOperand(1);
11226 static SDValue PerformBTCombine(SDNode *N,
11228 TargetLowering::DAGCombinerInfo &DCI) {
11229 // BT ignores high bits in the bit index operand.
11230 SDValue Op1 = N->getOperand(1);
11231 if (Op1.hasOneUse()) {
11232 unsigned BitWidth = Op1.getValueSizeInBits();
11233 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
11234 APInt KnownZero, KnownOne;
11235 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
11236 !DCI.isBeforeLegalizeOps());
11237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11238 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
11239 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
11240 DCI.CommitTargetLoweringOpt(TLO);
11245 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
11246 SDValue Op = N->getOperand(0);
11247 if (Op.getOpcode() == ISD::BITCAST)
11248 Op = Op.getOperand(0);
11249 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
11250 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
11251 VT.getVectorElementType().getSizeInBits() ==
11252 OpVT.getVectorElementType().getSizeInBits()) {
11253 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
11258 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
11259 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
11260 // (and (i32 x86isd::setcc_carry), 1)
11261 // This eliminates the zext. This transformation is necessary because
11262 // ISD::SETCC is always legalized to i8.
11263 DebugLoc dl = N->getDebugLoc();
11264 SDValue N0 = N->getOperand(0);
11265 EVT VT = N->getValueType(0);
11266 if (N0.getOpcode() == ISD::AND &&
11268 N0.getOperand(0).hasOneUse()) {
11269 SDValue N00 = N0.getOperand(0);
11270 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
11272 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11273 if (!C || C->getZExtValue() != 1)
11275 return DAG.getNode(ISD::AND, dl, VT,
11276 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
11277 N00.getOperand(0), N00.getOperand(1)),
11278 DAG.getConstant(1, VT));
11284 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
11285 DAGCombinerInfo &DCI) const {
11286 SelectionDAG &DAG = DCI.DAG;
11287 switch (N->getOpcode()) {
11289 case ISD::EXTRACT_VECTOR_ELT:
11290 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
11291 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
11292 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
11293 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
11296 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
11297 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
11298 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
11300 case X86ISD::FOR: return PerformFORCombine(N, DAG);
11301 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
11302 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
11303 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
11304 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
11305 case X86ISD::SHUFPS: // Handle all target specific shuffles
11306 case X86ISD::SHUFPD:
11307 case X86ISD::PALIGN:
11308 case X86ISD::PUNPCKHBW:
11309 case X86ISD::PUNPCKHWD:
11310 case X86ISD::PUNPCKHDQ:
11311 case X86ISD::PUNPCKHQDQ:
11312 case X86ISD::UNPCKHPS:
11313 case X86ISD::UNPCKHPD:
11314 case X86ISD::PUNPCKLBW:
11315 case X86ISD::PUNPCKLWD:
11316 case X86ISD::PUNPCKLDQ:
11317 case X86ISD::PUNPCKLQDQ:
11318 case X86ISD::UNPCKLPS:
11319 case X86ISD::UNPCKLPD:
11320 case X86ISD::MOVHLPS:
11321 case X86ISD::MOVLHPS:
11322 case X86ISD::PSHUFD:
11323 case X86ISD::PSHUFHW:
11324 case X86ISD::PSHUFLW:
11325 case X86ISD::MOVSS:
11326 case X86ISD::MOVSD:
11327 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
11333 /// isTypeDesirableForOp - Return true if the target has native support for
11334 /// the specified value type and it is 'desirable' to use the type for the
11335 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
11336 /// instruction encodings are longer and some i16 instructions are slow.
11337 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
11338 if (!isTypeLegal(VT))
11340 if (VT != MVT::i16)
11347 case ISD::SIGN_EXTEND:
11348 case ISD::ZERO_EXTEND:
11349 case ISD::ANY_EXTEND:
11362 /// IsDesirableToPromoteOp - This method query the target whether it is
11363 /// beneficial for dag combiner to promote the specified node. If true, it
11364 /// should return the desired promotion type by reference.
11365 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
11366 EVT VT = Op.getValueType();
11367 if (VT != MVT::i16)
11370 bool Promote = false;
11371 bool Commute = false;
11372 switch (Op.getOpcode()) {
11375 LoadSDNode *LD = cast<LoadSDNode>(Op);
11376 // If the non-extending load has a single use and it's not live out, then it
11377 // might be folded.
11378 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
11379 Op.hasOneUse()*/) {
11380 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11381 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
11382 // The only case where we'd want to promote LOAD (rather then it being
11383 // promoted as an operand is when it's only use is liveout.
11384 if (UI->getOpcode() != ISD::CopyToReg)
11391 case ISD::SIGN_EXTEND:
11392 case ISD::ZERO_EXTEND:
11393 case ISD::ANY_EXTEND:
11398 SDValue N0 = Op.getOperand(0);
11399 // Look out for (store (shl (load), x)).
11400 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
11413 SDValue N0 = Op.getOperand(0);
11414 SDValue N1 = Op.getOperand(1);
11415 if (!Commute && MayFoldLoad(N1))
11417 // Avoid disabling potential load folding opportunities.
11418 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
11420 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
11430 //===----------------------------------------------------------------------===//
11431 // X86 Inline Assembly Support
11432 //===----------------------------------------------------------------------===//
11434 static bool LowerToBSwap(CallInst *CI) {
11435 // FIXME: this should verify that we are targetting a 486 or better. If not,
11436 // we will turn this bswap into something that will be lowered to logical ops
11437 // instead of emitting the bswap asm. For now, we don't support 486 or lower
11438 // so don't worry about this.
11440 // Verify this is a simple bswap.
11441 if (CI->getNumArgOperands() != 1 ||
11442 CI->getType() != CI->getArgOperand(0)->getType() ||
11443 !CI->getType()->isIntegerTy())
11446 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11447 if (!Ty || Ty->getBitWidth() % 16 != 0)
11450 // Okay, we can do this xform, do so now.
11451 const Type *Tys[] = { Ty };
11452 Module *M = CI->getParent()->getParent()->getParent();
11453 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
11455 Value *Op = CI->getArgOperand(0);
11456 Op = CallInst::Create(Int, Op, CI->getName(), CI);
11458 CI->replaceAllUsesWith(Op);
11459 CI->eraseFromParent();
11463 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
11464 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11465 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
11467 std::string AsmStr = IA->getAsmString();
11469 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
11470 SmallVector<StringRef, 4> AsmPieces;
11471 SplitString(AsmStr, AsmPieces, ";\n");
11473 switch (AsmPieces.size()) {
11474 default: return false;
11476 AsmStr = AsmPieces[0];
11478 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
11481 if (AsmPieces.size() == 2 &&
11482 (AsmPieces[0] == "bswap" ||
11483 AsmPieces[0] == "bswapq" ||
11484 AsmPieces[0] == "bswapl") &&
11485 (AsmPieces[1] == "$0" ||
11486 AsmPieces[1] == "${0:q}")) {
11487 // No need to check constraints, nothing other than the equivalent of
11488 // "=r,0" would be valid here.
11489 return LowerToBSwap(CI);
11491 // rorw $$8, ${0:w} --> llvm.bswap.i16
11492 if (CI->getType()->isIntegerTy(16) &&
11493 AsmPieces.size() == 3 &&
11494 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
11495 AsmPieces[1] == "$$8," &&
11496 AsmPieces[2] == "${0:w}" &&
11497 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11499 const std::string &Constraints = IA->getConstraintString();
11500 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11501 std::sort(AsmPieces.begin(), AsmPieces.end());
11502 if (AsmPieces.size() == 4 &&
11503 AsmPieces[0] == "~{cc}" &&
11504 AsmPieces[1] == "~{dirflag}" &&
11505 AsmPieces[2] == "~{flags}" &&
11506 AsmPieces[3] == "~{fpsr}") {
11507 return LowerToBSwap(CI);
11512 if (CI->getType()->isIntegerTy(32) &&
11513 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11514 SmallVector<StringRef, 4> Words;
11515 SplitString(AsmPieces[0], Words, " \t,");
11516 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11517 Words[2] == "${0:w}") {
11519 SplitString(AsmPieces[1], Words, " \t,");
11520 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
11521 Words[2] == "$0") {
11523 SplitString(AsmPieces[2], Words, " \t,");
11524 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11525 Words[2] == "${0:w}") {
11527 const std::string &Constraints = IA->getConstraintString();
11528 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11529 std::sort(AsmPieces.begin(), AsmPieces.end());
11530 if (AsmPieces.size() == 4 &&
11531 AsmPieces[0] == "~{cc}" &&
11532 AsmPieces[1] == "~{dirflag}" &&
11533 AsmPieces[2] == "~{flags}" &&
11534 AsmPieces[3] == "~{fpsr}") {
11535 return LowerToBSwap(CI);
11541 if (CI->getType()->isIntegerTy(64) &&
11542 Constraints.size() >= 2 &&
11543 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11544 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11545 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11546 SmallVector<StringRef, 4> Words;
11547 SplitString(AsmPieces[0], Words, " \t");
11548 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11550 SplitString(AsmPieces[1], Words, " \t");
11551 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11553 SplitString(AsmPieces[2], Words, " \t,");
11554 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11555 Words[2] == "%edx") {
11556 return LowerToBSwap(CI);
11568 /// getConstraintType - Given a constraint letter, return the type of
11569 /// constraint it is for this target.
11570 X86TargetLowering::ConstraintType
11571 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11572 if (Constraint.size() == 1) {
11573 switch (Constraint[0]) {
11583 return C_RegisterClass;
11607 return TargetLowering::getConstraintType(Constraint);
11610 /// Examine constraint type and operand type and determine a weight value.
11611 /// This object must already have been set up with the operand type
11612 /// and the current alternative constraint selected.
11613 TargetLowering::ConstraintWeight
11614 X86TargetLowering::getSingleConstraintMatchWeight(
11615 AsmOperandInfo &info, const char *constraint) const {
11616 ConstraintWeight weight = CW_Invalid;
11617 Value *CallOperandVal = info.CallOperandVal;
11618 // If we don't have a value, we can't do a match,
11619 // but allow it at the lowest weight.
11620 if (CallOperandVal == NULL)
11622 const Type *type = CallOperandVal->getType();
11623 // Look at the constraint type.
11624 switch (*constraint) {
11626 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11637 if (CallOperandVal->getType()->isIntegerTy())
11638 weight = CW_SpecificReg;
11643 if (type->isFloatingPointTy())
11644 weight = CW_SpecificReg;
11647 if (type->isX86_MMXTy() && !DisableMMX && Subtarget->hasMMX())
11648 weight = CW_SpecificReg;
11652 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1())
11653 weight = CW_Register;
11656 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
11657 if (C->getZExtValue() <= 31)
11658 weight = CW_Constant;
11662 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11663 if (C->getZExtValue() <= 63)
11664 weight = CW_Constant;
11668 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11669 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
11670 weight = CW_Constant;
11674 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11675 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
11676 weight = CW_Constant;
11680 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11681 if (C->getZExtValue() <= 3)
11682 weight = CW_Constant;
11686 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11687 if (C->getZExtValue() <= 0xff)
11688 weight = CW_Constant;
11693 if (dyn_cast<ConstantFP>(CallOperandVal)) {
11694 weight = CW_Constant;
11698 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11699 if ((C->getSExtValue() >= -0x80000000LL) &&
11700 (C->getSExtValue() <= 0x7fffffffLL))
11701 weight = CW_Constant;
11705 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11706 if (C->getZExtValue() <= 0xffffffff)
11707 weight = CW_Constant;
11714 /// LowerXConstraint - try to replace an X constraint, which matches anything,
11715 /// with another that has more specific requirements based on the type of the
11716 /// corresponding operand.
11717 const char *X86TargetLowering::
11718 LowerXConstraint(EVT ConstraintVT) const {
11719 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
11720 // 'f' like normal targets.
11721 if (ConstraintVT.isFloatingPoint()) {
11722 if (Subtarget->hasSSE2())
11724 if (Subtarget->hasSSE1())
11728 return TargetLowering::LowerXConstraint(ConstraintVT);
11731 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11732 /// vector. If it is invalid, don't add anything to Ops.
11733 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11735 std::vector<SDValue>&Ops,
11736 SelectionDAG &DAG) const {
11737 SDValue Result(0, 0);
11739 switch (Constraint) {
11742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11743 if (C->getZExtValue() <= 31) {
11744 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11750 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11751 if (C->getZExtValue() <= 63) {
11752 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11758 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11759 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
11760 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11766 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11767 if (C->getZExtValue() <= 255) {
11768 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11774 // 32-bit signed value
11775 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11776 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11777 C->getSExtValue())) {
11778 // Widen to 64 bits here to get it sign extended.
11779 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
11782 // FIXME gcc accepts some relocatable values here too, but only in certain
11783 // memory models; it's complicated.
11788 // 32-bit unsigned value
11789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11790 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11791 C->getZExtValue())) {
11792 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11796 // FIXME gcc accepts some relocatable values here too, but only in certain
11797 // memory models; it's complicated.
11801 // Literal immediates are always ok.
11802 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
11803 // Widen to 64 bits here to get it sign extended.
11804 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
11808 // In any sort of PIC mode addresses need to be computed at runtime by
11809 // adding in a register or some sort of table lookup. These can't
11810 // be used as immediates.
11811 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
11814 // If we are in non-pic codegen mode, we allow the address of a global (with
11815 // an optional displacement) to be used with 'i'.
11816 GlobalAddressSDNode *GA = 0;
11817 int64_t Offset = 0;
11819 // Match either (GA), (GA+C), (GA+C1+C2), etc.
11821 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
11822 Offset += GA->getOffset();
11824 } else if (Op.getOpcode() == ISD::ADD) {
11825 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11826 Offset += C->getZExtValue();
11827 Op = Op.getOperand(0);
11830 } else if (Op.getOpcode() == ISD::SUB) {
11831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11832 Offset += -C->getZExtValue();
11833 Op = Op.getOperand(0);
11838 // Otherwise, this isn't something we can handle, reject it.
11842 const GlobalValue *GV = GA->getGlobal();
11843 // If we require an extra load to get this address, as in PIC mode, we
11844 // can't accept it.
11845 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
11846 getTargetMachine())))
11849 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
11850 GA->getValueType(0), Offset);
11855 if (Result.getNode()) {
11856 Ops.push_back(Result);
11859 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11862 std::vector<unsigned> X86TargetLowering::
11863 getRegClassForInlineAsmConstraint(const std::string &Constraint,
11865 if (Constraint.size() == 1) {
11866 // FIXME: not handling fp-stack yet!
11867 switch (Constraint[0]) { // GCC X86 Constraint Letters
11868 default: break; // Unknown constraint letter
11869 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
11870 if (Subtarget->is64Bit()) {
11871 if (VT == MVT::i32)
11872 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
11873 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
11874 X86::R10D,X86::R11D,X86::R12D,
11875 X86::R13D,X86::R14D,X86::R15D,
11876 X86::EBP, X86::ESP, 0);
11877 else if (VT == MVT::i16)
11878 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
11879 X86::SI, X86::DI, X86::R8W,X86::R9W,
11880 X86::R10W,X86::R11W,X86::R12W,
11881 X86::R13W,X86::R14W,X86::R15W,
11882 X86::BP, X86::SP, 0);
11883 else if (VT == MVT::i8)
11884 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
11885 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
11886 X86::R10B,X86::R11B,X86::R12B,
11887 X86::R13B,X86::R14B,X86::R15B,
11888 X86::BPL, X86::SPL, 0);
11890 else if (VT == MVT::i64)
11891 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
11892 X86::RSI, X86::RDI, X86::R8, X86::R9,
11893 X86::R10, X86::R11, X86::R12,
11894 X86::R13, X86::R14, X86::R15,
11895 X86::RBP, X86::RSP, 0);
11899 // 32-bit fallthrough
11900 case 'Q': // Q_REGS
11901 if (VT == MVT::i32)
11902 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
11903 else if (VT == MVT::i16)
11904 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
11905 else if (VT == MVT::i8)
11906 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
11907 else if (VT == MVT::i64)
11908 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
11913 return std::vector<unsigned>();
11916 std::pair<unsigned, const TargetRegisterClass*>
11917 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
11919 // First, see if this is a constraint that directly corresponds to an LLVM
11921 if (Constraint.size() == 1) {
11922 // GCC Constraint Letters
11923 switch (Constraint[0]) {
11925 case 'r': // GENERAL_REGS
11926 case 'l': // INDEX_REGS
11928 return std::make_pair(0U, X86::GR8RegisterClass);
11929 if (VT == MVT::i16)
11930 return std::make_pair(0U, X86::GR16RegisterClass);
11931 if (VT == MVT::i32 || !Subtarget->is64Bit())
11932 return std::make_pair(0U, X86::GR32RegisterClass);
11933 return std::make_pair(0U, X86::GR64RegisterClass);
11934 case 'R': // LEGACY_REGS
11936 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
11937 if (VT == MVT::i16)
11938 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
11939 if (VT == MVT::i32 || !Subtarget->is64Bit())
11940 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
11941 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
11942 case 'f': // FP Stack registers.
11943 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
11944 // value to the correct fpstack register class.
11945 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
11946 return std::make_pair(0U, X86::RFP32RegisterClass);
11947 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
11948 return std::make_pair(0U, X86::RFP64RegisterClass);
11949 return std::make_pair(0U, X86::RFP80RegisterClass);
11950 case 'y': // MMX_REGS if MMX allowed.
11951 if (!Subtarget->hasMMX()) break;
11952 return std::make_pair(0U, X86::VR64RegisterClass);
11953 case 'Y': // SSE_REGS if SSE2 allowed
11954 if (!Subtarget->hasSSE2()) break;
11956 case 'x': // SSE_REGS if SSE1 allowed
11957 if (!Subtarget->hasSSE1()) break;
11959 switch (VT.getSimpleVT().SimpleTy) {
11961 // Scalar SSE types.
11964 return std::make_pair(0U, X86::FR32RegisterClass);
11967 return std::make_pair(0U, X86::FR64RegisterClass);
11975 return std::make_pair(0U, X86::VR128RegisterClass);
11981 // Use the default implementation in TargetLowering to convert the register
11982 // constraint into a member of a register class.
11983 std::pair<unsigned, const TargetRegisterClass*> Res;
11984 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
11986 // Not found as a standard register?
11987 if (Res.second == 0) {
11988 // Map st(0) -> st(7) -> ST0
11989 if (Constraint.size() == 7 && Constraint[0] == '{' &&
11990 tolower(Constraint[1]) == 's' &&
11991 tolower(Constraint[2]) == 't' &&
11992 Constraint[3] == '(' &&
11993 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
11994 Constraint[5] == ')' &&
11995 Constraint[6] == '}') {
11997 Res.first = X86::ST0+Constraint[4]-'0';
11998 Res.second = X86::RFP80RegisterClass;
12002 // GCC allows "st(0)" to be called just plain "st".
12003 if (StringRef("{st}").equals_lower(Constraint)) {
12004 Res.first = X86::ST0;
12005 Res.second = X86::RFP80RegisterClass;
12010 if (StringRef("{flags}").equals_lower(Constraint)) {
12011 Res.first = X86::EFLAGS;
12012 Res.second = X86::CCRRegisterClass;
12016 // 'A' means EAX + EDX.
12017 if (Constraint == "A") {
12018 Res.first = X86::EAX;
12019 Res.second = X86::GR32_ADRegisterClass;
12025 // Otherwise, check to see if this is a register class of the wrong value
12026 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
12027 // turn into {ax},{dx}.
12028 if (Res.second->hasType(VT))
12029 return Res; // Correct type already, nothing to do.
12031 // All of the single-register GCC register classes map their values onto
12032 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
12033 // really want an 8-bit or 32-bit register, map to the appropriate register
12034 // class and return the appropriate register.
12035 if (Res.second == X86::GR16RegisterClass) {
12036 if (VT == MVT::i8) {
12037 unsigned DestReg = 0;
12038 switch (Res.first) {
12040 case X86::AX: DestReg = X86::AL; break;
12041 case X86::DX: DestReg = X86::DL; break;
12042 case X86::CX: DestReg = X86::CL; break;
12043 case X86::BX: DestReg = X86::BL; break;
12046 Res.first = DestReg;
12047 Res.second = X86::GR8RegisterClass;
12049 } else if (VT == MVT::i32) {
12050 unsigned DestReg = 0;
12051 switch (Res.first) {
12053 case X86::AX: DestReg = X86::EAX; break;
12054 case X86::DX: DestReg = X86::EDX; break;
12055 case X86::CX: DestReg = X86::ECX; break;
12056 case X86::BX: DestReg = X86::EBX; break;
12057 case X86::SI: DestReg = X86::ESI; break;
12058 case X86::DI: DestReg = X86::EDI; break;
12059 case X86::BP: DestReg = X86::EBP; break;
12060 case X86::SP: DestReg = X86::ESP; break;
12063 Res.first = DestReg;
12064 Res.second = X86::GR32RegisterClass;
12066 } else if (VT == MVT::i64) {
12067 unsigned DestReg = 0;
12068 switch (Res.first) {
12070 case X86::AX: DestReg = X86::RAX; break;
12071 case X86::DX: DestReg = X86::RDX; break;
12072 case X86::CX: DestReg = X86::RCX; break;
12073 case X86::BX: DestReg = X86::RBX; break;
12074 case X86::SI: DestReg = X86::RSI; break;
12075 case X86::DI: DestReg = X86::RDI; break;
12076 case X86::BP: DestReg = X86::RBP; break;
12077 case X86::SP: DestReg = X86::RSP; break;
12080 Res.first = DestReg;
12081 Res.second = X86::GR64RegisterClass;
12084 } else if (Res.second == X86::FR32RegisterClass ||
12085 Res.second == X86::FR64RegisterClass ||
12086 Res.second == X86::VR128RegisterClass) {
12087 // Handle references to XMM physical registers that got mapped into the
12088 // wrong class. This can happen with constraints like {xmm0} where the
12089 // target independent register mapper will just pick the first match it can
12090 // find, ignoring the required type.
12091 if (VT == MVT::f32)
12092 Res.second = X86::FR32RegisterClass;
12093 else if (VT == MVT::f64)
12094 Res.second = X86::FR64RegisterClass;
12095 else if (X86::VR128RegisterClass->hasType(VT))
12096 Res.second = X86::VR128RegisterClass;