1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "X86TargetObjectFile.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalAlias.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/LLVMContext.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/VectorExtras.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Disable16Bit - 16-bit operations typically have a larger encoding than
51 // corresponding 32-bit instructions, and 16-bit code is slow on some
52 // processors. This is an experimental flag to disable 16-bit operations
53 // (which forces them to be Legalized to 32-bit operations).
55 Disable16Bit("disable-16bit", cl::Hidden,
56 cl::desc("Disable use of 16-bit instructions"));
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64 default: llvm_unreachable("unknown subtarget type");
65 case X86Subtarget::isDarwin:
66 if (TM.getSubtarget<X86Subtarget>().is64Bit())
67 return new X8664_MachoTargetObjectFile();
68 return new X8632_MachoTargetObjectFile();
69 case X86Subtarget::isELF:
70 return new TargetLoweringObjectFileELF();
71 case X86Subtarget::isMingw:
72 case X86Subtarget::isCygwin:
73 case X86Subtarget::isWindows:
74 return new TargetLoweringObjectFileCOFF();
79 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
80 : TargetLowering(TM, createTLOF(TM)) {
81 Subtarget = &TM.getSubtarget<X86Subtarget>();
82 X86ScalarSSEf64 = Subtarget->hasSSE2();
83 X86ScalarSSEf32 = Subtarget->hasSSE1();
84 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
86 RegInfo = TM.getRegisterInfo();
89 // Set up the TargetLowering object.
91 // X86 is weird, it always uses i8 for shift amounts and setcc results.
92 setShiftAmountType(MVT::i8);
93 setBooleanContents(ZeroOrOneBooleanContent);
94 setSchedulingPreference(SchedulingForRegPressure);
95 setStackPointerRegisterToSaveRestore(X86StackPtr);
97 if (Subtarget->isTargetDarwin()) {
98 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
99 setUseUnderscoreSetJmp(false);
100 setUseUnderscoreLongJmp(false);
101 } else if (Subtarget->isTargetMingw()) {
102 // MS runtime is weird: it exports _setjmp, but longjmp!
103 setUseUnderscoreSetJmp(true);
104 setUseUnderscoreLongJmp(false);
106 setUseUnderscoreSetJmp(true);
107 setUseUnderscoreLongJmp(true);
110 // Set up the register classes.
111 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
113 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
114 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
115 if (Subtarget->is64Bit())
116 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
120 // We don't accept any truncstore of integer registers.
121 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
128 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
130 // SETOEQ and SETUNE require checking two conditions.
131 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
133 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
136 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
138 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
140 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
142 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
144 if (Subtarget->is64Bit()) {
145 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
146 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
147 } else if (!UseSoftFloat) {
148 if (X86ScalarSSEf64) {
149 // We have an impenetrably clever algorithm for ui64->double only.
150 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
152 // We have an algorithm for SSE2, and we turn this into a 64-bit
153 // FILD for other targets.
154 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
157 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
159 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
163 // SSE has no i16 to fp conversion, only i32
164 if (X86ScalarSSEf32) {
165 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
166 // f32 and f64 cases are Legal, f80 case is not
167 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
169 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
170 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
173 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
174 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
177 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
178 // are Legal, f80 is custom lowered.
179 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
180 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
182 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
184 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
185 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
187 if (X86ScalarSSEf32) {
188 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
189 // f32 and f64 cases are Legal, f80 case is not
190 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
192 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
193 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
196 // Handle FP_TO_UINT by promoting the destination to a larger signed
198 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
199 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
200 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
202 if (Subtarget->is64Bit()) {
203 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
204 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
205 } else if (!UseSoftFloat) {
206 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
207 // Expand FP_TO_UINT into a select.
208 // FIXME: We would like to use a Custom expander here eventually to do
209 // the optimal thing for SSE vs. the default expansion in the legalizer.
210 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
212 // With SSE3 we can use fisttpll to convert to a signed i64; without
213 // SSE, we're stuck with a fistpll.
214 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
217 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
218 if (!X86ScalarSSEf64) {
219 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
220 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
223 // Scalar integer divide and remainder are lowered to use operations that
224 // produce two results, to match the available instructions. This exposes
225 // the two-result form to trivial CSE, which is able to combine x/y and x%y
226 // into a single instruction.
228 // Scalar integer multiply-high is also lowered to use two-result
229 // operations, to match the available instructions. However, plain multiply
230 // (low) operations are left as Legal, as there are single-result
231 // instructions for this in x86. Using the two-result multiply instructions
232 // when both high and low results are needed must be arranged by dagcombine.
233 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
234 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
235 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
236 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
237 setOperationAction(ISD::SREM , MVT::i8 , Expand);
238 setOperationAction(ISD::UREM , MVT::i8 , Expand);
239 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
243 setOperationAction(ISD::SREM , MVT::i16 , Expand);
244 setOperationAction(ISD::UREM , MVT::i16 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
249 setOperationAction(ISD::SREM , MVT::i32 , Expand);
250 setOperationAction(ISD::UREM , MVT::i32 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
255 setOperationAction(ISD::SREM , MVT::i64 , Expand);
256 setOperationAction(ISD::UREM , MVT::i64 , Expand);
258 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
259 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
260 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
261 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
262 if (Subtarget->is64Bit())
263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
267 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
268 setOperationAction(ISD::FREM , MVT::f32 , Expand);
269 setOperationAction(ISD::FREM , MVT::f64 , Expand);
270 setOperationAction(ISD::FREM , MVT::f80 , Expand);
271 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
273 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
274 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
275 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
276 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
278 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
279 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
281 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
289 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
290 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
293 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
294 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
296 // These should be promoted to a larger select which is supported.
297 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
298 // X86 wants to expand cmov itself.
299 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
303 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
304 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
306 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
307 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
310 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
312 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
313 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
314 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
315 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
316 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
321 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
324 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
325 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
326 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
327 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
328 if (Subtarget->is64Bit())
329 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
330 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
331 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
334 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
335 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
336 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
337 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
339 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
340 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
343 if (Subtarget->is64Bit()) {
344 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
345 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
346 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
349 if (Subtarget->hasSSE1())
350 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
352 if (!Subtarget->hasSSE2())
353 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
355 // Expand certain atomics
356 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
361 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
362 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
366 if (!Subtarget->is64Bit()) {
367 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
376 // Use the default ISD::DBG_STOPPOINT.
377 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
378 // FIXME - use subtarget debug flags
379 if (!Subtarget->isTargetDarwin() &&
380 !Subtarget->isTargetELF() &&
381 !Subtarget->isTargetCygMing()) {
382 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
383 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
386 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
387 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
388 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
389 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
390 if (Subtarget->is64Bit()) {
391 setExceptionPointerRegister(X86::RAX);
392 setExceptionSelectorRegister(X86::RDX);
394 setExceptionPointerRegister(X86::EAX);
395 setExceptionSelectorRegister(X86::EDX);
397 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
398 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
400 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
402 setOperationAction(ISD::TRAP, MVT::Other, Legal);
404 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
405 setOperationAction(ISD::VASTART , MVT::Other, Custom);
406 setOperationAction(ISD::VAEND , MVT::Other, Expand);
407 if (Subtarget->is64Bit()) {
408 setOperationAction(ISD::VAARG , MVT::Other, Custom);
409 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
411 setOperationAction(ISD::VAARG , MVT::Other, Expand);
412 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
415 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
416 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
417 if (Subtarget->is64Bit())
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
419 if (Subtarget->isTargetCygMing())
420 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
422 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
424 if (!UseSoftFloat && X86ScalarSSEf64) {
425 // f32 and f64 use SSE.
426 // Set up the FP register classes.
427 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
428 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
430 // Use ANDPD to simulate FABS.
431 setOperationAction(ISD::FABS , MVT::f64, Custom);
432 setOperationAction(ISD::FABS , MVT::f32, Custom);
434 // Use XORP to simulate FNEG.
435 setOperationAction(ISD::FNEG , MVT::f64, Custom);
436 setOperationAction(ISD::FNEG , MVT::f32, Custom);
438 // Use ANDPD and ORPD to simulate FCOPYSIGN.
439 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
440 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
442 // We don't support sin/cos/fmod
443 setOperationAction(ISD::FSIN , MVT::f64, Expand);
444 setOperationAction(ISD::FCOS , MVT::f64, Expand);
445 setOperationAction(ISD::FSIN , MVT::f32, Expand);
446 setOperationAction(ISD::FCOS , MVT::f32, Expand);
448 // Expand FP immediates into loads from the stack, except for the special
450 addLegalFPImmediate(APFloat(+0.0)); // xorpd
451 addLegalFPImmediate(APFloat(+0.0f)); // xorps
452 } else if (!UseSoftFloat && X86ScalarSSEf32) {
453 // Use SSE for f32, x87 for f64.
454 // Set up the FP register classes.
455 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
456 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
458 // Use ANDPS to simulate FABS.
459 setOperationAction(ISD::FABS , MVT::f32, Custom);
461 // Use XORP to simulate FNEG.
462 setOperationAction(ISD::FNEG , MVT::f32, Custom);
464 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
466 // Use ANDPS and ORPS to simulate FCOPYSIGN.
467 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
470 // We don't support sin/cos/fmod
471 setOperationAction(ISD::FSIN , MVT::f32, Expand);
472 setOperationAction(ISD::FCOS , MVT::f32, Expand);
474 // Special cases we handle for FP constants.
475 addLegalFPImmediate(APFloat(+0.0f)); // xorps
476 addLegalFPImmediate(APFloat(+0.0)); // FLD0
477 addLegalFPImmediate(APFloat(+1.0)); // FLD1
478 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
479 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
482 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
483 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
485 } else if (!UseSoftFloat) {
486 // f32 and f64 in x87.
487 // Set up the FP register classes.
488 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
489 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
491 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
492 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
493 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
494 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
497 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
498 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
500 addLegalFPImmediate(APFloat(+0.0)); // FLD0
501 addLegalFPImmediate(APFloat(+1.0)); // FLD1
502 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
503 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
504 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
505 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
506 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
507 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
510 // Long double always uses X87.
512 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
513 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
514 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
517 APFloat TmpFlt(+0.0);
518 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
520 addLegalFPImmediate(TmpFlt); // FLD0
522 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
523 APFloat TmpFlt2(+1.0);
524 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
526 addLegalFPImmediate(TmpFlt2); // FLD1
527 TmpFlt2.changeSign();
528 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
532 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
533 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
537 // Always use a library call for pow.
538 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
539 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
540 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
542 setOperationAction(ISD::FLOG, MVT::f80, Expand);
543 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
544 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
545 setOperationAction(ISD::FEXP, MVT::f80, Expand);
546 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
548 // First set operation action for all vector types to either promote
549 // (for widening) or expand (for scalarization). Then we will selectively
550 // turn on ones that can be effectively codegen'd.
551 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
552 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
553 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
568 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
569 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
603 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
604 // with -msoft-float, disable use of MMX as well.
605 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
606 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
607 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
608 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
609 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
610 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
612 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
613 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
614 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
615 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
617 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
618 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
619 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
620 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
622 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
623 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
625 setOperationAction(ISD::AND, MVT::v8i8, Promote);
626 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
627 setOperationAction(ISD::AND, MVT::v4i16, Promote);
628 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
629 setOperationAction(ISD::AND, MVT::v2i32, Promote);
630 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
631 setOperationAction(ISD::AND, MVT::v1i64, Legal);
633 setOperationAction(ISD::OR, MVT::v8i8, Promote);
634 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
635 setOperationAction(ISD::OR, MVT::v4i16, Promote);
636 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
637 setOperationAction(ISD::OR, MVT::v2i32, Promote);
638 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
639 setOperationAction(ISD::OR, MVT::v1i64, Legal);
641 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
642 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
643 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
644 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
645 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
646 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
647 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
649 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
650 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
651 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
652 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
653 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
654 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
655 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
656 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
657 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
659 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
660 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
661 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
662 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
663 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
665 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
667 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
668 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
670 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
671 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
672 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
673 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
675 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
677 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
678 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
679 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
680 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
681 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
682 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
683 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
684 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
685 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
688 if (!UseSoftFloat && Subtarget->hasSSE1()) {
689 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
691 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
692 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
693 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
694 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
695 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
696 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
697 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
698 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
699 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
700 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
701 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
702 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
705 if (!UseSoftFloat && Subtarget->hasSSE2()) {
706 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
708 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
709 // registers cannot be used even for integer operations.
710 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
711 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
712 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
713 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
715 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
716 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
717 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
718 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
719 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
720 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
721 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
722 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
723 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
724 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
725 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
726 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
727 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
728 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
729 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
730 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
732 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
733 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
734 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
735 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
737 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
738 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
739 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
740 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
741 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
743 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
744 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
745 EVT VT = (MVT::SimpleValueType)i;
746 // Do not attempt to custom lower non-power-of-2 vectors
747 if (!isPowerOf2_32(VT.getVectorNumElements()))
749 // Do not attempt to custom lower non-128-bit vectors
750 if (!VT.is128BitVector())
752 setOperationAction(ISD::BUILD_VECTOR,
753 VT.getSimpleVT().SimpleTy, Custom);
754 setOperationAction(ISD::VECTOR_SHUFFLE,
755 VT.getSimpleVT().SimpleTy, Custom);
756 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
757 VT.getSimpleVT().SimpleTy, Custom);
760 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
761 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
762 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
763 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
764 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
765 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
767 if (Subtarget->is64Bit()) {
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
769 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
772 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
773 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
774 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
777 // Do not attempt to promote non-128-bit vectors
778 if (!VT.is128BitVector()) {
781 setOperationAction(ISD::AND, SVT, Promote);
782 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
783 setOperationAction(ISD::OR, SVT, Promote);
784 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
785 setOperationAction(ISD::XOR, SVT, Promote);
786 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
787 setOperationAction(ISD::LOAD, SVT, Promote);
788 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
789 setOperationAction(ISD::SELECT, SVT, Promote);
790 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
793 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
795 // Custom lower v2i64 and v2f64 selects.
796 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
797 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
798 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
799 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
801 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
802 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
803 if (!DisableMMX && Subtarget->hasMMX()) {
804 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
805 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
809 if (Subtarget->hasSSE41()) {
810 // FIXME: Do we need to handle scalar-to-vector here?
811 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
813 // i8 and i16 vectors are custom , because the source register and source
814 // source memory operand types are not the same width. f32 vectors are
815 // custom since the immediate controlling the insert encodes additional
817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
818 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
819 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
820 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
822 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
824 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
827 if (Subtarget->is64Bit()) {
828 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
829 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
833 if (Subtarget->hasSSE42()) {
834 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
837 if (!UseSoftFloat && Subtarget->hasAVX()) {
838 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
839 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
840 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
841 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
843 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
844 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
845 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
846 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
847 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
848 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
849 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
850 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
851 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
852 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
853 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
854 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
855 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
856 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
857 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
859 // Operations to consider commented out -v16i16 v32i8
860 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
861 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
862 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
863 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
864 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
865 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
866 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
867 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
868 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
869 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
870 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
871 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
872 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
873 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
875 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
876 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
877 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
878 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
880 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
881 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
882 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
883 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
884 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
887 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
889 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
894 // Not sure we want to do this since there are no 256-bit integer
897 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
898 // This includes 256-bit vectors
899 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
900 EVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to custom lower non-power-of-2 vectors
903 if (!isPowerOf2_32(VT.getVectorNumElements()))
906 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
907 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
908 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
911 if (Subtarget->is64Bit()) {
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
913 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
918 // Not sure we want to do this since there are no 256-bit integer
921 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
922 // Including 256-bit vectors
923 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
924 EVT VT = (MVT::SimpleValueType)i;
926 if (!VT.is256BitVector()) {
929 setOperationAction(ISD::AND, VT, Promote);
930 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
931 setOperationAction(ISD::OR, VT, Promote);
932 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
933 setOperationAction(ISD::XOR, VT, Promote);
934 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
935 setOperationAction(ISD::LOAD, VT, Promote);
936 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
937 setOperationAction(ISD::SELECT, VT, Promote);
938 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
941 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
945 // We want to custom lower some of our intrinsics.
946 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
948 // Add/Sub/Mul with overflow operations are custom lowered.
949 setOperationAction(ISD::SADDO, MVT::i32, Custom);
950 setOperationAction(ISD::SADDO, MVT::i64, Custom);
951 setOperationAction(ISD::UADDO, MVT::i32, Custom);
952 setOperationAction(ISD::UADDO, MVT::i64, Custom);
953 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
954 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
955 setOperationAction(ISD::USUBO, MVT::i32, Custom);
956 setOperationAction(ISD::USUBO, MVT::i64, Custom);
957 setOperationAction(ISD::SMULO, MVT::i32, Custom);
958 setOperationAction(ISD::SMULO, MVT::i64, Custom);
960 if (!Subtarget->is64Bit()) {
961 // These libcalls are not available in 32-bit.
962 setLibcallName(RTLIB::SHL_I128, 0);
963 setLibcallName(RTLIB::SRL_I128, 0);
964 setLibcallName(RTLIB::SRA_I128, 0);
967 // We have target-specific dag combine patterns for the following nodes:
968 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
969 setTargetDAGCombine(ISD::BUILD_VECTOR);
970 setTargetDAGCombine(ISD::SELECT);
971 setTargetDAGCombine(ISD::SHL);
972 setTargetDAGCombine(ISD::SRA);
973 setTargetDAGCombine(ISD::SRL);
974 setTargetDAGCombine(ISD::STORE);
975 setTargetDAGCombine(ISD::MEMBARRIER);
976 if (Subtarget->is64Bit())
977 setTargetDAGCombine(ISD::MUL);
979 computeRegisterProperties();
981 // FIXME: These should be based on subtarget info. Plus, the values should
982 // be smaller when we are in optimizing for size mode.
983 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
984 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
985 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
986 setPrefLoopAlignment(16);
987 benefitFromCodePlacementOpt = true;
991 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
996 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
997 /// the desired ByVal argument alignment.
998 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1001 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1002 if (VTy->getBitWidth() == 128)
1004 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1005 unsigned EltAlign = 0;
1006 getMaxByValAlign(ATy->getElementType(), EltAlign);
1007 if (EltAlign > MaxAlign)
1008 MaxAlign = EltAlign;
1009 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1010 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1011 unsigned EltAlign = 0;
1012 getMaxByValAlign(STy->getElementType(i), EltAlign);
1013 if (EltAlign > MaxAlign)
1014 MaxAlign = EltAlign;
1022 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1023 /// function arguments in the caller parameter area. For X86, aggregates
1024 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1025 /// are at 4-byte boundaries.
1026 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1027 if (Subtarget->is64Bit()) {
1028 // Max of 8 and alignment of type.
1029 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1036 if (Subtarget->hasSSE1())
1037 getMaxByValAlign(Ty, Align);
1041 /// getOptimalMemOpType - Returns the target specific optimal type for load
1042 /// and store operations as a result of memset, memcpy, and memmove
1043 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1046 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1047 bool isSrcConst, bool isSrcStr,
1048 SelectionDAG &DAG) const {
1049 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1050 // linux. This is because the stack realignment code can't handle certain
1051 // cases like PR2962. This should be removed when PR2962 is fixed.
1052 const Function *F = DAG.getMachineFunction().getFunction();
1053 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1054 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1055 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1057 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1060 if (Subtarget->is64Bit() && Size >= 8)
1065 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1067 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1068 SelectionDAG &DAG) const {
1069 if (usesGlobalOffsetTable())
1070 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1071 if (!Subtarget->is64Bit())
1072 // This doesn't have DebugLoc associated with it, but is not really the
1073 // same as a Register.
1074 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1079 /// getFunctionAlignment - Return the Log2 alignment of this function.
1080 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1081 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1084 //===----------------------------------------------------------------------===//
1085 // Return Value Calling Convention Implementation
1086 //===----------------------------------------------------------------------===//
1088 #include "X86GenCallingConv.inc"
1091 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1092 const SmallVectorImpl<EVT> &OutTys,
1093 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1094 SelectionDAG &DAG) {
1095 SmallVector<CCValAssign, 16> RVLocs;
1096 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1097 RVLocs, *DAG.getContext());
1098 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1102 X86TargetLowering::LowerReturn(SDValue Chain,
1103 CallingConv::ID CallConv, bool isVarArg,
1104 const SmallVectorImpl<ISD::OutputArg> &Outs,
1105 DebugLoc dl, SelectionDAG &DAG) {
1107 SmallVector<CCValAssign, 16> RVLocs;
1108 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1109 RVLocs, *DAG.getContext());
1110 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1112 // If this is the first return lowered for this function, add the regs to the
1113 // liveout set for the function.
1114 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1115 for (unsigned i = 0; i != RVLocs.size(); ++i)
1116 if (RVLocs[i].isRegLoc())
1117 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1122 SmallVector<SDValue, 6> RetOps;
1123 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1124 // Operand #1 = Bytes To Pop
1125 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1127 // Copy the result values into the output registers.
1128 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1129 CCValAssign &VA = RVLocs[i];
1130 assert(VA.isRegLoc() && "Can only return in registers!");
1131 SDValue ValToCopy = Outs[i].Val;
1133 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1134 // the RET instruction and handled by the FP Stackifier.
1135 if (VA.getLocReg() == X86::ST0 ||
1136 VA.getLocReg() == X86::ST1) {
1137 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1138 // change the value to the FP stack register class.
1139 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1140 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1141 RetOps.push_back(ValToCopy);
1142 // Don't emit a copytoreg.
1146 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1147 // which is returned in RAX / RDX.
1148 if (Subtarget->is64Bit()) {
1149 EVT ValVT = ValToCopy.getValueType();
1150 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1151 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1152 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1153 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1157 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1158 Flag = Chain.getValue(1);
1161 // The x86-64 ABI for returning structs by value requires that we copy
1162 // the sret argument into %rax for the return. We saved the argument into
1163 // a virtual register in the entry block, so now we copy the value out
1165 if (Subtarget->is64Bit() &&
1166 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1167 MachineFunction &MF = DAG.getMachineFunction();
1168 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1169 unsigned Reg = FuncInfo->getSRetReturnReg();
1171 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1172 FuncInfo->setSRetReturnReg(Reg);
1174 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1176 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1177 Flag = Chain.getValue(1);
1179 // RAX now acts like a return value.
1180 MF.getRegInfo().addLiveOut(X86::RAX);
1183 RetOps[0] = Chain; // Update chain.
1185 // Add the flag if we have it.
1187 RetOps.push_back(Flag);
1189 return DAG.getNode(X86ISD::RET_FLAG, dl,
1190 MVT::Other, &RetOps[0], RetOps.size());
1193 /// LowerCallResult - Lower the result values of a call into the
1194 /// appropriate copies out of appropriate physical registers.
1197 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1198 CallingConv::ID CallConv, bool isVarArg,
1199 const SmallVectorImpl<ISD::InputArg> &Ins,
1200 DebugLoc dl, SelectionDAG &DAG,
1201 SmallVectorImpl<SDValue> &InVals) {
1203 // Assign locations to each value returned by this call.
1204 SmallVector<CCValAssign, 16> RVLocs;
1205 bool Is64Bit = Subtarget->is64Bit();
1206 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1207 RVLocs, *DAG.getContext());
1208 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1210 // Copy all of the result registers out of their specified physreg.
1211 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1212 CCValAssign &VA = RVLocs[i];
1213 EVT CopyVT = VA.getValVT();
1215 // If this is x86-64, and we disabled SSE, we can't return FP values
1216 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1217 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1218 llvm_report_error("SSE register return with SSE disabled");
1221 // If this is a call to a function that returns an fp value on the floating
1222 // point stack, but where we prefer to use the value in xmm registers, copy
1223 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1224 if ((VA.getLocReg() == X86::ST0 ||
1225 VA.getLocReg() == X86::ST1) &&
1226 isScalarFPTypeInSSEReg(VA.getValVT())) {
1231 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1232 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1233 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1234 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1235 MVT::v2i64, InFlag).getValue(1);
1236 Val = Chain.getValue(0);
1237 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1238 Val, DAG.getConstant(0, MVT::i64));
1240 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1241 MVT::i64, InFlag).getValue(1);
1242 Val = Chain.getValue(0);
1244 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1246 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1247 CopyVT, InFlag).getValue(1);
1248 Val = Chain.getValue(0);
1250 InFlag = Chain.getValue(2);
1252 if (CopyVT != VA.getValVT()) {
1253 // Round the F80 the right size, which also moves to the appropriate xmm
1255 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1256 // This truncation won't change the value.
1257 DAG.getIntPtrConstant(1));
1260 InVals.push_back(Val);
1267 //===----------------------------------------------------------------------===//
1268 // C & StdCall & Fast Calling Convention implementation
1269 //===----------------------------------------------------------------------===//
1270 // StdCall calling convention seems to be standard for many Windows' API
1271 // routines and around. It differs from C calling convention just a little:
1272 // callee should clean up the stack, not caller. Symbols should be also
1273 // decorated in some fancy way :) It doesn't support any vector arguments.
1274 // For info on fast calling convention see Fast Calling Convention (tail call)
1275 // implementation LowerX86_32FastCCCallTo.
1277 /// CallIsStructReturn - Determines whether a call uses struct return
1279 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1283 return Outs[0].Flags.isSRet();
1286 /// ArgsAreStructReturn - Determines whether a function uses struct
1287 /// return semantics.
1289 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1293 return Ins[0].Flags.isSRet();
1296 /// IsCalleePop - Determines whether the callee is required to pop its
1297 /// own arguments. Callee pop is necessary to support tail calls.
1298 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1302 switch (CallingConv) {
1305 case CallingConv::X86_StdCall:
1306 return !Subtarget->is64Bit();
1307 case CallingConv::X86_FastCall:
1308 return !Subtarget->is64Bit();
1309 case CallingConv::Fast:
1310 return PerformTailCallOpt;
1314 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1315 /// given CallingConvention value.
1316 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1317 if (Subtarget->is64Bit()) {
1318 if (Subtarget->isTargetWin64())
1319 return CC_X86_Win64_C;
1324 if (CC == CallingConv::X86_FastCall)
1325 return CC_X86_32_FastCall;
1326 else if (CC == CallingConv::Fast)
1327 return CC_X86_32_FastCC;
1332 /// NameDecorationForCallConv - Selects the appropriate decoration to
1333 /// apply to a MachineFunction containing a given calling convention.
1335 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1336 if (CallConv == CallingConv::X86_FastCall)
1338 else if (CallConv == CallingConv::X86_StdCall)
1344 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1345 /// by "Src" to address "Dst" with size and alignment information specified by
1346 /// the specific parameter attribute. The copy will be passed as a byval
1347 /// function parameter.
1349 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1350 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1352 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1353 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1354 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1358 X86TargetLowering::LowerMemArgument(SDValue Chain,
1359 CallingConv::ID CallConv,
1360 const SmallVectorImpl<ISD::InputArg> &Ins,
1361 DebugLoc dl, SelectionDAG &DAG,
1362 const CCValAssign &VA,
1363 MachineFrameInfo *MFI,
1366 // Create the nodes corresponding to a load from this parameter slot.
1367 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1368 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1369 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1372 // If value is passed by pointer we have address passed instead of the value
1374 if (VA.getLocInfo() == CCValAssign::Indirect)
1375 ValVT = VA.getLocVT();
1377 ValVT = VA.getValVT();
1379 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1380 // changed with more analysis.
1381 // In case of tail call optimization mark all arguments mutable. Since they
1382 // could be overwritten by lowering of arguments in case of a tail call.
1383 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1384 VA.getLocMemOffset(), isImmutable, false);
1385 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1386 if (Flags.isByVal())
1388 return DAG.getLoad(ValVT, dl, Chain, FIN,
1389 PseudoSourceValue::getFixedStack(FI), 0);
1393 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1394 CallingConv::ID CallConv,
1396 const SmallVectorImpl<ISD::InputArg> &Ins,
1399 SmallVectorImpl<SDValue> &InVals) {
1401 MachineFunction &MF = DAG.getMachineFunction();
1402 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1404 const Function* Fn = MF.getFunction();
1405 if (Fn->hasExternalLinkage() &&
1406 Subtarget->isTargetCygMing() &&
1407 Fn->getName() == "main")
1408 FuncInfo->setForceFramePointer(true);
1410 // Decorate the function name.
1411 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1413 MachineFrameInfo *MFI = MF.getFrameInfo();
1414 bool Is64Bit = Subtarget->is64Bit();
1415 bool IsWin64 = Subtarget->isTargetWin64();
1417 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1418 "Var args not supported with calling convention fastcc");
1420 // Assign locations to all of the incoming arguments.
1421 SmallVector<CCValAssign, 16> ArgLocs;
1422 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1423 ArgLocs, *DAG.getContext());
1424 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1426 unsigned LastVal = ~0U;
1428 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1429 CCValAssign &VA = ArgLocs[i];
1430 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1432 assert(VA.getValNo() != LastVal &&
1433 "Don't support value assigned to multiple locs yet");
1434 LastVal = VA.getValNo();
1436 if (VA.isRegLoc()) {
1437 EVT RegVT = VA.getLocVT();
1438 TargetRegisterClass *RC = NULL;
1439 if (RegVT == MVT::i32)
1440 RC = X86::GR32RegisterClass;
1441 else if (Is64Bit && RegVT == MVT::i64)
1442 RC = X86::GR64RegisterClass;
1443 else if (RegVT == MVT::f32)
1444 RC = X86::FR32RegisterClass;
1445 else if (RegVT == MVT::f64)
1446 RC = X86::FR64RegisterClass;
1447 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1448 RC = X86::VR128RegisterClass;
1449 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1450 RC = X86::VR64RegisterClass;
1452 llvm_unreachable("Unknown argument type!");
1454 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1455 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1457 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1458 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1460 if (VA.getLocInfo() == CCValAssign::SExt)
1461 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1462 DAG.getValueType(VA.getValVT()));
1463 else if (VA.getLocInfo() == CCValAssign::ZExt)
1464 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1465 DAG.getValueType(VA.getValVT()));
1466 else if (VA.getLocInfo() == CCValAssign::BCvt)
1467 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1469 if (VA.isExtInLoc()) {
1470 // Handle MMX values passed in XMM regs.
1471 if (RegVT.isVector()) {
1472 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1473 ArgValue, DAG.getConstant(0, MVT::i64));
1474 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1476 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1479 assert(VA.isMemLoc());
1480 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1483 // If value is passed via pointer - do a load.
1484 if (VA.getLocInfo() == CCValAssign::Indirect)
1485 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1487 InVals.push_back(ArgValue);
1490 // The x86-64 ABI for returning structs by value requires that we copy
1491 // the sret argument into %rax for the return. Save the argument into
1492 // a virtual register so that we can access it from the return points.
1493 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1494 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1495 unsigned Reg = FuncInfo->getSRetReturnReg();
1497 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1498 FuncInfo->setSRetReturnReg(Reg);
1500 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1501 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1504 unsigned StackSize = CCInfo.getNextStackOffset();
1505 // align stack specially for tail calls
1506 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1507 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1509 // If the function takes variable number of arguments, make a frame index for
1510 // the start of the first vararg value... for expansion of llvm.va_start.
1512 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1513 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize, true, false);
1516 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1518 // FIXME: We should really autogenerate these arrays
1519 static const unsigned GPR64ArgRegsWin64[] = {
1520 X86::RCX, X86::RDX, X86::R8, X86::R9
1522 static const unsigned XMMArgRegsWin64[] = {
1523 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1525 static const unsigned GPR64ArgRegs64Bit[] = {
1526 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1528 static const unsigned XMMArgRegs64Bit[] = {
1529 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1530 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1532 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1535 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1536 GPR64ArgRegs = GPR64ArgRegsWin64;
1537 XMMArgRegs = XMMArgRegsWin64;
1539 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1540 GPR64ArgRegs = GPR64ArgRegs64Bit;
1541 XMMArgRegs = XMMArgRegs64Bit;
1543 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1545 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1548 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1549 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1550 "SSE register cannot be used when SSE is disabled!");
1551 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1552 "SSE register cannot be used when SSE is disabled!");
1553 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1554 // Kernel mode asks for SSE to be disabled, so don't push them
1556 TotalNumXMMRegs = 0;
1558 // For X86-64, if there are vararg parameters that are passed via
1559 // registers, then we must store them to their spots on the stack so they
1560 // may be loaded by deferencing the result of va_next.
1561 VarArgsGPOffset = NumIntRegs * 8;
1562 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1563 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1564 TotalNumXMMRegs * 16, 16,
1567 // Store the integer parameter registers.
1568 SmallVector<SDValue, 8> MemOps;
1569 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1570 unsigned Offset = VarArgsGPOffset;
1571 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1572 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1573 DAG.getIntPtrConstant(Offset));
1574 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1575 X86::GR64RegisterClass);
1576 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1578 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1579 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1581 MemOps.push_back(Store);
1585 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1586 // Now store the XMM (fp + vector) parameter registers.
1587 SmallVector<SDValue, 11> SaveXMMOps;
1588 SaveXMMOps.push_back(Chain);
1590 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1591 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1592 SaveXMMOps.push_back(ALVal);
1594 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1595 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1597 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1598 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1599 X86::VR128RegisterClass);
1600 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1601 SaveXMMOps.push_back(Val);
1603 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1605 &SaveXMMOps[0], SaveXMMOps.size()));
1608 if (!MemOps.empty())
1609 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1610 &MemOps[0], MemOps.size());
1614 // Some CCs need callee pop.
1615 if (IsCalleePop(isVarArg, CallConv)) {
1616 BytesToPopOnReturn = StackSize; // Callee pops everything.
1617 BytesCallerReserves = 0;
1619 BytesToPopOnReturn = 0; // Callee pops nothing.
1620 // If this is an sret function, the return should pop the hidden pointer.
1621 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1622 BytesToPopOnReturn = 4;
1623 BytesCallerReserves = StackSize;
1627 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1628 if (CallConv == CallingConv::X86_FastCall)
1629 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1632 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1638 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1639 SDValue StackPtr, SDValue Arg,
1640 DebugLoc dl, SelectionDAG &DAG,
1641 const CCValAssign &VA,
1642 ISD::ArgFlagsTy Flags) {
1643 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1644 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1645 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1646 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1647 if (Flags.isByVal()) {
1648 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1650 return DAG.getStore(Chain, dl, Arg, PtrOff,
1651 PseudoSourceValue::getStack(), LocMemOffset);
1654 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1655 /// optimization is performed and it is required.
1657 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1658 SDValue &OutRetAddr,
1664 if (!IsTailCall || FPDiff==0) return Chain;
1666 // Adjust the Return address stack slot.
1667 EVT VT = getPointerTy();
1668 OutRetAddr = getReturnAddressFrameIndex(DAG);
1670 // Load the "old" Return address.
1671 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1672 return SDValue(OutRetAddr.getNode(), 1);
1675 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1676 /// optimization is performed and it is required (FPDiff!=0).
1678 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1679 SDValue Chain, SDValue RetAddrFrIdx,
1680 bool Is64Bit, int FPDiff, DebugLoc dl) {
1681 // Store the return address to the appropriate stack slot.
1682 if (!FPDiff) return Chain;
1683 // Calculate the new stack slot for the return address.
1684 int SlotSize = Is64Bit ? 8 : 4;
1685 int NewReturnAddrFI =
1686 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize,
1688 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1689 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1690 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1691 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1696 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1697 CallingConv::ID CallConv, bool isVarArg,
1699 const SmallVectorImpl<ISD::OutputArg> &Outs,
1700 const SmallVectorImpl<ISD::InputArg> &Ins,
1701 DebugLoc dl, SelectionDAG &DAG,
1702 SmallVectorImpl<SDValue> &InVals) {
1704 MachineFunction &MF = DAG.getMachineFunction();
1705 bool Is64Bit = Subtarget->is64Bit();
1706 bool IsStructRet = CallIsStructReturn(Outs);
1708 assert((!isTailCall ||
1709 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1710 "IsEligibleForTailCallOptimization missed a case!");
1711 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1712 "Var args not supported with calling convention fastcc");
1714 // Analyze operands of the call, assigning locations to each operand.
1715 SmallVector<CCValAssign, 16> ArgLocs;
1716 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1717 ArgLocs, *DAG.getContext());
1718 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1720 // Get a count of how many bytes are to be pushed on the stack.
1721 unsigned NumBytes = CCInfo.getNextStackOffset();
1722 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1723 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1727 // Lower arguments at fp - stackoffset + fpdiff.
1728 unsigned NumBytesCallerPushed =
1729 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1730 FPDiff = NumBytesCallerPushed - NumBytes;
1732 // Set the delta of movement of the returnaddr stackslot.
1733 // But only set if delta is greater than previous delta.
1734 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1735 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1738 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1740 SDValue RetAddrFrIdx;
1741 // Load return adress for tail calls.
1742 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1745 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1746 SmallVector<SDValue, 8> MemOpChains;
1749 // Walk the register/memloc assignments, inserting copies/loads. In the case
1750 // of tail call optimization arguments are handle later.
1751 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1752 CCValAssign &VA = ArgLocs[i];
1753 EVT RegVT = VA.getLocVT();
1754 SDValue Arg = Outs[i].Val;
1755 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1756 bool isByVal = Flags.isByVal();
1758 // Promote the value if needed.
1759 switch (VA.getLocInfo()) {
1760 default: llvm_unreachable("Unknown loc info!");
1761 case CCValAssign::Full: break;
1762 case CCValAssign::SExt:
1763 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1765 case CCValAssign::ZExt:
1766 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1768 case CCValAssign::AExt:
1769 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1770 // Special case: passing MMX values in XMM registers.
1771 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1772 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1773 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1775 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1777 case CCValAssign::BCvt:
1778 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1780 case CCValAssign::Indirect: {
1781 // Store the argument.
1782 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1783 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1784 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1785 PseudoSourceValue::getFixedStack(FI), 0);
1791 if (VA.isRegLoc()) {
1792 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1794 if (!isTailCall || (isTailCall && isByVal)) {
1795 assert(VA.isMemLoc());
1796 if (StackPtr.getNode() == 0)
1797 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1799 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1800 dl, DAG, VA, Flags));
1805 if (!MemOpChains.empty())
1806 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1807 &MemOpChains[0], MemOpChains.size());
1809 // Build a sequence of copy-to-reg nodes chained together with token chain
1810 // and flag operands which copy the outgoing args into registers.
1812 // Tail call byval lowering might overwrite argument registers so in case of
1813 // tail call optimization the copies to registers are lowered later.
1815 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1816 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1817 RegsToPass[i].second, InFlag);
1818 InFlag = Chain.getValue(1);
1822 if (Subtarget->isPICStyleGOT()) {
1823 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1826 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1827 DAG.getNode(X86ISD::GlobalBaseReg,
1828 DebugLoc::getUnknownLoc(),
1831 InFlag = Chain.getValue(1);
1833 // If we are tail calling and generating PIC/GOT style code load the
1834 // address of the callee into ECX. The value in ecx is used as target of
1835 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1836 // for tail calls on PIC/GOT architectures. Normally we would just put the
1837 // address of GOT into ebx and then call target@PLT. But for tail calls
1838 // ebx would be restored (since ebx is callee saved) before jumping to the
1841 // Note: The actual moving to ECX is done further down.
1842 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1843 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1844 !G->getGlobal()->hasProtectedVisibility())
1845 Callee = LowerGlobalAddress(Callee, DAG);
1846 else if (isa<ExternalSymbolSDNode>(Callee))
1847 Callee = LowerExternalSymbol(Callee, DAG);
1851 if (Is64Bit && isVarArg) {
1852 // From AMD64 ABI document:
1853 // For calls that may call functions that use varargs or stdargs
1854 // (prototype-less calls or calls to functions containing ellipsis (...) in
1855 // the declaration) %al is used as hidden argument to specify the number
1856 // of SSE registers used. The contents of %al do not need to match exactly
1857 // the number of registers, but must be an ubound on the number of SSE
1858 // registers used and is in the range 0 - 8 inclusive.
1860 // FIXME: Verify this on Win64
1861 // Count the number of XMM registers allocated.
1862 static const unsigned XMMArgRegs[] = {
1863 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1864 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1866 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1867 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1868 && "SSE registers cannot be used when SSE is disabled");
1870 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1871 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1872 InFlag = Chain.getValue(1);
1876 // For tail calls lower the arguments to the 'real' stack slot.
1878 // Force all the incoming stack arguments to be loaded from the stack
1879 // before any new outgoing arguments are stored to the stack, because the
1880 // outgoing stack slots may alias the incoming argument stack slots, and
1881 // the alias isn't otherwise explicit. This is slightly more conservative
1882 // than necessary, because it means that each store effectively depends
1883 // on every argument instead of just those arguments it would clobber.
1884 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1886 SmallVector<SDValue, 8> MemOpChains2;
1889 // Do not flag preceeding copytoreg stuff together with the following stuff.
1891 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1892 CCValAssign &VA = ArgLocs[i];
1893 if (!VA.isRegLoc()) {
1894 assert(VA.isMemLoc());
1895 SDValue Arg = Outs[i].Val;
1896 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1897 // Create frame index.
1898 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1899 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1900 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
1901 FIN = DAG.getFrameIndex(FI, getPointerTy());
1903 if (Flags.isByVal()) {
1904 // Copy relative to framepointer.
1905 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1906 if (StackPtr.getNode() == 0)
1907 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1909 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1911 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1915 // Store relative to framepointer.
1916 MemOpChains2.push_back(
1917 DAG.getStore(ArgChain, dl, Arg, FIN,
1918 PseudoSourceValue::getFixedStack(FI), 0));
1923 if (!MemOpChains2.empty())
1924 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1925 &MemOpChains2[0], MemOpChains2.size());
1927 // Copy arguments to their registers.
1928 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1929 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1930 RegsToPass[i].second, InFlag);
1931 InFlag = Chain.getValue(1);
1935 // Store the return address to the appropriate stack slot.
1936 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1940 bool WasGlobalOrExternal = false;
1941 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
1942 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
1943 // In the 64-bit large code model, we have to make all calls
1944 // through a register, since the call instruction's 32-bit
1945 // pc-relative offset may not be large enough to hold the whole
1947 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1948 WasGlobalOrExternal = true;
1949 // If the callee is a GlobalAddress node (quite common, every direct call
1950 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
1953 // We should use extra load for direct calls to dllimported functions in
1955 GlobalValue *GV = G->getGlobal();
1956 if (!GV->hasDLLImportLinkage()) {
1957 unsigned char OpFlags = 0;
1959 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1960 // external symbols most go through the PLT in PIC mode. If the symbol
1961 // has hidden or protected visibility, or if it is static or local, then
1962 // we don't need to use the PLT - we can directly call it.
1963 if (Subtarget->isTargetELF() &&
1964 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1965 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1966 OpFlags = X86II::MO_PLT;
1967 } else if (Subtarget->isPICStyleStubAny() &&
1968 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1969 Subtarget->getDarwinVers() < 9) {
1970 // PC-relative references to external symbols should go through $stub,
1971 // unless we're building with the leopard linker or later, which
1972 // automatically synthesizes these stubs.
1973 OpFlags = X86II::MO_DARWIN_STUB;
1976 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1977 G->getOffset(), OpFlags);
1979 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1980 WasGlobalOrExternal = true;
1981 unsigned char OpFlags = 0;
1983 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1984 // symbols should go through the PLT.
1985 if (Subtarget->isTargetELF() &&
1986 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1987 OpFlags = X86II::MO_PLT;
1988 } else if (Subtarget->isPICStyleStubAny() &&
1989 Subtarget->getDarwinVers() < 9) {
1990 // PC-relative references to external symbols should go through $stub,
1991 // unless we're building with the leopard linker or later, which
1992 // automatically synthesizes these stubs.
1993 OpFlags = X86II::MO_DARWIN_STUB;
1996 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2000 if (isTailCall && !WasGlobalOrExternal) {
2001 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
2003 Chain = DAG.getCopyToReg(Chain, dl,
2004 DAG.getRegister(Opc, getPointerTy()),
2006 Callee = DAG.getRegister(Opc, getPointerTy());
2007 // Add register as live out.
2008 MF.getRegInfo().addLiveOut(Opc);
2011 // Returns a chain & a flag for retval copy to use.
2012 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2013 SmallVector<SDValue, 8> Ops;
2016 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2017 DAG.getIntPtrConstant(0, true), InFlag);
2018 InFlag = Chain.getValue(1);
2021 Ops.push_back(Chain);
2022 Ops.push_back(Callee);
2025 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2027 // Add argument registers to the end of the list so that they are known live
2029 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2030 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2031 RegsToPass[i].second.getValueType()));
2033 // Add an implicit use GOT pointer in EBX.
2034 if (!isTailCall && Subtarget->isPICStyleGOT())
2035 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2037 // Add an implicit use of AL for x86 vararg functions.
2038 if (Is64Bit && isVarArg)
2039 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2041 if (InFlag.getNode())
2042 Ops.push_back(InFlag);
2045 // If this is the first return lowered for this function, add the regs
2046 // to the liveout set for the function.
2047 if (MF.getRegInfo().liveout_empty()) {
2048 SmallVector<CCValAssign, 16> RVLocs;
2049 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2051 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2052 for (unsigned i = 0; i != RVLocs.size(); ++i)
2053 if (RVLocs[i].isRegLoc())
2054 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2057 assert(((Callee.getOpcode() == ISD::Register &&
2058 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2059 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2060 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2061 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2062 "Expecting an global address, external symbol, or register");
2064 return DAG.getNode(X86ISD::TC_RETURN, dl,
2065 NodeTys, &Ops[0], Ops.size());
2068 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2069 InFlag = Chain.getValue(1);
2071 // Create the CALLSEQ_END node.
2072 unsigned NumBytesForCalleeToPush;
2073 if (IsCalleePop(isVarArg, CallConv))
2074 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2075 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2076 // If this is is a call to a struct-return function, the callee
2077 // pops the hidden struct pointer, so we have to push it back.
2078 // This is common for Darwin/X86, Linux & Mingw32 targets.
2079 NumBytesForCalleeToPush = 4;
2081 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2083 // Returns a flag for retval copy to use.
2084 Chain = DAG.getCALLSEQ_END(Chain,
2085 DAG.getIntPtrConstant(NumBytes, true),
2086 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2089 InFlag = Chain.getValue(1);
2091 // Handle result values, copying them out of physregs into vregs that we
2093 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2094 Ins, dl, DAG, InVals);
2098 //===----------------------------------------------------------------------===//
2099 // Fast Calling Convention (tail call) implementation
2100 //===----------------------------------------------------------------------===//
2102 // Like std call, callee cleans arguments, convention except that ECX is
2103 // reserved for storing the tail called function address. Only 2 registers are
2104 // free for argument passing (inreg). Tail call optimization is performed
2106 // * tailcallopt is enabled
2107 // * caller/callee are fastcc
2108 // On X86_64 architecture with GOT-style position independent code only local
2109 // (within module) calls are supported at the moment.
2110 // To keep the stack aligned according to platform abi the function
2111 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2112 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2113 // If a tail called function callee has more arguments than the caller the
2114 // caller needs to make sure that there is room to move the RETADDR to. This is
2115 // achieved by reserving an area the size of the argument delta right after the
2116 // original REtADDR, but before the saved framepointer or the spilled registers
2117 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2129 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2130 /// for a 16 byte align requirement.
2131 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2132 SelectionDAG& DAG) {
2133 MachineFunction &MF = DAG.getMachineFunction();
2134 const TargetMachine &TM = MF.getTarget();
2135 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2136 unsigned StackAlignment = TFI.getStackAlignment();
2137 uint64_t AlignMask = StackAlignment - 1;
2138 int64_t Offset = StackSize;
2139 uint64_t SlotSize = TD->getPointerSize();
2140 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2141 // Number smaller than 12 so just add the difference.
2142 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2144 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2145 Offset = ((~AlignMask) & Offset) + StackAlignment +
2146 (StackAlignment-SlotSize);
2151 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2152 /// for tail call optimization. Targets which want to do tail call
2153 /// optimization should implement this function.
2155 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2156 CallingConv::ID CalleeCC,
2158 const SmallVectorImpl<ISD::InputArg> &Ins,
2159 SelectionDAG& DAG) const {
2160 MachineFunction &MF = DAG.getMachineFunction();
2161 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2162 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2166 X86TargetLowering::createFastISel(MachineFunction &mf,
2167 MachineModuleInfo *mmo,
2169 DenseMap<const Value *, unsigned> &vm,
2170 DenseMap<const BasicBlock *,
2171 MachineBasicBlock *> &bm,
2172 DenseMap<const AllocaInst *, int> &am
2174 , SmallSet<Instruction*, 8> &cil
2177 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2185 //===----------------------------------------------------------------------===//
2186 // Other Lowering Hooks
2187 //===----------------------------------------------------------------------===//
2190 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2191 MachineFunction &MF = DAG.getMachineFunction();
2192 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2193 int ReturnAddrIndex = FuncInfo->getRAIndex();
2195 if (ReturnAddrIndex == 0) {
2196 // Set up a frame object for the return address.
2197 uint64_t SlotSize = TD->getPointerSize();
2198 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2200 FuncInfo->setRAIndex(ReturnAddrIndex);
2203 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2207 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2208 bool hasSymbolicDisplacement) {
2209 // Offset should fit into 32 bit immediate field.
2210 if (!isInt32(Offset))
2213 // If we don't have a symbolic displacement - we don't have any extra
2215 if (!hasSymbolicDisplacement)
2218 // FIXME: Some tweaks might be needed for medium code model.
2219 if (M != CodeModel::Small && M != CodeModel::Kernel)
2222 // For small code model we assume that latest object is 16MB before end of 31
2223 // bits boundary. We may also accept pretty large negative constants knowing
2224 // that all objects are in the positive half of address space.
2225 if (M == CodeModel::Small && Offset < 16*1024*1024)
2228 // For kernel code model we know that all object resist in the negative half
2229 // of 32bits address space. We may not accept negative offsets, since they may
2230 // be just off and we may accept pretty large positive ones.
2231 if (M == CodeModel::Kernel && Offset > 0)
2237 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2238 /// specific condition code, returning the condition code and the LHS/RHS of the
2239 /// comparison to make.
2240 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2241 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2243 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2244 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2245 // X > -1 -> X == 0, jump !sign.
2246 RHS = DAG.getConstant(0, RHS.getValueType());
2247 return X86::COND_NS;
2248 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2249 // X < 0 -> X == 0, jump on sign.
2251 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2253 RHS = DAG.getConstant(0, RHS.getValueType());
2254 return X86::COND_LE;
2258 switch (SetCCOpcode) {
2259 default: llvm_unreachable("Invalid integer condition!");
2260 case ISD::SETEQ: return X86::COND_E;
2261 case ISD::SETGT: return X86::COND_G;
2262 case ISD::SETGE: return X86::COND_GE;
2263 case ISD::SETLT: return X86::COND_L;
2264 case ISD::SETLE: return X86::COND_LE;
2265 case ISD::SETNE: return X86::COND_NE;
2266 case ISD::SETULT: return X86::COND_B;
2267 case ISD::SETUGT: return X86::COND_A;
2268 case ISD::SETULE: return X86::COND_BE;
2269 case ISD::SETUGE: return X86::COND_AE;
2273 // First determine if it is required or is profitable to flip the operands.
2275 // If LHS is a foldable load, but RHS is not, flip the condition.
2276 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2277 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2278 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2279 std::swap(LHS, RHS);
2282 switch (SetCCOpcode) {
2288 std::swap(LHS, RHS);
2292 // On a floating point condition, the flags are set as follows:
2294 // 0 | 0 | 0 | X > Y
2295 // 0 | 0 | 1 | X < Y
2296 // 1 | 0 | 0 | X == Y
2297 // 1 | 1 | 1 | unordered
2298 switch (SetCCOpcode) {
2299 default: llvm_unreachable("Condcode should be pre-legalized away");
2301 case ISD::SETEQ: return X86::COND_E;
2302 case ISD::SETOLT: // flipped
2304 case ISD::SETGT: return X86::COND_A;
2305 case ISD::SETOLE: // flipped
2307 case ISD::SETGE: return X86::COND_AE;
2308 case ISD::SETUGT: // flipped
2310 case ISD::SETLT: return X86::COND_B;
2311 case ISD::SETUGE: // flipped
2313 case ISD::SETLE: return X86::COND_BE;
2315 case ISD::SETNE: return X86::COND_NE;
2316 case ISD::SETUO: return X86::COND_P;
2317 case ISD::SETO: return X86::COND_NP;
2319 case ISD::SETUNE: return X86::COND_INVALID;
2323 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2324 /// code. Current x86 isa includes the following FP cmov instructions:
2325 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2326 static bool hasFPCMov(unsigned X86CC) {
2342 /// isFPImmLegal - Returns true if the target can instruction select the
2343 /// specified FP immediate natively. If false, the legalizer will
2344 /// materialize the FP immediate as a load from a constant pool.
2345 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2346 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2347 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2353 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2354 /// the specified range (L, H].
2355 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2356 return (Val < 0) || (Val >= Low && Val < Hi);
2359 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2360 /// specified value.
2361 static bool isUndefOrEqual(int Val, int CmpVal) {
2362 if (Val < 0 || Val == CmpVal)
2367 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2368 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2369 /// the second operand.
2370 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2371 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2372 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2373 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2374 return (Mask[0] < 2 && Mask[1] < 2);
2378 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2379 SmallVector<int, 8> M;
2381 return ::isPSHUFDMask(M, N->getValueType(0));
2384 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2385 /// is suitable for input to PSHUFHW.
2386 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2387 if (VT != MVT::v8i16)
2390 // Lower quadword copied in order or undef.
2391 for (int i = 0; i != 4; ++i)
2392 if (Mask[i] >= 0 && Mask[i] != i)
2395 // Upper quadword shuffled.
2396 for (int i = 4; i != 8; ++i)
2397 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2403 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2404 SmallVector<int, 8> M;
2406 return ::isPSHUFHWMask(M, N->getValueType(0));
2409 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2410 /// is suitable for input to PSHUFLW.
2411 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2412 if (VT != MVT::v8i16)
2415 // Upper quadword copied in order.
2416 for (int i = 4; i != 8; ++i)
2417 if (Mask[i] >= 0 && Mask[i] != i)
2420 // Lower quadword shuffled.
2421 for (int i = 0; i != 4; ++i)
2428 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2429 SmallVector<int, 8> M;
2431 return ::isPSHUFLWMask(M, N->getValueType(0));
2434 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2435 /// is suitable for input to PALIGNR.
2436 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2438 int i, e = VT.getVectorNumElements();
2440 // Do not handle v2i64 / v2f64 shuffles with palignr.
2441 if (e < 4 || !hasSSSE3)
2444 for (i = 0; i != e; ++i)
2448 // All undef, not a palignr.
2452 // Determine if it's ok to perform a palignr with only the LHS, since we
2453 // don't have access to the actual shuffle elements to see if RHS is undef.
2454 bool Unary = Mask[i] < (int)e;
2455 bool NeedsUnary = false;
2457 int s = Mask[i] - i;
2459 // Check the rest of the elements to see if they are consecutive.
2460 for (++i; i != e; ++i) {
2465 Unary = Unary && (m < (int)e);
2466 NeedsUnary = NeedsUnary || (m < s);
2468 if (NeedsUnary && !Unary)
2470 if (Unary && m != ((s+i) & (e-1)))
2472 if (!Unary && m != (s+i))
2478 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2479 SmallVector<int, 8> M;
2481 return ::isPALIGNRMask(M, N->getValueType(0), true);
2484 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2485 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2486 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2487 int NumElems = VT.getVectorNumElements();
2488 if (NumElems != 2 && NumElems != 4)
2491 int Half = NumElems / 2;
2492 for (int i = 0; i < Half; ++i)
2493 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2495 for (int i = Half; i < NumElems; ++i)
2496 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2502 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2503 SmallVector<int, 8> M;
2505 return ::isSHUFPMask(M, N->getValueType(0));
2508 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2509 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2510 /// half elements to come from vector 1 (which would equal the dest.) and
2511 /// the upper half to come from vector 2.
2512 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2513 int NumElems = VT.getVectorNumElements();
2515 if (NumElems != 2 && NumElems != 4)
2518 int Half = NumElems / 2;
2519 for (int i = 0; i < Half; ++i)
2520 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2522 for (int i = Half; i < NumElems; ++i)
2523 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2528 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2529 SmallVector<int, 8> M;
2531 return isCommutedSHUFPMask(M, N->getValueType(0));
2534 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2535 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2536 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2537 if (N->getValueType(0).getVectorNumElements() != 4)
2540 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2541 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2542 isUndefOrEqual(N->getMaskElt(1), 7) &&
2543 isUndefOrEqual(N->getMaskElt(2), 2) &&
2544 isUndefOrEqual(N->getMaskElt(3), 3);
2547 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2548 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2550 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2551 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2556 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2557 isUndefOrEqual(N->getMaskElt(1), 3) &&
2558 isUndefOrEqual(N->getMaskElt(2), 2) &&
2559 isUndefOrEqual(N->getMaskElt(3), 3);
2562 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2563 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2564 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2565 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2567 if (NumElems != 2 && NumElems != 4)
2570 for (unsigned i = 0; i < NumElems/2; ++i)
2571 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2574 for (unsigned i = NumElems/2; i < NumElems; ++i)
2575 if (!isUndefOrEqual(N->getMaskElt(i), i))
2581 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
2582 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
2583 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
2584 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2586 if (NumElems != 2 && NumElems != 4)
2589 for (unsigned i = 0; i < NumElems/2; ++i)
2590 if (!isUndefOrEqual(N->getMaskElt(i), i))
2593 for (unsigned i = 0; i < NumElems/2; ++i)
2594 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2600 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2601 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2602 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2603 bool V2IsSplat = false) {
2604 int NumElts = VT.getVectorNumElements();
2605 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2608 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2610 int BitI1 = Mask[i+1];
2611 if (!isUndefOrEqual(BitI, j))
2614 if (!isUndefOrEqual(BitI1, NumElts))
2617 if (!isUndefOrEqual(BitI1, j + NumElts))
2624 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2625 SmallVector<int, 8> M;
2627 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2630 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2631 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2632 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2633 bool V2IsSplat = false) {
2634 int NumElts = VT.getVectorNumElements();
2635 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2638 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2640 int BitI1 = Mask[i+1];
2641 if (!isUndefOrEqual(BitI, j + NumElts/2))
2644 if (isUndefOrEqual(BitI1, NumElts))
2647 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2654 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2655 SmallVector<int, 8> M;
2657 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2660 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2661 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2663 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2664 int NumElems = VT.getVectorNumElements();
2665 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2668 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2670 int BitI1 = Mask[i+1];
2671 if (!isUndefOrEqual(BitI, j))
2673 if (!isUndefOrEqual(BitI1, j))
2679 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2680 SmallVector<int, 8> M;
2682 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2685 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2686 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2688 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2689 int NumElems = VT.getVectorNumElements();
2690 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2693 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2695 int BitI1 = Mask[i+1];
2696 if (!isUndefOrEqual(BitI, j))
2698 if (!isUndefOrEqual(BitI1, j))
2704 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2705 SmallVector<int, 8> M;
2707 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2710 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2711 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2712 /// MOVSD, and MOVD, i.e. setting the lowest element.
2713 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2714 if (VT.getVectorElementType().getSizeInBits() < 32)
2717 int NumElts = VT.getVectorNumElements();
2719 if (!isUndefOrEqual(Mask[0], NumElts))
2722 for (int i = 1; i < NumElts; ++i)
2723 if (!isUndefOrEqual(Mask[i], i))
2729 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2730 SmallVector<int, 8> M;
2732 return ::isMOVLMask(M, N->getValueType(0));
2735 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2736 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2737 /// element of vector 2 and the other elements to come from vector 1 in order.
2738 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2739 bool V2IsSplat = false, bool V2IsUndef = false) {
2740 int NumOps = VT.getVectorNumElements();
2741 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2744 if (!isUndefOrEqual(Mask[0], 0))
2747 for (int i = 1; i < NumOps; ++i)
2748 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2749 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2750 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2756 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2757 bool V2IsUndef = false) {
2758 SmallVector<int, 8> M;
2760 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2763 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2764 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2765 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2766 if (N->getValueType(0).getVectorNumElements() != 4)
2769 // Expect 1, 1, 3, 3
2770 for (unsigned i = 0; i < 2; ++i) {
2771 int Elt = N->getMaskElt(i);
2772 if (Elt >= 0 && Elt != 1)
2777 for (unsigned i = 2; i < 4; ++i) {
2778 int Elt = N->getMaskElt(i);
2779 if (Elt >= 0 && Elt != 3)
2784 // Don't use movshdup if it can be done with a shufps.
2785 // FIXME: verify that matching u, u, 3, 3 is what we want.
2789 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2790 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2791 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2792 if (N->getValueType(0).getVectorNumElements() != 4)
2795 // Expect 0, 0, 2, 2
2796 for (unsigned i = 0; i < 2; ++i)
2797 if (N->getMaskElt(i) > 0)
2801 for (unsigned i = 2; i < 4; ++i) {
2802 int Elt = N->getMaskElt(i);
2803 if (Elt >= 0 && Elt != 2)
2808 // Don't use movsldup if it can be done with a shufps.
2812 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2813 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2814 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2815 int e = N->getValueType(0).getVectorNumElements() / 2;
2817 for (int i = 0; i < e; ++i)
2818 if (!isUndefOrEqual(N->getMaskElt(i), i))
2820 for (int i = 0; i < e; ++i)
2821 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2826 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2827 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
2828 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2830 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2832 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2834 for (int i = 0; i < NumOperands; ++i) {
2835 int Val = SVOp->getMaskElt(NumOperands-i-1);
2836 if (Val < 0) Val = 0;
2837 if (Val >= NumOperands) Val -= NumOperands;
2839 if (i != NumOperands - 1)
2845 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2846 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
2847 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2848 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2850 // 8 nodes, but we only care about the last 4.
2851 for (unsigned i = 7; i >= 4; --i) {
2852 int Val = SVOp->getMaskElt(i);
2861 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2862 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
2863 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2864 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2866 // 8 nodes, but we only care about the first 4.
2867 for (int i = 3; i >= 0; --i) {
2868 int Val = SVOp->getMaskElt(i);
2877 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
2878 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
2879 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
2880 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2881 EVT VVT = N->getValueType(0);
2882 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
2886 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
2887 Val = SVOp->getMaskElt(i);
2891 return (Val - i) * EltSize;
2894 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2896 bool X86::isZeroNode(SDValue Elt) {
2897 return ((isa<ConstantSDNode>(Elt) &&
2898 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2899 (isa<ConstantFPSDNode>(Elt) &&
2900 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2903 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2904 /// their permute mask.
2905 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2906 SelectionDAG &DAG) {
2907 EVT VT = SVOp->getValueType(0);
2908 unsigned NumElems = VT.getVectorNumElements();
2909 SmallVector<int, 8> MaskVec;
2911 for (unsigned i = 0; i != NumElems; ++i) {
2912 int idx = SVOp->getMaskElt(i);
2914 MaskVec.push_back(idx);
2915 else if (idx < (int)NumElems)
2916 MaskVec.push_back(idx + NumElems);
2918 MaskVec.push_back(idx - NumElems);
2920 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2921 SVOp->getOperand(0), &MaskVec[0]);
2924 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2925 /// the two vector operands have swapped position.
2926 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2927 unsigned NumElems = VT.getVectorNumElements();
2928 for (unsigned i = 0; i != NumElems; ++i) {
2932 else if (idx < (int)NumElems)
2933 Mask[i] = idx + NumElems;
2935 Mask[i] = idx - NumElems;
2939 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2940 /// match movhlps. The lower half elements should come from upper half of
2941 /// V1 (and in order), and the upper half elements should come from the upper
2942 /// half of V2 (and in order).
2943 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2944 if (Op->getValueType(0).getVectorNumElements() != 4)
2946 for (unsigned i = 0, e = 2; i != e; ++i)
2947 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2949 for (unsigned i = 2; i != 4; ++i)
2950 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2955 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2956 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2958 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2959 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2961 N = N->getOperand(0).getNode();
2962 if (!ISD::isNON_EXTLoad(N))
2965 *LD = cast<LoadSDNode>(N);
2969 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2970 /// match movlp{s|d}. The lower half elements should come from lower half of
2971 /// V1 (and in order), and the upper half elements should come from the upper
2972 /// half of V2 (and in order). And since V1 will become the source of the
2973 /// MOVLP, it must be either a vector load or a scalar load to vector.
2974 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2975 ShuffleVectorSDNode *Op) {
2976 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2978 // Is V2 is a vector load, don't do this transformation. We will try to use
2979 // load folding shufps op.
2980 if (ISD::isNON_EXTLoad(V2))
2983 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2985 if (NumElems != 2 && NumElems != 4)
2987 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2988 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2990 for (unsigned i = NumElems/2; i != NumElems; ++i)
2991 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2996 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2998 static bool isSplatVector(SDNode *N) {
2999 if (N->getOpcode() != ISD::BUILD_VECTOR)
3002 SDValue SplatValue = N->getOperand(0);
3003 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3004 if (N->getOperand(i) != SplatValue)
3009 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3010 /// to an zero vector.
3011 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3012 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3013 SDValue V1 = N->getOperand(0);
3014 SDValue V2 = N->getOperand(1);
3015 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3016 for (unsigned i = 0; i != NumElems; ++i) {
3017 int Idx = N->getMaskElt(i);
3018 if (Idx >= (int)NumElems) {
3019 unsigned Opc = V2.getOpcode();
3020 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3022 if (Opc != ISD::BUILD_VECTOR ||
3023 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3025 } else if (Idx >= 0) {
3026 unsigned Opc = V1.getOpcode();
3027 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3029 if (Opc != ISD::BUILD_VECTOR ||
3030 !X86::isZeroNode(V1.getOperand(Idx)))
3037 /// getZeroVector - Returns a vector of specified type with all zero elements.
3039 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3041 assert(VT.isVector() && "Expected a vector type");
3043 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3044 // type. This ensures they get CSE'd.
3046 if (VT.getSizeInBits() == 64) { // MMX
3047 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3048 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3049 } else if (HasSSE2) { // SSE2
3050 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3051 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3053 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3054 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3056 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3059 /// getOnesVector - Returns a vector of specified type with all bits set.
3061 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3062 assert(VT.isVector() && "Expected a vector type");
3064 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3065 // type. This ensures they get CSE'd.
3066 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3068 if (VT.getSizeInBits() == 64) // MMX
3069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3071 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3072 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3076 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3077 /// that point to V2 points to its first element.
3078 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3079 EVT VT = SVOp->getValueType(0);
3080 unsigned NumElems = VT.getVectorNumElements();
3082 bool Changed = false;
3083 SmallVector<int, 8> MaskVec;
3084 SVOp->getMask(MaskVec);
3086 for (unsigned i = 0; i != NumElems; ++i) {
3087 if (MaskVec[i] > (int)NumElems) {
3088 MaskVec[i] = NumElems;
3093 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3094 SVOp->getOperand(1), &MaskVec[0]);
3095 return SDValue(SVOp, 0);
3098 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3099 /// operation of specified width.
3100 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3102 unsigned NumElems = VT.getVectorNumElements();
3103 SmallVector<int, 8> Mask;
3104 Mask.push_back(NumElems);
3105 for (unsigned i = 1; i != NumElems; ++i)
3107 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3110 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3111 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3113 unsigned NumElems = VT.getVectorNumElements();
3114 SmallVector<int, 8> Mask;
3115 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3117 Mask.push_back(i + NumElems);
3119 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3122 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3123 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3125 unsigned NumElems = VT.getVectorNumElements();
3126 unsigned Half = NumElems/2;
3127 SmallVector<int, 8> Mask;
3128 for (unsigned i = 0; i != Half; ++i) {
3129 Mask.push_back(i + Half);
3130 Mask.push_back(i + NumElems + Half);
3132 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3135 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3136 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3138 if (SV->getValueType(0).getVectorNumElements() <= 4)
3139 return SDValue(SV, 0);
3141 EVT PVT = MVT::v4f32;
3142 EVT VT = SV->getValueType(0);
3143 DebugLoc dl = SV->getDebugLoc();
3144 SDValue V1 = SV->getOperand(0);
3145 int NumElems = VT.getVectorNumElements();
3146 int EltNo = SV->getSplatIndex();
3148 // unpack elements to the correct location
3149 while (NumElems > 4) {
3150 if (EltNo < NumElems/2) {
3151 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3153 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3154 EltNo -= NumElems/2;
3159 // Perform the splat.
3160 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3161 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3162 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3163 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3166 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3167 /// vector of zero or undef vector. This produces a shuffle where the low
3168 /// element of V2 is swizzled into the zero/undef vector, landing at element
3169 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3170 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3171 bool isZero, bool HasSSE2,
3172 SelectionDAG &DAG) {
3173 EVT VT = V2.getValueType();
3175 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3176 unsigned NumElems = VT.getVectorNumElements();
3177 SmallVector<int, 16> MaskVec;
3178 for (unsigned i = 0; i != NumElems; ++i)
3179 // If this is the insertion idx, put the low elt of V2 here.
3180 MaskVec.push_back(i == Idx ? NumElems : i);
3181 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3184 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3185 /// a shuffle that is zero.
3187 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3188 bool Low, SelectionDAG &DAG) {
3189 unsigned NumZeros = 0;
3190 for (int i = 0; i < NumElems; ++i) {
3191 unsigned Index = Low ? i : NumElems-i-1;
3192 int Idx = SVOp->getMaskElt(Index);
3197 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3198 if (Elt.getNode() && X86::isZeroNode(Elt))
3206 /// isVectorShift - Returns true if the shuffle can be implemented as a
3207 /// logical left or right shift of a vector.
3208 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3209 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3210 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3211 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3214 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3217 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3221 bool SeenV1 = false;
3222 bool SeenV2 = false;
3223 for (int i = NumZeros; i < NumElems; ++i) {
3224 int Val = isLeft ? (i - NumZeros) : i;
3225 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3237 if (SeenV1 && SeenV2)
3240 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3246 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3248 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3249 unsigned NumNonZero, unsigned NumZero,
3250 SelectionDAG &DAG, TargetLowering &TLI) {
3254 DebugLoc dl = Op.getDebugLoc();
3257 for (unsigned i = 0; i < 16; ++i) {
3258 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3259 if (ThisIsNonZero && First) {
3261 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3263 V = DAG.getUNDEF(MVT::v8i16);
3268 SDValue ThisElt(0, 0), LastElt(0, 0);
3269 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3270 if (LastIsNonZero) {
3271 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3272 MVT::i16, Op.getOperand(i-1));
3274 if (ThisIsNonZero) {
3275 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3276 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3277 ThisElt, DAG.getConstant(8, MVT::i8));
3279 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3283 if (ThisElt.getNode())
3284 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3285 DAG.getIntPtrConstant(i/2));
3289 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3292 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3294 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3295 unsigned NumNonZero, unsigned NumZero,
3296 SelectionDAG &DAG, TargetLowering &TLI) {
3300 DebugLoc dl = Op.getDebugLoc();
3303 for (unsigned i = 0; i < 8; ++i) {
3304 bool isNonZero = (NonZeros & (1 << i)) != 0;
3308 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3310 V = DAG.getUNDEF(MVT::v8i16);
3313 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3314 MVT::v8i16, V, Op.getOperand(i),
3315 DAG.getIntPtrConstant(i));
3322 /// getVShift - Return a vector logical shift node.
3324 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3325 unsigned NumBits, SelectionDAG &DAG,
3326 const TargetLowering &TLI, DebugLoc dl) {
3327 bool isMMX = VT.getSizeInBits() == 64;
3328 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3329 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3330 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3331 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3332 DAG.getNode(Opc, dl, ShVT, SrcOp,
3333 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3337 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3338 DebugLoc dl = Op.getDebugLoc();
3339 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3340 if (ISD::isBuildVectorAllZeros(Op.getNode())
3341 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3342 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3343 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3344 // eliminated on x86-32 hosts.
3345 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3348 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3349 return getOnesVector(Op.getValueType(), DAG, dl);
3350 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3353 EVT VT = Op.getValueType();
3354 EVT ExtVT = VT.getVectorElementType();
3355 unsigned EVTBits = ExtVT.getSizeInBits();
3357 unsigned NumElems = Op.getNumOperands();
3358 unsigned NumZero = 0;
3359 unsigned NumNonZero = 0;
3360 unsigned NonZeros = 0;
3361 bool IsAllConstants = true;
3362 SmallSet<SDValue, 8> Values;
3363 for (unsigned i = 0; i < NumElems; ++i) {
3364 SDValue Elt = Op.getOperand(i);
3365 if (Elt.getOpcode() == ISD::UNDEF)
3368 if (Elt.getOpcode() != ISD::Constant &&
3369 Elt.getOpcode() != ISD::ConstantFP)
3370 IsAllConstants = false;
3371 if (X86::isZeroNode(Elt))
3374 NonZeros |= (1 << i);
3379 if (NumNonZero == 0) {
3380 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3381 return DAG.getUNDEF(VT);
3384 // Special case for single non-zero, non-undef, element.
3385 if (NumNonZero == 1) {
3386 unsigned Idx = CountTrailingZeros_32(NonZeros);
3387 SDValue Item = Op.getOperand(Idx);
3389 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3390 // the value are obviously zero, truncate the value to i32 and do the
3391 // insertion that way. Only do this if the value is non-constant or if the
3392 // value is a constant being inserted into element 0. It is cheaper to do
3393 // a constant pool load than it is to do a movd + shuffle.
3394 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3395 (!IsAllConstants || Idx == 0)) {
3396 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3397 // Handle MMX and SSE both.
3398 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3399 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3401 // Truncate the value (which may itself be a constant) to i32, and
3402 // convert it to a vector with movd (S2V+shuffle to zero extend).
3403 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3404 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3405 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3406 Subtarget->hasSSE2(), DAG);
3408 // Now we have our 32-bit value zero extended in the low element of
3409 // a vector. If Idx != 0, swizzle it into place.
3411 SmallVector<int, 4> Mask;
3412 Mask.push_back(Idx);
3413 for (unsigned i = 1; i != VecElts; ++i)
3415 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3416 DAG.getUNDEF(Item.getValueType()),
3419 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3423 // If we have a constant or non-constant insertion into the low element of
3424 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3425 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3426 // depending on what the source datatype is.
3429 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3430 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3431 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3432 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3433 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3434 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3436 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3437 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3438 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3439 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3440 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3441 Subtarget->hasSSE2(), DAG);
3442 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3446 // Is it a vector logical left shift?
3447 if (NumElems == 2 && Idx == 1 &&
3448 X86::isZeroNode(Op.getOperand(0)) &&
3449 !X86::isZeroNode(Op.getOperand(1))) {
3450 unsigned NumBits = VT.getSizeInBits();
3451 return getVShift(true, VT,
3452 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3453 VT, Op.getOperand(1)),
3454 NumBits/2, DAG, *this, dl);
3457 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3460 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3461 // is a non-constant being inserted into an element other than the low one,
3462 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3463 // movd/movss) to move this into the low element, then shuffle it into
3465 if (EVTBits == 32) {
3466 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3468 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3469 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3470 Subtarget->hasSSE2(), DAG);
3471 SmallVector<int, 8> MaskVec;
3472 for (unsigned i = 0; i < NumElems; i++)
3473 MaskVec.push_back(i == Idx ? 0 : 1);
3474 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3478 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3479 if (Values.size() == 1)
3482 // A vector full of immediates; various special cases are already
3483 // handled, so this is best done with a single constant-pool load.
3487 // Let legalizer expand 2-wide build_vectors.
3488 if (EVTBits == 64) {
3489 if (NumNonZero == 1) {
3490 // One half is zero or undef.
3491 unsigned Idx = CountTrailingZeros_32(NonZeros);
3492 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3493 Op.getOperand(Idx));
3494 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3495 Subtarget->hasSSE2(), DAG);
3500 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3501 if (EVTBits == 8 && NumElems == 16) {
3502 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3504 if (V.getNode()) return V;
3507 if (EVTBits == 16 && NumElems == 8) {
3508 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3510 if (V.getNode()) return V;
3513 // If element VT is == 32 bits, turn it into a number of shuffles.
3514 SmallVector<SDValue, 8> V;
3516 if (NumElems == 4 && NumZero > 0) {
3517 for (unsigned i = 0; i < 4; ++i) {
3518 bool isZero = !(NonZeros & (1 << i));
3520 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3522 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3525 for (unsigned i = 0; i < 2; ++i) {
3526 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3529 V[i] = V[i*2]; // Must be a zero vector.
3532 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3535 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3538 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3543 SmallVector<int, 8> MaskVec;
3544 bool Reverse = (NonZeros & 0x3) == 2;
3545 for (unsigned i = 0; i < 2; ++i)
3546 MaskVec.push_back(Reverse ? 1-i : i);
3547 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3548 for (unsigned i = 0; i < 2; ++i)
3549 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3550 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3553 if (Values.size() > 2) {
3554 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3555 // values to be inserted is equal to the number of elements, in which case
3556 // use the unpack code below in the hopes of matching the consecutive elts
3557 // load merge pattern for shuffles.
3558 // FIXME: We could probably just check that here directly.
3559 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3560 getSubtarget()->hasSSE41()) {
3561 V[0] = DAG.getUNDEF(VT);
3562 for (unsigned i = 0; i < NumElems; ++i)
3563 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3564 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3565 Op.getOperand(i), DAG.getIntPtrConstant(i));
3568 // Expand into a number of unpckl*.
3570 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3571 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3572 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3573 for (unsigned i = 0; i < NumElems; ++i)
3574 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3576 while (NumElems != 0) {
3577 for (unsigned i = 0; i < NumElems; ++i)
3578 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3587 // v8i16 shuffles - Prefer shuffles in the following order:
3588 // 1. [all] pshuflw, pshufhw, optional move
3589 // 2. [ssse3] 1 x pshufb
3590 // 3. [ssse3] 2 x pshufb + 1 x por
3591 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3593 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3594 SelectionDAG &DAG, X86TargetLowering &TLI) {
3595 SDValue V1 = SVOp->getOperand(0);
3596 SDValue V2 = SVOp->getOperand(1);
3597 DebugLoc dl = SVOp->getDebugLoc();
3598 SmallVector<int, 8> MaskVals;
3600 // Determine if more than 1 of the words in each of the low and high quadwords
3601 // of the result come from the same quadword of one of the two inputs. Undef
3602 // mask values count as coming from any quadword, for better codegen.
3603 SmallVector<unsigned, 4> LoQuad(4);
3604 SmallVector<unsigned, 4> HiQuad(4);
3605 BitVector InputQuads(4);
3606 for (unsigned i = 0; i < 8; ++i) {
3607 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3608 int EltIdx = SVOp->getMaskElt(i);
3609 MaskVals.push_back(EltIdx);
3618 InputQuads.set(EltIdx / 4);
3621 int BestLoQuad = -1;
3622 unsigned MaxQuad = 1;
3623 for (unsigned i = 0; i < 4; ++i) {
3624 if (LoQuad[i] > MaxQuad) {
3626 MaxQuad = LoQuad[i];
3630 int BestHiQuad = -1;
3632 for (unsigned i = 0; i < 4; ++i) {
3633 if (HiQuad[i] > MaxQuad) {
3635 MaxQuad = HiQuad[i];
3639 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3640 // of the two input vectors, shuffle them into one input vector so only a
3641 // single pshufb instruction is necessary. If There are more than 2 input
3642 // quads, disable the next transformation since it does not help SSSE3.
3643 bool V1Used = InputQuads[0] || InputQuads[1];
3644 bool V2Used = InputQuads[2] || InputQuads[3];
3645 if (TLI.getSubtarget()->hasSSSE3()) {
3646 if (InputQuads.count() == 2 && V1Used && V2Used) {
3647 BestLoQuad = InputQuads.find_first();
3648 BestHiQuad = InputQuads.find_next(BestLoQuad);
3650 if (InputQuads.count() > 2) {
3656 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3657 // the shuffle mask. If a quad is scored as -1, that means that it contains
3658 // words from all 4 input quadwords.
3660 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3661 SmallVector<int, 8> MaskV;
3662 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3663 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3664 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3665 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3666 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3667 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3669 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3670 // source words for the shuffle, to aid later transformations.
3671 bool AllWordsInNewV = true;
3672 bool InOrder[2] = { true, true };
3673 for (unsigned i = 0; i != 8; ++i) {
3674 int idx = MaskVals[i];
3676 InOrder[i/4] = false;
3677 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3679 AllWordsInNewV = false;
3683 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3684 if (AllWordsInNewV) {
3685 for (int i = 0; i != 8; ++i) {
3686 int idx = MaskVals[i];
3689 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3690 if ((idx != i) && idx < 4)
3692 if ((idx != i) && idx > 3)
3701 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3702 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3703 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3704 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3705 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3709 // If we have SSSE3, and all words of the result are from 1 input vector,
3710 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3711 // is present, fall back to case 4.
3712 if (TLI.getSubtarget()->hasSSSE3()) {
3713 SmallVector<SDValue,16> pshufbMask;
3715 // If we have elements from both input vectors, set the high bit of the
3716 // shuffle mask element to zero out elements that come from V2 in the V1
3717 // mask, and elements that come from V1 in the V2 mask, so that the two
3718 // results can be OR'd together.
3719 bool TwoInputs = V1Used && V2Used;
3720 for (unsigned i = 0; i != 8; ++i) {
3721 int EltIdx = MaskVals[i] * 2;
3722 if (TwoInputs && (EltIdx >= 16)) {
3723 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3724 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3727 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3728 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3730 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3731 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3732 DAG.getNode(ISD::BUILD_VECTOR, dl,
3733 MVT::v16i8, &pshufbMask[0], 16));
3735 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3737 // Calculate the shuffle mask for the second input, shuffle it, and
3738 // OR it with the first shuffled input.
3740 for (unsigned i = 0; i != 8; ++i) {
3741 int EltIdx = MaskVals[i] * 2;
3743 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3744 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3747 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3748 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3750 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3751 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3752 DAG.getNode(ISD::BUILD_VECTOR, dl,
3753 MVT::v16i8, &pshufbMask[0], 16));
3754 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3755 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3758 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3759 // and update MaskVals with new element order.
3760 BitVector InOrder(8);
3761 if (BestLoQuad >= 0) {
3762 SmallVector<int, 8> MaskV;
3763 for (int i = 0; i != 4; ++i) {
3764 int idx = MaskVals[i];
3766 MaskV.push_back(-1);
3768 } else if ((idx / 4) == BestLoQuad) {
3769 MaskV.push_back(idx & 3);
3772 MaskV.push_back(-1);
3775 for (unsigned i = 4; i != 8; ++i)
3777 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3781 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3782 // and update MaskVals with the new element order.
3783 if (BestHiQuad >= 0) {
3784 SmallVector<int, 8> MaskV;
3785 for (unsigned i = 0; i != 4; ++i)
3787 for (unsigned i = 4; i != 8; ++i) {
3788 int idx = MaskVals[i];
3790 MaskV.push_back(-1);
3792 } else if ((idx / 4) == BestHiQuad) {
3793 MaskV.push_back((idx & 3) + 4);
3796 MaskV.push_back(-1);
3799 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3803 // In case BestHi & BestLo were both -1, which means each quadword has a word
3804 // from each of the four input quadwords, calculate the InOrder bitvector now
3805 // before falling through to the insert/extract cleanup.
3806 if (BestLoQuad == -1 && BestHiQuad == -1) {
3808 for (int i = 0; i != 8; ++i)
3809 if (MaskVals[i] < 0 || MaskVals[i] == i)
3813 // The other elements are put in the right place using pextrw and pinsrw.
3814 for (unsigned i = 0; i != 8; ++i) {
3817 int EltIdx = MaskVals[i];
3820 SDValue ExtOp = (EltIdx < 8)
3821 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3822 DAG.getIntPtrConstant(EltIdx))
3823 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3824 DAG.getIntPtrConstant(EltIdx - 8));
3825 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3826 DAG.getIntPtrConstant(i));
3831 // v16i8 shuffles - Prefer shuffles in the following order:
3832 // 1. [ssse3] 1 x pshufb
3833 // 2. [ssse3] 2 x pshufb + 1 x por
3834 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3836 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3837 SelectionDAG &DAG, X86TargetLowering &TLI) {
3838 SDValue V1 = SVOp->getOperand(0);
3839 SDValue V2 = SVOp->getOperand(1);
3840 DebugLoc dl = SVOp->getDebugLoc();
3841 SmallVector<int, 16> MaskVals;
3842 SVOp->getMask(MaskVals);
3844 // If we have SSSE3, case 1 is generated when all result bytes come from
3845 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3846 // present, fall back to case 3.
3847 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3850 for (unsigned i = 0; i < 16; ++i) {
3851 int EltIdx = MaskVals[i];
3860 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3861 if (TLI.getSubtarget()->hasSSSE3()) {
3862 SmallVector<SDValue,16> pshufbMask;
3864 // If all result elements are from one input vector, then only translate
3865 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3867 // Otherwise, we have elements from both input vectors, and must zero out
3868 // elements that come from V2 in the first mask, and V1 in the second mask
3869 // so that we can OR them together.
3870 bool TwoInputs = !(V1Only || V2Only);
3871 for (unsigned i = 0; i != 16; ++i) {
3872 int EltIdx = MaskVals[i];
3873 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3874 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3877 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3879 // If all the elements are from V2, assign it to V1 and return after
3880 // building the first pshufb.
3883 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3884 DAG.getNode(ISD::BUILD_VECTOR, dl,
3885 MVT::v16i8, &pshufbMask[0], 16));
3889 // Calculate the shuffle mask for the second input, shuffle it, and
3890 // OR it with the first shuffled input.
3892 for (unsigned i = 0; i != 16; ++i) {
3893 int EltIdx = MaskVals[i];
3895 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3898 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3900 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3901 DAG.getNode(ISD::BUILD_VECTOR, dl,
3902 MVT::v16i8, &pshufbMask[0], 16));
3903 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3906 // No SSSE3 - Calculate in place words and then fix all out of place words
3907 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3908 // the 16 different words that comprise the two doublequadword input vectors.
3909 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3910 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3911 SDValue NewV = V2Only ? V2 : V1;
3912 for (int i = 0; i != 8; ++i) {
3913 int Elt0 = MaskVals[i*2];
3914 int Elt1 = MaskVals[i*2+1];
3916 // This word of the result is all undef, skip it.
3917 if (Elt0 < 0 && Elt1 < 0)
3920 // This word of the result is already in the correct place, skip it.
3921 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3923 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3926 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3927 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3930 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3931 // using a single extract together, load it and store it.
3932 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3933 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3934 DAG.getIntPtrConstant(Elt1 / 2));
3935 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3936 DAG.getIntPtrConstant(i));
3940 // If Elt1 is defined, extract it from the appropriate source. If the
3941 // source byte is not also odd, shift the extracted word left 8 bits
3942 // otherwise clear the bottom 8 bits if we need to do an or.
3944 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3945 DAG.getIntPtrConstant(Elt1 / 2));
3946 if ((Elt1 & 1) == 0)
3947 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3948 DAG.getConstant(8, TLI.getShiftAmountTy()));
3950 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3951 DAG.getConstant(0xFF00, MVT::i16));
3953 // If Elt0 is defined, extract it from the appropriate source. If the
3954 // source byte is not also even, shift the extracted word right 8 bits. If
3955 // Elt1 was also defined, OR the extracted values together before
3956 // inserting them in the result.
3958 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3959 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3960 if ((Elt0 & 1) != 0)
3961 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3962 DAG.getConstant(8, TLI.getShiftAmountTy()));
3964 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3965 DAG.getConstant(0x00FF, MVT::i16));
3966 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3969 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3970 DAG.getIntPtrConstant(i));
3972 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3975 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3976 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3977 /// done when every pair / quad of shuffle mask elements point to elements in
3978 /// the right sequence. e.g.
3979 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3981 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3983 TargetLowering &TLI, DebugLoc dl) {
3984 EVT VT = SVOp->getValueType(0);
3985 SDValue V1 = SVOp->getOperand(0);
3986 SDValue V2 = SVOp->getOperand(1);
3987 unsigned NumElems = VT.getVectorNumElements();
3988 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3989 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3990 EVT MaskEltVT = MaskVT.getVectorElementType();
3992 switch (VT.getSimpleVT().SimpleTy) {
3993 default: assert(false && "Unexpected!");
3994 case MVT::v4f32: NewVT = MVT::v2f64; break;
3995 case MVT::v4i32: NewVT = MVT::v2i64; break;
3996 case MVT::v8i16: NewVT = MVT::v4i32; break;
3997 case MVT::v16i8: NewVT = MVT::v4i32; break;
4000 if (NewWidth == 2) {
4006 int Scale = NumElems / NewWidth;
4007 SmallVector<int, 8> MaskVec;
4008 for (unsigned i = 0; i < NumElems; i += Scale) {
4010 for (int j = 0; j < Scale; ++j) {
4011 int EltIdx = SVOp->getMaskElt(i+j);
4015 StartIdx = EltIdx - (EltIdx % Scale);
4016 if (EltIdx != StartIdx + j)
4020 MaskVec.push_back(-1);
4022 MaskVec.push_back(StartIdx / Scale);
4025 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4026 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4027 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4030 /// getVZextMovL - Return a zero-extending vector move low node.
4032 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4033 SDValue SrcOp, SelectionDAG &DAG,
4034 const X86Subtarget *Subtarget, DebugLoc dl) {
4035 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4036 LoadSDNode *LD = NULL;
4037 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4038 LD = dyn_cast<LoadSDNode>(SrcOp);
4040 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4042 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4043 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4044 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4045 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4046 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4048 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4049 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4050 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4051 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4059 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4060 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4061 DAG.getNode(ISD::BIT_CONVERT, dl,
4065 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4068 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4069 SDValue V1 = SVOp->getOperand(0);
4070 SDValue V2 = SVOp->getOperand(1);
4071 DebugLoc dl = SVOp->getDebugLoc();
4072 EVT VT = SVOp->getValueType(0);
4074 SmallVector<std::pair<int, int>, 8> Locs;
4076 SmallVector<int, 8> Mask1(4U, -1);
4077 SmallVector<int, 8> PermMask;
4078 SVOp->getMask(PermMask);
4082 for (unsigned i = 0; i != 4; ++i) {
4083 int Idx = PermMask[i];
4085 Locs[i] = std::make_pair(-1, -1);
4087 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4089 Locs[i] = std::make_pair(0, NumLo);
4093 Locs[i] = std::make_pair(1, NumHi);
4095 Mask1[2+NumHi] = Idx;
4101 if (NumLo <= 2 && NumHi <= 2) {
4102 // If no more than two elements come from either vector. This can be
4103 // implemented with two shuffles. First shuffle gather the elements.
4104 // The second shuffle, which takes the first shuffle as both of its
4105 // vector operands, put the elements into the right order.
4106 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4108 SmallVector<int, 8> Mask2(4U, -1);
4110 for (unsigned i = 0; i != 4; ++i) {
4111 if (Locs[i].first == -1)
4114 unsigned Idx = (i < 2) ? 0 : 4;
4115 Idx += Locs[i].first * 2 + Locs[i].second;
4120 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4121 } else if (NumLo == 3 || NumHi == 3) {
4122 // Otherwise, we must have three elements from one vector, call it X, and
4123 // one element from the other, call it Y. First, use a shufps to build an
4124 // intermediate vector with the one element from Y and the element from X
4125 // that will be in the same half in the final destination (the indexes don't
4126 // matter). Then, use a shufps to build the final vector, taking the half
4127 // containing the element from Y from the intermediate, and the other half
4130 // Normalize it so the 3 elements come from V1.
4131 CommuteVectorShuffleMask(PermMask, VT);
4135 // Find the element from V2.
4137 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4138 int Val = PermMask[HiIndex];
4145 Mask1[0] = PermMask[HiIndex];
4147 Mask1[2] = PermMask[HiIndex^1];
4149 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4152 Mask1[0] = PermMask[0];
4153 Mask1[1] = PermMask[1];
4154 Mask1[2] = HiIndex & 1 ? 6 : 4;
4155 Mask1[3] = HiIndex & 1 ? 4 : 6;
4156 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4158 Mask1[0] = HiIndex & 1 ? 2 : 0;
4159 Mask1[1] = HiIndex & 1 ? 0 : 2;
4160 Mask1[2] = PermMask[2];
4161 Mask1[3] = PermMask[3];
4166 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4170 // Break it into (shuffle shuffle_hi, shuffle_lo).
4172 SmallVector<int,8> LoMask(4U, -1);
4173 SmallVector<int,8> HiMask(4U, -1);
4175 SmallVector<int,8> *MaskPtr = &LoMask;
4176 unsigned MaskIdx = 0;
4179 for (unsigned i = 0; i != 4; ++i) {
4186 int Idx = PermMask[i];
4188 Locs[i] = std::make_pair(-1, -1);
4189 } else if (Idx < 4) {
4190 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4191 (*MaskPtr)[LoIdx] = Idx;
4194 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4195 (*MaskPtr)[HiIdx] = Idx;
4200 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4201 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4202 SmallVector<int, 8> MaskOps;
4203 for (unsigned i = 0; i != 4; ++i) {
4204 if (Locs[i].first == -1) {
4205 MaskOps.push_back(-1);
4207 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4208 MaskOps.push_back(Idx);
4211 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4215 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4216 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4217 SDValue V1 = Op.getOperand(0);
4218 SDValue V2 = Op.getOperand(1);
4219 EVT VT = Op.getValueType();
4220 DebugLoc dl = Op.getDebugLoc();
4221 unsigned NumElems = VT.getVectorNumElements();
4222 bool isMMX = VT.getSizeInBits() == 64;
4223 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4224 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4225 bool V1IsSplat = false;
4226 bool V2IsSplat = false;
4228 if (isZeroShuffle(SVOp))
4229 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4231 // Promote splats to v4f32.
4232 if (SVOp->isSplat()) {
4233 if (isMMX || NumElems < 4)
4235 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4238 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4240 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4241 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4242 if (NewOp.getNode())
4243 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4244 LowerVECTOR_SHUFFLE(NewOp, DAG));
4245 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4246 // FIXME: Figure out a cleaner way to do this.
4247 // Try to make use of movq to zero out the top part.
4248 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4249 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4250 if (NewOp.getNode()) {
4251 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4252 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4253 DAG, Subtarget, dl);
4255 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4256 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4257 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4258 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4259 DAG, Subtarget, dl);
4263 if (X86::isPSHUFDMask(SVOp))
4266 // Check if this can be converted into a logical shift.
4267 bool isLeft = false;
4270 bool isShift = getSubtarget()->hasSSE2() &&
4271 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4272 if (isShift && ShVal.hasOneUse()) {
4273 // If the shifted value has multiple uses, it may be cheaper to use
4274 // v_set0 + movlhps or movhlps, etc.
4275 EVT EltVT = VT.getVectorElementType();
4276 ShAmt *= EltVT.getSizeInBits();
4277 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4280 if (X86::isMOVLMask(SVOp)) {
4283 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4284 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4289 // FIXME: fold these into legal mask.
4290 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4291 X86::isMOVSLDUPMask(SVOp) ||
4292 X86::isMOVHLPSMask(SVOp) ||
4293 X86::isMOVLHPSMask(SVOp) ||
4294 X86::isMOVLPMask(SVOp)))
4297 if (ShouldXformToMOVHLPS(SVOp) ||
4298 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4299 return CommuteVectorShuffle(SVOp, DAG);
4302 // No better options. Use a vshl / vsrl.
4303 EVT EltVT = VT.getVectorElementType();
4304 ShAmt *= EltVT.getSizeInBits();
4305 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4308 bool Commuted = false;
4309 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4310 // 1,1,1,1 -> v8i16 though.
4311 V1IsSplat = isSplatVector(V1.getNode());
4312 V2IsSplat = isSplatVector(V2.getNode());
4314 // Canonicalize the splat or undef, if present, to be on the RHS.
4315 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4316 Op = CommuteVectorShuffle(SVOp, DAG);
4317 SVOp = cast<ShuffleVectorSDNode>(Op);
4318 V1 = SVOp->getOperand(0);
4319 V2 = SVOp->getOperand(1);
4320 std::swap(V1IsSplat, V2IsSplat);
4321 std::swap(V1IsUndef, V2IsUndef);
4325 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4326 // Shuffling low element of v1 into undef, just return v1.
4329 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4330 // the instruction selector will not match, so get a canonical MOVL with
4331 // swapped operands to undo the commute.
4332 return getMOVL(DAG, dl, VT, V2, V1);
4335 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4336 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4337 X86::isUNPCKLMask(SVOp) ||
4338 X86::isUNPCKHMask(SVOp))
4342 // Normalize mask so all entries that point to V2 points to its first
4343 // element then try to match unpck{h|l} again. If match, return a
4344 // new vector_shuffle with the corrected mask.
4345 SDValue NewMask = NormalizeMask(SVOp, DAG);
4346 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4347 if (NSVOp != SVOp) {
4348 if (X86::isUNPCKLMask(NSVOp, true)) {
4350 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4357 // Commute is back and try unpck* again.
4358 // FIXME: this seems wrong.
4359 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4360 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4361 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4362 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4363 X86::isUNPCKLMask(NewSVOp) ||
4364 X86::isUNPCKHMask(NewSVOp))
4368 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4370 // Normalize the node to match x86 shuffle ops if needed
4371 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4372 return CommuteVectorShuffle(SVOp, DAG);
4374 // Check for legal shuffle and return?
4375 SmallVector<int, 16> PermMask;
4376 SVOp->getMask(PermMask);
4377 if (isShuffleMaskLegal(PermMask, VT))
4380 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4381 if (VT == MVT::v8i16) {
4382 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4383 if (NewOp.getNode())
4387 if (VT == MVT::v16i8) {
4388 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4389 if (NewOp.getNode())
4393 // Handle all 4 wide cases with a number of shuffles except for MMX.
4394 if (NumElems == 4 && !isMMX)
4395 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4401 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4402 SelectionDAG &DAG) {
4403 EVT VT = Op.getValueType();
4404 DebugLoc dl = Op.getDebugLoc();
4405 if (VT.getSizeInBits() == 8) {
4406 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4407 Op.getOperand(0), Op.getOperand(1));
4408 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4409 DAG.getValueType(VT));
4410 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4411 } else if (VT.getSizeInBits() == 16) {
4412 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4413 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4415 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4416 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4417 DAG.getNode(ISD::BIT_CONVERT, dl,
4421 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4422 Op.getOperand(0), Op.getOperand(1));
4423 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4424 DAG.getValueType(VT));
4425 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4426 } else if (VT == MVT::f32) {
4427 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4428 // the result back to FR32 register. It's only worth matching if the
4429 // result has a single use which is a store or a bitcast to i32. And in
4430 // the case of a store, it's not worth it if the index is a constant 0,
4431 // because a MOVSSmr can be used instead, which is smaller and faster.
4432 if (!Op.hasOneUse())
4434 SDNode *User = *Op.getNode()->use_begin();
4435 if ((User->getOpcode() != ISD::STORE ||
4436 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4437 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4438 (User->getOpcode() != ISD::BIT_CONVERT ||
4439 User->getValueType(0) != MVT::i32))
4441 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4442 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4445 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4446 } else if (VT == MVT::i32) {
4447 // ExtractPS works with constant index.
4448 if (isa<ConstantSDNode>(Op.getOperand(1)))
4456 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4457 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4460 if (Subtarget->hasSSE41()) {
4461 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4466 EVT VT = Op.getValueType();
4467 DebugLoc dl = Op.getDebugLoc();
4468 // TODO: handle v16i8.
4469 if (VT.getSizeInBits() == 16) {
4470 SDValue Vec = Op.getOperand(0);
4471 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4473 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4474 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4475 DAG.getNode(ISD::BIT_CONVERT, dl,
4478 // Transform it so it match pextrw which produces a 32-bit result.
4479 EVT EltVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
4480 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
4481 Op.getOperand(0), Op.getOperand(1));
4482 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
4483 DAG.getValueType(VT));
4484 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4485 } else if (VT.getSizeInBits() == 32) {
4486 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4490 // SHUFPS the element to the lowest double word, then movss.
4491 int Mask[4] = { Idx, -1, -1, -1 };
4492 EVT VVT = Op.getOperand(0).getValueType();
4493 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4494 DAG.getUNDEF(VVT), Mask);
4495 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4496 DAG.getIntPtrConstant(0));
4497 } else if (VT.getSizeInBits() == 64) {
4498 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4499 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4500 // to match extract_elt for f64.
4501 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4505 // UNPCKHPD the element to the lowest double word, then movsd.
4506 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4507 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4508 int Mask[2] = { 1, -1 };
4509 EVT VVT = Op.getOperand(0).getValueType();
4510 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4511 DAG.getUNDEF(VVT), Mask);
4512 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4513 DAG.getIntPtrConstant(0));
4520 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4521 EVT VT = Op.getValueType();
4522 EVT EltVT = VT.getVectorElementType();
4523 DebugLoc dl = Op.getDebugLoc();
4525 SDValue N0 = Op.getOperand(0);
4526 SDValue N1 = Op.getOperand(1);
4527 SDValue N2 = Op.getOperand(2);
4529 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
4530 isa<ConstantSDNode>(N2)) {
4531 unsigned Opc = (EltVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4533 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4535 if (N1.getValueType() != MVT::i32)
4536 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4537 if (N2.getValueType() != MVT::i32)
4538 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4539 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4540 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4541 // Bits [7:6] of the constant are the source select. This will always be
4542 // zero here. The DAG Combiner may combine an extract_elt index into these
4543 // bits. For example (insert (extract, 3), 2) could be matched by putting
4544 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4545 // Bits [5:4] of the constant are the destination select. This is the
4546 // value of the incoming immediate.
4547 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4548 // combine either bitwise AND or insert of float 0.0 to set these bits.
4549 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4550 // Create this as a scalar to vector..
4551 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4552 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4553 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4554 // PINSR* works with constant index.
4561 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4562 EVT VT = Op.getValueType();
4563 EVT EltVT = VT.getVectorElementType();
4565 if (Subtarget->hasSSE41())
4566 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4568 if (EltVT == MVT::i8)
4571 DebugLoc dl = Op.getDebugLoc();
4572 SDValue N0 = Op.getOperand(0);
4573 SDValue N1 = Op.getOperand(1);
4574 SDValue N2 = Op.getOperand(2);
4576 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4577 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4578 // as its second argument.
4579 if (N1.getValueType() != MVT::i32)
4580 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4581 if (N2.getValueType() != MVT::i32)
4582 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4583 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4589 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4590 DebugLoc dl = Op.getDebugLoc();
4591 if (Op.getValueType() == MVT::v2f32)
4592 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4593 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4594 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4595 Op.getOperand(0))));
4597 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4598 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4600 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4601 EVT VT = MVT::v2i32;
4602 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4609 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4610 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4613 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4614 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4615 // one of the above mentioned nodes. It has to be wrapped because otherwise
4616 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4617 // be used to form addressing mode. These wrapped nodes will be selected
4620 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4621 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4623 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4625 unsigned char OpFlag = 0;
4626 unsigned WrapperKind = X86ISD::Wrapper;
4627 CodeModel::Model M = getTargetMachine().getCodeModel();
4629 if (Subtarget->isPICStyleRIPRel() &&
4630 (M == CodeModel::Small || M == CodeModel::Kernel))
4631 WrapperKind = X86ISD::WrapperRIP;
4632 else if (Subtarget->isPICStyleGOT())
4633 OpFlag = X86II::MO_GOTOFF;
4634 else if (Subtarget->isPICStyleStubPIC())
4635 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4637 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4639 CP->getOffset(), OpFlag);
4640 DebugLoc DL = CP->getDebugLoc();
4641 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4642 // With PIC, the address is actually $g + Offset.
4644 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4645 DAG.getNode(X86ISD::GlobalBaseReg,
4646 DebugLoc::getUnknownLoc(), getPointerTy()),
4653 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4654 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4656 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4658 unsigned char OpFlag = 0;
4659 unsigned WrapperKind = X86ISD::Wrapper;
4660 CodeModel::Model M = getTargetMachine().getCodeModel();
4662 if (Subtarget->isPICStyleRIPRel() &&
4663 (M == CodeModel::Small || M == CodeModel::Kernel))
4664 WrapperKind = X86ISD::WrapperRIP;
4665 else if (Subtarget->isPICStyleGOT())
4666 OpFlag = X86II::MO_GOTOFF;
4667 else if (Subtarget->isPICStyleStubPIC())
4668 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4670 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4672 DebugLoc DL = JT->getDebugLoc();
4673 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4675 // With PIC, the address is actually $g + Offset.
4677 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4678 DAG.getNode(X86ISD::GlobalBaseReg,
4679 DebugLoc::getUnknownLoc(), getPointerTy()),
4687 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4688 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4690 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4692 unsigned char OpFlag = 0;
4693 unsigned WrapperKind = X86ISD::Wrapper;
4694 CodeModel::Model M = getTargetMachine().getCodeModel();
4696 if (Subtarget->isPICStyleRIPRel() &&
4697 (M == CodeModel::Small || M == CodeModel::Kernel))
4698 WrapperKind = X86ISD::WrapperRIP;
4699 else if (Subtarget->isPICStyleGOT())
4700 OpFlag = X86II::MO_GOTOFF;
4701 else if (Subtarget->isPICStyleStubPIC())
4702 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4704 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4706 DebugLoc DL = Op.getDebugLoc();
4707 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4710 // With PIC, the address is actually $g + Offset.
4711 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4712 !Subtarget->is64Bit()) {
4713 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4714 DAG.getNode(X86ISD::GlobalBaseReg,
4715 DebugLoc::getUnknownLoc(),
4724 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
4725 // Create the TargetBlockAddressAddress node.
4726 unsigned char OpFlags =
4727 Subtarget->ClassifyBlockAddressReference();
4728 CodeModel::Model M = getTargetMachine().getCodeModel();
4729 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
4730 DebugLoc dl = Op.getDebugLoc();
4731 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
4732 /*isTarget=*/true, OpFlags);
4734 if (Subtarget->isPICStyleRIPRel() &&
4735 (M == CodeModel::Small || M == CodeModel::Kernel))
4736 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4738 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4740 // With PIC, the address is actually $g + Offset.
4741 if (isGlobalRelativeToPICBase(OpFlags)) {
4742 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4743 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4751 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4753 SelectionDAG &DAG) const {
4754 // Create the TargetGlobalAddress node, folding in the constant
4755 // offset if it is legal.
4756 unsigned char OpFlags =
4757 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4758 CodeModel::Model M = getTargetMachine().getCodeModel();
4760 if (OpFlags == X86II::MO_NO_FLAG &&
4761 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4762 // A direct static reference to a global.
4763 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4766 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4769 if (Subtarget->isPICStyleRIPRel() &&
4770 (M == CodeModel::Small || M == CodeModel::Kernel))
4771 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4773 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4775 // With PIC, the address is actually $g + Offset.
4776 if (isGlobalRelativeToPICBase(OpFlags)) {
4777 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4778 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4782 // For globals that require a load from a stub to get the address, emit the
4784 if (isGlobalStubReference(OpFlags))
4785 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4786 PseudoSourceValue::getGOT(), 0);
4788 // If there was a non-zero offset that we didn't fold, create an explicit
4791 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4792 DAG.getConstant(Offset, getPointerTy()));
4798 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4799 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4800 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4801 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4805 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4806 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4807 unsigned char OperandFlags) {
4808 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4809 DebugLoc dl = GA->getDebugLoc();
4810 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4811 GA->getValueType(0),
4815 SDValue Ops[] = { Chain, TGA, *InFlag };
4816 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4818 SDValue Ops[] = { Chain, TGA };
4819 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4821 SDValue Flag = Chain.getValue(1);
4822 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4825 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4827 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4830 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4831 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4832 DAG.getNode(X86ISD::GlobalBaseReg,
4833 DebugLoc::getUnknownLoc(),
4835 InFlag = Chain.getValue(1);
4837 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4840 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4842 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4844 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4845 X86::RAX, X86II::MO_TLSGD);
4848 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4849 // "local exec" model.
4850 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4851 const EVT PtrVT, TLSModel::Model model,
4853 DebugLoc dl = GA->getDebugLoc();
4854 // Get the Thread Pointer
4855 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4856 DebugLoc::getUnknownLoc(), PtrVT,
4857 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4860 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4863 unsigned char OperandFlags = 0;
4864 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4866 unsigned WrapperKind = X86ISD::Wrapper;
4867 if (model == TLSModel::LocalExec) {
4868 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4869 } else if (is64Bit) {
4870 assert(model == TLSModel::InitialExec);
4871 OperandFlags = X86II::MO_GOTTPOFF;
4872 WrapperKind = X86ISD::WrapperRIP;
4874 assert(model == TLSModel::InitialExec);
4875 OperandFlags = X86II::MO_INDNTPOFF;
4878 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4880 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4881 GA->getOffset(), OperandFlags);
4882 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4884 if (model == TLSModel::InitialExec)
4885 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4886 PseudoSourceValue::getGOT(), 0);
4888 // The address of the thread local variable is the add of the thread
4889 // pointer with the offset of the variable.
4890 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4894 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4895 // TODO: implement the "local dynamic" model
4896 // TODO: implement the "initial exec"model for pic executables
4897 assert(Subtarget->isTargetELF() &&
4898 "TLS not implemented for non-ELF targets");
4899 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4900 const GlobalValue *GV = GA->getGlobal();
4902 // If GV is an alias then use the aliasee for determining
4903 // thread-localness.
4904 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4905 GV = GA->resolveAliasedGlobal(false);
4907 TLSModel::Model model = getTLSModel(GV,
4908 getTargetMachine().getRelocationModel());
4911 case TLSModel::GeneralDynamic:
4912 case TLSModel::LocalDynamic: // not implemented
4913 if (Subtarget->is64Bit())
4914 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4915 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4917 case TLSModel::InitialExec:
4918 case TLSModel::LocalExec:
4919 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4920 Subtarget->is64Bit());
4923 llvm_unreachable("Unreachable");
4928 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4929 /// take a 2 x i32 value to shift plus a shift amount.
4930 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4931 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4932 EVT VT = Op.getValueType();
4933 unsigned VTBits = VT.getSizeInBits();
4934 DebugLoc dl = Op.getDebugLoc();
4935 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4936 SDValue ShOpLo = Op.getOperand(0);
4937 SDValue ShOpHi = Op.getOperand(1);
4938 SDValue ShAmt = Op.getOperand(2);
4939 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4940 DAG.getConstant(VTBits - 1, MVT::i8))
4941 : DAG.getConstant(0, VT);
4944 if (Op.getOpcode() == ISD::SHL_PARTS) {
4945 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4946 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4948 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4949 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4952 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4953 DAG.getConstant(VTBits, MVT::i8));
4954 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4955 AndNode, DAG.getConstant(0, MVT::i8));
4958 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4959 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4960 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4962 if (Op.getOpcode() == ISD::SHL_PARTS) {
4963 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4964 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4966 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4967 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4970 SDValue Ops[2] = { Lo, Hi };
4971 return DAG.getMergeValues(Ops, 2, dl);
4974 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4975 EVT SrcVT = Op.getOperand(0).getValueType();
4977 if (SrcVT.isVector()) {
4978 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4984 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4985 "Unknown SINT_TO_FP to lower!");
4987 // These are really Legal; return the operand so the caller accepts it as
4989 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4991 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4992 Subtarget->is64Bit()) {
4996 DebugLoc dl = Op.getDebugLoc();
4997 unsigned Size = SrcVT.getSizeInBits()/8;
4998 MachineFunction &MF = DAG.getMachineFunction();
4999 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
5000 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5001 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5003 PseudoSourceValue::getFixedStack(SSFI), 0);
5004 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
5007 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
5009 SelectionDAG &DAG) {
5011 DebugLoc dl = Op.getDebugLoc();
5013 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
5015 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
5017 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
5018 SmallVector<SDValue, 8> Ops;
5019 Ops.push_back(Chain);
5020 Ops.push_back(StackSlot);
5021 Ops.push_back(DAG.getValueType(SrcVT));
5022 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
5023 Tys, &Ops[0], Ops.size());
5026 Chain = Result.getValue(1);
5027 SDValue InFlag = Result.getValue(2);
5029 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
5030 // shouldn't be necessary except that RFP cannot be live across
5031 // multiple blocks. When stackifier is fixed, they can be uncoupled.
5032 MachineFunction &MF = DAG.getMachineFunction();
5033 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5034 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5035 Tys = DAG.getVTList(MVT::Other);
5036 SmallVector<SDValue, 8> Ops;
5037 Ops.push_back(Chain);
5038 Ops.push_back(Result);
5039 Ops.push_back(StackSlot);
5040 Ops.push_back(DAG.getValueType(Op.getValueType()));
5041 Ops.push_back(InFlag);
5042 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
5043 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
5044 PseudoSourceValue::getFixedStack(SSFI), 0);
5050 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
5051 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
5052 // This algorithm is not obvious. Here it is in C code, more or less:
5054 double uint64_to_double( uint32_t hi, uint32_t lo ) {
5055 static const __m128i exp = { 0x4330000045300000ULL, 0 };
5056 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
5058 // Copy ints to xmm registers.
5059 __m128i xh = _mm_cvtsi32_si128( hi );
5060 __m128i xl = _mm_cvtsi32_si128( lo );
5062 // Combine into low half of a single xmm register.
5063 __m128i x = _mm_unpacklo_epi32( xh, xl );
5067 // Merge in appropriate exponents to give the integer bits the right
5069 x = _mm_unpacklo_epi32( x, exp );
5071 // Subtract away the biases to deal with the IEEE-754 double precision
5073 d = _mm_sub_pd( (__m128d) x, bias );
5075 // All conversions up to here are exact. The correctly rounded result is
5076 // calculated using the current rounding mode using the following
5078 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
5079 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
5080 // store doesn't really need to be here (except
5081 // maybe to zero the other double)
5086 DebugLoc dl = Op.getDebugLoc();
5087 LLVMContext *Context = DAG.getContext();
5089 // Build some magic constants.
5090 std::vector<Constant*> CV0;
5091 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
5092 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
5093 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5094 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
5095 Constant *C0 = ConstantVector::get(CV0);
5096 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
5098 std::vector<Constant*> CV1;
5100 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
5102 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
5103 Constant *C1 = ConstantVector::get(CV1);
5104 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
5106 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5107 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5109 DAG.getIntPtrConstant(1)));
5110 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5111 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5113 DAG.getIntPtrConstant(0)));
5114 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
5115 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
5116 PseudoSourceValue::getConstantPool(), 0,
5118 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
5119 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
5120 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
5121 PseudoSourceValue::getConstantPool(), 0,
5123 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
5125 // Add the halves; easiest way is to swap them into another reg first.
5126 int ShufMask[2] = { 1, -1 };
5127 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
5128 DAG.getUNDEF(MVT::v2f64), ShufMask);
5129 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
5130 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
5131 DAG.getIntPtrConstant(0));
5134 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
5135 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
5136 DebugLoc dl = Op.getDebugLoc();
5137 // FP constant to bias correct the final result.
5138 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5141 // Load the 32-bit value into an XMM register.
5142 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5143 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5145 DAG.getIntPtrConstant(0)));
5147 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5148 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5149 DAG.getIntPtrConstant(0));
5151 // Or the load with the bias.
5152 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5153 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5154 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5156 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5157 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5158 MVT::v2f64, Bias)));
5159 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5160 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5161 DAG.getIntPtrConstant(0));
5163 // Subtract the bias.
5164 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5166 // Handle final rounding.
5167 EVT DestVT = Op.getValueType();
5169 if (DestVT.bitsLT(MVT::f64)) {
5170 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5171 DAG.getIntPtrConstant(0));
5172 } else if (DestVT.bitsGT(MVT::f64)) {
5173 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5176 // Handle final rounding.
5180 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5181 SDValue N0 = Op.getOperand(0);
5182 DebugLoc dl = Op.getDebugLoc();
5184 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5185 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5186 // the optimization here.
5187 if (DAG.SignBitIsZero(N0))
5188 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5190 EVT SrcVT = N0.getValueType();
5191 if (SrcVT == MVT::i64) {
5192 // We only handle SSE2 f64 target here; caller can expand the rest.
5193 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5196 return LowerUINT_TO_FP_i64(Op, DAG);
5197 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5198 return LowerUINT_TO_FP_i32(Op, DAG);
5201 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5203 // Make a 64-bit buffer, and use it to build an FILD.
5204 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5205 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5206 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5207 getPointerTy(), StackSlot, WordOff);
5208 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5209 StackSlot, NULL, 0);
5210 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5211 OffsetSlot, NULL, 0);
5212 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5215 std::pair<SDValue,SDValue> X86TargetLowering::
5216 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5217 DebugLoc dl = Op.getDebugLoc();
5219 EVT DstTy = Op.getValueType();
5222 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5226 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5227 DstTy.getSimpleVT() >= MVT::i16 &&
5228 "Unknown FP_TO_SINT to lower!");
5230 // These are really Legal.
5231 if (DstTy == MVT::i32 &&
5232 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5233 return std::make_pair(SDValue(), SDValue());
5234 if (Subtarget->is64Bit() &&
5235 DstTy == MVT::i64 &&
5236 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5237 return std::make_pair(SDValue(), SDValue());
5239 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5241 MachineFunction &MF = DAG.getMachineFunction();
5242 unsigned MemSize = DstTy.getSizeInBits()/8;
5243 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5244 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5247 switch (DstTy.getSimpleVT().SimpleTy) {
5248 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5249 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5250 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5251 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5254 SDValue Chain = DAG.getEntryNode();
5255 SDValue Value = Op.getOperand(0);
5256 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5257 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5258 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5259 PseudoSourceValue::getFixedStack(SSFI), 0);
5260 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5262 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5264 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5265 Chain = Value.getValue(1);
5266 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
5267 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5270 // Build the FP_TO_INT*_IN_MEM
5271 SDValue Ops[] = { Chain, Value, StackSlot };
5272 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5274 return std::make_pair(FIST, StackSlot);
5277 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5278 if (Op.getValueType().isVector()) {
5279 if (Op.getValueType() == MVT::v2i32 &&
5280 Op.getOperand(0).getValueType() == MVT::v2f64) {
5286 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5287 SDValue FIST = Vals.first, StackSlot = Vals.second;
5288 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5289 if (FIST.getNode() == 0) return Op;
5292 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5293 FIST, StackSlot, NULL, 0);
5296 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5297 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5298 SDValue FIST = Vals.first, StackSlot = Vals.second;
5299 assert(FIST.getNode() && "Unexpected failure");
5302 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5303 FIST, StackSlot, NULL, 0);
5306 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5307 LLVMContext *Context = DAG.getContext();
5308 DebugLoc dl = Op.getDebugLoc();
5309 EVT VT = Op.getValueType();
5312 EltVT = VT.getVectorElementType();
5313 std::vector<Constant*> CV;
5314 if (EltVT == MVT::f64) {
5315 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5319 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5325 Constant *C = ConstantVector::get(CV);
5326 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5327 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5328 PseudoSourceValue::getConstantPool(), 0,
5330 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5333 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5334 LLVMContext *Context = DAG.getContext();
5335 DebugLoc dl = Op.getDebugLoc();
5336 EVT VT = Op.getValueType();
5339 EltVT = VT.getVectorElementType();
5340 std::vector<Constant*> CV;
5341 if (EltVT == MVT::f64) {
5342 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5346 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5352 Constant *C = ConstantVector::get(CV);
5353 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5354 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5355 PseudoSourceValue::getConstantPool(), 0,
5357 if (VT.isVector()) {
5358 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5359 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5360 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5362 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5364 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5368 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5369 LLVMContext *Context = DAG.getContext();
5370 SDValue Op0 = Op.getOperand(0);
5371 SDValue Op1 = Op.getOperand(1);
5372 DebugLoc dl = Op.getDebugLoc();
5373 EVT VT = Op.getValueType();
5374 EVT SrcVT = Op1.getValueType();
5376 // If second operand is smaller, extend it first.
5377 if (SrcVT.bitsLT(VT)) {
5378 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5381 // And if it is bigger, shrink it first.
5382 if (SrcVT.bitsGT(VT)) {
5383 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5387 // At this point the operands and the result should have the same
5388 // type, and that won't be f80 since that is not custom lowered.
5390 // First get the sign bit of second operand.
5391 std::vector<Constant*> CV;
5392 if (SrcVT == MVT::f64) {
5393 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5394 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5396 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5397 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5398 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5399 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5401 Constant *C = ConstantVector::get(CV);
5402 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5403 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5404 PseudoSourceValue::getConstantPool(), 0,
5406 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5408 // Shift sign bit right or left if the two operands have different types.
5409 if (SrcVT.bitsGT(VT)) {
5410 // Op0 is MVT::f32, Op1 is MVT::f64.
5411 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5412 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5413 DAG.getConstant(32, MVT::i32));
5414 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5415 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5416 DAG.getIntPtrConstant(0));
5419 // Clear first operand sign bit.
5421 if (VT == MVT::f64) {
5422 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5423 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5425 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5426 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5427 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5428 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5430 C = ConstantVector::get(CV);
5431 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5432 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5433 PseudoSourceValue::getConstantPool(), 0,
5435 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5437 // Or the value with the sign bit.
5438 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5441 /// Emit nodes that will be selected as "test Op0,Op0", or something
5443 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5444 SelectionDAG &DAG) {
5445 DebugLoc dl = Op.getDebugLoc();
5447 // CF and OF aren't always set the way we want. Determine which
5448 // of these we need.
5449 bool NeedCF = false;
5450 bool NeedOF = false;
5452 case X86::COND_A: case X86::COND_AE:
5453 case X86::COND_B: case X86::COND_BE:
5456 case X86::COND_G: case X86::COND_GE:
5457 case X86::COND_L: case X86::COND_LE:
5458 case X86::COND_O: case X86::COND_NO:
5464 // See if we can use the EFLAGS value from the operand instead of
5465 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5466 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5467 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5468 unsigned Opcode = 0;
5469 unsigned NumOperands = 0;
5470 switch (Op.getNode()->getOpcode()) {
5472 // Due to an isel shortcoming, be conservative if this add is likely to
5473 // be selected as part of a load-modify-store instruction. When the root
5474 // node in a match is a store, isel doesn't know how to remap non-chain
5475 // non-flag uses of other nodes in the match, such as the ADD in this
5476 // case. This leads to the ADD being left around and reselected, with
5477 // the result being two adds in the output.
5478 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5479 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5480 if (UI->getOpcode() == ISD::STORE)
5482 if (ConstantSDNode *C =
5483 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5484 // An add of one will be selected as an INC.
5485 if (C->getAPIntValue() == 1) {
5486 Opcode = X86ISD::INC;
5490 // An add of negative one (subtract of one) will be selected as a DEC.
5491 if (C->getAPIntValue().isAllOnesValue()) {
5492 Opcode = X86ISD::DEC;
5497 // Otherwise use a regular EFLAGS-setting add.
5498 Opcode = X86ISD::ADD;
5502 // If the primary and result isn't used, don't bother using X86ISD::AND,
5503 // because a TEST instruction will be better.
5504 bool NonFlagUse = false;
5505 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5506 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5507 if (UI->getOpcode() != ISD::BRCOND &&
5508 UI->getOpcode() != ISD::SELECT &&
5509 UI->getOpcode() != ISD::SETCC) {
5520 // Due to the ISEL shortcoming noted above, be conservative if this op is
5521 // likely to be selected as part of a load-modify-store instruction.
5522 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5523 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5524 if (UI->getOpcode() == ISD::STORE)
5526 // Otherwise use a regular EFLAGS-setting instruction.
5527 switch (Op.getNode()->getOpcode()) {
5528 case ISD::SUB: Opcode = X86ISD::SUB; break;
5529 case ISD::OR: Opcode = X86ISD::OR; break;
5530 case ISD::XOR: Opcode = X86ISD::XOR; break;
5531 case ISD::AND: Opcode = X86ISD::AND; break;
5532 default: llvm_unreachable("unexpected operator!");
5543 return SDValue(Op.getNode(), 1);
5549 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5550 SmallVector<SDValue, 4> Ops;
5551 for (unsigned i = 0; i != NumOperands; ++i)
5552 Ops.push_back(Op.getOperand(i));
5553 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5554 DAG.ReplaceAllUsesWith(Op, New);
5555 return SDValue(New.getNode(), 1);
5559 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5560 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5561 DAG.getConstant(0, Op.getValueType()));
5564 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5566 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5567 SelectionDAG &DAG) {
5568 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5569 if (C->getAPIntValue() == 0)
5570 return EmitTest(Op0, X86CC, DAG);
5572 DebugLoc dl = Op0.getDebugLoc();
5573 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5576 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5577 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5578 SDValue Op0 = Op.getOperand(0);
5579 SDValue Op1 = Op.getOperand(1);
5580 DebugLoc dl = Op.getDebugLoc();
5581 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5583 // Lower (X & (1 << N)) == 0 to BT(X, N).
5584 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5585 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5586 if (Op0.getOpcode() == ISD::AND &&
5588 Op1.getOpcode() == ISD::Constant &&
5589 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5590 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5592 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5593 if (ConstantSDNode *Op010C =
5594 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5595 if (Op010C->getZExtValue() == 1) {
5596 LHS = Op0.getOperand(0);
5597 RHS = Op0.getOperand(1).getOperand(1);
5599 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5600 if (ConstantSDNode *Op000C =
5601 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5602 if (Op000C->getZExtValue() == 1) {
5603 LHS = Op0.getOperand(1);
5604 RHS = Op0.getOperand(0).getOperand(1);
5606 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5607 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5608 SDValue AndLHS = Op0.getOperand(0);
5609 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5610 LHS = AndLHS.getOperand(0);
5611 RHS = AndLHS.getOperand(1);
5615 if (LHS.getNode()) {
5616 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5617 // instruction. Since the shift amount is in-range-or-undefined, we know
5618 // that doing a bittest on the i16 value is ok. We extend to i32 because
5619 // the encoding for the i16 version is larger than the i32 version.
5620 if (LHS.getValueType() == MVT::i8)
5621 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5623 // If the operand types disagree, extend the shift amount to match. Since
5624 // BT ignores high bits (like shifts) we can use anyextend.
5625 if (LHS.getValueType() != RHS.getValueType())
5626 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5628 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5629 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5630 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5631 DAG.getConstant(Cond, MVT::i8), BT);
5635 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5636 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5637 if (X86CC == X86::COND_INVALID)
5640 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5641 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5642 DAG.getConstant(X86CC, MVT::i8), Cond);
5645 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5647 SDValue Op0 = Op.getOperand(0);
5648 SDValue Op1 = Op.getOperand(1);
5649 SDValue CC = Op.getOperand(2);
5650 EVT VT = Op.getValueType();
5651 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5652 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5653 DebugLoc dl = Op.getDebugLoc();
5657 EVT VT0 = Op0.getValueType();
5658 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5659 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5662 switch (SetCCOpcode) {
5665 case ISD::SETEQ: SSECC = 0; break;
5667 case ISD::SETGT: Swap = true; // Fallthrough
5669 case ISD::SETOLT: SSECC = 1; break;
5671 case ISD::SETGE: Swap = true; // Fallthrough
5673 case ISD::SETOLE: SSECC = 2; break;
5674 case ISD::SETUO: SSECC = 3; break;
5676 case ISD::SETNE: SSECC = 4; break;
5677 case ISD::SETULE: Swap = true;
5678 case ISD::SETUGE: SSECC = 5; break;
5679 case ISD::SETULT: Swap = true;
5680 case ISD::SETUGT: SSECC = 6; break;
5681 case ISD::SETO: SSECC = 7; break;
5684 std::swap(Op0, Op1);
5686 // In the two special cases we can't handle, emit two comparisons.
5688 if (SetCCOpcode == ISD::SETUEQ) {
5690 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5691 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5692 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5694 else if (SetCCOpcode == ISD::SETONE) {
5696 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5697 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5698 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5700 llvm_unreachable("Illegal FP comparison");
5702 // Handle all other FP comparisons here.
5703 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5706 // We are handling one of the integer comparisons here. Since SSE only has
5707 // GT and EQ comparisons for integer, swapping operands and multiple
5708 // operations may be required for some comparisons.
5709 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5710 bool Swap = false, Invert = false, FlipSigns = false;
5712 switch (VT.getSimpleVT().SimpleTy) {
5715 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5717 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5719 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5720 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5723 switch (SetCCOpcode) {
5725 case ISD::SETNE: Invert = true;
5726 case ISD::SETEQ: Opc = EQOpc; break;
5727 case ISD::SETLT: Swap = true;
5728 case ISD::SETGT: Opc = GTOpc; break;
5729 case ISD::SETGE: Swap = true;
5730 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5731 case ISD::SETULT: Swap = true;
5732 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5733 case ISD::SETUGE: Swap = true;
5734 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5737 std::swap(Op0, Op1);
5739 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5740 // bits of the inputs before performing those operations.
5742 EVT EltVT = VT.getVectorElementType();
5743 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5745 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5746 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5748 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5749 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5752 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5754 // If the logical-not of the result is required, perform that now.
5756 Result = DAG.getNOT(dl, Result, VT);
5761 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5762 static bool isX86LogicalCmp(SDValue Op) {
5763 unsigned Opc = Op.getNode()->getOpcode();
5764 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5766 if (Op.getResNo() == 1 &&
5767 (Opc == X86ISD::ADD ||
5768 Opc == X86ISD::SUB ||
5769 Opc == X86ISD::SMUL ||
5770 Opc == X86ISD::UMUL ||
5771 Opc == X86ISD::INC ||
5772 Opc == X86ISD::DEC ||
5773 Opc == X86ISD::OR ||
5774 Opc == X86ISD::XOR ||
5775 Opc == X86ISD::AND))
5781 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5782 bool addTest = true;
5783 SDValue Cond = Op.getOperand(0);
5784 DebugLoc dl = Op.getDebugLoc();
5787 if (Cond.getOpcode() == ISD::SETCC) {
5788 SDValue NewCond = LowerSETCC(Cond, DAG);
5789 if (NewCond.getNode())
5793 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5794 // setting operand in place of the X86ISD::SETCC.
5795 if (Cond.getOpcode() == X86ISD::SETCC) {
5796 CC = Cond.getOperand(0);
5798 SDValue Cmp = Cond.getOperand(1);
5799 unsigned Opc = Cmp.getOpcode();
5800 EVT VT = Op.getValueType();
5802 bool IllegalFPCMov = false;
5803 if (VT.isFloatingPoint() && !VT.isVector() &&
5804 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5805 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5807 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5808 Opc == X86ISD::BT) { // FIXME
5815 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5816 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5819 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5820 SmallVector<SDValue, 4> Ops;
5821 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5822 // condition is true.
5823 Ops.push_back(Op.getOperand(2));
5824 Ops.push_back(Op.getOperand(1));
5826 Ops.push_back(Cond);
5827 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5830 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5831 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5832 // from the AND / OR.
5833 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5834 Opc = Op.getOpcode();
5835 if (Opc != ISD::OR && Opc != ISD::AND)
5837 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5838 Op.getOperand(0).hasOneUse() &&
5839 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5840 Op.getOperand(1).hasOneUse());
5843 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5844 // 1 and that the SETCC node has a single use.
5845 static bool isXor1OfSetCC(SDValue Op) {
5846 if (Op.getOpcode() != ISD::XOR)
5848 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5849 if (N1C && N1C->getAPIntValue() == 1) {
5850 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5851 Op.getOperand(0).hasOneUse();
5856 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5857 bool addTest = true;
5858 SDValue Chain = Op.getOperand(0);
5859 SDValue Cond = Op.getOperand(1);
5860 SDValue Dest = Op.getOperand(2);
5861 DebugLoc dl = Op.getDebugLoc();
5864 if (Cond.getOpcode() == ISD::SETCC) {
5865 SDValue NewCond = LowerSETCC(Cond, DAG);
5866 if (NewCond.getNode())
5870 // FIXME: LowerXALUO doesn't handle these!!
5871 else if (Cond.getOpcode() == X86ISD::ADD ||
5872 Cond.getOpcode() == X86ISD::SUB ||
5873 Cond.getOpcode() == X86ISD::SMUL ||
5874 Cond.getOpcode() == X86ISD::UMUL)
5875 Cond = LowerXALUO(Cond, DAG);
5878 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5879 // setting operand in place of the X86ISD::SETCC.
5880 if (Cond.getOpcode() == X86ISD::SETCC) {
5881 CC = Cond.getOperand(0);
5883 SDValue Cmp = Cond.getOperand(1);
5884 unsigned Opc = Cmp.getOpcode();
5885 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5886 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5890 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5894 // These can only come from an arithmetic instruction with overflow,
5895 // e.g. SADDO, UADDO.
5896 Cond = Cond.getNode()->getOperand(1);
5903 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5904 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5905 if (CondOpc == ISD::OR) {
5906 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5907 // two branches instead of an explicit OR instruction with a
5909 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5910 isX86LogicalCmp(Cmp)) {
5911 CC = Cond.getOperand(0).getOperand(0);
5912 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5913 Chain, Dest, CC, Cmp);
5914 CC = Cond.getOperand(1).getOperand(0);
5918 } else { // ISD::AND
5919 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5920 // two branches instead of an explicit AND instruction with a
5921 // separate test. However, we only do this if this block doesn't
5922 // have a fall-through edge, because this requires an explicit
5923 // jmp when the condition is false.
5924 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5925 isX86LogicalCmp(Cmp) &&
5926 Op.getNode()->hasOneUse()) {
5927 X86::CondCode CCode =
5928 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5929 CCode = X86::GetOppositeBranchCondition(CCode);
5930 CC = DAG.getConstant(CCode, MVT::i8);
5931 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5932 // Look for an unconditional branch following this conditional branch.
5933 // We need this because we need to reverse the successors in order
5934 // to implement FCMP_OEQ.
5935 if (User.getOpcode() == ISD::BR) {
5936 SDValue FalseBB = User.getOperand(1);
5938 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5939 assert(NewBR == User);
5942 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5943 Chain, Dest, CC, Cmp);
5944 X86::CondCode CCode =
5945 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5946 CCode = X86::GetOppositeBranchCondition(CCode);
5947 CC = DAG.getConstant(CCode, MVT::i8);
5953 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5954 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5955 // It should be transformed during dag combiner except when the condition
5956 // is set by a arithmetics with overflow node.
5957 X86::CondCode CCode =
5958 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5959 CCode = X86::GetOppositeBranchCondition(CCode);
5960 CC = DAG.getConstant(CCode, MVT::i8);
5961 Cond = Cond.getOperand(0).getOperand(1);
5967 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5968 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5970 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5971 Chain, Dest, CC, Cond);
5975 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5976 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5977 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5978 // that the guard pages used by the OS virtual memory manager are allocated in
5979 // correct sequence.
5981 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5982 SelectionDAG &DAG) {
5983 assert(Subtarget->isTargetCygMing() &&
5984 "This should be used only on Cygwin/Mingw targets");
5985 DebugLoc dl = Op.getDebugLoc();
5988 SDValue Chain = Op.getOperand(0);
5989 SDValue Size = Op.getOperand(1);
5990 // FIXME: Ensure alignment here
5994 EVT IntPtr = getPointerTy();
5995 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5997 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5999 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
6000 Flag = Chain.getValue(1);
6002 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6003 SDValue Ops[] = { Chain,
6004 DAG.getTargetExternalSymbol("_alloca", IntPtr),
6005 DAG.getRegister(X86::EAX, IntPtr),
6006 DAG.getRegister(X86StackPtr, SPTy),
6008 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
6009 Flag = Chain.getValue(1);
6011 Chain = DAG.getCALLSEQ_END(Chain,
6012 DAG.getIntPtrConstant(0, true),
6013 DAG.getIntPtrConstant(0, true),
6016 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
6018 SDValue Ops1[2] = { Chain.getValue(0), Chain };
6019 return DAG.getMergeValues(Ops1, 2, dl);
6023 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
6025 SDValue Dst, SDValue Src,
6026 SDValue Size, unsigned Align,
6028 uint64_t DstSVOff) {
6029 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6031 // If not DWORD aligned or size is more than the threshold, call the library.
6032 // The libc version is likely to be faster for these cases. It can use the
6033 // address value and run time information about the CPU.
6034 if ((Align & 3) != 0 ||
6036 ConstantSize->getZExtValue() >
6037 getSubtarget()->getMaxInlineSizeThreshold()) {
6038 SDValue InFlag(0, 0);
6040 // Check to see if there is a specialized entry-point for memory zeroing.
6041 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
6043 if (const char *bzeroEntry = V &&
6044 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
6045 EVT IntPtr = getPointerTy();
6046 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
6047 TargetLowering::ArgListTy Args;
6048 TargetLowering::ArgListEntry Entry;
6050 Entry.Ty = IntPtrTy;
6051 Args.push_back(Entry);
6053 Args.push_back(Entry);
6054 std::pair<SDValue,SDValue> CallResult =
6055 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
6056 false, false, false, false,
6057 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
6058 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
6059 return CallResult.second;
6062 // Otherwise have the target-independent code call memset.
6066 uint64_t SizeVal = ConstantSize->getZExtValue();
6067 SDValue InFlag(0, 0);
6070 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
6071 unsigned BytesLeft = 0;
6072 bool TwoRepStos = false;
6075 uint64_t Val = ValC->getZExtValue() & 255;
6077 // If the value is a constant, then we can potentially use larger sets.
6078 switch (Align & 3) {
6079 case 2: // WORD aligned
6082 Val = (Val << 8) | Val;
6084 case 0: // DWORD aligned
6087 Val = (Val << 8) | Val;
6088 Val = (Val << 16) | Val;
6089 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
6092 Val = (Val << 32) | Val;
6095 default: // Byte aligned
6098 Count = DAG.getIntPtrConstant(SizeVal);
6102 if (AVT.bitsGT(MVT::i8)) {
6103 unsigned UBytes = AVT.getSizeInBits() / 8;
6104 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
6105 BytesLeft = SizeVal % UBytes;
6108 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
6110 InFlag = Chain.getValue(1);
6113 Count = DAG.getIntPtrConstant(SizeVal);
6114 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
6115 InFlag = Chain.getValue(1);
6118 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6121 InFlag = Chain.getValue(1);
6122 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6125 InFlag = Chain.getValue(1);
6127 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6128 SmallVector<SDValue, 8> Ops;
6129 Ops.push_back(Chain);
6130 Ops.push_back(DAG.getValueType(AVT));
6131 Ops.push_back(InFlag);
6132 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6135 InFlag = Chain.getValue(1);
6137 EVT CVT = Count.getValueType();
6138 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
6139 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
6140 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
6143 InFlag = Chain.getValue(1);
6144 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6146 Ops.push_back(Chain);
6147 Ops.push_back(DAG.getValueType(MVT::i8));
6148 Ops.push_back(InFlag);
6149 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
6150 } else if (BytesLeft) {
6151 // Handle the last 1 - 7 bytes.
6152 unsigned Offset = SizeVal - BytesLeft;
6153 EVT AddrVT = Dst.getValueType();
6154 EVT SizeVT = Size.getValueType();
6156 Chain = DAG.getMemset(Chain, dl,
6157 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
6158 DAG.getConstant(Offset, AddrVT)),
6160 DAG.getConstant(BytesLeft, SizeVT),
6161 Align, DstSV, DstSVOff + Offset);
6164 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
6169 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
6170 SDValue Chain, SDValue Dst, SDValue Src,
6171 SDValue Size, unsigned Align,
6173 const Value *DstSV, uint64_t DstSVOff,
6174 const Value *SrcSV, uint64_t SrcSVOff) {
6175 // This requires the copy size to be a constant, preferrably
6176 // within a subtarget-specific limit.
6177 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6180 uint64_t SizeVal = ConstantSize->getZExtValue();
6181 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6184 /// If not DWORD aligned, call the library.
6185 if ((Align & 3) != 0)
6190 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6193 unsigned UBytes = AVT.getSizeInBits() / 8;
6194 unsigned CountVal = SizeVal / UBytes;
6195 SDValue Count = DAG.getIntPtrConstant(CountVal);
6196 unsigned BytesLeft = SizeVal % UBytes;
6198 SDValue InFlag(0, 0);
6199 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6202 InFlag = Chain.getValue(1);
6203 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6206 InFlag = Chain.getValue(1);
6207 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6210 InFlag = Chain.getValue(1);
6212 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6213 SmallVector<SDValue, 8> Ops;
6214 Ops.push_back(Chain);
6215 Ops.push_back(DAG.getValueType(AVT));
6216 Ops.push_back(InFlag);
6217 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6219 SmallVector<SDValue, 4> Results;
6220 Results.push_back(RepMovs);
6222 // Handle the last 1 - 7 bytes.
6223 unsigned Offset = SizeVal - BytesLeft;
6224 EVT DstVT = Dst.getValueType();
6225 EVT SrcVT = Src.getValueType();
6226 EVT SizeVT = Size.getValueType();
6227 Results.push_back(DAG.getMemcpy(Chain, dl,
6228 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6229 DAG.getConstant(Offset, DstVT)),
6230 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6231 DAG.getConstant(Offset, SrcVT)),
6232 DAG.getConstant(BytesLeft, SizeVT),
6233 Align, AlwaysInline,
6234 DstSV, DstSVOff + Offset,
6235 SrcSV, SrcSVOff + Offset));
6238 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6239 &Results[0], Results.size());
6242 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6243 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6244 DebugLoc dl = Op.getDebugLoc();
6246 if (!Subtarget->is64Bit()) {
6247 // vastart just stores the address of the VarArgsFrameIndex slot into the
6248 // memory location argument.
6249 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6250 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6254 // gp_offset (0 - 6 * 8)
6255 // fp_offset (48 - 48 + 8 * 16)
6256 // overflow_arg_area (point to parameters coming in memory).
6258 SmallVector<SDValue, 8> MemOps;
6259 SDValue FIN = Op.getOperand(1);
6261 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6262 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6264 MemOps.push_back(Store);
6267 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6268 FIN, DAG.getIntPtrConstant(4));
6269 Store = DAG.getStore(Op.getOperand(0), dl,
6270 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6272 MemOps.push_back(Store);
6274 // Store ptr to overflow_arg_area
6275 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6276 FIN, DAG.getIntPtrConstant(4));
6277 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6278 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6279 MemOps.push_back(Store);
6281 // Store ptr to reg_save_area.
6282 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6283 FIN, DAG.getIntPtrConstant(8));
6284 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6285 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6286 MemOps.push_back(Store);
6287 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6288 &MemOps[0], MemOps.size());
6291 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6292 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6293 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6294 SDValue Chain = Op.getOperand(0);
6295 SDValue SrcPtr = Op.getOperand(1);
6296 SDValue SrcSV = Op.getOperand(2);
6298 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6302 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6303 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6304 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6305 SDValue Chain = Op.getOperand(0);
6306 SDValue DstPtr = Op.getOperand(1);
6307 SDValue SrcPtr = Op.getOperand(2);
6308 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6309 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6310 DebugLoc dl = Op.getDebugLoc();
6312 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6313 DAG.getIntPtrConstant(24), 8, false,
6314 DstSV, 0, SrcSV, 0);
6318 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6319 DebugLoc dl = Op.getDebugLoc();
6320 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6322 default: return SDValue(); // Don't custom lower most intrinsics.
6323 // Comparison intrinsics.
6324 case Intrinsic::x86_sse_comieq_ss:
6325 case Intrinsic::x86_sse_comilt_ss:
6326 case Intrinsic::x86_sse_comile_ss:
6327 case Intrinsic::x86_sse_comigt_ss:
6328 case Intrinsic::x86_sse_comige_ss:
6329 case Intrinsic::x86_sse_comineq_ss:
6330 case Intrinsic::x86_sse_ucomieq_ss:
6331 case Intrinsic::x86_sse_ucomilt_ss:
6332 case Intrinsic::x86_sse_ucomile_ss:
6333 case Intrinsic::x86_sse_ucomigt_ss:
6334 case Intrinsic::x86_sse_ucomige_ss:
6335 case Intrinsic::x86_sse_ucomineq_ss:
6336 case Intrinsic::x86_sse2_comieq_sd:
6337 case Intrinsic::x86_sse2_comilt_sd:
6338 case Intrinsic::x86_sse2_comile_sd:
6339 case Intrinsic::x86_sse2_comigt_sd:
6340 case Intrinsic::x86_sse2_comige_sd:
6341 case Intrinsic::x86_sse2_comineq_sd:
6342 case Intrinsic::x86_sse2_ucomieq_sd:
6343 case Intrinsic::x86_sse2_ucomilt_sd:
6344 case Intrinsic::x86_sse2_ucomile_sd:
6345 case Intrinsic::x86_sse2_ucomigt_sd:
6346 case Intrinsic::x86_sse2_ucomige_sd:
6347 case Intrinsic::x86_sse2_ucomineq_sd: {
6349 ISD::CondCode CC = ISD::SETCC_INVALID;
6352 case Intrinsic::x86_sse_comieq_ss:
6353 case Intrinsic::x86_sse2_comieq_sd:
6357 case Intrinsic::x86_sse_comilt_ss:
6358 case Intrinsic::x86_sse2_comilt_sd:
6362 case Intrinsic::x86_sse_comile_ss:
6363 case Intrinsic::x86_sse2_comile_sd:
6367 case Intrinsic::x86_sse_comigt_ss:
6368 case Intrinsic::x86_sse2_comigt_sd:
6372 case Intrinsic::x86_sse_comige_ss:
6373 case Intrinsic::x86_sse2_comige_sd:
6377 case Intrinsic::x86_sse_comineq_ss:
6378 case Intrinsic::x86_sse2_comineq_sd:
6382 case Intrinsic::x86_sse_ucomieq_ss:
6383 case Intrinsic::x86_sse2_ucomieq_sd:
6384 Opc = X86ISD::UCOMI;
6387 case Intrinsic::x86_sse_ucomilt_ss:
6388 case Intrinsic::x86_sse2_ucomilt_sd:
6389 Opc = X86ISD::UCOMI;
6392 case Intrinsic::x86_sse_ucomile_ss:
6393 case Intrinsic::x86_sse2_ucomile_sd:
6394 Opc = X86ISD::UCOMI;
6397 case Intrinsic::x86_sse_ucomigt_ss:
6398 case Intrinsic::x86_sse2_ucomigt_sd:
6399 Opc = X86ISD::UCOMI;
6402 case Intrinsic::x86_sse_ucomige_ss:
6403 case Intrinsic::x86_sse2_ucomige_sd:
6404 Opc = X86ISD::UCOMI;
6407 case Intrinsic::x86_sse_ucomineq_ss:
6408 case Intrinsic::x86_sse2_ucomineq_sd:
6409 Opc = X86ISD::UCOMI;
6414 SDValue LHS = Op.getOperand(1);
6415 SDValue RHS = Op.getOperand(2);
6416 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6417 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
6418 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6419 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6420 DAG.getConstant(X86CC, MVT::i8), Cond);
6421 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6423 // ptest intrinsics. The intrinsic these come from are designed to return
6424 // an integer value, not just an instruction so lower it to the ptest
6425 // pattern and a setcc for the result.
6426 case Intrinsic::x86_sse41_ptestz:
6427 case Intrinsic::x86_sse41_ptestc:
6428 case Intrinsic::x86_sse41_ptestnzc:{
6431 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6432 case Intrinsic::x86_sse41_ptestz:
6434 X86CC = X86::COND_E;
6436 case Intrinsic::x86_sse41_ptestc:
6438 X86CC = X86::COND_B;
6440 case Intrinsic::x86_sse41_ptestnzc:
6442 X86CC = X86::COND_A;
6446 SDValue LHS = Op.getOperand(1);
6447 SDValue RHS = Op.getOperand(2);
6448 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6449 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6450 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6451 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6454 // Fix vector shift instructions where the last operand is a non-immediate
6456 case Intrinsic::x86_sse2_pslli_w:
6457 case Intrinsic::x86_sse2_pslli_d:
6458 case Intrinsic::x86_sse2_pslli_q:
6459 case Intrinsic::x86_sse2_psrli_w:
6460 case Intrinsic::x86_sse2_psrli_d:
6461 case Intrinsic::x86_sse2_psrli_q:
6462 case Intrinsic::x86_sse2_psrai_w:
6463 case Intrinsic::x86_sse2_psrai_d:
6464 case Intrinsic::x86_mmx_pslli_w:
6465 case Intrinsic::x86_mmx_pslli_d:
6466 case Intrinsic::x86_mmx_pslli_q:
6467 case Intrinsic::x86_mmx_psrli_w:
6468 case Intrinsic::x86_mmx_psrli_d:
6469 case Intrinsic::x86_mmx_psrli_q:
6470 case Intrinsic::x86_mmx_psrai_w:
6471 case Intrinsic::x86_mmx_psrai_d: {
6472 SDValue ShAmt = Op.getOperand(2);
6473 if (isa<ConstantSDNode>(ShAmt))
6476 unsigned NewIntNo = 0;
6477 EVT ShAmtVT = MVT::v4i32;
6479 case Intrinsic::x86_sse2_pslli_w:
6480 NewIntNo = Intrinsic::x86_sse2_psll_w;
6482 case Intrinsic::x86_sse2_pslli_d:
6483 NewIntNo = Intrinsic::x86_sse2_psll_d;
6485 case Intrinsic::x86_sse2_pslli_q:
6486 NewIntNo = Intrinsic::x86_sse2_psll_q;
6488 case Intrinsic::x86_sse2_psrli_w:
6489 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6491 case Intrinsic::x86_sse2_psrli_d:
6492 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6494 case Intrinsic::x86_sse2_psrli_q:
6495 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6497 case Intrinsic::x86_sse2_psrai_w:
6498 NewIntNo = Intrinsic::x86_sse2_psra_w;
6500 case Intrinsic::x86_sse2_psrai_d:
6501 NewIntNo = Intrinsic::x86_sse2_psra_d;
6504 ShAmtVT = MVT::v2i32;
6506 case Intrinsic::x86_mmx_pslli_w:
6507 NewIntNo = Intrinsic::x86_mmx_psll_w;
6509 case Intrinsic::x86_mmx_pslli_d:
6510 NewIntNo = Intrinsic::x86_mmx_psll_d;
6512 case Intrinsic::x86_mmx_pslli_q:
6513 NewIntNo = Intrinsic::x86_mmx_psll_q;
6515 case Intrinsic::x86_mmx_psrli_w:
6516 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6518 case Intrinsic::x86_mmx_psrli_d:
6519 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6521 case Intrinsic::x86_mmx_psrli_q:
6522 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6524 case Intrinsic::x86_mmx_psrai_w:
6525 NewIntNo = Intrinsic::x86_mmx_psra_w;
6527 case Intrinsic::x86_mmx_psrai_d:
6528 NewIntNo = Intrinsic::x86_mmx_psra_d;
6530 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6536 // The vector shift intrinsics with scalars uses 32b shift amounts but
6537 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6541 ShOps[1] = DAG.getConstant(0, MVT::i32);
6542 if (ShAmtVT == MVT::v4i32) {
6543 ShOps[2] = DAG.getUNDEF(MVT::i32);
6544 ShOps[3] = DAG.getUNDEF(MVT::i32);
6545 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6547 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6550 EVT VT = Op.getValueType();
6551 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6552 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6553 DAG.getConstant(NewIntNo, MVT::i32),
6554 Op.getOperand(1), ShAmt);
6559 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6560 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6561 DebugLoc dl = Op.getDebugLoc();
6564 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6566 DAG.getConstant(TD->getPointerSize(),
6567 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6568 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6569 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6574 // Just load the return address.
6575 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6576 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6577 RetAddrFI, NULL, 0);
6580 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6581 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6582 MFI->setFrameAddressIsTaken(true);
6583 EVT VT = Op.getValueType();
6584 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6585 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6586 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6587 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6589 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6593 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6594 SelectionDAG &DAG) {
6595 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6598 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6600 MachineFunction &MF = DAG.getMachineFunction();
6601 SDValue Chain = Op.getOperand(0);
6602 SDValue Offset = Op.getOperand(1);
6603 SDValue Handler = Op.getOperand(2);
6604 DebugLoc dl = Op.getDebugLoc();
6606 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6608 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6610 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6611 DAG.getIntPtrConstant(-TD->getPointerSize()));
6612 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6613 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6614 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6615 MF.getRegInfo().addLiveOut(StoreAddrReg);
6617 return DAG.getNode(X86ISD::EH_RETURN, dl,
6619 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6622 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6623 SelectionDAG &DAG) {
6624 SDValue Root = Op.getOperand(0);
6625 SDValue Trmp = Op.getOperand(1); // trampoline
6626 SDValue FPtr = Op.getOperand(2); // nested function
6627 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6628 DebugLoc dl = Op.getDebugLoc();
6630 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6632 const X86InstrInfo *TII =
6633 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6635 if (Subtarget->is64Bit()) {
6636 SDValue OutChains[6];
6638 // Large code-model.
6640 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6641 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6643 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6644 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6646 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6648 // Load the pointer to the nested function into R11.
6649 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6650 SDValue Addr = Trmp;
6651 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6654 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6655 DAG.getConstant(2, MVT::i64));
6656 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6658 // Load the 'nest' parameter value into R10.
6659 // R10 is specified in X86CallingConv.td
6660 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6661 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6662 DAG.getConstant(10, MVT::i64));
6663 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6664 Addr, TrmpAddr, 10);
6666 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6667 DAG.getConstant(12, MVT::i64));
6668 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6670 // Jump to the nested function.
6671 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6672 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6673 DAG.getConstant(20, MVT::i64));
6674 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6675 Addr, TrmpAddr, 20);
6677 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6678 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6679 DAG.getConstant(22, MVT::i64));
6680 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6684 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6685 return DAG.getMergeValues(Ops, 2, dl);
6687 const Function *Func =
6688 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6689 CallingConv::ID CC = Func->getCallingConv();
6694 llvm_unreachable("Unsupported calling convention");
6695 case CallingConv::C:
6696 case CallingConv::X86_StdCall: {
6697 // Pass 'nest' parameter in ECX.
6698 // Must be kept in sync with X86CallingConv.td
6701 // Check that ECX wasn't needed by an 'inreg' parameter.
6702 const FunctionType *FTy = Func->getFunctionType();
6703 const AttrListPtr &Attrs = Func->getAttributes();
6705 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6706 unsigned InRegCount = 0;
6709 for (FunctionType::param_iterator I = FTy->param_begin(),
6710 E = FTy->param_end(); I != E; ++I, ++Idx)
6711 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6712 // FIXME: should only count parameters that are lowered to integers.
6713 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6715 if (InRegCount > 2) {
6716 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6721 case CallingConv::X86_FastCall:
6722 case CallingConv::Fast:
6723 // Pass 'nest' parameter in EAX.
6724 // Must be kept in sync with X86CallingConv.td
6729 SDValue OutChains[4];
6732 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6733 DAG.getConstant(10, MVT::i32));
6734 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6736 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6737 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6738 OutChains[0] = DAG.getStore(Root, dl,
6739 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6742 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6743 DAG.getConstant(1, MVT::i32));
6744 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6746 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6747 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6748 DAG.getConstant(5, MVT::i32));
6749 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6750 TrmpAddr, 5, false, 1);
6752 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6753 DAG.getConstant(6, MVT::i32));
6754 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6757 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6758 return DAG.getMergeValues(Ops, 2, dl);
6762 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6764 The rounding mode is in bits 11:10 of FPSR, and has the following
6771 FLT_ROUNDS, on the other hand, expects the following:
6778 To perform the conversion, we do:
6779 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6782 MachineFunction &MF = DAG.getMachineFunction();
6783 const TargetMachine &TM = MF.getTarget();
6784 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6785 unsigned StackAlignment = TFI.getStackAlignment();
6786 EVT VT = Op.getValueType();
6787 DebugLoc dl = Op.getDebugLoc();
6789 // Save FP Control Word to stack slot
6790 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
6791 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6793 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6794 DAG.getEntryNode(), StackSlot);
6796 // Load FP Control Word from stack slot
6797 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6799 // Transform as necessary
6801 DAG.getNode(ISD::SRL, dl, MVT::i16,
6802 DAG.getNode(ISD::AND, dl, MVT::i16,
6803 CWD, DAG.getConstant(0x800, MVT::i16)),
6804 DAG.getConstant(11, MVT::i8));
6806 DAG.getNode(ISD::SRL, dl, MVT::i16,
6807 DAG.getNode(ISD::AND, dl, MVT::i16,
6808 CWD, DAG.getConstant(0x400, MVT::i16)),
6809 DAG.getConstant(9, MVT::i8));
6812 DAG.getNode(ISD::AND, dl, MVT::i16,
6813 DAG.getNode(ISD::ADD, dl, MVT::i16,
6814 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6815 DAG.getConstant(1, MVT::i16)),
6816 DAG.getConstant(3, MVT::i16));
6819 return DAG.getNode((VT.getSizeInBits() < 16 ?
6820 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6823 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6824 EVT VT = Op.getValueType();
6826 unsigned NumBits = VT.getSizeInBits();
6827 DebugLoc dl = Op.getDebugLoc();
6829 Op = Op.getOperand(0);
6830 if (VT == MVT::i8) {
6831 // Zero extend to i32 since there is not an i8 bsr.
6833 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6836 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6837 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6838 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6840 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6841 SmallVector<SDValue, 4> Ops;
6843 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6844 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6845 Ops.push_back(Op.getValue(1));
6846 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6848 // Finally xor with NumBits-1.
6849 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6852 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6856 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6857 EVT VT = Op.getValueType();
6859 unsigned NumBits = VT.getSizeInBits();
6860 DebugLoc dl = Op.getDebugLoc();
6862 Op = Op.getOperand(0);
6863 if (VT == MVT::i8) {
6865 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6868 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6869 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6870 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6872 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6873 SmallVector<SDValue, 4> Ops;
6875 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6876 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6877 Ops.push_back(Op.getValue(1));
6878 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6881 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6885 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6886 EVT VT = Op.getValueType();
6887 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6888 DebugLoc dl = Op.getDebugLoc();
6890 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6891 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6892 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6893 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6894 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6896 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6897 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6898 // return AloBlo + AloBhi + AhiBlo;
6900 SDValue A = Op.getOperand(0);
6901 SDValue B = Op.getOperand(1);
6903 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6904 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6905 A, DAG.getConstant(32, MVT::i32));
6906 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6907 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6908 B, DAG.getConstant(32, MVT::i32));
6909 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6910 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6912 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6913 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6915 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6916 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6918 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6919 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6920 AloBhi, DAG.getConstant(32, MVT::i32));
6921 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6922 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6923 AhiBlo, DAG.getConstant(32, MVT::i32));
6924 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6925 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6930 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6931 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6932 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6933 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6934 // has only one use.
6935 SDNode *N = Op.getNode();
6936 SDValue LHS = N->getOperand(0);
6937 SDValue RHS = N->getOperand(1);
6938 unsigned BaseOp = 0;
6940 DebugLoc dl = Op.getDebugLoc();
6942 switch (Op.getOpcode()) {
6943 default: llvm_unreachable("Unknown ovf instruction!");
6945 // A subtract of one will be selected as a INC. Note that INC doesn't
6946 // set CF, so we can't do this for UADDO.
6947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6948 if (C->getAPIntValue() == 1) {
6949 BaseOp = X86ISD::INC;
6953 BaseOp = X86ISD::ADD;
6957 BaseOp = X86ISD::ADD;
6961 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6962 // set CF, so we can't do this for USUBO.
6963 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6964 if (C->getAPIntValue() == 1) {
6965 BaseOp = X86ISD::DEC;
6969 BaseOp = X86ISD::SUB;
6973 BaseOp = X86ISD::SUB;
6977 BaseOp = X86ISD::SMUL;
6981 BaseOp = X86ISD::UMUL;
6986 // Also sets EFLAGS.
6987 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6988 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6991 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6992 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6994 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6998 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6999 EVT T = Op.getValueType();
7000 DebugLoc dl = Op.getDebugLoc();
7003 switch(T.getSimpleVT().SimpleTy) {
7005 assert(false && "Invalid value type!");
7006 case MVT::i8: Reg = X86::AL; size = 1; break;
7007 case MVT::i16: Reg = X86::AX; size = 2; break;
7008 case MVT::i32: Reg = X86::EAX; size = 4; break;
7010 assert(Subtarget->is64Bit() && "Node not type legal!");
7011 Reg = X86::RAX; size = 8;
7014 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
7015 Op.getOperand(2), SDValue());
7016 SDValue Ops[] = { cpIn.getValue(0),
7019 DAG.getTargetConstant(size, MVT::i8),
7021 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7022 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
7024 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
7028 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
7029 SelectionDAG &DAG) {
7030 assert(Subtarget->is64Bit() && "Result not type legalized?");
7031 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7032 SDValue TheChain = Op.getOperand(0);
7033 DebugLoc dl = Op.getDebugLoc();
7034 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7035 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
7036 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
7038 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
7039 DAG.getConstant(32, MVT::i8));
7041 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
7044 return DAG.getMergeValues(Ops, 2, dl);
7047 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
7048 SDNode *Node = Op.getNode();
7049 DebugLoc dl = Node->getDebugLoc();
7050 EVT T = Node->getValueType(0);
7051 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
7052 DAG.getConstant(0, T), Node->getOperand(2));
7053 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
7054 cast<AtomicSDNode>(Node)->getMemoryVT(),
7055 Node->getOperand(0),
7056 Node->getOperand(1), negOp,
7057 cast<AtomicSDNode>(Node)->getSrcValue(),
7058 cast<AtomicSDNode>(Node)->getAlignment());
7061 /// LowerOperation - Provide custom lowering hooks for some operations.
7063 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
7064 switch (Op.getOpcode()) {
7065 default: llvm_unreachable("Should not custom lower this!");
7066 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
7067 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
7068 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7069 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7070 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7071 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
7072 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7073 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7074 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7075 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7076 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
7077 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7078 case ISD::SHL_PARTS:
7079 case ISD::SRA_PARTS:
7080 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
7081 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
7082 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
7083 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
7084 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
7085 case ISD::FABS: return LowerFABS(Op, DAG);
7086 case ISD::FNEG: return LowerFNEG(Op, DAG);
7087 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
7088 case ISD::SETCC: return LowerSETCC(Op, DAG);
7089 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
7090 case ISD::SELECT: return LowerSELECT(Op, DAG);
7091 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
7092 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7093 case ISD::VASTART: return LowerVASTART(Op, DAG);
7094 case ISD::VAARG: return LowerVAARG(Op, DAG);
7095 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
7096 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7097 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7098 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7099 case ISD::FRAME_TO_ARGS_OFFSET:
7100 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
7101 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
7102 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
7103 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
7104 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7105 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
7106 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
7107 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
7113 case ISD::UMULO: return LowerXALUO(Op, DAG);
7114 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
7118 void X86TargetLowering::
7119 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
7120 SelectionDAG &DAG, unsigned NewOp) {
7121 EVT T = Node->getValueType(0);
7122 DebugLoc dl = Node->getDebugLoc();
7123 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
7125 SDValue Chain = Node->getOperand(0);
7126 SDValue In1 = Node->getOperand(1);
7127 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7128 Node->getOperand(2), DAG.getIntPtrConstant(0));
7129 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7130 Node->getOperand(2), DAG.getIntPtrConstant(1));
7131 SDValue Ops[] = { Chain, In1, In2L, In2H };
7132 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7134 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
7135 cast<MemSDNode>(Node)->getMemOperand());
7136 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
7137 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7138 Results.push_back(Result.getValue(2));
7141 /// ReplaceNodeResults - Replace a node with an illegal result type
7142 /// with a new node built out of custom code.
7143 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
7144 SmallVectorImpl<SDValue>&Results,
7145 SelectionDAG &DAG) {
7146 DebugLoc dl = N->getDebugLoc();
7147 switch (N->getOpcode()) {
7149 assert(false && "Do not know how to custom type legalize this operation!");
7151 case ISD::FP_TO_SINT: {
7152 std::pair<SDValue,SDValue> Vals =
7153 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
7154 SDValue FIST = Vals.first, StackSlot = Vals.second;
7155 if (FIST.getNode() != 0) {
7156 EVT VT = N->getValueType(0);
7157 // Return a load from the stack slot.
7158 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
7162 case ISD::READCYCLECOUNTER: {
7163 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7164 SDValue TheChain = N->getOperand(0);
7165 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
7166 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
7168 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
7170 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
7171 SDValue Ops[] = { eax, edx };
7172 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
7173 Results.push_back(edx.getValue(1));
7176 case ISD::ATOMIC_CMP_SWAP: {
7177 EVT T = N->getValueType(0);
7178 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7179 SDValue cpInL, cpInH;
7180 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7181 DAG.getConstant(0, MVT::i32));
7182 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7183 DAG.getConstant(1, MVT::i32));
7184 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7185 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7187 SDValue swapInL, swapInH;
7188 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7189 DAG.getConstant(0, MVT::i32));
7190 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7191 DAG.getConstant(1, MVT::i32));
7192 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7194 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7195 swapInL.getValue(1));
7196 SDValue Ops[] = { swapInH.getValue(0),
7198 swapInH.getValue(1) };
7199 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7200 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7201 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7202 MVT::i32, Result.getValue(1));
7203 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7204 MVT::i32, cpOutL.getValue(2));
7205 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7206 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7207 Results.push_back(cpOutH.getValue(1));
7210 case ISD::ATOMIC_LOAD_ADD:
7211 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7213 case ISD::ATOMIC_LOAD_AND:
7214 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7216 case ISD::ATOMIC_LOAD_NAND:
7217 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7219 case ISD::ATOMIC_LOAD_OR:
7220 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7222 case ISD::ATOMIC_LOAD_SUB:
7223 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7225 case ISD::ATOMIC_LOAD_XOR:
7226 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7228 case ISD::ATOMIC_SWAP:
7229 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7234 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7236 default: return NULL;
7237 case X86ISD::BSF: return "X86ISD::BSF";
7238 case X86ISD::BSR: return "X86ISD::BSR";
7239 case X86ISD::SHLD: return "X86ISD::SHLD";
7240 case X86ISD::SHRD: return "X86ISD::SHRD";
7241 case X86ISD::FAND: return "X86ISD::FAND";
7242 case X86ISD::FOR: return "X86ISD::FOR";
7243 case X86ISD::FXOR: return "X86ISD::FXOR";
7244 case X86ISD::FSRL: return "X86ISD::FSRL";
7245 case X86ISD::FILD: return "X86ISD::FILD";
7246 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7247 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7248 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7249 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7250 case X86ISD::FLD: return "X86ISD::FLD";
7251 case X86ISD::FST: return "X86ISD::FST";
7252 case X86ISD::CALL: return "X86ISD::CALL";
7253 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7254 case X86ISD::BT: return "X86ISD::BT";
7255 case X86ISD::CMP: return "X86ISD::CMP";
7256 case X86ISD::COMI: return "X86ISD::COMI";
7257 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7258 case X86ISD::SETCC: return "X86ISD::SETCC";
7259 case X86ISD::CMOV: return "X86ISD::CMOV";
7260 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7261 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7262 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7263 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7264 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7265 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7266 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7267 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7268 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7269 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7270 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7271 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7272 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7273 case X86ISD::FMAX: return "X86ISD::FMAX";
7274 case X86ISD::FMIN: return "X86ISD::FMIN";
7275 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7276 case X86ISD::FRCP: return "X86ISD::FRCP";
7277 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7278 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7279 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7280 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7281 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7282 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7283 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7284 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7285 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7286 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7287 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7288 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7289 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7290 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7291 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7292 case X86ISD::VSHL: return "X86ISD::VSHL";
7293 case X86ISD::VSRL: return "X86ISD::VSRL";
7294 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7295 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7296 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7297 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7298 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7299 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7300 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7301 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7302 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7303 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7304 case X86ISD::ADD: return "X86ISD::ADD";
7305 case X86ISD::SUB: return "X86ISD::SUB";
7306 case X86ISD::SMUL: return "X86ISD::SMUL";
7307 case X86ISD::UMUL: return "X86ISD::UMUL";
7308 case X86ISD::INC: return "X86ISD::INC";
7309 case X86ISD::DEC: return "X86ISD::DEC";
7310 case X86ISD::OR: return "X86ISD::OR";
7311 case X86ISD::XOR: return "X86ISD::XOR";
7312 case X86ISD::AND: return "X86ISD::AND";
7313 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7314 case X86ISD::PTEST: return "X86ISD::PTEST";
7315 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7319 // isLegalAddressingMode - Return true if the addressing mode represented
7320 // by AM is legal for this target, for a load/store of the specified type.
7321 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7322 const Type *Ty) const {
7323 // X86 supports extremely general addressing modes.
7324 CodeModel::Model M = getTargetMachine().getCodeModel();
7326 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7327 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7332 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7334 // If a reference to this global requires an extra load, we can't fold it.
7335 if (isGlobalStubReference(GVFlags))
7338 // If BaseGV requires a register for the PIC base, we cannot also have a
7339 // BaseReg specified.
7340 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7343 // If lower 4G is not available, then we must use rip-relative addressing.
7344 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7354 // These scales always work.
7359 // These scales are formed with basereg+scalereg. Only accept if there is
7364 default: // Other stuff never works.
7372 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7373 if (!Ty1->isInteger() || !Ty2->isInteger())
7375 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7376 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7377 if (NumBits1 <= NumBits2)
7379 return Subtarget->is64Bit() || NumBits1 < 64;
7382 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7383 if (!VT1.isInteger() || !VT2.isInteger())
7385 unsigned NumBits1 = VT1.getSizeInBits();
7386 unsigned NumBits2 = VT2.getSizeInBits();
7387 if (NumBits1 <= NumBits2)
7389 return Subtarget->is64Bit() || NumBits1 < 64;
7392 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7393 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7394 return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
7395 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
7398 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7399 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7400 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7403 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7404 // i16 instructions are longer (0x66 prefix) and potentially slower.
7405 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7408 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7409 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7410 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7411 /// are assumed to be legal.
7413 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7415 // Only do shuffles on 128-bit vector types for now.
7416 if (VT.getSizeInBits() == 64)
7419 // FIXME: pshufb, blends, shifts.
7420 return (VT.getVectorNumElements() == 2 ||
7421 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7422 isMOVLMask(M, VT) ||
7423 isSHUFPMask(M, VT) ||
7424 isPSHUFDMask(M, VT) ||
7425 isPSHUFHWMask(M, VT) ||
7426 isPSHUFLWMask(M, VT) ||
7427 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
7428 isUNPCKLMask(M, VT) ||
7429 isUNPCKHMask(M, VT) ||
7430 isUNPCKL_v_undef_Mask(M, VT) ||
7431 isUNPCKH_v_undef_Mask(M, VT));
7435 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7437 unsigned NumElts = VT.getVectorNumElements();
7438 // FIXME: This collection of masks seems suspect.
7441 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7442 return (isMOVLMask(Mask, VT) ||
7443 isCommutedMOVLMask(Mask, VT, true) ||
7444 isSHUFPMask(Mask, VT) ||
7445 isCommutedSHUFPMask(Mask, VT));
7450 //===----------------------------------------------------------------------===//
7451 // X86 Scheduler Hooks
7452 //===----------------------------------------------------------------------===//
7454 // private utility function
7456 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7457 MachineBasicBlock *MBB,
7465 TargetRegisterClass *RC,
7466 bool invSrc) const {
7467 // For the atomic bitwise operator, we generate
7470 // ld t1 = [bitinstr.addr]
7471 // op t2 = t1, [bitinstr.val]
7473 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7475 // fallthrough -->nextMBB
7476 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7477 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7478 MachineFunction::iterator MBBIter = MBB;
7481 /// First build the CFG
7482 MachineFunction *F = MBB->getParent();
7483 MachineBasicBlock *thisMBB = MBB;
7484 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7485 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7486 F->insert(MBBIter, newMBB);
7487 F->insert(MBBIter, nextMBB);
7489 // Move all successors to thisMBB to nextMBB
7490 nextMBB->transferSuccessors(thisMBB);
7492 // Update thisMBB to fall through to newMBB
7493 thisMBB->addSuccessor(newMBB);
7495 // newMBB jumps to itself and fall through to nextMBB
7496 newMBB->addSuccessor(nextMBB);
7497 newMBB->addSuccessor(newMBB);
7499 // Insert instructions into newMBB based on incoming instruction
7500 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7501 "unexpected number of operands");
7502 DebugLoc dl = bInstr->getDebugLoc();
7503 MachineOperand& destOper = bInstr->getOperand(0);
7504 MachineOperand* argOpers[2 + X86AddrNumOperands];
7505 int numArgs = bInstr->getNumOperands() - 1;
7506 for (int i=0; i < numArgs; ++i)
7507 argOpers[i] = &bInstr->getOperand(i+1);
7509 // x86 address has 4 operands: base, index, scale, and displacement
7510 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7511 int valArgIndx = lastAddrIndx + 1;
7513 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7514 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7515 for (int i=0; i <= lastAddrIndx; ++i)
7516 (*MIB).addOperand(*argOpers[i]);
7518 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7520 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7525 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7526 assert((argOpers[valArgIndx]->isReg() ||
7527 argOpers[valArgIndx]->isImm()) &&
7529 if (argOpers[valArgIndx]->isReg())
7530 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7532 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7534 (*MIB).addOperand(*argOpers[valArgIndx]);
7536 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7539 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7540 for (int i=0; i <= lastAddrIndx; ++i)
7541 (*MIB).addOperand(*argOpers[i]);
7543 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7544 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7545 bInstr->memoperands_end());
7547 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7551 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7553 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7557 // private utility function: 64 bit atomics on 32 bit host.
7559 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7560 MachineBasicBlock *MBB,
7565 bool invSrc) const {
7566 // For the atomic bitwise operator, we generate
7567 // thisMBB (instructions are in pairs, except cmpxchg8b)
7568 // ld t1,t2 = [bitinstr.addr]
7570 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7571 // op t5, t6 <- out1, out2, [bitinstr.val]
7572 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7573 // mov ECX, EBX <- t5, t6
7574 // mov EAX, EDX <- t1, t2
7575 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7576 // mov t3, t4 <- EAX, EDX
7578 // result in out1, out2
7579 // fallthrough -->nextMBB
7581 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7582 const unsigned LoadOpc = X86::MOV32rm;
7583 const unsigned copyOpc = X86::MOV32rr;
7584 const unsigned NotOpc = X86::NOT32r;
7585 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7586 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7587 MachineFunction::iterator MBBIter = MBB;
7590 /// First build the CFG
7591 MachineFunction *F = MBB->getParent();
7592 MachineBasicBlock *thisMBB = MBB;
7593 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7594 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7595 F->insert(MBBIter, newMBB);
7596 F->insert(MBBIter, nextMBB);
7598 // Move all successors to thisMBB to nextMBB
7599 nextMBB->transferSuccessors(thisMBB);
7601 // Update thisMBB to fall through to newMBB
7602 thisMBB->addSuccessor(newMBB);
7604 // newMBB jumps to itself and fall through to nextMBB
7605 newMBB->addSuccessor(nextMBB);
7606 newMBB->addSuccessor(newMBB);
7608 DebugLoc dl = bInstr->getDebugLoc();
7609 // Insert instructions into newMBB based on incoming instruction
7610 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7611 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7612 "unexpected number of operands");
7613 MachineOperand& dest1Oper = bInstr->getOperand(0);
7614 MachineOperand& dest2Oper = bInstr->getOperand(1);
7615 MachineOperand* argOpers[2 + X86AddrNumOperands];
7616 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7617 argOpers[i] = &bInstr->getOperand(i+2);
7619 // x86 address has 4 operands: base, index, scale, and displacement
7620 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7622 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7623 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7624 for (int i=0; i <= lastAddrIndx; ++i)
7625 (*MIB).addOperand(*argOpers[i]);
7626 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7627 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7628 // add 4 to displacement.
7629 for (int i=0; i <= lastAddrIndx-2; ++i)
7630 (*MIB).addOperand(*argOpers[i]);
7631 MachineOperand newOp3 = *(argOpers[3]);
7633 newOp3.setImm(newOp3.getImm()+4);
7635 newOp3.setOffset(newOp3.getOffset()+4);
7636 (*MIB).addOperand(newOp3);
7637 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7639 // t3/4 are defined later, at the bottom of the loop
7640 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7641 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7642 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7643 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7644 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7645 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7647 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7648 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7650 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7651 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7657 int valArgIndx = lastAddrIndx + 1;
7658 assert((argOpers[valArgIndx]->isReg() ||
7659 argOpers[valArgIndx]->isImm()) &&
7661 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7662 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7663 if (argOpers[valArgIndx]->isReg())
7664 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7666 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7667 if (regOpcL != X86::MOV32rr)
7669 (*MIB).addOperand(*argOpers[valArgIndx]);
7670 assert(argOpers[valArgIndx + 1]->isReg() ==
7671 argOpers[valArgIndx]->isReg());
7672 assert(argOpers[valArgIndx + 1]->isImm() ==
7673 argOpers[valArgIndx]->isImm());
7674 if (argOpers[valArgIndx + 1]->isReg())
7675 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7677 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7678 if (regOpcH != X86::MOV32rr)
7680 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7682 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7684 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7687 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7689 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7692 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7693 for (int i=0; i <= lastAddrIndx; ++i)
7694 (*MIB).addOperand(*argOpers[i]);
7696 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7697 (*MIB).setMemRefs(bInstr->memoperands_begin(),
7698 bInstr->memoperands_end());
7700 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7701 MIB.addReg(X86::EAX);
7702 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7703 MIB.addReg(X86::EDX);
7706 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7708 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7712 // private utility function
7714 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7715 MachineBasicBlock *MBB,
7716 unsigned cmovOpc) const {
7717 // For the atomic min/max operator, we generate
7720 // ld t1 = [min/max.addr]
7721 // mov t2 = [min/max.val]
7723 // cmov[cond] t2 = t1
7725 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7727 // fallthrough -->nextMBB
7729 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7730 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7731 MachineFunction::iterator MBBIter = MBB;
7734 /// First build the CFG
7735 MachineFunction *F = MBB->getParent();
7736 MachineBasicBlock *thisMBB = MBB;
7737 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7738 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7739 F->insert(MBBIter, newMBB);
7740 F->insert(MBBIter, nextMBB);
7742 // Move all successors of thisMBB to nextMBB
7743 nextMBB->transferSuccessors(thisMBB);
7745 // Update thisMBB to fall through to newMBB
7746 thisMBB->addSuccessor(newMBB);
7748 // newMBB jumps to newMBB and fall through to nextMBB
7749 newMBB->addSuccessor(nextMBB);
7750 newMBB->addSuccessor(newMBB);
7752 DebugLoc dl = mInstr->getDebugLoc();
7753 // Insert instructions into newMBB based on incoming instruction
7754 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7755 "unexpected number of operands");
7756 MachineOperand& destOper = mInstr->getOperand(0);
7757 MachineOperand* argOpers[2 + X86AddrNumOperands];
7758 int numArgs = mInstr->getNumOperands() - 1;
7759 for (int i=0; i < numArgs; ++i)
7760 argOpers[i] = &mInstr->getOperand(i+1);
7762 // x86 address has 4 operands: base, index, scale, and displacement
7763 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7764 int valArgIndx = lastAddrIndx + 1;
7766 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7767 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7768 for (int i=0; i <= lastAddrIndx; ++i)
7769 (*MIB).addOperand(*argOpers[i]);
7771 // We only support register and immediate values
7772 assert((argOpers[valArgIndx]->isReg() ||
7773 argOpers[valArgIndx]->isImm()) &&
7776 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7777 if (argOpers[valArgIndx]->isReg())
7778 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7780 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7781 (*MIB).addOperand(*argOpers[valArgIndx]);
7783 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7786 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7791 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7792 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7796 // Cmp and exchange if none has modified the memory location
7797 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7798 for (int i=0; i <= lastAddrIndx; ++i)
7799 (*MIB).addOperand(*argOpers[i]);
7801 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7802 (*MIB).setMemRefs(mInstr->memoperands_begin(),
7803 mInstr->memoperands_end());
7805 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7806 MIB.addReg(X86::EAX);
7809 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7811 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7815 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7816 // all of this code can be replaced with that in the .td file.
7818 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7819 unsigned numArgs, bool memArg) const {
7821 MachineFunction *F = BB->getParent();
7822 DebugLoc dl = MI->getDebugLoc();
7823 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7827 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
7829 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
7831 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
7833 for (unsigned i = 0; i < numArgs; ++i) {
7834 MachineOperand &Op = MI->getOperand(i+1);
7836 if (!(Op.isReg() && Op.isImplicit()))
7840 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
7843 F->DeleteMachineInstr(MI);
7849 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
7851 MachineBasicBlock *MBB) const {
7852 // Emit code to save XMM registers to the stack. The ABI says that the
7853 // number of registers to save is given in %al, so it's theoretically
7854 // possible to do an indirect jump trick to avoid saving all of them,
7855 // however this code takes a simpler approach and just executes all
7856 // of the stores if %al is non-zero. It's less code, and it's probably
7857 // easier on the hardware branch predictor, and stores aren't all that
7858 // expensive anyway.
7860 // Create the new basic blocks. One block contains all the XMM stores,
7861 // and one block is the final destination regardless of whether any
7862 // stores were performed.
7863 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7864 MachineFunction *F = MBB->getParent();
7865 MachineFunction::iterator MBBIter = MBB;
7867 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
7868 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
7869 F->insert(MBBIter, XMMSaveMBB);
7870 F->insert(MBBIter, EndMBB);
7873 // Move any original successors of MBB to the end block.
7874 EndMBB->transferSuccessors(MBB);
7875 // The original block will now fall through to the XMM save block.
7876 MBB->addSuccessor(XMMSaveMBB);
7877 // The XMMSaveMBB will fall through to the end block.
7878 XMMSaveMBB->addSuccessor(EndMBB);
7880 // Now add the instructions.
7881 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7882 DebugLoc DL = MI->getDebugLoc();
7884 unsigned CountReg = MI->getOperand(0).getReg();
7885 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
7886 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
7888 if (!Subtarget->isTargetWin64()) {
7889 // If %al is 0, branch around the XMM save block.
7890 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
7891 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
7892 MBB->addSuccessor(EndMBB);
7895 // In the XMM save block, save all the XMM argument registers.
7896 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
7897 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
7898 MachineMemOperand *MMO =
7899 F->getMachineMemOperand(
7900 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
7901 MachineMemOperand::MOStore, Offset,
7902 /*Size=*/16, /*Align=*/16);
7903 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
7904 .addFrameIndex(RegSaveFrameIndex)
7905 .addImm(/*Scale=*/1)
7906 .addReg(/*IndexReg=*/0)
7907 .addImm(/*Disp=*/Offset)
7908 .addReg(/*Segment=*/0)
7909 .addReg(MI->getOperand(i).getReg())
7910 .addMemOperand(MMO);
7913 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7919 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
7920 MachineBasicBlock *BB,
7921 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
7922 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7923 DebugLoc DL = MI->getDebugLoc();
7925 // To "insert" a SELECT_CC instruction, we actually have to insert the
7926 // diamond control-flow pattern. The incoming instruction knows the
7927 // destination vreg to set, the condition code register to branch on, the
7928 // true/false values to select between, and a branch opcode to use.
7929 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7930 MachineFunction::iterator It = BB;
7936 // cmpTY ccX, r1, r2
7938 // fallthrough --> copy0MBB
7939 MachineBasicBlock *thisMBB = BB;
7940 MachineFunction *F = BB->getParent();
7941 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7942 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7944 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7945 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
7946 F->insert(It, copy0MBB);
7947 F->insert(It, sinkMBB);
7948 // Update machine-CFG edges by first adding all successors of the current
7949 // block to the new block which will contain the Phi node for the select.
7950 // Also inform sdisel of the edge changes.
7951 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
7952 E = BB->succ_end(); I != E; ++I) {
7953 EM->insert(std::make_pair(*I, sinkMBB));
7954 sinkMBB->addSuccessor(*I);
7956 // Next, remove all successors of the current block, and add the true
7957 // and fallthrough blocks as its successors.
7958 while (!BB->succ_empty())
7959 BB->removeSuccessor(BB->succ_begin());
7960 // Add the true and fallthrough blocks as its successors.
7961 BB->addSuccessor(copy0MBB);
7962 BB->addSuccessor(sinkMBB);
7965 // %FalseValue = ...
7966 // # fallthrough to sinkMBB
7969 // Update machine-CFG edges
7970 BB->addSuccessor(sinkMBB);
7973 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7976 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
7977 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7978 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7980 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7986 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7987 MachineBasicBlock *BB,
7988 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
7989 switch (MI->getOpcode()) {
7990 default: assert(false && "Unexpected instr type to insert");
7992 case X86::CMOV_V1I64:
7993 case X86::CMOV_FR32:
7994 case X86::CMOV_FR64:
7995 case X86::CMOV_V4F32:
7996 case X86::CMOV_V2F64:
7997 case X86::CMOV_V2I64:
7998 return EmitLoweredSelect(MI, BB, EM);
8000 case X86::FP32_TO_INT16_IN_MEM:
8001 case X86::FP32_TO_INT32_IN_MEM:
8002 case X86::FP32_TO_INT64_IN_MEM:
8003 case X86::FP64_TO_INT16_IN_MEM:
8004 case X86::FP64_TO_INT32_IN_MEM:
8005 case X86::FP64_TO_INT64_IN_MEM:
8006 case X86::FP80_TO_INT16_IN_MEM:
8007 case X86::FP80_TO_INT32_IN_MEM:
8008 case X86::FP80_TO_INT64_IN_MEM: {
8009 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
8010 DebugLoc DL = MI->getDebugLoc();
8012 // Change the floating point control register to use "round towards zero"
8013 // mode when truncating to an integer value.
8014 MachineFunction *F = BB->getParent();
8015 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
8016 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
8018 // Load the old value of the high byte of the control word...
8020 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
8021 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
8024 // Set the high part to be round to zero...
8025 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
8028 // Reload the modified control word now...
8029 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8031 // Restore the memory image of control word to original value
8032 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
8035 // Get the X86 opcode to use.
8037 switch (MI->getOpcode()) {
8038 default: llvm_unreachable("illegal opcode!");
8039 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
8040 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
8041 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
8042 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
8043 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
8044 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
8045 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
8046 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
8047 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
8051 MachineOperand &Op = MI->getOperand(0);
8053 AM.BaseType = X86AddressMode::RegBase;
8054 AM.Base.Reg = Op.getReg();
8056 AM.BaseType = X86AddressMode::FrameIndexBase;
8057 AM.Base.FrameIndex = Op.getIndex();
8059 Op = MI->getOperand(1);
8061 AM.Scale = Op.getImm();
8062 Op = MI->getOperand(2);
8064 AM.IndexReg = Op.getImm();
8065 Op = MI->getOperand(3);
8066 if (Op.isGlobal()) {
8067 AM.GV = Op.getGlobal();
8069 AM.Disp = Op.getImm();
8071 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
8072 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
8074 // Reload the original control word now.
8075 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
8077 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
8080 // String/text processing lowering.
8081 case X86::PCMPISTRM128REG:
8082 return EmitPCMP(MI, BB, 3, false /* in-mem */);
8083 case X86::PCMPISTRM128MEM:
8084 return EmitPCMP(MI, BB, 3, true /* in-mem */);
8085 case X86::PCMPESTRM128REG:
8086 return EmitPCMP(MI, BB, 5, false /* in mem */);
8087 case X86::PCMPESTRM128MEM:
8088 return EmitPCMP(MI, BB, 5, true /* in mem */);
8091 case X86::ATOMAND32:
8092 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8093 X86::AND32ri, X86::MOV32rm,
8094 X86::LCMPXCHG32, X86::MOV32rr,
8095 X86::NOT32r, X86::EAX,
8096 X86::GR32RegisterClass);
8098 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
8099 X86::OR32ri, X86::MOV32rm,
8100 X86::LCMPXCHG32, X86::MOV32rr,
8101 X86::NOT32r, X86::EAX,
8102 X86::GR32RegisterClass);
8103 case X86::ATOMXOR32:
8104 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
8105 X86::XOR32ri, X86::MOV32rm,
8106 X86::LCMPXCHG32, X86::MOV32rr,
8107 X86::NOT32r, X86::EAX,
8108 X86::GR32RegisterClass);
8109 case X86::ATOMNAND32:
8110 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
8111 X86::AND32ri, X86::MOV32rm,
8112 X86::LCMPXCHG32, X86::MOV32rr,
8113 X86::NOT32r, X86::EAX,
8114 X86::GR32RegisterClass, true);
8115 case X86::ATOMMIN32:
8116 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
8117 case X86::ATOMMAX32:
8118 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
8119 case X86::ATOMUMIN32:
8120 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
8121 case X86::ATOMUMAX32:
8122 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
8124 case X86::ATOMAND16:
8125 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8126 X86::AND16ri, X86::MOV16rm,
8127 X86::LCMPXCHG16, X86::MOV16rr,
8128 X86::NOT16r, X86::AX,
8129 X86::GR16RegisterClass);
8131 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
8132 X86::OR16ri, X86::MOV16rm,
8133 X86::LCMPXCHG16, X86::MOV16rr,
8134 X86::NOT16r, X86::AX,
8135 X86::GR16RegisterClass);
8136 case X86::ATOMXOR16:
8137 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
8138 X86::XOR16ri, X86::MOV16rm,
8139 X86::LCMPXCHG16, X86::MOV16rr,
8140 X86::NOT16r, X86::AX,
8141 X86::GR16RegisterClass);
8142 case X86::ATOMNAND16:
8143 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
8144 X86::AND16ri, X86::MOV16rm,
8145 X86::LCMPXCHG16, X86::MOV16rr,
8146 X86::NOT16r, X86::AX,
8147 X86::GR16RegisterClass, true);
8148 case X86::ATOMMIN16:
8149 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
8150 case X86::ATOMMAX16:
8151 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
8152 case X86::ATOMUMIN16:
8153 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
8154 case X86::ATOMUMAX16:
8155 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
8158 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8159 X86::AND8ri, X86::MOV8rm,
8160 X86::LCMPXCHG8, X86::MOV8rr,
8161 X86::NOT8r, X86::AL,
8162 X86::GR8RegisterClass);
8164 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
8165 X86::OR8ri, X86::MOV8rm,
8166 X86::LCMPXCHG8, X86::MOV8rr,
8167 X86::NOT8r, X86::AL,
8168 X86::GR8RegisterClass);
8170 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
8171 X86::XOR8ri, X86::MOV8rm,
8172 X86::LCMPXCHG8, X86::MOV8rr,
8173 X86::NOT8r, X86::AL,
8174 X86::GR8RegisterClass);
8175 case X86::ATOMNAND8:
8176 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
8177 X86::AND8ri, X86::MOV8rm,
8178 X86::LCMPXCHG8, X86::MOV8rr,
8179 X86::NOT8r, X86::AL,
8180 X86::GR8RegisterClass, true);
8181 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
8182 // This group is for 64-bit host.
8183 case X86::ATOMAND64:
8184 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8185 X86::AND64ri32, X86::MOV64rm,
8186 X86::LCMPXCHG64, X86::MOV64rr,
8187 X86::NOT64r, X86::RAX,
8188 X86::GR64RegisterClass);
8190 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8191 X86::OR64ri32, X86::MOV64rm,
8192 X86::LCMPXCHG64, X86::MOV64rr,
8193 X86::NOT64r, X86::RAX,
8194 X86::GR64RegisterClass);
8195 case X86::ATOMXOR64:
8196 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8197 X86::XOR64ri32, X86::MOV64rm,
8198 X86::LCMPXCHG64, X86::MOV64rr,
8199 X86::NOT64r, X86::RAX,
8200 X86::GR64RegisterClass);
8201 case X86::ATOMNAND64:
8202 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8203 X86::AND64ri32, X86::MOV64rm,
8204 X86::LCMPXCHG64, X86::MOV64rr,
8205 X86::NOT64r, X86::RAX,
8206 X86::GR64RegisterClass, true);
8207 case X86::ATOMMIN64:
8208 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8209 case X86::ATOMMAX64:
8210 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8211 case X86::ATOMUMIN64:
8212 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8213 case X86::ATOMUMAX64:
8214 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8216 // This group does 64-bit operations on a 32-bit host.
8217 case X86::ATOMAND6432:
8218 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8219 X86::AND32rr, X86::AND32rr,
8220 X86::AND32ri, X86::AND32ri,
8222 case X86::ATOMOR6432:
8223 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8224 X86::OR32rr, X86::OR32rr,
8225 X86::OR32ri, X86::OR32ri,
8227 case X86::ATOMXOR6432:
8228 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8229 X86::XOR32rr, X86::XOR32rr,
8230 X86::XOR32ri, X86::XOR32ri,
8232 case X86::ATOMNAND6432:
8233 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8234 X86::AND32rr, X86::AND32rr,
8235 X86::AND32ri, X86::AND32ri,
8237 case X86::ATOMADD6432:
8238 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8239 X86::ADD32rr, X86::ADC32rr,
8240 X86::ADD32ri, X86::ADC32ri,
8242 case X86::ATOMSUB6432:
8243 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8244 X86::SUB32rr, X86::SBB32rr,
8245 X86::SUB32ri, X86::SBB32ri,
8247 case X86::ATOMSWAP6432:
8248 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8249 X86::MOV32rr, X86::MOV32rr,
8250 X86::MOV32ri, X86::MOV32ri,
8252 case X86::VASTART_SAVE_XMM_REGS:
8253 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8257 //===----------------------------------------------------------------------===//
8258 // X86 Optimization Hooks
8259 //===----------------------------------------------------------------------===//
8261 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8265 const SelectionDAG &DAG,
8266 unsigned Depth) const {
8267 unsigned Opc = Op.getOpcode();
8268 assert((Opc >= ISD::BUILTIN_OP_END ||
8269 Opc == ISD::INTRINSIC_WO_CHAIN ||
8270 Opc == ISD::INTRINSIC_W_CHAIN ||
8271 Opc == ISD::INTRINSIC_VOID) &&
8272 "Should use MaskedValueIsZero if you don't know whether Op"
8273 " is a target node!");
8275 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8287 // These nodes' second result is a boolean.
8288 if (Op.getResNo() == 0)
8292 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8293 Mask.getBitWidth() - 1);
8298 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8299 /// node is a GlobalAddress + offset.
8300 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8301 GlobalValue* &GA, int64_t &Offset) const{
8302 if (N->getOpcode() == X86ISD::Wrapper) {
8303 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8304 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8305 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8309 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8312 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
8313 const TargetLowering &TLI) {
8316 if (TLI.isGAPlusOffset(Base, GV, Offset))
8317 return (GV->getAlignment() >= N && (Offset % N) == 0);
8318 // DAG combine handles the stack object case.
8322 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8323 EVT EltVT, LoadSDNode *&LDBase,
8324 unsigned &LastLoadedElt,
8325 SelectionDAG &DAG, MachineFrameInfo *MFI,
8326 const TargetLowering &TLI) {
8328 LastLoadedElt = -1U;
8329 for (unsigned i = 0; i < NumElems; ++i) {
8330 if (N->getMaskElt(i) < 0) {
8336 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8337 if (!Elt.getNode() ||
8338 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8341 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8343 LDBase = cast<LoadSDNode>(Elt.getNode());
8347 if (Elt.getOpcode() == ISD::UNDEF)
8350 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8351 if (!TLI.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i, MFI))
8358 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8359 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8360 /// if the load addresses are consecutive, non-overlapping, and in the right
8361 /// order. In the case of v2i64, it will see if it can rewrite the
8362 /// shuffle to be an appropriate build vector so it can take advantage of
8363 // performBuildVectorCombine.
8364 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8365 const TargetLowering &TLI) {
8366 DebugLoc dl = N->getDebugLoc();
8367 EVT VT = N->getValueType(0);
8368 EVT EltVT = VT.getVectorElementType();
8369 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8370 unsigned NumElems = VT.getVectorNumElements();
8372 if (VT.getSizeInBits() != 128)
8375 // Try to combine a vector_shuffle into a 128-bit load.
8376 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8377 LoadSDNode *LD = NULL;
8378 unsigned LastLoadedElt;
8379 if (!EltsFromConsecutiveLoads(SVN, NumElems, EltVT, LD, LastLoadedElt, DAG,
8383 if (LastLoadedElt == NumElems - 1) {
8384 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
8385 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8386 LD->getSrcValue(), LD->getSrcValueOffset(),
8388 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8389 LD->getSrcValue(), LD->getSrcValueOffset(),
8390 LD->isVolatile(), LD->getAlignment());
8391 } else if (NumElems == 4 && LastLoadedElt == 1) {
8392 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8393 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8394 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8395 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8400 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8401 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8402 const X86Subtarget *Subtarget) {
8403 DebugLoc DL = N->getDebugLoc();
8404 SDValue Cond = N->getOperand(0);
8405 // Get the LHS/RHS of the select.
8406 SDValue LHS = N->getOperand(1);
8407 SDValue RHS = N->getOperand(2);
8409 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
8410 // instructions have the peculiarity that if either operand is a NaN,
8411 // they chose what we call the RHS operand (and as such are not symmetric).
8412 // It happens that this matches the semantics of the common C idiom
8413 // x<y?x:y and related forms, so we can recognize these cases.
8414 if (Subtarget->hasSSE2() &&
8415 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8416 Cond.getOpcode() == ISD::SETCC) {
8417 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8419 unsigned Opcode = 0;
8420 // Check for x CC y ? x : y.
8421 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8425 // This can be a min if we can prove that at least one of the operands
8427 if (!FiniteOnlyFPMath()) {
8428 if (DAG.isKnownNeverNaN(RHS)) {
8429 // Put the potential NaN in the RHS so that SSE will preserve it.
8430 std::swap(LHS, RHS);
8431 } else if (!DAG.isKnownNeverNaN(LHS))
8434 Opcode = X86ISD::FMIN;
8437 // This can be a min if we can prove that at least one of the operands
8439 if (!FiniteOnlyFPMath()) {
8440 if (DAG.isKnownNeverNaN(LHS)) {
8441 // Put the potential NaN in the RHS so that SSE will preserve it.
8442 std::swap(LHS, RHS);
8443 } else if (!DAG.isKnownNeverNaN(RHS))
8446 Opcode = X86ISD::FMIN;
8449 // This can be a min, but if either operand is a NaN we need it to
8450 // preserve the original LHS.
8451 std::swap(LHS, RHS);
8455 Opcode = X86ISD::FMIN;
8459 // This can be a max if we can prove that at least one of the operands
8461 if (!FiniteOnlyFPMath()) {
8462 if (DAG.isKnownNeverNaN(LHS)) {
8463 // Put the potential NaN in the RHS so that SSE will preserve it.
8464 std::swap(LHS, RHS);
8465 } else if (!DAG.isKnownNeverNaN(RHS))
8468 Opcode = X86ISD::FMAX;
8471 // This can be a max if we can prove that at least one of the operands
8473 if (!FiniteOnlyFPMath()) {
8474 if (DAG.isKnownNeverNaN(RHS)) {
8475 // Put the potential NaN in the RHS so that SSE will preserve it.
8476 std::swap(LHS, RHS);
8477 } else if (!DAG.isKnownNeverNaN(LHS))
8480 Opcode = X86ISD::FMAX;
8483 // This can be a max, but if either operand is a NaN we need it to
8484 // preserve the original LHS.
8485 std::swap(LHS, RHS);
8489 Opcode = X86ISD::FMAX;
8492 // Check for x CC y ? y : x -- a min/max with reversed arms.
8493 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8497 // This can be a min if we can prove that at least one of the operands
8499 if (!FiniteOnlyFPMath()) {
8500 if (DAG.isKnownNeverNaN(RHS)) {
8501 // Put the potential NaN in the RHS so that SSE will preserve it.
8502 std::swap(LHS, RHS);
8503 } else if (!DAG.isKnownNeverNaN(LHS))
8506 Opcode = X86ISD::FMIN;
8509 // This can be a min if we can prove that at least one of the operands
8511 if (!FiniteOnlyFPMath()) {
8512 if (DAG.isKnownNeverNaN(LHS)) {
8513 // Put the potential NaN in the RHS so that SSE will preserve it.
8514 std::swap(LHS, RHS);
8515 } else if (!DAG.isKnownNeverNaN(RHS))
8518 Opcode = X86ISD::FMIN;
8521 // This can be a min, but if either operand is a NaN we need it to
8522 // preserve the original LHS.
8523 std::swap(LHS, RHS);
8527 Opcode = X86ISD::FMIN;
8531 // This can be a max if we can prove that at least one of the operands
8533 if (!FiniteOnlyFPMath()) {
8534 if (DAG.isKnownNeverNaN(LHS)) {
8535 // Put the potential NaN in the RHS so that SSE will preserve it.
8536 std::swap(LHS, RHS);
8537 } else if (!DAG.isKnownNeverNaN(RHS))
8540 Opcode = X86ISD::FMAX;
8543 // This can be a max if we can prove that at least one of the operands
8545 if (!FiniteOnlyFPMath()) {
8546 if (DAG.isKnownNeverNaN(RHS)) {
8547 // Put the potential NaN in the RHS so that SSE will preserve it.
8548 std::swap(LHS, RHS);
8549 } else if (!DAG.isKnownNeverNaN(LHS))
8552 Opcode = X86ISD::FMAX;
8555 // This can be a max, but if either operand is a NaN we need it to
8556 // preserve the original LHS.
8557 std::swap(LHS, RHS);
8561 Opcode = X86ISD::FMAX;
8567 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8570 // If this is a select between two integer constants, try to do some
8572 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8573 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8574 // Don't do this for crazy integer types.
8575 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8576 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8577 // so that TrueC (the true value) is larger than FalseC.
8578 bool NeedsCondInvert = false;
8580 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8581 // Efficiently invertible.
8582 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8583 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8584 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8585 NeedsCondInvert = true;
8586 std::swap(TrueC, FalseC);
8589 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8590 if (FalseC->getAPIntValue() == 0 &&
8591 TrueC->getAPIntValue().isPowerOf2()) {
8592 if (NeedsCondInvert) // Invert the condition if needed.
8593 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8594 DAG.getConstant(1, Cond.getValueType()));
8596 // Zero extend the condition if needed.
8597 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8599 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8600 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8601 DAG.getConstant(ShAmt, MVT::i8));
8604 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8605 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8606 if (NeedsCondInvert) // Invert the condition if needed.
8607 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8608 DAG.getConstant(1, Cond.getValueType()));
8610 // Zero extend the condition if needed.
8611 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8612 FalseC->getValueType(0), Cond);
8613 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8614 SDValue(FalseC, 0));
8617 // Optimize cases that will turn into an LEA instruction. This requires
8618 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8619 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8620 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8621 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8623 bool isFastMultiplier = false;
8625 switch ((unsigned char)Diff) {
8627 case 1: // result = add base, cond
8628 case 2: // result = lea base( , cond*2)
8629 case 3: // result = lea base(cond, cond*2)
8630 case 4: // result = lea base( , cond*4)
8631 case 5: // result = lea base(cond, cond*4)
8632 case 8: // result = lea base( , cond*8)
8633 case 9: // result = lea base(cond, cond*8)
8634 isFastMultiplier = true;
8639 if (isFastMultiplier) {
8640 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8641 if (NeedsCondInvert) // Invert the condition if needed.
8642 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8643 DAG.getConstant(1, Cond.getValueType()));
8645 // Zero extend the condition if needed.
8646 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8648 // Scale the condition by the difference.
8650 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8651 DAG.getConstant(Diff, Cond.getValueType()));
8653 // Add the base if non-zero.
8654 if (FalseC->getAPIntValue() != 0)
8655 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8656 SDValue(FalseC, 0));
8666 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8667 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8668 TargetLowering::DAGCombinerInfo &DCI) {
8669 DebugLoc DL = N->getDebugLoc();
8671 // If the flag operand isn't dead, don't touch this CMOV.
8672 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8675 // If this is a select between two integer constants, try to do some
8676 // optimizations. Note that the operands are ordered the opposite of SELECT
8678 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8679 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8680 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8681 // larger than FalseC (the false value).
8682 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8684 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8685 CC = X86::GetOppositeBranchCondition(CC);
8686 std::swap(TrueC, FalseC);
8689 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8690 // This is efficient for any integer data type (including i8/i16) and
8692 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8693 SDValue Cond = N->getOperand(3);
8694 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8695 DAG.getConstant(CC, MVT::i8), Cond);
8697 // Zero extend the condition if needed.
8698 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8700 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8701 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8702 DAG.getConstant(ShAmt, MVT::i8));
8703 if (N->getNumValues() == 2) // Dead flag value?
8704 return DCI.CombineTo(N, Cond, SDValue());
8708 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8709 // for any integer data type, including i8/i16.
8710 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8711 SDValue Cond = N->getOperand(3);
8712 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8713 DAG.getConstant(CC, MVT::i8), Cond);
8715 // Zero extend the condition if needed.
8716 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8717 FalseC->getValueType(0), Cond);
8718 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8719 SDValue(FalseC, 0));
8721 if (N->getNumValues() == 2) // Dead flag value?
8722 return DCI.CombineTo(N, Cond, SDValue());
8726 // Optimize cases that will turn into an LEA instruction. This requires
8727 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8728 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8729 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8730 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8732 bool isFastMultiplier = false;
8734 switch ((unsigned char)Diff) {
8736 case 1: // result = add base, cond
8737 case 2: // result = lea base( , cond*2)
8738 case 3: // result = lea base(cond, cond*2)
8739 case 4: // result = lea base( , cond*4)
8740 case 5: // result = lea base(cond, cond*4)
8741 case 8: // result = lea base( , cond*8)
8742 case 9: // result = lea base(cond, cond*8)
8743 isFastMultiplier = true;
8748 if (isFastMultiplier) {
8749 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8750 SDValue Cond = N->getOperand(3);
8751 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8752 DAG.getConstant(CC, MVT::i8), Cond);
8753 // Zero extend the condition if needed.
8754 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8756 // Scale the condition by the difference.
8758 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8759 DAG.getConstant(Diff, Cond.getValueType()));
8761 // Add the base if non-zero.
8762 if (FalseC->getAPIntValue() != 0)
8763 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8764 SDValue(FalseC, 0));
8765 if (N->getNumValues() == 2) // Dead flag value?
8766 return DCI.CombineTo(N, Cond, SDValue());
8776 /// PerformMulCombine - Optimize a single multiply with constant into two
8777 /// in order to implement it with two cheaper instructions, e.g.
8778 /// LEA + SHL, LEA + LEA.
8779 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8780 TargetLowering::DAGCombinerInfo &DCI) {
8781 if (DAG.getMachineFunction().
8782 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8785 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8788 EVT VT = N->getValueType(0);
8792 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8795 uint64_t MulAmt = C->getZExtValue();
8796 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8799 uint64_t MulAmt1 = 0;
8800 uint64_t MulAmt2 = 0;
8801 if ((MulAmt % 9) == 0) {
8803 MulAmt2 = MulAmt / 9;
8804 } else if ((MulAmt % 5) == 0) {
8806 MulAmt2 = MulAmt / 5;
8807 } else if ((MulAmt % 3) == 0) {
8809 MulAmt2 = MulAmt / 3;
8812 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8813 DebugLoc DL = N->getDebugLoc();
8815 if (isPowerOf2_64(MulAmt2) &&
8816 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8817 // If second multiplifer is pow2, issue it first. We want the multiply by
8818 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8820 std::swap(MulAmt1, MulAmt2);
8823 if (isPowerOf2_64(MulAmt1))
8824 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8825 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8827 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8828 DAG.getConstant(MulAmt1, VT));
8830 if (isPowerOf2_64(MulAmt2))
8831 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8832 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8834 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8835 DAG.getConstant(MulAmt2, VT));
8837 // Do not add new nodes to DAG combiner worklist.
8838 DCI.CombineTo(N, NewMul, false);
8844 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8846 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8847 const X86Subtarget *Subtarget) {
8848 // On X86 with SSE2 support, we can transform this to a vector shift if
8849 // all elements are shifted by the same amount. We can't do this in legalize
8850 // because the a constant vector is typically transformed to a constant pool
8851 // so we have no knowledge of the shift amount.
8852 if (!Subtarget->hasSSE2())
8855 EVT VT = N->getValueType(0);
8856 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8859 SDValue ShAmtOp = N->getOperand(1);
8860 EVT EltVT = VT.getVectorElementType();
8861 DebugLoc DL = N->getDebugLoc();
8862 SDValue BaseShAmt = SDValue();
8863 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8864 unsigned NumElts = VT.getVectorNumElements();
8866 for (; i != NumElts; ++i) {
8867 SDValue Arg = ShAmtOp.getOperand(i);
8868 if (Arg.getOpcode() == ISD::UNDEF) continue;
8872 for (; i != NumElts; ++i) {
8873 SDValue Arg = ShAmtOp.getOperand(i);
8874 if (Arg.getOpcode() == ISD::UNDEF) continue;
8875 if (Arg != BaseShAmt) {
8879 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8880 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8881 SDValue InVec = ShAmtOp.getOperand(0);
8882 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8883 unsigned NumElts = InVec.getValueType().getVectorNumElements();
8885 for (; i != NumElts; ++i) {
8886 SDValue Arg = InVec.getOperand(i);
8887 if (Arg.getOpcode() == ISD::UNDEF) continue;
8891 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
8892 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
8893 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
8894 if (C->getZExtValue() == SplatIdx)
8895 BaseShAmt = InVec.getOperand(1);
8898 if (BaseShAmt.getNode() == 0)
8899 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8900 DAG.getIntPtrConstant(0));
8904 // The shift amount is an i32.
8905 if (EltVT.bitsGT(MVT::i32))
8906 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8907 else if (EltVT.bitsLT(MVT::i32))
8908 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
8910 // The shift amount is identical so we can do a vector shift.
8911 SDValue ValOp = N->getOperand(0);
8912 switch (N->getOpcode()) {
8914 llvm_unreachable("Unknown shift opcode!");
8917 if (VT == MVT::v2i64)
8918 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8919 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8921 if (VT == MVT::v4i32)
8922 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8923 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8925 if (VT == MVT::v8i16)
8926 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8927 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8931 if (VT == MVT::v4i32)
8932 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8933 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8935 if (VT == MVT::v8i16)
8936 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8937 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8941 if (VT == MVT::v2i64)
8942 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8943 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8945 if (VT == MVT::v4i32)
8946 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8947 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8949 if (VT == MVT::v8i16)
8950 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8951 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8958 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8959 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8960 const X86Subtarget *Subtarget) {
8961 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8962 // the FP state in cases where an emms may be missing.
8963 // A preferable solution to the general problem is to figure out the right
8964 // places to insert EMMS. This qualifies as a quick hack.
8966 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8967 StoreSDNode *St = cast<StoreSDNode>(N);
8968 EVT VT = St->getValue().getValueType();
8969 if (VT.getSizeInBits() != 64)
8972 const Function *F = DAG.getMachineFunction().getFunction();
8973 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8974 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8975 && Subtarget->hasSSE2();
8976 if ((VT.isVector() ||
8977 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8978 isa<LoadSDNode>(St->getValue()) &&
8979 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8980 St->getChain().hasOneUse() && !St->isVolatile()) {
8981 SDNode* LdVal = St->getValue().getNode();
8983 int TokenFactorIndex = -1;
8984 SmallVector<SDValue, 8> Ops;
8985 SDNode* ChainVal = St->getChain().getNode();
8986 // Must be a store of a load. We currently handle two cases: the load
8987 // is a direct child, and it's under an intervening TokenFactor. It is
8988 // possible to dig deeper under nested TokenFactors.
8989 if (ChainVal == LdVal)
8990 Ld = cast<LoadSDNode>(St->getChain());
8991 else if (St->getValue().hasOneUse() &&
8992 ChainVal->getOpcode() == ISD::TokenFactor) {
8993 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8994 if (ChainVal->getOperand(i).getNode() == LdVal) {
8995 TokenFactorIndex = i;
8996 Ld = cast<LoadSDNode>(St->getValue());
8998 Ops.push_back(ChainVal->getOperand(i));
9002 if (!Ld || !ISD::isNormalLoad(Ld))
9005 // If this is not the MMX case, i.e. we are just turning i64 load/store
9006 // into f64 load/store, avoid the transformation if there are multiple
9007 // uses of the loaded value.
9008 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
9011 DebugLoc LdDL = Ld->getDebugLoc();
9012 DebugLoc StDL = N->getDebugLoc();
9013 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
9014 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
9016 if (Subtarget->is64Bit() || F64IsLegal) {
9017 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
9018 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
9019 Ld->getBasePtr(), Ld->getSrcValue(),
9020 Ld->getSrcValueOffset(), Ld->isVolatile(),
9021 Ld->getAlignment());
9022 SDValue NewChain = NewLd.getValue(1);
9023 if (TokenFactorIndex != -1) {
9024 Ops.push_back(NewChain);
9025 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9028 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
9029 St->getSrcValue(), St->getSrcValueOffset(),
9030 St->isVolatile(), St->getAlignment());
9033 // Otherwise, lower to two pairs of 32-bit loads / stores.
9034 SDValue LoAddr = Ld->getBasePtr();
9035 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
9036 DAG.getConstant(4, MVT::i32));
9038 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
9039 Ld->getSrcValue(), Ld->getSrcValueOffset(),
9040 Ld->isVolatile(), Ld->getAlignment());
9041 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
9042 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
9044 MinAlign(Ld->getAlignment(), 4));
9046 SDValue NewChain = LoLd.getValue(1);
9047 if (TokenFactorIndex != -1) {
9048 Ops.push_back(LoLd);
9049 Ops.push_back(HiLd);
9050 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
9054 LoAddr = St->getBasePtr();
9055 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
9056 DAG.getConstant(4, MVT::i32));
9058 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
9059 St->getSrcValue(), St->getSrcValueOffset(),
9060 St->isVolatile(), St->getAlignment());
9061 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
9063 St->getSrcValueOffset() + 4,
9065 MinAlign(St->getAlignment(), 4));
9066 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
9071 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
9072 /// X86ISD::FXOR nodes.
9073 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
9074 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
9075 // F[X]OR(0.0, x) -> x
9076 // F[X]OR(x, 0.0) -> x
9077 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9078 if (C->getValueAPF().isPosZero())
9079 return N->getOperand(1);
9080 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9081 if (C->getValueAPF().isPosZero())
9082 return N->getOperand(0);
9086 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
9087 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
9088 // FAND(0.0, x) -> 0.0
9089 // FAND(x, 0.0) -> 0.0
9090 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
9091 if (C->getValueAPF().isPosZero())
9092 return N->getOperand(0);
9093 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
9094 if (C->getValueAPF().isPosZero())
9095 return N->getOperand(1);
9099 static SDValue PerformBTCombine(SDNode *N,
9101 TargetLowering::DAGCombinerInfo &DCI) {
9102 // BT ignores high bits in the bit index operand.
9103 SDValue Op1 = N->getOperand(1);
9104 if (Op1.hasOneUse()) {
9105 unsigned BitWidth = Op1.getValueSizeInBits();
9106 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
9107 APInt KnownZero, KnownOne;
9108 TargetLowering::TargetLoweringOpt TLO(DAG);
9109 TargetLowering &TLI = DAG.getTargetLoweringInfo();
9110 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
9111 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
9112 DCI.CommitTargetLoweringOpt(TLO);
9117 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
9118 SDValue Op = N->getOperand(0);
9119 if (Op.getOpcode() == ISD::BIT_CONVERT)
9120 Op = Op.getOperand(0);
9121 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
9122 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
9123 VT.getVectorElementType().getSizeInBits() ==
9124 OpVT.getVectorElementType().getSizeInBits()) {
9125 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
9130 // On X86 and X86-64, atomic operations are lowered to locked instructions.
9131 // Locked instructions, in turn, have implicit fence semantics (all memory
9132 // operations are flushed before issuing the locked instruction, and the
9133 // are not buffered), so we can fold away the common pattern of
9134 // fence-atomic-fence.
9135 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
9136 SDValue atomic = N->getOperand(0);
9137 switch (atomic.getOpcode()) {
9138 case ISD::ATOMIC_CMP_SWAP:
9139 case ISD::ATOMIC_SWAP:
9140 case ISD::ATOMIC_LOAD_ADD:
9141 case ISD::ATOMIC_LOAD_SUB:
9142 case ISD::ATOMIC_LOAD_AND:
9143 case ISD::ATOMIC_LOAD_OR:
9144 case ISD::ATOMIC_LOAD_XOR:
9145 case ISD::ATOMIC_LOAD_NAND:
9146 case ISD::ATOMIC_LOAD_MIN:
9147 case ISD::ATOMIC_LOAD_MAX:
9148 case ISD::ATOMIC_LOAD_UMIN:
9149 case ISD::ATOMIC_LOAD_UMAX:
9155 SDValue fence = atomic.getOperand(0);
9156 if (fence.getOpcode() != ISD::MEMBARRIER)
9159 switch (atomic.getOpcode()) {
9160 case ISD::ATOMIC_CMP_SWAP:
9161 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9162 atomic.getOperand(1), atomic.getOperand(2),
9163 atomic.getOperand(3));
9164 case ISD::ATOMIC_SWAP:
9165 case ISD::ATOMIC_LOAD_ADD:
9166 case ISD::ATOMIC_LOAD_SUB:
9167 case ISD::ATOMIC_LOAD_AND:
9168 case ISD::ATOMIC_LOAD_OR:
9169 case ISD::ATOMIC_LOAD_XOR:
9170 case ISD::ATOMIC_LOAD_NAND:
9171 case ISD::ATOMIC_LOAD_MIN:
9172 case ISD::ATOMIC_LOAD_MAX:
9173 case ISD::ATOMIC_LOAD_UMIN:
9174 case ISD::ATOMIC_LOAD_UMAX:
9175 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
9176 atomic.getOperand(1), atomic.getOperand(2));
9182 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
9183 DAGCombinerInfo &DCI) const {
9184 SelectionDAG &DAG = DCI.DAG;
9185 switch (N->getOpcode()) {
9187 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
9188 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
9189 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
9190 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
9193 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
9194 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
9196 case X86ISD::FOR: return PerformFORCombine(N, DAG);
9197 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
9198 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
9199 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
9200 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
9206 //===----------------------------------------------------------------------===//
9207 // X86 Inline Assembly Support
9208 //===----------------------------------------------------------------------===//
9210 static bool LowerToBSwap(CallInst *CI) {
9211 // FIXME: this should verify that we are targetting a 486 or better. If not,
9212 // we will turn this bswap into something that will be lowered to logical ops
9213 // instead of emitting the bswap asm. For now, we don't support 486 or lower
9214 // so don't worry about this.
9216 // Verify this is a simple bswap.
9217 if (CI->getNumOperands() != 2 ||
9218 CI->getType() != CI->getOperand(1)->getType() ||
9219 !CI->getType()->isInteger())
9222 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9223 if (!Ty || Ty->getBitWidth() % 16 != 0)
9226 // Okay, we can do this xform, do so now.
9227 const Type *Tys[] = { Ty };
9228 Module *M = CI->getParent()->getParent()->getParent();
9229 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
9231 Value *Op = CI->getOperand(1);
9232 Op = CallInst::Create(Int, Op, CI->getName(), CI);
9234 CI->replaceAllUsesWith(Op);
9235 CI->eraseFromParent();
9239 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
9240 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9241 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
9243 std::string AsmStr = IA->getAsmString();
9245 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
9246 std::vector<std::string> AsmPieces;
9247 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
9249 switch (AsmPieces.size()) {
9250 default: return false;
9252 AsmStr = AsmPieces[0];
9254 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
9257 if (AsmPieces.size() == 2 &&
9258 (AsmPieces[0] == "bswap" ||
9259 AsmPieces[0] == "bswapq" ||
9260 AsmPieces[0] == "bswapl") &&
9261 (AsmPieces[1] == "$0" ||
9262 AsmPieces[1] == "${0:q}")) {
9263 // No need to check constraints, nothing other than the equivalent of
9264 // "=r,0" would be valid here.
9265 return LowerToBSwap(CI);
9267 // rorw $$8, ${0:w} --> llvm.bswap.i16
9268 if (CI->getType() == Type::getInt16Ty(CI->getContext()) &&
9269 AsmPieces.size() == 3 &&
9270 AsmPieces[0] == "rorw" &&
9271 AsmPieces[1] == "$$8," &&
9272 AsmPieces[2] == "${0:w}" &&
9273 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9274 return LowerToBSwap(CI);
9278 if (CI->getType() == Type::getInt64Ty(CI->getContext()) &&
9279 Constraints.size() >= 2 &&
9280 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9281 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9282 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9283 std::vector<std::string> Words;
9284 SplitString(AsmPieces[0], Words, " \t");
9285 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9287 SplitString(AsmPieces[1], Words, " \t");
9288 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9290 SplitString(AsmPieces[2], Words, " \t,");
9291 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9292 Words[2] == "%edx") {
9293 return LowerToBSwap(CI);
9305 /// getConstraintType - Given a constraint letter, return the type of
9306 /// constraint it is for this target.
9307 X86TargetLowering::ConstraintType
9308 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9309 if (Constraint.size() == 1) {
9310 switch (Constraint[0]) {
9322 return C_RegisterClass;
9330 return TargetLowering::getConstraintType(Constraint);
9333 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9334 /// with another that has more specific requirements based on the type of the
9335 /// corresponding operand.
9336 const char *X86TargetLowering::
9337 LowerXConstraint(EVT ConstraintVT) const {
9338 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9339 // 'f' like normal targets.
9340 if (ConstraintVT.isFloatingPoint()) {
9341 if (Subtarget->hasSSE2())
9343 if (Subtarget->hasSSE1())
9347 return TargetLowering::LowerXConstraint(ConstraintVT);
9350 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9351 /// vector. If it is invalid, don't add anything to Ops.
9352 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9355 std::vector<SDValue>&Ops,
9356 SelectionDAG &DAG) const {
9357 SDValue Result(0, 0);
9359 switch (Constraint) {
9362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9363 if (C->getZExtValue() <= 31) {
9364 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9371 if (C->getZExtValue() <= 63) {
9372 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9379 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9380 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9387 if (C->getZExtValue() <= 255) {
9388 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9394 // 32-bit signed value
9395 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9396 const ConstantInt *CI = C->getConstantIntValue();
9397 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9398 C->getSExtValue())) {
9399 // Widen to 64 bits here to get it sign extended.
9400 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9403 // FIXME gcc accepts some relocatable values here too, but only in certain
9404 // memory models; it's complicated.
9409 // 32-bit unsigned value
9410 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9411 const ConstantInt *CI = C->getConstantIntValue();
9412 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9413 C->getZExtValue())) {
9414 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9418 // FIXME gcc accepts some relocatable values here too, but only in certain
9419 // memory models; it's complicated.
9423 // Literal immediates are always ok.
9424 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9425 // Widen to 64 bits here to get it sign extended.
9426 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9430 // If we are in non-pic codegen mode, we allow the address of a global (with
9431 // an optional displacement) to be used with 'i'.
9432 GlobalAddressSDNode *GA = 0;
9435 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9437 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9438 Offset += GA->getOffset();
9440 } else if (Op.getOpcode() == ISD::ADD) {
9441 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9442 Offset += C->getZExtValue();
9443 Op = Op.getOperand(0);
9446 } else if (Op.getOpcode() == ISD::SUB) {
9447 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9448 Offset += -C->getZExtValue();
9449 Op = Op.getOperand(0);
9454 // Otherwise, this isn't something we can handle, reject it.
9458 GlobalValue *GV = GA->getGlobal();
9459 // If we require an extra load to get this address, as in PIC mode, we
9461 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9462 getTargetMachine())))
9466 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9468 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9474 if (Result.getNode()) {
9475 Ops.push_back(Result);
9478 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9482 std::vector<unsigned> X86TargetLowering::
9483 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9485 if (Constraint.size() == 1) {
9486 // FIXME: not handling fp-stack yet!
9487 switch (Constraint[0]) { // GCC X86 Constraint Letters
9488 default: break; // Unknown constraint letter
9489 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9490 if (Subtarget->is64Bit()) {
9492 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9493 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9494 X86::R10D,X86::R11D,X86::R12D,
9495 X86::R13D,X86::R14D,X86::R15D,
9496 X86::EBP, X86::ESP, 0);
9497 else if (VT == MVT::i16)
9498 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9499 X86::SI, X86::DI, X86::R8W,X86::R9W,
9500 X86::R10W,X86::R11W,X86::R12W,
9501 X86::R13W,X86::R14W,X86::R15W,
9502 X86::BP, X86::SP, 0);
9503 else if (VT == MVT::i8)
9504 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9505 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9506 X86::R10B,X86::R11B,X86::R12B,
9507 X86::R13B,X86::R14B,X86::R15B,
9508 X86::BPL, X86::SPL, 0);
9510 else if (VT == MVT::i64)
9511 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9512 X86::RSI, X86::RDI, X86::R8, X86::R9,
9513 X86::R10, X86::R11, X86::R12,
9514 X86::R13, X86::R14, X86::R15,
9515 X86::RBP, X86::RSP, 0);
9519 // 32-bit fallthrough
9522 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9523 else if (VT == MVT::i16)
9524 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9525 else if (VT == MVT::i8)
9526 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9527 else if (VT == MVT::i64)
9528 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9533 return std::vector<unsigned>();
9536 std::pair<unsigned, const TargetRegisterClass*>
9537 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9539 // First, see if this is a constraint that directly corresponds to an LLVM
9541 if (Constraint.size() == 1) {
9542 // GCC Constraint Letters
9543 switch (Constraint[0]) {
9545 case 'r': // GENERAL_REGS
9546 case 'l': // INDEX_REGS
9548 return std::make_pair(0U, X86::GR8RegisterClass);
9550 return std::make_pair(0U, X86::GR16RegisterClass);
9551 if (VT == MVT::i32 || !Subtarget->is64Bit())
9552 return std::make_pair(0U, X86::GR32RegisterClass);
9553 return std::make_pair(0U, X86::GR64RegisterClass);
9554 case 'R': // LEGACY_REGS
9556 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
9558 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
9559 if (VT == MVT::i32 || !Subtarget->is64Bit())
9560 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
9561 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
9562 case 'f': // FP Stack registers.
9563 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9564 // value to the correct fpstack register class.
9565 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9566 return std::make_pair(0U, X86::RFP32RegisterClass);
9567 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9568 return std::make_pair(0U, X86::RFP64RegisterClass);
9569 return std::make_pair(0U, X86::RFP80RegisterClass);
9570 case 'y': // MMX_REGS if MMX allowed.
9571 if (!Subtarget->hasMMX()) break;
9572 return std::make_pair(0U, X86::VR64RegisterClass);
9573 case 'Y': // SSE_REGS if SSE2 allowed
9574 if (!Subtarget->hasSSE2()) break;
9576 case 'x': // SSE_REGS if SSE1 allowed
9577 if (!Subtarget->hasSSE1()) break;
9579 switch (VT.getSimpleVT().SimpleTy) {
9581 // Scalar SSE types.
9584 return std::make_pair(0U, X86::FR32RegisterClass);
9587 return std::make_pair(0U, X86::FR64RegisterClass);
9595 return std::make_pair(0U, X86::VR128RegisterClass);
9601 // Use the default implementation in TargetLowering to convert the register
9602 // constraint into a member of a register class.
9603 std::pair<unsigned, const TargetRegisterClass*> Res;
9604 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9606 // Not found as a standard register?
9607 if (Res.second == 0) {
9608 // Map st(0) -> st(7) -> ST0
9609 if (Constraint.size() == 7 && Constraint[0] == '{' &&
9610 tolower(Constraint[1]) == 's' &&
9611 tolower(Constraint[2]) == 't' &&
9612 Constraint[3] == '(' &&
9613 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
9614 Constraint[5] == ')' &&
9615 Constraint[6] == '}') {
9617 Res.first = X86::ST0+Constraint[4]-'0';
9618 Res.second = X86::RFP80RegisterClass;
9622 // GCC allows "st(0)" to be called just plain "st".
9623 if (StringRef("{st}").equals_lower(Constraint)) {
9624 Res.first = X86::ST0;
9625 Res.second = X86::RFP80RegisterClass;
9630 if (StringRef("{flags}").equals_lower(Constraint)) {
9631 Res.first = X86::EFLAGS;
9632 Res.second = X86::CCRRegisterClass;
9636 // 'A' means EAX + EDX.
9637 if (Constraint == "A") {
9638 Res.first = X86::EAX;
9639 Res.second = X86::GR32_ADRegisterClass;
9645 // Otherwise, check to see if this is a register class of the wrong value
9646 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9647 // turn into {ax},{dx}.
9648 if (Res.second->hasType(VT))
9649 return Res; // Correct type already, nothing to do.
9651 // All of the single-register GCC register classes map their values onto
9652 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9653 // really want an 8-bit or 32-bit register, map to the appropriate register
9654 // class and return the appropriate register.
9655 if (Res.second == X86::GR16RegisterClass) {
9656 if (VT == MVT::i8) {
9657 unsigned DestReg = 0;
9658 switch (Res.first) {
9660 case X86::AX: DestReg = X86::AL; break;
9661 case X86::DX: DestReg = X86::DL; break;
9662 case X86::CX: DestReg = X86::CL; break;
9663 case X86::BX: DestReg = X86::BL; break;
9666 Res.first = DestReg;
9667 Res.second = X86::GR8RegisterClass;
9669 } else if (VT == MVT::i32) {
9670 unsigned DestReg = 0;
9671 switch (Res.first) {
9673 case X86::AX: DestReg = X86::EAX; break;
9674 case X86::DX: DestReg = X86::EDX; break;
9675 case X86::CX: DestReg = X86::ECX; break;
9676 case X86::BX: DestReg = X86::EBX; break;
9677 case X86::SI: DestReg = X86::ESI; break;
9678 case X86::DI: DestReg = X86::EDI; break;
9679 case X86::BP: DestReg = X86::EBP; break;
9680 case X86::SP: DestReg = X86::ESP; break;
9683 Res.first = DestReg;
9684 Res.second = X86::GR32RegisterClass;
9686 } else if (VT == MVT::i64) {
9687 unsigned DestReg = 0;
9688 switch (Res.first) {
9690 case X86::AX: DestReg = X86::RAX; break;
9691 case X86::DX: DestReg = X86::RDX; break;
9692 case X86::CX: DestReg = X86::RCX; break;
9693 case X86::BX: DestReg = X86::RBX; break;
9694 case X86::SI: DestReg = X86::RSI; break;
9695 case X86::DI: DestReg = X86::RDI; break;
9696 case X86::BP: DestReg = X86::RBP; break;
9697 case X86::SP: DestReg = X86::RSP; break;
9700 Res.first = DestReg;
9701 Res.second = X86::GR64RegisterClass;
9704 } else if (Res.second == X86::FR32RegisterClass ||
9705 Res.second == X86::FR64RegisterClass ||
9706 Res.second == X86::VR128RegisterClass) {
9707 // Handle references to XMM physical registers that got mapped into the
9708 // wrong class. This can happen with constraints like {xmm0} where the
9709 // target independent register mapper will just pick the first match it can
9710 // find, ignoring the required type.
9712 Res.second = X86::FR32RegisterClass;
9713 else if (VT == MVT::f64)
9714 Res.second = X86::FR64RegisterClass;
9715 else if (X86::VR128RegisterClass->hasType(VT))
9716 Res.second = X86::VR128RegisterClass;
9722 //===----------------------------------------------------------------------===//
9723 // X86 Widen vector type
9724 //===----------------------------------------------------------------------===//
9726 /// getWidenVectorType: given a vector type, returns the type to widen
9727 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9728 /// If there is no vector type that we want to widen to, returns MVT::Other
9729 /// When and where to widen is target dependent based on the cost of
9730 /// scalarizing vs using the wider vector type.
9732 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9733 assert(VT.isVector());
9734 if (isTypeLegal(VT))
9737 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9738 // type based on element type. This would speed up our search (though
9739 // it may not be worth it since the size of the list is relatively
9741 EVT EltVT = VT.getVectorElementType();
9742 unsigned NElts = VT.getVectorNumElements();
9744 // On X86, it make sense to widen any vector wider than 1
9748 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9749 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9750 EVT SVT = (MVT::SimpleValueType)nVT;
9752 if (isTypeLegal(SVT) &&
9753 SVT.getVectorElementType() == EltVT &&
9754 SVT.getVectorNumElements() > NElts)