1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!TM.Options.UseSoftFloat) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!TM.Options.UseSoftFloat) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!TM.Options.UseSoftFloat) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!TM.Options.UseSoftFloat) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!TM.Options.UseSoftFloat) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
752 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
753 // with -msoft-float, disable use of MMX as well.
754 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
755 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
756 // No operations on x86mmx supported, everything uses intrinsics.
759 // MMX-sized vectors (other than x86mmx) are expected to be expanded
760 // into smaller operations.
761 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
762 setOperationAction(ISD::MULHS, MMXTy, Expand);
763 setOperationAction(ISD::AND, MMXTy, Expand);
764 setOperationAction(ISD::OR, MMXTy, Expand);
765 setOperationAction(ISD::XOR, MMXTy, Expand);
766 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
767 setOperationAction(ISD::SELECT, MMXTy, Expand);
768 setOperationAction(ISD::BITCAST, MMXTy, Expand);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
772 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
773 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
775 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
776 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
777 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
778 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
780 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
781 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
782 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
783 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
785 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
787 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
788 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
791 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
792 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
794 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
795 // registers cannot be used even for integer operations.
796 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
797 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
798 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
799 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
801 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
802 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
803 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
804 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
805 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
806 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
807 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
808 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
809 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
810 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
811 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
812 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
813 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
814 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
815 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
816 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
817 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
818 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
819 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
820 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
822 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
823 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
825 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
826 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
827 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
828 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
831 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
834 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
836 // Only provide customized ctpop vector bit twiddling for vector types we
837 // know to perform better than using the popcnt instructions on each vector
838 // element. If popcnt isn't supported, always provide the custom version.
839 if (!Subtarget->hasPOPCNT()) {
840 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
841 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
844 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
845 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
846 MVT VT = (MVT::SimpleValueType)i;
847 // Do not attempt to custom lower non-power-of-2 vectors
848 if (!isPowerOf2_32(VT.getVectorNumElements()))
850 // Do not attempt to custom lower non-128-bit vectors
851 if (!VT.is128BitVector())
853 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
855 setOperationAction(ISD::VSELECT, VT, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
859 // We support custom legalizing of sext and anyext loads for specific
860 // memory vector types which we can load as a scalar (or sequence of
861 // scalars) and extend in-register to a legal 128-bit vector type. For sext
862 // loads these must work with a single scalar load.
863 for (MVT VT : MVT::integer_vector_valuetypes()) {
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
866 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
884 if (Subtarget->is64Bit()) {
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
889 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
890 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
891 MVT VT = (MVT::SimpleValueType)i;
893 // Do not attempt to promote non-128-bit vectors
894 if (!VT.is128BitVector())
897 setOperationAction(ISD::AND, VT, Promote);
898 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
899 setOperationAction(ISD::OR, VT, Promote);
900 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
901 setOperationAction(ISD::XOR, VT, Promote);
902 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
903 setOperationAction(ISD::LOAD, VT, Promote);
904 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
905 setOperationAction(ISD::SELECT, VT, Promote);
906 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
909 // Custom lower v2i64 and v2f64 selects.
910 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
911 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
912 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
913 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
915 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
916 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
918 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
919 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
920 // As there is no 64-bit GPR available, we need build a special custom
921 // sequence to convert from v2i32 to v2f32.
922 if (!Subtarget->is64Bit())
923 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
925 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
926 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
928 for (MVT VT : MVT::fp_vector_valuetypes())
929 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
931 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
932 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
933 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
936 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
937 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
938 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
939 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
940 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
941 setOperationAction(ISD::FRINT, RoundedTy, Legal);
942 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
945 // FIXME: Do we need to handle scalar-to-vector here?
946 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
948 // We directly match byte blends in the backend as they match the VSELECT
950 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 // SSE41 brings specific instructions for doing vector sign extend even in
953 // cases where we don't have SRA.
954 for (MVT VT : MVT::integer_vector_valuetypes()) {
955 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
956 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
957 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
960 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
961 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
962 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
966 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
968 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
969 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
973 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
975 // i8 and i16 vectors are custom because the source register and source
976 // source memory operand types are not the same width. f32 vectors are
977 // custom since the immediate controlling the insert encodes additional
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
989 // FIXME: these should be Legal, but that's only for the case where
990 // the index is constant. For now custom expand to deal with that.
991 if (Subtarget->is64Bit()) {
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
993 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
997 if (Subtarget->hasSSE2()) {
998 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
999 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1001 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1002 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1004 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1005 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1007 // In the customized shift lowering, the legal cases in AVX2 will be
1009 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1010 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1012 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1013 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1015 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1018 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1019 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1020 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1021 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1022 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1023 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1024 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1026 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1027 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1028 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1030 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1032 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1033 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1034 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1035 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1036 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1041 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1043 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1044 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1045 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1046 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1047 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1048 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1049 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1054 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1056 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1057 // even though v8i16 is a legal type.
1058 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1059 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1060 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1063 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1064 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1066 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1069 for (MVT VT : MVT::fp_vector_valuetypes())
1070 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1072 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1073 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1075 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1076 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1078 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1079 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1081 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1082 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1083 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1084 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1086 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1087 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1088 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1090 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1091 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1092 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1093 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1094 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1095 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1096 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1097 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1098 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1099 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1100 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1101 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1103 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1104 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1105 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1106 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1107 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FMA, MVT::f32, Legal);
1109 setOperationAction(ISD::FMA, MVT::f64, Legal);
1112 if (Subtarget->hasInt256()) {
1113 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1114 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1115 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1116 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1118 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1119 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1120 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1121 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1123 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1124 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1125 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1126 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1128 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1129 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1130 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1131 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1133 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1134 // when we have a 256bit-wide blend with immediate.
1135 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1137 // Only provide customized ctpop vector bit twiddling for vector types we
1138 // know to perform better than using the popcnt instructions on each
1139 // vector element. If popcnt isn't supported, always provide the custom
1141 if (!Subtarget->hasPOPCNT())
1142 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1144 // Custom CTPOP always performs better on natively supported v8i32
1145 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1147 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1148 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1153 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1155 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1160 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1162 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1178 // In the customized shift lowering, the legal cases in AVX2 will be
1180 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1181 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1184 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1186 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1188 // Custom lower several nodes for 256-bit types.
1189 for (MVT VT : MVT::vector_valuetypes()) {
1190 if (VT.getScalarSizeInBits() >= 32) {
1191 setOperationAction(ISD::MLOAD, VT, Legal);
1192 setOperationAction(ISD::MSTORE, VT, Legal);
1194 // Extract subvector is special because the value type
1195 // (result) is 128-bit but the source is 256-bit wide.
1196 if (VT.is128BitVector()) {
1197 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1199 // Do not attempt to custom lower other non-256-bit vectors
1200 if (!VT.is256BitVector())
1203 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1204 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1205 setOperationAction(ISD::VSELECT, VT, Custom);
1206 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1207 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1208 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1209 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1210 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1213 if (Subtarget->hasInt256())
1214 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1217 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1218 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1219 MVT VT = (MVT::SimpleValueType)i;
1221 // Do not attempt to promote non-256-bit vectors
1222 if (!VT.is256BitVector())
1225 setOperationAction(ISD::AND, VT, Promote);
1226 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1227 setOperationAction(ISD::OR, VT, Promote);
1228 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1229 setOperationAction(ISD::XOR, VT, Promote);
1230 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1231 setOperationAction(ISD::LOAD, VT, Promote);
1232 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1233 setOperationAction(ISD::SELECT, VT, Promote);
1234 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1238 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1239 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1240 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1242 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1244 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1245 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1246 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1248 for (MVT VT : MVT::fp_vector_valuetypes())
1249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1251 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1252 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1253 setOperationAction(ISD::XOR, MVT::i1, Legal);
1254 setOperationAction(ISD::OR, MVT::i1, Legal);
1255 setOperationAction(ISD::AND, MVT::i1, Legal);
1256 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1257 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1258 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1259 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1260 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1262 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1263 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1264 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1265 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1266 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1267 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1269 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1270 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1271 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1272 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1273 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1274 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1275 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1276 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1278 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1279 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1280 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1281 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1282 if (Subtarget->is64Bit()) {
1283 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1284 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1285 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1286 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1288 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1289 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1290 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1291 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1292 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1293 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1294 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1295 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1296 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1297 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1298 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1299 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1300 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1301 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1303 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1304 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1305 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1306 if (Subtarget->hasDQI()) {
1307 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1308 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1310 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1311 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1312 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1313 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1314 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1315 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1316 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1317 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1318 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1319 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1320 if (Subtarget->hasDQI()) {
1321 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1322 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1324 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1331 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1332 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1333 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1335 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1336 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1337 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1338 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1339 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1341 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1342 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1344 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1346 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1347 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1348 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1349 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1350 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1351 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1352 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1353 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1354 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1356 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1357 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1359 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1360 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1362 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1365 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1367 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1368 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1370 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1371 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1373 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1374 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1375 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1376 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1377 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1378 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1380 if (Subtarget->hasCDI()) {
1381 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1382 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1384 if (Subtarget->hasDQI()) {
1385 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1386 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1387 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1389 // Custom lower several nodes.
1390 for (MVT VT : MVT::vector_valuetypes()) {
1391 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1392 // Extract subvector is special because the value type
1393 // (result) is 256/128-bit but the source is 512-bit wide.
1394 if (VT.is128BitVector() || VT.is256BitVector()) {
1395 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1397 if (VT.getVectorElementType() == MVT::i1)
1398 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1400 // Do not attempt to custom lower other non-512-bit vectors
1401 if (!VT.is512BitVector())
1404 if ( EltSize >= 32) {
1405 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1406 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1407 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1408 setOperationAction(ISD::VSELECT, VT, Legal);
1409 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1410 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1411 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1412 setOperationAction(ISD::MLOAD, VT, Legal);
1413 setOperationAction(ISD::MSTORE, VT, Legal);
1416 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1417 MVT VT = (MVT::SimpleValueType)i;
1419 // Do not attempt to promote non-512-bit vectors.
1420 if (!VT.is512BitVector())
1423 setOperationAction(ISD::SELECT, VT, Promote);
1424 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1428 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1429 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1430 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1432 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1433 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1435 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1436 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1437 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1438 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1439 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1440 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1441 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1442 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1443 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1446 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1447 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1449 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1450 const MVT VT = (MVT::SimpleValueType)i;
1452 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1454 // Do not attempt to promote non-512-bit vectors.
1455 if (!VT.is512BitVector())
1459 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1460 setOperationAction(ISD::VSELECT, VT, Legal);
1465 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1466 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1467 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1469 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1470 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1473 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1474 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1479 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1484 // We want to custom lower some of our intrinsics.
1485 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1486 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1487 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1488 if (!Subtarget->is64Bit())
1489 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1491 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1492 // handle type legalization for these operations here.
1494 // FIXME: We really should do custom legalization for addition and
1495 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1496 // than generic legalization for 64-bit multiplication-with-overflow, though.
1497 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1498 // Add/Sub/Mul with overflow operations are custom lowered.
1500 setOperationAction(ISD::SADDO, VT, Custom);
1501 setOperationAction(ISD::UADDO, VT, Custom);
1502 setOperationAction(ISD::SSUBO, VT, Custom);
1503 setOperationAction(ISD::USUBO, VT, Custom);
1504 setOperationAction(ISD::SMULO, VT, Custom);
1505 setOperationAction(ISD::UMULO, VT, Custom);
1509 if (!Subtarget->is64Bit()) {
1510 // These libcalls are not available in 32-bit.
1511 setLibcallName(RTLIB::SHL_I128, nullptr);
1512 setLibcallName(RTLIB::SRL_I128, nullptr);
1513 setLibcallName(RTLIB::SRA_I128, nullptr);
1516 // Combine sin / cos into one node or libcall if possible.
1517 if (Subtarget->hasSinCos()) {
1518 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1519 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1520 if (Subtarget->isTargetDarwin()) {
1521 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1522 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1523 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1524 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1528 if (Subtarget->isTargetWin64()) {
1529 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1530 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1531 setOperationAction(ISD::SREM, MVT::i128, Custom);
1532 setOperationAction(ISD::UREM, MVT::i128, Custom);
1533 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1534 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1537 // We have target-specific dag combine patterns for the following nodes:
1538 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1539 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1540 setTargetDAGCombine(ISD::BITCAST);
1541 setTargetDAGCombine(ISD::VSELECT);
1542 setTargetDAGCombine(ISD::SELECT);
1543 setTargetDAGCombine(ISD::SHL);
1544 setTargetDAGCombine(ISD::SRA);
1545 setTargetDAGCombine(ISD::SRL);
1546 setTargetDAGCombine(ISD::OR);
1547 setTargetDAGCombine(ISD::AND);
1548 setTargetDAGCombine(ISD::ADD);
1549 setTargetDAGCombine(ISD::FADD);
1550 setTargetDAGCombine(ISD::FSUB);
1551 setTargetDAGCombine(ISD::FMA);
1552 setTargetDAGCombine(ISD::SUB);
1553 setTargetDAGCombine(ISD::LOAD);
1554 setTargetDAGCombine(ISD::MLOAD);
1555 setTargetDAGCombine(ISD::STORE);
1556 setTargetDAGCombine(ISD::MSTORE);
1557 setTargetDAGCombine(ISD::ZERO_EXTEND);
1558 setTargetDAGCombine(ISD::ANY_EXTEND);
1559 setTargetDAGCombine(ISD::SIGN_EXTEND);
1560 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1561 setTargetDAGCombine(ISD::TRUNCATE);
1562 setTargetDAGCombine(ISD::SINT_TO_FP);
1563 setTargetDAGCombine(ISD::SETCC);
1564 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1565 setTargetDAGCombine(ISD::BUILD_VECTOR);
1566 setTargetDAGCombine(ISD::MUL);
1567 setTargetDAGCombine(ISD::XOR);
1569 computeRegisterProperties(Subtarget->getRegisterInfo());
1571 // On Darwin, -Os means optimize for size without hurting performance,
1572 // do not reduce the limit.
1573 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1574 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1575 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1576 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1577 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1578 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1579 setPrefLoopAlignment(4); // 2^4 bytes.
1581 // Predictable cmov don't hurt on atom because it's in-order.
1582 PredictableSelectIsExpensive = !Subtarget->isAtom();
1583 EnableExtLdPromotion = true;
1584 setPrefFunctionAlignment(4); // 2^4 bytes.
1586 verifyIntrinsicTables();
1589 // This has so far only been implemented for 64-bit MachO.
1590 bool X86TargetLowering::useLoadStackGuardNode() const {
1591 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1594 TargetLoweringBase::LegalizeTypeAction
1595 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1596 if (ExperimentalVectorWideningLegalization &&
1597 VT.getVectorNumElements() != 1 &&
1598 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1599 return TypeWidenVector;
1601 return TargetLoweringBase::getPreferredVectorAction(VT);
1604 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1606 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1608 const unsigned NumElts = VT.getVectorNumElements();
1609 const EVT EltVT = VT.getVectorElementType();
1610 if (VT.is512BitVector()) {
1611 if (Subtarget->hasAVX512())
1612 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1613 EltVT == MVT::f32 || EltVT == MVT::f64)
1615 case 8: return MVT::v8i1;
1616 case 16: return MVT::v16i1;
1618 if (Subtarget->hasBWI())
1619 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1621 case 32: return MVT::v32i1;
1622 case 64: return MVT::v64i1;
1626 if (VT.is256BitVector() || VT.is128BitVector()) {
1627 if (Subtarget->hasVLX())
1628 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1629 EltVT == MVT::f32 || EltVT == MVT::f64)
1631 case 2: return MVT::v2i1;
1632 case 4: return MVT::v4i1;
1633 case 8: return MVT::v8i1;
1635 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1636 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1638 case 8: return MVT::v8i1;
1639 case 16: return MVT::v16i1;
1640 case 32: return MVT::v32i1;
1644 return VT.changeVectorElementTypeToInteger();
1647 /// Helper for getByValTypeAlignment to determine
1648 /// the desired ByVal argument alignment.
1649 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1652 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1653 if (VTy->getBitWidth() == 128)
1655 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1656 unsigned EltAlign = 0;
1657 getMaxByValAlign(ATy->getElementType(), EltAlign);
1658 if (EltAlign > MaxAlign)
1659 MaxAlign = EltAlign;
1660 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1661 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1662 unsigned EltAlign = 0;
1663 getMaxByValAlign(STy->getElementType(i), EltAlign);
1664 if (EltAlign > MaxAlign)
1665 MaxAlign = EltAlign;
1672 /// Return the desired alignment for ByVal aggregate
1673 /// function arguments in the caller parameter area. For X86, aggregates
1674 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1675 /// are at 4-byte boundaries.
1676 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1677 if (Subtarget->is64Bit()) {
1678 // Max of 8 and alignment of type.
1679 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1686 if (Subtarget->hasSSE1())
1687 getMaxByValAlign(Ty, Align);
1691 /// Returns the target specific optimal type for load
1692 /// and store operations as a result of memset, memcpy, and memmove
1693 /// lowering. If DstAlign is zero that means it's safe to destination
1694 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1695 /// means there isn't a need to check it against alignment requirement,
1696 /// probably because the source does not need to be loaded. If 'IsMemset' is
1697 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1698 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1699 /// source is constant so it does not need to be loaded.
1700 /// It returns EVT::Other if the type should be determined using generic
1701 /// target-independent logic.
1703 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1704 unsigned DstAlign, unsigned SrcAlign,
1705 bool IsMemset, bool ZeroMemset,
1707 MachineFunction &MF) const {
1708 const Function *F = MF.getFunction();
1709 if ((!IsMemset || ZeroMemset) &&
1710 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1712 (Subtarget->isUnalignedMemAccessFast() ||
1713 ((DstAlign == 0 || DstAlign >= 16) &&
1714 (SrcAlign == 0 || SrcAlign >= 16)))) {
1716 if (Subtarget->hasInt256())
1718 if (Subtarget->hasFp256())
1721 if (Subtarget->hasSSE2())
1723 if (Subtarget->hasSSE1())
1725 } else if (!MemcpyStrSrc && Size >= 8 &&
1726 !Subtarget->is64Bit() &&
1727 Subtarget->hasSSE2()) {
1728 // Do not use f64 to lower memcpy if source is string constant. It's
1729 // better to use i32 to avoid the loads.
1733 if (Subtarget->is64Bit() && Size >= 8)
1738 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1740 return X86ScalarSSEf32;
1741 else if (VT == MVT::f64)
1742 return X86ScalarSSEf64;
1747 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1752 *Fast = Subtarget->isUnalignedMemAccessFast();
1756 /// Return the entry encoding for a jump table in the
1757 /// current function. The returned value is a member of the
1758 /// MachineJumpTableInfo::JTEntryKind enum.
1759 unsigned X86TargetLowering::getJumpTableEncoding() const {
1760 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1762 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1763 Subtarget->isPICStyleGOT())
1764 return MachineJumpTableInfo::EK_Custom32;
1766 // Otherwise, use the normal jump table encoding heuristics.
1767 return TargetLowering::getJumpTableEncoding();
1771 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1772 const MachineBasicBlock *MBB,
1773 unsigned uid,MCContext &Ctx) const{
1774 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1775 Subtarget->isPICStyleGOT());
1776 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1778 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1779 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1782 /// Returns relocation base for the given PIC jumptable.
1783 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1784 SelectionDAG &DAG) const {
1785 if (!Subtarget->is64Bit())
1786 // This doesn't have SDLoc associated with it, but is not really the
1787 // same as a Register.
1788 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1792 /// This returns the relocation base for the given PIC jumptable,
1793 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1794 const MCExpr *X86TargetLowering::
1795 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1796 MCContext &Ctx) const {
1797 // X86-64 uses RIP relative addressing based on the jump table label.
1798 if (Subtarget->isPICStyleRIPRel())
1799 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1801 // Otherwise, the reference is relative to the PIC base.
1802 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1805 std::pair<const TargetRegisterClass *, uint8_t>
1806 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1808 const TargetRegisterClass *RRC = nullptr;
1810 switch (VT.SimpleTy) {
1812 return TargetLowering::findRepresentativeClass(TRI, VT);
1813 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1814 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1817 RRC = &X86::VR64RegClass;
1819 case MVT::f32: case MVT::f64:
1820 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1821 case MVT::v4f32: case MVT::v2f64:
1822 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1824 RRC = &X86::VR128RegClass;
1827 return std::make_pair(RRC, Cost);
1830 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1831 unsigned &Offset) const {
1832 if (!Subtarget->isTargetLinux())
1835 if (Subtarget->is64Bit()) {
1836 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1838 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1850 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1851 unsigned DestAS) const {
1852 assert(SrcAS != DestAS && "Expected different address spaces!");
1854 return SrcAS < 256 && DestAS < 256;
1857 //===----------------------------------------------------------------------===//
1858 // Return Value Calling Convention Implementation
1859 //===----------------------------------------------------------------------===//
1861 #include "X86GenCallingConv.inc"
1864 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1865 MachineFunction &MF, bool isVarArg,
1866 const SmallVectorImpl<ISD::OutputArg> &Outs,
1867 LLVMContext &Context) const {
1868 SmallVector<CCValAssign, 16> RVLocs;
1869 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1870 return CCInfo.CheckReturn(Outs, RetCC_X86);
1873 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1874 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1879 X86TargetLowering::LowerReturn(SDValue Chain,
1880 CallingConv::ID CallConv, bool isVarArg,
1881 const SmallVectorImpl<ISD::OutputArg> &Outs,
1882 const SmallVectorImpl<SDValue> &OutVals,
1883 SDLoc dl, SelectionDAG &DAG) const {
1884 MachineFunction &MF = DAG.getMachineFunction();
1885 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1887 SmallVector<CCValAssign, 16> RVLocs;
1888 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1889 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1892 SmallVector<SDValue, 6> RetOps;
1893 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1894 // Operand #1 = Bytes To Pop
1895 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1898 // Copy the result values into the output registers.
1899 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1900 CCValAssign &VA = RVLocs[i];
1901 assert(VA.isRegLoc() && "Can only return in registers!");
1902 SDValue ValToCopy = OutVals[i];
1903 EVT ValVT = ValToCopy.getValueType();
1905 // Promote values to the appropriate types.
1906 if (VA.getLocInfo() == CCValAssign::SExt)
1907 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1908 else if (VA.getLocInfo() == CCValAssign::ZExt)
1909 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1910 else if (VA.getLocInfo() == CCValAssign::AExt) {
1911 if (ValVT.getScalarType() == MVT::i1)
1912 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1914 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1916 else if (VA.getLocInfo() == CCValAssign::BCvt)
1917 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1919 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1920 "Unexpected FP-extend for return value.");
1922 // If this is x86-64, and we disabled SSE, we can't return FP values,
1923 // or SSE or MMX vectors.
1924 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1925 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1926 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1927 report_fatal_error("SSE register return with SSE disabled");
1929 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1930 // llvm-gcc has never done it right and no one has noticed, so this
1931 // should be OK for now.
1932 if (ValVT == MVT::f64 &&
1933 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1934 report_fatal_error("SSE2 register return with SSE2 disabled");
1936 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1937 // the RET instruction and handled by the FP Stackifier.
1938 if (VA.getLocReg() == X86::FP0 ||
1939 VA.getLocReg() == X86::FP1) {
1940 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1941 // change the value to the FP stack register class.
1942 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1943 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1944 RetOps.push_back(ValToCopy);
1945 // Don't emit a copytoreg.
1949 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1950 // which is returned in RAX / RDX.
1951 if (Subtarget->is64Bit()) {
1952 if (ValVT == MVT::x86mmx) {
1953 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1954 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1955 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1957 // If we don't have SSE2 available, convert to v4f32 so the generated
1958 // register is legal.
1959 if (!Subtarget->hasSSE2())
1960 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1965 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1966 Flag = Chain.getValue(1);
1967 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1970 // The x86-64 ABIs require that for returning structs by value we copy
1971 // the sret argument into %rax/%eax (depending on ABI) for the return.
1972 // Win32 requires us to put the sret argument to %eax as well.
1973 // We saved the argument into a virtual register in the entry block,
1974 // so now we copy the value out and into %rax/%eax.
1976 // Checking Function.hasStructRetAttr() here is insufficient because the IR
1977 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
1978 // false, then an sret argument may be implicitly inserted in the SelDAG. In
1979 // either case FuncInfo->setSRetReturnReg() will have been called.
1980 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
1981 assert((Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) &&
1982 "No need for an sret register");
1983 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
1986 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1987 X86::RAX : X86::EAX;
1988 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1989 Flag = Chain.getValue(1);
1991 // RAX/EAX now acts like a return value.
1992 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1995 RetOps[0] = Chain; // Update chain.
1997 // Add the flag if we have it.
1999 RetOps.push_back(Flag);
2001 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2004 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2005 if (N->getNumValues() != 1)
2007 if (!N->hasNUsesOfValue(1, 0))
2010 SDValue TCChain = Chain;
2011 SDNode *Copy = *N->use_begin();
2012 if (Copy->getOpcode() == ISD::CopyToReg) {
2013 // If the copy has a glue operand, we conservatively assume it isn't safe to
2014 // perform a tail call.
2015 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2017 TCChain = Copy->getOperand(0);
2018 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2021 bool HasRet = false;
2022 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2024 if (UI->getOpcode() != X86ISD::RET_FLAG)
2026 // If we are returning more than one value, we can definitely
2027 // not make a tail call see PR19530
2028 if (UI->getNumOperands() > 4)
2030 if (UI->getNumOperands() == 4 &&
2031 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2044 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2045 ISD::NodeType ExtendKind) const {
2047 // TODO: Is this also valid on 32-bit?
2048 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2049 ReturnMVT = MVT::i8;
2051 ReturnMVT = MVT::i32;
2053 EVT MinVT = getRegisterType(Context, ReturnMVT);
2054 return VT.bitsLT(MinVT) ? MinVT : VT;
2057 /// Lower the result values of a call into the
2058 /// appropriate copies out of appropriate physical registers.
2061 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2062 CallingConv::ID CallConv, bool isVarArg,
2063 const SmallVectorImpl<ISD::InputArg> &Ins,
2064 SDLoc dl, SelectionDAG &DAG,
2065 SmallVectorImpl<SDValue> &InVals) const {
2067 // Assign locations to each value returned by this call.
2068 SmallVector<CCValAssign, 16> RVLocs;
2069 bool Is64Bit = Subtarget->is64Bit();
2070 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2072 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2074 // Copy all of the result registers out of their specified physreg.
2075 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2076 CCValAssign &VA = RVLocs[i];
2077 EVT CopyVT = VA.getValVT();
2079 // If this is x86-64, and we disabled SSE, we can't return FP values
2080 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2081 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2082 report_fatal_error("SSE register return with SSE disabled");
2085 // If we prefer to use the value in xmm registers, copy it out as f80 and
2086 // use a truncate to move it from fp stack reg to xmm reg.
2087 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2088 isScalarFPTypeInSSEReg(VA.getValVT()))
2091 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2092 CopyVT, InFlag).getValue(1);
2093 SDValue Val = Chain.getValue(0);
2095 if (CopyVT != VA.getValVT())
2096 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2097 // This truncation won't change the value.
2098 DAG.getIntPtrConstant(1, dl));
2100 InFlag = Chain.getValue(2);
2101 InVals.push_back(Val);
2107 //===----------------------------------------------------------------------===//
2108 // C & StdCall & Fast Calling Convention implementation
2109 //===----------------------------------------------------------------------===//
2110 // StdCall calling convention seems to be standard for many Windows' API
2111 // routines and around. It differs from C calling convention just a little:
2112 // callee should clean up the stack, not caller. Symbols should be also
2113 // decorated in some fancy way :) It doesn't support any vector arguments.
2114 // For info on fast calling convention see Fast Calling Convention (tail call)
2115 // implementation LowerX86_32FastCCCallTo.
2117 /// CallIsStructReturn - Determines whether a call uses struct return
2119 enum StructReturnType {
2124 static StructReturnType
2125 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2127 return NotStructReturn;
2129 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2130 if (!Flags.isSRet())
2131 return NotStructReturn;
2132 if (Flags.isInReg())
2133 return RegStructReturn;
2134 return StackStructReturn;
2137 /// Determines whether a function uses struct return semantics.
2138 static StructReturnType
2139 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2141 return NotStructReturn;
2143 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2144 if (!Flags.isSRet())
2145 return NotStructReturn;
2146 if (Flags.isInReg())
2147 return RegStructReturn;
2148 return StackStructReturn;
2151 /// Make a copy of an aggregate at address specified by "Src" to address
2152 /// "Dst" with size and alignment information specified by the specific
2153 /// parameter attribute. The copy will be passed as a byval function parameter.
2155 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2156 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2158 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2160 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2161 /*isVolatile*/false, /*AlwaysInline=*/true,
2162 /*isTailCall*/false,
2163 MachinePointerInfo(), MachinePointerInfo());
2166 /// Return true if the calling convention is one that
2167 /// supports tail call optimization.
2168 static bool IsTailCallConvention(CallingConv::ID CC) {
2169 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2170 CC == CallingConv::HiPE);
2173 /// \brief Return true if the calling convention is a C calling convention.
2174 static bool IsCCallConvention(CallingConv::ID CC) {
2175 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2176 CC == CallingConv::X86_64_SysV);
2179 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2180 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2184 CallingConv::ID CalleeCC = CS.getCallingConv();
2185 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2191 /// Return true if the function is being made into
2192 /// a tailcall target by changing its ABI.
2193 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2194 bool GuaranteedTailCallOpt) {
2195 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2199 X86TargetLowering::LowerMemArgument(SDValue Chain,
2200 CallingConv::ID CallConv,
2201 const SmallVectorImpl<ISD::InputArg> &Ins,
2202 SDLoc dl, SelectionDAG &DAG,
2203 const CCValAssign &VA,
2204 MachineFrameInfo *MFI,
2206 // Create the nodes corresponding to a load from this parameter slot.
2207 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2208 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2209 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2210 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2213 // If value is passed by pointer we have address passed instead of the value
2215 if (VA.getLocInfo() == CCValAssign::Indirect)
2216 ValVT = VA.getLocVT();
2218 ValVT = VA.getValVT();
2220 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2221 // changed with more analysis.
2222 // In case of tail call optimization mark all arguments mutable. Since they
2223 // could be overwritten by lowering of arguments in case of a tail call.
2224 if (Flags.isByVal()) {
2225 unsigned Bytes = Flags.getByValSize();
2226 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2227 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2228 return DAG.getFrameIndex(FI, getPointerTy());
2230 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2231 VA.getLocMemOffset(), isImmutable);
2232 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2233 return DAG.getLoad(ValVT, dl, Chain, FIN,
2234 MachinePointerInfo::getFixedStack(FI),
2235 false, false, false, 0);
2239 // FIXME: Get this from tablegen.
2240 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2241 const X86Subtarget *Subtarget) {
2242 assert(Subtarget->is64Bit());
2244 if (Subtarget->isCallingConvWin64(CallConv)) {
2245 static const MCPhysReg GPR64ArgRegsWin64[] = {
2246 X86::RCX, X86::RDX, X86::R8, X86::R9
2248 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2251 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2252 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2254 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2257 // FIXME: Get this from tablegen.
2258 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2259 CallingConv::ID CallConv,
2260 const X86Subtarget *Subtarget) {
2261 assert(Subtarget->is64Bit());
2262 if (Subtarget->isCallingConvWin64(CallConv)) {
2263 // The XMM registers which might contain var arg parameters are shadowed
2264 // in their paired GPR. So we only need to save the GPR to their home
2266 // TODO: __vectorcall will change this.
2270 const Function *Fn = MF.getFunction();
2271 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2272 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2273 "SSE register cannot be used when SSE is disabled!");
2274 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2275 !Subtarget->hasSSE1())
2276 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2280 static const MCPhysReg XMMArgRegs64Bit[] = {
2281 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2282 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2284 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2288 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2289 CallingConv::ID CallConv,
2291 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SmallVectorImpl<SDValue> &InVals)
2296 MachineFunction &MF = DAG.getMachineFunction();
2297 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2298 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2300 const Function* Fn = MF.getFunction();
2301 if (Fn->hasExternalLinkage() &&
2302 Subtarget->isTargetCygMing() &&
2303 Fn->getName() == "main")
2304 FuncInfo->setForceFramePointer(true);
2306 MachineFrameInfo *MFI = MF.getFrameInfo();
2307 bool Is64Bit = Subtarget->is64Bit();
2308 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2310 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2311 "Var args not supported with calling convention fastcc, ghc or hipe");
2313 // Assign locations to all of the incoming arguments.
2314 SmallVector<CCValAssign, 16> ArgLocs;
2315 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2317 // Allocate shadow area for Win64
2319 CCInfo.AllocateStack(32, 8);
2321 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2323 unsigned LastVal = ~0U;
2325 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2326 CCValAssign &VA = ArgLocs[i];
2327 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2329 assert(VA.getValNo() != LastVal &&
2330 "Don't support value assigned to multiple locs yet");
2332 LastVal = VA.getValNo();
2334 if (VA.isRegLoc()) {
2335 EVT RegVT = VA.getLocVT();
2336 const TargetRegisterClass *RC;
2337 if (RegVT == MVT::i32)
2338 RC = &X86::GR32RegClass;
2339 else if (Is64Bit && RegVT == MVT::i64)
2340 RC = &X86::GR64RegClass;
2341 else if (RegVT == MVT::f32)
2342 RC = &X86::FR32RegClass;
2343 else if (RegVT == MVT::f64)
2344 RC = &X86::FR64RegClass;
2345 else if (RegVT.is512BitVector())
2346 RC = &X86::VR512RegClass;
2347 else if (RegVT.is256BitVector())
2348 RC = &X86::VR256RegClass;
2349 else if (RegVT.is128BitVector())
2350 RC = &X86::VR128RegClass;
2351 else if (RegVT == MVT::x86mmx)
2352 RC = &X86::VR64RegClass;
2353 else if (RegVT == MVT::i1)
2354 RC = &X86::VK1RegClass;
2355 else if (RegVT == MVT::v8i1)
2356 RC = &X86::VK8RegClass;
2357 else if (RegVT == MVT::v16i1)
2358 RC = &X86::VK16RegClass;
2359 else if (RegVT == MVT::v32i1)
2360 RC = &X86::VK32RegClass;
2361 else if (RegVT == MVT::v64i1)
2362 RC = &X86::VK64RegClass;
2364 llvm_unreachable("Unknown argument type!");
2366 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2367 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2369 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2370 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2372 if (VA.getLocInfo() == CCValAssign::SExt)
2373 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2374 DAG.getValueType(VA.getValVT()));
2375 else if (VA.getLocInfo() == CCValAssign::ZExt)
2376 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2377 DAG.getValueType(VA.getValVT()));
2378 else if (VA.getLocInfo() == CCValAssign::BCvt)
2379 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2381 if (VA.isExtInLoc()) {
2382 // Handle MMX values passed in XMM regs.
2383 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2384 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2386 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2389 assert(VA.isMemLoc());
2390 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2393 // If value is passed via pointer - do a load.
2394 if (VA.getLocInfo() == CCValAssign::Indirect)
2395 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2396 MachinePointerInfo(), false, false, false, 0);
2398 InVals.push_back(ArgValue);
2401 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2402 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2403 // The x86-64 ABIs require that for returning structs by value we copy
2404 // the sret argument into %rax/%eax (depending on ABI) for the return.
2405 // Win32 requires us to put the sret argument to %eax as well.
2406 // Save the argument into a virtual register so that we can access it
2407 // from the return points.
2408 if (Ins[i].Flags.isSRet()) {
2409 unsigned Reg = FuncInfo->getSRetReturnReg();
2411 MVT PtrTy = getPointerTy();
2412 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2413 FuncInfo->setSRetReturnReg(Reg);
2415 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2416 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2422 unsigned StackSize = CCInfo.getNextStackOffset();
2423 // Align stack specially for tail calls.
2424 if (FuncIsMadeTailCallSafe(CallConv,
2425 MF.getTarget().Options.GuaranteedTailCallOpt))
2426 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2428 // If the function takes variable number of arguments, make a frame index for
2429 // the start of the first vararg value... for expansion of llvm.va_start. We
2430 // can skip this if there are no va_start calls.
2431 if (MFI->hasVAStart() &&
2432 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2433 CallConv != CallingConv::X86_ThisCall))) {
2434 FuncInfo->setVarArgsFrameIndex(
2435 MFI->CreateFixedObject(1, StackSize, true));
2438 MachineModuleInfo &MMI = MF.getMMI();
2439 const Function *WinEHParent = nullptr;
2440 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2441 WinEHParent = MMI.getWinEHParent(Fn);
2442 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2443 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2445 // Figure out if XMM registers are in use.
2446 assert(!(MF.getTarget().Options.UseSoftFloat &&
2447 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2448 "SSE register cannot be used when SSE is disabled!");
2450 // 64-bit calling conventions support varargs and register parameters, so we
2451 // have to do extra work to spill them in the prologue.
2452 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2453 // Find the first unallocated argument registers.
2454 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2455 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2456 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2457 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2458 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2459 "SSE register cannot be used when SSE is disabled!");
2461 // Gather all the live in physical registers.
2462 SmallVector<SDValue, 6> LiveGPRs;
2463 SmallVector<SDValue, 8> LiveXMMRegs;
2465 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2466 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2468 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2470 if (!ArgXMMs.empty()) {
2471 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2472 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2473 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2474 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2475 LiveXMMRegs.push_back(
2476 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2481 // Get to the caller-allocated home save location. Add 8 to account
2482 // for the return address.
2483 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2484 FuncInfo->setRegSaveFrameIndex(
2485 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2486 // Fixup to set vararg frame on shadow area (4 x i64).
2488 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2490 // For X86-64, if there are vararg parameters that are passed via
2491 // registers, then we must store them to their spots on the stack so
2492 // they may be loaded by deferencing the result of va_next.
2493 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2494 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2495 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2496 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2499 // Store the integer parameter registers.
2500 SmallVector<SDValue, 8> MemOps;
2501 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2503 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2504 for (SDValue Val : LiveGPRs) {
2505 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2506 DAG.getIntPtrConstant(Offset, dl));
2508 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2509 MachinePointerInfo::getFixedStack(
2510 FuncInfo->getRegSaveFrameIndex(), Offset),
2512 MemOps.push_back(Store);
2516 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2517 // Now store the XMM (fp + vector) parameter registers.
2518 SmallVector<SDValue, 12> SaveXMMOps;
2519 SaveXMMOps.push_back(Chain);
2520 SaveXMMOps.push_back(ALVal);
2521 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2522 FuncInfo->getRegSaveFrameIndex(), dl));
2523 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2524 FuncInfo->getVarArgsFPOffset(), dl));
2525 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2527 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2528 MVT::Other, SaveXMMOps));
2531 if (!MemOps.empty())
2532 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2533 } else if (IsWinEHOutlined) {
2534 // Get to the caller-allocated home save location. Add 8 to account
2535 // for the return address.
2536 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2537 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2538 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2540 MMI.getWinEHFuncInfo(Fn)
2541 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2542 FuncInfo->getRegSaveFrameIndex();
2544 // Store the second integer parameter (rdx) into rsp+16 relative to the
2545 // stack pointer at the entry of the function.
2547 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2548 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2549 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2550 Chain = DAG.getStore(
2551 Val.getValue(1), dl, Val, RSFIN,
2552 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2553 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2556 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2557 // Find the largest legal vector type.
2558 MVT VecVT = MVT::Other;
2559 // FIXME: Only some x86_32 calling conventions support AVX512.
2560 if (Subtarget->hasAVX512() &&
2561 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2562 CallConv == CallingConv::Intel_OCL_BI)))
2563 VecVT = MVT::v16f32;
2564 else if (Subtarget->hasAVX())
2566 else if (Subtarget->hasSSE2())
2569 // We forward some GPRs and some vector types.
2570 SmallVector<MVT, 2> RegParmTypes;
2571 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2572 RegParmTypes.push_back(IntVT);
2573 if (VecVT != MVT::Other)
2574 RegParmTypes.push_back(VecVT);
2576 // Compute the set of forwarded registers. The rest are scratch.
2577 SmallVectorImpl<ForwardedRegister> &Forwards =
2578 FuncInfo->getForwardedMustTailRegParms();
2579 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2581 // Conservatively forward AL on x86_64, since it might be used for varargs.
2582 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2583 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2584 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2587 // Copy all forwards from physical to virtual registers.
2588 for (ForwardedRegister &F : Forwards) {
2589 // FIXME: Can we use a less constrained schedule?
2590 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2591 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2592 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2596 // Some CCs need callee pop.
2597 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2598 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2599 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2601 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2602 // If this is an sret function, the return should pop the hidden pointer.
2603 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2604 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2605 argsAreStructReturn(Ins) == StackStructReturn)
2606 FuncInfo->setBytesToPopOnReturn(4);
2610 // RegSaveFrameIndex is X86-64 only.
2611 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2612 if (CallConv == CallingConv::X86_FastCall ||
2613 CallConv == CallingConv::X86_ThisCall)
2614 // fastcc functions can't have varargs.
2615 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2618 FuncInfo->setArgumentStackSize(StackSize);
2620 if (IsWinEHParent) {
2621 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2622 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2623 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2624 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2625 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2626 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2627 /*isVolatile=*/true,
2628 /*isNonTemporal=*/false, /*Alignment=*/0);
2635 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2636 SDValue StackPtr, SDValue Arg,
2637 SDLoc dl, SelectionDAG &DAG,
2638 const CCValAssign &VA,
2639 ISD::ArgFlagsTy Flags) const {
2640 unsigned LocMemOffset = VA.getLocMemOffset();
2641 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2642 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2643 if (Flags.isByVal())
2644 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2646 return DAG.getStore(Chain, dl, Arg, PtrOff,
2647 MachinePointerInfo::getStack(LocMemOffset),
2651 /// Emit a load of return address if tail call
2652 /// optimization is performed and it is required.
2654 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2655 SDValue &OutRetAddr, SDValue Chain,
2656 bool IsTailCall, bool Is64Bit,
2657 int FPDiff, SDLoc dl) const {
2658 // Adjust the Return address stack slot.
2659 EVT VT = getPointerTy();
2660 OutRetAddr = getReturnAddressFrameIndex(DAG);
2662 // Load the "old" Return address.
2663 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2664 false, false, false, 0);
2665 return SDValue(OutRetAddr.getNode(), 1);
2668 /// Emit a store of the return address if tail call
2669 /// optimization is performed and it is required (FPDiff!=0).
2670 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2671 SDValue Chain, SDValue RetAddrFrIdx,
2672 EVT PtrVT, unsigned SlotSize,
2673 int FPDiff, SDLoc dl) {
2674 // Store the return address to the appropriate stack slot.
2675 if (!FPDiff) return Chain;
2676 // Calculate the new stack slot for the return address.
2677 int NewReturnAddrFI =
2678 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2680 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2681 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2682 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2688 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2689 SmallVectorImpl<SDValue> &InVals) const {
2690 SelectionDAG &DAG = CLI.DAG;
2692 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2693 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2694 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2695 SDValue Chain = CLI.Chain;
2696 SDValue Callee = CLI.Callee;
2697 CallingConv::ID CallConv = CLI.CallConv;
2698 bool &isTailCall = CLI.IsTailCall;
2699 bool isVarArg = CLI.IsVarArg;
2701 MachineFunction &MF = DAG.getMachineFunction();
2702 bool Is64Bit = Subtarget->is64Bit();
2703 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2704 StructReturnType SR = callIsStructReturn(Outs);
2705 bool IsSibcall = false;
2706 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2708 if (MF.getTarget().Options.DisableTailCalls)
2711 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2713 // Force this to be a tail call. The verifier rules are enough to ensure
2714 // that we can lower this successfully without moving the return address
2717 } else if (isTailCall) {
2718 // Check if it's really possible to do a tail call.
2719 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2720 isVarArg, SR != NotStructReturn,
2721 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2722 Outs, OutVals, Ins, DAG);
2724 // Sibcalls are automatically detected tailcalls which do not require
2726 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2733 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2734 "Var args not supported with calling convention fastcc, ghc or hipe");
2736 // Analyze operands of the call, assigning locations to each operand.
2737 SmallVector<CCValAssign, 16> ArgLocs;
2738 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2740 // Allocate shadow area for Win64
2742 CCInfo.AllocateStack(32, 8);
2744 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2746 // Get a count of how many bytes are to be pushed on the stack.
2747 unsigned NumBytes = CCInfo.getNextStackOffset();
2749 // This is a sibcall. The memory operands are available in caller's
2750 // own caller's stack.
2752 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2753 IsTailCallConvention(CallConv))
2754 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2757 if (isTailCall && !IsSibcall && !IsMustTail) {
2758 // Lower arguments at fp - stackoffset + fpdiff.
2759 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2761 FPDiff = NumBytesCallerPushed - NumBytes;
2763 // Set the delta of movement of the returnaddr stackslot.
2764 // But only set if delta is greater than previous delta.
2765 if (FPDiff < X86Info->getTCReturnAddrDelta())
2766 X86Info->setTCReturnAddrDelta(FPDiff);
2769 unsigned NumBytesToPush = NumBytes;
2770 unsigned NumBytesToPop = NumBytes;
2772 // If we have an inalloca argument, all stack space has already been allocated
2773 // for us and be right at the top of the stack. We don't support multiple
2774 // arguments passed in memory when using inalloca.
2775 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2777 if (!ArgLocs.back().isMemLoc())
2778 report_fatal_error("cannot use inalloca attribute on a register "
2780 if (ArgLocs.back().getLocMemOffset() != 0)
2781 report_fatal_error("any parameter with the inalloca attribute must be "
2782 "the only memory argument");
2786 Chain = DAG.getCALLSEQ_START(
2787 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2789 SDValue RetAddrFrIdx;
2790 // Load return address for tail calls.
2791 if (isTailCall && FPDiff)
2792 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2793 Is64Bit, FPDiff, dl);
2795 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2796 SmallVector<SDValue, 8> MemOpChains;
2799 // Walk the register/memloc assignments, inserting copies/loads. In the case
2800 // of tail call optimization arguments are handle later.
2801 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2802 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2803 // Skip inalloca arguments, they have already been written.
2804 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2805 if (Flags.isInAlloca())
2808 CCValAssign &VA = ArgLocs[i];
2809 EVT RegVT = VA.getLocVT();
2810 SDValue Arg = OutVals[i];
2811 bool isByVal = Flags.isByVal();
2813 // Promote the value if needed.
2814 switch (VA.getLocInfo()) {
2815 default: llvm_unreachable("Unknown loc info!");
2816 case CCValAssign::Full: break;
2817 case CCValAssign::SExt:
2818 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2820 case CCValAssign::ZExt:
2821 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2823 case CCValAssign::AExt:
2824 if (RegVT.is128BitVector()) {
2825 // Special case: passing MMX values in XMM registers.
2826 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2827 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2828 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2830 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2832 case CCValAssign::BCvt:
2833 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2835 case CCValAssign::Indirect: {
2836 // Store the argument.
2837 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2838 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2839 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2840 MachinePointerInfo::getFixedStack(FI),
2847 if (VA.isRegLoc()) {
2848 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2849 if (isVarArg && IsWin64) {
2850 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2851 // shadow reg if callee is a varargs function.
2852 unsigned ShadowReg = 0;
2853 switch (VA.getLocReg()) {
2854 case X86::XMM0: ShadowReg = X86::RCX; break;
2855 case X86::XMM1: ShadowReg = X86::RDX; break;
2856 case X86::XMM2: ShadowReg = X86::R8; break;
2857 case X86::XMM3: ShadowReg = X86::R9; break;
2860 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2862 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2863 assert(VA.isMemLoc());
2864 if (!StackPtr.getNode())
2865 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2867 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2868 dl, DAG, VA, Flags));
2872 if (!MemOpChains.empty())
2873 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2875 if (Subtarget->isPICStyleGOT()) {
2876 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2879 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2880 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2882 // If we are tail calling and generating PIC/GOT style code load the
2883 // address of the callee into ECX. The value in ecx is used as target of
2884 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2885 // for tail calls on PIC/GOT architectures. Normally we would just put the
2886 // address of GOT into ebx and then call target@PLT. But for tail calls
2887 // ebx would be restored (since ebx is callee saved) before jumping to the
2890 // Note: The actual moving to ECX is done further down.
2891 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2892 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2893 !G->getGlobal()->hasProtectedVisibility())
2894 Callee = LowerGlobalAddress(Callee, DAG);
2895 else if (isa<ExternalSymbolSDNode>(Callee))
2896 Callee = LowerExternalSymbol(Callee, DAG);
2900 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2901 // From AMD64 ABI document:
2902 // For calls that may call functions that use varargs or stdargs
2903 // (prototype-less calls or calls to functions containing ellipsis (...) in
2904 // the declaration) %al is used as hidden argument to specify the number
2905 // of SSE registers used. The contents of %al do not need to match exactly
2906 // the number of registers, but must be an ubound on the number of SSE
2907 // registers used and is in the range 0 - 8 inclusive.
2909 // Count the number of XMM registers allocated.
2910 static const MCPhysReg XMMArgRegs[] = {
2911 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2912 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2914 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2915 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2916 && "SSE registers cannot be used when SSE is disabled");
2918 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2919 DAG.getConstant(NumXMMRegs, dl,
2923 if (isVarArg && IsMustTail) {
2924 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2925 for (const auto &F : Forwards) {
2926 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2927 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2931 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2932 // don't need this because the eligibility check rejects calls that require
2933 // shuffling arguments passed in memory.
2934 if (!IsSibcall && isTailCall) {
2935 // Force all the incoming stack arguments to be loaded from the stack
2936 // before any new outgoing arguments are stored to the stack, because the
2937 // outgoing stack slots may alias the incoming argument stack slots, and
2938 // the alias isn't otherwise explicit. This is slightly more conservative
2939 // than necessary, because it means that each store effectively depends
2940 // on every argument instead of just those arguments it would clobber.
2941 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2943 SmallVector<SDValue, 8> MemOpChains2;
2946 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2947 CCValAssign &VA = ArgLocs[i];
2950 assert(VA.isMemLoc());
2951 SDValue Arg = OutVals[i];
2952 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2953 // Skip inalloca arguments. They don't require any work.
2954 if (Flags.isInAlloca())
2956 // Create frame index.
2957 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2958 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2959 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2960 FIN = DAG.getFrameIndex(FI, getPointerTy());
2962 if (Flags.isByVal()) {
2963 // Copy relative to framepointer.
2964 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
2965 if (!StackPtr.getNode())
2966 StackPtr = DAG.getCopyFromReg(Chain, dl,
2967 RegInfo->getStackRegister(),
2969 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2971 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2975 // Store relative to framepointer.
2976 MemOpChains2.push_back(
2977 DAG.getStore(ArgChain, dl, Arg, FIN,
2978 MachinePointerInfo::getFixedStack(FI),
2983 if (!MemOpChains2.empty())
2984 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2986 // Store the return address to the appropriate stack slot.
2987 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2988 getPointerTy(), RegInfo->getSlotSize(),
2992 // Build a sequence of copy-to-reg nodes chained together with token chain
2993 // and flag operands which copy the outgoing args into registers.
2995 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2996 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2997 RegsToPass[i].second, InFlag);
2998 InFlag = Chain.getValue(1);
3001 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3002 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3003 // In the 64-bit large code model, we have to make all calls
3004 // through a register, since the call instruction's 32-bit
3005 // pc-relative offset may not be large enough to hold the whole
3007 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3008 // If the callee is a GlobalAddress node (quite common, every direct call
3009 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3011 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3013 // We should use extra load for direct calls to dllimported functions in
3015 const GlobalValue *GV = G->getGlobal();
3016 if (!GV->hasDLLImportStorageClass()) {
3017 unsigned char OpFlags = 0;
3018 bool ExtraLoad = false;
3019 unsigned WrapperKind = ISD::DELETED_NODE;
3021 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3022 // external symbols most go through the PLT in PIC mode. If the symbol
3023 // has hidden or protected visibility, or if it is static or local, then
3024 // we don't need to use the PLT - we can directly call it.
3025 if (Subtarget->isTargetELF() &&
3026 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3027 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3028 OpFlags = X86II::MO_PLT;
3029 } else if (Subtarget->isPICStyleStubAny() &&
3030 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3031 (!Subtarget->getTargetTriple().isMacOSX() ||
3032 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3033 // PC-relative references to external symbols should go through $stub,
3034 // unless we're building with the leopard linker or later, which
3035 // automatically synthesizes these stubs.
3036 OpFlags = X86II::MO_DARWIN_STUB;
3037 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3038 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3039 // If the function is marked as non-lazy, generate an indirect call
3040 // which loads from the GOT directly. This avoids runtime overhead
3041 // at the cost of eager binding (and one extra byte of encoding).
3042 OpFlags = X86II::MO_GOTPCREL;
3043 WrapperKind = X86ISD::WrapperRIP;
3047 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3048 G->getOffset(), OpFlags);
3050 // Add a wrapper if needed.
3051 if (WrapperKind != ISD::DELETED_NODE)
3052 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3053 // Add extra indirection if needed.
3055 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3056 MachinePointerInfo::getGOT(),
3057 false, false, false, 0);
3059 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3060 unsigned char OpFlags = 0;
3062 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3063 // external symbols should go through the PLT.
3064 if (Subtarget->isTargetELF() &&
3065 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3066 OpFlags = X86II::MO_PLT;
3067 } else if (Subtarget->isPICStyleStubAny() &&
3068 (!Subtarget->getTargetTriple().isMacOSX() ||
3069 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3070 // PC-relative references to external symbols should go through $stub,
3071 // unless we're building with the leopard linker or later, which
3072 // automatically synthesizes these stubs.
3073 OpFlags = X86II::MO_DARWIN_STUB;
3076 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3078 } else if (Subtarget->isTarget64BitILP32() &&
3079 Callee->getValueType(0) == MVT::i32) {
3080 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3081 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3084 // Returns a chain & a flag for retval copy to use.
3085 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3086 SmallVector<SDValue, 8> Ops;
3088 if (!IsSibcall && isTailCall) {
3089 Chain = DAG.getCALLSEQ_END(Chain,
3090 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3091 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3092 InFlag = Chain.getValue(1);
3095 Ops.push_back(Chain);
3096 Ops.push_back(Callee);
3099 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3101 // Add argument registers to the end of the list so that they are known live
3103 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3104 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3105 RegsToPass[i].second.getValueType()));
3107 // Add a register mask operand representing the call-preserved registers.
3108 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3109 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3110 assert(Mask && "Missing call preserved mask for calling convention");
3111 Ops.push_back(DAG.getRegisterMask(Mask));
3113 if (InFlag.getNode())
3114 Ops.push_back(InFlag);
3118 //// If this is the first return lowered for this function, add the regs
3119 //// to the liveout set for the function.
3120 // This isn't right, although it's probably harmless on x86; liveouts
3121 // should be computed from returns not tail calls. Consider a void
3122 // function making a tail call to a function returning int.
3123 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3126 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3127 InFlag = Chain.getValue(1);
3129 // Create the CALLSEQ_END node.
3130 unsigned NumBytesForCalleeToPop;
3131 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3132 DAG.getTarget().Options.GuaranteedTailCallOpt))
3133 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3134 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3135 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3136 SR == StackStructReturn)
3137 // If this is a call to a struct-return function, the callee
3138 // pops the hidden struct pointer, so we have to push it back.
3139 // This is common for Darwin/X86, Linux & Mingw32 targets.
3140 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3141 NumBytesForCalleeToPop = 4;
3143 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3145 // Returns a flag for retval copy to use.
3147 Chain = DAG.getCALLSEQ_END(Chain,
3148 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3149 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3152 InFlag = Chain.getValue(1);
3155 // Handle result values, copying them out of physregs into vregs that we
3157 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3158 Ins, dl, DAG, InVals);
3161 //===----------------------------------------------------------------------===//
3162 // Fast Calling Convention (tail call) implementation
3163 //===----------------------------------------------------------------------===//
3165 // Like std call, callee cleans arguments, convention except that ECX is
3166 // reserved for storing the tail called function address. Only 2 registers are
3167 // free for argument passing (inreg). Tail call optimization is performed
3169 // * tailcallopt is enabled
3170 // * caller/callee are fastcc
3171 // On X86_64 architecture with GOT-style position independent code only local
3172 // (within module) calls are supported at the moment.
3173 // To keep the stack aligned according to platform abi the function
3174 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3175 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3176 // If a tail called function callee has more arguments than the caller the
3177 // caller needs to make sure that there is room to move the RETADDR to. This is
3178 // achieved by reserving an area the size of the argument delta right after the
3179 // original RETADDR, but before the saved framepointer or the spilled registers
3180 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3192 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3193 /// for a 16 byte align requirement.
3195 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3196 SelectionDAG& DAG) const {
3197 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3198 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3199 unsigned StackAlignment = TFI.getStackAlignment();
3200 uint64_t AlignMask = StackAlignment - 1;
3201 int64_t Offset = StackSize;
3202 unsigned SlotSize = RegInfo->getSlotSize();
3203 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3204 // Number smaller than 12 so just add the difference.
3205 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3207 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3208 Offset = ((~AlignMask) & Offset) + StackAlignment +
3209 (StackAlignment-SlotSize);
3214 /// MatchingStackOffset - Return true if the given stack call argument is
3215 /// already available in the same position (relatively) of the caller's
3216 /// incoming argument stack.
3218 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3219 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3220 const X86InstrInfo *TII) {
3221 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3223 if (Arg.getOpcode() == ISD::CopyFromReg) {
3224 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3225 if (!TargetRegisterInfo::isVirtualRegister(VR))
3227 MachineInstr *Def = MRI->getVRegDef(VR);
3230 if (!Flags.isByVal()) {
3231 if (!TII->isLoadFromStackSlot(Def, FI))
3234 unsigned Opcode = Def->getOpcode();
3235 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3236 Opcode == X86::LEA64_32r) &&
3237 Def->getOperand(1).isFI()) {
3238 FI = Def->getOperand(1).getIndex();
3239 Bytes = Flags.getByValSize();
3243 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3244 if (Flags.isByVal())
3245 // ByVal argument is passed in as a pointer but it's now being
3246 // dereferenced. e.g.
3247 // define @foo(%struct.X* %A) {
3248 // tail call @bar(%struct.X* byval %A)
3251 SDValue Ptr = Ld->getBasePtr();
3252 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3255 FI = FINode->getIndex();
3256 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3257 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3258 FI = FINode->getIndex();
3259 Bytes = Flags.getByValSize();
3263 assert(FI != INT_MAX);
3264 if (!MFI->isFixedObjectIndex(FI))
3266 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3269 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3270 /// for tail call optimization. Targets which want to do tail call
3271 /// optimization should implement this function.
3273 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3274 CallingConv::ID CalleeCC,
3276 bool isCalleeStructRet,
3277 bool isCallerStructRet,
3279 const SmallVectorImpl<ISD::OutputArg> &Outs,
3280 const SmallVectorImpl<SDValue> &OutVals,
3281 const SmallVectorImpl<ISD::InputArg> &Ins,
3282 SelectionDAG &DAG) const {
3283 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3286 // If -tailcallopt is specified, make fastcc functions tail-callable.
3287 const MachineFunction &MF = DAG.getMachineFunction();
3288 const Function *CallerF = MF.getFunction();
3290 // If the function return type is x86_fp80 and the callee return type is not,
3291 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3292 // perform a tailcall optimization here.
3293 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3296 CallingConv::ID CallerCC = CallerF->getCallingConv();
3297 bool CCMatch = CallerCC == CalleeCC;
3298 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3299 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3301 // Win64 functions have extra shadow space for argument homing. Don't do the
3302 // sibcall if the caller and callee have mismatched expectations for this
3304 if (IsCalleeWin64 != IsCallerWin64)
3307 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3308 if (IsTailCallConvention(CalleeCC) && CCMatch)
3313 // Look for obvious safe cases to perform tail call optimization that do not
3314 // require ABI changes. This is what gcc calls sibcall.
3316 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3317 // emit a special epilogue.
3318 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3319 if (RegInfo->needsStackRealignment(MF))
3322 // Also avoid sibcall optimization if either caller or callee uses struct
3323 // return semantics.
3324 if (isCalleeStructRet || isCallerStructRet)
3327 // An stdcall/thiscall caller is expected to clean up its arguments; the
3328 // callee isn't going to do that.
3329 // FIXME: this is more restrictive than needed. We could produce a tailcall
3330 // when the stack adjustment matches. For example, with a thiscall that takes
3331 // only one argument.
3332 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3333 CallerCC == CallingConv::X86_ThisCall))
3336 // Do not sibcall optimize vararg calls unless all arguments are passed via
3338 if (isVarArg && !Outs.empty()) {
3340 // Optimizing for varargs on Win64 is unlikely to be safe without
3341 // additional testing.
3342 if (IsCalleeWin64 || IsCallerWin64)
3345 SmallVector<CCValAssign, 16> ArgLocs;
3346 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3349 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3350 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3351 if (!ArgLocs[i].isRegLoc())
3355 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3356 // stack. Therefore, if it's not used by the call it is not safe to optimize
3357 // this into a sibcall.
3358 bool Unused = false;
3359 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3366 SmallVector<CCValAssign, 16> RVLocs;
3367 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3369 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3370 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3371 CCValAssign &VA = RVLocs[i];
3372 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3377 // If the calling conventions do not match, then we'd better make sure the
3378 // results are returned in the same way as what the caller expects.
3380 SmallVector<CCValAssign, 16> RVLocs1;
3381 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3383 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3385 SmallVector<CCValAssign, 16> RVLocs2;
3386 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3388 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3390 if (RVLocs1.size() != RVLocs2.size())
3392 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3393 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3395 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3397 if (RVLocs1[i].isRegLoc()) {
3398 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3401 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3407 // If the callee takes no arguments then go on to check the results of the
3409 if (!Outs.empty()) {
3410 // Check if stack adjustment is needed. For now, do not do this if any
3411 // argument is passed on the stack.
3412 SmallVector<CCValAssign, 16> ArgLocs;
3413 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3416 // Allocate shadow area for Win64
3418 CCInfo.AllocateStack(32, 8);
3420 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3421 if (CCInfo.getNextStackOffset()) {
3422 MachineFunction &MF = DAG.getMachineFunction();
3423 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3426 // Check if the arguments are already laid out in the right way as
3427 // the caller's fixed stack objects.
3428 MachineFrameInfo *MFI = MF.getFrameInfo();
3429 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3430 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3431 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3432 CCValAssign &VA = ArgLocs[i];
3433 SDValue Arg = OutVals[i];
3434 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3435 if (VA.getLocInfo() == CCValAssign::Indirect)
3437 if (!VA.isRegLoc()) {
3438 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3445 // If the tailcall address may be in a register, then make sure it's
3446 // possible to register allocate for it. In 32-bit, the call address can
3447 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3448 // callee-saved registers are restored. These happen to be the same
3449 // registers used to pass 'inreg' arguments so watch out for those.
3450 if (!Subtarget->is64Bit() &&
3451 ((!isa<GlobalAddressSDNode>(Callee) &&
3452 !isa<ExternalSymbolSDNode>(Callee)) ||
3453 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3454 unsigned NumInRegs = 0;
3455 // In PIC we need an extra register to formulate the address computation
3457 unsigned MaxInRegs =
3458 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3460 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3461 CCValAssign &VA = ArgLocs[i];
3464 unsigned Reg = VA.getLocReg();
3467 case X86::EAX: case X86::EDX: case X86::ECX:
3468 if (++NumInRegs == MaxInRegs)
3480 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3481 const TargetLibraryInfo *libInfo) const {
3482 return X86::createFastISel(funcInfo, libInfo);
3485 //===----------------------------------------------------------------------===//
3486 // Other Lowering Hooks
3487 //===----------------------------------------------------------------------===//
3489 static bool MayFoldLoad(SDValue Op) {
3490 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3493 static bool MayFoldIntoStore(SDValue Op) {
3494 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3497 static bool isTargetShuffle(unsigned Opcode) {
3499 default: return false;
3500 case X86ISD::BLENDI:
3501 case X86ISD::PSHUFB:
3502 case X86ISD::PSHUFD:
3503 case X86ISD::PSHUFHW:
3504 case X86ISD::PSHUFLW:
3506 case X86ISD::PALIGNR:
3507 case X86ISD::MOVLHPS:
3508 case X86ISD::MOVLHPD:
3509 case X86ISD::MOVHLPS:
3510 case X86ISD::MOVLPS:
3511 case X86ISD::MOVLPD:
3512 case X86ISD::MOVSHDUP:
3513 case X86ISD::MOVSLDUP:
3514 case X86ISD::MOVDDUP:
3517 case X86ISD::UNPCKL:
3518 case X86ISD::UNPCKH:
3519 case X86ISD::VPERMILPI:
3520 case X86ISD::VPERM2X128:
3521 case X86ISD::VPERMI:
3526 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3527 SDValue V1, unsigned TargetMask,
3528 SelectionDAG &DAG) {
3530 default: llvm_unreachable("Unknown x86 shuffle node");
3531 case X86ISD::PSHUFD:
3532 case X86ISD::PSHUFHW:
3533 case X86ISD::PSHUFLW:
3534 case X86ISD::VPERMILPI:
3535 case X86ISD::VPERMI:
3536 return DAG.getNode(Opc, dl, VT, V1,
3537 DAG.getConstant(TargetMask, dl, MVT::i8));
3541 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3542 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3544 default: llvm_unreachable("Unknown x86 shuffle node");
3545 case X86ISD::MOVLHPS:
3546 case X86ISD::MOVLHPD:
3547 case X86ISD::MOVHLPS:
3548 case X86ISD::MOVLPS:
3549 case X86ISD::MOVLPD:
3552 case X86ISD::UNPCKL:
3553 case X86ISD::UNPCKH:
3554 return DAG.getNode(Opc, dl, VT, V1, V2);
3558 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3559 MachineFunction &MF = DAG.getMachineFunction();
3560 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3561 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3562 int ReturnAddrIndex = FuncInfo->getRAIndex();
3564 if (ReturnAddrIndex == 0) {
3565 // Set up a frame object for the return address.
3566 unsigned SlotSize = RegInfo->getSlotSize();
3567 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3570 FuncInfo->setRAIndex(ReturnAddrIndex);
3573 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3576 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3577 bool hasSymbolicDisplacement) {
3578 // Offset should fit into 32 bit immediate field.
3579 if (!isInt<32>(Offset))
3582 // If we don't have a symbolic displacement - we don't have any extra
3584 if (!hasSymbolicDisplacement)
3587 // FIXME: Some tweaks might be needed for medium code model.
3588 if (M != CodeModel::Small && M != CodeModel::Kernel)
3591 // For small code model we assume that latest object is 16MB before end of 31
3592 // bits boundary. We may also accept pretty large negative constants knowing
3593 // that all objects are in the positive half of address space.
3594 if (M == CodeModel::Small && Offset < 16*1024*1024)
3597 // For kernel code model we know that all object resist in the negative half
3598 // of 32bits address space. We may not accept negative offsets, since they may
3599 // be just off and we may accept pretty large positive ones.
3600 if (M == CodeModel::Kernel && Offset >= 0)
3606 /// isCalleePop - Determines whether the callee is required to pop its
3607 /// own arguments. Callee pop is necessary to support tail calls.
3608 bool X86::isCalleePop(CallingConv::ID CallingConv,
3609 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3610 switch (CallingConv) {
3613 case CallingConv::X86_StdCall:
3614 case CallingConv::X86_FastCall:
3615 case CallingConv::X86_ThisCall:
3617 case CallingConv::Fast:
3618 case CallingConv::GHC:
3619 case CallingConv::HiPE:
3626 /// \brief Return true if the condition is an unsigned comparison operation.
3627 static bool isX86CCUnsigned(unsigned X86CC) {
3629 default: llvm_unreachable("Invalid integer condition!");
3630 case X86::COND_E: return true;
3631 case X86::COND_G: return false;
3632 case X86::COND_GE: return false;
3633 case X86::COND_L: return false;
3634 case X86::COND_LE: return false;
3635 case X86::COND_NE: return true;
3636 case X86::COND_B: return true;
3637 case X86::COND_A: return true;
3638 case X86::COND_BE: return true;
3639 case X86::COND_AE: return true;
3641 llvm_unreachable("covered switch fell through?!");
3644 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3645 /// specific condition code, returning the condition code and the LHS/RHS of the
3646 /// comparison to make.
3647 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3648 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3650 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3651 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3652 // X > -1 -> X == 0, jump !sign.
3653 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3654 return X86::COND_NS;
3656 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3657 // X < 0 -> X == 0, jump on sign.
3660 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3662 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3663 return X86::COND_LE;
3667 switch (SetCCOpcode) {
3668 default: llvm_unreachable("Invalid integer condition!");
3669 case ISD::SETEQ: return X86::COND_E;
3670 case ISD::SETGT: return X86::COND_G;
3671 case ISD::SETGE: return X86::COND_GE;
3672 case ISD::SETLT: return X86::COND_L;
3673 case ISD::SETLE: return X86::COND_LE;
3674 case ISD::SETNE: return X86::COND_NE;
3675 case ISD::SETULT: return X86::COND_B;
3676 case ISD::SETUGT: return X86::COND_A;
3677 case ISD::SETULE: return X86::COND_BE;
3678 case ISD::SETUGE: return X86::COND_AE;
3682 // First determine if it is required or is profitable to flip the operands.
3684 // If LHS is a foldable load, but RHS is not, flip the condition.
3685 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3686 !ISD::isNON_EXTLoad(RHS.getNode())) {
3687 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3688 std::swap(LHS, RHS);
3691 switch (SetCCOpcode) {
3697 std::swap(LHS, RHS);
3701 // On a floating point condition, the flags are set as follows:
3703 // 0 | 0 | 0 | X > Y
3704 // 0 | 0 | 1 | X < Y
3705 // 1 | 0 | 0 | X == Y
3706 // 1 | 1 | 1 | unordered
3707 switch (SetCCOpcode) {
3708 default: llvm_unreachable("Condcode should be pre-legalized away");
3710 case ISD::SETEQ: return X86::COND_E;
3711 case ISD::SETOLT: // flipped
3713 case ISD::SETGT: return X86::COND_A;
3714 case ISD::SETOLE: // flipped
3716 case ISD::SETGE: return X86::COND_AE;
3717 case ISD::SETUGT: // flipped
3719 case ISD::SETLT: return X86::COND_B;
3720 case ISD::SETUGE: // flipped
3722 case ISD::SETLE: return X86::COND_BE;
3724 case ISD::SETNE: return X86::COND_NE;
3725 case ISD::SETUO: return X86::COND_P;
3726 case ISD::SETO: return X86::COND_NP;
3728 case ISD::SETUNE: return X86::COND_INVALID;
3732 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3733 /// code. Current x86 isa includes the following FP cmov instructions:
3734 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3735 static bool hasFPCMov(unsigned X86CC) {
3751 /// isFPImmLegal - Returns true if the target can instruction select the
3752 /// specified FP immediate natively. If false, the legalizer will
3753 /// materialize the FP immediate as a load from a constant pool.
3754 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3755 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3756 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3762 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3763 ISD::LoadExtType ExtTy,
3765 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3766 // relocation target a movq or addq instruction: don't let the load shrink.
3767 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3768 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3769 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3770 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3774 /// \brief Returns true if it is beneficial to convert a load of a constant
3775 /// to just the constant itself.
3776 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3778 assert(Ty->isIntegerTy());
3780 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3781 if (BitSize == 0 || BitSize > 64)
3786 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3787 unsigned Index) const {
3788 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3791 return (Index == 0 || Index == ResVT.getVectorNumElements());
3794 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3795 // Speculate cttz only if we can directly use TZCNT.
3796 return Subtarget->hasBMI();
3799 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3800 // Speculate ctlz only if we can directly use LZCNT.
3801 return Subtarget->hasLZCNT();
3804 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3805 /// the specified range (L, H].
3806 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3807 return (Val < 0) || (Val >= Low && Val < Hi);
3810 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3811 /// specified value.
3812 static bool isUndefOrEqual(int Val, int CmpVal) {
3813 return (Val < 0 || Val == CmpVal);
3816 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3817 /// from position Pos and ending in Pos+Size, falls within the specified
3818 /// sequential range (Low, Low+Size]. or is undef.
3819 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3820 unsigned Pos, unsigned Size, int Low) {
3821 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3822 if (!isUndefOrEqual(Mask[i], Low))
3827 /// isVEXTRACTIndex - Return true if the specified
3828 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3829 /// suitable for instruction that extract 128 or 256 bit vectors
3830 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3831 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3832 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3835 // The index should be aligned on a vecWidth-bit boundary.
3837 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3839 MVT VT = N->getSimpleValueType(0);
3840 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3841 bool Result = (Index * ElSize) % vecWidth == 0;
3846 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3847 /// operand specifies a subvector insert that is suitable for input to
3848 /// insertion of 128 or 256-bit subvectors
3849 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3850 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3851 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3853 // The index should be aligned on a vecWidth-bit boundary.
3855 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3857 MVT VT = N->getSimpleValueType(0);
3858 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3859 bool Result = (Index * ElSize) % vecWidth == 0;
3864 bool X86::isVINSERT128Index(SDNode *N) {
3865 return isVINSERTIndex(N, 128);
3868 bool X86::isVINSERT256Index(SDNode *N) {
3869 return isVINSERTIndex(N, 256);
3872 bool X86::isVEXTRACT128Index(SDNode *N) {
3873 return isVEXTRACTIndex(N, 128);
3876 bool X86::isVEXTRACT256Index(SDNode *N) {
3877 return isVEXTRACTIndex(N, 256);
3880 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3881 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3882 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3883 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3886 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3888 MVT VecVT = N->getOperand(0).getSimpleValueType();
3889 MVT ElVT = VecVT.getVectorElementType();
3891 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3892 return Index / NumElemsPerChunk;
3895 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3896 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3897 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3898 llvm_unreachable("Illegal insert subvector for VINSERT");
3901 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3903 MVT VecVT = N->getSimpleValueType(0);
3904 MVT ElVT = VecVT.getVectorElementType();
3906 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3907 return Index / NumElemsPerChunk;
3910 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3911 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3912 /// and VINSERTI128 instructions.
3913 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3914 return getExtractVEXTRACTImmediate(N, 128);
3917 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3918 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3919 /// and VINSERTI64x4 instructions.
3920 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3921 return getExtractVEXTRACTImmediate(N, 256);
3924 /// getInsertVINSERT128Immediate - Return the appropriate immediate
3925 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3926 /// and VINSERTI128 instructions.
3927 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
3928 return getInsertVINSERTImmediate(N, 128);
3931 /// getInsertVINSERT256Immediate - Return the appropriate immediate
3932 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
3933 /// and VINSERTI64x4 instructions.
3934 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
3935 return getInsertVINSERTImmediate(N, 256);
3938 /// isZero - Returns true if Elt is a constant integer zero
3939 static bool isZero(SDValue V) {
3940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
3941 return C && C->isNullValue();
3944 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3946 bool X86::isZeroNode(SDValue Elt) {
3949 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
3950 return CFP->getValueAPF().isPosZero();
3954 /// getZeroVector - Returns a vector of specified type with all zero elements.
3956 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
3957 SelectionDAG &DAG, SDLoc dl) {
3958 assert(VT.isVector() && "Expected a vector type");
3960 // Always build SSE zero vectors as <4 x i32> bitcasted
3961 // to their dest type. This ensures they get CSE'd.
3963 if (VT.is128BitVector()) { // SSE
3964 if (Subtarget->hasSSE2()) { // SSE2
3965 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
3966 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3968 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
3969 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3971 } else if (VT.is256BitVector()) { // AVX
3972 if (Subtarget->hasInt256()) { // AVX2
3973 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
3974 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3975 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
3977 // 256-bit logic and arithmetic instructions in AVX are all
3978 // floating-point, no support for integer ops. Emit fp zeroed vectors.
3979 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
3980 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3981 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
3983 } else if (VT.is512BitVector()) { // AVX-512
3984 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
3985 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
3986 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3987 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
3988 } else if (VT.getScalarType() == MVT::i1) {
3990 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
3991 && "Unexpected vector type");
3992 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
3993 && "Unexpected vector type");
3994 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
3995 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
3996 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3998 llvm_unreachable("Unexpected vector type");
4000 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4003 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4004 SelectionDAG &DAG, SDLoc dl,
4005 unsigned vectorWidth) {
4006 assert((vectorWidth == 128 || vectorWidth == 256) &&
4007 "Unsupported vector width");
4008 EVT VT = Vec.getValueType();
4009 EVT ElVT = VT.getVectorElementType();
4010 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4011 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4012 VT.getVectorNumElements()/Factor);
4014 // Extract from UNDEF is UNDEF.
4015 if (Vec.getOpcode() == ISD::UNDEF)
4016 return DAG.getUNDEF(ResultVT);
4018 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4019 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4021 // This is the index of the first element of the vectorWidth-bit chunk
4023 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4026 // If the input is a buildvector just emit a smaller one.
4027 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4028 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4029 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4032 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4033 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4036 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4037 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4038 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4039 /// instructions or a simple subregister reference. Idx is an index in the
4040 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4041 /// lowering EXTRACT_VECTOR_ELT operations easier.
4042 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4043 SelectionDAG &DAG, SDLoc dl) {
4044 assert((Vec.getValueType().is256BitVector() ||
4045 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4046 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4049 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4050 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4051 SelectionDAG &DAG, SDLoc dl) {
4052 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4053 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4056 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4057 unsigned IdxVal, SelectionDAG &DAG,
4058 SDLoc dl, unsigned vectorWidth) {
4059 assert((vectorWidth == 128 || vectorWidth == 256) &&
4060 "Unsupported vector width");
4061 // Inserting UNDEF is Result
4062 if (Vec.getOpcode() == ISD::UNDEF)
4064 EVT VT = Vec.getValueType();
4065 EVT ElVT = VT.getVectorElementType();
4066 EVT ResultVT = Result.getValueType();
4068 // Insert the relevant vectorWidth bits.
4069 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4071 // This is the index of the first element of the vectorWidth-bit chunk
4073 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4076 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4077 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4080 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4081 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4082 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4083 /// simple superregister reference. Idx is an index in the 128 bits
4084 /// we want. It need not be aligned to a 128-bit boundary. That makes
4085 /// lowering INSERT_VECTOR_ELT operations easier.
4086 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4087 SelectionDAG &DAG, SDLoc dl) {
4088 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4090 // For insertion into the zero index (low half) of a 256-bit vector, it is
4091 // more efficient to generate a blend with immediate instead of an insert*128.
4092 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4093 // extend the subvector to the size of the result vector. Make sure that
4094 // we are not recursing on that node by checking for undef here.
4095 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4096 Result.getOpcode() != ISD::UNDEF) {
4097 EVT ResultVT = Result.getValueType();
4098 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4099 SDValue Undef = DAG.getUNDEF(ResultVT);
4100 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4103 // The blend instruction, and therefore its mask, depend on the data type.
4104 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4105 if (ScalarType.isFloatingPoint()) {
4106 // Choose either vblendps (float) or vblendpd (double).
4107 unsigned ScalarSize = ScalarType.getSizeInBits();
4108 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4109 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4110 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4111 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4114 const X86Subtarget &Subtarget =
4115 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4117 // AVX2 is needed for 256-bit integer blend support.
4118 // Integers must be cast to 32-bit because there is only vpblendd;
4119 // vpblendw can't be used for this because it has a handicapped mask.
4121 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4122 // is still more efficient than using the wrong domain vinsertf128 that
4123 // will be created by InsertSubVector().
4124 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4126 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4127 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4128 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4129 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4132 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4135 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4136 SelectionDAG &DAG, SDLoc dl) {
4137 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4138 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4141 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4142 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4143 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4144 /// large BUILD_VECTORS.
4145 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4146 unsigned NumElems, SelectionDAG &DAG,
4148 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4149 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4152 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4153 unsigned NumElems, SelectionDAG &DAG,
4155 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4156 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4159 /// getOnesVector - Returns a vector of specified type with all bits set.
4160 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4161 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4162 /// Then bitcast to their original type, ensuring they get CSE'd.
4163 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4165 assert(VT.isVector() && "Expected a vector type");
4167 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4169 if (VT.is256BitVector()) {
4170 if (HasInt256) { // AVX2
4171 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4172 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4174 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4175 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4177 } else if (VT.is128BitVector()) {
4178 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4180 llvm_unreachable("Unexpected vector type");
4182 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4185 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4186 /// operation of specified width.
4187 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4189 unsigned NumElems = VT.getVectorNumElements();
4190 SmallVector<int, 8> Mask;
4191 Mask.push_back(NumElems);
4192 for (unsigned i = 1; i != NumElems; ++i)
4194 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4197 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4198 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4200 unsigned NumElems = VT.getVectorNumElements();
4201 SmallVector<int, 8> Mask;
4202 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4204 Mask.push_back(i + NumElems);
4206 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4209 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4210 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4212 unsigned NumElems = VT.getVectorNumElements();
4213 SmallVector<int, 8> Mask;
4214 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4215 Mask.push_back(i + Half);
4216 Mask.push_back(i + NumElems + Half);
4218 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4221 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4222 /// vector of zero or undef vector. This produces a shuffle where the low
4223 /// element of V2 is swizzled into the zero/undef vector, landing at element
4224 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4225 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4227 const X86Subtarget *Subtarget,
4228 SelectionDAG &DAG) {
4229 MVT VT = V2.getSimpleValueType();
4231 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4232 unsigned NumElems = VT.getVectorNumElements();
4233 SmallVector<int, 16> MaskVec;
4234 for (unsigned i = 0; i != NumElems; ++i)
4235 // If this is the insertion idx, put the low elt of V2 here.
4236 MaskVec.push_back(i == Idx ? NumElems : i);
4237 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4240 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4241 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4242 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4243 /// shuffles which use a single input multiple times, and in those cases it will
4244 /// adjust the mask to only have indices within that single input.
4245 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4246 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4247 unsigned NumElems = VT.getVectorNumElements();
4251 bool IsFakeUnary = false;
4252 switch(N->getOpcode()) {
4253 case X86ISD::BLENDI:
4254 ImmN = N->getOperand(N->getNumOperands()-1);
4255 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4258 ImmN = N->getOperand(N->getNumOperands()-1);
4259 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4260 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4262 case X86ISD::UNPCKH:
4263 DecodeUNPCKHMask(VT, Mask);
4264 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4266 case X86ISD::UNPCKL:
4267 DecodeUNPCKLMask(VT, Mask);
4268 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4270 case X86ISD::MOVHLPS:
4271 DecodeMOVHLPSMask(NumElems, Mask);
4272 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4274 case X86ISD::MOVLHPS:
4275 DecodeMOVLHPSMask(NumElems, Mask);
4276 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4278 case X86ISD::PALIGNR:
4279 ImmN = N->getOperand(N->getNumOperands()-1);
4280 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4282 case X86ISD::PSHUFD:
4283 case X86ISD::VPERMILPI:
4284 ImmN = N->getOperand(N->getNumOperands()-1);
4285 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4288 case X86ISD::PSHUFHW:
4289 ImmN = N->getOperand(N->getNumOperands()-1);
4290 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4293 case X86ISD::PSHUFLW:
4294 ImmN = N->getOperand(N->getNumOperands()-1);
4295 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4298 case X86ISD::PSHUFB: {
4300 SDValue MaskNode = N->getOperand(1);
4301 while (MaskNode->getOpcode() == ISD::BITCAST)
4302 MaskNode = MaskNode->getOperand(0);
4304 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4305 // If we have a build-vector, then things are easy.
4306 EVT VT = MaskNode.getValueType();
4307 assert(VT.isVector() &&
4308 "Can't produce a non-vector with a build_vector!");
4309 if (!VT.isInteger())
4312 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4314 SmallVector<uint64_t, 32> RawMask;
4315 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4316 SDValue Op = MaskNode->getOperand(i);
4317 if (Op->getOpcode() == ISD::UNDEF) {
4318 RawMask.push_back((uint64_t)SM_SentinelUndef);
4321 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4324 APInt MaskElement = CN->getAPIntValue();
4326 // We now have to decode the element which could be any integer size and
4327 // extract each byte of it.
4328 for (int j = 0; j < NumBytesPerElement; ++j) {
4329 // Note that this is x86 and so always little endian: the low byte is
4330 // the first byte of the mask.
4331 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4332 MaskElement = MaskElement.lshr(8);
4335 DecodePSHUFBMask(RawMask, Mask);
4339 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4343 SDValue Ptr = MaskLoad->getBasePtr();
4344 if (Ptr->getOpcode() == X86ISD::Wrapper)
4345 Ptr = Ptr->getOperand(0);
4347 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4348 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4351 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4352 DecodePSHUFBMask(C, Mask);
4360 case X86ISD::VPERMI:
4361 ImmN = N->getOperand(N->getNumOperands()-1);
4362 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4367 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4369 case X86ISD::VPERM2X128:
4370 ImmN = N->getOperand(N->getNumOperands()-1);
4371 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4372 if (Mask.empty()) return false;
4374 case X86ISD::MOVSLDUP:
4375 DecodeMOVSLDUPMask(VT, Mask);
4378 case X86ISD::MOVSHDUP:
4379 DecodeMOVSHDUPMask(VT, Mask);
4382 case X86ISD::MOVDDUP:
4383 DecodeMOVDDUPMask(VT, Mask);
4386 case X86ISD::MOVLHPD:
4387 case X86ISD::MOVLPD:
4388 case X86ISD::MOVLPS:
4389 // Not yet implemented
4391 default: llvm_unreachable("unknown target shuffle node");
4394 // If we have a fake unary shuffle, the shuffle mask is spread across two
4395 // inputs that are actually the same node. Re-map the mask to always point
4396 // into the first input.
4399 if (M >= (int)Mask.size())
4405 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4406 /// element of the result of the vector shuffle.
4407 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4410 return SDValue(); // Limit search depth.
4412 SDValue V = SDValue(N, 0);
4413 EVT VT = V.getValueType();
4414 unsigned Opcode = V.getOpcode();
4416 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4417 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4418 int Elt = SV->getMaskElt(Index);
4421 return DAG.getUNDEF(VT.getVectorElementType());
4423 unsigned NumElems = VT.getVectorNumElements();
4424 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4425 : SV->getOperand(1);
4426 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4429 // Recurse into target specific vector shuffles to find scalars.
4430 if (isTargetShuffle(Opcode)) {
4431 MVT ShufVT = V.getSimpleValueType();
4432 unsigned NumElems = ShufVT.getVectorNumElements();
4433 SmallVector<int, 16> ShuffleMask;
4436 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4439 int Elt = ShuffleMask[Index];
4441 return DAG.getUNDEF(ShufVT.getVectorElementType());
4443 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4445 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4449 // Actual nodes that may contain scalar elements
4450 if (Opcode == ISD::BITCAST) {
4451 V = V.getOperand(0);
4452 EVT SrcVT = V.getValueType();
4453 unsigned NumElems = VT.getVectorNumElements();
4455 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4459 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4460 return (Index == 0) ? V.getOperand(0)
4461 : DAG.getUNDEF(VT.getVectorElementType());
4463 if (V.getOpcode() == ISD::BUILD_VECTOR)
4464 return V.getOperand(Index);
4469 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4471 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4472 unsigned NumNonZero, unsigned NumZero,
4474 const X86Subtarget* Subtarget,
4475 const TargetLowering &TLI) {
4483 // SSE4.1 - use PINSRB to insert each byte directly.
4484 if (Subtarget->hasSSE41()) {
4485 for (unsigned i = 0; i < 16; ++i) {
4486 bool isNonZero = (NonZeros & (1 << i)) != 0;
4490 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4492 V = DAG.getUNDEF(MVT::v16i8);
4495 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4496 MVT::v16i8, V, Op.getOperand(i),
4497 DAG.getIntPtrConstant(i, dl));
4504 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4505 for (unsigned i = 0; i < 16; ++i) {
4506 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4507 if (ThisIsNonZero && First) {
4509 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4511 V = DAG.getUNDEF(MVT::v8i16);
4516 SDValue ThisElt, LastElt;
4517 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4518 if (LastIsNonZero) {
4519 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4520 MVT::i16, Op.getOperand(i-1));
4522 if (ThisIsNonZero) {
4523 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4524 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4525 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4527 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4531 if (ThisElt.getNode())
4532 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4533 DAG.getIntPtrConstant(i/2, dl));
4537 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4540 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4542 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4543 unsigned NumNonZero, unsigned NumZero,
4545 const X86Subtarget* Subtarget,
4546 const TargetLowering &TLI) {
4553 for (unsigned i = 0; i < 8; ++i) {
4554 bool isNonZero = (NonZeros & (1 << i)) != 0;
4558 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4560 V = DAG.getUNDEF(MVT::v8i16);
4563 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4564 MVT::v8i16, V, Op.getOperand(i),
4565 DAG.getIntPtrConstant(i, dl));
4572 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4573 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4574 const X86Subtarget *Subtarget,
4575 const TargetLowering &TLI) {
4576 // Find all zeroable elements.
4577 std::bitset<4> Zeroable;
4578 for (int i=0; i < 4; ++i) {
4579 SDValue Elt = Op->getOperand(i);
4580 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4582 assert(Zeroable.size() - Zeroable.count() > 1 &&
4583 "We expect at least two non-zero elements!");
4585 // We only know how to deal with build_vector nodes where elements are either
4586 // zeroable or extract_vector_elt with constant index.
4587 SDValue FirstNonZero;
4588 unsigned FirstNonZeroIdx;
4589 for (unsigned i=0; i < 4; ++i) {
4592 SDValue Elt = Op->getOperand(i);
4593 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4594 !isa<ConstantSDNode>(Elt.getOperand(1)))
4596 // Make sure that this node is extracting from a 128-bit vector.
4597 MVT VT = Elt.getOperand(0).getSimpleValueType();
4598 if (!VT.is128BitVector())
4600 if (!FirstNonZero.getNode()) {
4602 FirstNonZeroIdx = i;
4606 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4607 SDValue V1 = FirstNonZero.getOperand(0);
4608 MVT VT = V1.getSimpleValueType();
4610 // See if this build_vector can be lowered as a blend with zero.
4612 unsigned EltMaskIdx, EltIdx;
4614 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4615 if (Zeroable[EltIdx]) {
4616 // The zero vector will be on the right hand side.
4617 Mask[EltIdx] = EltIdx+4;
4621 Elt = Op->getOperand(EltIdx);
4622 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4623 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4624 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4626 Mask[EltIdx] = EltIdx;
4630 // Let the shuffle legalizer deal with blend operations.
4631 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4632 if (V1.getSimpleValueType() != VT)
4633 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4634 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4637 // See if we can lower this build_vector to a INSERTPS.
4638 if (!Subtarget->hasSSE41())
4641 SDValue V2 = Elt.getOperand(0);
4642 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4645 bool CanFold = true;
4646 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4650 SDValue Current = Op->getOperand(i);
4651 SDValue SrcVector = Current->getOperand(0);
4654 CanFold = SrcVector == V1 &&
4655 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4661 assert(V1.getNode() && "Expected at least two non-zero elements!");
4662 if (V1.getSimpleValueType() != MVT::v4f32)
4663 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4664 if (V2.getSimpleValueType() != MVT::v4f32)
4665 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4667 // Ok, we can emit an INSERTPS instruction.
4668 unsigned ZMask = Zeroable.to_ulong();
4670 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4671 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4673 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4674 DAG.getIntPtrConstant(InsertPSMask, DL));
4675 return DAG.getNode(ISD::BITCAST, DL, VT, Result);
4678 /// Return a vector logical shift node.
4679 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4680 unsigned NumBits, SelectionDAG &DAG,
4681 const TargetLowering &TLI, SDLoc dl) {
4682 assert(VT.is128BitVector() && "Unknown type for VShift");
4683 MVT ShVT = MVT::v2i64;
4684 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4685 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4686 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4687 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4688 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4689 return DAG.getNode(ISD::BITCAST, dl, VT,
4690 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4694 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4696 // Check if the scalar load can be widened into a vector load. And if
4697 // the address is "base + cst" see if the cst can be "absorbed" into
4698 // the shuffle mask.
4699 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4700 SDValue Ptr = LD->getBasePtr();
4701 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4703 EVT PVT = LD->getValueType(0);
4704 if (PVT != MVT::i32 && PVT != MVT::f32)
4709 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4710 FI = FINode->getIndex();
4712 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4713 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4714 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4715 Offset = Ptr.getConstantOperandVal(1);
4716 Ptr = Ptr.getOperand(0);
4721 // FIXME: 256-bit vector instructions don't require a strict alignment,
4722 // improve this code to support it better.
4723 unsigned RequiredAlign = VT.getSizeInBits()/8;
4724 SDValue Chain = LD->getChain();
4725 // Make sure the stack object alignment is at least 16 or 32.
4726 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4727 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4728 if (MFI->isFixedObjectIndex(FI)) {
4729 // Can't change the alignment. FIXME: It's possible to compute
4730 // the exact stack offset and reference FI + adjust offset instead.
4731 // If someone *really* cares about this. That's the way to implement it.
4734 MFI->setObjectAlignment(FI, RequiredAlign);
4738 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4739 // Ptr + (Offset & ~15).
4742 if ((Offset % RequiredAlign) & 3)
4744 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4747 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4748 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4751 int EltNo = (Offset - StartOffset) >> 2;
4752 unsigned NumElems = VT.getVectorNumElements();
4754 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4755 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4756 LD->getPointerInfo().getWithOffset(StartOffset),
4757 false, false, false, 0);
4759 SmallVector<int, 8> Mask(NumElems, EltNo);
4761 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4767 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4768 /// elements can be replaced by a single large load which has the same value as
4769 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4771 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4773 /// FIXME: we'd also like to handle the case where the last elements are zero
4774 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4775 /// There's even a handy isZeroNode for that purpose.
4776 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4777 SDLoc &DL, SelectionDAG &DAG,
4778 bool isAfterLegalize) {
4779 unsigned NumElems = Elts.size();
4781 LoadSDNode *LDBase = nullptr;
4782 unsigned LastLoadedElt = -1U;
4784 // For each element in the initializer, see if we've found a load or an undef.
4785 // If we don't find an initial load element, or later load elements are
4786 // non-consecutive, bail out.
4787 for (unsigned i = 0; i < NumElems; ++i) {
4788 SDValue Elt = Elts[i];
4789 // Look through a bitcast.
4790 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4791 Elt = Elt.getOperand(0);
4792 if (!Elt.getNode() ||
4793 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4796 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4798 LDBase = cast<LoadSDNode>(Elt.getNode());
4802 if (Elt.getOpcode() == ISD::UNDEF)
4805 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4806 EVT LdVT = Elt.getValueType();
4807 // Each loaded element must be the correct fractional portion of the
4808 // requested vector load.
4809 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4811 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4816 // If we have found an entire vector of loads and undefs, then return a large
4817 // load of the entire vector width starting at the base pointer. If we found
4818 // consecutive loads for the low half, generate a vzext_load node.
4819 if (LastLoadedElt == NumElems - 1) {
4820 assert(LDBase && "Did not find base load for merging consecutive loads");
4821 EVT EltVT = LDBase->getValueType(0);
4822 // Ensure that the input vector size for the merged loads matches the
4823 // cumulative size of the input elements.
4824 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4827 if (isAfterLegalize &&
4828 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4831 SDValue NewLd = SDValue();
4833 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4834 LDBase->getPointerInfo(), LDBase->isVolatile(),
4835 LDBase->isNonTemporal(), LDBase->isInvariant(),
4836 LDBase->getAlignment());
4838 if (LDBase->hasAnyUseOfValue(1)) {
4839 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4841 SDValue(NewLd.getNode(), 1));
4842 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4843 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4844 SDValue(NewLd.getNode(), 1));
4850 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4851 //of a v4i32 / v4f32. It's probably worth generalizing.
4852 EVT EltVT = VT.getVectorElementType();
4853 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4854 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4855 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4856 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4858 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4859 LDBase->getPointerInfo(),
4860 LDBase->getAlignment(),
4861 false/*isVolatile*/, true/*ReadMem*/,
4864 // Make sure the newly-created LOAD is in the same position as LDBase in
4865 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4866 // update uses of LDBase's output chain to use the TokenFactor.
4867 if (LDBase->hasAnyUseOfValue(1)) {
4868 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4869 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4870 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4871 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4872 SDValue(ResNode.getNode(), 1));
4875 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4880 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4881 /// to generate a splat value for the following cases:
4882 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4883 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4884 /// a scalar load, or a constant.
4885 /// The VBROADCAST node is returned when a pattern is found,
4886 /// or SDValue() otherwise.
4887 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4888 SelectionDAG &DAG) {
4889 // VBROADCAST requires AVX.
4890 // TODO: Splats could be generated for non-AVX CPUs using SSE
4891 // instructions, but there's less potential gain for only 128-bit vectors.
4892 if (!Subtarget->hasAVX())
4895 MVT VT = Op.getSimpleValueType();
4898 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4899 "Unsupported vector type for broadcast.");
4904 switch (Op.getOpcode()) {
4906 // Unknown pattern found.
4909 case ISD::BUILD_VECTOR: {
4910 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4911 BitVector UndefElements;
4912 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4914 // We need a splat of a single value to use broadcast, and it doesn't
4915 // make any sense if the value is only in one element of the vector.
4916 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4920 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4921 Ld.getOpcode() == ISD::ConstantFP);
4923 // Make sure that all of the users of a non-constant load are from the
4924 // BUILD_VECTOR node.
4925 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4930 case ISD::VECTOR_SHUFFLE: {
4931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4933 // Shuffles must have a splat mask where the first element is
4935 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4938 SDValue Sc = Op.getOperand(0);
4939 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4940 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4942 if (!Subtarget->hasInt256())
4945 // Use the register form of the broadcast instruction available on AVX2.
4946 if (VT.getSizeInBits() >= 256)
4947 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4948 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4951 Ld = Sc.getOperand(0);
4952 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4953 Ld.getOpcode() == ISD::ConstantFP);
4955 // The scalar_to_vector node and the suspected
4956 // load node must have exactly one user.
4957 // Constants may have multiple users.
4959 // AVX-512 has register version of the broadcast
4960 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
4961 Ld.getValueType().getSizeInBits() >= 32;
4962 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
4969 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4970 bool IsGE256 = (VT.getSizeInBits() >= 256);
4972 // When optimizing for size, generate up to 5 extra bytes for a broadcast
4973 // instruction to save 8 or more bytes of constant pool data.
4974 // TODO: If multiple splats are generated to load the same constant,
4975 // it may be detrimental to overall size. There needs to be a way to detect
4976 // that condition to know if this is truly a size win.
4977 const Function *F = DAG.getMachineFunction().getFunction();
4978 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
4980 // Handle broadcasting a single constant scalar from the constant pool
4982 // On Sandybridge (no AVX2), it is still better to load a constant vector
4983 // from the constant pool and not to broadcast it from a scalar.
4984 // But override that restriction when optimizing for size.
4985 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
4986 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
4987 EVT CVT = Ld.getValueType();
4988 assert(!CVT.isVector() && "Must not broadcast a vector type");
4990 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
4991 // For size optimization, also splat v2f64 and v2i64, and for size opt
4992 // with AVX2, also splat i8 and i16.
4993 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
4994 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
4995 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
4996 const Constant *C = nullptr;
4997 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4998 C = CI->getConstantIntValue();
4999 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5000 C = CF->getConstantFPValue();
5002 assert(C && "Invalid constant type");
5004 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5005 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5006 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5007 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5008 MachinePointerInfo::getConstantPool(),
5009 false, false, false, Alignment);
5011 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5015 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5017 // Handle AVX2 in-register broadcasts.
5018 if (!IsLoad && Subtarget->hasInt256() &&
5019 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5020 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5022 // The scalar source must be a normal load.
5026 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5027 (Subtarget->hasVLX() && ScalarSize == 64))
5028 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5030 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5031 // double since there is no vbroadcastsd xmm
5032 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5033 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5034 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5037 // Unsupported broadcast.
5041 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5042 /// underlying vector and index.
5044 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5046 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5048 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5049 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5052 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5054 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5056 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5057 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5060 // In this case the vector is the extract_subvector expression and the index
5061 // is 2, as specified by the shuffle.
5062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5063 SDValue ShuffleVec = SVOp->getOperand(0);
5064 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5065 assert(ShuffleVecVT.getVectorElementType() ==
5066 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5068 int ShuffleIdx = SVOp->getMaskElt(Idx);
5069 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5070 ExtractedFromVec = ShuffleVec;
5076 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5077 MVT VT = Op.getSimpleValueType();
5079 // Skip if insert_vec_elt is not supported.
5080 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5081 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5085 unsigned NumElems = Op.getNumOperands();
5089 SmallVector<unsigned, 4> InsertIndices;
5090 SmallVector<int, 8> Mask(NumElems, -1);
5092 for (unsigned i = 0; i != NumElems; ++i) {
5093 unsigned Opc = Op.getOperand(i).getOpcode();
5095 if (Opc == ISD::UNDEF)
5098 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5099 // Quit if more than 1 elements need inserting.
5100 if (InsertIndices.size() > 1)
5103 InsertIndices.push_back(i);
5107 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5108 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5109 // Quit if non-constant index.
5110 if (!isa<ConstantSDNode>(ExtIdx))
5112 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5114 // Quit if extracted from vector of different type.
5115 if (ExtractedFromVec.getValueType() != VT)
5118 if (!VecIn1.getNode())
5119 VecIn1 = ExtractedFromVec;
5120 else if (VecIn1 != ExtractedFromVec) {
5121 if (!VecIn2.getNode())
5122 VecIn2 = ExtractedFromVec;
5123 else if (VecIn2 != ExtractedFromVec)
5124 // Quit if more than 2 vectors to shuffle
5128 if (ExtractedFromVec == VecIn1)
5130 else if (ExtractedFromVec == VecIn2)
5131 Mask[i] = Idx + NumElems;
5134 if (!VecIn1.getNode())
5137 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5138 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5139 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5140 unsigned Idx = InsertIndices[i];
5141 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5142 DAG.getIntPtrConstant(Idx, DL));
5148 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5150 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5152 MVT VT = Op.getSimpleValueType();
5153 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5154 "Unexpected type in LowerBUILD_VECTORvXi1!");
5157 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5158 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5159 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5160 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5163 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5164 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5165 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5166 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5169 bool AllContants = true;
5170 uint64_t Immediate = 0;
5171 int NonConstIdx = -1;
5172 bool IsSplat = true;
5173 unsigned NumNonConsts = 0;
5174 unsigned NumConsts = 0;
5175 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5176 SDValue In = Op.getOperand(idx);
5177 if (In.getOpcode() == ISD::UNDEF)
5179 if (!isa<ConstantSDNode>(In)) {
5180 AllContants = false;
5185 if (cast<ConstantSDNode>(In)->getZExtValue())
5186 Immediate |= (1ULL << idx);
5188 if (In != Op.getOperand(0))
5193 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5194 DAG.getConstant(Immediate, dl, MVT::i16));
5195 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5196 DAG.getIntPtrConstant(0, dl));
5199 if (NumNonConsts == 1 && NonConstIdx != 0) {
5202 SDValue VecAsImm = DAG.getConstant(Immediate, dl,
5203 MVT::getIntegerVT(VT.getSizeInBits()));
5204 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5207 DstVec = DAG.getUNDEF(VT);
5208 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5209 Op.getOperand(NonConstIdx),
5210 DAG.getIntPtrConstant(NonConstIdx, dl));
5212 if (!IsSplat && (NonConstIdx != 0))
5213 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5214 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5217 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5218 DAG.getConstant(-1, dl, SelectVT),
5219 DAG.getConstant(0, dl, SelectVT));
5221 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5222 DAG.getConstant((Immediate | 1), dl, SelectVT),
5223 DAG.getConstant(Immediate, dl, SelectVT));
5224 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5227 /// \brief Return true if \p N implements a horizontal binop and return the
5228 /// operands for the horizontal binop into V0 and V1.
5230 /// This is a helper function of LowerToHorizontalOp().
5231 /// This function checks that the build_vector \p N in input implements a
5232 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5233 /// operation to match.
5234 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5235 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5236 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5239 /// This function only analyzes elements of \p N whose indices are
5240 /// in range [BaseIdx, LastIdx).
5241 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5243 unsigned BaseIdx, unsigned LastIdx,
5244 SDValue &V0, SDValue &V1) {
5245 EVT VT = N->getValueType(0);
5247 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5248 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5249 "Invalid Vector in input!");
5251 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5252 bool CanFold = true;
5253 unsigned ExpectedVExtractIdx = BaseIdx;
5254 unsigned NumElts = LastIdx - BaseIdx;
5255 V0 = DAG.getUNDEF(VT);
5256 V1 = DAG.getUNDEF(VT);
5258 // Check if N implements a horizontal binop.
5259 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5260 SDValue Op = N->getOperand(i + BaseIdx);
5263 if (Op->getOpcode() == ISD::UNDEF) {
5264 // Update the expected vector extract index.
5265 if (i * 2 == NumElts)
5266 ExpectedVExtractIdx = BaseIdx;
5267 ExpectedVExtractIdx += 2;
5271 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5276 SDValue Op0 = Op.getOperand(0);
5277 SDValue Op1 = Op.getOperand(1);
5279 // Try to match the following pattern:
5280 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5281 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5282 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5283 Op0.getOperand(0) == Op1.getOperand(0) &&
5284 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5285 isa<ConstantSDNode>(Op1.getOperand(1)));
5289 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5290 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5292 if (i * 2 < NumElts) {
5293 if (V0.getOpcode() == ISD::UNDEF) {
5294 V0 = Op0.getOperand(0);
5295 if (V0.getValueType() != VT)
5299 if (V1.getOpcode() == ISD::UNDEF) {
5300 V1 = Op0.getOperand(0);
5301 if (V1.getValueType() != VT)
5304 if (i * 2 == NumElts)
5305 ExpectedVExtractIdx = BaseIdx;
5308 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5309 if (I0 == ExpectedVExtractIdx)
5310 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5311 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5312 // Try to match the following dag sequence:
5313 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5314 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5318 ExpectedVExtractIdx += 2;
5324 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5325 /// a concat_vector.
5327 /// This is a helper function of LowerToHorizontalOp().
5328 /// This function expects two 256-bit vectors called V0 and V1.
5329 /// At first, each vector is split into two separate 128-bit vectors.
5330 /// Then, the resulting 128-bit vectors are used to implement two
5331 /// horizontal binary operations.
5333 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5335 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5336 /// the two new horizontal binop.
5337 /// When Mode is set, the first horizontal binop dag node would take as input
5338 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5339 /// horizontal binop dag node would take as input the lower 128-bit of V1
5340 /// and the upper 128-bit of V1.
5342 /// HADD V0_LO, V0_HI
5343 /// HADD V1_LO, V1_HI
5345 /// Otherwise, the first horizontal binop dag node takes as input the lower
5346 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5347 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5349 /// HADD V0_LO, V1_LO
5350 /// HADD V0_HI, V1_HI
5352 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5353 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5354 /// the upper 128-bits of the result.
5355 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5356 SDLoc DL, SelectionDAG &DAG,
5357 unsigned X86Opcode, bool Mode,
5358 bool isUndefLO, bool isUndefHI) {
5359 EVT VT = V0.getValueType();
5360 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5361 "Invalid nodes in input!");
5363 unsigned NumElts = VT.getVectorNumElements();
5364 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5365 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5366 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5367 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5368 EVT NewVT = V0_LO.getValueType();
5370 SDValue LO = DAG.getUNDEF(NewVT);
5371 SDValue HI = DAG.getUNDEF(NewVT);
5374 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5375 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5376 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5377 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5378 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5380 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5381 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5382 V1_LO->getOpcode() != ISD::UNDEF))
5383 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5385 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5386 V1_HI->getOpcode() != ISD::UNDEF))
5387 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5390 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5393 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5395 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5396 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5397 EVT VT = BV->getValueType(0);
5398 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5399 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5403 unsigned NumElts = VT.getVectorNumElements();
5404 SDValue InVec0 = DAG.getUNDEF(VT);
5405 SDValue InVec1 = DAG.getUNDEF(VT);
5407 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5408 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5410 // Odd-numbered elements in the input build vector are obtained from
5411 // adding two integer/float elements.
5412 // Even-numbered elements in the input build vector are obtained from
5413 // subtracting two integer/float elements.
5414 unsigned ExpectedOpcode = ISD::FSUB;
5415 unsigned NextExpectedOpcode = ISD::FADD;
5416 bool AddFound = false;
5417 bool SubFound = false;
5419 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5420 SDValue Op = BV->getOperand(i);
5422 // Skip 'undef' values.
5423 unsigned Opcode = Op.getOpcode();
5424 if (Opcode == ISD::UNDEF) {
5425 std::swap(ExpectedOpcode, NextExpectedOpcode);
5429 // Early exit if we found an unexpected opcode.
5430 if (Opcode != ExpectedOpcode)
5433 SDValue Op0 = Op.getOperand(0);
5434 SDValue Op1 = Op.getOperand(1);
5436 // Try to match the following pattern:
5437 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5438 // Early exit if we cannot match that sequence.
5439 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5440 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5441 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5442 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5443 Op0.getOperand(1) != Op1.getOperand(1))
5446 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5450 // We found a valid add/sub node. Update the information accordingly.
5456 // Update InVec0 and InVec1.
5457 if (InVec0.getOpcode() == ISD::UNDEF) {
5458 InVec0 = Op0.getOperand(0);
5459 if (InVec0.getValueType() != VT)
5462 if (InVec1.getOpcode() == ISD::UNDEF) {
5463 InVec1 = Op1.getOperand(0);
5464 if (InVec1.getValueType() != VT)
5468 // Make sure that operands in input to each add/sub node always
5469 // come from a same pair of vectors.
5470 if (InVec0 != Op0.getOperand(0)) {
5471 if (ExpectedOpcode == ISD::FSUB)
5474 // FADD is commutable. Try to commute the operands
5475 // and then test again.
5476 std::swap(Op0, Op1);
5477 if (InVec0 != Op0.getOperand(0))
5481 if (InVec1 != Op1.getOperand(0))
5484 // Update the pair of expected opcodes.
5485 std::swap(ExpectedOpcode, NextExpectedOpcode);
5488 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5489 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5490 InVec1.getOpcode() != ISD::UNDEF)
5491 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5496 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5497 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5498 const X86Subtarget *Subtarget,
5499 SelectionDAG &DAG) {
5500 EVT VT = BV->getValueType(0);
5501 unsigned NumElts = VT.getVectorNumElements();
5502 unsigned NumUndefsLO = 0;
5503 unsigned NumUndefsHI = 0;
5504 unsigned Half = NumElts/2;
5506 // Count the number of UNDEF operands in the build_vector in input.
5507 for (unsigned i = 0, e = Half; i != e; ++i)
5508 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5511 for (unsigned i = Half, e = NumElts; i != e; ++i)
5512 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5515 // Early exit if this is either a build_vector of all UNDEFs or all the
5516 // operands but one are UNDEF.
5517 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5521 SDValue InVec0, InVec1;
5522 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5523 // Try to match an SSE3 float HADD/HSUB.
5524 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5525 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5527 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5528 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5529 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5530 // Try to match an SSSE3 integer HADD/HSUB.
5531 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5532 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5534 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5535 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5538 if (!Subtarget->hasAVX())
5541 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5542 // Try to match an AVX horizontal add/sub of packed single/double
5543 // precision floating point values from 256-bit vectors.
5544 SDValue InVec2, InVec3;
5545 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5546 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5547 ((InVec0.getOpcode() == ISD::UNDEF ||
5548 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5549 ((InVec1.getOpcode() == ISD::UNDEF ||
5550 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5551 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5553 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5554 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5555 ((InVec0.getOpcode() == ISD::UNDEF ||
5556 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5557 ((InVec1.getOpcode() == ISD::UNDEF ||
5558 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5559 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5560 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5561 // Try to match an AVX2 horizontal add/sub of signed integers.
5562 SDValue InVec2, InVec3;
5564 bool CanFold = true;
5566 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5567 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5568 ((InVec0.getOpcode() == ISD::UNDEF ||
5569 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5570 ((InVec1.getOpcode() == ISD::UNDEF ||
5571 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5572 X86Opcode = X86ISD::HADD;
5573 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5574 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5575 ((InVec0.getOpcode() == ISD::UNDEF ||
5576 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5577 ((InVec1.getOpcode() == ISD::UNDEF ||
5578 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5579 X86Opcode = X86ISD::HSUB;
5584 // Fold this build_vector into a single horizontal add/sub.
5585 // Do this only if the target has AVX2.
5586 if (Subtarget->hasAVX2())
5587 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5589 // Do not try to expand this build_vector into a pair of horizontal
5590 // add/sub if we can emit a pair of scalar add/sub.
5591 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5594 // Convert this build_vector into a pair of horizontal binop followed by
5596 bool isUndefLO = NumUndefsLO == Half;
5597 bool isUndefHI = NumUndefsHI == Half;
5598 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5599 isUndefLO, isUndefHI);
5603 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5604 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5606 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5607 X86Opcode = X86ISD::HADD;
5608 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5609 X86Opcode = X86ISD::HSUB;
5610 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5611 X86Opcode = X86ISD::FHADD;
5612 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5613 X86Opcode = X86ISD::FHSUB;
5617 // Don't try to expand this build_vector into a pair of horizontal add/sub
5618 // if we can simply emit a pair of scalar add/sub.
5619 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5622 // Convert this build_vector into two horizontal add/sub followed by
5624 bool isUndefLO = NumUndefsLO == Half;
5625 bool isUndefHI = NumUndefsHI == Half;
5626 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5627 isUndefLO, isUndefHI);
5634 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5637 MVT VT = Op.getSimpleValueType();
5638 MVT ExtVT = VT.getVectorElementType();
5639 unsigned NumElems = Op.getNumOperands();
5641 // Generate vectors for predicate vectors.
5642 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5643 return LowerBUILD_VECTORvXi1(Op, DAG);
5645 // Vectors containing all zeros can be matched by pxor and xorps later
5646 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5647 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5648 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5649 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5652 return getZeroVector(VT, Subtarget, DAG, dl);
5655 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5656 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5657 // vpcmpeqd on 256-bit vectors.
5658 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5659 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5662 if (!VT.is512BitVector())
5663 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5666 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5667 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5669 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5670 return HorizontalOp;
5671 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5674 unsigned EVTBits = ExtVT.getSizeInBits();
5676 unsigned NumZero = 0;
5677 unsigned NumNonZero = 0;
5678 unsigned NonZeros = 0;
5679 bool IsAllConstants = true;
5680 SmallSet<SDValue, 8> Values;
5681 for (unsigned i = 0; i < NumElems; ++i) {
5682 SDValue Elt = Op.getOperand(i);
5683 if (Elt.getOpcode() == ISD::UNDEF)
5686 if (Elt.getOpcode() != ISD::Constant &&
5687 Elt.getOpcode() != ISD::ConstantFP)
5688 IsAllConstants = false;
5689 if (X86::isZeroNode(Elt))
5692 NonZeros |= (1 << i);
5697 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5698 if (NumNonZero == 0)
5699 return DAG.getUNDEF(VT);
5701 // Special case for single non-zero, non-undef, element.
5702 if (NumNonZero == 1) {
5703 unsigned Idx = countTrailingZeros(NonZeros);
5704 SDValue Item = Op.getOperand(Idx);
5706 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5707 // the value are obviously zero, truncate the value to i32 and do the
5708 // insertion that way. Only do this if the value is non-constant or if the
5709 // value is a constant being inserted into element 0. It is cheaper to do
5710 // a constant pool load than it is to do a movd + shuffle.
5711 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5712 (!IsAllConstants || Idx == 0)) {
5713 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5715 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5716 EVT VecVT = MVT::v4i32;
5718 // Truncate the value (which may itself be a constant) to i32, and
5719 // convert it to a vector with movd (S2V+shuffle to zero extend).
5720 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5721 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5723 ISD::BITCAST, dl, VT,
5724 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5728 // If we have a constant or non-constant insertion into the low element of
5729 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5730 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5731 // depending on what the source datatype is.
5734 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5736 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5737 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5738 if (VT.is512BitVector()) {
5739 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5740 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5741 Item, DAG.getIntPtrConstant(0, dl));
5743 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5744 "Expected an SSE value type!");
5745 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5746 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5747 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5750 // We can't directly insert an i8 or i16 into a vector, so zero extend
5752 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5753 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5754 if (VT.is256BitVector()) {
5755 if (Subtarget->hasAVX()) {
5756 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5757 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5759 // Without AVX, we need to extend to a 128-bit vector and then
5760 // insert into the 256-bit vector.
5761 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5762 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5763 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5766 assert(VT.is128BitVector() && "Expected an SSE value type!");
5767 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5768 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5770 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5774 // Is it a vector logical left shift?
5775 if (NumElems == 2 && Idx == 1 &&
5776 X86::isZeroNode(Op.getOperand(0)) &&
5777 !X86::isZeroNode(Op.getOperand(1))) {
5778 unsigned NumBits = VT.getSizeInBits();
5779 return getVShift(true, VT,
5780 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5781 VT, Op.getOperand(1)),
5782 NumBits/2, DAG, *this, dl);
5785 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5788 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5789 // is a non-constant being inserted into an element other than the low one,
5790 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5791 // movd/movss) to move this into the low element, then shuffle it into
5793 if (EVTBits == 32) {
5794 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5795 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5799 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5800 if (Values.size() == 1) {
5801 if (EVTBits == 32) {
5802 // Instead of a shuffle like this:
5803 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5804 // Check if it's possible to issue this instead.
5805 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5806 unsigned Idx = countTrailingZeros(NonZeros);
5807 SDValue Item = Op.getOperand(Idx);
5808 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5809 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5814 // A vector full of immediates; various special cases are already
5815 // handled, so this is best done with a single constant-pool load.
5819 // For AVX-length vectors, see if we can use a vector load to get all of the
5820 // elements, otherwise build the individual 128-bit pieces and use
5821 // shuffles to put them in place.
5822 if (VT.is256BitVector() || VT.is512BitVector()) {
5823 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5825 // Check for a build vector of consecutive loads.
5826 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5829 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5831 // Build both the lower and upper subvector.
5832 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5833 makeArrayRef(&V[0], NumElems/2));
5834 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5835 makeArrayRef(&V[NumElems / 2], NumElems/2));
5837 // Recreate the wider vector with the lower and upper part.
5838 if (VT.is256BitVector())
5839 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5840 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5843 // Let legalizer expand 2-wide build_vectors.
5844 if (EVTBits == 64) {
5845 if (NumNonZero == 1) {
5846 // One half is zero or undef.
5847 unsigned Idx = countTrailingZeros(NonZeros);
5848 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5849 Op.getOperand(Idx));
5850 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5855 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5856 if (EVTBits == 8 && NumElems == 16)
5857 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5861 if (EVTBits == 16 && NumElems == 8)
5862 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5866 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5867 if (EVTBits == 32 && NumElems == 4)
5868 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5871 // If element VT is == 32 bits, turn it into a number of shuffles.
5872 SmallVector<SDValue, 8> V(NumElems);
5873 if (NumElems == 4 && NumZero > 0) {
5874 for (unsigned i = 0; i < 4; ++i) {
5875 bool isZero = !(NonZeros & (1 << i));
5877 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5879 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5882 for (unsigned i = 0; i < 2; ++i) {
5883 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5886 V[i] = V[i*2]; // Must be a zero vector.
5889 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5892 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5895 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5900 bool Reverse1 = (NonZeros & 0x3) == 2;
5901 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5905 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5906 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5908 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5911 if (Values.size() > 1 && VT.is128BitVector()) {
5912 // Check for a build vector of consecutive loads.
5913 for (unsigned i = 0; i < NumElems; ++i)
5914 V[i] = Op.getOperand(i);
5916 // Check for elements which are consecutive loads.
5917 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5920 // Check for a build vector from mostly shuffle plus few inserting.
5921 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
5924 // For SSE 4.1, use insertps to put the high elements into the low element.
5925 if (Subtarget->hasSSE41()) {
5927 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5928 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5930 Result = DAG.getUNDEF(VT);
5932 for (unsigned i = 1; i < NumElems; ++i) {
5933 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5934 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5935 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
5940 // Otherwise, expand into a number of unpckl*, start by extending each of
5941 // our (non-undef) elements to the full vector width with the element in the
5942 // bottom slot of the vector (which generates no code for SSE).
5943 for (unsigned i = 0; i < NumElems; ++i) {
5944 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5945 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5947 V[i] = DAG.getUNDEF(VT);
5950 // Next, we iteratively mix elements, e.g. for v4f32:
5951 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5952 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5953 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5954 unsigned EltStride = NumElems >> 1;
5955 while (EltStride != 0) {
5956 for (unsigned i = 0; i < EltStride; ++i) {
5957 // If V[i+EltStride] is undef and this is the first round of mixing,
5958 // then it is safe to just drop this shuffle: V[i] is already in the
5959 // right place, the one element (since it's the first round) being
5960 // inserted as undef can be dropped. This isn't safe for successive
5961 // rounds because they will permute elements within both vectors.
5962 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5963 EltStride == NumElems/2)
5966 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5975 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5976 // to create 256-bit vectors from two other 128-bit ones.
5977 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5979 MVT ResVT = Op.getSimpleValueType();
5981 assert((ResVT.is256BitVector() ||
5982 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
5984 SDValue V1 = Op.getOperand(0);
5985 SDValue V2 = Op.getOperand(1);
5986 unsigned NumElems = ResVT.getVectorNumElements();
5987 if (ResVT.is256BitVector())
5988 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5990 if (Op.getNumOperands() == 4) {
5991 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5992 ResVT.getVectorNumElements()/2);
5993 SDValue V3 = Op.getOperand(2);
5994 SDValue V4 = Op.getOperand(3);
5995 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
5996 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
5998 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6001 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6002 const X86Subtarget *Subtarget,
6003 SelectionDAG & DAG) {
6005 MVT ResVT = Op.getSimpleValueType();
6006 unsigned NumOfOperands = Op.getNumOperands();
6008 assert(isPowerOf2_32(NumOfOperands) &&
6009 "Unexpected number of operands in CONCAT_VECTORS");
6011 if (NumOfOperands > 2) {
6012 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6013 ResVT.getVectorNumElements()/2);
6014 SmallVector<SDValue, 2> Ops;
6015 for (unsigned i = 0; i < NumOfOperands/2; i++)
6016 Ops.push_back(Op.getOperand(i));
6017 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6019 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6020 Ops.push_back(Op.getOperand(i));
6021 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6022 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6025 SDValue V1 = Op.getOperand(0);
6026 SDValue V2 = Op.getOperand(1);
6027 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6028 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6030 if (IsZeroV1 && IsZeroV2)
6031 return getZeroVector(ResVT, Subtarget, DAG, dl);
6033 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6034 SDValue Undef = DAG.getUNDEF(ResVT);
6035 unsigned NumElems = ResVT.getVectorNumElements();
6036 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6038 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6039 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6043 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6044 // Zero the upper bits of V1
6045 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6046 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6049 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6052 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6053 const X86Subtarget *Subtarget,
6054 SelectionDAG &DAG) {
6055 MVT VT = Op.getSimpleValueType();
6056 if (VT.getVectorElementType() == MVT::i1)
6057 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6059 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6060 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6061 Op.getNumOperands() == 4)));
6063 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6064 // from two other 128-bit ones.
6066 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6067 return LowerAVXCONCAT_VECTORS(Op, DAG);
6071 //===----------------------------------------------------------------------===//
6072 // Vector shuffle lowering
6074 // This is an experimental code path for lowering vector shuffles on x86. It is
6075 // designed to handle arbitrary vector shuffles and blends, gracefully
6076 // degrading performance as necessary. It works hard to recognize idiomatic
6077 // shuffles and lower them to optimal instruction patterns without leaving
6078 // a framework that allows reasonably efficient handling of all vector shuffle
6080 //===----------------------------------------------------------------------===//
6082 /// \brief Tiny helper function to identify a no-op mask.
6084 /// This is a somewhat boring predicate function. It checks whether the mask
6085 /// array input, which is assumed to be a single-input shuffle mask of the kind
6086 /// used by the X86 shuffle instructions (not a fully general
6087 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6088 /// in-place shuffle are 'no-op's.
6089 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6090 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6091 if (Mask[i] != -1 && Mask[i] != i)
6096 /// \brief Helper function to classify a mask as a single-input mask.
6098 /// This isn't a generic single-input test because in the vector shuffle
6099 /// lowering we canonicalize single inputs to be the first input operand. This
6100 /// means we can more quickly test for a single input by only checking whether
6101 /// an input from the second operand exists. We also assume that the size of
6102 /// mask corresponds to the size of the input vectors which isn't true in the
6103 /// fully general case.
6104 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6106 if (M >= (int)Mask.size())
6111 /// \brief Test whether there are elements crossing 128-bit lanes in this
6114 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6115 /// and we routinely test for these.
6116 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6117 int LaneSize = 128 / VT.getScalarSizeInBits();
6118 int Size = Mask.size();
6119 for (int i = 0; i < Size; ++i)
6120 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6125 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6127 /// This checks a shuffle mask to see if it is performing the same
6128 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6129 /// that it is also not lane-crossing. It may however involve a blend from the
6130 /// same lane of a second vector.
6132 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6133 /// non-trivial to compute in the face of undef lanes. The representation is
6134 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6135 /// entries from both V1 and V2 inputs to the wider mask.
6137 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6138 SmallVectorImpl<int> &RepeatedMask) {
6139 int LaneSize = 128 / VT.getScalarSizeInBits();
6140 RepeatedMask.resize(LaneSize, -1);
6141 int Size = Mask.size();
6142 for (int i = 0; i < Size; ++i) {
6145 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6146 // This entry crosses lanes, so there is no way to model this shuffle.
6149 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6150 if (RepeatedMask[i % LaneSize] == -1)
6151 // This is the first non-undef entry in this slot of a 128-bit lane.
6152 RepeatedMask[i % LaneSize] =
6153 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6154 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6155 // Found a mismatch with the repeated mask.
6161 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6164 /// This is a fast way to test a shuffle mask against a fixed pattern:
6166 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6168 /// It returns true if the mask is exactly as wide as the argument list, and
6169 /// each element of the mask is either -1 (signifying undef) or the value given
6170 /// in the argument.
6171 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6172 ArrayRef<int> ExpectedMask) {
6173 if (Mask.size() != ExpectedMask.size())
6176 int Size = Mask.size();
6178 // If the values are build vectors, we can look through them to find
6179 // equivalent inputs that make the shuffles equivalent.
6180 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6181 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6183 for (int i = 0; i < Size; ++i)
6184 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6185 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6186 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6187 if (!MaskBV || !ExpectedBV ||
6188 MaskBV->getOperand(Mask[i] % Size) !=
6189 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6196 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6198 /// This helper function produces an 8-bit shuffle immediate corresponding to
6199 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6200 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6203 /// NB: We rely heavily on "undef" masks preserving the input lane.
6204 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6205 SelectionDAG &DAG) {
6206 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6207 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6208 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6209 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6210 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6213 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6214 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6215 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6216 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6217 return DAG.getConstant(Imm, DL, MVT::i8);
6220 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6222 /// This is used as a fallback approach when first class blend instructions are
6223 /// unavailable. Currently it is only suitable for integer vectors, but could
6224 /// be generalized for floating point vectors if desirable.
6225 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6226 SDValue V2, ArrayRef<int> Mask,
6227 SelectionDAG &DAG) {
6228 assert(VT.isInteger() && "Only supports integer vector types!");
6229 MVT EltVT = VT.getScalarType();
6230 int NumEltBits = EltVT.getSizeInBits();
6231 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6232 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6234 SmallVector<SDValue, 16> MaskOps;
6235 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6236 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6237 return SDValue(); // Shuffled input!
6238 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6241 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6242 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6243 // We have to cast V2 around.
6244 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6245 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6246 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6247 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6248 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6249 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6252 /// \brief Try to emit a blend instruction for a shuffle.
6254 /// This doesn't do any checks for the availability of instructions for blending
6255 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6256 /// be matched in the backend with the type given. What it does check for is
6257 /// that the shuffle mask is in fact a blend.
6258 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6259 SDValue V2, ArrayRef<int> Mask,
6260 const X86Subtarget *Subtarget,
6261 SelectionDAG &DAG) {
6262 unsigned BlendMask = 0;
6263 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6264 if (Mask[i] >= Size) {
6265 if (Mask[i] != i + Size)
6266 return SDValue(); // Shuffled V2 input!
6267 BlendMask |= 1u << i;
6270 if (Mask[i] >= 0 && Mask[i] != i)
6271 return SDValue(); // Shuffled V1 input!
6273 switch (VT.SimpleTy) {
6278 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6279 DAG.getConstant(BlendMask, DL, MVT::i8));
6283 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6287 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6288 // that instruction.
6289 if (Subtarget->hasAVX2()) {
6290 // Scale the blend by the number of 32-bit dwords per element.
6291 int Scale = VT.getScalarSizeInBits() / 32;
6293 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6294 if (Mask[i] >= Size)
6295 for (int j = 0; j < Scale; ++j)
6296 BlendMask |= 1u << (i * Scale + j);
6298 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6299 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6300 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6301 return DAG.getNode(ISD::BITCAST, DL, VT,
6302 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6303 DAG.getConstant(BlendMask, DL, MVT::i8)));
6307 // For integer shuffles we need to expand the mask and cast the inputs to
6308 // v8i16s prior to blending.
6309 int Scale = 8 / VT.getVectorNumElements();
6311 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6312 if (Mask[i] >= Size)
6313 for (int j = 0; j < Scale; ++j)
6314 BlendMask |= 1u << (i * Scale + j);
6316 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6317 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6318 return DAG.getNode(ISD::BITCAST, DL, VT,
6319 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6320 DAG.getConstant(BlendMask, DL, MVT::i8)));
6324 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6325 SmallVector<int, 8> RepeatedMask;
6326 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6327 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6328 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6330 for (int i = 0; i < 8; ++i)
6331 if (RepeatedMask[i] >= 16)
6332 BlendMask |= 1u << i;
6333 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6334 DAG.getConstant(BlendMask, DL, MVT::i8));
6340 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6341 "256-bit byte-blends require AVX2 support!");
6343 // Scale the blend by the number of bytes per element.
6344 int Scale = VT.getScalarSizeInBits() / 8;
6346 // This form of blend is always done on bytes. Compute the byte vector
6348 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6350 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6351 // mix of LLVM's code generator and the x86 backend. We tell the code
6352 // generator that boolean values in the elements of an x86 vector register
6353 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6354 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6355 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6356 // of the element (the remaining are ignored) and 0 in that high bit would
6357 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6358 // the LLVM model for boolean values in vector elements gets the relevant
6359 // bit set, it is set backwards and over constrained relative to x86's
6361 SmallVector<SDValue, 32> VSELECTMask;
6362 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6363 for (int j = 0; j < Scale; ++j)
6364 VSELECTMask.push_back(
6365 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6366 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6369 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6370 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6372 ISD::BITCAST, DL, VT,
6373 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6374 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6379 llvm_unreachable("Not a supported integer vector type!");
6383 /// \brief Try to lower as a blend of elements from two inputs followed by
6384 /// a single-input permutation.
6386 /// This matches the pattern where we can blend elements from two inputs and
6387 /// then reduce the shuffle to a single-input permutation.
6388 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6391 SelectionDAG &DAG) {
6392 // We build up the blend mask while checking whether a blend is a viable way
6393 // to reduce the shuffle.
6394 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6395 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6397 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6401 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6403 if (BlendMask[Mask[i] % Size] == -1)
6404 BlendMask[Mask[i] % Size] = Mask[i];
6405 else if (BlendMask[Mask[i] % Size] != Mask[i])
6406 return SDValue(); // Can't blend in the needed input!
6408 PermuteMask[i] = Mask[i] % Size;
6411 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6412 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6415 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6416 /// blends and permutes.
6418 /// This matches the extremely common pattern for handling combined
6419 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6420 /// operations. It will try to pick the best arrangement of shuffles and
6422 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6426 SelectionDAG &DAG) {
6427 // Shuffle the input elements into the desired positions in V1 and V2 and
6428 // blend them together.
6429 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6430 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6431 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6432 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6433 if (Mask[i] >= 0 && Mask[i] < Size) {
6434 V1Mask[i] = Mask[i];
6436 } else if (Mask[i] >= Size) {
6437 V2Mask[i] = Mask[i] - Size;
6438 BlendMask[i] = i + Size;
6441 // Try to lower with the simpler initial blend strategy unless one of the
6442 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6443 // shuffle may be able to fold with a load or other benefit. However, when
6444 // we'll have to do 2x as many shuffles in order to achieve this, blending
6445 // first is a better strategy.
6446 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6447 if (SDValue BlendPerm =
6448 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6451 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6452 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6453 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6456 /// \brief Try to lower a vector shuffle as a byte rotation.
6458 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6459 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6460 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6461 /// try to generically lower a vector shuffle through such an pattern. It
6462 /// does not check for the profitability of lowering either as PALIGNR or
6463 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6464 /// This matches shuffle vectors that look like:
6466 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6468 /// Essentially it concatenates V1 and V2, shifts right by some number of
6469 /// elements, and takes the low elements as the result. Note that while this is
6470 /// specified as a *right shift* because x86 is little-endian, it is a *left
6471 /// rotate* of the vector lanes.
6472 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6475 const X86Subtarget *Subtarget,
6476 SelectionDAG &DAG) {
6477 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6479 int NumElts = Mask.size();
6480 int NumLanes = VT.getSizeInBits() / 128;
6481 int NumLaneElts = NumElts / NumLanes;
6483 // We need to detect various ways of spelling a rotation:
6484 // [11, 12, 13, 14, 15, 0, 1, 2]
6485 // [-1, 12, 13, 14, -1, -1, 1, -1]
6486 // [-1, -1, -1, -1, -1, -1, 1, 2]
6487 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6488 // [-1, 4, 5, 6, -1, -1, 9, -1]
6489 // [-1, 4, 5, 6, -1, -1, -1, -1]
6492 for (int l = 0; l < NumElts; l += NumLaneElts) {
6493 for (int i = 0; i < NumLaneElts; ++i) {
6494 if (Mask[l + i] == -1)
6496 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6498 // Get the mod-Size index and lane correct it.
6499 int LaneIdx = (Mask[l + i] % NumElts) - l;
6500 // Make sure it was in this lane.
6501 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6504 // Determine where a rotated vector would have started.
6505 int StartIdx = i - LaneIdx;
6507 // The identity rotation isn't interesting, stop.
6510 // If we found the tail of a vector the rotation must be the missing
6511 // front. If we found the head of a vector, it must be how much of the
6513 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6516 Rotation = CandidateRotation;
6517 else if (Rotation != CandidateRotation)
6518 // The rotations don't match, so we can't match this mask.
6521 // Compute which value this mask is pointing at.
6522 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6524 // Compute which of the two target values this index should be assigned
6525 // to. This reflects whether the high elements are remaining or the low
6526 // elements are remaining.
6527 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6529 // Either set up this value if we've not encountered it before, or check
6530 // that it remains consistent.
6533 else if (TargetV != MaskV)
6534 // This may be a rotation, but it pulls from the inputs in some
6535 // unsupported interleaving.
6540 // Check that we successfully analyzed the mask, and normalize the results.
6541 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6542 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6548 // The actual rotate instruction rotates bytes, so we need to scale the
6549 // rotation based on how many bytes are in the vector lane.
6550 int Scale = 16 / NumLaneElts;
6552 // SSSE3 targets can use the palignr instruction.
6553 if (Subtarget->hasSSSE3()) {
6554 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6555 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6556 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6557 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6559 return DAG.getNode(ISD::BITCAST, DL, VT,
6560 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6561 DAG.getConstant(Rotation * Scale, DL,
6565 assert(VT.getSizeInBits() == 128 &&
6566 "Rotate-based lowering only supports 128-bit lowering!");
6567 assert(Mask.size() <= 16 &&
6568 "Can shuffle at most 16 bytes in a 128-bit vector!");
6570 // Default SSE2 implementation
6571 int LoByteShift = 16 - Rotation * Scale;
6572 int HiByteShift = Rotation * Scale;
6574 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6575 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6576 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6578 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6579 DAG.getConstant(LoByteShift, DL, MVT::i8));
6580 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6581 DAG.getConstant(HiByteShift, DL, MVT::i8));
6582 return DAG.getNode(ISD::BITCAST, DL, VT,
6583 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6586 /// \brief Compute whether each element of a shuffle is zeroable.
6588 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6589 /// Either it is an undef element in the shuffle mask, the element of the input
6590 /// referenced is undef, or the element of the input referenced is known to be
6591 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6592 /// as many lanes with this technique as possible to simplify the remaining
6594 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6595 SDValue V1, SDValue V2) {
6596 SmallBitVector Zeroable(Mask.size(), false);
6598 while (V1.getOpcode() == ISD::BITCAST)
6599 V1 = V1->getOperand(0);
6600 while (V2.getOpcode() == ISD::BITCAST)
6601 V2 = V2->getOperand(0);
6603 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6604 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6606 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6608 // Handle the easy cases.
6609 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6614 // If this is an index into a build_vector node (which has the same number
6615 // of elements), dig out the input value and use it.
6616 SDValue V = M < Size ? V1 : V2;
6617 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6620 SDValue Input = V.getOperand(M % Size);
6621 // The UNDEF opcode check really should be dead code here, but not quite
6622 // worth asserting on (it isn't invalid, just unexpected).
6623 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6630 /// \brief Try to emit a bitmask instruction for a shuffle.
6632 /// This handles cases where we can model a blend exactly as a bitmask due to
6633 /// one of the inputs being zeroable.
6634 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6635 SDValue V2, ArrayRef<int> Mask,
6636 SelectionDAG &DAG) {
6637 MVT EltVT = VT.getScalarType();
6638 int NumEltBits = EltVT.getSizeInBits();
6639 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6640 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6641 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6643 if (EltVT.isFloatingPoint()) {
6644 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6645 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6647 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6648 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6650 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6653 if (Mask[i] % Size != i)
6654 return SDValue(); // Not a blend.
6656 V = Mask[i] < Size ? V1 : V2;
6657 else if (V != (Mask[i] < Size ? V1 : V2))
6658 return SDValue(); // Can only let one input through the mask.
6660 VMaskOps[i] = AllOnes;
6663 return SDValue(); // No non-zeroable elements!
6665 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6666 V = DAG.getNode(VT.isFloatingPoint()
6667 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6672 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6674 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6675 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6676 /// matches elements from one of the input vectors shuffled to the left or
6677 /// right with zeroable elements 'shifted in'. It handles both the strictly
6678 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6681 /// PSHL : (little-endian) left bit shift.
6682 /// [ zz, 0, zz, 2 ]
6683 /// [ -1, 4, zz, -1 ]
6684 /// PSRL : (little-endian) right bit shift.
6686 /// [ -1, -1, 7, zz]
6687 /// PSLLDQ : (little-endian) left byte shift
6688 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6689 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6690 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6691 /// PSRLDQ : (little-endian) right byte shift
6692 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6693 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6694 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6695 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6696 SDValue V2, ArrayRef<int> Mask,
6697 SelectionDAG &DAG) {
6698 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6700 int Size = Mask.size();
6701 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6703 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6704 for (int i = 0; i < Size; i += Scale)
6705 for (int j = 0; j < Shift; ++j)
6706 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6712 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6713 for (int i = 0; i != Size; i += Scale) {
6714 unsigned Pos = Left ? i + Shift : i;
6715 unsigned Low = Left ? i : i + Shift;
6716 unsigned Len = Scale - Shift;
6717 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6718 Low + (V == V1 ? 0 : Size)))
6722 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6723 bool ByteShift = ShiftEltBits > 64;
6724 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6725 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6726 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6728 // Normalize the scale for byte shifts to still produce an i64 element
6730 Scale = ByteShift ? Scale / 2 : Scale;
6732 // We need to round trip through the appropriate type for the shift.
6733 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6734 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6735 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6736 "Illegal integer vector type");
6737 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6739 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6740 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6741 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6744 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6745 // keep doubling the size of the integer elements up to that. We can
6746 // then shift the elements of the integer vector by whole multiples of
6747 // their width within the elements of the larger integer vector. Test each
6748 // multiple to see if we can find a match with the moved element indices
6749 // and that the shifted in elements are all zeroable.
6750 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6751 for (int Shift = 1; Shift != Scale; ++Shift)
6752 for (bool Left : {true, false})
6753 if (CheckZeros(Shift, Scale, Left))
6754 for (SDValue V : {V1, V2})
6755 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6762 /// \brief Lower a vector shuffle as a zero or any extension.
6764 /// Given a specific number of elements, element bit width, and extension
6765 /// stride, produce either a zero or any extension based on the available
6766 /// features of the subtarget.
6767 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6768 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6769 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6770 assert(Scale > 1 && "Need a scale to extend.");
6771 int NumElements = VT.getVectorNumElements();
6772 int EltBits = VT.getScalarSizeInBits();
6773 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6774 "Only 8, 16, and 32 bit elements can be extended.");
6775 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6777 // Found a valid zext mask! Try various lowering strategies based on the
6778 // input type and available ISA extensions.
6779 if (Subtarget->hasSSE41()) {
6780 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6781 NumElements / Scale);
6782 return DAG.getNode(ISD::BITCAST, DL, VT,
6783 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6786 // For any extends we can cheat for larger element sizes and use shuffle
6787 // instructions that can fold with a load and/or copy.
6788 if (AnyExt && EltBits == 32) {
6789 int PSHUFDMask[4] = {0, -1, 1, -1};
6791 ISD::BITCAST, DL, VT,
6792 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6793 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6794 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6796 if (AnyExt && EltBits == 16 && Scale > 2) {
6797 int PSHUFDMask[4] = {0, -1, 0, -1};
6798 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6799 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6800 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6801 int PSHUFHWMask[4] = {1, -1, -1, -1};
6803 ISD::BITCAST, DL, VT,
6804 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6805 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6806 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6809 // If this would require more than 2 unpack instructions to expand, use
6810 // pshufb when available. We can only use more than 2 unpack instructions
6811 // when zero extending i8 elements which also makes it easier to use pshufb.
6812 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6813 assert(NumElements == 16 && "Unexpected byte vector width!");
6814 SDValue PSHUFBMask[16];
6815 for (int i = 0; i < 16; ++i)
6817 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6818 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6819 return DAG.getNode(ISD::BITCAST, DL, VT,
6820 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6821 DAG.getNode(ISD::BUILD_VECTOR, DL,
6822 MVT::v16i8, PSHUFBMask)));
6825 // Otherwise emit a sequence of unpacks.
6827 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6828 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6829 : getZeroVector(InputVT, Subtarget, DAG, DL);
6830 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6831 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6835 } while (Scale > 1);
6836 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6839 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6841 /// This routine will try to do everything in its power to cleverly lower
6842 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6843 /// check for the profitability of this lowering, it tries to aggressively
6844 /// match this pattern. It will use all of the micro-architectural details it
6845 /// can to emit an efficient lowering. It handles both blends with all-zero
6846 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6847 /// masking out later).
6849 /// The reason we have dedicated lowering for zext-style shuffles is that they
6850 /// are both incredibly common and often quite performance sensitive.
6851 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6852 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6853 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6854 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6856 int Bits = VT.getSizeInBits();
6857 int NumElements = VT.getVectorNumElements();
6858 assert(VT.getScalarSizeInBits() <= 32 &&
6859 "Exceeds 32-bit integer zero extension limit");
6860 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6862 // Define a helper function to check a particular ext-scale and lower to it if
6864 auto Lower = [&](int Scale) -> SDValue {
6867 for (int i = 0; i < NumElements; ++i) {
6869 continue; // Valid anywhere but doesn't tell us anything.
6870 if (i % Scale != 0) {
6871 // Each of the extended elements need to be zeroable.
6875 // We no longer are in the anyext case.
6880 // Each of the base elements needs to be consecutive indices into the
6881 // same input vector.
6882 SDValue V = Mask[i] < NumElements ? V1 : V2;
6885 else if (InputV != V)
6886 return SDValue(); // Flip-flopping inputs.
6888 if (Mask[i] % NumElements != i / Scale)
6889 return SDValue(); // Non-consecutive strided elements.
6892 // If we fail to find an input, we have a zero-shuffle which should always
6893 // have already been handled.
6894 // FIXME: Maybe handle this here in case during blending we end up with one?
6898 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6899 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6902 // The widest scale possible for extending is to a 64-bit integer.
6903 assert(Bits % 64 == 0 &&
6904 "The number of bits in a vector must be divisible by 64 on x86!");
6905 int NumExtElements = Bits / 64;
6907 // Each iteration, try extending the elements half as much, but into twice as
6909 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6910 assert(NumElements % NumExtElements == 0 &&
6911 "The input vector size must be divisible by the extended size.");
6912 if (SDValue V = Lower(NumElements / NumExtElements))
6916 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6920 // Returns one of the source operands if the shuffle can be reduced to a
6921 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6922 auto CanZExtLowHalf = [&]() {
6923 for (int i = NumElements / 2; i != NumElements; ++i)
6926 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6928 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6933 if (SDValue V = CanZExtLowHalf()) {
6934 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6935 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6936 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6939 // No viable ext lowering found.
6943 /// \brief Try to get a scalar value for a specific element of a vector.
6945 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6946 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6947 SelectionDAG &DAG) {
6948 MVT VT = V.getSimpleValueType();
6949 MVT EltVT = VT.getVectorElementType();
6950 while (V.getOpcode() == ISD::BITCAST)
6951 V = V.getOperand(0);
6952 // If the bitcasts shift the element size, we can't extract an equivalent
6954 MVT NewVT = V.getSimpleValueType();
6955 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
6958 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6959 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
6960 // Ensure the scalar operand is the same size as the destination.
6961 // FIXME: Add support for scalar truncation where possible.
6962 SDValue S = V.getOperand(Idx);
6963 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
6964 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
6970 /// \brief Helper to test for a load that can be folded with x86 shuffles.
6972 /// This is particularly important because the set of instructions varies
6973 /// significantly based on whether the operand is a load or not.
6974 static bool isShuffleFoldableLoad(SDValue V) {
6975 while (V.getOpcode() == ISD::BITCAST)
6976 V = V.getOperand(0);
6978 return ISD::isNON_EXTLoad(V.getNode());
6981 /// \brief Try to lower insertion of a single element into a zero vector.
6983 /// This is a common pattern that we have especially efficient patterns to lower
6984 /// across all subtarget feature sets.
6985 static SDValue lowerVectorShuffleAsElementInsertion(
6986 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6987 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6988 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6990 MVT EltVT = VT.getVectorElementType();
6992 int V2Index = std::find_if(Mask.begin(), Mask.end(),
6993 [&Mask](int M) { return M >= (int)Mask.size(); }) -
6995 bool IsV1Zeroable = true;
6996 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6997 if (i != V2Index && !Zeroable[i]) {
6998 IsV1Zeroable = false;
7002 // Check for a single input from a SCALAR_TO_VECTOR node.
7003 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7004 // all the smarts here sunk into that routine. However, the current
7005 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7006 // vector shuffle lowering is dead.
7007 if (SDValue V2S = getScalarValueForVectorElement(
7008 V2, Mask[V2Index] - Mask.size(), DAG)) {
7009 // We need to zext the scalar if it is smaller than an i32.
7010 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7011 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7012 // Using zext to expand a narrow element won't work for non-zero
7017 // Zero-extend directly to i32.
7019 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7021 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7022 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7023 EltVT == MVT::i16) {
7024 // Either not inserting from the low element of the input or the input
7025 // element size is too small to use VZEXT_MOVL to clear the high bits.
7029 if (!IsV1Zeroable) {
7030 // If V1 can't be treated as a zero vector we have fewer options to lower
7031 // this. We can't support integer vectors or non-zero targets cheaply, and
7032 // the V1 elements can't be permuted in any way.
7033 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7034 if (!VT.isFloatingPoint() || V2Index != 0)
7036 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7037 V1Mask[V2Index] = -1;
7038 if (!isNoopShuffleMask(V1Mask))
7040 // This is essentially a special case blend operation, but if we have
7041 // general purpose blend operations, they are always faster. Bail and let
7042 // the rest of the lowering handle these as blends.
7043 if (Subtarget->hasSSE41())
7046 // Otherwise, use MOVSD or MOVSS.
7047 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7048 "Only two types of floating point element types to handle!");
7049 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7053 // This lowering only works for the low element with floating point vectors.
7054 if (VT.isFloatingPoint() && V2Index != 0)
7057 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7059 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7062 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7063 // the desired position. Otherwise it is more efficient to do a vector
7064 // shift left. We know that we can do a vector shift left because all
7065 // the inputs are zero.
7066 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7067 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7068 V2Shuffle[V2Index] = 0;
7069 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7071 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7073 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7075 V2Index * EltVT.getSizeInBits()/8, DL,
7076 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7077 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7083 /// \brief Try to lower broadcast of a single element.
7085 /// For convenience, this code also bundles all of the subtarget feature set
7086 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7087 /// a convenient way to factor it out.
7088 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7090 const X86Subtarget *Subtarget,
7091 SelectionDAG &DAG) {
7092 if (!Subtarget->hasAVX())
7094 if (VT.isInteger() && !Subtarget->hasAVX2())
7097 // Check that the mask is a broadcast.
7098 int BroadcastIdx = -1;
7100 if (M >= 0 && BroadcastIdx == -1)
7102 else if (M >= 0 && M != BroadcastIdx)
7105 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7106 "a sorted mask where the broadcast "
7109 // Go up the chain of (vector) values to find a scalar load that we can
7110 // combine with the broadcast.
7112 switch (V.getOpcode()) {
7113 case ISD::CONCAT_VECTORS: {
7114 int OperandSize = Mask.size() / V.getNumOperands();
7115 V = V.getOperand(BroadcastIdx / OperandSize);
7116 BroadcastIdx %= OperandSize;
7120 case ISD::INSERT_SUBVECTOR: {
7121 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7122 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7126 int BeginIdx = (int)ConstantIdx->getZExtValue();
7128 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7129 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7130 BroadcastIdx -= BeginIdx;
7141 // Check if this is a broadcast of a scalar. We special case lowering
7142 // for scalars so that we can more effectively fold with loads.
7143 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7144 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7145 V = V.getOperand(BroadcastIdx);
7147 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7148 // Only AVX2 has register broadcasts.
7149 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7151 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7152 // We can't broadcast from a vector register without AVX2, and we can only
7153 // broadcast from the zero-element of a vector register.
7157 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7160 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7161 // INSERTPS when the V1 elements are already in the correct locations
7162 // because otherwise we can just always use two SHUFPS instructions which
7163 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7164 // perform INSERTPS if a single V1 element is out of place and all V2
7165 // elements are zeroable.
7166 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7168 SelectionDAG &DAG) {
7169 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7170 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7171 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7172 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7174 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7177 int V1DstIndex = -1;
7178 int V2DstIndex = -1;
7179 bool V1UsedInPlace = false;
7181 for (int i = 0; i < 4; ++i) {
7182 // Synthesize a zero mask from the zeroable elements (includes undefs).
7188 // Flag if we use any V1 inputs in place.
7190 V1UsedInPlace = true;
7194 // We can only insert a single non-zeroable element.
7195 if (V1DstIndex != -1 || V2DstIndex != -1)
7199 // V1 input out of place for insertion.
7202 // V2 input for insertion.
7207 // Don't bother if we have no (non-zeroable) element for insertion.
7208 if (V1DstIndex == -1 && V2DstIndex == -1)
7211 // Determine element insertion src/dst indices. The src index is from the
7212 // start of the inserted vector, not the start of the concatenated vector.
7213 unsigned V2SrcIndex = 0;
7214 if (V1DstIndex != -1) {
7215 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7216 // and don't use the original V2 at all.
7217 V2SrcIndex = Mask[V1DstIndex];
7218 V2DstIndex = V1DstIndex;
7221 V2SrcIndex = Mask[V2DstIndex] - 4;
7224 // If no V1 inputs are used in place, then the result is created only from
7225 // the zero mask and the V2 insertion - so remove V1 dependency.
7227 V1 = DAG.getUNDEF(MVT::v4f32);
7229 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7230 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7232 // Insert the V2 element into the desired position.
7234 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7235 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7238 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7239 /// UNPCK instruction.
7241 /// This specifically targets cases where we end up with alternating between
7242 /// the two inputs, and so can permute them into something that feeds a single
7243 /// UNPCK instruction. Note that this routine only targets integer vectors
7244 /// because for floating point vectors we have a generalized SHUFPS lowering
7245 /// strategy that handles everything that doesn't *exactly* match an unpack,
7246 /// making this clever lowering unnecessary.
7247 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7248 SDValue V2, ArrayRef<int> Mask,
7249 SelectionDAG &DAG) {
7250 assert(!VT.isFloatingPoint() &&
7251 "This routine only supports integer vectors.");
7252 assert(!isSingleInputShuffleMask(Mask) &&
7253 "This routine should only be used when blending two inputs.");
7254 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7256 int Size = Mask.size();
7258 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7259 return M >= 0 && M % Size < Size / 2;
7261 int NumHiInputs = std::count_if(
7262 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7264 bool UnpackLo = NumLoInputs >= NumHiInputs;
7266 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7267 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7268 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7270 for (int i = 0; i < Size; ++i) {
7274 // Each element of the unpack contains Scale elements from this mask.
7275 int UnpackIdx = i / Scale;
7277 // We only handle the case where V1 feeds the first slots of the unpack.
7278 // We rely on canonicalization to ensure this is the case.
7279 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7282 // Setup the mask for this input. The indexing is tricky as we have to
7283 // handle the unpack stride.
7284 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7285 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7289 // If we will have to shuffle both inputs to use the unpack, check whether
7290 // we can just unpack first and shuffle the result. If so, skip this unpack.
7291 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7292 !isNoopShuffleMask(V2Mask))
7295 // Shuffle the inputs into place.
7296 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7297 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7299 // Cast the inputs to the type we will use to unpack them.
7300 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7301 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7303 // Unpack the inputs and cast the result back to the desired type.
7304 return DAG.getNode(ISD::BITCAST, DL, VT,
7305 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7306 DL, UnpackVT, V1, V2));
7309 // We try each unpack from the largest to the smallest to try and find one
7310 // that fits this mask.
7311 int OrigNumElements = VT.getVectorNumElements();
7312 int OrigScalarSize = VT.getScalarSizeInBits();
7313 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7314 int Scale = ScalarSize / OrigScalarSize;
7315 int NumElements = OrigNumElements / Scale;
7316 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7317 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7321 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7323 if (NumLoInputs == 0 || NumHiInputs == 0) {
7324 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7325 "We have to have *some* inputs!");
7326 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7328 // FIXME: We could consider the total complexity of the permute of each
7329 // possible unpacking. Or at the least we should consider how many
7330 // half-crossings are created.
7331 // FIXME: We could consider commuting the unpacks.
7333 SmallVector<int, 32> PermMask;
7334 PermMask.assign(Size, -1);
7335 for (int i = 0; i < Size; ++i) {
7339 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7342 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7344 return DAG.getVectorShuffle(
7345 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7347 DAG.getUNDEF(VT), PermMask);
7353 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7355 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7356 /// support for floating point shuffles but not integer shuffles. These
7357 /// instructions will incur a domain crossing penalty on some chips though so
7358 /// it is better to avoid lowering through this for integer vectors where
7360 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7361 const X86Subtarget *Subtarget,
7362 SelectionDAG &DAG) {
7364 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7365 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7366 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7367 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7368 ArrayRef<int> Mask = SVOp->getMask();
7369 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7371 if (isSingleInputShuffleMask(Mask)) {
7372 // Use low duplicate instructions for masks that match their pattern.
7373 if (Subtarget->hasSSE3())
7374 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7375 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7377 // Straight shuffle of a single input vector. Simulate this by using the
7378 // single input as both of the "inputs" to this instruction..
7379 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7381 if (Subtarget->hasAVX()) {
7382 // If we have AVX, we can use VPERMILPS which will allow folding a load
7383 // into the shuffle.
7384 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7385 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7388 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7389 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7391 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7392 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7394 // If we have a single input, insert that into V1 if we can do so cheaply.
7395 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7396 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7397 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7399 // Try inverting the insertion since for v2 masks it is easy to do and we
7400 // can't reliably sort the mask one way or the other.
7401 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7402 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7403 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7404 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7408 // Try to use one of the special instruction patterns to handle two common
7409 // blend patterns if a zero-blend above didn't work.
7410 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7411 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7412 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7413 // We can either use a special instruction to load over the low double or
7414 // to move just the low double.
7416 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7418 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7420 if (Subtarget->hasSSE41())
7421 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7425 // Use dedicated unpack instructions for masks that match their pattern.
7426 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7427 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7428 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7429 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7431 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7432 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7433 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7436 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7438 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7439 /// the integer unit to minimize domain crossing penalties. However, for blends
7440 /// it falls back to the floating point shuffle operation with appropriate bit
7442 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7443 const X86Subtarget *Subtarget,
7444 SelectionDAG &DAG) {
7446 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7447 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7448 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7449 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7450 ArrayRef<int> Mask = SVOp->getMask();
7451 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7453 if (isSingleInputShuffleMask(Mask)) {
7454 // Check for being able to broadcast a single element.
7455 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7456 Mask, Subtarget, DAG))
7459 // Straight shuffle of a single input vector. For everything from SSE2
7460 // onward this has a single fast instruction with no scary immediates.
7461 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7462 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7463 int WidenedMask[4] = {
7464 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7465 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7467 ISD::BITCAST, DL, MVT::v2i64,
7468 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7469 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7471 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7472 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7473 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7474 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7476 // If we have a blend of two PACKUS operations an the blend aligns with the
7477 // low and half halves, we can just merge the PACKUS operations. This is
7478 // particularly important as it lets us merge shuffles that this routine itself
7480 auto GetPackNode = [](SDValue V) {
7481 while (V.getOpcode() == ISD::BITCAST)
7482 V = V.getOperand(0);
7484 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7486 if (SDValue V1Pack = GetPackNode(V1))
7487 if (SDValue V2Pack = GetPackNode(V2))
7488 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7489 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7490 Mask[0] == 0 ? V1Pack.getOperand(0)
7491 : V1Pack.getOperand(1),
7492 Mask[1] == 2 ? V2Pack.getOperand(0)
7493 : V2Pack.getOperand(1)));
7495 // Try to use shift instructions.
7497 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7500 // When loading a scalar and then shuffling it into a vector we can often do
7501 // the insertion cheaply.
7502 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7503 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7505 // Try inverting the insertion since for v2 masks it is easy to do and we
7506 // can't reliably sort the mask one way or the other.
7507 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7508 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7509 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7512 // We have different paths for blend lowering, but they all must use the
7513 // *exact* same predicate.
7514 bool IsBlendSupported = Subtarget->hasSSE41();
7515 if (IsBlendSupported)
7516 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7520 // Use dedicated unpack instructions for masks that match their pattern.
7521 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7522 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7523 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7524 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7526 // Try to use byte rotation instructions.
7527 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7528 if (Subtarget->hasSSSE3())
7529 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7530 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7533 // If we have direct support for blends, we should lower by decomposing into
7534 // a permute. That will be faster than the domain cross.
7535 if (IsBlendSupported)
7536 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7539 // We implement this with SHUFPD which is pretty lame because it will likely
7540 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7541 // However, all the alternatives are still more cycles and newer chips don't
7542 // have this problem. It would be really nice if x86 had better shuffles here.
7543 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7544 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7545 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7546 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7549 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7551 /// This is used to disable more specialized lowerings when the shufps lowering
7552 /// will happen to be efficient.
7553 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7554 // This routine only handles 128-bit shufps.
7555 assert(Mask.size() == 4 && "Unsupported mask size!");
7557 // To lower with a single SHUFPS we need to have the low half and high half
7558 // each requiring a single input.
7559 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7561 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7567 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7569 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7570 /// It makes no assumptions about whether this is the *best* lowering, it simply
7572 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7573 ArrayRef<int> Mask, SDValue V1,
7574 SDValue V2, SelectionDAG &DAG) {
7575 SDValue LowV = V1, HighV = V2;
7576 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7579 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7581 if (NumV2Elements == 1) {
7583 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7586 // Compute the index adjacent to V2Index and in the same half by toggling
7588 int V2AdjIndex = V2Index ^ 1;
7590 if (Mask[V2AdjIndex] == -1) {
7591 // Handles all the cases where we have a single V2 element and an undef.
7592 // This will only ever happen in the high lanes because we commute the
7593 // vector otherwise.
7595 std::swap(LowV, HighV);
7596 NewMask[V2Index] -= 4;
7598 // Handle the case where the V2 element ends up adjacent to a V1 element.
7599 // To make this work, blend them together as the first step.
7600 int V1Index = V2AdjIndex;
7601 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7602 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7603 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7605 // Now proceed to reconstruct the final blend as we have the necessary
7606 // high or low half formed.
7613 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7614 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7616 } else if (NumV2Elements == 2) {
7617 if (Mask[0] < 4 && Mask[1] < 4) {
7618 // Handle the easy case where we have V1 in the low lanes and V2 in the
7622 } else if (Mask[2] < 4 && Mask[3] < 4) {
7623 // We also handle the reversed case because this utility may get called
7624 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7625 // arrange things in the right direction.
7631 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7632 // trying to place elements directly, just blend them and set up the final
7633 // shuffle to place them.
7635 // The first two blend mask elements are for V1, the second two are for
7637 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7638 Mask[2] < 4 ? Mask[2] : Mask[3],
7639 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7640 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7641 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7642 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7644 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7647 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7648 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7649 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7650 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7653 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7654 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7657 /// \brief Lower 4-lane 32-bit floating point shuffles.
7659 /// Uses instructions exclusively from the floating point unit to minimize
7660 /// domain crossing penalties, as these are sufficient to implement all v4f32
7662 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7663 const X86Subtarget *Subtarget,
7664 SelectionDAG &DAG) {
7666 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7667 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7668 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7669 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7670 ArrayRef<int> Mask = SVOp->getMask();
7671 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7674 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7676 if (NumV2Elements == 0) {
7677 // Check for being able to broadcast a single element.
7678 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7679 Mask, Subtarget, DAG))
7682 // Use even/odd duplicate instructions for masks that match their pattern.
7683 if (Subtarget->hasSSE3()) {
7684 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7685 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7686 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7687 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7690 if (Subtarget->hasAVX()) {
7691 // If we have AVX, we can use VPERMILPS which will allow folding a load
7692 // into the shuffle.
7693 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7694 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7697 // Otherwise, use a straight shuffle of a single input vector. We pass the
7698 // input vector to both operands to simulate this with a SHUFPS.
7699 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7700 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7703 // There are special ways we can lower some single-element blends. However, we
7704 // have custom ways we can lower more complex single-element blends below that
7705 // we defer to if both this and BLENDPS fail to match, so restrict this to
7706 // when the V2 input is targeting element 0 of the mask -- that is the fast
7708 if (NumV2Elements == 1 && Mask[0] >= 4)
7709 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7710 Mask, Subtarget, DAG))
7713 if (Subtarget->hasSSE41()) {
7714 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7718 // Use INSERTPS if we can complete the shuffle efficiently.
7719 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7722 if (!isSingleSHUFPSMask(Mask))
7723 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7724 DL, MVT::v4f32, V1, V2, Mask, DAG))
7728 // Use dedicated unpack instructions for masks that match their pattern.
7729 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7730 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7731 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7732 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7733 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7734 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7735 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7736 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7738 // Otherwise fall back to a SHUFPS lowering strategy.
7739 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7742 /// \brief Lower 4-lane i32 vector shuffles.
7744 /// We try to handle these with integer-domain shuffles where we can, but for
7745 /// blends we use the floating point domain blend instructions.
7746 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7747 const X86Subtarget *Subtarget,
7748 SelectionDAG &DAG) {
7750 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7751 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7752 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7753 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7754 ArrayRef<int> Mask = SVOp->getMask();
7755 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7757 // Whenever we can lower this as a zext, that instruction is strictly faster
7758 // than any alternative. It also allows us to fold memory operands into the
7759 // shuffle in many cases.
7760 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7761 Mask, Subtarget, DAG))
7765 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7767 if (NumV2Elements == 0) {
7768 // Check for being able to broadcast a single element.
7769 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7770 Mask, Subtarget, DAG))
7773 // Straight shuffle of a single input vector. For everything from SSE2
7774 // onward this has a single fast instruction with no scary immediates.
7775 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7776 // but we aren't actually going to use the UNPCK instruction because doing
7777 // so prevents folding a load into this instruction or making a copy.
7778 const int UnpackLoMask[] = {0, 0, 1, 1};
7779 const int UnpackHiMask[] = {2, 2, 3, 3};
7780 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7781 Mask = UnpackLoMask;
7782 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7783 Mask = UnpackHiMask;
7785 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7786 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7789 // Try to use shift instructions.
7791 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7794 // There are special ways we can lower some single-element blends.
7795 if (NumV2Elements == 1)
7796 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7797 Mask, Subtarget, DAG))
7800 // We have different paths for blend lowering, but they all must use the
7801 // *exact* same predicate.
7802 bool IsBlendSupported = Subtarget->hasSSE41();
7803 if (IsBlendSupported)
7804 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7808 if (SDValue Masked =
7809 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7812 // Use dedicated unpack instructions for masks that match their pattern.
7813 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7814 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7815 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7816 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7817 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7818 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7819 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7820 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7822 // Try to use byte rotation instructions.
7823 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7824 if (Subtarget->hasSSSE3())
7825 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7826 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7829 // If we have direct support for blends, we should lower by decomposing into
7830 // a permute. That will be faster than the domain cross.
7831 if (IsBlendSupported)
7832 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7835 // Try to lower by permuting the inputs into an unpack instruction.
7836 if (SDValue Unpack =
7837 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7840 // We implement this with SHUFPS because it can blend from two vectors.
7841 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7842 // up the inputs, bypassing domain shift penalties that we would encur if we
7843 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7845 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7846 DAG.getVectorShuffle(
7848 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7849 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7852 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7853 /// shuffle lowering, and the most complex part.
7855 /// The lowering strategy is to try to form pairs of input lanes which are
7856 /// targeted at the same half of the final vector, and then use a dword shuffle
7857 /// to place them onto the right half, and finally unpack the paired lanes into
7858 /// their final position.
7860 /// The exact breakdown of how to form these dword pairs and align them on the
7861 /// correct sides is really tricky. See the comments within the function for
7862 /// more of the details.
7864 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7865 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7866 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7867 /// vector, form the analogous 128-bit 8-element Mask.
7868 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7869 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7870 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7871 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7872 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7874 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7875 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7876 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7878 SmallVector<int, 4> LoInputs;
7879 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7880 [](int M) { return M >= 0; });
7881 std::sort(LoInputs.begin(), LoInputs.end());
7882 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7883 SmallVector<int, 4> HiInputs;
7884 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7885 [](int M) { return M >= 0; });
7886 std::sort(HiInputs.begin(), HiInputs.end());
7887 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7889 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7890 int NumHToL = LoInputs.size() - NumLToL;
7892 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7893 int NumHToH = HiInputs.size() - NumLToH;
7894 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7895 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7896 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7897 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7899 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7900 // such inputs we can swap two of the dwords across the half mark and end up
7901 // with <=2 inputs to each half in each half. Once there, we can fall through
7902 // to the generic code below. For example:
7904 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7905 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7907 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7908 // and an existing 2-into-2 on the other half. In this case we may have to
7909 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7910 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7911 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7912 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7913 // half than the one we target for fixing) will be fixed when we re-enter this
7914 // path. We will also combine away any sequence of PSHUFD instructions that
7915 // result into a single instruction. Here is an example of the tricky case:
7917 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7918 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7920 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7922 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7923 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7925 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7926 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7928 // The result is fine to be handled by the generic logic.
7929 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7930 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7931 int AOffset, int BOffset) {
7932 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7933 "Must call this with A having 3 or 1 inputs from the A half.");
7934 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7935 "Must call this with B having 1 or 3 inputs from the B half.");
7936 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7937 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7939 // Compute the index of dword with only one word among the three inputs in
7940 // a half by taking the sum of the half with three inputs and subtracting
7941 // the sum of the actual three inputs. The difference is the remaining
7944 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7945 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7946 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7947 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7948 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7949 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7950 int TripleNonInputIdx =
7951 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7952 TripleDWord = TripleNonInputIdx / 2;
7954 // We use xor with one to compute the adjacent DWord to whichever one the
7956 OneInputDWord = (OneInput / 2) ^ 1;
7958 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7959 // and BToA inputs. If there is also such a problem with the BToB and AToB
7960 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7961 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7962 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7963 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7964 // Compute how many inputs will be flipped by swapping these DWords. We
7966 // to balance this to ensure we don't form a 3-1 shuffle in the other
7968 int NumFlippedAToBInputs =
7969 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7970 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7971 int NumFlippedBToBInputs =
7972 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7973 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7974 if ((NumFlippedAToBInputs == 1 &&
7975 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7976 (NumFlippedBToBInputs == 1 &&
7977 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7978 // We choose whether to fix the A half or B half based on whether that
7979 // half has zero flipped inputs. At zero, we may not be able to fix it
7980 // with that half. We also bias towards fixing the B half because that
7981 // will more commonly be the high half, and we have to bias one way.
7982 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7983 ArrayRef<int> Inputs) {
7984 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7985 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7986 PinnedIdx ^ 1) != Inputs.end();
7987 // Determine whether the free index is in the flipped dword or the
7988 // unflipped dword based on where the pinned index is. We use this bit
7989 // in an xor to conditionally select the adjacent dword.
7990 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7991 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7992 FixFreeIdx) != Inputs.end();
7993 if (IsFixIdxInput == IsFixFreeIdxInput)
7995 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7996 FixFreeIdx) != Inputs.end();
7997 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7998 "We need to be changing the number of flipped inputs!");
7999 int PSHUFHalfMask[] = {0, 1, 2, 3};
8000 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8001 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8003 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8006 if (M != -1 && M == FixIdx)
8008 else if (M != -1 && M == FixFreeIdx)
8011 if (NumFlippedBToBInputs != 0) {
8013 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8014 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8016 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8018 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8019 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8024 int PSHUFDMask[] = {0, 1, 2, 3};
8025 PSHUFDMask[ADWord] = BDWord;
8026 PSHUFDMask[BDWord] = ADWord;
8027 V = DAG.getNode(ISD::BITCAST, DL, VT,
8028 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8029 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8030 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8033 // Adjust the mask to match the new locations of A and B.
8035 if (M != -1 && M/2 == ADWord)
8036 M = 2 * BDWord + M % 2;
8037 else if (M != -1 && M/2 == BDWord)
8038 M = 2 * ADWord + M % 2;
8040 // Recurse back into this routine to re-compute state now that this isn't
8041 // a 3 and 1 problem.
8042 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8045 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8046 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8047 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8048 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8050 // At this point there are at most two inputs to the low and high halves from
8051 // each half. That means the inputs can always be grouped into dwords and
8052 // those dwords can then be moved to the correct half with a dword shuffle.
8053 // We use at most one low and one high word shuffle to collect these paired
8054 // inputs into dwords, and finally a dword shuffle to place them.
8055 int PSHUFLMask[4] = {-1, -1, -1, -1};
8056 int PSHUFHMask[4] = {-1, -1, -1, -1};
8057 int PSHUFDMask[4] = {-1, -1, -1, -1};
8059 // First fix the masks for all the inputs that are staying in their
8060 // original halves. This will then dictate the targets of the cross-half
8062 auto fixInPlaceInputs =
8063 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8064 MutableArrayRef<int> SourceHalfMask,
8065 MutableArrayRef<int> HalfMask, int HalfOffset) {
8066 if (InPlaceInputs.empty())
8068 if (InPlaceInputs.size() == 1) {
8069 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8070 InPlaceInputs[0] - HalfOffset;
8071 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8074 if (IncomingInputs.empty()) {
8075 // Just fix all of the in place inputs.
8076 for (int Input : InPlaceInputs) {
8077 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8078 PSHUFDMask[Input / 2] = Input / 2;
8083 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8084 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8085 InPlaceInputs[0] - HalfOffset;
8086 // Put the second input next to the first so that they are packed into
8087 // a dword. We find the adjacent index by toggling the low bit.
8088 int AdjIndex = InPlaceInputs[0] ^ 1;
8089 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8090 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8091 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8093 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8094 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8096 // Now gather the cross-half inputs and place them into a free dword of
8097 // their target half.
8098 // FIXME: This operation could almost certainly be simplified dramatically to
8099 // look more like the 3-1 fixing operation.
8100 auto moveInputsToRightHalf = [&PSHUFDMask](
8101 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8102 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8103 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8105 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8106 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8108 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8110 int LowWord = Word & ~1;
8111 int HighWord = Word | 1;
8112 return isWordClobbered(SourceHalfMask, LowWord) ||
8113 isWordClobbered(SourceHalfMask, HighWord);
8116 if (IncomingInputs.empty())
8119 if (ExistingInputs.empty()) {
8120 // Map any dwords with inputs from them into the right half.
8121 for (int Input : IncomingInputs) {
8122 // If the source half mask maps over the inputs, turn those into
8123 // swaps and use the swapped lane.
8124 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8125 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8126 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8127 Input - SourceOffset;
8128 // We have to swap the uses in our half mask in one sweep.
8129 for (int &M : HalfMask)
8130 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8132 else if (M == Input)
8133 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8135 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8136 Input - SourceOffset &&
8137 "Previous placement doesn't match!");
8139 // Note that this correctly re-maps both when we do a swap and when
8140 // we observe the other side of the swap above. We rely on that to
8141 // avoid swapping the members of the input list directly.
8142 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8145 // Map the input's dword into the correct half.
8146 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8147 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8149 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8151 "Previous placement doesn't match!");
8154 // And just directly shift any other-half mask elements to be same-half
8155 // as we will have mirrored the dword containing the element into the
8156 // same position within that half.
8157 for (int &M : HalfMask)
8158 if (M >= SourceOffset && M < SourceOffset + 4) {
8159 M = M - SourceOffset + DestOffset;
8160 assert(M >= 0 && "This should never wrap below zero!");
8165 // Ensure we have the input in a viable dword of its current half. This
8166 // is particularly tricky because the original position may be clobbered
8167 // by inputs being moved and *staying* in that half.
8168 if (IncomingInputs.size() == 1) {
8169 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8170 int InputFixed = std::find(std::begin(SourceHalfMask),
8171 std::end(SourceHalfMask), -1) -
8172 std::begin(SourceHalfMask) + SourceOffset;
8173 SourceHalfMask[InputFixed - SourceOffset] =
8174 IncomingInputs[0] - SourceOffset;
8175 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8177 IncomingInputs[0] = InputFixed;
8179 } else if (IncomingInputs.size() == 2) {
8180 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8181 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8182 // We have two non-adjacent or clobbered inputs we need to extract from
8183 // the source half. To do this, we need to map them into some adjacent
8184 // dword slot in the source mask.
8185 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8186 IncomingInputs[1] - SourceOffset};
8188 // If there is a free slot in the source half mask adjacent to one of
8189 // the inputs, place the other input in it. We use (Index XOR 1) to
8190 // compute an adjacent index.
8191 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8192 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8193 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8194 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8195 InputsFixed[1] = InputsFixed[0] ^ 1;
8196 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8197 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8198 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8199 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8200 InputsFixed[0] = InputsFixed[1] ^ 1;
8201 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8202 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8203 // The two inputs are in the same DWord but it is clobbered and the
8204 // adjacent DWord isn't used at all. Move both inputs to the free
8206 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8207 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8208 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8209 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8211 // The only way we hit this point is if there is no clobbering
8212 // (because there are no off-half inputs to this half) and there is no
8213 // free slot adjacent to one of the inputs. In this case, we have to
8214 // swap an input with a non-input.
8215 for (int i = 0; i < 4; ++i)
8216 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8217 "We can't handle any clobbers here!");
8218 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8219 "Cannot have adjacent inputs here!");
8221 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8222 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8224 // We also have to update the final source mask in this case because
8225 // it may need to undo the above swap.
8226 for (int &M : FinalSourceHalfMask)
8227 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8228 M = InputsFixed[1] + SourceOffset;
8229 else if (M == InputsFixed[1] + SourceOffset)
8230 M = (InputsFixed[0] ^ 1) + SourceOffset;
8232 InputsFixed[1] = InputsFixed[0] ^ 1;
8235 // Point everything at the fixed inputs.
8236 for (int &M : HalfMask)
8237 if (M == IncomingInputs[0])
8238 M = InputsFixed[0] + SourceOffset;
8239 else if (M == IncomingInputs[1])
8240 M = InputsFixed[1] + SourceOffset;
8242 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8243 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8246 llvm_unreachable("Unhandled input size!");
8249 // Now hoist the DWord down to the right half.
8250 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8251 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8252 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8253 for (int &M : HalfMask)
8254 for (int Input : IncomingInputs)
8256 M = FreeDWord * 2 + Input % 2;
8258 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8259 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8260 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8261 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8263 // Now enact all the shuffles we've computed to move the inputs into their
8265 if (!isNoopShuffleMask(PSHUFLMask))
8266 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8267 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8268 if (!isNoopShuffleMask(PSHUFHMask))
8269 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8270 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8271 if (!isNoopShuffleMask(PSHUFDMask))
8272 V = DAG.getNode(ISD::BITCAST, DL, VT,
8273 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8274 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8275 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,
8278 // At this point, each half should contain all its inputs, and we can then
8279 // just shuffle them into their final position.
8280 assert(std::count_if(LoMask.begin(), LoMask.end(),
8281 [](int M) { return M >= 4; }) == 0 &&
8282 "Failed to lift all the high half inputs to the low mask!");
8283 assert(std::count_if(HiMask.begin(), HiMask.end(),
8284 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8285 "Failed to lift all the low half inputs to the high mask!");
8287 // Do a half shuffle for the low mask.
8288 if (!isNoopShuffleMask(LoMask))
8289 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8290 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8292 // Do a half shuffle with the high mask after shifting its values down.
8293 for (int &M : HiMask)
8296 if (!isNoopShuffleMask(HiMask))
8297 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8298 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8303 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8304 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8305 SDValue V2, ArrayRef<int> Mask,
8306 SelectionDAG &DAG, bool &V1InUse,
8308 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8314 int Size = Mask.size();
8315 int Scale = 16 / Size;
8316 for (int i = 0; i < 16; ++i) {
8317 if (Mask[i / Scale] == -1) {
8318 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8320 const int ZeroMask = 0x80;
8321 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8323 int V2Idx = Mask[i / Scale] < Size
8325 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8326 if (Zeroable[i / Scale])
8327 V1Idx = V2Idx = ZeroMask;
8328 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8329 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8330 V1InUse |= (ZeroMask != V1Idx);
8331 V2InUse |= (ZeroMask != V2Idx);
8336 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8337 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8338 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8340 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8341 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8342 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8344 // If we need shuffled inputs from both, blend the two.
8346 if (V1InUse && V2InUse)
8347 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8349 V = V1InUse ? V1 : V2;
8351 // Cast the result back to the correct type.
8352 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8355 /// \brief Generic lowering of 8-lane i16 shuffles.
8357 /// This handles both single-input shuffles and combined shuffle/blends with
8358 /// two inputs. The single input shuffles are immediately delegated to
8359 /// a dedicated lowering routine.
8361 /// The blends are lowered in one of three fundamental ways. If there are few
8362 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8363 /// of the input is significantly cheaper when lowered as an interleaving of
8364 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8365 /// halves of the inputs separately (making them have relatively few inputs)
8366 /// and then concatenate them.
8367 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8368 const X86Subtarget *Subtarget,
8369 SelectionDAG &DAG) {
8371 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8372 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8373 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8374 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8375 ArrayRef<int> OrigMask = SVOp->getMask();
8376 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8377 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8378 MutableArrayRef<int> Mask(MaskStorage);
8380 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8382 // Whenever we can lower this as a zext, that instruction is strictly faster
8383 // than any alternative.
8384 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8385 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8388 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8390 auto isV2 = [](int M) { return M >= 8; };
8392 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8394 if (NumV2Inputs == 0) {
8395 // Check for being able to broadcast a single element.
8396 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8397 Mask, Subtarget, DAG))
8400 // Try to use shift instructions.
8402 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8405 // Use dedicated unpack instructions for masks that match their pattern.
8406 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8407 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8408 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8409 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8411 // Try to use byte rotation instructions.
8412 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8413 Mask, Subtarget, DAG))
8416 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8420 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8421 "All single-input shuffles should be canonicalized to be V1-input "
8424 // Try to use shift instructions.
8426 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8429 // There are special ways we can lower some single-element blends.
8430 if (NumV2Inputs == 1)
8431 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8432 Mask, Subtarget, DAG))
8435 // We have different paths for blend lowering, but they all must use the
8436 // *exact* same predicate.
8437 bool IsBlendSupported = Subtarget->hasSSE41();
8438 if (IsBlendSupported)
8439 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8443 if (SDValue Masked =
8444 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8447 // Use dedicated unpack instructions for masks that match their pattern.
8448 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8449 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8450 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8451 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8453 // Try to use byte rotation instructions.
8454 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8455 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8458 if (SDValue BitBlend =
8459 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8462 if (SDValue Unpack =
8463 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8466 // If we can't directly blend but can use PSHUFB, that will be better as it
8467 // can both shuffle and set up the inefficient blend.
8468 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8469 bool V1InUse, V2InUse;
8470 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8474 // We can always bit-blend if we have to so the fallback strategy is to
8475 // decompose into single-input permutes and blends.
8476 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8480 /// \brief Check whether a compaction lowering can be done by dropping even
8481 /// elements and compute how many times even elements must be dropped.
8483 /// This handles shuffles which take every Nth element where N is a power of
8484 /// two. Example shuffle masks:
8486 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8487 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8488 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8489 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8490 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8491 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8493 /// Any of these lanes can of course be undef.
8495 /// This routine only supports N <= 3.
8496 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8499 /// \returns N above, or the number of times even elements must be dropped if
8500 /// there is such a number. Otherwise returns zero.
8501 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8502 // Figure out whether we're looping over two inputs or just one.
8503 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8505 // The modulus for the shuffle vector entries is based on whether this is
8506 // a single input or not.
8507 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8508 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8509 "We should only be called with masks with a power-of-2 size!");
8511 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8513 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8514 // and 2^3 simultaneously. This is because we may have ambiguity with
8515 // partially undef inputs.
8516 bool ViableForN[3] = {true, true, true};
8518 for (int i = 0, e = Mask.size(); i < e; ++i) {
8519 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8524 bool IsAnyViable = false;
8525 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8526 if (ViableForN[j]) {
8529 // The shuffle mask must be equal to (i * 2^N) % M.
8530 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8533 ViableForN[j] = false;
8535 // Early exit if we exhaust the possible powers of two.
8540 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8544 // Return 0 as there is no viable power of two.
8548 /// \brief Generic lowering of v16i8 shuffles.
8550 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8551 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8552 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8553 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8555 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8556 const X86Subtarget *Subtarget,
8557 SelectionDAG &DAG) {
8559 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8560 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8561 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8562 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8563 ArrayRef<int> Mask = SVOp->getMask();
8564 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8566 // Try to use shift instructions.
8568 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8571 // Try to use byte rotation instructions.
8572 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8573 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8576 // Try to use a zext lowering.
8577 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8578 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8582 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8584 // For single-input shuffles, there are some nicer lowering tricks we can use.
8585 if (NumV2Elements == 0) {
8586 // Check for being able to broadcast a single element.
8587 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8588 Mask, Subtarget, DAG))
8591 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8592 // Notably, this handles splat and partial-splat shuffles more efficiently.
8593 // However, it only makes sense if the pre-duplication shuffle simplifies
8594 // things significantly. Currently, this means we need to be able to
8595 // express the pre-duplication shuffle as an i16 shuffle.
8597 // FIXME: We should check for other patterns which can be widened into an
8598 // i16 shuffle as well.
8599 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8600 for (int i = 0; i < 16; i += 2)
8601 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8606 auto tryToWidenViaDuplication = [&]() -> SDValue {
8607 if (!canWidenViaDuplication(Mask))
8609 SmallVector<int, 4> LoInputs;
8610 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8611 [](int M) { return M >= 0 && M < 8; });
8612 std::sort(LoInputs.begin(), LoInputs.end());
8613 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8615 SmallVector<int, 4> HiInputs;
8616 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8617 [](int M) { return M >= 8; });
8618 std::sort(HiInputs.begin(), HiInputs.end());
8619 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8622 bool TargetLo = LoInputs.size() >= HiInputs.size();
8623 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8624 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8626 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8627 SmallDenseMap<int, int, 8> LaneMap;
8628 for (int I : InPlaceInputs) {
8629 PreDupI16Shuffle[I/2] = I/2;
8632 int j = TargetLo ? 0 : 4, je = j + 4;
8633 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8634 // Check if j is already a shuffle of this input. This happens when
8635 // there are two adjacent bytes after we move the low one.
8636 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8637 // If we haven't yet mapped the input, search for a slot into which
8639 while (j < je && PreDupI16Shuffle[j] != -1)
8643 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8646 // Map this input with the i16 shuffle.
8647 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8650 // Update the lane map based on the mapping we ended up with.
8651 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8654 ISD::BITCAST, DL, MVT::v16i8,
8655 DAG.getVectorShuffle(MVT::v8i16, DL,
8656 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8657 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8659 // Unpack the bytes to form the i16s that will be shuffled into place.
8660 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8661 MVT::v16i8, V1, V1);
8663 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8664 for (int i = 0; i < 16; ++i)
8665 if (Mask[i] != -1) {
8666 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8667 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8668 if (PostDupI16Shuffle[i / 2] == -1)
8669 PostDupI16Shuffle[i / 2] = MappedMask;
8671 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8672 "Conflicting entrties in the original shuffle!");
8675 ISD::BITCAST, DL, MVT::v16i8,
8676 DAG.getVectorShuffle(MVT::v8i16, DL,
8677 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8678 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8680 if (SDValue V = tryToWidenViaDuplication())
8684 // Use dedicated unpack instructions for masks that match their pattern.
8685 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8686 0, 16, 1, 17, 2, 18, 3, 19,
8688 4, 20, 5, 21, 6, 22, 7, 23}))
8689 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8690 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8691 8, 24, 9, 25, 10, 26, 11, 27,
8693 12, 28, 13, 29, 14, 30, 15, 31}))
8694 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8696 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8697 // with PSHUFB. It is important to do this before we attempt to generate any
8698 // blends but after all of the single-input lowerings. If the single input
8699 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8700 // want to preserve that and we can DAG combine any longer sequences into
8701 // a PSHUFB in the end. But once we start blending from multiple inputs,
8702 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8703 // and there are *very* few patterns that would actually be faster than the
8704 // PSHUFB approach because of its ability to zero lanes.
8706 // FIXME: The only exceptions to the above are blends which are exact
8707 // interleavings with direct instructions supporting them. We currently don't
8708 // handle those well here.
8709 if (Subtarget->hasSSSE3()) {
8710 bool V1InUse = false;
8711 bool V2InUse = false;
8713 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8714 DAG, V1InUse, V2InUse);
8716 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8717 // do so. This avoids using them to handle blends-with-zero which is
8718 // important as a single pshufb is significantly faster for that.
8719 if (V1InUse && V2InUse) {
8720 if (Subtarget->hasSSE41())
8721 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8722 Mask, Subtarget, DAG))
8725 // We can use an unpack to do the blending rather than an or in some
8726 // cases. Even though the or may be (very minorly) more efficient, we
8727 // preference this lowering because there are common cases where part of
8728 // the complexity of the shuffles goes away when we do the final blend as
8730 // FIXME: It might be worth trying to detect if the unpack-feeding
8731 // shuffles will both be pshufb, in which case we shouldn't bother with
8733 if (SDValue Unpack =
8734 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8741 // There are special ways we can lower some single-element blends.
8742 if (NumV2Elements == 1)
8743 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8744 Mask, Subtarget, DAG))
8747 if (SDValue BitBlend =
8748 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8751 // Check whether a compaction lowering can be done. This handles shuffles
8752 // which take every Nth element for some even N. See the helper function for
8755 // We special case these as they can be particularly efficiently handled with
8756 // the PACKUSB instruction on x86 and they show up in common patterns of
8757 // rearranging bytes to truncate wide elements.
8758 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8759 // NumEvenDrops is the power of two stride of the elements. Another way of
8760 // thinking about it is that we need to drop the even elements this many
8761 // times to get the original input.
8762 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8764 // First we need to zero all the dropped bytes.
8765 assert(NumEvenDrops <= 3 &&
8766 "No support for dropping even elements more than 3 times.");
8767 // We use the mask type to pick which bytes are preserved based on how many
8768 // elements are dropped.
8769 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8770 SDValue ByteClearMask =
8771 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8772 DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8773 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8775 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8777 // Now pack things back together.
8778 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8779 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8780 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8781 for (int i = 1; i < NumEvenDrops; ++i) {
8782 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8783 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8789 // Handle multi-input cases by blending single-input shuffles.
8790 if (NumV2Elements > 0)
8791 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8794 // The fallback path for single-input shuffles widens this into two v8i16
8795 // vectors with unpacks, shuffles those, and then pulls them back together
8799 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8800 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8801 for (int i = 0; i < 16; ++i)
8803 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8805 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8807 SDValue VLoHalf, VHiHalf;
8808 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8809 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8811 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8812 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8813 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8814 [](int M) { return M >= 0 && M % 2 == 1; })) {
8815 // Use a mask to drop the high bytes.
8816 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8817 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8818 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8820 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8821 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8823 // Squash the masks to point directly into VLoHalf.
8824 for (int &M : LoBlendMask)
8827 for (int &M : HiBlendMask)
8831 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8832 // VHiHalf so that we can blend them as i16s.
8833 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8834 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8835 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8836 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8839 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8840 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8842 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8845 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8847 /// This routine breaks down the specific type of 128-bit shuffle and
8848 /// dispatches to the lowering routines accordingly.
8849 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8850 MVT VT, const X86Subtarget *Subtarget,
8851 SelectionDAG &DAG) {
8852 switch (VT.SimpleTy) {
8854 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8856 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8858 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8860 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8862 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8864 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8867 llvm_unreachable("Unimplemented!");
8871 /// \brief Helper function to test whether a shuffle mask could be
8872 /// simplified by widening the elements being shuffled.
8874 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8875 /// leaves it in an unspecified state.
8877 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8878 /// shuffle masks. The latter have the special property of a '-2' representing
8879 /// a zero-ed lane of a vector.
8880 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8881 SmallVectorImpl<int> &WidenedMask) {
8882 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8883 // If both elements are undef, its trivial.
8884 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8885 WidenedMask.push_back(SM_SentinelUndef);
8889 // Check for an undef mask and a mask value properly aligned to fit with
8890 // a pair of values. If we find such a case, use the non-undef mask's value.
8891 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8892 WidenedMask.push_back(Mask[i + 1] / 2);
8895 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8896 WidenedMask.push_back(Mask[i] / 2);
8900 // When zeroing, we need to spread the zeroing across both lanes to widen.
8901 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8902 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8903 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8904 WidenedMask.push_back(SM_SentinelZero);
8910 // Finally check if the two mask values are adjacent and aligned with
8912 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8913 WidenedMask.push_back(Mask[i] / 2);
8917 // Otherwise we can't safely widen the elements used in this shuffle.
8920 assert(WidenedMask.size() == Mask.size() / 2 &&
8921 "Incorrect size of mask after widening the elements!");
8926 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8928 /// This routine just extracts two subvectors, shuffles them independently, and
8929 /// then concatenates them back together. This should work effectively with all
8930 /// AVX vector shuffle types.
8931 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8932 SDValue V2, ArrayRef<int> Mask,
8933 SelectionDAG &DAG) {
8934 assert(VT.getSizeInBits() >= 256 &&
8935 "Only for 256-bit or wider vector shuffles!");
8936 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8937 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8939 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8940 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8942 int NumElements = VT.getVectorNumElements();
8943 int SplitNumElements = NumElements / 2;
8944 MVT ScalarVT = VT.getScalarType();
8945 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8947 // Rather than splitting build-vectors, just build two narrower build
8948 // vectors. This helps shuffling with splats and zeros.
8949 auto SplitVector = [&](SDValue V) {
8950 while (V.getOpcode() == ISD::BITCAST)
8951 V = V->getOperand(0);
8953 MVT OrigVT = V.getSimpleValueType();
8954 int OrigNumElements = OrigVT.getVectorNumElements();
8955 int OrigSplitNumElements = OrigNumElements / 2;
8956 MVT OrigScalarVT = OrigVT.getScalarType();
8957 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
8961 auto *BV = dyn_cast<BuildVectorSDNode>(V);
8963 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8964 DAG.getIntPtrConstant(0, DL));
8965 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8966 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
8969 SmallVector<SDValue, 16> LoOps, HiOps;
8970 for (int i = 0; i < OrigSplitNumElements; ++i) {
8971 LoOps.push_back(BV->getOperand(i));
8972 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
8974 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
8975 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
8977 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
8978 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
8981 SDValue LoV1, HiV1, LoV2, HiV2;
8982 std::tie(LoV1, HiV1) = SplitVector(V1);
8983 std::tie(LoV2, HiV2) = SplitVector(V2);
8985 // Now create two 4-way blends of these half-width vectors.
8986 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8987 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
8988 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
8989 for (int i = 0; i < SplitNumElements; ++i) {
8990 int M = HalfMask[i];
8991 if (M >= NumElements) {
8992 if (M >= NumElements + SplitNumElements)
8996 V2BlendMask.push_back(M - NumElements);
8997 V1BlendMask.push_back(-1);
8998 BlendMask.push_back(SplitNumElements + i);
8999 } else if (M >= 0) {
9000 if (M >= SplitNumElements)
9004 V2BlendMask.push_back(-1);
9005 V1BlendMask.push_back(M);
9006 BlendMask.push_back(i);
9008 V2BlendMask.push_back(-1);
9009 V1BlendMask.push_back(-1);
9010 BlendMask.push_back(-1);
9014 // Because the lowering happens after all combining takes place, we need to
9015 // manually combine these blend masks as much as possible so that we create
9016 // a minimal number of high-level vector shuffle nodes.
9018 // First try just blending the halves of V1 or V2.
9019 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9020 return DAG.getUNDEF(SplitVT);
9021 if (!UseLoV2 && !UseHiV2)
9022 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9023 if (!UseLoV1 && !UseHiV1)
9024 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9026 SDValue V1Blend, V2Blend;
9027 if (UseLoV1 && UseHiV1) {
9029 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9031 // We only use half of V1 so map the usage down into the final blend mask.
9032 V1Blend = UseLoV1 ? LoV1 : HiV1;
9033 for (int i = 0; i < SplitNumElements; ++i)
9034 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9035 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9037 if (UseLoV2 && UseHiV2) {
9039 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9041 // We only use half of V2 so map the usage down into the final blend mask.
9042 V2Blend = UseLoV2 ? LoV2 : HiV2;
9043 for (int i = 0; i < SplitNumElements; ++i)
9044 if (BlendMask[i] >= SplitNumElements)
9045 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9047 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9049 SDValue Lo = HalfBlend(LoMask);
9050 SDValue Hi = HalfBlend(HiMask);
9051 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9054 /// \brief Either split a vector in halves or decompose the shuffles and the
9057 /// This is provided as a good fallback for many lowerings of non-single-input
9058 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9059 /// between splitting the shuffle into 128-bit components and stitching those
9060 /// back together vs. extracting the single-input shuffles and blending those
9062 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9063 SDValue V2, ArrayRef<int> Mask,
9064 SelectionDAG &DAG) {
9065 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9066 "lower single-input shuffles as it "
9067 "could then recurse on itself.");
9068 int Size = Mask.size();
9070 // If this can be modeled as a broadcast of two elements followed by a blend,
9071 // prefer that lowering. This is especially important because broadcasts can
9072 // often fold with memory operands.
9073 auto DoBothBroadcast = [&] {
9074 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9077 if (V2BroadcastIdx == -1)
9078 V2BroadcastIdx = M - Size;
9079 else if (M - Size != V2BroadcastIdx)
9081 } else if (M >= 0) {
9082 if (V1BroadcastIdx == -1)
9084 else if (M != V1BroadcastIdx)
9089 if (DoBothBroadcast())
9090 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9093 // If the inputs all stem from a single 128-bit lane of each input, then we
9094 // split them rather than blending because the split will decompose to
9095 // unusually few instructions.
9096 int LaneCount = VT.getSizeInBits() / 128;
9097 int LaneSize = Size / LaneCount;
9098 SmallBitVector LaneInputs[2];
9099 LaneInputs[0].resize(LaneCount, false);
9100 LaneInputs[1].resize(LaneCount, false);
9101 for (int i = 0; i < Size; ++i)
9103 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9104 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9105 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9107 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9108 // that the decomposed single-input shuffles don't end up here.
9109 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9112 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9113 /// a permutation and blend of those lanes.
9115 /// This essentially blends the out-of-lane inputs to each lane into the lane
9116 /// from a permuted copy of the vector. This lowering strategy results in four
9117 /// instructions in the worst case for a single-input cross lane shuffle which
9118 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9119 /// of. Special cases for each particular shuffle pattern should be handled
9120 /// prior to trying this lowering.
9121 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9122 SDValue V1, SDValue V2,
9124 SelectionDAG &DAG) {
9125 // FIXME: This should probably be generalized for 512-bit vectors as well.
9126 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9127 int LaneSize = Mask.size() / 2;
9129 // If there are only inputs from one 128-bit lane, splitting will in fact be
9130 // less expensive. The flags track whether the given lane contains an element
9131 // that crosses to another lane.
9132 bool LaneCrossing[2] = {false, false};
9133 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9134 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9135 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9136 if (!LaneCrossing[0] || !LaneCrossing[1])
9137 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9139 if (isSingleInputShuffleMask(Mask)) {
9140 SmallVector<int, 32> FlippedBlendMask;
9141 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9142 FlippedBlendMask.push_back(
9143 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9145 : Mask[i] % LaneSize +
9146 (i / LaneSize) * LaneSize + Size));
9148 // Flip the vector, and blend the results which should now be in-lane. The
9149 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9150 // 5 for the high source. The value 3 selects the high half of source 2 and
9151 // the value 2 selects the low half of source 2. We only use source 2 to
9152 // allow folding it into a memory operand.
9153 unsigned PERMMask = 3 | 2 << 4;
9154 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9155 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9156 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9159 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9160 // will be handled by the above logic and a blend of the results, much like
9161 // other patterns in AVX.
9162 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9165 /// \brief Handle lowering 2-lane 128-bit shuffles.
9166 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9167 SDValue V2, ArrayRef<int> Mask,
9168 const X86Subtarget *Subtarget,
9169 SelectionDAG &DAG) {
9170 // TODO: If minimizing size and one of the inputs is a zero vector and the
9171 // the zero vector has only one use, we could use a VPERM2X128 to save the
9172 // instruction bytes needed to explicitly generate the zero vector.
9174 // Blends are faster and handle all the non-lane-crossing cases.
9175 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9179 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9180 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9182 // If either input operand is a zero vector, use VPERM2X128 because its mask
9183 // allows us to replace the zero input with an implicit zero.
9184 if (!IsV1Zero && !IsV2Zero) {
9185 // Check for patterns which can be matched with a single insert of a 128-bit
9187 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9188 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9189 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9190 VT.getVectorNumElements() / 2);
9191 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9192 DAG.getIntPtrConstant(0, DL));
9193 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9194 OnlyUsesV1 ? V1 : V2,
9195 DAG.getIntPtrConstant(0, DL));
9196 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9200 // Otherwise form a 128-bit permutation. After accounting for undefs,
9201 // convert the 64-bit shuffle mask selection values into 128-bit
9202 // selection bits by dividing the indexes by 2 and shifting into positions
9203 // defined by a vperm2*128 instruction's immediate control byte.
9205 // The immediate permute control byte looks like this:
9206 // [1:0] - select 128 bits from sources for low half of destination
9208 // [3] - zero low half of destination
9209 // [5:4] - select 128 bits from sources for high half of destination
9211 // [7] - zero high half of destination
9213 int MaskLO = Mask[0];
9214 if (MaskLO == SM_SentinelUndef)
9215 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9217 int MaskHI = Mask[2];
9218 if (MaskHI == SM_SentinelUndef)
9219 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9221 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9223 // If either input is a zero vector, replace it with an undef input.
9224 // Shuffle mask values < 4 are selecting elements of V1.
9225 // Shuffle mask values >= 4 are selecting elements of V2.
9226 // Adjust each half of the permute mask by clearing the half that was
9227 // selecting the zero vector and setting the zero mask bit.
9229 V1 = DAG.getUNDEF(VT);
9231 PermMask = (PermMask & 0xf0) | 0x08;
9233 PermMask = (PermMask & 0x0f) | 0x80;
9236 V2 = DAG.getUNDEF(VT);
9238 PermMask = (PermMask & 0xf0) | 0x08;
9240 PermMask = (PermMask & 0x0f) | 0x80;
9243 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9244 DAG.getConstant(PermMask, DL, MVT::i8));
9247 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9248 /// shuffling each lane.
9250 /// This will only succeed when the result of fixing the 128-bit lanes results
9251 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9252 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9253 /// the lane crosses early and then use simpler shuffles within each lane.
9255 /// FIXME: It might be worthwhile at some point to support this without
9256 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9257 /// in x86 only floating point has interesting non-repeating shuffles, and even
9258 /// those are still *marginally* more expensive.
9259 static SDValue lowerVectorShuffleByMerging128BitLanes(
9260 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9261 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9262 assert(!isSingleInputShuffleMask(Mask) &&
9263 "This is only useful with multiple inputs.");
9265 int Size = Mask.size();
9266 int LaneSize = 128 / VT.getScalarSizeInBits();
9267 int NumLanes = Size / LaneSize;
9268 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9270 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9271 // check whether the in-128-bit lane shuffles share a repeating pattern.
9272 SmallVector<int, 4> Lanes;
9273 Lanes.resize(NumLanes, -1);
9274 SmallVector<int, 4> InLaneMask;
9275 InLaneMask.resize(LaneSize, -1);
9276 for (int i = 0; i < Size; ++i) {
9280 int j = i / LaneSize;
9283 // First entry we've seen for this lane.
9284 Lanes[j] = Mask[i] / LaneSize;
9285 } else if (Lanes[j] != Mask[i] / LaneSize) {
9286 // This doesn't match the lane selected previously!
9290 // Check that within each lane we have a consistent shuffle mask.
9291 int k = i % LaneSize;
9292 if (InLaneMask[k] < 0) {
9293 InLaneMask[k] = Mask[i] % LaneSize;
9294 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9295 // This doesn't fit a repeating in-lane mask.
9300 // First shuffle the lanes into place.
9301 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9302 VT.getSizeInBits() / 64);
9303 SmallVector<int, 8> LaneMask;
9304 LaneMask.resize(NumLanes * 2, -1);
9305 for (int i = 0; i < NumLanes; ++i)
9306 if (Lanes[i] >= 0) {
9307 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9308 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9311 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9312 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9313 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9315 // Cast it back to the type we actually want.
9316 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9318 // Now do a simple shuffle that isn't lane crossing.
9319 SmallVector<int, 8> NewMask;
9320 NewMask.resize(Size, -1);
9321 for (int i = 0; i < Size; ++i)
9323 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9324 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9325 "Must not introduce lane crosses at this point!");
9327 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9330 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9333 /// This returns true if the elements from a particular input are already in the
9334 /// slot required by the given mask and require no permutation.
9335 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9336 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9337 int Size = Mask.size();
9338 for (int i = 0; i < Size; ++i)
9339 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9345 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9347 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9348 /// isn't available.
9349 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9350 const X86Subtarget *Subtarget,
9351 SelectionDAG &DAG) {
9353 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9354 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9355 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9356 ArrayRef<int> Mask = SVOp->getMask();
9357 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9359 SmallVector<int, 4> WidenedMask;
9360 if (canWidenShuffleElements(Mask, WidenedMask))
9361 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9364 if (isSingleInputShuffleMask(Mask)) {
9365 // Check for being able to broadcast a single element.
9366 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9367 Mask, Subtarget, DAG))
9370 // Use low duplicate instructions for masks that match their pattern.
9371 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9372 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9374 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9375 // Non-half-crossing single input shuffles can be lowerid with an
9376 // interleaved permutation.
9377 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9378 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9379 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9380 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9383 // With AVX2 we have direct support for this permutation.
9384 if (Subtarget->hasAVX2())
9385 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9386 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9388 // Otherwise, fall back.
9389 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9393 // X86 has dedicated unpack instructions that can handle specific blend
9394 // operations: UNPCKH and UNPCKL.
9395 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9396 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9397 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9398 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9399 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9400 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9401 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9402 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9404 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9408 // Check if the blend happens to exactly fit that of SHUFPD.
9409 if ((Mask[0] == -1 || Mask[0] < 2) &&
9410 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9411 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9412 (Mask[3] == -1 || Mask[3] >= 6)) {
9413 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9414 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9415 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9416 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9418 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9419 (Mask[1] == -1 || Mask[1] < 2) &&
9420 (Mask[2] == -1 || Mask[2] >= 6) &&
9421 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9422 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9423 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9424 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9425 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
9428 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9429 // shuffle. However, if we have AVX2 and either inputs are already in place,
9430 // we will be able to shuffle even across lanes the other input in a single
9431 // instruction so skip this pattern.
9432 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9433 isShuffleMaskInputInPlace(1, Mask))))
9434 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9435 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9438 // If we have AVX2 then we always want to lower with a blend because an v4 we
9439 // can fully permute the elements.
9440 if (Subtarget->hasAVX2())
9441 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9444 // Otherwise fall back on generic lowering.
9445 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9448 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9450 /// This routine is only called when we have AVX2 and thus a reasonable
9451 /// instruction set for v4i64 shuffling..
9452 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9453 const X86Subtarget *Subtarget,
9454 SelectionDAG &DAG) {
9456 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9457 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9459 ArrayRef<int> Mask = SVOp->getMask();
9460 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9461 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9463 SmallVector<int, 4> WidenedMask;
9464 if (canWidenShuffleElements(Mask, WidenedMask))
9465 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9468 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9472 // Check for being able to broadcast a single element.
9473 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9474 Mask, Subtarget, DAG))
9477 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9478 // use lower latency instructions that will operate on both 128-bit lanes.
9479 SmallVector<int, 2> RepeatedMask;
9480 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9481 if (isSingleInputShuffleMask(Mask)) {
9482 int PSHUFDMask[] = {-1, -1, -1, -1};
9483 for (int i = 0; i < 2; ++i)
9484 if (RepeatedMask[i] >= 0) {
9485 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9486 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9489 ISD::BITCAST, DL, MVT::v4i64,
9490 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9491 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9492 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9496 // AVX2 provides a direct instruction for permuting a single input across
9498 if (isSingleInputShuffleMask(Mask))
9499 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9500 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9502 // Try to use shift instructions.
9504 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9507 // Use dedicated unpack instructions for masks that match their pattern.
9508 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9509 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9510 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9511 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9512 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9513 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9514 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9515 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9517 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9518 // shuffle. However, if we have AVX2 and either inputs are already in place,
9519 // we will be able to shuffle even across lanes the other input in a single
9520 // instruction so skip this pattern.
9521 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9522 isShuffleMaskInputInPlace(1, Mask))))
9523 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9524 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9527 // Otherwise fall back on generic blend lowering.
9528 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9532 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9534 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9535 /// isn't available.
9536 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9537 const X86Subtarget *Subtarget,
9538 SelectionDAG &DAG) {
9540 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9541 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9542 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9543 ArrayRef<int> Mask = SVOp->getMask();
9544 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9546 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9550 // Check for being able to broadcast a single element.
9551 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9552 Mask, Subtarget, DAG))
9555 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9556 // options to efficiently lower the shuffle.
9557 SmallVector<int, 4> RepeatedMask;
9558 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9559 assert(RepeatedMask.size() == 4 &&
9560 "Repeated masks must be half the mask width!");
9562 // Use even/odd duplicate instructions for masks that match their pattern.
9563 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9564 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9565 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9566 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9568 if (isSingleInputShuffleMask(Mask))
9569 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9570 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9572 // Use dedicated unpack instructions for masks that match their pattern.
9573 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9574 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9575 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9576 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9577 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9578 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9579 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9580 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9582 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9583 // have already handled any direct blends. We also need to squash the
9584 // repeated mask into a simulated v4f32 mask.
9585 for (int i = 0; i < 4; ++i)
9586 if (RepeatedMask[i] >= 8)
9587 RepeatedMask[i] -= 4;
9588 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9591 // If we have a single input shuffle with different shuffle patterns in the
9592 // two 128-bit lanes use the variable mask to VPERMILPS.
9593 if (isSingleInputShuffleMask(Mask)) {
9594 SDValue VPermMask[8];
9595 for (int i = 0; i < 8; ++i)
9596 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9597 : DAG.getConstant(Mask[i], DL, MVT::i32);
9598 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9600 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9601 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9603 if (Subtarget->hasAVX2())
9604 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9605 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9606 DAG.getNode(ISD::BUILD_VECTOR, DL,
9607 MVT::v8i32, VPermMask)),
9610 // Otherwise, fall back.
9611 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9615 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9617 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9618 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9621 // If we have AVX2 then we always want to lower with a blend because at v8 we
9622 // can fully permute the elements.
9623 if (Subtarget->hasAVX2())
9624 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9627 // Otherwise fall back on generic lowering.
9628 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9631 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9633 /// This routine is only called when we have AVX2 and thus a reasonable
9634 /// instruction set for v8i32 shuffling..
9635 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9636 const X86Subtarget *Subtarget,
9637 SelectionDAG &DAG) {
9639 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9640 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9641 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9642 ArrayRef<int> Mask = SVOp->getMask();
9643 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9644 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9646 // Whenever we can lower this as a zext, that instruction is strictly faster
9647 // than any alternative. It also allows us to fold memory operands into the
9648 // shuffle in many cases.
9649 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9650 Mask, Subtarget, DAG))
9653 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9657 // Check for being able to broadcast a single element.
9658 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9659 Mask, Subtarget, DAG))
9662 // If the shuffle mask is repeated in each 128-bit lane we can use more
9663 // efficient instructions that mirror the shuffles across the two 128-bit
9665 SmallVector<int, 4> RepeatedMask;
9666 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9667 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9668 if (isSingleInputShuffleMask(Mask))
9669 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9670 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9672 // Use dedicated unpack instructions for masks that match their pattern.
9673 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9674 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9675 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9676 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9677 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9678 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9679 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9680 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9683 // Try to use shift instructions.
9685 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9688 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9689 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9692 // If the shuffle patterns aren't repeated but it is a single input, directly
9693 // generate a cross-lane VPERMD instruction.
9694 if (isSingleInputShuffleMask(Mask)) {
9695 SDValue VPermMask[8];
9696 for (int i = 0; i < 8; ++i)
9697 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9698 : DAG.getConstant(Mask[i], DL, MVT::i32);
9700 X86ISD::VPERMV, DL, MVT::v8i32,
9701 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9704 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9706 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9707 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9710 // Otherwise fall back on generic blend lowering.
9711 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9715 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9717 /// This routine is only called when we have AVX2 and thus a reasonable
9718 /// instruction set for v16i16 shuffling..
9719 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9720 const X86Subtarget *Subtarget,
9721 SelectionDAG &DAG) {
9723 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9724 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9726 ArrayRef<int> Mask = SVOp->getMask();
9727 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9728 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9730 // Whenever we can lower this as a zext, that instruction is strictly faster
9731 // than any alternative. It also allows us to fold memory operands into the
9732 // shuffle in many cases.
9733 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9734 Mask, Subtarget, DAG))
9737 // Check for being able to broadcast a single element.
9738 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9739 Mask, Subtarget, DAG))
9742 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9746 // Use dedicated unpack instructions for masks that match their pattern.
9747 if (isShuffleEquivalent(V1, V2, Mask,
9748 {// First 128-bit lane:
9749 0, 16, 1, 17, 2, 18, 3, 19,
9750 // Second 128-bit lane:
9751 8, 24, 9, 25, 10, 26, 11, 27}))
9752 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9753 if (isShuffleEquivalent(V1, V2, Mask,
9754 {// First 128-bit lane:
9755 4, 20, 5, 21, 6, 22, 7, 23,
9756 // Second 128-bit lane:
9757 12, 28, 13, 29, 14, 30, 15, 31}))
9758 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9760 // Try to use shift instructions.
9762 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9765 // Try to use byte rotation instructions.
9766 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9767 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9770 if (isSingleInputShuffleMask(Mask)) {
9771 // There are no generalized cross-lane shuffle operations available on i16
9773 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9774 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9777 SmallVector<int, 8> RepeatedMask;
9778 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9779 // As this is a single-input shuffle, the repeated mask should be
9780 // a strictly valid v8i16 mask that we can pass through to the v8i16
9781 // lowering to handle even the v16 case.
9782 return lowerV8I16GeneralSingleInputVectorShuffle(
9783 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9786 SDValue PSHUFBMask[32];
9787 for (int i = 0; i < 16; ++i) {
9788 if (Mask[i] == -1) {
9789 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9793 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9794 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9795 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9796 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9799 ISD::BITCAST, DL, MVT::v16i16,
9801 X86ISD::PSHUFB, DL, MVT::v32i8,
9802 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9803 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9806 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9808 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9809 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9812 // Otherwise fall back on generic lowering.
9813 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9816 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9818 /// This routine is only called when we have AVX2 and thus a reasonable
9819 /// instruction set for v32i8 shuffling..
9820 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9821 const X86Subtarget *Subtarget,
9822 SelectionDAG &DAG) {
9824 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9825 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9826 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9827 ArrayRef<int> Mask = SVOp->getMask();
9828 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9829 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9831 // Whenever we can lower this as a zext, that instruction is strictly faster
9832 // than any alternative. It also allows us to fold memory operands into the
9833 // shuffle in many cases.
9834 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9835 Mask, Subtarget, DAG))
9838 // Check for being able to broadcast a single element.
9839 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9840 Mask, Subtarget, DAG))
9843 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9847 // Use dedicated unpack instructions for masks that match their pattern.
9848 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9850 if (isShuffleEquivalent(
9852 {// First 128-bit lane:
9853 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9854 // Second 128-bit lane:
9855 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9856 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9857 if (isShuffleEquivalent(
9859 {// First 128-bit lane:
9860 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9861 // Second 128-bit lane:
9862 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9863 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9865 // Try to use shift instructions.
9867 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9870 // Try to use byte rotation instructions.
9871 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9872 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9875 if (isSingleInputShuffleMask(Mask)) {
9876 // There are no generalized cross-lane shuffle operations available on i8
9878 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9879 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9882 SDValue PSHUFBMask[32];
9883 for (int i = 0; i < 32; ++i)
9886 ? DAG.getUNDEF(MVT::i8)
9887 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
9891 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9892 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9895 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9897 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9898 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9901 // Otherwise fall back on generic lowering.
9902 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9905 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9907 /// This routine either breaks down the specific type of a 256-bit x86 vector
9908 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9909 /// together based on the available instructions.
9910 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9911 MVT VT, const X86Subtarget *Subtarget,
9912 SelectionDAG &DAG) {
9914 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9915 ArrayRef<int> Mask = SVOp->getMask();
9917 // If we have a single input to the zero element, insert that into V1 if we
9918 // can do so cheaply.
9919 int NumElts = VT.getVectorNumElements();
9920 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
9921 return M >= NumElts;
9924 if (NumV2Elements == 1 && Mask[0] >= NumElts)
9925 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9926 DL, VT, V1, V2, Mask, Subtarget, DAG))
9929 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9930 // check for those subtargets here and avoid much of the subtarget querying in
9931 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9932 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9933 // floating point types there eventually, just immediately cast everything to
9934 // a float and operate entirely in that domain.
9935 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9936 int ElementBits = VT.getScalarSizeInBits();
9937 if (ElementBits < 32)
9938 // No floating point type available, decompose into 128-bit vectors.
9939 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9941 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9942 VT.getVectorNumElements());
9943 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9944 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9945 return DAG.getNode(ISD::BITCAST, DL, VT,
9946 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9949 switch (VT.SimpleTy) {
9951 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9953 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9955 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9957 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9959 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9961 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9964 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9968 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9969 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9970 const X86Subtarget *Subtarget,
9971 SelectionDAG &DAG) {
9973 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9974 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9975 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9976 ArrayRef<int> Mask = SVOp->getMask();
9977 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9979 // X86 has dedicated unpack instructions that can handle specific blend
9980 // operations: UNPCKH and UNPCKL.
9981 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9982 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
9983 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9984 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
9986 // FIXME: Implement direct support for this type!
9987 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9990 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9991 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9992 const X86Subtarget *Subtarget,
9993 SelectionDAG &DAG) {
9995 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9996 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9998 ArrayRef<int> Mask = SVOp->getMask();
9999 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10001 // Use dedicated unpack instructions for masks that match their pattern.
10002 if (isShuffleEquivalent(V1, V2, Mask,
10003 {// First 128-bit lane.
10004 0, 16, 1, 17, 4, 20, 5, 21,
10005 // Second 128-bit lane.
10006 8, 24, 9, 25, 12, 28, 13, 29}))
10007 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10008 if (isShuffleEquivalent(V1, V2, Mask,
10009 {// First 128-bit lane.
10010 2, 18, 3, 19, 6, 22, 7, 23,
10011 // Second 128-bit lane.
10012 10, 26, 11, 27, 14, 30, 15, 31}))
10013 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10015 // FIXME: Implement direct support for this type!
10016 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10019 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10020 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10021 const X86Subtarget *Subtarget,
10022 SelectionDAG &DAG) {
10024 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10025 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10026 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10027 ArrayRef<int> Mask = SVOp->getMask();
10028 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10030 // X86 has dedicated unpack instructions that can handle specific blend
10031 // operations: UNPCKH and UNPCKL.
10032 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10033 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10034 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10035 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10037 // FIXME: Implement direct support for this type!
10038 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10041 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10042 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10043 const X86Subtarget *Subtarget,
10044 SelectionDAG &DAG) {
10046 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10047 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10048 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10049 ArrayRef<int> Mask = SVOp->getMask();
10050 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10052 // Use dedicated unpack instructions for masks that match their pattern.
10053 if (isShuffleEquivalent(V1, V2, Mask,
10054 {// First 128-bit lane.
10055 0, 16, 1, 17, 4, 20, 5, 21,
10056 // Second 128-bit lane.
10057 8, 24, 9, 25, 12, 28, 13, 29}))
10058 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10059 if (isShuffleEquivalent(V1, V2, Mask,
10060 {// First 128-bit lane.
10061 2, 18, 3, 19, 6, 22, 7, 23,
10062 // Second 128-bit lane.
10063 10, 26, 11, 27, 14, 30, 15, 31}))
10064 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10066 // FIXME: Implement direct support for this type!
10067 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10070 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10071 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10072 const X86Subtarget *Subtarget,
10073 SelectionDAG &DAG) {
10075 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10076 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10077 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10078 ArrayRef<int> Mask = SVOp->getMask();
10079 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10080 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10082 // FIXME: Implement direct support for this type!
10083 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10086 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10087 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10088 const X86Subtarget *Subtarget,
10089 SelectionDAG &DAG) {
10091 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10092 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10093 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10094 ArrayRef<int> Mask = SVOp->getMask();
10095 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10096 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10098 // FIXME: Implement direct support for this type!
10099 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10102 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10104 /// This routine either breaks down the specific type of a 512-bit x86 vector
10105 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10106 /// together based on the available instructions.
10107 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10108 MVT VT, const X86Subtarget *Subtarget,
10109 SelectionDAG &DAG) {
10111 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10112 ArrayRef<int> Mask = SVOp->getMask();
10113 assert(Subtarget->hasAVX512() &&
10114 "Cannot lower 512-bit vectors w/ basic ISA!");
10116 // Check for being able to broadcast a single element.
10117 if (SDValue Broadcast =
10118 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10121 // Dispatch to each element type for lowering. If we don't have supprot for
10122 // specific element type shuffles at 512 bits, immediately split them and
10123 // lower them. Each lowering routine of a given type is allowed to assume that
10124 // the requisite ISA extensions for that element type are available.
10125 switch (VT.SimpleTy) {
10127 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10129 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10131 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10133 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10135 if (Subtarget->hasBWI())
10136 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10139 if (Subtarget->hasBWI())
10140 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10144 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10147 // Otherwise fall back on splitting.
10148 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10151 /// \brief Top-level lowering for x86 vector shuffles.
10153 /// This handles decomposition, canonicalization, and lowering of all x86
10154 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10155 /// above in helper routines. The canonicalization attempts to widen shuffles
10156 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10157 /// s.t. only one of the two inputs needs to be tested, etc.
10158 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10159 SelectionDAG &DAG) {
10160 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10161 ArrayRef<int> Mask = SVOp->getMask();
10162 SDValue V1 = Op.getOperand(0);
10163 SDValue V2 = Op.getOperand(1);
10164 MVT VT = Op.getSimpleValueType();
10165 int NumElements = VT.getVectorNumElements();
10168 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10170 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10171 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10172 if (V1IsUndef && V2IsUndef)
10173 return DAG.getUNDEF(VT);
10175 // When we create a shuffle node we put the UNDEF node to second operand,
10176 // but in some cases the first operand may be transformed to UNDEF.
10177 // In this case we should just commute the node.
10179 return DAG.getCommutedVectorShuffle(*SVOp);
10181 // Check for non-undef masks pointing at an undef vector and make the masks
10182 // undef as well. This makes it easier to match the shuffle based solely on
10186 if (M >= NumElements) {
10187 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10188 for (int &M : NewMask)
10189 if (M >= NumElements)
10191 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10194 // We actually see shuffles that are entirely re-arrangements of a set of
10195 // zero inputs. This mostly happens while decomposing complex shuffles into
10196 // simple ones. Directly lower these as a buildvector of zeros.
10197 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10198 if (Zeroable.all())
10199 return getZeroVector(VT, Subtarget, DAG, dl);
10201 // Try to collapse shuffles into using a vector type with fewer elements but
10202 // wider element types. We cap this to not form integers or floating point
10203 // elements wider than 64 bits, but it might be interesting to form i128
10204 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10205 SmallVector<int, 16> WidenedMask;
10206 if (VT.getScalarSizeInBits() < 64 &&
10207 canWidenShuffleElements(Mask, WidenedMask)) {
10208 MVT NewEltVT = VT.isFloatingPoint()
10209 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10210 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10211 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10212 // Make sure that the new vector type is legal. For example, v2f64 isn't
10214 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10215 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10216 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10217 return DAG.getNode(ISD::BITCAST, dl, VT,
10218 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10222 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10223 for (int M : SVOp->getMask())
10225 ++NumUndefElements;
10226 else if (M < NumElements)
10231 // Commute the shuffle as needed such that more elements come from V1 than
10232 // V2. This allows us to match the shuffle pattern strictly on how many
10233 // elements come from V1 without handling the symmetric cases.
10234 if (NumV2Elements > NumV1Elements)
10235 return DAG.getCommutedVectorShuffle(*SVOp);
10237 // When the number of V1 and V2 elements are the same, try to minimize the
10238 // number of uses of V2 in the low half of the vector. When that is tied,
10239 // ensure that the sum of indices for V1 is equal to or lower than the sum
10240 // indices for V2. When those are equal, try to ensure that the number of odd
10241 // indices for V1 is lower than the number of odd indices for V2.
10242 if (NumV1Elements == NumV2Elements) {
10243 int LowV1Elements = 0, LowV2Elements = 0;
10244 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10245 if (M >= NumElements)
10249 if (LowV2Elements > LowV1Elements) {
10250 return DAG.getCommutedVectorShuffle(*SVOp);
10251 } else if (LowV2Elements == LowV1Elements) {
10252 int SumV1Indices = 0, SumV2Indices = 0;
10253 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10254 if (SVOp->getMask()[i] >= NumElements)
10256 else if (SVOp->getMask()[i] >= 0)
10258 if (SumV2Indices < SumV1Indices) {
10259 return DAG.getCommutedVectorShuffle(*SVOp);
10260 } else if (SumV2Indices == SumV1Indices) {
10261 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10262 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10263 if (SVOp->getMask()[i] >= NumElements)
10264 NumV2OddIndices += i % 2;
10265 else if (SVOp->getMask()[i] >= 0)
10266 NumV1OddIndices += i % 2;
10267 if (NumV2OddIndices < NumV1OddIndices)
10268 return DAG.getCommutedVectorShuffle(*SVOp);
10273 // For each vector width, delegate to a specialized lowering routine.
10274 if (VT.getSizeInBits() == 128)
10275 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10277 if (VT.getSizeInBits() == 256)
10278 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10280 // Force AVX-512 vectors to be scalarized for now.
10281 // FIXME: Implement AVX-512 support!
10282 if (VT.getSizeInBits() == 512)
10283 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10285 llvm_unreachable("Unimplemented!");
10288 // This function assumes its argument is a BUILD_VECTOR of constants or
10289 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10291 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10292 unsigned &MaskValue) {
10294 unsigned NumElems = BuildVector->getNumOperands();
10295 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10296 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10297 unsigned NumElemsInLane = NumElems / NumLanes;
10299 // Blend for v16i16 should be symetric for the both lanes.
10300 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10301 SDValue EltCond = BuildVector->getOperand(i);
10302 SDValue SndLaneEltCond =
10303 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10305 int Lane1Cond = -1, Lane2Cond = -1;
10306 if (isa<ConstantSDNode>(EltCond))
10307 Lane1Cond = !isZero(EltCond);
10308 if (isa<ConstantSDNode>(SndLaneEltCond))
10309 Lane2Cond = !isZero(SndLaneEltCond);
10311 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10312 // Lane1Cond != 0, means we want the first argument.
10313 // Lane1Cond == 0, means we want the second argument.
10314 // The encoding of this argument is 0 for the first argument, 1
10315 // for the second. Therefore, invert the condition.
10316 MaskValue |= !Lane1Cond << i;
10317 else if (Lane1Cond < 0)
10318 MaskValue |= !Lane2Cond << i;
10325 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10326 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10327 const X86Subtarget *Subtarget,
10328 SelectionDAG &DAG) {
10329 SDValue Cond = Op.getOperand(0);
10330 SDValue LHS = Op.getOperand(1);
10331 SDValue RHS = Op.getOperand(2);
10333 MVT VT = Op.getSimpleValueType();
10335 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10337 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10339 // Only non-legal VSELECTs reach this lowering, convert those into generic
10340 // shuffles and re-use the shuffle lowering path for blends.
10341 SmallVector<int, 32> Mask;
10342 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10343 SDValue CondElt = CondBV->getOperand(i);
10345 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10347 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10350 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10351 // A vselect where all conditions and data are constants can be optimized into
10352 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10353 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10354 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10355 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10358 // Try to lower this to a blend-style vector shuffle. This can handle all
10359 // constant condition cases.
10360 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10363 // Variable blends are only legal from SSE4.1 onward.
10364 if (!Subtarget->hasSSE41())
10367 // Only some types will be legal on some subtargets. If we can emit a legal
10368 // VSELECT-matching blend, return Op, and but if we need to expand, return
10370 switch (Op.getSimpleValueType().SimpleTy) {
10372 // Most of the vector types have blends past SSE4.1.
10376 // The byte blends for AVX vectors were introduced only in AVX2.
10377 if (Subtarget->hasAVX2())
10384 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10385 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10388 // FIXME: We should custom lower this by fixing the condition and using i8
10394 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10395 MVT VT = Op.getSimpleValueType();
10398 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10401 if (VT.getSizeInBits() == 8) {
10402 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10403 Op.getOperand(0), Op.getOperand(1));
10404 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10405 DAG.getValueType(VT));
10406 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10409 if (VT.getSizeInBits() == 16) {
10410 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10411 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10413 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10414 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10415 DAG.getNode(ISD::BITCAST, dl,
10418 Op.getOperand(1)));
10419 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10420 Op.getOperand(0), Op.getOperand(1));
10421 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10422 DAG.getValueType(VT));
10423 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10426 if (VT == MVT::f32) {
10427 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10428 // the result back to FR32 register. It's only worth matching if the
10429 // result has a single use which is a store or a bitcast to i32. And in
10430 // the case of a store, it's not worth it if the index is a constant 0,
10431 // because a MOVSSmr can be used instead, which is smaller and faster.
10432 if (!Op.hasOneUse())
10434 SDNode *User = *Op.getNode()->use_begin();
10435 if ((User->getOpcode() != ISD::STORE ||
10436 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10437 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10438 (User->getOpcode() != ISD::BITCAST ||
10439 User->getValueType(0) != MVT::i32))
10441 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10442 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10445 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10448 if (VT == MVT::i32 || VT == MVT::i64) {
10449 // ExtractPS/pextrq works with constant index.
10450 if (isa<ConstantSDNode>(Op.getOperand(1)))
10456 /// Extract one bit from mask vector, like v16i1 or v8i1.
10457 /// AVX-512 feature.
10459 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10460 SDValue Vec = Op.getOperand(0);
10462 MVT VecVT = Vec.getSimpleValueType();
10463 SDValue Idx = Op.getOperand(1);
10464 MVT EltVT = Op.getSimpleValueType();
10466 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10467 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10468 "Unexpected vector type in ExtractBitFromMaskVector");
10470 // variable index can't be handled in mask registers,
10471 // extend vector to VR512
10472 if (!isa<ConstantSDNode>(Idx)) {
10473 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10474 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10475 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10476 ExtVT.getVectorElementType(), Ext, Idx);
10477 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10480 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10481 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10482 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10483 rc = getRegClassFor(MVT::v16i1);
10484 unsigned MaxSift = rc->getSize()*8 - 1;
10485 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10486 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10487 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10488 DAG.getConstant(MaxSift, dl, MVT::i8));
10489 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10490 DAG.getIntPtrConstant(0, dl));
10494 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10495 SelectionDAG &DAG) const {
10497 SDValue Vec = Op.getOperand(0);
10498 MVT VecVT = Vec.getSimpleValueType();
10499 SDValue Idx = Op.getOperand(1);
10501 if (Op.getSimpleValueType() == MVT::i1)
10502 return ExtractBitFromMaskVector(Op, DAG);
10504 if (!isa<ConstantSDNode>(Idx)) {
10505 if (VecVT.is512BitVector() ||
10506 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10507 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10510 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10511 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10512 MaskEltVT.getSizeInBits());
10514 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10515 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10516 getZeroVector(MaskVT, Subtarget, DAG, dl),
10517 Idx, DAG.getConstant(0, dl, getPointerTy()));
10518 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10519 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10520 Perm, DAG.getConstant(0, dl, getPointerTy()));
10525 // If this is a 256-bit vector result, first extract the 128-bit vector and
10526 // then extract the element from the 128-bit vector.
10527 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10529 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10530 // Get the 128-bit vector.
10531 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10532 MVT EltVT = VecVT.getVectorElementType();
10534 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10536 //if (IdxVal >= NumElems/2)
10537 // IdxVal -= NumElems/2;
10538 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10539 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10540 DAG.getConstant(IdxVal, dl, MVT::i32));
10543 assert(VecVT.is128BitVector() && "Unexpected vector length");
10545 if (Subtarget->hasSSE41()) {
10546 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10551 MVT VT = Op.getSimpleValueType();
10552 // TODO: handle v16i8.
10553 if (VT.getSizeInBits() == 16) {
10554 SDValue Vec = Op.getOperand(0);
10555 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10557 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10558 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10559 DAG.getNode(ISD::BITCAST, dl,
10561 Op.getOperand(1)));
10562 // Transform it so it match pextrw which produces a 32-bit result.
10563 MVT EltVT = MVT::i32;
10564 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10565 Op.getOperand(0), Op.getOperand(1));
10566 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10567 DAG.getValueType(VT));
10568 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10571 if (VT.getSizeInBits() == 32) {
10572 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10576 // SHUFPS the element to the lowest double word, then movss.
10577 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10578 MVT VVT = Op.getOperand(0).getSimpleValueType();
10579 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10580 DAG.getUNDEF(VVT), Mask);
10581 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10582 DAG.getIntPtrConstant(0, dl));
10585 if (VT.getSizeInBits() == 64) {
10586 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10587 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10588 // to match extract_elt for f64.
10589 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10593 // UNPCKHPD the element to the lowest double word, then movsd.
10594 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10595 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10596 int Mask[2] = { 1, -1 };
10597 MVT VVT = Op.getOperand(0).getSimpleValueType();
10598 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10599 DAG.getUNDEF(VVT), Mask);
10600 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10601 DAG.getIntPtrConstant(0, dl));
10607 /// Insert one bit to mask vector, like v16i1 or v8i1.
10608 /// AVX-512 feature.
10610 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10612 SDValue Vec = Op.getOperand(0);
10613 SDValue Elt = Op.getOperand(1);
10614 SDValue Idx = Op.getOperand(2);
10615 MVT VecVT = Vec.getSimpleValueType();
10617 if (!isa<ConstantSDNode>(Idx)) {
10618 // Non constant index. Extend source and destination,
10619 // insert element and then truncate the result.
10620 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10621 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10622 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10623 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10624 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10625 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10628 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10629 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10630 if (Vec.getOpcode() == ISD::UNDEF)
10631 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10632 DAG.getConstant(IdxVal, dl, MVT::i8));
10633 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10634 unsigned MaxSift = rc->getSize()*8 - 1;
10635 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10636 DAG.getConstant(MaxSift, dl, MVT::i8));
10637 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10638 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10639 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10642 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10643 SelectionDAG &DAG) const {
10644 MVT VT = Op.getSimpleValueType();
10645 MVT EltVT = VT.getVectorElementType();
10647 if (EltVT == MVT::i1)
10648 return InsertBitToMaskVector(Op, DAG);
10651 SDValue N0 = Op.getOperand(0);
10652 SDValue N1 = Op.getOperand(1);
10653 SDValue N2 = Op.getOperand(2);
10654 if (!isa<ConstantSDNode>(N2))
10656 auto *N2C = cast<ConstantSDNode>(N2);
10657 unsigned IdxVal = N2C->getZExtValue();
10659 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10660 // into that, and then insert the subvector back into the result.
10661 if (VT.is256BitVector() || VT.is512BitVector()) {
10662 // With a 256-bit vector, we can insert into the zero element efficiently
10663 // using a blend if we have AVX or AVX2 and the right data type.
10664 if (VT.is256BitVector() && IdxVal == 0) {
10665 // TODO: It is worthwhile to cast integer to floating point and back
10666 // and incur a domain crossing penalty if that's what we'll end up
10667 // doing anyway after extracting to a 128-bit vector.
10668 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10669 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10670 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10671 N2 = DAG.getIntPtrConstant(1, dl);
10672 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10676 // Get the desired 128-bit vector chunk.
10677 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10679 // Insert the element into the desired chunk.
10680 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10681 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10683 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10684 DAG.getConstant(IdxIn128, dl, MVT::i32));
10686 // Insert the changed part back into the bigger vector
10687 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10689 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10691 if (Subtarget->hasSSE41()) {
10692 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10694 if (VT == MVT::v8i16) {
10695 Opc = X86ISD::PINSRW;
10697 assert(VT == MVT::v16i8);
10698 Opc = X86ISD::PINSRB;
10701 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10703 if (N1.getValueType() != MVT::i32)
10704 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10705 if (N2.getValueType() != MVT::i32)
10706 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10707 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10710 if (EltVT == MVT::f32) {
10711 // Bits [7:6] of the constant are the source select. This will always be
10712 // zero here. The DAG Combiner may combine an extract_elt index into
10713 // these bits. For example (insert (extract, 3), 2) could be matched by
10714 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10715 // Bits [5:4] of the constant are the destination select. This is the
10716 // value of the incoming immediate.
10717 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10718 // combine either bitwise AND or insert of float 0.0 to set these bits.
10720 const Function *F = DAG.getMachineFunction().getFunction();
10721 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10722 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10723 // If this is an insertion of 32-bits into the low 32-bits of
10724 // a vector, we prefer to generate a blend with immediate rather
10725 // than an insertps. Blends are simpler operations in hardware and so
10726 // will always have equal or better performance than insertps.
10727 // But if optimizing for size and there's a load folding opportunity,
10728 // generate insertps because blendps does not have a 32-bit memory
10730 N2 = DAG.getIntPtrConstant(1, dl);
10731 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10732 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10734 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10735 // Create this as a scalar to vector..
10736 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10737 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10740 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10741 // PINSR* works with constant index.
10746 if (EltVT == MVT::i8)
10749 if (EltVT.getSizeInBits() == 16) {
10750 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10751 // as its second argument.
10752 if (N1.getValueType() != MVT::i32)
10753 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10754 if (N2.getValueType() != MVT::i32)
10755 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10756 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10761 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10763 MVT OpVT = Op.getSimpleValueType();
10765 // If this is a 256-bit vector result, first insert into a 128-bit
10766 // vector and then insert into the 256-bit vector.
10767 if (!OpVT.is128BitVector()) {
10768 // Insert into a 128-bit vector.
10769 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10770 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10771 OpVT.getVectorNumElements() / SizeFactor);
10773 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10775 // Insert the 128-bit vector.
10776 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10779 if (OpVT == MVT::v1i64 &&
10780 Op.getOperand(0).getValueType() == MVT::i64)
10781 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10783 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10784 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10785 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10786 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10789 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10790 // a simple subregister reference or explicit instructions to grab
10791 // upper bits of a vector.
10792 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10793 SelectionDAG &DAG) {
10795 SDValue In = Op.getOperand(0);
10796 SDValue Idx = Op.getOperand(1);
10797 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10798 MVT ResVT = Op.getSimpleValueType();
10799 MVT InVT = In.getSimpleValueType();
10801 if (Subtarget->hasFp256()) {
10802 if (ResVT.is128BitVector() &&
10803 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10804 isa<ConstantSDNode>(Idx)) {
10805 return Extract128BitVector(In, IdxVal, DAG, dl);
10807 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10808 isa<ConstantSDNode>(Idx)) {
10809 return Extract256BitVector(In, IdxVal, DAG, dl);
10815 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10816 // simple superregister reference or explicit instructions to insert
10817 // the upper bits of a vector.
10818 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10819 SelectionDAG &DAG) {
10820 if (!Subtarget->hasAVX())
10824 SDValue Vec = Op.getOperand(0);
10825 SDValue SubVec = Op.getOperand(1);
10826 SDValue Idx = Op.getOperand(2);
10828 if (!isa<ConstantSDNode>(Idx))
10831 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10832 MVT OpVT = Op.getSimpleValueType();
10833 MVT SubVecVT = SubVec.getSimpleValueType();
10835 // Fold two 16-byte subvector loads into one 32-byte load:
10836 // (insert_subvector (insert_subvector undef, (load addr), 0),
10837 // (load addr + 16), Elts/2)
10839 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10840 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10841 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10842 !Subtarget->isUnalignedMem32Slow()) {
10843 SDValue SubVec2 = Vec.getOperand(1);
10844 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10845 if (Idx2->getZExtValue() == 0) {
10846 SDValue Ops[] = { SubVec2, SubVec };
10847 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10854 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10855 SubVecVT.is128BitVector())
10856 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10858 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10859 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10861 if (OpVT.getVectorElementType() == MVT::i1) {
10862 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10864 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10865 SDValue Undef = DAG.getUNDEF(OpVT);
10866 unsigned NumElems = OpVT.getVectorNumElements();
10867 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10869 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10870 // Zero upper bits of the Vec
10871 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10872 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10874 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10876 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10877 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10880 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10882 // Zero upper bits of the Vec2
10883 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10884 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10885 // Zero lower bits of the Vec
10886 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10887 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10888 // Merge them together
10889 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10895 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10896 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10897 // one of the above mentioned nodes. It has to be wrapped because otherwise
10898 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10899 // be used to form addressing mode. These wrapped nodes will be selected
10902 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10903 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10905 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10906 // global base reg.
10907 unsigned char OpFlag = 0;
10908 unsigned WrapperKind = X86ISD::Wrapper;
10909 CodeModel::Model M = DAG.getTarget().getCodeModel();
10911 if (Subtarget->isPICStyleRIPRel() &&
10912 (M == CodeModel::Small || M == CodeModel::Kernel))
10913 WrapperKind = X86ISD::WrapperRIP;
10914 else if (Subtarget->isPICStyleGOT())
10915 OpFlag = X86II::MO_GOTOFF;
10916 else if (Subtarget->isPICStyleStubPIC())
10917 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10919 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10920 CP->getAlignment(),
10921 CP->getOffset(), OpFlag);
10923 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10924 // With PIC, the address is actually $g + Offset.
10926 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10927 DAG.getNode(X86ISD::GlobalBaseReg,
10928 SDLoc(), getPointerTy()),
10935 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10936 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10938 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10939 // global base reg.
10940 unsigned char OpFlag = 0;
10941 unsigned WrapperKind = X86ISD::Wrapper;
10942 CodeModel::Model M = DAG.getTarget().getCodeModel();
10944 if (Subtarget->isPICStyleRIPRel() &&
10945 (M == CodeModel::Small || M == CodeModel::Kernel))
10946 WrapperKind = X86ISD::WrapperRIP;
10947 else if (Subtarget->isPICStyleGOT())
10948 OpFlag = X86II::MO_GOTOFF;
10949 else if (Subtarget->isPICStyleStubPIC())
10950 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10952 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10955 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10957 // With PIC, the address is actually $g + Offset.
10959 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10960 DAG.getNode(X86ISD::GlobalBaseReg,
10961 SDLoc(), getPointerTy()),
10968 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10969 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10971 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10972 // global base reg.
10973 unsigned char OpFlag = 0;
10974 unsigned WrapperKind = X86ISD::Wrapper;
10975 CodeModel::Model M = DAG.getTarget().getCodeModel();
10977 if (Subtarget->isPICStyleRIPRel() &&
10978 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10979 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10980 OpFlag = X86II::MO_GOTPCREL;
10981 WrapperKind = X86ISD::WrapperRIP;
10982 } else if (Subtarget->isPICStyleGOT()) {
10983 OpFlag = X86II::MO_GOT;
10984 } else if (Subtarget->isPICStyleStubPIC()) {
10985 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10986 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10987 OpFlag = X86II::MO_DARWIN_NONLAZY;
10990 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10993 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10995 // With PIC, the address is actually $g + Offset.
10996 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10997 !Subtarget->is64Bit()) {
10998 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10999 DAG.getNode(X86ISD::GlobalBaseReg,
11000 SDLoc(), getPointerTy()),
11004 // For symbols that require a load from a stub to get the address, emit the
11006 if (isGlobalStubReference(OpFlag))
11007 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11008 MachinePointerInfo::getGOT(), false, false, false, 0);
11014 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11015 // Create the TargetBlockAddressAddress node.
11016 unsigned char OpFlags =
11017 Subtarget->ClassifyBlockAddressReference();
11018 CodeModel::Model M = DAG.getTarget().getCodeModel();
11019 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11020 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11022 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11025 if (Subtarget->isPICStyleRIPRel() &&
11026 (M == CodeModel::Small || M == CodeModel::Kernel))
11027 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11029 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11031 // With PIC, the address is actually $g + Offset.
11032 if (isGlobalRelativeToPICBase(OpFlags)) {
11033 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11034 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11042 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11043 int64_t Offset, SelectionDAG &DAG) const {
11044 // Create the TargetGlobalAddress node, folding in the constant
11045 // offset if it is legal.
11046 unsigned char OpFlags =
11047 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11048 CodeModel::Model M = DAG.getTarget().getCodeModel();
11050 if (OpFlags == X86II::MO_NO_FLAG &&
11051 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11052 // A direct static reference to a global.
11053 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11056 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11059 if (Subtarget->isPICStyleRIPRel() &&
11060 (M == CodeModel::Small || M == CodeModel::Kernel))
11061 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11063 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11065 // With PIC, the address is actually $g + Offset.
11066 if (isGlobalRelativeToPICBase(OpFlags)) {
11067 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11068 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11072 // For globals that require a load from a stub to get the address, emit the
11074 if (isGlobalStubReference(OpFlags))
11075 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11076 MachinePointerInfo::getGOT(), false, false, false, 0);
11078 // If there was a non-zero offset that we didn't fold, create an explicit
11079 // addition for it.
11081 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11082 DAG.getConstant(Offset, dl, getPointerTy()));
11088 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11089 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11090 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11091 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11095 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11096 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11097 unsigned char OperandFlags, bool LocalDynamic = false) {
11098 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11099 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11101 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11102 GA->getValueType(0),
11106 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11110 SDValue Ops[] = { Chain, TGA, *InFlag };
11111 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11113 SDValue Ops[] = { Chain, TGA };
11114 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11117 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11118 MFI->setAdjustsStack(true);
11119 MFI->setHasCalls(true);
11121 SDValue Flag = Chain.getValue(1);
11122 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11125 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11127 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11130 SDLoc dl(GA); // ? function entry point might be better
11131 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11132 DAG.getNode(X86ISD::GlobalBaseReg,
11133 SDLoc(), PtrVT), InFlag);
11134 InFlag = Chain.getValue(1);
11136 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11139 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11141 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11143 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11144 X86::RAX, X86II::MO_TLSGD);
11147 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11153 // Get the start address of the TLS block for this module.
11154 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11155 .getInfo<X86MachineFunctionInfo>();
11156 MFI->incNumLocalDynamicTLSAccesses();
11160 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11161 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11164 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11165 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11166 InFlag = Chain.getValue(1);
11167 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11168 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11171 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11175 unsigned char OperandFlags = X86II::MO_DTPOFF;
11176 unsigned WrapperKind = X86ISD::Wrapper;
11177 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11178 GA->getValueType(0),
11179 GA->getOffset(), OperandFlags);
11180 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11182 // Add x@dtpoff with the base.
11183 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11186 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11187 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11188 const EVT PtrVT, TLSModel::Model model,
11189 bool is64Bit, bool isPIC) {
11192 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11193 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11194 is64Bit ? 257 : 256));
11196 SDValue ThreadPointer =
11197 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11198 MachinePointerInfo(Ptr), false, false, false, 0);
11200 unsigned char OperandFlags = 0;
11201 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11203 unsigned WrapperKind = X86ISD::Wrapper;
11204 if (model == TLSModel::LocalExec) {
11205 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11206 } else if (model == TLSModel::InitialExec) {
11208 OperandFlags = X86II::MO_GOTTPOFF;
11209 WrapperKind = X86ISD::WrapperRIP;
11211 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11214 llvm_unreachable("Unexpected model");
11217 // emit "addl x@ntpoff,%eax" (local exec)
11218 // or "addl x@indntpoff,%eax" (initial exec)
11219 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11221 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11222 GA->getOffset(), OperandFlags);
11223 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11225 if (model == TLSModel::InitialExec) {
11226 if (isPIC && !is64Bit) {
11227 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11228 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11232 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11233 MachinePointerInfo::getGOT(), false, false, false, 0);
11236 // The address of the thread local variable is the add of the thread
11237 // pointer with the offset of the variable.
11238 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11242 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11244 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11245 const GlobalValue *GV = GA->getGlobal();
11247 if (Subtarget->isTargetELF()) {
11248 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11251 case TLSModel::GeneralDynamic:
11252 if (Subtarget->is64Bit())
11253 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11254 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11255 case TLSModel::LocalDynamic:
11256 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11257 Subtarget->is64Bit());
11258 case TLSModel::InitialExec:
11259 case TLSModel::LocalExec:
11260 return LowerToTLSExecModel(
11261 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11262 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11264 llvm_unreachable("Unknown TLS model.");
11267 if (Subtarget->isTargetDarwin()) {
11268 // Darwin only has one model of TLS. Lower to that.
11269 unsigned char OpFlag = 0;
11270 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11271 X86ISD::WrapperRIP : X86ISD::Wrapper;
11273 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11274 // global base reg.
11275 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11276 !Subtarget->is64Bit();
11278 OpFlag = X86II::MO_TLVP_PIC_BASE;
11280 OpFlag = X86II::MO_TLVP;
11282 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11283 GA->getValueType(0),
11284 GA->getOffset(), OpFlag);
11285 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11287 // With PIC32, the address is actually $g + Offset.
11289 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11290 DAG.getNode(X86ISD::GlobalBaseReg,
11291 SDLoc(), getPointerTy()),
11294 // Lowering the machine isd will make sure everything is in the right
11296 SDValue Chain = DAG.getEntryNode();
11297 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11298 SDValue Args[] = { Chain, Offset };
11299 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11301 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11302 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11303 MFI->setAdjustsStack(true);
11305 // And our return value (tls address) is in the standard call return value
11307 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11308 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11309 Chain.getValue(1));
11312 if (Subtarget->isTargetKnownWindowsMSVC() ||
11313 Subtarget->isTargetWindowsGNU()) {
11314 // Just use the implicit TLS architecture
11315 // Need to generate someting similar to:
11316 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11318 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11319 // mov rcx, qword [rdx+rcx*8]
11320 // mov eax, .tls$:tlsvar
11321 // [rax+rcx] contains the address
11322 // Windows 64bit: gs:0x58
11323 // Windows 32bit: fs:__tls_array
11326 SDValue Chain = DAG.getEntryNode();
11328 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11329 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11330 // use its literal value of 0x2C.
11331 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11332 ? Type::getInt8PtrTy(*DAG.getContext(),
11334 : Type::getInt32PtrTy(*DAG.getContext(),
11338 Subtarget->is64Bit()
11339 ? DAG.getIntPtrConstant(0x58, dl)
11340 : (Subtarget->isTargetWindowsGNU()
11341 ? DAG.getIntPtrConstant(0x2C, dl)
11342 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11344 SDValue ThreadPointer =
11345 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11346 MachinePointerInfo(Ptr), false, false, false, 0);
11348 // Load the _tls_index variable
11349 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11350 if (Subtarget->is64Bit())
11351 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11352 IDX, MachinePointerInfo(), MVT::i32,
11353 false, false, false, 0);
11355 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11356 false, false, false, 0);
11358 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11360 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11362 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11363 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11364 false, false, false, 0);
11366 // Get the offset of start of .tls section
11367 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11368 GA->getValueType(0),
11369 GA->getOffset(), X86II::MO_SECREL);
11370 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11372 // The address of the thread local variable is the add of the thread
11373 // pointer with the offset of the variable.
11374 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11377 llvm_unreachable("TLS not implemented for this target.");
11380 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11381 /// and take a 2 x i32 value to shift plus a shift amount.
11382 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11383 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11384 MVT VT = Op.getSimpleValueType();
11385 unsigned VTBits = VT.getSizeInBits();
11387 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11388 SDValue ShOpLo = Op.getOperand(0);
11389 SDValue ShOpHi = Op.getOperand(1);
11390 SDValue ShAmt = Op.getOperand(2);
11391 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11392 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11394 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11395 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11396 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11397 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11398 : DAG.getConstant(0, dl, VT);
11400 SDValue Tmp2, Tmp3;
11401 if (Op.getOpcode() == ISD::SHL_PARTS) {
11402 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11403 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11405 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11406 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11409 // If the shift amount is larger or equal than the width of a part we can't
11410 // rely on the results of shld/shrd. Insert a test and select the appropriate
11411 // values for large shift amounts.
11412 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11413 DAG.getConstant(VTBits, dl, MVT::i8));
11414 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11415 AndNode, DAG.getConstant(0, dl, MVT::i8));
11418 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11419 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11420 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11422 if (Op.getOpcode() == ISD::SHL_PARTS) {
11423 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11424 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11426 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11427 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11430 SDValue Ops[2] = { Lo, Hi };
11431 return DAG.getMergeValues(Ops, dl);
11434 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11435 SelectionDAG &DAG) const {
11436 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11439 if (SrcVT.isVector()) {
11440 if (SrcVT.getVectorElementType() == MVT::i1) {
11441 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11442 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11443 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11444 Op.getOperand(0)));
11449 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11450 "Unknown SINT_TO_FP to lower!");
11452 // These are really Legal; return the operand so the caller accepts it as
11454 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11456 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11457 Subtarget->is64Bit()) {
11461 unsigned Size = SrcVT.getSizeInBits()/8;
11462 MachineFunction &MF = DAG.getMachineFunction();
11463 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11464 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11465 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11467 MachinePointerInfo::getFixedStack(SSFI),
11469 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11472 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11474 SelectionDAG &DAG) const {
11478 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11480 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11482 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11484 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11486 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11487 MachineMemOperand *MMO;
11489 int SSFI = FI->getIndex();
11491 DAG.getMachineFunction()
11492 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11493 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11495 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11496 StackSlot = StackSlot.getOperand(1);
11498 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11499 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11501 Tys, Ops, SrcVT, MMO);
11504 Chain = Result.getValue(1);
11505 SDValue InFlag = Result.getValue(2);
11507 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11508 // shouldn't be necessary except that RFP cannot be live across
11509 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11510 MachineFunction &MF = DAG.getMachineFunction();
11511 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11512 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11513 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11514 Tys = DAG.getVTList(MVT::Other);
11516 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11518 MachineMemOperand *MMO =
11519 DAG.getMachineFunction()
11520 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11521 MachineMemOperand::MOStore, SSFISize, SSFISize);
11523 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11524 Ops, Op.getValueType(), MMO);
11525 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11526 MachinePointerInfo::getFixedStack(SSFI),
11527 false, false, false, 0);
11533 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11534 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11535 SelectionDAG &DAG) const {
11536 // This algorithm is not obvious. Here it is what we're trying to output:
11539 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11540 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11542 haddpd %xmm0, %xmm0
11544 pshufd $0x4e, %xmm0, %xmm1
11550 LLVMContext *Context = DAG.getContext();
11552 // Build some magic constants.
11553 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11554 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11555 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11557 SmallVector<Constant*,2> CV1;
11559 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11560 APInt(64, 0x4330000000000000ULL))));
11562 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11563 APInt(64, 0x4530000000000000ULL))));
11564 Constant *C1 = ConstantVector::get(CV1);
11565 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11567 // Load the 64-bit value into an XMM register.
11568 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11570 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11571 MachinePointerInfo::getConstantPool(),
11572 false, false, false, 16);
11573 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11574 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11577 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11578 MachinePointerInfo::getConstantPool(),
11579 false, false, false, 16);
11580 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11581 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11584 if (Subtarget->hasSSE3()) {
11585 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11586 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11588 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11589 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11591 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11592 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11596 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11597 DAG.getIntPtrConstant(0, dl));
11600 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11601 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11602 SelectionDAG &DAG) const {
11604 // FP constant to bias correct the final result.
11605 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11608 // Load the 32-bit value into an XMM register.
11609 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11612 // Zero out the upper parts of the register.
11613 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11615 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11616 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11617 DAG.getIntPtrConstant(0, dl));
11619 // Or the load with the bias.
11620 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11621 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11622 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11623 MVT::v2f64, Load)),
11624 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11625 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11626 MVT::v2f64, Bias)));
11627 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11628 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11629 DAG.getIntPtrConstant(0, dl));
11631 // Subtract the bias.
11632 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11634 // Handle final rounding.
11635 EVT DestVT = Op.getValueType();
11637 if (DestVT.bitsLT(MVT::f64))
11638 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11639 DAG.getIntPtrConstant(0, dl));
11640 if (DestVT.bitsGT(MVT::f64))
11641 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11643 // Handle final rounding.
11647 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11648 const X86Subtarget &Subtarget) {
11649 // The algorithm is the following:
11650 // #ifdef __SSE4_1__
11651 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11652 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11653 // (uint4) 0x53000000, 0xaa);
11655 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11656 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11658 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11659 // return (float4) lo + fhi;
11662 SDValue V = Op->getOperand(0);
11663 EVT VecIntVT = V.getValueType();
11664 bool Is128 = VecIntVT == MVT::v4i32;
11665 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11666 // If we convert to something else than the supported type, e.g., to v4f64,
11668 if (VecFloatVT != Op->getValueType(0))
11671 unsigned NumElts = VecIntVT.getVectorNumElements();
11672 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11673 "Unsupported custom type");
11674 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11676 // In the #idef/#else code, we have in common:
11677 // - The vector of constants:
11683 // Create the splat vector for 0x4b000000.
11684 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11685 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11686 CstLow, CstLow, CstLow, CstLow};
11687 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11688 makeArrayRef(&CstLowArray[0], NumElts));
11689 // Create the splat vector for 0x53000000.
11690 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11691 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11692 CstHigh, CstHigh, CstHigh, CstHigh};
11693 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11694 makeArrayRef(&CstHighArray[0], NumElts));
11696 // Create the right shift.
11697 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11698 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11699 CstShift, CstShift, CstShift, CstShift};
11700 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11701 makeArrayRef(&CstShiftArray[0], NumElts));
11702 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11705 if (Subtarget.hasSSE41()) {
11706 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11707 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11708 SDValue VecCstLowBitcast =
11709 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11710 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11711 // Low will be bitcasted right away, so do not bother bitcasting back to its
11713 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11714 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11715 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11716 // (uint4) 0x53000000, 0xaa);
11717 SDValue VecCstHighBitcast =
11718 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11719 SDValue VecShiftBitcast =
11720 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11721 // High will be bitcasted right away, so do not bother bitcasting back to
11722 // its original type.
11723 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11724 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11726 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11727 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11728 CstMask, CstMask, CstMask);
11729 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11730 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11731 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11733 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11734 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11737 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11738 SDValue CstFAdd = DAG.getConstantFP(
11739 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11740 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11741 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11742 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11743 makeArrayRef(&CstFAddArray[0], NumElts));
11745 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11746 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11748 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11749 // return (float4) lo + fhi;
11750 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11751 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11754 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11755 SelectionDAG &DAG) const {
11756 SDValue N0 = Op.getOperand(0);
11757 MVT SVT = N0.getSimpleValueType();
11760 switch (SVT.SimpleTy) {
11762 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11767 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11768 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11769 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11773 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11775 llvm_unreachable(nullptr);
11778 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11779 SelectionDAG &DAG) const {
11780 SDValue N0 = Op.getOperand(0);
11783 if (Op.getValueType().isVector())
11784 return lowerUINT_TO_FP_vec(Op, DAG);
11786 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11787 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11788 // the optimization here.
11789 if (DAG.SignBitIsZero(N0))
11790 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11792 MVT SrcVT = N0.getSimpleValueType();
11793 MVT DstVT = Op.getSimpleValueType();
11794 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11795 return LowerUINT_TO_FP_i64(Op, DAG);
11796 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11797 return LowerUINT_TO_FP_i32(Op, DAG);
11798 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11801 // Make a 64-bit buffer, and use it to build an FILD.
11802 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11803 if (SrcVT == MVT::i32) {
11804 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11805 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11806 getPointerTy(), StackSlot, WordOff);
11807 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11808 StackSlot, MachinePointerInfo(),
11810 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11811 OffsetSlot, MachinePointerInfo(),
11813 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11817 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11818 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11819 StackSlot, MachinePointerInfo(),
11821 // For i64 source, we need to add the appropriate power of 2 if the input
11822 // was negative. This is the same as the optimization in
11823 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11824 // we must be careful to do the computation in x87 extended precision, not
11825 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11826 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11827 MachineMemOperand *MMO =
11828 DAG.getMachineFunction()
11829 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11830 MachineMemOperand::MOLoad, 8, 8);
11832 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11833 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11834 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11837 APInt FF(32, 0x5F800000ULL);
11839 // Check whether the sign bit is set.
11840 SDValue SignSet = DAG.getSetCC(dl,
11841 getSetCCResultType(*DAG.getContext(), MVT::i64),
11843 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11845 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11846 SDValue FudgePtr = DAG.getConstantPool(
11847 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11850 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11851 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11852 SDValue Four = DAG.getIntPtrConstant(4, dl);
11853 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11855 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11857 // Load the value out, extending it from f32 to f80.
11858 // FIXME: Avoid the extend by constructing the right constant pool?
11859 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11860 FudgePtr, MachinePointerInfo::getConstantPool(),
11861 MVT::f32, false, false, false, 4);
11862 // Extend everything to 80 bits to force it to be done on x87.
11863 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11864 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11865 DAG.getIntPtrConstant(0, dl));
11868 std::pair<SDValue,SDValue>
11869 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11870 bool IsSigned, bool IsReplace) const {
11873 EVT DstTy = Op.getValueType();
11875 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11876 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11880 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11881 DstTy.getSimpleVT() >= MVT::i16 &&
11882 "Unknown FP_TO_INT to lower!");
11884 // These are really Legal.
11885 if (DstTy == MVT::i32 &&
11886 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11887 return std::make_pair(SDValue(), SDValue());
11888 if (Subtarget->is64Bit() &&
11889 DstTy == MVT::i64 &&
11890 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11891 return std::make_pair(SDValue(), SDValue());
11893 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11894 // stack slot, or into the FTOL runtime function.
11895 MachineFunction &MF = DAG.getMachineFunction();
11896 unsigned MemSize = DstTy.getSizeInBits()/8;
11897 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11898 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11901 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11902 Opc = X86ISD::WIN_FTOL;
11904 switch (DstTy.getSimpleVT().SimpleTy) {
11905 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11906 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11907 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11908 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11911 SDValue Chain = DAG.getEntryNode();
11912 SDValue Value = Op.getOperand(0);
11913 EVT TheVT = Op.getOperand(0).getValueType();
11914 // FIXME This causes a redundant load/store if the SSE-class value is already
11915 // in memory, such as if it is on the callstack.
11916 if (isScalarFPTypeInSSEReg(TheVT)) {
11917 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11918 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11919 MachinePointerInfo::getFixedStack(SSFI),
11921 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11923 Chain, StackSlot, DAG.getValueType(TheVT)
11926 MachineMemOperand *MMO =
11927 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11928 MachineMemOperand::MOLoad, MemSize, MemSize);
11929 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11930 Chain = Value.getValue(1);
11931 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11932 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11935 MachineMemOperand *MMO =
11936 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11937 MachineMemOperand::MOStore, MemSize, MemSize);
11939 if (Opc != X86ISD::WIN_FTOL) {
11940 // Build the FP_TO_INT*_IN_MEM
11941 SDValue Ops[] = { Chain, Value, StackSlot };
11942 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11944 return std::make_pair(FIST, StackSlot);
11946 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11947 DAG.getVTList(MVT::Other, MVT::Glue),
11949 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11950 MVT::i32, ftol.getValue(1));
11951 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11952 MVT::i32, eax.getValue(2));
11953 SDValue Ops[] = { eax, edx };
11954 SDValue pair = IsReplace
11955 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11956 : DAG.getMergeValues(Ops, DL);
11957 return std::make_pair(pair, SDValue());
11961 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11962 const X86Subtarget *Subtarget) {
11963 MVT VT = Op->getSimpleValueType(0);
11964 SDValue In = Op->getOperand(0);
11965 MVT InVT = In.getSimpleValueType();
11968 // Optimize vectors in AVX mode:
11971 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11972 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11973 // Concat upper and lower parts.
11976 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11977 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11978 // Concat upper and lower parts.
11981 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11982 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11983 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11986 if (Subtarget->hasInt256())
11987 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11989 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11990 SDValue Undef = DAG.getUNDEF(InVT);
11991 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11992 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11993 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11995 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11996 VT.getVectorNumElements()/2);
11998 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11999 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
12001 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12004 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12005 SelectionDAG &DAG) {
12006 MVT VT = Op->getSimpleValueType(0);
12007 SDValue In = Op->getOperand(0);
12008 MVT InVT = In.getSimpleValueType();
12010 unsigned int NumElts = VT.getVectorNumElements();
12011 if (NumElts != 8 && NumElts != 16)
12014 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12015 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12017 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
12018 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12019 // Now we have only mask extension
12020 assert(InVT.getVectorElementType() == MVT::i1);
12021 SDValue Cst = DAG.getTargetConstant(1, DL, ExtVT.getScalarType());
12022 const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();
12023 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12024 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12025 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12026 MachinePointerInfo::getConstantPool(),
12027 false, false, false, Alignment);
12029 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
12030 if (VT.is512BitVector())
12032 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
12035 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12036 SelectionDAG &DAG) {
12037 if (Subtarget->hasFp256()) {
12038 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12046 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12047 SelectionDAG &DAG) {
12049 MVT VT = Op.getSimpleValueType();
12050 SDValue In = Op.getOperand(0);
12051 MVT SVT = In.getSimpleValueType();
12053 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12054 return LowerZERO_EXTEND_AVX512(Op, DAG);
12056 if (Subtarget->hasFp256()) {
12057 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12062 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12063 VT.getVectorNumElements() != SVT.getVectorNumElements());
12067 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12069 MVT VT = Op.getSimpleValueType();
12070 SDValue In = Op.getOperand(0);
12071 MVT InVT = In.getSimpleValueType();
12073 if (VT == MVT::i1) {
12074 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12075 "Invalid scalar TRUNCATE operation");
12076 if (InVT.getSizeInBits() >= 32)
12078 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12079 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12081 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12082 "Invalid TRUNCATE operation");
12084 // move vector to mask - truncate solution for SKX
12085 if (VT.getVectorElementType() == MVT::i1) {
12086 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12087 Subtarget->hasBWI())
12088 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12089 if ((InVT.is256BitVector() || InVT.is128BitVector())
12090 && InVT.getScalarSizeInBits() <= 16 &&
12091 Subtarget->hasBWI() && Subtarget->hasVLX())
12092 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12093 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12094 Subtarget->hasDQI())
12095 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12096 if ((InVT.is256BitVector() || InVT.is128BitVector())
12097 && InVT.getScalarSizeInBits() >= 32 &&
12098 Subtarget->hasDQI() && Subtarget->hasVLX())
12099 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12101 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12102 if (VT.getVectorElementType().getSizeInBits() >=8)
12103 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12105 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12106 unsigned NumElts = InVT.getVectorNumElements();
12107 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12108 if (InVT.getSizeInBits() < 512) {
12109 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12110 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12114 SDValue Cst = DAG.getTargetConstant(1, DL, InVT.getVectorElementType());
12115 const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();
12116 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12117 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12118 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12119 MachinePointerInfo::getConstantPool(),
12120 false, false, false, Alignment);
12121 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12122 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12123 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12126 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12127 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12128 if (Subtarget->hasInt256()) {
12129 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12130 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12131 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12133 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12134 DAG.getIntPtrConstant(0, DL));
12137 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12138 DAG.getIntPtrConstant(0, DL));
12139 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12140 DAG.getIntPtrConstant(2, DL));
12141 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12142 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12143 static const int ShufMask[] = {0, 2, 4, 6};
12144 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12147 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12148 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12149 if (Subtarget->hasInt256()) {
12150 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12152 SmallVector<SDValue,32> pshufbMask;
12153 for (unsigned i = 0; i < 2; ++i) {
12154 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12155 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12156 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12157 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12158 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12159 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12160 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12161 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12162 for (unsigned j = 0; j < 8; ++j)
12163 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12165 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12166 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12167 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12169 static const int ShufMask[] = {0, 2, -1, -1};
12170 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12172 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12173 DAG.getIntPtrConstant(0, DL));
12174 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12177 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12178 DAG.getIntPtrConstant(0, DL));
12180 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12181 DAG.getIntPtrConstant(4, DL));
12183 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12184 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12186 // The PSHUFB mask:
12187 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12188 -1, -1, -1, -1, -1, -1, -1, -1};
12190 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12191 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12192 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12194 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12195 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12197 // The MOVLHPS Mask:
12198 static const int ShufMask2[] = {0, 1, 4, 5};
12199 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12200 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12203 // Handle truncation of V256 to V128 using shuffles.
12204 if (!VT.is128BitVector() || !InVT.is256BitVector())
12207 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12209 unsigned NumElems = VT.getVectorNumElements();
12210 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12212 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12213 // Prepare truncation shuffle mask
12214 for (unsigned i = 0; i != NumElems; ++i)
12215 MaskVec[i] = i * 2;
12216 SDValue V = DAG.getVectorShuffle(NVT, DL,
12217 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12218 DAG.getUNDEF(NVT), &MaskVec[0]);
12219 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12220 DAG.getIntPtrConstant(0, DL));
12223 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12224 SelectionDAG &DAG) const {
12225 assert(!Op.getSimpleValueType().isVector());
12227 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12228 /*IsSigned=*/ true, /*IsReplace=*/ false);
12229 SDValue FIST = Vals.first, StackSlot = Vals.second;
12230 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12231 if (!FIST.getNode()) return Op;
12233 if (StackSlot.getNode())
12234 // Load the result.
12235 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12236 FIST, StackSlot, MachinePointerInfo(),
12237 false, false, false, 0);
12239 // The node is the result.
12243 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12244 SelectionDAG &DAG) const {
12245 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12246 /*IsSigned=*/ false, /*IsReplace=*/ false);
12247 SDValue FIST = Vals.first, StackSlot = Vals.second;
12248 assert(FIST.getNode() && "Unexpected failure");
12250 if (StackSlot.getNode())
12251 // Load the result.
12252 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12253 FIST, StackSlot, MachinePointerInfo(),
12254 false, false, false, 0);
12256 // The node is the result.
12260 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12262 MVT VT = Op.getSimpleValueType();
12263 SDValue In = Op.getOperand(0);
12264 MVT SVT = In.getSimpleValueType();
12266 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12268 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12269 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12270 In, DAG.getUNDEF(SVT)));
12273 /// The only differences between FABS and FNEG are the mask and the logic op.
12274 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12275 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12276 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12277 "Wrong opcode for lowering FABS or FNEG.");
12279 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12281 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12282 // into an FNABS. We'll lower the FABS after that if it is still in use.
12284 for (SDNode *User : Op->uses())
12285 if (User->getOpcode() == ISD::FNEG)
12288 SDValue Op0 = Op.getOperand(0);
12289 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12292 MVT VT = Op.getSimpleValueType();
12293 // Assume scalar op for initialization; update for vector if needed.
12294 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12295 // generate a 16-byte vector constant and logic op even for the scalar case.
12296 // Using a 16-byte mask allows folding the load of the mask with
12297 // the logic op, so it can save (~4 bytes) on code size.
12299 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12300 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12301 // decide if we should generate a 16-byte constant mask when we only need 4 or
12302 // 8 bytes for the scalar case.
12303 if (VT.isVector()) {
12304 EltVT = VT.getVectorElementType();
12305 NumElts = VT.getVectorNumElements();
12308 unsigned EltBits = EltVT.getSizeInBits();
12309 LLVMContext *Context = DAG.getContext();
12310 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12312 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12313 Constant *C = ConstantInt::get(*Context, MaskElt);
12314 C = ConstantVector::getSplat(NumElts, C);
12315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12316 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12317 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12318 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12319 MachinePointerInfo::getConstantPool(),
12320 false, false, false, Alignment);
12322 if (VT.isVector()) {
12323 // For a vector, cast operands to a vector type, perform the logic op,
12324 // and cast the result back to the original value type.
12325 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12326 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12327 SDValue Operand = IsFNABS ?
12328 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12329 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12330 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12331 return DAG.getNode(ISD::BITCAST, dl, VT,
12332 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12335 // If not vector, then scalar.
12336 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12337 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12338 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12341 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12342 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12343 LLVMContext *Context = DAG.getContext();
12344 SDValue Op0 = Op.getOperand(0);
12345 SDValue Op1 = Op.getOperand(1);
12347 MVT VT = Op.getSimpleValueType();
12348 MVT SrcVT = Op1.getSimpleValueType();
12350 // If second operand is smaller, extend it first.
12351 if (SrcVT.bitsLT(VT)) {
12352 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12355 // And if it is bigger, shrink it first.
12356 if (SrcVT.bitsGT(VT)) {
12357 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12361 // At this point the operands and the result should have the same
12362 // type, and that won't be f80 since that is not custom lowered.
12364 const fltSemantics &Sem =
12365 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12366 const unsigned SizeInBits = VT.getSizeInBits();
12368 SmallVector<Constant *, 4> CV(
12369 VT == MVT::f64 ? 2 : 4,
12370 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12372 // First, clear all bits but the sign bit from the second operand (sign).
12373 CV[0] = ConstantFP::get(*Context,
12374 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12375 Constant *C = ConstantVector::get(CV);
12376 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12377 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12378 MachinePointerInfo::getConstantPool(),
12379 false, false, false, 16);
12380 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12382 // Next, clear the sign bit from the first operand (magnitude).
12383 // If it's a constant, we can clear it here.
12384 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12385 APFloat APF = Op0CN->getValueAPF();
12386 // If the magnitude is a positive zero, the sign bit alone is enough.
12387 if (APF.isPosZero())
12390 CV[0] = ConstantFP::get(*Context, APF);
12392 CV[0] = ConstantFP::get(
12394 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12396 C = ConstantVector::get(CV);
12397 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12398 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12399 MachinePointerInfo::getConstantPool(),
12400 false, false, false, 16);
12401 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12402 if (!isa<ConstantFPSDNode>(Op0))
12403 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12405 // OR the magnitude value with the sign bit.
12406 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12409 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12410 SDValue N0 = Op.getOperand(0);
12412 MVT VT = Op.getSimpleValueType();
12414 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12415 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12416 DAG.getConstant(1, dl, VT));
12417 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12420 // Check whether an OR'd tree is PTEST-able.
12421 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12422 SelectionDAG &DAG) {
12423 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12425 if (!Subtarget->hasSSE41())
12428 if (!Op->hasOneUse())
12431 SDNode *N = Op.getNode();
12434 SmallVector<SDValue, 8> Opnds;
12435 DenseMap<SDValue, unsigned> VecInMap;
12436 SmallVector<SDValue, 8> VecIns;
12437 EVT VT = MVT::Other;
12439 // Recognize a special case where a vector is casted into wide integer to
12441 Opnds.push_back(N->getOperand(0));
12442 Opnds.push_back(N->getOperand(1));
12444 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12445 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12446 // BFS traverse all OR'd operands.
12447 if (I->getOpcode() == ISD::OR) {
12448 Opnds.push_back(I->getOperand(0));
12449 Opnds.push_back(I->getOperand(1));
12450 // Re-evaluate the number of nodes to be traversed.
12451 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12455 // Quit if a non-EXTRACT_VECTOR_ELT
12456 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12459 // Quit if without a constant index.
12460 SDValue Idx = I->getOperand(1);
12461 if (!isa<ConstantSDNode>(Idx))
12464 SDValue ExtractedFromVec = I->getOperand(0);
12465 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12466 if (M == VecInMap.end()) {
12467 VT = ExtractedFromVec.getValueType();
12468 // Quit if not 128/256-bit vector.
12469 if (!VT.is128BitVector() && !VT.is256BitVector())
12471 // Quit if not the same type.
12472 if (VecInMap.begin() != VecInMap.end() &&
12473 VT != VecInMap.begin()->first.getValueType())
12475 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12476 VecIns.push_back(ExtractedFromVec);
12478 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12481 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12482 "Not extracted from 128-/256-bit vector.");
12484 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12486 for (DenseMap<SDValue, unsigned>::const_iterator
12487 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12488 // Quit if not all elements are used.
12489 if (I->second != FullMask)
12493 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12495 // Cast all vectors into TestVT for PTEST.
12496 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12497 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12499 // If more than one full vectors are evaluated, OR them first before PTEST.
12500 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12501 // Each iteration will OR 2 nodes and append the result until there is only
12502 // 1 node left, i.e. the final OR'd value of all vectors.
12503 SDValue LHS = VecIns[Slot];
12504 SDValue RHS = VecIns[Slot + 1];
12505 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12508 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12509 VecIns.back(), VecIns.back());
12512 /// \brief return true if \c Op has a use that doesn't just read flags.
12513 static bool hasNonFlagsUse(SDValue Op) {
12514 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12516 SDNode *User = *UI;
12517 unsigned UOpNo = UI.getOperandNo();
12518 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12519 // Look pass truncate.
12520 UOpNo = User->use_begin().getOperandNo();
12521 User = *User->use_begin();
12524 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12525 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12531 /// Emit nodes that will be selected as "test Op0,Op0", or something
12533 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12534 SelectionDAG &DAG) const {
12535 if (Op.getValueType() == MVT::i1) {
12536 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12537 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12538 DAG.getConstant(0, dl, MVT::i8));
12540 // CF and OF aren't always set the way we want. Determine which
12541 // of these we need.
12542 bool NeedCF = false;
12543 bool NeedOF = false;
12546 case X86::COND_A: case X86::COND_AE:
12547 case X86::COND_B: case X86::COND_BE:
12550 case X86::COND_G: case X86::COND_GE:
12551 case X86::COND_L: case X86::COND_LE:
12552 case X86::COND_O: case X86::COND_NO: {
12553 // Check if we really need to set the
12554 // Overflow flag. If NoSignedWrap is present
12555 // that is not actually needed.
12556 switch (Op->getOpcode()) {
12561 const BinaryWithFlagsSDNode *BinNode =
12562 cast<BinaryWithFlagsSDNode>(Op.getNode());
12563 if (BinNode->Flags.hasNoSignedWrap())
12573 // See if we can use the EFLAGS value from the operand instead of
12574 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12575 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12576 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12577 // Emit a CMP with 0, which is the TEST pattern.
12578 //if (Op.getValueType() == MVT::i1)
12579 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12580 // DAG.getConstant(0, MVT::i1));
12581 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12582 DAG.getConstant(0, dl, Op.getValueType()));
12584 unsigned Opcode = 0;
12585 unsigned NumOperands = 0;
12587 // Truncate operations may prevent the merge of the SETCC instruction
12588 // and the arithmetic instruction before it. Attempt to truncate the operands
12589 // of the arithmetic instruction and use a reduced bit-width instruction.
12590 bool NeedTruncation = false;
12591 SDValue ArithOp = Op;
12592 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12593 SDValue Arith = Op->getOperand(0);
12594 // Both the trunc and the arithmetic op need to have one user each.
12595 if (Arith->hasOneUse())
12596 switch (Arith.getOpcode()) {
12603 NeedTruncation = true;
12609 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12610 // which may be the result of a CAST. We use the variable 'Op', which is the
12611 // non-casted variable when we check for possible users.
12612 switch (ArithOp.getOpcode()) {
12614 // Due to an isel shortcoming, be conservative if this add is likely to be
12615 // selected as part of a load-modify-store instruction. When the root node
12616 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12617 // uses of other nodes in the match, such as the ADD in this case. This
12618 // leads to the ADD being left around and reselected, with the result being
12619 // two adds in the output. Alas, even if none our users are stores, that
12620 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12621 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12622 // climbing the DAG back to the root, and it doesn't seem to be worth the
12624 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12625 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12626 if (UI->getOpcode() != ISD::CopyToReg &&
12627 UI->getOpcode() != ISD::SETCC &&
12628 UI->getOpcode() != ISD::STORE)
12631 if (ConstantSDNode *C =
12632 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12633 // An add of one will be selected as an INC.
12634 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12635 Opcode = X86ISD::INC;
12640 // An add of negative one (subtract of one) will be selected as a DEC.
12641 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12642 Opcode = X86ISD::DEC;
12648 // Otherwise use a regular EFLAGS-setting add.
12649 Opcode = X86ISD::ADD;
12654 // If we have a constant logical shift that's only used in a comparison
12655 // against zero turn it into an equivalent AND. This allows turning it into
12656 // a TEST instruction later.
12657 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12658 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12659 EVT VT = Op.getValueType();
12660 unsigned BitWidth = VT.getSizeInBits();
12661 unsigned ShAmt = Op->getConstantOperandVal(1);
12662 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12664 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12665 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12666 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12667 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12669 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12670 DAG.getConstant(Mask, dl, VT));
12671 DAG.ReplaceAllUsesWith(Op, New);
12677 // If the primary and result isn't used, don't bother using X86ISD::AND,
12678 // because a TEST instruction will be better.
12679 if (!hasNonFlagsUse(Op))
12685 // Due to the ISEL shortcoming noted above, be conservative if this op is
12686 // likely to be selected as part of a load-modify-store instruction.
12687 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12688 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12689 if (UI->getOpcode() == ISD::STORE)
12692 // Otherwise use a regular EFLAGS-setting instruction.
12693 switch (ArithOp.getOpcode()) {
12694 default: llvm_unreachable("unexpected operator!");
12695 case ISD::SUB: Opcode = X86ISD::SUB; break;
12696 case ISD::XOR: Opcode = X86ISD::XOR; break;
12697 case ISD::AND: Opcode = X86ISD::AND; break;
12699 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12700 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12701 if (EFLAGS.getNode())
12704 Opcode = X86ISD::OR;
12718 return SDValue(Op.getNode(), 1);
12724 // If we found that truncation is beneficial, perform the truncation and
12726 if (NeedTruncation) {
12727 EVT VT = Op.getValueType();
12728 SDValue WideVal = Op->getOperand(0);
12729 EVT WideVT = WideVal.getValueType();
12730 unsigned ConvertedOp = 0;
12731 // Use a target machine opcode to prevent further DAGCombine
12732 // optimizations that may separate the arithmetic operations
12733 // from the setcc node.
12734 switch (WideVal.getOpcode()) {
12736 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12737 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12738 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12739 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12740 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12744 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12745 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12746 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12747 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12748 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12754 // Emit a CMP with 0, which is the TEST pattern.
12755 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12756 DAG.getConstant(0, dl, Op.getValueType()));
12758 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12759 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12761 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12762 DAG.ReplaceAllUsesWith(Op, New);
12763 return SDValue(New.getNode(), 1);
12766 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12768 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12769 SDLoc dl, SelectionDAG &DAG) const {
12770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12771 if (C->getAPIntValue() == 0)
12772 return EmitTest(Op0, X86CC, dl, DAG);
12774 if (Op0.getValueType() == MVT::i1)
12775 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12778 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12779 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12780 // Do the comparison at i32 if it's smaller, besides the Atom case.
12781 // This avoids subregister aliasing issues. Keep the smaller reference
12782 // if we're optimizing for size, however, as that'll allow better folding
12783 // of memory operations.
12784 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12785 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12786 Attribute::MinSize) &&
12787 !Subtarget->isAtom()) {
12788 unsigned ExtendOp =
12789 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12790 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12791 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12793 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12794 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12795 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12797 return SDValue(Sub.getNode(), 1);
12799 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12802 /// Convert a comparison if required by the subtarget.
12803 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12804 SelectionDAG &DAG) const {
12805 // If the subtarget does not support the FUCOMI instruction, floating-point
12806 // comparisons have to be converted.
12807 if (Subtarget->hasCMov() ||
12808 Cmp.getOpcode() != X86ISD::CMP ||
12809 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12810 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12813 // The instruction selector will select an FUCOM instruction instead of
12814 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12815 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12816 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12818 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12819 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12820 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12821 DAG.getConstant(8, dl, MVT::i8));
12822 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12823 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12826 /// The minimum architected relative accuracy is 2^-12. We need one
12827 /// Newton-Raphson step to have a good float result (24 bits of precision).
12828 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12829 DAGCombinerInfo &DCI,
12830 unsigned &RefinementSteps,
12831 bool &UseOneConstNR) const {
12832 // FIXME: We should use instruction latency models to calculate the cost of
12833 // each potential sequence, but this is very hard to do reliably because
12834 // at least Intel's Core* chips have variable timing based on the number of
12835 // significant digits in the divisor and/or sqrt operand.
12836 if (!Subtarget->useSqrtEst())
12839 EVT VT = Op.getValueType();
12841 // SSE1 has rsqrtss and rsqrtps.
12842 // TODO: Add support for AVX512 (v16f32).
12843 // It is likely not profitable to do this for f64 because a double-precision
12844 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12845 // instructions: convert to single, rsqrtss, convert back to double, refine
12846 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12847 // along with FMA, this could be a throughput win.
12848 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12849 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12850 RefinementSteps = 1;
12851 UseOneConstNR = false;
12852 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12857 /// The minimum architected relative accuracy is 2^-12. We need one
12858 /// Newton-Raphson step to have a good float result (24 bits of precision).
12859 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12860 DAGCombinerInfo &DCI,
12861 unsigned &RefinementSteps) const {
12862 // FIXME: We should use instruction latency models to calculate the cost of
12863 // each potential sequence, but this is very hard to do reliably because
12864 // at least Intel's Core* chips have variable timing based on the number of
12865 // significant digits in the divisor.
12866 if (!Subtarget->useReciprocalEst())
12869 EVT VT = Op.getValueType();
12871 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12872 // TODO: Add support for AVX512 (v16f32).
12873 // It is likely not profitable to do this for f64 because a double-precision
12874 // reciprocal estimate with refinement on x86 prior to FMA requires
12875 // 15 instructions: convert to single, rcpss, convert back to double, refine
12876 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12877 // along with FMA, this could be a throughput win.
12878 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12879 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12880 RefinementSteps = ReciprocalEstimateRefinementSteps;
12881 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12886 /// If we have at least two divisions that use the same divisor, convert to
12887 /// multplication by a reciprocal. This may need to be adjusted for a given
12888 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12889 /// This is because we still need one division to calculate the reciprocal and
12890 /// then we need two multiplies by that reciprocal as replacements for the
12891 /// original divisions.
12892 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12893 return NumUsers > 1;
12896 static bool isAllOnes(SDValue V) {
12897 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12898 return C && C->isAllOnesValue();
12901 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12902 /// if it's possible.
12903 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12904 SDLoc dl, SelectionDAG &DAG) const {
12905 SDValue Op0 = And.getOperand(0);
12906 SDValue Op1 = And.getOperand(1);
12907 if (Op0.getOpcode() == ISD::TRUNCATE)
12908 Op0 = Op0.getOperand(0);
12909 if (Op1.getOpcode() == ISD::TRUNCATE)
12910 Op1 = Op1.getOperand(0);
12913 if (Op1.getOpcode() == ISD::SHL)
12914 std::swap(Op0, Op1);
12915 if (Op0.getOpcode() == ISD::SHL) {
12916 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12917 if (And00C->getZExtValue() == 1) {
12918 // If we looked past a truncate, check that it's only truncating away
12920 unsigned BitWidth = Op0.getValueSizeInBits();
12921 unsigned AndBitWidth = And.getValueSizeInBits();
12922 if (BitWidth > AndBitWidth) {
12924 DAG.computeKnownBits(Op0, Zeros, Ones);
12925 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12929 RHS = Op0.getOperand(1);
12931 } else if (Op1.getOpcode() == ISD::Constant) {
12932 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12933 uint64_t AndRHSVal = AndRHS->getZExtValue();
12934 SDValue AndLHS = Op0;
12936 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12937 LHS = AndLHS.getOperand(0);
12938 RHS = AndLHS.getOperand(1);
12941 // Use BT if the immediate can't be encoded in a TEST instruction.
12942 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12944 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
12948 if (LHS.getNode()) {
12949 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12950 // instruction. Since the shift amount is in-range-or-undefined, we know
12951 // that doing a bittest on the i32 value is ok. We extend to i32 because
12952 // the encoding for the i16 version is larger than the i32 version.
12953 // Also promote i16 to i32 for performance / code size reason.
12954 if (LHS.getValueType() == MVT::i8 ||
12955 LHS.getValueType() == MVT::i16)
12956 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12958 // If the operand types disagree, extend the shift amount to match. Since
12959 // BT ignores high bits (like shifts) we can use anyextend.
12960 if (LHS.getValueType() != RHS.getValueType())
12961 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12963 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12964 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12965 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12966 DAG.getConstant(Cond, dl, MVT::i8), BT);
12972 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12974 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12979 // SSE Condition code mapping:
12988 switch (SetCCOpcode) {
12989 default: llvm_unreachable("Unexpected SETCC condition");
12991 case ISD::SETEQ: SSECC = 0; break;
12993 case ISD::SETGT: Swap = true; // Fallthrough
12995 case ISD::SETOLT: SSECC = 1; break;
12997 case ISD::SETGE: Swap = true; // Fallthrough
12999 case ISD::SETOLE: SSECC = 2; break;
13000 case ISD::SETUO: SSECC = 3; break;
13002 case ISD::SETNE: SSECC = 4; break;
13003 case ISD::SETULE: Swap = true; // Fallthrough
13004 case ISD::SETUGE: SSECC = 5; break;
13005 case ISD::SETULT: Swap = true; // Fallthrough
13006 case ISD::SETUGT: SSECC = 6; break;
13007 case ISD::SETO: SSECC = 7; break;
13009 case ISD::SETONE: SSECC = 8; break;
13012 std::swap(Op0, Op1);
13017 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13018 // ones, and then concatenate the result back.
13019 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13020 MVT VT = Op.getSimpleValueType();
13022 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13023 "Unsupported value type for operation");
13025 unsigned NumElems = VT.getVectorNumElements();
13027 SDValue CC = Op.getOperand(2);
13029 // Extract the LHS vectors
13030 SDValue LHS = Op.getOperand(0);
13031 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13032 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13034 // Extract the RHS vectors
13035 SDValue RHS = Op.getOperand(1);
13036 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13037 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13039 // Issue the operation on the smaller types and concatenate the result back
13040 MVT EltVT = VT.getVectorElementType();
13041 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13042 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13043 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13044 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13047 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13048 SDValue Op0 = Op.getOperand(0);
13049 SDValue Op1 = Op.getOperand(1);
13050 SDValue CC = Op.getOperand(2);
13051 MVT VT = Op.getSimpleValueType();
13054 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13055 "Unexpected type for boolean compare operation");
13056 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13057 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13058 DAG.getConstant(-1, dl, VT));
13059 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13060 DAG.getConstant(-1, dl, VT));
13061 switch (SetCCOpcode) {
13062 default: llvm_unreachable("Unexpected SETCC condition");
13064 // (x != y) -> ~(x ^ y)
13065 return DAG.getNode(ISD::XOR, dl, VT,
13066 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13067 DAG.getConstant(-1, dl, VT));
13069 // (x == y) -> (x ^ y)
13070 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13073 // (x > y) -> (x & ~y)
13074 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13077 // (x < y) -> (~x & y)
13078 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13081 // (x <= y) -> (~x | y)
13082 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13085 // (x >=y) -> (x | ~y)
13086 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13090 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13091 const X86Subtarget *Subtarget) {
13092 SDValue Op0 = Op.getOperand(0);
13093 SDValue Op1 = Op.getOperand(1);
13094 SDValue CC = Op.getOperand(2);
13095 MVT VT = Op.getSimpleValueType();
13098 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13099 Op.getValueType().getScalarType() == MVT::i1 &&
13100 "Cannot set masked compare for this operation");
13102 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13104 bool Unsigned = false;
13107 switch (SetCCOpcode) {
13108 default: llvm_unreachable("Unexpected SETCC condition");
13109 case ISD::SETNE: SSECC = 4; break;
13110 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13111 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13112 case ISD::SETLT: Swap = true; //fall-through
13113 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13114 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13115 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13116 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13117 case ISD::SETULE: Unsigned = true; //fall-through
13118 case ISD::SETLE: SSECC = 2; break;
13122 std::swap(Op0, Op1);
13124 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13125 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13126 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13127 DAG.getConstant(SSECC, dl, MVT::i8));
13130 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13131 /// operand \p Op1. If non-trivial (for example because it's not constant)
13132 /// return an empty value.
13133 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13135 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13139 MVT VT = Op1.getSimpleValueType();
13140 MVT EVT = VT.getVectorElementType();
13141 unsigned n = VT.getVectorNumElements();
13142 SmallVector<SDValue, 8> ULTOp1;
13144 for (unsigned i = 0; i < n; ++i) {
13145 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13146 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13149 // Avoid underflow.
13150 APInt Val = Elt->getAPIntValue();
13154 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13157 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13160 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13161 SelectionDAG &DAG) {
13162 SDValue Op0 = Op.getOperand(0);
13163 SDValue Op1 = Op.getOperand(1);
13164 SDValue CC = Op.getOperand(2);
13165 MVT VT = Op.getSimpleValueType();
13166 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13167 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13172 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13173 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13176 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13177 unsigned Opc = X86ISD::CMPP;
13178 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13179 assert(VT.getVectorNumElements() <= 16);
13180 Opc = X86ISD::CMPM;
13182 // In the two special cases we can't handle, emit two comparisons.
13185 unsigned CombineOpc;
13186 if (SetCCOpcode == ISD::SETUEQ) {
13187 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13189 assert(SetCCOpcode == ISD::SETONE);
13190 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13193 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13194 DAG.getConstant(CC0, dl, MVT::i8));
13195 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13196 DAG.getConstant(CC1, dl, MVT::i8));
13197 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13199 // Handle all other FP comparisons here.
13200 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13201 DAG.getConstant(SSECC, dl, MVT::i8));
13204 // Break 256-bit integer vector compare into smaller ones.
13205 if (VT.is256BitVector() && !Subtarget->hasInt256())
13206 return Lower256IntVSETCC(Op, DAG);
13208 EVT OpVT = Op1.getValueType();
13209 if (OpVT.getVectorElementType() == MVT::i1)
13210 return LowerBoolVSETCC_AVX512(Op, DAG);
13212 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13213 if (Subtarget->hasAVX512()) {
13214 if (Op1.getValueType().is512BitVector() ||
13215 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13216 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13217 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13219 // In AVX-512 architecture setcc returns mask with i1 elements,
13220 // But there is no compare instruction for i8 and i16 elements in KNL.
13221 // We are not talking about 512-bit operands in this case, these
13222 // types are illegal.
13224 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13225 OpVT.getVectorElementType().getSizeInBits() >= 8))
13226 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13227 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13230 // We are handling one of the integer comparisons here. Since SSE only has
13231 // GT and EQ comparisons for integer, swapping operands and multiple
13232 // operations may be required for some comparisons.
13234 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13235 bool Subus = false;
13237 switch (SetCCOpcode) {
13238 default: llvm_unreachable("Unexpected SETCC condition");
13239 case ISD::SETNE: Invert = true;
13240 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13241 case ISD::SETLT: Swap = true;
13242 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13243 case ISD::SETGE: Swap = true;
13244 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13245 Invert = true; break;
13246 case ISD::SETULT: Swap = true;
13247 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13248 FlipSigns = true; break;
13249 case ISD::SETUGE: Swap = true;
13250 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13251 FlipSigns = true; Invert = true; break;
13254 // Special case: Use min/max operations for SETULE/SETUGE
13255 MVT VET = VT.getVectorElementType();
13257 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13258 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13261 switch (SetCCOpcode) {
13263 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13264 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13267 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13270 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13271 if (!MinMax && hasSubus) {
13272 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13274 // t = psubus Op0, Op1
13275 // pcmpeq t, <0..0>
13276 switch (SetCCOpcode) {
13278 case ISD::SETULT: {
13279 // If the comparison is against a constant we can turn this into a
13280 // setule. With psubus, setule does not require a swap. This is
13281 // beneficial because the constant in the register is no longer
13282 // destructed as the destination so it can be hoisted out of a loop.
13283 // Only do this pre-AVX since vpcmp* is no longer destructive.
13284 if (Subtarget->hasAVX())
13286 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13287 if (ULEOp1.getNode()) {
13289 Subus = true; Invert = false; Swap = false;
13293 // Psubus is better than flip-sign because it requires no inversion.
13294 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13295 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13299 Opc = X86ISD::SUBUS;
13305 std::swap(Op0, Op1);
13307 // Check that the operation in question is available (most are plain SSE2,
13308 // but PCMPGTQ and PCMPEQQ have different requirements).
13309 if (VT == MVT::v2i64) {
13310 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13311 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13313 // First cast everything to the right type.
13314 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13315 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13317 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13318 // bits of the inputs before performing those operations. The lower
13319 // compare is always unsigned.
13322 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13324 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13325 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13326 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13327 Sign, Zero, Sign, Zero);
13329 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13330 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13332 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13333 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13334 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13336 // Create masks for only the low parts/high parts of the 64 bit integers.
13337 static const int MaskHi[] = { 1, 1, 3, 3 };
13338 static const int MaskLo[] = { 0, 0, 2, 2 };
13339 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13340 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13341 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13343 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13344 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13347 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13349 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13352 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13353 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13354 // pcmpeqd + pshufd + pand.
13355 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13357 // First cast everything to the right type.
13358 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13359 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13362 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13364 // Make sure the lower and upper halves are both all-ones.
13365 static const int Mask[] = { 1, 0, 3, 2 };
13366 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13367 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13370 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13372 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13376 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13377 // bits of the inputs before performing those operations.
13379 EVT EltVT = VT.getVectorElementType();
13380 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13382 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13383 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13386 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13388 // If the logical-not of the result is required, perform that now.
13390 Result = DAG.getNOT(dl, Result, VT);
13393 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13396 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13397 getZeroVector(VT, Subtarget, DAG, dl));
13402 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13404 MVT VT = Op.getSimpleValueType();
13406 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13408 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13409 && "SetCC type must be 8-bit or 1-bit integer");
13410 SDValue Op0 = Op.getOperand(0);
13411 SDValue Op1 = Op.getOperand(1);
13413 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13415 // Optimize to BT if possible.
13416 // Lower (X & (1 << N)) == 0 to BT(X, N).
13417 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13418 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13419 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13420 Op1.getOpcode() == ISD::Constant &&
13421 cast<ConstantSDNode>(Op1)->isNullValue() &&
13422 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13423 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13424 if (NewSetCC.getNode()) {
13426 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13431 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13433 if (Op1.getOpcode() == ISD::Constant &&
13434 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13435 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13436 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13438 // If the input is a setcc, then reuse the input setcc or use a new one with
13439 // the inverted condition.
13440 if (Op0.getOpcode() == X86ISD::SETCC) {
13441 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13442 bool Invert = (CC == ISD::SETNE) ^
13443 cast<ConstantSDNode>(Op1)->isNullValue();
13447 CCode = X86::GetOppositeBranchCondition(CCode);
13448 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13449 DAG.getConstant(CCode, dl, MVT::i8),
13450 Op0.getOperand(1));
13452 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13456 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13457 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13458 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13460 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13461 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13464 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13465 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13466 if (X86CC == X86::COND_INVALID)
13469 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13470 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13471 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13472 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13474 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13478 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13479 static bool isX86LogicalCmp(SDValue Op) {
13480 unsigned Opc = Op.getNode()->getOpcode();
13481 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13482 Opc == X86ISD::SAHF)
13484 if (Op.getResNo() == 1 &&
13485 (Opc == X86ISD::ADD ||
13486 Opc == X86ISD::SUB ||
13487 Opc == X86ISD::ADC ||
13488 Opc == X86ISD::SBB ||
13489 Opc == X86ISD::SMUL ||
13490 Opc == X86ISD::UMUL ||
13491 Opc == X86ISD::INC ||
13492 Opc == X86ISD::DEC ||
13493 Opc == X86ISD::OR ||
13494 Opc == X86ISD::XOR ||
13495 Opc == X86ISD::AND))
13498 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13504 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13505 if (V.getOpcode() != ISD::TRUNCATE)
13508 SDValue VOp0 = V.getOperand(0);
13509 unsigned InBits = VOp0.getValueSizeInBits();
13510 unsigned Bits = V.getValueSizeInBits();
13511 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13514 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13515 bool addTest = true;
13516 SDValue Cond = Op.getOperand(0);
13517 SDValue Op1 = Op.getOperand(1);
13518 SDValue Op2 = Op.getOperand(2);
13520 EVT VT = Op1.getValueType();
13523 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13524 // are available or VBLENDV if AVX is available.
13525 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13526 if (Cond.getOpcode() == ISD::SETCC &&
13527 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13528 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13529 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13530 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13531 int SSECC = translateX86FSETCC(
13532 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13535 if (Subtarget->hasAVX512()) {
13536 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13537 DAG.getConstant(SSECC, DL, MVT::i8));
13538 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13541 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13542 DAG.getConstant(SSECC, DL, MVT::i8));
13544 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13545 // of 3 logic instructions for size savings and potentially speed.
13546 // Unfortunately, there is no scalar form of VBLENDV.
13548 // If either operand is a constant, don't try this. We can expect to
13549 // optimize away at least one of the logic instructions later in that
13550 // case, so that sequence would be faster than a variable blend.
13552 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13553 // uses XMM0 as the selection register. That may need just as many
13554 // instructions as the AND/ANDN/OR sequence due to register moves, so
13557 if (Subtarget->hasAVX() &&
13558 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13560 // Convert to vectors, do a VSELECT, and convert back to scalar.
13561 // All of the conversions should be optimized away.
13563 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13564 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13565 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13566 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13568 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13569 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13571 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13573 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13574 VSel, DAG.getIntPtrConstant(0, DL));
13576 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13577 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13578 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13582 if (Cond.getOpcode() == ISD::SETCC) {
13583 SDValue NewCond = LowerSETCC(Cond, DAG);
13584 if (NewCond.getNode())
13588 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13589 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13590 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13591 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13592 if (Cond.getOpcode() == X86ISD::SETCC &&
13593 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13594 isZero(Cond.getOperand(1).getOperand(1))) {
13595 SDValue Cmp = Cond.getOperand(1);
13597 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13599 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13600 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13601 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13603 SDValue CmpOp0 = Cmp.getOperand(0);
13604 // Apply further optimizations for special cases
13605 // (select (x != 0), -1, 0) -> neg & sbb
13606 // (select (x == 0), 0, -1) -> neg & sbb
13607 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13608 if (YC->isNullValue() &&
13609 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13610 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13611 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13612 DAG.getConstant(0, DL,
13613 CmpOp0.getValueType()),
13615 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13616 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13617 SDValue(Neg.getNode(), 1));
13621 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13622 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13623 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13625 SDValue Res = // Res = 0 or -1.
13626 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13627 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13629 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13630 Res = DAG.getNOT(DL, Res, Res.getValueType());
13632 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13633 if (!N2C || !N2C->isNullValue())
13634 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13639 // Look past (and (setcc_carry (cmp ...)), 1).
13640 if (Cond.getOpcode() == ISD::AND &&
13641 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13643 if (C && C->getAPIntValue() == 1)
13644 Cond = Cond.getOperand(0);
13647 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13648 // setting operand in place of the X86ISD::SETCC.
13649 unsigned CondOpcode = Cond.getOpcode();
13650 if (CondOpcode == X86ISD::SETCC ||
13651 CondOpcode == X86ISD::SETCC_CARRY) {
13652 CC = Cond.getOperand(0);
13654 SDValue Cmp = Cond.getOperand(1);
13655 unsigned Opc = Cmp.getOpcode();
13656 MVT VT = Op.getSimpleValueType();
13658 bool IllegalFPCMov = false;
13659 if (VT.isFloatingPoint() && !VT.isVector() &&
13660 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13661 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13663 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13664 Opc == X86ISD::BT) { // FIXME
13668 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13669 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13670 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13671 Cond.getOperand(0).getValueType() != MVT::i8)) {
13672 SDValue LHS = Cond.getOperand(0);
13673 SDValue RHS = Cond.getOperand(1);
13674 unsigned X86Opcode;
13677 switch (CondOpcode) {
13678 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13679 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13680 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13681 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13682 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13683 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13684 default: llvm_unreachable("unexpected overflowing operator");
13686 if (CondOpcode == ISD::UMULO)
13687 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13690 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13692 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13694 if (CondOpcode == ISD::UMULO)
13695 Cond = X86Op.getValue(2);
13697 Cond = X86Op.getValue(1);
13699 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13704 // Look pass the truncate if the high bits are known zero.
13705 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13706 Cond = Cond.getOperand(0);
13708 // We know the result of AND is compared against zero. Try to match
13710 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13711 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13712 if (NewSetCC.getNode()) {
13713 CC = NewSetCC.getOperand(0);
13714 Cond = NewSetCC.getOperand(1);
13721 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13722 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13725 // a < b ? -1 : 0 -> RES = ~setcc_carry
13726 // a < b ? 0 : -1 -> RES = setcc_carry
13727 // a >= b ? -1 : 0 -> RES = setcc_carry
13728 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13729 if (Cond.getOpcode() == X86ISD::SUB) {
13730 Cond = ConvertCmpIfNecessary(Cond, DAG);
13731 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13733 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13734 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13735 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13736 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13738 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13739 return DAG.getNOT(DL, Res, Res.getValueType());
13744 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13745 // widen the cmov and push the truncate through. This avoids introducing a new
13746 // branch during isel and doesn't add any extensions.
13747 if (Op.getValueType() == MVT::i8 &&
13748 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13749 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13750 if (T1.getValueType() == T2.getValueType() &&
13751 // Blacklist CopyFromReg to avoid partial register stalls.
13752 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13753 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13754 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13755 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13759 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13760 // condition is true.
13761 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13762 SDValue Ops[] = { Op2, Op1, CC, Cond };
13763 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13766 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13767 SelectionDAG &DAG) {
13768 MVT VT = Op->getSimpleValueType(0);
13769 SDValue In = Op->getOperand(0);
13770 MVT InVT = In.getSimpleValueType();
13771 MVT VTElt = VT.getVectorElementType();
13772 MVT InVTElt = InVT.getVectorElementType();
13776 if ((InVTElt == MVT::i1) &&
13777 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13778 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13780 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13781 VTElt.getSizeInBits() <= 16)) ||
13783 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13784 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13786 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13787 VTElt.getSizeInBits() >= 32))))
13788 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13790 unsigned int NumElts = VT.getVectorNumElements();
13792 if (NumElts != 8 && NumElts != 16)
13795 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13796 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13797 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13798 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13801 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13802 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13804 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13805 Constant *C = ConstantInt::get(*DAG.getContext(),
13806 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13808 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13809 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13810 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13811 MachinePointerInfo::getConstantPool(),
13812 false, false, false, Alignment);
13813 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13814 if (VT.is512BitVector())
13816 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13819 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13820 SelectionDAG &DAG) {
13821 MVT VT = Op->getSimpleValueType(0);
13822 SDValue In = Op->getOperand(0);
13823 MVT InVT = In.getSimpleValueType();
13826 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13827 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13829 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13830 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13831 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13834 if (Subtarget->hasInt256())
13835 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13837 // Optimize vectors in AVX mode
13838 // Sign extend v8i16 to v8i32 and
13841 // Divide input vector into two parts
13842 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13843 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13844 // concat the vectors to original VT
13846 unsigned NumElems = InVT.getVectorNumElements();
13847 SDValue Undef = DAG.getUNDEF(InVT);
13849 SmallVector<int,8> ShufMask1(NumElems, -1);
13850 for (unsigned i = 0; i != NumElems/2; ++i)
13853 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13855 SmallVector<int,8> ShufMask2(NumElems, -1);
13856 for (unsigned i = 0; i != NumElems/2; ++i)
13857 ShufMask2[i] = i + NumElems/2;
13859 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13861 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13862 VT.getVectorNumElements()/2);
13864 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13865 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13867 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13870 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13871 // may emit an illegal shuffle but the expansion is still better than scalar
13872 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13873 // we'll emit a shuffle and a arithmetic shift.
13874 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13875 // TODO: It is possible to support ZExt by zeroing the undef values during
13876 // the shuffle phase or after the shuffle.
13877 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13878 SelectionDAG &DAG) {
13879 MVT RegVT = Op.getSimpleValueType();
13880 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13881 assert(RegVT.isInteger() &&
13882 "We only custom lower integer vector sext loads.");
13884 // Nothing useful we can do without SSE2 shuffles.
13885 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13887 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13889 EVT MemVT = Ld->getMemoryVT();
13890 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13891 unsigned RegSz = RegVT.getSizeInBits();
13893 ISD::LoadExtType Ext = Ld->getExtensionType();
13895 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13896 && "Only anyext and sext are currently implemented.");
13897 assert(MemVT != RegVT && "Cannot extend to the same type");
13898 assert(MemVT.isVector() && "Must load a vector from memory");
13900 unsigned NumElems = RegVT.getVectorNumElements();
13901 unsigned MemSz = MemVT.getSizeInBits();
13902 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13904 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13905 // The only way in which we have a legal 256-bit vector result but not the
13906 // integer 256-bit operations needed to directly lower a sextload is if we
13907 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13908 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13909 // correctly legalized. We do this late to allow the canonical form of
13910 // sextload to persist throughout the rest of the DAG combiner -- it wants
13911 // to fold together any extensions it can, and so will fuse a sign_extend
13912 // of an sextload into a sextload targeting a wider value.
13914 if (MemSz == 128) {
13915 // Just switch this to a normal load.
13916 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13917 "it must be a legal 128-bit vector "
13919 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13920 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13921 Ld->isInvariant(), Ld->getAlignment());
13923 assert(MemSz < 128 &&
13924 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13925 // Do an sext load to a 128-bit vector type. We want to use the same
13926 // number of elements, but elements half as wide. This will end up being
13927 // recursively lowered by this routine, but will succeed as we definitely
13928 // have all the necessary features if we're using AVX1.
13930 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13931 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13933 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13934 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13935 Ld->isNonTemporal(), Ld->isInvariant(),
13936 Ld->getAlignment());
13939 // Replace chain users with the new chain.
13940 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13941 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13943 // Finally, do a normal sign-extend to the desired register.
13944 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13947 // All sizes must be a power of two.
13948 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13949 "Non-power-of-two elements are not custom lowered!");
13951 // Attempt to load the original value using scalar loads.
13952 // Find the largest scalar type that divides the total loaded size.
13953 MVT SclrLoadTy = MVT::i8;
13954 for (MVT Tp : MVT::integer_valuetypes()) {
13955 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13960 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13961 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13963 SclrLoadTy = MVT::f64;
13965 // Calculate the number of scalar loads that we need to perform
13966 // in order to load our vector from memory.
13967 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13969 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13970 "Can only lower sext loads with a single scalar load!");
13972 unsigned loadRegZize = RegSz;
13973 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13976 // Represent our vector as a sequence of elements which are the
13977 // largest scalar that we can load.
13978 EVT LoadUnitVecVT = EVT::getVectorVT(
13979 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13981 // Represent the data using the same element type that is stored in
13982 // memory. In practice, we ''widen'' MemVT.
13984 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13985 loadRegZize / MemVT.getScalarType().getSizeInBits());
13987 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13988 "Invalid vector type");
13990 // We can't shuffle using an illegal type.
13991 assert(TLI.isTypeLegal(WideVecVT) &&
13992 "We only lower types that form legal widened vector types");
13994 SmallVector<SDValue, 8> Chains;
13995 SDValue Ptr = Ld->getBasePtr();
13996 SDValue Increment =
13997 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
13998 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14000 for (unsigned i = 0; i < NumLoads; ++i) {
14001 // Perform a single load.
14002 SDValue ScalarLoad =
14003 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14004 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14005 Ld->getAlignment());
14006 Chains.push_back(ScalarLoad.getValue(1));
14007 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14008 // another round of DAGCombining.
14010 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14012 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14013 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14015 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14018 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14020 // Bitcast the loaded value to a vector of the original element type, in
14021 // the size of the target vector type.
14022 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14023 unsigned SizeRatio = RegSz / MemSz;
14025 if (Ext == ISD::SEXTLOAD) {
14026 // If we have SSE4.1, we can directly emit a VSEXT node.
14027 if (Subtarget->hasSSE41()) {
14028 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14029 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14033 // Otherwise we'll shuffle the small elements in the high bits of the
14034 // larger type and perform an arithmetic shift. If the shift is not legal
14035 // it's better to scalarize.
14036 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14037 "We can't implement a sext load without an arithmetic right shift!");
14039 // Redistribute the loaded elements into the different locations.
14040 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14041 for (unsigned i = 0; i != NumElems; ++i)
14042 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14044 SDValue Shuff = DAG.getVectorShuffle(
14045 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14047 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14049 // Build the arithmetic shift.
14050 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14051 MemVT.getVectorElementType().getSizeInBits();
14053 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14054 DAG.getConstant(Amt, dl, RegVT));
14056 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14060 // Redistribute the loaded elements into the different locations.
14061 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14062 for (unsigned i = 0; i != NumElems; ++i)
14063 ShuffleVec[i * SizeRatio] = i;
14065 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14066 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14068 // Bitcast to the requested type.
14069 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14070 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14074 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14075 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14076 // from the AND / OR.
14077 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14078 Opc = Op.getOpcode();
14079 if (Opc != ISD::OR && Opc != ISD::AND)
14081 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14082 Op.getOperand(0).hasOneUse() &&
14083 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14084 Op.getOperand(1).hasOneUse());
14087 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14088 // 1 and that the SETCC node has a single use.
14089 static bool isXor1OfSetCC(SDValue Op) {
14090 if (Op.getOpcode() != ISD::XOR)
14092 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14093 if (N1C && N1C->getAPIntValue() == 1) {
14094 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14095 Op.getOperand(0).hasOneUse();
14100 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14101 bool addTest = true;
14102 SDValue Chain = Op.getOperand(0);
14103 SDValue Cond = Op.getOperand(1);
14104 SDValue Dest = Op.getOperand(2);
14107 bool Inverted = false;
14109 if (Cond.getOpcode() == ISD::SETCC) {
14110 // Check for setcc([su]{add,sub,mul}o == 0).
14111 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14112 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14113 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14114 Cond.getOperand(0).getResNo() == 1 &&
14115 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14116 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14117 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14118 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14119 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14120 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14122 Cond = Cond.getOperand(0);
14124 SDValue NewCond = LowerSETCC(Cond, DAG);
14125 if (NewCond.getNode())
14130 // FIXME: LowerXALUO doesn't handle these!!
14131 else if (Cond.getOpcode() == X86ISD::ADD ||
14132 Cond.getOpcode() == X86ISD::SUB ||
14133 Cond.getOpcode() == X86ISD::SMUL ||
14134 Cond.getOpcode() == X86ISD::UMUL)
14135 Cond = LowerXALUO(Cond, DAG);
14138 // Look pass (and (setcc_carry (cmp ...)), 1).
14139 if (Cond.getOpcode() == ISD::AND &&
14140 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14141 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14142 if (C && C->getAPIntValue() == 1)
14143 Cond = Cond.getOperand(0);
14146 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14147 // setting operand in place of the X86ISD::SETCC.
14148 unsigned CondOpcode = Cond.getOpcode();
14149 if (CondOpcode == X86ISD::SETCC ||
14150 CondOpcode == X86ISD::SETCC_CARRY) {
14151 CC = Cond.getOperand(0);
14153 SDValue Cmp = Cond.getOperand(1);
14154 unsigned Opc = Cmp.getOpcode();
14155 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14156 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14160 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14164 // These can only come from an arithmetic instruction with overflow,
14165 // e.g. SADDO, UADDO.
14166 Cond = Cond.getNode()->getOperand(1);
14172 CondOpcode = Cond.getOpcode();
14173 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14174 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14175 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14176 Cond.getOperand(0).getValueType() != MVT::i8)) {
14177 SDValue LHS = Cond.getOperand(0);
14178 SDValue RHS = Cond.getOperand(1);
14179 unsigned X86Opcode;
14182 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14183 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14185 switch (CondOpcode) {
14186 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14188 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14190 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14193 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14194 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14196 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14198 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14201 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14202 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14203 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14204 default: llvm_unreachable("unexpected overflowing operator");
14207 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14208 if (CondOpcode == ISD::UMULO)
14209 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14212 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14214 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14216 if (CondOpcode == ISD::UMULO)
14217 Cond = X86Op.getValue(2);
14219 Cond = X86Op.getValue(1);
14221 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14225 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14226 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14227 if (CondOpc == ISD::OR) {
14228 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14229 // two branches instead of an explicit OR instruction with a
14231 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14232 isX86LogicalCmp(Cmp)) {
14233 CC = Cond.getOperand(0).getOperand(0);
14234 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14235 Chain, Dest, CC, Cmp);
14236 CC = Cond.getOperand(1).getOperand(0);
14240 } else { // ISD::AND
14241 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14242 // two branches instead of an explicit AND instruction with a
14243 // separate test. However, we only do this if this block doesn't
14244 // have a fall-through edge, because this requires an explicit
14245 // jmp when the condition is false.
14246 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14247 isX86LogicalCmp(Cmp) &&
14248 Op.getNode()->hasOneUse()) {
14249 X86::CondCode CCode =
14250 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14251 CCode = X86::GetOppositeBranchCondition(CCode);
14252 CC = DAG.getConstant(CCode, dl, MVT::i8);
14253 SDNode *User = *Op.getNode()->use_begin();
14254 // Look for an unconditional branch following this conditional branch.
14255 // We need this because we need to reverse the successors in order
14256 // to implement FCMP_OEQ.
14257 if (User->getOpcode() == ISD::BR) {
14258 SDValue FalseBB = User->getOperand(1);
14260 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14261 assert(NewBR == User);
14265 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14266 Chain, Dest, CC, Cmp);
14267 X86::CondCode CCode =
14268 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14269 CCode = X86::GetOppositeBranchCondition(CCode);
14270 CC = DAG.getConstant(CCode, dl, MVT::i8);
14276 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14277 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14278 // It should be transformed during dag combiner except when the condition
14279 // is set by a arithmetics with overflow node.
14280 X86::CondCode CCode =
14281 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14282 CCode = X86::GetOppositeBranchCondition(CCode);
14283 CC = DAG.getConstant(CCode, dl, MVT::i8);
14284 Cond = Cond.getOperand(0).getOperand(1);
14286 } else if (Cond.getOpcode() == ISD::SETCC &&
14287 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14288 // For FCMP_OEQ, we can emit
14289 // two branches instead of an explicit AND instruction with a
14290 // separate test. However, we only do this if this block doesn't
14291 // have a fall-through edge, because this requires an explicit
14292 // jmp when the condition is false.
14293 if (Op.getNode()->hasOneUse()) {
14294 SDNode *User = *Op.getNode()->use_begin();
14295 // Look for an unconditional branch following this conditional branch.
14296 // We need this because we need to reverse the successors in order
14297 // to implement FCMP_OEQ.
14298 if (User->getOpcode() == ISD::BR) {
14299 SDValue FalseBB = User->getOperand(1);
14301 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14302 assert(NewBR == User);
14306 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14307 Cond.getOperand(0), Cond.getOperand(1));
14308 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14309 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14310 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14311 Chain, Dest, CC, Cmp);
14312 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14317 } else if (Cond.getOpcode() == ISD::SETCC &&
14318 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14319 // For FCMP_UNE, we can emit
14320 // two branches instead of an explicit AND instruction with a
14321 // separate test. However, we only do this if this block doesn't
14322 // have a fall-through edge, because this requires an explicit
14323 // jmp when the condition is false.
14324 if (Op.getNode()->hasOneUse()) {
14325 SDNode *User = *Op.getNode()->use_begin();
14326 // Look for an unconditional branch following this conditional branch.
14327 // We need this because we need to reverse the successors in order
14328 // to implement FCMP_UNE.
14329 if (User->getOpcode() == ISD::BR) {
14330 SDValue FalseBB = User->getOperand(1);
14332 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14333 assert(NewBR == User);
14336 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14337 Cond.getOperand(0), Cond.getOperand(1));
14338 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14339 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14340 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14341 Chain, Dest, CC, Cmp);
14342 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14352 // Look pass the truncate if the high bits are known zero.
14353 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14354 Cond = Cond.getOperand(0);
14356 // We know the result of AND is compared against zero. Try to match
14358 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14359 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14360 if (NewSetCC.getNode()) {
14361 CC = NewSetCC.getOperand(0);
14362 Cond = NewSetCC.getOperand(1);
14369 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14370 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14371 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14373 Cond = ConvertCmpIfNecessary(Cond, DAG);
14374 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14375 Chain, Dest, CC, Cond);
14378 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14379 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14380 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14381 // that the guard pages used by the OS virtual memory manager are allocated in
14382 // correct sequence.
14384 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14385 SelectionDAG &DAG) const {
14386 MachineFunction &MF = DAG.getMachineFunction();
14387 bool SplitStack = MF.shouldSplitStack();
14388 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14394 SDNode* Node = Op.getNode();
14396 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14397 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14398 " not tell us which reg is the stack pointer!");
14399 EVT VT = Node->getValueType(0);
14400 SDValue Tmp1 = SDValue(Node, 0);
14401 SDValue Tmp2 = SDValue(Node, 1);
14402 SDValue Tmp3 = Node->getOperand(2);
14403 SDValue Chain = Tmp1.getOperand(0);
14405 // Chain the dynamic stack allocation so that it doesn't modify the stack
14406 // pointer when other instructions are using the stack.
14407 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14410 SDValue Size = Tmp2.getOperand(1);
14411 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14412 Chain = SP.getValue(1);
14413 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14414 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14415 unsigned StackAlign = TFI.getStackAlignment();
14416 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14417 if (Align > StackAlign)
14418 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14419 DAG.getConstant(-(uint64_t)Align, dl, VT));
14420 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14422 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14423 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14426 SDValue Ops[2] = { Tmp1, Tmp2 };
14427 return DAG.getMergeValues(Ops, dl);
14431 SDValue Chain = Op.getOperand(0);
14432 SDValue Size = Op.getOperand(1);
14433 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14434 EVT VT = Op.getNode()->getValueType(0);
14436 bool Is64Bit = Subtarget->is64Bit();
14437 EVT SPTy = getPointerTy();
14440 MachineRegisterInfo &MRI = MF.getRegInfo();
14443 // The 64 bit implementation of segmented stacks needs to clobber both r10
14444 // r11. This makes it impossible to use it along with nested parameters.
14445 const Function *F = MF.getFunction();
14447 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14449 if (I->hasNestAttr())
14450 report_fatal_error("Cannot use segmented stacks with functions that "
14451 "have nested arguments.");
14454 const TargetRegisterClass *AddrRegClass =
14455 getRegClassFor(getPointerTy());
14456 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14457 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14458 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14459 DAG.getRegister(Vreg, SPTy));
14460 SDValue Ops1[2] = { Value, Chain };
14461 return DAG.getMergeValues(Ops1, dl);
14464 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14466 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14467 Flag = Chain.getValue(1);
14468 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14470 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14472 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14473 unsigned SPReg = RegInfo->getStackRegister();
14474 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14475 Chain = SP.getValue(1);
14478 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14479 DAG.getConstant(-(uint64_t)Align, dl, VT));
14480 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14483 SDValue Ops1[2] = { SP, Chain };
14484 return DAG.getMergeValues(Ops1, dl);
14488 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14489 MachineFunction &MF = DAG.getMachineFunction();
14490 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14492 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14495 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14496 // vastart just stores the address of the VarArgsFrameIndex slot into the
14497 // memory location argument.
14498 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14500 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14501 MachinePointerInfo(SV), false, false, 0);
14505 // gp_offset (0 - 6 * 8)
14506 // fp_offset (48 - 48 + 8 * 16)
14507 // overflow_arg_area (point to parameters coming in memory).
14509 SmallVector<SDValue, 8> MemOps;
14510 SDValue FIN = Op.getOperand(1);
14512 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14513 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14515 FIN, MachinePointerInfo(SV), false, false, 0);
14516 MemOps.push_back(Store);
14519 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14520 FIN, DAG.getIntPtrConstant(4, DL));
14521 Store = DAG.getStore(Op.getOperand(0), DL,
14522 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14524 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14525 MemOps.push_back(Store);
14527 // Store ptr to overflow_arg_area
14528 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14529 FIN, DAG.getIntPtrConstant(4, DL));
14530 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14532 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14533 MachinePointerInfo(SV, 8),
14535 MemOps.push_back(Store);
14537 // Store ptr to reg_save_area.
14538 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14539 FIN, DAG.getIntPtrConstant(8, DL));
14540 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14542 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14543 MachinePointerInfo(SV, 16), false, false, 0);
14544 MemOps.push_back(Store);
14545 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14548 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14549 assert(Subtarget->is64Bit() &&
14550 "LowerVAARG only handles 64-bit va_arg!");
14551 assert((Subtarget->isTargetLinux() ||
14552 Subtarget->isTargetDarwin()) &&
14553 "Unhandled target in LowerVAARG");
14554 assert(Op.getNode()->getNumOperands() == 4);
14555 SDValue Chain = Op.getOperand(0);
14556 SDValue SrcPtr = Op.getOperand(1);
14557 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14558 unsigned Align = Op.getConstantOperandVal(3);
14561 EVT ArgVT = Op.getNode()->getValueType(0);
14562 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14563 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14566 // Decide which area this value should be read from.
14567 // TODO: Implement the AMD64 ABI in its entirety. This simple
14568 // selection mechanism works only for the basic types.
14569 if (ArgVT == MVT::f80) {
14570 llvm_unreachable("va_arg for f80 not yet implemented");
14571 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14572 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14573 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14574 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14576 llvm_unreachable("Unhandled argument type in LowerVAARG");
14579 if (ArgMode == 2) {
14580 // Sanity Check: Make sure using fp_offset makes sense.
14581 assert(!DAG.getTarget().Options.UseSoftFloat &&
14582 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14583 Attribute::NoImplicitFloat)) &&
14584 Subtarget->hasSSE1());
14587 // Insert VAARG_64 node into the DAG
14588 // VAARG_64 returns two values: Variable Argument Address, Chain
14589 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14590 DAG.getConstant(ArgMode, dl, MVT::i8),
14591 DAG.getConstant(Align, dl, MVT::i32)};
14592 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14593 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14594 VTs, InstOps, MVT::i64,
14595 MachinePointerInfo(SV),
14597 /*Volatile=*/false,
14599 /*WriteMem=*/true);
14600 Chain = VAARG.getValue(1);
14602 // Load the next argument and return it
14603 return DAG.getLoad(ArgVT, dl,
14606 MachinePointerInfo(),
14607 false, false, false, 0);
14610 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14611 SelectionDAG &DAG) {
14612 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14613 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14614 SDValue Chain = Op.getOperand(0);
14615 SDValue DstPtr = Op.getOperand(1);
14616 SDValue SrcPtr = Op.getOperand(2);
14617 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14618 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14621 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14622 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14624 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14627 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14628 // amount is a constant. Takes immediate version of shift as input.
14629 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14630 SDValue SrcOp, uint64_t ShiftAmt,
14631 SelectionDAG &DAG) {
14632 MVT ElementType = VT.getVectorElementType();
14634 // Fold this packed shift into its first operand if ShiftAmt is 0.
14638 // Check for ShiftAmt >= element width
14639 if (ShiftAmt >= ElementType.getSizeInBits()) {
14640 if (Opc == X86ISD::VSRAI)
14641 ShiftAmt = ElementType.getSizeInBits() - 1;
14643 return DAG.getConstant(0, dl, VT);
14646 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14647 && "Unknown target vector shift-by-constant node");
14649 // Fold this packed vector shift into a build vector if SrcOp is a
14650 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14651 if (VT == SrcOp.getSimpleValueType() &&
14652 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14653 SmallVector<SDValue, 8> Elts;
14654 unsigned NumElts = SrcOp->getNumOperands();
14655 ConstantSDNode *ND;
14658 default: llvm_unreachable(nullptr);
14659 case X86ISD::VSHLI:
14660 for (unsigned i=0; i!=NumElts; ++i) {
14661 SDValue CurrentOp = SrcOp->getOperand(i);
14662 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14663 Elts.push_back(CurrentOp);
14666 ND = cast<ConstantSDNode>(CurrentOp);
14667 const APInt &C = ND->getAPIntValue();
14668 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14671 case X86ISD::VSRLI:
14672 for (unsigned i=0; i!=NumElts; ++i) {
14673 SDValue CurrentOp = SrcOp->getOperand(i);
14674 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14675 Elts.push_back(CurrentOp);
14678 ND = cast<ConstantSDNode>(CurrentOp);
14679 const APInt &C = ND->getAPIntValue();
14680 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14683 case X86ISD::VSRAI:
14684 for (unsigned i=0; i!=NumElts; ++i) {
14685 SDValue CurrentOp = SrcOp->getOperand(i);
14686 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14687 Elts.push_back(CurrentOp);
14690 ND = cast<ConstantSDNode>(CurrentOp);
14691 const APInt &C = ND->getAPIntValue();
14692 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14697 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14700 return DAG.getNode(Opc, dl, VT, SrcOp,
14701 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14704 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14705 // may or may not be a constant. Takes immediate version of shift as input.
14706 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14707 SDValue SrcOp, SDValue ShAmt,
14708 SelectionDAG &DAG) {
14709 MVT SVT = ShAmt.getSimpleValueType();
14710 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14712 // Catch shift-by-constant.
14713 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14714 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14715 CShAmt->getZExtValue(), DAG);
14717 // Change opcode to non-immediate version
14719 default: llvm_unreachable("Unknown target vector shift node");
14720 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14721 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14722 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14725 const X86Subtarget &Subtarget =
14726 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14727 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14728 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14729 // Let the shuffle legalizer expand this shift amount node.
14730 SDValue Op0 = ShAmt.getOperand(0);
14731 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14732 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14734 // Need to build a vector containing shift amount.
14735 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14736 SmallVector<SDValue, 4> ShOps;
14737 ShOps.push_back(ShAmt);
14738 if (SVT == MVT::i32) {
14739 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14740 ShOps.push_back(DAG.getUNDEF(SVT));
14742 ShOps.push_back(DAG.getUNDEF(SVT));
14744 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14745 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14748 // The return type has to be a 128-bit type with the same element
14749 // type as the input type.
14750 MVT EltVT = VT.getVectorElementType();
14751 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14753 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14754 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14757 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14758 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14759 /// necessary casting for \p Mask when lowering masking intrinsics.
14760 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14761 SDValue PreservedSrc,
14762 const X86Subtarget *Subtarget,
14763 SelectionDAG &DAG) {
14764 EVT VT = Op.getValueType();
14765 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14766 MVT::i1, VT.getVectorNumElements());
14767 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14768 Mask.getValueType().getSizeInBits());
14771 assert(MaskVT.isSimple() && "invalid mask type");
14773 if (isAllOnes(Mask))
14776 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14777 // are extracted by EXTRACT_SUBVECTOR.
14778 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14779 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14780 DAG.getIntPtrConstant(0, dl));
14782 switch (Op.getOpcode()) {
14784 case X86ISD::PCMPEQM:
14785 case X86ISD::PCMPGTM:
14787 case X86ISD::CMPMU:
14788 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14790 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14791 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14792 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14795 /// \brief Creates an SDNode for a predicated scalar operation.
14796 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14797 /// The mask is comming as MVT::i8 and it should be truncated
14798 /// to MVT::i1 while lowering masking intrinsics.
14799 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14800 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14801 /// a scalar instruction.
14802 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14803 SDValue PreservedSrc,
14804 const X86Subtarget *Subtarget,
14805 SelectionDAG &DAG) {
14806 if (isAllOnes(Mask))
14809 EVT VT = Op.getValueType();
14811 // The mask should be of type MVT::i1
14812 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14814 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14815 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14816 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14819 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14820 SelectionDAG &DAG) {
14822 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14823 EVT VT = Op.getValueType();
14824 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14826 switch(IntrData->Type) {
14827 case INTR_TYPE_1OP:
14828 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14829 case INTR_TYPE_2OP:
14830 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14832 case INTR_TYPE_3OP:
14833 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14834 Op.getOperand(2), Op.getOperand(3));
14835 case INTR_TYPE_1OP_MASK_RM: {
14836 SDValue Src = Op.getOperand(1);
14837 SDValue Src0 = Op.getOperand(2);
14838 SDValue Mask = Op.getOperand(3);
14839 SDValue RoundingMode = Op.getOperand(4);
14840 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14842 Mask, Src0, Subtarget, DAG);
14844 case INTR_TYPE_SCALAR_MASK_RM: {
14845 SDValue Src1 = Op.getOperand(1);
14846 SDValue Src2 = Op.getOperand(2);
14847 SDValue Src0 = Op.getOperand(3);
14848 SDValue Mask = Op.getOperand(4);
14849 // There are 2 kinds of intrinsics in this group:
14850 // (1) With supress-all-exceptions (sae) - 6 operands
14851 // (2) With rounding mode and sae - 7 operands.
14852 if (Op.getNumOperands() == 6) {
14853 SDValue Sae = Op.getOperand(5);
14854 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14856 Mask, Src0, Subtarget, DAG);
14858 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
14859 SDValue RoundingMode = Op.getOperand(5);
14860 SDValue Sae = Op.getOperand(6);
14861 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14862 RoundingMode, Sae),
14863 Mask, Src0, Subtarget, DAG);
14865 case INTR_TYPE_2OP_MASK: {
14866 SDValue Src1 = Op.getOperand(1);
14867 SDValue Src2 = Op.getOperand(2);
14868 SDValue PassThru = Op.getOperand(3);
14869 SDValue Mask = Op.getOperand(4);
14870 // We specify 2 possible opcodes for intrinsics with rounding modes.
14871 // First, we check if the intrinsic may have non-default rounding mode,
14872 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14873 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14874 if (IntrWithRoundingModeOpcode != 0) {
14875 SDValue Rnd = Op.getOperand(5);
14876 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14877 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14878 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14879 dl, Op.getValueType(),
14881 Mask, PassThru, Subtarget, DAG);
14884 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14886 Mask, PassThru, Subtarget, DAG);
14888 case FMA_OP_MASK: {
14889 SDValue Src1 = Op.getOperand(1);
14890 SDValue Src2 = Op.getOperand(2);
14891 SDValue Src3 = Op.getOperand(3);
14892 SDValue Mask = Op.getOperand(4);
14893 // We specify 2 possible opcodes for intrinsics with rounding modes.
14894 // First, we check if the intrinsic may have non-default rounding mode,
14895 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14896 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14897 if (IntrWithRoundingModeOpcode != 0) {
14898 SDValue Rnd = Op.getOperand(5);
14899 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14900 X86::STATIC_ROUNDING::CUR_DIRECTION)
14901 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14902 dl, Op.getValueType(),
14903 Src1, Src2, Src3, Rnd),
14904 Mask, Src1, Subtarget, DAG);
14906 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14907 dl, Op.getValueType(),
14909 Mask, Src1, Subtarget, DAG);
14912 case CMP_MASK_CC: {
14913 // Comparison intrinsics with masks.
14914 // Example of transformation:
14915 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14916 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14918 // (v8i1 (insert_subvector undef,
14919 // (v2i1 (and (PCMPEQM %a, %b),
14920 // (extract_subvector
14921 // (v8i1 (bitcast %mask)), 0))), 0))))
14922 EVT VT = Op.getOperand(1).getValueType();
14923 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14924 VT.getVectorNumElements());
14925 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14926 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14927 Mask.getValueType().getSizeInBits());
14929 if (IntrData->Type == CMP_MASK_CC) {
14930 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14931 Op.getOperand(2), Op.getOperand(3));
14933 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14934 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14937 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
14938 DAG.getTargetConstant(0, dl,
14941 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
14942 DAG.getUNDEF(BitcastVT), CmpMask,
14943 DAG.getIntPtrConstant(0, dl));
14944 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
14946 case COMI: { // Comparison intrinsics
14947 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
14948 SDValue LHS = Op.getOperand(1);
14949 SDValue RHS = Op.getOperand(2);
14950 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
14951 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14952 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
14953 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14954 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
14955 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14958 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
14959 Op.getOperand(1), Op.getOperand(2), DAG);
14961 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
14962 Op.getSimpleValueType(),
14964 Op.getOperand(2), DAG),
14965 Op.getOperand(4), Op.getOperand(3), Subtarget,
14967 case COMPRESS_EXPAND_IN_REG: {
14968 SDValue Mask = Op.getOperand(3);
14969 SDValue DataToCompress = Op.getOperand(1);
14970 SDValue PassThru = Op.getOperand(2);
14971 if (isAllOnes(Mask)) // return data as is
14972 return Op.getOperand(1);
14973 EVT VT = Op.getValueType();
14974 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14975 VT.getVectorNumElements());
14976 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14977 Mask.getValueType().getSizeInBits());
14979 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14980 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14981 DAG.getIntPtrConstant(0, dl));
14983 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
14987 SDValue Mask = Op.getOperand(3);
14988 EVT VT = Op.getValueType();
14989 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14990 VT.getVectorNumElements());
14991 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14992 Mask.getValueType().getSizeInBits());
14994 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14995 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14996 DAG.getIntPtrConstant(0, dl));
14997 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15006 default: return SDValue(); // Don't custom lower most intrinsics.
15008 case Intrinsic::x86_avx2_permd:
15009 case Intrinsic::x86_avx2_permps:
15010 // Operands intentionally swapped. Mask is last operand to intrinsic,
15011 // but second operand for node/instruction.
15012 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15013 Op.getOperand(2), Op.getOperand(1));
15015 case Intrinsic::x86_avx512_mask_valign_q_512:
15016 case Intrinsic::x86_avx512_mask_valign_d_512:
15017 // Vector source operands are swapped.
15018 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
15019 Op.getValueType(), Op.getOperand(2),
15022 Op.getOperand(5), Op.getOperand(4),
15025 // ptest and testp intrinsics. The intrinsic these come from are designed to
15026 // return an integer value, not just an instruction so lower it to the ptest
15027 // or testp pattern and a setcc for the result.
15028 case Intrinsic::x86_sse41_ptestz:
15029 case Intrinsic::x86_sse41_ptestc:
15030 case Intrinsic::x86_sse41_ptestnzc:
15031 case Intrinsic::x86_avx_ptestz_256:
15032 case Intrinsic::x86_avx_ptestc_256:
15033 case Intrinsic::x86_avx_ptestnzc_256:
15034 case Intrinsic::x86_avx_vtestz_ps:
15035 case Intrinsic::x86_avx_vtestc_ps:
15036 case Intrinsic::x86_avx_vtestnzc_ps:
15037 case Intrinsic::x86_avx_vtestz_pd:
15038 case Intrinsic::x86_avx_vtestc_pd:
15039 case Intrinsic::x86_avx_vtestnzc_pd:
15040 case Intrinsic::x86_avx_vtestz_ps_256:
15041 case Intrinsic::x86_avx_vtestc_ps_256:
15042 case Intrinsic::x86_avx_vtestnzc_ps_256:
15043 case Intrinsic::x86_avx_vtestz_pd_256:
15044 case Intrinsic::x86_avx_vtestc_pd_256:
15045 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15046 bool IsTestPacked = false;
15049 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15050 case Intrinsic::x86_avx_vtestz_ps:
15051 case Intrinsic::x86_avx_vtestz_pd:
15052 case Intrinsic::x86_avx_vtestz_ps_256:
15053 case Intrinsic::x86_avx_vtestz_pd_256:
15054 IsTestPacked = true; // Fallthrough
15055 case Intrinsic::x86_sse41_ptestz:
15056 case Intrinsic::x86_avx_ptestz_256:
15058 X86CC = X86::COND_E;
15060 case Intrinsic::x86_avx_vtestc_ps:
15061 case Intrinsic::x86_avx_vtestc_pd:
15062 case Intrinsic::x86_avx_vtestc_ps_256:
15063 case Intrinsic::x86_avx_vtestc_pd_256:
15064 IsTestPacked = true; // Fallthrough
15065 case Intrinsic::x86_sse41_ptestc:
15066 case Intrinsic::x86_avx_ptestc_256:
15068 X86CC = X86::COND_B;
15070 case Intrinsic::x86_avx_vtestnzc_ps:
15071 case Intrinsic::x86_avx_vtestnzc_pd:
15072 case Intrinsic::x86_avx_vtestnzc_ps_256:
15073 case Intrinsic::x86_avx_vtestnzc_pd_256:
15074 IsTestPacked = true; // Fallthrough
15075 case Intrinsic::x86_sse41_ptestnzc:
15076 case Intrinsic::x86_avx_ptestnzc_256:
15078 X86CC = X86::COND_A;
15082 SDValue LHS = Op.getOperand(1);
15083 SDValue RHS = Op.getOperand(2);
15084 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15085 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15086 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15087 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15088 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15090 case Intrinsic::x86_avx512_kortestz_w:
15091 case Intrinsic::x86_avx512_kortestc_w: {
15092 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15093 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
15094 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
15095 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15096 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15097 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15098 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15101 case Intrinsic::x86_sse42_pcmpistria128:
15102 case Intrinsic::x86_sse42_pcmpestria128:
15103 case Intrinsic::x86_sse42_pcmpistric128:
15104 case Intrinsic::x86_sse42_pcmpestric128:
15105 case Intrinsic::x86_sse42_pcmpistrio128:
15106 case Intrinsic::x86_sse42_pcmpestrio128:
15107 case Intrinsic::x86_sse42_pcmpistris128:
15108 case Intrinsic::x86_sse42_pcmpestris128:
15109 case Intrinsic::x86_sse42_pcmpistriz128:
15110 case Intrinsic::x86_sse42_pcmpestriz128: {
15114 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15115 case Intrinsic::x86_sse42_pcmpistria128:
15116 Opcode = X86ISD::PCMPISTRI;
15117 X86CC = X86::COND_A;
15119 case Intrinsic::x86_sse42_pcmpestria128:
15120 Opcode = X86ISD::PCMPESTRI;
15121 X86CC = X86::COND_A;
15123 case Intrinsic::x86_sse42_pcmpistric128:
15124 Opcode = X86ISD::PCMPISTRI;
15125 X86CC = X86::COND_B;
15127 case Intrinsic::x86_sse42_pcmpestric128:
15128 Opcode = X86ISD::PCMPESTRI;
15129 X86CC = X86::COND_B;
15131 case Intrinsic::x86_sse42_pcmpistrio128:
15132 Opcode = X86ISD::PCMPISTRI;
15133 X86CC = X86::COND_O;
15135 case Intrinsic::x86_sse42_pcmpestrio128:
15136 Opcode = X86ISD::PCMPESTRI;
15137 X86CC = X86::COND_O;
15139 case Intrinsic::x86_sse42_pcmpistris128:
15140 Opcode = X86ISD::PCMPISTRI;
15141 X86CC = X86::COND_S;
15143 case Intrinsic::x86_sse42_pcmpestris128:
15144 Opcode = X86ISD::PCMPESTRI;
15145 X86CC = X86::COND_S;
15147 case Intrinsic::x86_sse42_pcmpistriz128:
15148 Opcode = X86ISD::PCMPISTRI;
15149 X86CC = X86::COND_E;
15151 case Intrinsic::x86_sse42_pcmpestriz128:
15152 Opcode = X86ISD::PCMPESTRI;
15153 X86CC = X86::COND_E;
15156 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15157 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15158 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15159 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15160 DAG.getConstant(X86CC, dl, MVT::i8),
15161 SDValue(PCMP.getNode(), 1));
15162 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15165 case Intrinsic::x86_sse42_pcmpistri128:
15166 case Intrinsic::x86_sse42_pcmpestri128: {
15168 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15169 Opcode = X86ISD::PCMPISTRI;
15171 Opcode = X86ISD::PCMPESTRI;
15173 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15174 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15175 return DAG.getNode(Opcode, dl, VTs, NewOps);
15180 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15181 SDValue Src, SDValue Mask, SDValue Base,
15182 SDValue Index, SDValue ScaleOp, SDValue Chain,
15183 const X86Subtarget * Subtarget) {
15185 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15186 assert(C && "Invalid scale type");
15187 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15188 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15189 Index.getSimpleValueType().getVectorNumElements());
15191 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15193 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15195 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15196 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15197 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15198 SDValue Segment = DAG.getRegister(0, MVT::i32);
15199 if (Src.getOpcode() == ISD::UNDEF)
15200 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15201 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15202 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15203 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15204 return DAG.getMergeValues(RetOps, dl);
15207 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15208 SDValue Src, SDValue Mask, SDValue Base,
15209 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15211 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15212 assert(C && "Invalid scale type");
15213 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15214 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15215 SDValue Segment = DAG.getRegister(0, MVT::i32);
15216 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15217 Index.getSimpleValueType().getVectorNumElements());
15219 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15221 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15223 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15224 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15225 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15226 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15227 return SDValue(Res, 1);
15230 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15231 SDValue Mask, SDValue Base, SDValue Index,
15232 SDValue ScaleOp, SDValue Chain) {
15234 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15235 assert(C && "Invalid scale type");
15236 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15237 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15238 SDValue Segment = DAG.getRegister(0, MVT::i32);
15240 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15242 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15244 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15246 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15247 //SDVTList VTs = DAG.getVTList(MVT::Other);
15248 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15249 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15250 return SDValue(Res, 0);
15253 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15254 // read performance monitor counters (x86_rdpmc).
15255 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15256 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15257 SmallVectorImpl<SDValue> &Results) {
15258 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15259 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15262 // The ECX register is used to select the index of the performance counter
15264 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15266 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15268 // Reads the content of a 64-bit performance counter and returns it in the
15269 // registers EDX:EAX.
15270 if (Subtarget->is64Bit()) {
15271 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15272 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15275 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15276 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15279 Chain = HI.getValue(1);
15281 if (Subtarget->is64Bit()) {
15282 // The EAX register is loaded with the low-order 32 bits. The EDX register
15283 // is loaded with the supported high-order bits of the counter.
15284 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15285 DAG.getConstant(32, DL, MVT::i8));
15286 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15287 Results.push_back(Chain);
15291 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15292 SDValue Ops[] = { LO, HI };
15293 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15294 Results.push_back(Pair);
15295 Results.push_back(Chain);
15298 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15299 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15300 // also used to custom lower READCYCLECOUNTER nodes.
15301 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15302 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15303 SmallVectorImpl<SDValue> &Results) {
15304 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15305 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15308 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15309 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15310 // and the EAX register is loaded with the low-order 32 bits.
15311 if (Subtarget->is64Bit()) {
15312 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15313 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15316 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15317 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15320 SDValue Chain = HI.getValue(1);
15322 if (Opcode == X86ISD::RDTSCP_DAG) {
15323 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15325 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15326 // the ECX register. Add 'ecx' explicitly to the chain.
15327 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15329 // Explicitly store the content of ECX at the location passed in input
15330 // to the 'rdtscp' intrinsic.
15331 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15332 MachinePointerInfo(), false, false, 0);
15335 if (Subtarget->is64Bit()) {
15336 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15337 // the EAX register is loaded with the low-order 32 bits.
15338 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15339 DAG.getConstant(32, DL, MVT::i8));
15340 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15341 Results.push_back(Chain);
15345 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15346 SDValue Ops[] = { LO, HI };
15347 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15348 Results.push_back(Pair);
15349 Results.push_back(Chain);
15352 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15353 SelectionDAG &DAG) {
15354 SmallVector<SDValue, 2> Results;
15356 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15358 return DAG.getMergeValues(Results, DL);
15362 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15363 SelectionDAG &DAG) {
15364 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15366 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15371 switch(IntrData->Type) {
15373 llvm_unreachable("Unknown Intrinsic Type");
15377 // Emit the node with the right value type.
15378 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15379 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15381 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15382 // Otherwise return the value from Rand, which is always 0, casted to i32.
15383 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15384 DAG.getConstant(1, dl, Op->getValueType(1)),
15385 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15386 SDValue(Result.getNode(), 1) };
15387 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15388 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15391 // Return { result, isValid, chain }.
15392 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15393 SDValue(Result.getNode(), 2));
15396 //gather(v1, mask, index, base, scale);
15397 SDValue Chain = Op.getOperand(0);
15398 SDValue Src = Op.getOperand(2);
15399 SDValue Base = Op.getOperand(3);
15400 SDValue Index = Op.getOperand(4);
15401 SDValue Mask = Op.getOperand(5);
15402 SDValue Scale = Op.getOperand(6);
15403 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15407 //scatter(base, mask, index, v1, scale);
15408 SDValue Chain = Op.getOperand(0);
15409 SDValue Base = Op.getOperand(2);
15410 SDValue Mask = Op.getOperand(3);
15411 SDValue Index = Op.getOperand(4);
15412 SDValue Src = Op.getOperand(5);
15413 SDValue Scale = Op.getOperand(6);
15414 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15417 SDValue Hint = Op.getOperand(6);
15418 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15419 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15420 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15421 SDValue Chain = Op.getOperand(0);
15422 SDValue Mask = Op.getOperand(2);
15423 SDValue Index = Op.getOperand(3);
15424 SDValue Base = Op.getOperand(4);
15425 SDValue Scale = Op.getOperand(5);
15426 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15428 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15430 SmallVector<SDValue, 2> Results;
15431 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15432 return DAG.getMergeValues(Results, dl);
15434 // Read Performance Monitoring Counters.
15436 SmallVector<SDValue, 2> Results;
15437 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15438 return DAG.getMergeValues(Results, dl);
15440 // XTEST intrinsics.
15442 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15443 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15444 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15445 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15447 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15448 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15449 Ret, SDValue(InTrans.getNode(), 1));
15453 SmallVector<SDValue, 2> Results;
15454 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15455 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15456 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15457 DAG.getConstant(-1, dl, MVT::i8));
15458 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15459 Op.getOperand(4), GenCF.getValue(1));
15460 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15461 Op.getOperand(5), MachinePointerInfo(),
15463 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15464 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15466 Results.push_back(SetCC);
15467 Results.push_back(Store);
15468 return DAG.getMergeValues(Results, dl);
15470 case COMPRESS_TO_MEM: {
15472 SDValue Mask = Op.getOperand(4);
15473 SDValue DataToCompress = Op.getOperand(3);
15474 SDValue Addr = Op.getOperand(2);
15475 SDValue Chain = Op.getOperand(0);
15477 if (isAllOnes(Mask)) // return just a store
15478 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15479 MachinePointerInfo(), false, false, 0);
15481 EVT VT = DataToCompress.getValueType();
15482 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15483 VT.getVectorNumElements());
15484 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15485 Mask.getValueType().getSizeInBits());
15486 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15487 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15488 DAG.getIntPtrConstant(0, dl));
15490 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15491 DataToCompress, DAG.getUNDEF(VT));
15492 return DAG.getStore(Chain, dl, Compressed, Addr,
15493 MachinePointerInfo(), false, false, 0);
15495 case EXPAND_FROM_MEM: {
15497 SDValue Mask = Op.getOperand(4);
15498 SDValue PathThru = Op.getOperand(3);
15499 SDValue Addr = Op.getOperand(2);
15500 SDValue Chain = Op.getOperand(0);
15501 EVT VT = Op.getValueType();
15503 if (isAllOnes(Mask)) // return just a load
15504 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15506 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15507 VT.getVectorNumElements());
15508 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15509 Mask.getValueType().getSizeInBits());
15510 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15511 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15512 DAG.getIntPtrConstant(0, dl));
15514 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15515 false, false, false, 0);
15517 SDValue Results[] = {
15518 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15520 return DAG.getMergeValues(Results, dl);
15525 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15526 SelectionDAG &DAG) const {
15527 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15528 MFI->setReturnAddressIsTaken(true);
15530 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15533 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15535 EVT PtrVT = getPointerTy();
15538 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15539 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15540 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15541 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15542 DAG.getNode(ISD::ADD, dl, PtrVT,
15543 FrameAddr, Offset),
15544 MachinePointerInfo(), false, false, false, 0);
15547 // Just load the return address.
15548 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15549 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15550 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15553 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15554 MachineFunction &MF = DAG.getMachineFunction();
15555 MachineFrameInfo *MFI = MF.getFrameInfo();
15556 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15557 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15558 EVT VT = Op.getValueType();
15560 MFI->setFrameAddressIsTaken(true);
15562 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15563 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15564 // is not possible to crawl up the stack without looking at the unwind codes
15566 int FrameAddrIndex = FuncInfo->getFAIndex();
15567 if (!FrameAddrIndex) {
15568 // Set up a frame object for the return address.
15569 unsigned SlotSize = RegInfo->getSlotSize();
15570 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15571 SlotSize, /*Offset=*/INT64_MIN, /*IsImmutable=*/false);
15572 FuncInfo->setFAIndex(FrameAddrIndex);
15574 return DAG.getFrameIndex(FrameAddrIndex, VT);
15577 unsigned FrameReg =
15578 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15579 SDLoc dl(Op); // FIXME probably not meaningful
15580 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15581 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15582 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15583 "Invalid Frame Register!");
15584 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15586 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15587 MachinePointerInfo(),
15588 false, false, false, 0);
15592 // FIXME? Maybe this could be a TableGen attribute on some registers and
15593 // this table could be generated automatically from RegInfo.
15594 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15596 unsigned Reg = StringSwitch<unsigned>(RegName)
15597 .Case("esp", X86::ESP)
15598 .Case("rsp", X86::RSP)
15602 report_fatal_error("Invalid register name global variable");
15605 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15606 SelectionDAG &DAG) const {
15607 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15608 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15611 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15612 SDValue Chain = Op.getOperand(0);
15613 SDValue Offset = Op.getOperand(1);
15614 SDValue Handler = Op.getOperand(2);
15617 EVT PtrVT = getPointerTy();
15618 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15619 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15620 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15621 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15622 "Invalid Frame Register!");
15623 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15624 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15626 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15627 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15629 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15630 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15632 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15634 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15635 DAG.getRegister(StoreAddrReg, PtrVT));
15638 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15639 SelectionDAG &DAG) const {
15641 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15642 DAG.getVTList(MVT::i32, MVT::Other),
15643 Op.getOperand(0), Op.getOperand(1));
15646 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15647 SelectionDAG &DAG) const {
15649 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15650 Op.getOperand(0), Op.getOperand(1));
15653 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15654 return Op.getOperand(0);
15657 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15658 SelectionDAG &DAG) const {
15659 SDValue Root = Op.getOperand(0);
15660 SDValue Trmp = Op.getOperand(1); // trampoline
15661 SDValue FPtr = Op.getOperand(2); // nested function
15662 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15665 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15666 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15668 if (Subtarget->is64Bit()) {
15669 SDValue OutChains[6];
15671 // Large code-model.
15672 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15673 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15675 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15676 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15678 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15680 // Load the pointer to the nested function into R11.
15681 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15682 SDValue Addr = Trmp;
15683 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15684 Addr, MachinePointerInfo(TrmpAddr),
15687 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15688 DAG.getConstant(2, dl, MVT::i64));
15689 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15690 MachinePointerInfo(TrmpAddr, 2),
15693 // Load the 'nest' parameter value into R10.
15694 // R10 is specified in X86CallingConv.td
15695 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15696 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15697 DAG.getConstant(10, dl, MVT::i64));
15698 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15699 Addr, MachinePointerInfo(TrmpAddr, 10),
15702 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15703 DAG.getConstant(12, dl, MVT::i64));
15704 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15705 MachinePointerInfo(TrmpAddr, 12),
15708 // Jump to the nested function.
15709 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15710 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15711 DAG.getConstant(20, dl, MVT::i64));
15712 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15713 Addr, MachinePointerInfo(TrmpAddr, 20),
15716 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15717 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15718 DAG.getConstant(22, dl, MVT::i64));
15719 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
15720 Addr, MachinePointerInfo(TrmpAddr, 22),
15723 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15725 const Function *Func =
15726 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15727 CallingConv::ID CC = Func->getCallingConv();
15732 llvm_unreachable("Unsupported calling convention");
15733 case CallingConv::C:
15734 case CallingConv::X86_StdCall: {
15735 // Pass 'nest' parameter in ECX.
15736 // Must be kept in sync with X86CallingConv.td
15737 NestReg = X86::ECX;
15739 // Check that ECX wasn't needed by an 'inreg' parameter.
15740 FunctionType *FTy = Func->getFunctionType();
15741 const AttributeSet &Attrs = Func->getAttributes();
15743 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15744 unsigned InRegCount = 0;
15747 for (FunctionType::param_iterator I = FTy->param_begin(),
15748 E = FTy->param_end(); I != E; ++I, ++Idx)
15749 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15750 // FIXME: should only count parameters that are lowered to integers.
15751 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15753 if (InRegCount > 2) {
15754 report_fatal_error("Nest register in use - reduce number of inreg"
15760 case CallingConv::X86_FastCall:
15761 case CallingConv::X86_ThisCall:
15762 case CallingConv::Fast:
15763 // Pass 'nest' parameter in EAX.
15764 // Must be kept in sync with X86CallingConv.td
15765 NestReg = X86::EAX;
15769 SDValue OutChains[4];
15770 SDValue Addr, Disp;
15772 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15773 DAG.getConstant(10, dl, MVT::i32));
15774 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15776 // This is storing the opcode for MOV32ri.
15777 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15778 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15779 OutChains[0] = DAG.getStore(Root, dl,
15780 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
15781 Trmp, MachinePointerInfo(TrmpAddr),
15784 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15785 DAG.getConstant(1, dl, MVT::i32));
15786 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15787 MachinePointerInfo(TrmpAddr, 1),
15790 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15791 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15792 DAG.getConstant(5, dl, MVT::i32));
15793 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
15794 Addr, MachinePointerInfo(TrmpAddr, 5),
15797 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15798 DAG.getConstant(6, dl, MVT::i32));
15799 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15800 MachinePointerInfo(TrmpAddr, 6),
15803 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15807 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15808 SelectionDAG &DAG) const {
15810 The rounding mode is in bits 11:10 of FPSR, and has the following
15812 00 Round to nearest
15817 FLT_ROUNDS, on the other hand, expects the following:
15824 To perform the conversion, we do:
15825 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15828 MachineFunction &MF = DAG.getMachineFunction();
15829 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15830 unsigned StackAlignment = TFI.getStackAlignment();
15831 MVT VT = Op.getSimpleValueType();
15834 // Save FP Control Word to stack slot
15835 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15836 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15838 MachineMemOperand *MMO =
15839 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15840 MachineMemOperand::MOStore, 2, 2);
15842 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15843 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15844 DAG.getVTList(MVT::Other),
15845 Ops, MVT::i16, MMO);
15847 // Load FP Control Word from stack slot
15848 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15849 MachinePointerInfo(), false, false, false, 0);
15851 // Transform as necessary
15853 DAG.getNode(ISD::SRL, DL, MVT::i16,
15854 DAG.getNode(ISD::AND, DL, MVT::i16,
15855 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
15856 DAG.getConstant(11, DL, MVT::i8));
15858 DAG.getNode(ISD::SRL, DL, MVT::i16,
15859 DAG.getNode(ISD::AND, DL, MVT::i16,
15860 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
15861 DAG.getConstant(9, DL, MVT::i8));
15864 DAG.getNode(ISD::AND, DL, MVT::i16,
15865 DAG.getNode(ISD::ADD, DL, MVT::i16,
15866 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15867 DAG.getConstant(1, DL, MVT::i16)),
15868 DAG.getConstant(3, DL, MVT::i16));
15870 return DAG.getNode((VT.getSizeInBits() < 16 ?
15871 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15874 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15875 MVT VT = Op.getSimpleValueType();
15877 unsigned NumBits = VT.getSizeInBits();
15880 Op = Op.getOperand(0);
15881 if (VT == MVT::i8) {
15882 // Zero extend to i32 since there is not an i8 bsr.
15884 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15887 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15888 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15889 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15891 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15894 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
15895 DAG.getConstant(X86::COND_E, dl, MVT::i8),
15898 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15900 // Finally xor with NumBits-1.
15901 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
15902 DAG.getConstant(NumBits - 1, dl, OpVT));
15905 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15909 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15910 MVT VT = Op.getSimpleValueType();
15912 unsigned NumBits = VT.getSizeInBits();
15915 Op = Op.getOperand(0);
15916 if (VT == MVT::i8) {
15917 // Zero extend to i32 since there is not an i8 bsr.
15919 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15922 // Issue a bsr (scan bits in reverse).
15923 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15924 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15926 // And xor with NumBits-1.
15927 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
15928 DAG.getConstant(NumBits - 1, dl, OpVT));
15931 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15935 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15936 MVT VT = Op.getSimpleValueType();
15937 unsigned NumBits = VT.getSizeInBits();
15939 Op = Op.getOperand(0);
15941 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15942 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15943 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15945 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15948 DAG.getConstant(NumBits, dl, VT),
15949 DAG.getConstant(X86::COND_E, dl, MVT::i8),
15952 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15955 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15956 // ones, and then concatenate the result back.
15957 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15958 MVT VT = Op.getSimpleValueType();
15960 assert(VT.is256BitVector() && VT.isInteger() &&
15961 "Unsupported value type for operation");
15963 unsigned NumElems = VT.getVectorNumElements();
15966 // Extract the LHS vectors
15967 SDValue LHS = Op.getOperand(0);
15968 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15969 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15971 // Extract the RHS vectors
15972 SDValue RHS = Op.getOperand(1);
15973 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15974 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15976 MVT EltVT = VT.getVectorElementType();
15977 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15979 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15980 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15981 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15984 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15985 assert(Op.getSimpleValueType().is256BitVector() &&
15986 Op.getSimpleValueType().isInteger() &&
15987 "Only handle AVX 256-bit vector integer operation");
15988 return Lower256IntArith(Op, DAG);
15991 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15992 assert(Op.getSimpleValueType().is256BitVector() &&
15993 Op.getSimpleValueType().isInteger() &&
15994 "Only handle AVX 256-bit vector integer operation");
15995 return Lower256IntArith(Op, DAG);
15998 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15999 SelectionDAG &DAG) {
16001 MVT VT = Op.getSimpleValueType();
16003 // Decompose 256-bit ops into smaller 128-bit ops.
16004 if (VT.is256BitVector() && !Subtarget->hasInt256())
16005 return Lower256IntArith(Op, DAG);
16007 SDValue A = Op.getOperand(0);
16008 SDValue B = Op.getOperand(1);
16010 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16011 // pairs, multiply and truncate.
16012 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16013 if (Subtarget->hasInt256()) {
16014 if (VT == MVT::v32i8) {
16015 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16016 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16017 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16018 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16019 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16020 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16021 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16022 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16023 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16024 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16027 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16028 return DAG.getNode(
16029 ISD::TRUNCATE, dl, VT,
16030 DAG.getNode(ISD::MUL, dl, ExVT,
16031 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16032 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16035 assert(VT == MVT::v16i8 &&
16036 "Pre-AVX2 support only supports v16i8 multiplication");
16037 MVT ExVT = MVT::v8i16;
16039 // Extract the lo parts and sign extend to i16
16041 if (Subtarget->hasSSE41()) {
16042 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16043 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16045 const int ShufMask[] = {0, -1, 1, -1, 2, -1, 3, -1,
16046 4, -1, 5, -1, 6, -1, 7, -1};
16047 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16048 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16049 ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);
16050 BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);
16051 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16052 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16055 // Extract the hi parts and sign extend to i16
16057 if (Subtarget->hasSSE41()) {
16058 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16059 -1, -1, -1, -1, -1, -1, -1, -1};
16060 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16061 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16062 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16063 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16065 const int ShufMask[] = {8, -1, 9, -1, 10, -1, 11, -1,
16066 12, -1, 13, -1, 14, -1, 15, -1};
16067 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16068 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16069 AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);
16070 BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);
16071 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16072 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16075 // Multiply, mask the lower 8bits of the lo/hi results and pack
16076 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16077 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16078 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16079 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16080 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16083 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16084 if (VT == MVT::v4i32) {
16085 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16086 "Should not custom lower when pmuldq is available!");
16088 // Extract the odd parts.
16089 static const int UnpackMask[] = { 1, -1, 3, -1 };
16090 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16091 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16093 // Multiply the even parts.
16094 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16095 // Now multiply odd parts.
16096 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16098 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
16099 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
16101 // Merge the two vectors back together with a shuffle. This expands into 2
16103 static const int ShufMask[] = { 0, 4, 2, 6 };
16104 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16107 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16108 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16110 // Ahi = psrlqi(a, 32);
16111 // Bhi = psrlqi(b, 32);
16113 // AloBlo = pmuludq(a, b);
16114 // AloBhi = pmuludq(a, Bhi);
16115 // AhiBlo = pmuludq(Ahi, b);
16117 // AloBhi = psllqi(AloBhi, 32);
16118 // AhiBlo = psllqi(AhiBlo, 32);
16119 // return AloBlo + AloBhi + AhiBlo;
16121 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16122 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16124 // Bit cast to 32-bit vectors for MULUDQ
16125 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16126 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16127 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
16128 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
16129 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
16130 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
16132 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16133 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16134 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16136 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16137 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16139 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16140 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16143 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16144 assert(Subtarget->isTargetWin64() && "Unexpected target");
16145 EVT VT = Op.getValueType();
16146 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16147 "Unexpected return type for lowering");
16151 switch (Op->getOpcode()) {
16152 default: llvm_unreachable("Unexpected request for libcall!");
16153 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16154 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16155 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16156 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16157 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16158 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16162 SDValue InChain = DAG.getEntryNode();
16164 TargetLowering::ArgListTy Args;
16165 TargetLowering::ArgListEntry Entry;
16166 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16167 EVT ArgVT = Op->getOperand(i).getValueType();
16168 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16169 "Unexpected argument type for lowering");
16170 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16171 Entry.Node = StackPtr;
16172 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16174 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16175 Entry.Ty = PointerType::get(ArgTy,0);
16176 Entry.isSExt = false;
16177 Entry.isZExt = false;
16178 Args.push_back(Entry);
16181 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16184 TargetLowering::CallLoweringInfo CLI(DAG);
16185 CLI.setDebugLoc(dl).setChain(InChain)
16186 .setCallee(getLibcallCallingConv(LC),
16187 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16188 Callee, std::move(Args), 0)
16189 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16191 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16192 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16195 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16196 SelectionDAG &DAG) {
16197 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16198 EVT VT = Op0.getValueType();
16201 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16202 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16204 // PMULxD operations multiply each even value (starting at 0) of LHS with
16205 // the related value of RHS and produce a widen result.
16206 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16207 // => <2 x i64> <ae|cg>
16209 // In other word, to have all the results, we need to perform two PMULxD:
16210 // 1. one with the even values.
16211 // 2. one with the odd values.
16212 // To achieve #2, with need to place the odd values at an even position.
16214 // Place the odd value at an even position (basically, shift all values 1
16215 // step to the left):
16216 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16217 // <a|b|c|d> => <b|undef|d|undef>
16218 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16219 // <e|f|g|h> => <f|undef|h|undef>
16220 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16222 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16224 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16225 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16227 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16228 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16229 // => <2 x i64> <ae|cg>
16230 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16231 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16232 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16233 // => <2 x i64> <bf|dh>
16234 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16235 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16237 // Shuffle it back into the right order.
16238 SDValue Highs, Lows;
16239 if (VT == MVT::v8i32) {
16240 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16241 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16242 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16243 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16245 const int HighMask[] = {1, 5, 3, 7};
16246 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16247 const int LowMask[] = {0, 4, 2, 6};
16248 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16251 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16252 // unsigned multiply.
16253 if (IsSigned && !Subtarget->hasSSE41()) {
16255 DAG.getConstant(31, dl,
16256 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16257 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16258 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16259 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16260 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16262 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16263 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16266 // The first result of MUL_LOHI is actually the low value, followed by the
16268 SDValue Ops[] = {Lows, Highs};
16269 return DAG.getMergeValues(Ops, dl);
16272 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16273 const X86Subtarget *Subtarget) {
16274 MVT VT = Op.getSimpleValueType();
16276 SDValue R = Op.getOperand(0);
16277 SDValue Amt = Op.getOperand(1);
16279 // Optimize shl/srl/sra with constant shift amount.
16280 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16281 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16282 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16284 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16285 (Subtarget->hasInt256() &&
16286 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16287 (Subtarget->hasAVX512() &&
16288 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16289 if (Op.getOpcode() == ISD::SHL)
16290 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16292 if (Op.getOpcode() == ISD::SRL)
16293 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16295 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16296 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16300 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16301 unsigned NumElts = VT.getVectorNumElements();
16302 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16304 if (Op.getOpcode() == ISD::SHL) {
16305 // Make a large shift.
16306 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16308 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16309 // Zero out the rightmost bits.
16310 SmallVector<SDValue, 32> V(
16311 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16312 return DAG.getNode(ISD::AND, dl, VT, SHL,
16313 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16315 if (Op.getOpcode() == ISD::SRL) {
16316 // Make a large shift.
16317 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16319 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16320 // Zero out the leftmost bits.
16321 SmallVector<SDValue, 32> V(
16322 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16323 return DAG.getNode(ISD::AND, dl, VT, SRL,
16324 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16326 if (Op.getOpcode() == ISD::SRA) {
16327 if (ShiftAmt == 7) {
16328 // R s>> 7 === R s< 0
16329 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16330 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16333 // R s>> a === ((R u>> a) ^ m) - m
16334 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16335 SmallVector<SDValue, 32> V(NumElts,
16336 DAG.getConstant(128 >> ShiftAmt, dl,
16338 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16339 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16340 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16343 llvm_unreachable("Unknown shift opcode.");
16348 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16349 if (!Subtarget->is64Bit() &&
16350 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16351 Amt.getOpcode() == ISD::BITCAST &&
16352 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16353 Amt = Amt.getOperand(0);
16354 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16355 VT.getVectorNumElements();
16356 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16357 uint64_t ShiftAmt = 0;
16358 for (unsigned i = 0; i != Ratio; ++i) {
16359 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16363 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16365 // Check remaining shift amounts.
16366 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16367 uint64_t ShAmt = 0;
16368 for (unsigned j = 0; j != Ratio; ++j) {
16369 ConstantSDNode *C =
16370 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16374 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16376 if (ShAmt != ShiftAmt)
16379 switch (Op.getOpcode()) {
16381 llvm_unreachable("Unknown shift opcode!");
16383 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16386 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16389 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16397 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16398 const X86Subtarget* Subtarget) {
16399 MVT VT = Op.getSimpleValueType();
16401 SDValue R = Op.getOperand(0);
16402 SDValue Amt = Op.getOperand(1);
16404 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16405 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16406 (Subtarget->hasInt256() &&
16407 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16408 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16409 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16411 EVT EltVT = VT.getVectorElementType();
16413 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16414 // Check if this build_vector node is doing a splat.
16415 // If so, then set BaseShAmt equal to the splat value.
16416 BaseShAmt = BV->getSplatValue();
16417 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16418 BaseShAmt = SDValue();
16420 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16421 Amt = Amt.getOperand(0);
16423 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16424 if (SVN && SVN->isSplat()) {
16425 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16426 SDValue InVec = Amt.getOperand(0);
16427 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16428 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16429 "Unexpected shuffle index found!");
16430 BaseShAmt = InVec.getOperand(SplatIdx);
16431 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16432 if (ConstantSDNode *C =
16433 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16434 if (C->getZExtValue() == SplatIdx)
16435 BaseShAmt = InVec.getOperand(1);
16440 // Avoid introducing an extract element from a shuffle.
16441 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16442 DAG.getIntPtrConstant(SplatIdx, dl));
16446 if (BaseShAmt.getNode()) {
16447 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16448 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16449 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16450 else if (EltVT.bitsLT(MVT::i32))
16451 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16453 switch (Op.getOpcode()) {
16455 llvm_unreachable("Unknown shift opcode!");
16457 switch (VT.SimpleTy) {
16458 default: return SDValue();
16467 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16470 switch (VT.SimpleTy) {
16471 default: return SDValue();
16478 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16481 switch (VT.SimpleTy) {
16482 default: return SDValue();
16491 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16497 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16498 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16499 Amt.getOpcode() == ISD::BITCAST &&
16500 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16501 Amt = Amt.getOperand(0);
16502 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16503 VT.getVectorNumElements();
16504 std::vector<SDValue> Vals(Ratio);
16505 for (unsigned i = 0; i != Ratio; ++i)
16506 Vals[i] = Amt.getOperand(i);
16507 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16508 for (unsigned j = 0; j != Ratio; ++j)
16509 if (Vals[j] != Amt.getOperand(i + j))
16512 switch (Op.getOpcode()) {
16514 llvm_unreachable("Unknown shift opcode!");
16516 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16518 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16520 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16527 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16528 SelectionDAG &DAG) {
16529 MVT VT = Op.getSimpleValueType();
16531 SDValue R = Op.getOperand(0);
16532 SDValue Amt = Op.getOperand(1);
16534 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16535 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16537 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16540 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16543 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16546 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16547 if (Subtarget->hasInt256()) {
16548 if (Op.getOpcode() == ISD::SRL &&
16549 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16550 VT == MVT::v4i64 || VT == MVT::v8i32))
16552 if (Op.getOpcode() == ISD::SHL &&
16553 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16554 VT == MVT::v4i64 || VT == MVT::v8i32))
16556 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16560 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16561 // shifts per-lane and then shuffle the partial results back together.
16562 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16563 // Splat the shift amounts so the scalar shifts above will catch it.
16564 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16565 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16566 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16567 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16568 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16571 // If possible, lower this packed shift into a vector multiply instead of
16572 // expanding it into a sequence of scalar shifts.
16573 // Do this only if the vector shift count is a constant build_vector.
16574 if (Op.getOpcode() == ISD::SHL &&
16575 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16576 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16577 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16578 SmallVector<SDValue, 8> Elts;
16579 EVT SVT = VT.getScalarType();
16580 unsigned SVTBits = SVT.getSizeInBits();
16581 const APInt &One = APInt(SVTBits, 1);
16582 unsigned NumElems = VT.getVectorNumElements();
16584 for (unsigned i=0; i !=NumElems; ++i) {
16585 SDValue Op = Amt->getOperand(i);
16586 if (Op->getOpcode() == ISD::UNDEF) {
16587 Elts.push_back(Op);
16591 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16592 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16593 uint64_t ShAmt = C.getZExtValue();
16594 if (ShAmt >= SVTBits) {
16595 Elts.push_back(DAG.getUNDEF(SVT));
16598 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16600 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16601 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16604 // Lower SHL with variable shift amount.
16605 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16606 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16608 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16609 DAG.getConstant(0x3f800000U, dl, VT));
16610 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16611 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16612 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16615 // If possible, lower this shift as a sequence of two shifts by
16616 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16618 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16620 // Could be rewritten as:
16621 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16623 // The advantage is that the two shifts from the example would be
16624 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16625 // the vector shift into four scalar shifts plus four pairs of vector
16627 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16628 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16629 unsigned TargetOpcode = X86ISD::MOVSS;
16630 bool CanBeSimplified;
16631 // The splat value for the first packed shift (the 'X' from the example).
16632 SDValue Amt1 = Amt->getOperand(0);
16633 // The splat value for the second packed shift (the 'Y' from the example).
16634 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16635 Amt->getOperand(2);
16637 // See if it is possible to replace this node with a sequence of
16638 // two shifts followed by a MOVSS/MOVSD
16639 if (VT == MVT::v4i32) {
16640 // Check if it is legal to use a MOVSS.
16641 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16642 Amt2 == Amt->getOperand(3);
16643 if (!CanBeSimplified) {
16644 // Otherwise, check if we can still simplify this node using a MOVSD.
16645 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16646 Amt->getOperand(2) == Amt->getOperand(3);
16647 TargetOpcode = X86ISD::MOVSD;
16648 Amt2 = Amt->getOperand(2);
16651 // Do similar checks for the case where the machine value type
16653 CanBeSimplified = Amt1 == Amt->getOperand(1);
16654 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16655 CanBeSimplified = Amt2 == Amt->getOperand(i);
16657 if (!CanBeSimplified) {
16658 TargetOpcode = X86ISD::MOVSD;
16659 CanBeSimplified = true;
16660 Amt2 = Amt->getOperand(4);
16661 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16662 CanBeSimplified = Amt1 == Amt->getOperand(i);
16663 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16664 CanBeSimplified = Amt2 == Amt->getOperand(j);
16668 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16669 isa<ConstantSDNode>(Amt2)) {
16670 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16671 EVT CastVT = MVT::v4i32;
16673 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16674 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16676 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16677 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16678 if (TargetOpcode == X86ISD::MOVSD)
16679 CastVT = MVT::v2i64;
16680 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16681 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16682 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16684 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16688 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16689 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16692 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));
16693 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16695 // Turn 'a' into a mask suitable for VSELECT
16696 SDValue VSelM = DAG.getConstant(0x80, dl, VT);
16697 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16698 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16700 SDValue CM1 = DAG.getConstant(0x0f, dl, VT);
16701 SDValue CM2 = DAG.getConstant(0x3f, dl, VT);
16703 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16704 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16705 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16706 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16707 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16710 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16711 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16712 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16714 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16715 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16716 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16717 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16718 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16721 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16722 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16723 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16725 // return VSELECT(r, r+r, a);
16726 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16727 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16731 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16732 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16733 // solution better.
16734 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16735 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16737 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16738 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16739 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16740 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16741 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16744 // Decompose 256-bit shifts into smaller 128-bit shifts.
16745 if (VT.is256BitVector()) {
16746 unsigned NumElems = VT.getVectorNumElements();
16747 MVT EltVT = VT.getVectorElementType();
16748 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16750 // Extract the two vectors
16751 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16752 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16754 // Recreate the shift amount vectors
16755 SDValue Amt1, Amt2;
16756 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16757 // Constant shift amount
16758 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16759 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16760 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16762 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16763 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16765 // Variable shift amount
16766 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16767 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16770 // Issue new vector shifts for the smaller types
16771 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16772 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16774 // Concatenate the result back
16775 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16781 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16782 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16783 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16784 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16785 // has only one use.
16786 SDNode *N = Op.getNode();
16787 SDValue LHS = N->getOperand(0);
16788 SDValue RHS = N->getOperand(1);
16789 unsigned BaseOp = 0;
16792 switch (Op.getOpcode()) {
16793 default: llvm_unreachable("Unknown ovf instruction!");
16795 // A subtract of one will be selected as a INC. Note that INC doesn't
16796 // set CF, so we can't do this for UADDO.
16797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16799 BaseOp = X86ISD::INC;
16800 Cond = X86::COND_O;
16803 BaseOp = X86ISD::ADD;
16804 Cond = X86::COND_O;
16807 BaseOp = X86ISD::ADD;
16808 Cond = X86::COND_B;
16811 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16812 // set CF, so we can't do this for USUBO.
16813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16815 BaseOp = X86ISD::DEC;
16816 Cond = X86::COND_O;
16819 BaseOp = X86ISD::SUB;
16820 Cond = X86::COND_O;
16823 BaseOp = X86ISD::SUB;
16824 Cond = X86::COND_B;
16827 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16828 Cond = X86::COND_O;
16830 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16831 if (N->getValueType(0) == MVT::i8) {
16832 BaseOp = X86ISD::UMUL8;
16833 Cond = X86::COND_O;
16836 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16838 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16841 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16842 DAG.getConstant(X86::COND_O, DL, MVT::i32),
16843 SDValue(Sum.getNode(), 2));
16845 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16849 // Also sets EFLAGS.
16850 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16851 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16854 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16855 DAG.getConstant(Cond, DL, MVT::i32),
16856 SDValue(Sum.getNode(), 1));
16858 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16861 /// Returns true if the operand type is exactly twice the native width, and
16862 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16863 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16864 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16865 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16866 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16869 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16870 else if (OpWidth == 128)
16871 return Subtarget->hasCmpxchg16b();
16876 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16877 return needsCmpXchgNb(SI->getValueOperand()->getType());
16880 // Note: this turns large loads into lock cmpxchg8b/16b.
16881 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16882 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16883 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16884 return needsCmpXchgNb(PTy->getElementType());
16887 TargetLoweringBase::AtomicRMWExpansionKind
16888 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16889 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16890 const Type *MemType = AI->getType();
16892 // If the operand is too big, we must see if cmpxchg8/16b is available
16893 // and default to library calls otherwise.
16894 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
16895 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
16896 : AtomicRMWExpansionKind::None;
16899 AtomicRMWInst::BinOp Op = AI->getOperation();
16902 llvm_unreachable("Unknown atomic operation");
16903 case AtomicRMWInst::Xchg:
16904 case AtomicRMWInst::Add:
16905 case AtomicRMWInst::Sub:
16906 // It's better to use xadd, xsub or xchg for these in all cases.
16907 return AtomicRMWExpansionKind::None;
16908 case AtomicRMWInst::Or:
16909 case AtomicRMWInst::And:
16910 case AtomicRMWInst::Xor:
16911 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16912 // prefix to a normal instruction for these operations.
16913 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
16914 : AtomicRMWExpansionKind::None;
16915 case AtomicRMWInst::Nand:
16916 case AtomicRMWInst::Max:
16917 case AtomicRMWInst::Min:
16918 case AtomicRMWInst::UMax:
16919 case AtomicRMWInst::UMin:
16920 // These always require a non-trivial set of data operations on x86. We must
16921 // use a cmpxchg loop.
16922 return AtomicRMWExpansionKind::CmpXChg;
16926 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16927 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16928 // no-sse2). There isn't any reason to disable it if the target processor
16930 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16934 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16935 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16936 const Type *MemType = AI->getType();
16937 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16938 // there is no benefit in turning such RMWs into loads, and it is actually
16939 // harmful as it introduces a mfence.
16940 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16943 auto Builder = IRBuilder<>(AI);
16944 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16945 auto SynchScope = AI->getSynchScope();
16946 // We must restrict the ordering to avoid generating loads with Release or
16947 // ReleaseAcquire orderings.
16948 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16949 auto Ptr = AI->getPointerOperand();
16951 // Before the load we need a fence. Here is an example lifted from
16952 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16955 // x.store(1, relaxed);
16956 // r1 = y.fetch_add(0, release);
16958 // y.fetch_add(42, acquire);
16959 // r2 = x.load(relaxed);
16960 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16961 // lowered to just a load without a fence. A mfence flushes the store buffer,
16962 // making the optimization clearly correct.
16963 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16964 // otherwise, we might be able to be more agressive on relaxed idempotent
16965 // rmw. In practice, they do not look useful, so we don't try to be
16966 // especially clever.
16967 if (SynchScope == SingleThread) {
16968 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16969 // the IR level, so we must wrap it in an intrinsic.
16971 } else if (hasMFENCE(*Subtarget)) {
16972 Function *MFence = llvm::Intrinsic::getDeclaration(M,
16973 Intrinsic::x86_sse2_mfence);
16974 Builder.CreateCall(MFence);
16976 // FIXME: it might make sense to use a locked operation here but on a
16977 // different cache-line to prevent cache-line bouncing. In practice it
16978 // is probably a small win, and x86 processors without mfence are rare
16979 // enough that we do not bother.
16983 // Finally we can emit the atomic load.
16984 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
16985 AI->getType()->getPrimitiveSizeInBits());
16986 Loaded->setAtomic(Order, SynchScope);
16987 AI->replaceAllUsesWith(Loaded);
16988 AI->eraseFromParent();
16992 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16993 SelectionDAG &DAG) {
16995 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16996 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16997 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16998 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17000 // The only fence that needs an instruction is a sequentially-consistent
17001 // cross-thread fence.
17002 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17003 if (hasMFENCE(*Subtarget))
17004 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17006 SDValue Chain = Op.getOperand(0);
17007 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17009 DAG.getRegister(X86::ESP, MVT::i32), // Base
17010 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17011 DAG.getRegister(0, MVT::i32), // Index
17012 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17013 DAG.getRegister(0, MVT::i32), // Segment.
17017 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17018 return SDValue(Res, 0);
17021 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17022 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17025 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17026 SelectionDAG &DAG) {
17027 MVT T = Op.getSimpleValueType();
17031 switch(T.SimpleTy) {
17032 default: llvm_unreachable("Invalid value type!");
17033 case MVT::i8: Reg = X86::AL; size = 1; break;
17034 case MVT::i16: Reg = X86::AX; size = 2; break;
17035 case MVT::i32: Reg = X86::EAX; size = 4; break;
17037 assert(Subtarget->is64Bit() && "Node not type legal!");
17038 Reg = X86::RAX; size = 8;
17041 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17042 Op.getOperand(2), SDValue());
17043 SDValue Ops[] = { cpIn.getValue(0),
17046 DAG.getTargetConstant(size, DL, MVT::i8),
17047 cpIn.getValue(1) };
17048 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17049 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17050 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17054 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17055 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17056 MVT::i32, cpOut.getValue(2));
17057 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17058 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17061 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17062 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17063 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17067 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17068 SelectionDAG &DAG) {
17069 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17070 MVT DstVT = Op.getSimpleValueType();
17072 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17073 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17074 if (DstVT != MVT::f64)
17075 // This conversion needs to be expanded.
17078 SDValue InVec = Op->getOperand(0);
17080 unsigned NumElts = SrcVT.getVectorNumElements();
17081 EVT SVT = SrcVT.getVectorElementType();
17083 // Widen the vector in input in the case of MVT::v2i32.
17084 // Example: from MVT::v2i32 to MVT::v4i32.
17085 SmallVector<SDValue, 16> Elts;
17086 for (unsigned i = 0, e = NumElts; i != e; ++i)
17087 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17088 DAG.getIntPtrConstant(i, dl)));
17090 // Explicitly mark the extra elements as Undef.
17091 Elts.append(NumElts, DAG.getUNDEF(SVT));
17093 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17094 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17095 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
17096 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17097 DAG.getIntPtrConstant(0, dl));
17100 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17101 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17102 assert((DstVT == MVT::i64 ||
17103 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17104 "Unexpected custom BITCAST");
17105 // i64 <=> MMX conversions are Legal.
17106 if (SrcVT==MVT::i64 && DstVT.isVector())
17108 if (DstVT==MVT::i64 && SrcVT.isVector())
17110 // MMX <=> MMX conversions are Legal.
17111 if (SrcVT.isVector() && DstVT.isVector())
17113 // All other conversions need to be expanded.
17117 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17118 SelectionDAG &DAG) {
17119 SDNode *Node = Op.getNode();
17122 Op = Op.getOperand(0);
17123 EVT VT = Op.getValueType();
17124 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17125 "CTPOP lowering only implemented for 128/256-bit wide vector types");
17127 unsigned NumElts = VT.getVectorNumElements();
17128 EVT EltVT = VT.getVectorElementType();
17129 unsigned Len = EltVT.getSizeInBits();
17131 // This is the vectorized version of the "best" algorithm from
17132 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17133 // with a minor tweak to use a series of adds + shifts instead of vector
17134 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
17136 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
17137 // v8i32 => Always profitable
17139 // FIXME: There a couple of possible improvements:
17141 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
17142 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
17144 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
17145 "CTPOP not implemented for this vector element type.");
17147 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
17148 // extra legalization.
17149 bool NeedsBitcast = EltVT == MVT::i32;
17150 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
17152 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl,
17154 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl,
17156 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl,
17159 // v = v - ((v >> 1) & 0x55555555...)
17160 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, dl, EltVT));
17161 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
17162 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
17164 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17166 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
17167 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
17169 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
17171 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
17172 if (VT != And.getValueType())
17173 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17174 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
17176 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17177 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
17178 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
17179 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, dl, EltVT));
17180 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
17182 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
17183 if (NeedsBitcast) {
17184 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
17185 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
17186 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
17189 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
17190 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
17191 if (VT != AndRHS.getValueType()) {
17192 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
17193 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
17195 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
17197 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17198 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, dl, EltVT));
17199 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
17200 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
17201 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17203 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
17204 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
17205 if (NeedsBitcast) {
17206 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17207 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
17209 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
17210 if (VT != And.getValueType())
17211 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17213 // The algorithm mentioned above uses:
17214 // v = (v * 0x01010101...) >> (Len - 8)
17216 // Change it to use vector adds + vector shifts which yield faster results on
17217 // Haswell than using vector integer multiplication.
17219 // For i32 elements:
17220 // v = v + (v >> 8)
17221 // v = v + (v >> 16)
17223 // For i64 elements:
17224 // v = v + (v >> 8)
17225 // v = v + (v >> 16)
17226 // v = v + (v >> 32)
17229 SmallVector<SDValue, 8> Csts;
17230 for (unsigned i = 8; i <= Len/2; i *= 2) {
17231 Csts.assign(NumElts, DAG.getConstant(i, dl, EltVT));
17232 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
17233 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
17234 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17238 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
17239 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), dl,
17241 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
17242 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
17243 if (NeedsBitcast) {
17244 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17245 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
17247 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
17248 if (VT != And.getValueType())
17249 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17254 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17255 SDNode *Node = Op.getNode();
17257 EVT T = Node->getValueType(0);
17258 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17259 DAG.getConstant(0, dl, T), Node->getOperand(2));
17260 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17261 cast<AtomicSDNode>(Node)->getMemoryVT(),
17262 Node->getOperand(0),
17263 Node->getOperand(1), negOp,
17264 cast<AtomicSDNode>(Node)->getMemOperand(),
17265 cast<AtomicSDNode>(Node)->getOrdering(),
17266 cast<AtomicSDNode>(Node)->getSynchScope());
17269 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17270 SDNode *Node = Op.getNode();
17272 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17274 // Convert seq_cst store -> xchg
17275 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17276 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17277 // (The only way to get a 16-byte store is cmpxchg16b)
17278 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17279 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17280 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17281 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17282 cast<AtomicSDNode>(Node)->getMemoryVT(),
17283 Node->getOperand(0),
17284 Node->getOperand(1), Node->getOperand(2),
17285 cast<AtomicSDNode>(Node)->getMemOperand(),
17286 cast<AtomicSDNode>(Node)->getOrdering(),
17287 cast<AtomicSDNode>(Node)->getSynchScope());
17288 return Swap.getValue(1);
17290 // Other atomic stores have a simple pattern.
17294 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17295 EVT VT = Op.getNode()->getSimpleValueType(0);
17297 // Let legalize expand this if it isn't a legal type yet.
17298 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17301 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17304 bool ExtraOp = false;
17305 switch (Op.getOpcode()) {
17306 default: llvm_unreachable("Invalid code");
17307 case ISD::ADDC: Opc = X86ISD::ADD; break;
17308 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17309 case ISD::SUBC: Opc = X86ISD::SUB; break;
17310 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17314 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17316 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17317 Op.getOperand(1), Op.getOperand(2));
17320 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17321 SelectionDAG &DAG) {
17322 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17324 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17325 // which returns the values as { float, float } (in XMM0) or
17326 // { double, double } (which is returned in XMM0, XMM1).
17328 SDValue Arg = Op.getOperand(0);
17329 EVT ArgVT = Arg.getValueType();
17330 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17332 TargetLowering::ArgListTy Args;
17333 TargetLowering::ArgListEntry Entry;
17337 Entry.isSExt = false;
17338 Entry.isZExt = false;
17339 Args.push_back(Entry);
17341 bool isF64 = ArgVT == MVT::f64;
17342 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17343 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17344 // the results are returned via SRet in memory.
17345 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17346 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17347 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17349 Type *RetTy = isF64
17350 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17351 : (Type*)VectorType::get(ArgTy, 4);
17353 TargetLowering::CallLoweringInfo CLI(DAG);
17354 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17355 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17357 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17360 // Returned in xmm0 and xmm1.
17361 return CallResult.first;
17363 // Returned in bits 0:31 and 32:64 xmm0.
17364 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17365 CallResult.first, DAG.getIntPtrConstant(0, dl));
17366 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17367 CallResult.first, DAG.getIntPtrConstant(1, dl));
17368 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17369 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17372 /// LowerOperation - Provide custom lowering hooks for some operations.
17374 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17375 switch (Op.getOpcode()) {
17376 default: llvm_unreachable("Should not custom lower this!");
17377 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17378 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17379 return LowerCMP_SWAP(Op, Subtarget, DAG);
17380 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17381 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17382 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17383 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17384 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17385 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17386 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17387 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17388 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17389 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17390 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17391 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17392 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17393 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17394 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17395 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17396 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17397 case ISD::SHL_PARTS:
17398 case ISD::SRA_PARTS:
17399 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17400 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17401 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17402 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17403 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17404 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17405 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17406 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17407 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17408 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17409 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17411 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17412 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17413 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17414 case ISD::SETCC: return LowerSETCC(Op, DAG);
17415 case ISD::SELECT: return LowerSELECT(Op, DAG);
17416 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17417 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17418 case ISD::VASTART: return LowerVASTART(Op, DAG);
17419 case ISD::VAARG: return LowerVAARG(Op, DAG);
17420 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17421 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17422 case ISD::INTRINSIC_VOID:
17423 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17424 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17425 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17426 case ISD::FRAME_TO_ARGS_OFFSET:
17427 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17428 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17429 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17430 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17431 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17432 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17433 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17434 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17435 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17436 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17437 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17438 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17439 case ISD::UMUL_LOHI:
17440 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17443 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17449 case ISD::UMULO: return LowerXALUO(Op, DAG);
17450 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17451 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17455 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17456 case ISD::ADD: return LowerADD(Op, DAG);
17457 case ISD::SUB: return LowerSUB(Op, DAG);
17458 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17462 /// ReplaceNodeResults - Replace a node with an illegal result type
17463 /// with a new node built out of custom code.
17464 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17465 SmallVectorImpl<SDValue>&Results,
17466 SelectionDAG &DAG) const {
17468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17469 switch (N->getOpcode()) {
17471 llvm_unreachable("Do not know how to custom type legalize this operation!");
17472 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17473 case X86ISD::FMINC:
17475 case X86ISD::FMAXC:
17476 case X86ISD::FMAX: {
17477 EVT VT = N->getValueType(0);
17478 if (VT != MVT::v2f32)
17479 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17480 SDValue UNDEF = DAG.getUNDEF(VT);
17481 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17482 N->getOperand(0), UNDEF);
17483 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17484 N->getOperand(1), UNDEF);
17485 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17488 case ISD::SIGN_EXTEND_INREG:
17493 // We don't want to expand or promote these.
17500 case ISD::UDIVREM: {
17501 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17502 Results.push_back(V);
17505 case ISD::FP_TO_SINT:
17506 case ISD::FP_TO_UINT: {
17507 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17509 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17512 std::pair<SDValue,SDValue> Vals =
17513 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17514 SDValue FIST = Vals.first, StackSlot = Vals.second;
17515 if (FIST.getNode()) {
17516 EVT VT = N->getValueType(0);
17517 // Return a load from the stack slot.
17518 if (StackSlot.getNode())
17519 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17520 MachinePointerInfo(),
17521 false, false, false, 0));
17523 Results.push_back(FIST);
17527 case ISD::UINT_TO_FP: {
17528 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17529 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17530 N->getValueType(0) != MVT::v2f32)
17532 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17534 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
17536 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17537 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17538 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17539 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17540 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17541 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17544 case ISD::FP_ROUND: {
17545 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17547 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17548 Results.push_back(V);
17551 case ISD::INTRINSIC_W_CHAIN: {
17552 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17554 default : llvm_unreachable("Do not know how to custom type "
17555 "legalize this intrinsic operation!");
17556 case Intrinsic::x86_rdtsc:
17557 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17559 case Intrinsic::x86_rdtscp:
17560 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17562 case Intrinsic::x86_rdpmc:
17563 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17566 case ISD::READCYCLECOUNTER: {
17567 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17570 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17571 EVT T = N->getValueType(0);
17572 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17573 bool Regs64bit = T == MVT::i128;
17574 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17575 SDValue cpInL, cpInH;
17576 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17577 DAG.getConstant(0, dl, HalfT));
17578 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17579 DAG.getConstant(1, dl, HalfT));
17580 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17581 Regs64bit ? X86::RAX : X86::EAX,
17583 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17584 Regs64bit ? X86::RDX : X86::EDX,
17585 cpInH, cpInL.getValue(1));
17586 SDValue swapInL, swapInH;
17587 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17588 DAG.getConstant(0, dl, HalfT));
17589 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17590 DAG.getConstant(1, dl, HalfT));
17591 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17592 Regs64bit ? X86::RBX : X86::EBX,
17593 swapInL, cpInH.getValue(1));
17594 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17595 Regs64bit ? X86::RCX : X86::ECX,
17596 swapInH, swapInL.getValue(1));
17597 SDValue Ops[] = { swapInH.getValue(0),
17599 swapInH.getValue(1) };
17600 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17601 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17602 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17603 X86ISD::LCMPXCHG8_DAG;
17604 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17605 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17606 Regs64bit ? X86::RAX : X86::EAX,
17607 HalfT, Result.getValue(1));
17608 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17609 Regs64bit ? X86::RDX : X86::EDX,
17610 HalfT, cpOutL.getValue(2));
17611 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17613 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17614 MVT::i32, cpOutH.getValue(2));
17616 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17617 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
17618 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17620 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17621 Results.push_back(Success);
17622 Results.push_back(EFLAGS.getValue(1));
17625 case ISD::ATOMIC_SWAP:
17626 case ISD::ATOMIC_LOAD_ADD:
17627 case ISD::ATOMIC_LOAD_SUB:
17628 case ISD::ATOMIC_LOAD_AND:
17629 case ISD::ATOMIC_LOAD_OR:
17630 case ISD::ATOMIC_LOAD_XOR:
17631 case ISD::ATOMIC_LOAD_NAND:
17632 case ISD::ATOMIC_LOAD_MIN:
17633 case ISD::ATOMIC_LOAD_MAX:
17634 case ISD::ATOMIC_LOAD_UMIN:
17635 case ISD::ATOMIC_LOAD_UMAX:
17636 case ISD::ATOMIC_LOAD: {
17637 // Delegate to generic TypeLegalization. Situations we can really handle
17638 // should have already been dealt with by AtomicExpandPass.cpp.
17641 case ISD::BITCAST: {
17642 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17643 EVT DstVT = N->getValueType(0);
17644 EVT SrcVT = N->getOperand(0)->getValueType(0);
17646 if (SrcVT != MVT::f64 ||
17647 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17650 unsigned NumElts = DstVT.getVectorNumElements();
17651 EVT SVT = DstVT.getVectorElementType();
17652 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17653 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17654 MVT::v2f64, N->getOperand(0));
17655 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17657 if (ExperimentalVectorWideningLegalization) {
17658 // If we are legalizing vectors by widening, we already have the desired
17659 // legal vector type, just return it.
17660 Results.push_back(ToVecInt);
17664 SmallVector<SDValue, 8> Elts;
17665 for (unsigned i = 0, e = NumElts; i != e; ++i)
17666 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17667 ToVecInt, DAG.getIntPtrConstant(i, dl)));
17669 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17674 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17676 default: return nullptr;
17677 case X86ISD::BSF: return "X86ISD::BSF";
17678 case X86ISD::BSR: return "X86ISD::BSR";
17679 case X86ISD::SHLD: return "X86ISD::SHLD";
17680 case X86ISD::SHRD: return "X86ISD::SHRD";
17681 case X86ISD::FAND: return "X86ISD::FAND";
17682 case X86ISD::FANDN: return "X86ISD::FANDN";
17683 case X86ISD::FOR: return "X86ISD::FOR";
17684 case X86ISD::FXOR: return "X86ISD::FXOR";
17685 case X86ISD::FSRL: return "X86ISD::FSRL";
17686 case X86ISD::FILD: return "X86ISD::FILD";
17687 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17688 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17689 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17690 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17691 case X86ISD::FLD: return "X86ISD::FLD";
17692 case X86ISD::FST: return "X86ISD::FST";
17693 case X86ISD::CALL: return "X86ISD::CALL";
17694 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17695 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17696 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17697 case X86ISD::BT: return "X86ISD::BT";
17698 case X86ISD::CMP: return "X86ISD::CMP";
17699 case X86ISD::COMI: return "X86ISD::COMI";
17700 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17701 case X86ISD::CMPM: return "X86ISD::CMPM";
17702 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17703 case X86ISD::SETCC: return "X86ISD::SETCC";
17704 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17705 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17706 case X86ISD::CMOV: return "X86ISD::CMOV";
17707 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17708 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17709 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17710 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17711 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17712 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17713 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17714 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17715 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17716 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17717 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17718 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17719 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17720 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17721 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17722 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17723 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17724 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17725 case X86ISD::HADD: return "X86ISD::HADD";
17726 case X86ISD::HSUB: return "X86ISD::HSUB";
17727 case X86ISD::FHADD: return "X86ISD::FHADD";
17728 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17729 case X86ISD::UMAX: return "X86ISD::UMAX";
17730 case X86ISD::UMIN: return "X86ISD::UMIN";
17731 case X86ISD::SMAX: return "X86ISD::SMAX";
17732 case X86ISD::SMIN: return "X86ISD::SMIN";
17733 case X86ISD::FMAX: return "X86ISD::FMAX";
17734 case X86ISD::FMIN: return "X86ISD::FMIN";
17735 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17736 case X86ISD::FMINC: return "X86ISD::FMINC";
17737 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17738 case X86ISD::FRCP: return "X86ISD::FRCP";
17739 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17740 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17741 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17742 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17743 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17744 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17745 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17746 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17747 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17748 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17749 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17750 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17751 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17752 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17753 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17754 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17755 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17756 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17757 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17758 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17759 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17760 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17761 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17762 case X86ISD::VSHL: return "X86ISD::VSHL";
17763 case X86ISD::VSRL: return "X86ISD::VSRL";
17764 case X86ISD::VSRA: return "X86ISD::VSRA";
17765 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17766 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17767 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17768 case X86ISD::CMPP: return "X86ISD::CMPP";
17769 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17770 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17771 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17772 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17773 case X86ISD::ADD: return "X86ISD::ADD";
17774 case X86ISD::SUB: return "X86ISD::SUB";
17775 case X86ISD::ADC: return "X86ISD::ADC";
17776 case X86ISD::SBB: return "X86ISD::SBB";
17777 case X86ISD::SMUL: return "X86ISD::SMUL";
17778 case X86ISD::UMUL: return "X86ISD::UMUL";
17779 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17780 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17781 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17782 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17783 case X86ISD::INC: return "X86ISD::INC";
17784 case X86ISD::DEC: return "X86ISD::DEC";
17785 case X86ISD::OR: return "X86ISD::OR";
17786 case X86ISD::XOR: return "X86ISD::XOR";
17787 case X86ISD::AND: return "X86ISD::AND";
17788 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17789 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17790 case X86ISD::PTEST: return "X86ISD::PTEST";
17791 case X86ISD::TESTP: return "X86ISD::TESTP";
17792 case X86ISD::TESTM: return "X86ISD::TESTM";
17793 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17794 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17795 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17796 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17797 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17798 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17799 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17800 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17801 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17802 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17803 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17804 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17805 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17806 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17807 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17808 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17809 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17810 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17811 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17812 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17813 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17814 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17815 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17816 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17817 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17818 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17819 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17820 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17821 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17822 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17823 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17824 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17825 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17826 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17827 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17828 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17829 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17830 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17831 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17832 case X86ISD::SAHF: return "X86ISD::SAHF";
17833 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17834 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17835 case X86ISD::FMADD: return "X86ISD::FMADD";
17836 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17837 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17838 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17839 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17840 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17841 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17842 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17843 case X86ISD::XTEST: return "X86ISD::XTEST";
17844 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17845 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17846 case X86ISD::SELECT: return "X86ISD::SELECT";
17847 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17848 case X86ISD::RCP28: return "X86ISD::RCP28";
17849 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17850 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17851 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17852 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17853 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17857 // isLegalAddressingMode - Return true if the addressing mode represented
17858 // by AM is legal for this target, for a load/store of the specified type.
17859 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17861 // X86 supports extremely general addressing modes.
17862 CodeModel::Model M = getTargetMachine().getCodeModel();
17863 Reloc::Model R = getTargetMachine().getRelocationModel();
17865 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17866 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17871 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17873 // If a reference to this global requires an extra load, we can't fold it.
17874 if (isGlobalStubReference(GVFlags))
17877 // If BaseGV requires a register for the PIC base, we cannot also have a
17878 // BaseReg specified.
17879 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17882 // If lower 4G is not available, then we must use rip-relative addressing.
17883 if ((M != CodeModel::Small || R != Reloc::Static) &&
17884 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17888 switch (AM.Scale) {
17894 // These scales always work.
17899 // These scales are formed with basereg+scalereg. Only accept if there is
17904 default: // Other stuff never works.
17911 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17912 unsigned Bits = Ty->getScalarSizeInBits();
17914 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17915 // particularly cheaper than those without.
17919 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17920 // variable shifts just as cheap as scalar ones.
17921 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17924 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17925 // fully general vector.
17929 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17930 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17932 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17933 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17934 return NumBits1 > NumBits2;
17937 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17938 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17941 if (!isTypeLegal(EVT::getEVT(Ty1)))
17944 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17946 // Assuming the caller doesn't have a zeroext or signext return parameter,
17947 // truncation all the way down to i1 is valid.
17951 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17952 return isInt<32>(Imm);
17955 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17956 // Can also use sub to handle negated immediates.
17957 return isInt<32>(Imm);
17960 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17961 if (!VT1.isInteger() || !VT2.isInteger())
17963 unsigned NumBits1 = VT1.getSizeInBits();
17964 unsigned NumBits2 = VT2.getSizeInBits();
17965 return NumBits1 > NumBits2;
17968 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17969 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17970 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17973 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17974 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17975 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17978 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17979 EVT VT1 = Val.getValueType();
17980 if (isZExtFree(VT1, VT2))
17983 if (Val.getOpcode() != ISD::LOAD)
17986 if (!VT1.isSimple() || !VT1.isInteger() ||
17987 !VT2.isSimple() || !VT2.isInteger())
17990 switch (VT1.getSimpleVT().SimpleTy) {
17995 // X86 has 8, 16, and 32-bit zero-extending loads.
18002 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18005 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18006 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
18009 VT = VT.getScalarType();
18011 if (!VT.isSimple())
18014 switch (VT.getSimpleVT().SimpleTy) {
18025 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18026 // i16 instructions are longer (0x66 prefix) and potentially slower.
18027 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18030 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18031 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18032 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18033 /// are assumed to be legal.
18035 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18037 if (!VT.isSimple())
18040 // Very little shuffling can be done for 64-bit vectors right now.
18041 if (VT.getSizeInBits() == 64)
18044 // We only care that the types being shuffled are legal. The lowering can
18045 // handle any possible shuffle mask that results.
18046 return isTypeLegal(VT.getSimpleVT());
18050 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18052 // Just delegate to the generic legality, clear masks aren't special.
18053 return isShuffleMaskLegal(Mask, VT);
18056 //===----------------------------------------------------------------------===//
18057 // X86 Scheduler Hooks
18058 //===----------------------------------------------------------------------===//
18060 /// Utility function to emit xbegin specifying the start of an RTM region.
18061 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18062 const TargetInstrInfo *TII) {
18063 DebugLoc DL = MI->getDebugLoc();
18065 const BasicBlock *BB = MBB->getBasicBlock();
18066 MachineFunction::iterator I = MBB;
18069 // For the v = xbegin(), we generate
18080 MachineBasicBlock *thisMBB = MBB;
18081 MachineFunction *MF = MBB->getParent();
18082 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18083 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18084 MF->insert(I, mainMBB);
18085 MF->insert(I, sinkMBB);
18087 // Transfer the remainder of BB and its successor edges to sinkMBB.
18088 sinkMBB->splice(sinkMBB->begin(), MBB,
18089 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18090 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18094 // # fallthrough to mainMBB
18095 // # abortion to sinkMBB
18096 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18097 thisMBB->addSuccessor(mainMBB);
18098 thisMBB->addSuccessor(sinkMBB);
18102 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18103 mainMBB->addSuccessor(sinkMBB);
18106 // EAX is live into the sinkMBB
18107 sinkMBB->addLiveIn(X86::EAX);
18108 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18109 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18112 MI->eraseFromParent();
18116 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18117 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18118 // in the .td file.
18119 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18120 const TargetInstrInfo *TII) {
18122 switch (MI->getOpcode()) {
18123 default: llvm_unreachable("illegal opcode!");
18124 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18125 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18126 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18127 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18128 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18129 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18130 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18131 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18134 DebugLoc dl = MI->getDebugLoc();
18135 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18137 unsigned NumArgs = MI->getNumOperands();
18138 for (unsigned i = 1; i < NumArgs; ++i) {
18139 MachineOperand &Op = MI->getOperand(i);
18140 if (!(Op.isReg() && Op.isImplicit()))
18141 MIB.addOperand(Op);
18143 if (MI->hasOneMemOperand())
18144 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18146 BuildMI(*BB, MI, dl,
18147 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18148 .addReg(X86::XMM0);
18150 MI->eraseFromParent();
18154 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18155 // defs in an instruction pattern
18156 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18157 const TargetInstrInfo *TII) {
18159 switch (MI->getOpcode()) {
18160 default: llvm_unreachable("illegal opcode!");
18161 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18162 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18163 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18164 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18165 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18166 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18167 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18168 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18171 DebugLoc dl = MI->getDebugLoc();
18172 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18174 unsigned NumArgs = MI->getNumOperands(); // remove the results
18175 for (unsigned i = 1; i < NumArgs; ++i) {
18176 MachineOperand &Op = MI->getOperand(i);
18177 if (!(Op.isReg() && Op.isImplicit()))
18178 MIB.addOperand(Op);
18180 if (MI->hasOneMemOperand())
18181 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18183 BuildMI(*BB, MI, dl,
18184 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18187 MI->eraseFromParent();
18191 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18192 const X86Subtarget *Subtarget) {
18193 DebugLoc dl = MI->getDebugLoc();
18194 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18195 // Address into RAX/EAX, other two args into ECX, EDX.
18196 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18197 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18198 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18199 for (int i = 0; i < X86::AddrNumOperands; ++i)
18200 MIB.addOperand(MI->getOperand(i));
18202 unsigned ValOps = X86::AddrNumOperands;
18203 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18204 .addReg(MI->getOperand(ValOps).getReg());
18205 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18206 .addReg(MI->getOperand(ValOps+1).getReg());
18208 // The instruction doesn't actually take any operands though.
18209 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18211 MI->eraseFromParent(); // The pseudo is gone now.
18215 MachineBasicBlock *
18216 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18217 MachineBasicBlock *MBB) const {
18218 // Emit va_arg instruction on X86-64.
18220 // Operands to this pseudo-instruction:
18221 // 0 ) Output : destination address (reg)
18222 // 1-5) Input : va_list address (addr, i64mem)
18223 // 6 ) ArgSize : Size (in bytes) of vararg type
18224 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18225 // 8 ) Align : Alignment of type
18226 // 9 ) EFLAGS (implicit-def)
18228 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18229 static_assert(X86::AddrNumOperands == 5,
18230 "VAARG_64 assumes 5 address operands");
18232 unsigned DestReg = MI->getOperand(0).getReg();
18233 MachineOperand &Base = MI->getOperand(1);
18234 MachineOperand &Scale = MI->getOperand(2);
18235 MachineOperand &Index = MI->getOperand(3);
18236 MachineOperand &Disp = MI->getOperand(4);
18237 MachineOperand &Segment = MI->getOperand(5);
18238 unsigned ArgSize = MI->getOperand(6).getImm();
18239 unsigned ArgMode = MI->getOperand(7).getImm();
18240 unsigned Align = MI->getOperand(8).getImm();
18242 // Memory Reference
18243 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18244 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18245 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18247 // Machine Information
18248 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18249 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18250 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18251 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18252 DebugLoc DL = MI->getDebugLoc();
18254 // struct va_list {
18257 // i64 overflow_area (address)
18258 // i64 reg_save_area (address)
18260 // sizeof(va_list) = 24
18261 // alignment(va_list) = 8
18263 unsigned TotalNumIntRegs = 6;
18264 unsigned TotalNumXMMRegs = 8;
18265 bool UseGPOffset = (ArgMode == 1);
18266 bool UseFPOffset = (ArgMode == 2);
18267 unsigned MaxOffset = TotalNumIntRegs * 8 +
18268 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18270 /* Align ArgSize to a multiple of 8 */
18271 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18272 bool NeedsAlign = (Align > 8);
18274 MachineBasicBlock *thisMBB = MBB;
18275 MachineBasicBlock *overflowMBB;
18276 MachineBasicBlock *offsetMBB;
18277 MachineBasicBlock *endMBB;
18279 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18280 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18281 unsigned OffsetReg = 0;
18283 if (!UseGPOffset && !UseFPOffset) {
18284 // If we only pull from the overflow region, we don't create a branch.
18285 // We don't need to alter control flow.
18286 OffsetDestReg = 0; // unused
18287 OverflowDestReg = DestReg;
18289 offsetMBB = nullptr;
18290 overflowMBB = thisMBB;
18293 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18294 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18295 // If not, pull from overflow_area. (branch to overflowMBB)
18300 // offsetMBB overflowMBB
18305 // Registers for the PHI in endMBB
18306 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18307 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18309 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18310 MachineFunction *MF = MBB->getParent();
18311 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18312 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18313 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18315 MachineFunction::iterator MBBIter = MBB;
18318 // Insert the new basic blocks
18319 MF->insert(MBBIter, offsetMBB);
18320 MF->insert(MBBIter, overflowMBB);
18321 MF->insert(MBBIter, endMBB);
18323 // Transfer the remainder of MBB and its successor edges to endMBB.
18324 endMBB->splice(endMBB->begin(), thisMBB,
18325 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18326 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18328 // Make offsetMBB and overflowMBB successors of thisMBB
18329 thisMBB->addSuccessor(offsetMBB);
18330 thisMBB->addSuccessor(overflowMBB);
18332 // endMBB is a successor of both offsetMBB and overflowMBB
18333 offsetMBB->addSuccessor(endMBB);
18334 overflowMBB->addSuccessor(endMBB);
18336 // Load the offset value into a register
18337 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18338 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18342 .addDisp(Disp, UseFPOffset ? 4 : 0)
18343 .addOperand(Segment)
18344 .setMemRefs(MMOBegin, MMOEnd);
18346 // Check if there is enough room left to pull this argument.
18347 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18349 .addImm(MaxOffset + 8 - ArgSizeA8);
18351 // Branch to "overflowMBB" if offset >= max
18352 // Fall through to "offsetMBB" otherwise
18353 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18354 .addMBB(overflowMBB);
18357 // In offsetMBB, emit code to use the reg_save_area.
18359 assert(OffsetReg != 0);
18361 // Read the reg_save_area address.
18362 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18363 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18368 .addOperand(Segment)
18369 .setMemRefs(MMOBegin, MMOEnd);
18371 // Zero-extend the offset
18372 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18373 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18376 .addImm(X86::sub_32bit);
18378 // Add the offset to the reg_save_area to get the final address.
18379 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18380 .addReg(OffsetReg64)
18381 .addReg(RegSaveReg);
18383 // Compute the offset for the next argument
18384 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18385 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18387 .addImm(UseFPOffset ? 16 : 8);
18389 // Store it back into the va_list.
18390 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18394 .addDisp(Disp, UseFPOffset ? 4 : 0)
18395 .addOperand(Segment)
18396 .addReg(NextOffsetReg)
18397 .setMemRefs(MMOBegin, MMOEnd);
18400 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18405 // Emit code to use overflow area
18408 // Load the overflow_area address into a register.
18409 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18410 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18415 .addOperand(Segment)
18416 .setMemRefs(MMOBegin, MMOEnd);
18418 // If we need to align it, do so. Otherwise, just copy the address
18419 // to OverflowDestReg.
18421 // Align the overflow address
18422 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18423 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18425 // aligned_addr = (addr + (align-1)) & ~(align-1)
18426 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18427 .addReg(OverflowAddrReg)
18430 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18432 .addImm(~(uint64_t)(Align-1));
18434 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18435 .addReg(OverflowAddrReg);
18438 // Compute the next overflow address after this argument.
18439 // (the overflow address should be kept 8-byte aligned)
18440 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18441 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18442 .addReg(OverflowDestReg)
18443 .addImm(ArgSizeA8);
18445 // Store the new overflow address.
18446 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18451 .addOperand(Segment)
18452 .addReg(NextAddrReg)
18453 .setMemRefs(MMOBegin, MMOEnd);
18455 // If we branched, emit the PHI to the front of endMBB.
18457 BuildMI(*endMBB, endMBB->begin(), DL,
18458 TII->get(X86::PHI), DestReg)
18459 .addReg(OffsetDestReg).addMBB(offsetMBB)
18460 .addReg(OverflowDestReg).addMBB(overflowMBB);
18463 // Erase the pseudo instruction
18464 MI->eraseFromParent();
18469 MachineBasicBlock *
18470 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18472 MachineBasicBlock *MBB) const {
18473 // Emit code to save XMM registers to the stack. The ABI says that the
18474 // number of registers to save is given in %al, so it's theoretically
18475 // possible to do an indirect jump trick to avoid saving all of them,
18476 // however this code takes a simpler approach and just executes all
18477 // of the stores if %al is non-zero. It's less code, and it's probably
18478 // easier on the hardware branch predictor, and stores aren't all that
18479 // expensive anyway.
18481 // Create the new basic blocks. One block contains all the XMM stores,
18482 // and one block is the final destination regardless of whether any
18483 // stores were performed.
18484 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18485 MachineFunction *F = MBB->getParent();
18486 MachineFunction::iterator MBBIter = MBB;
18488 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18489 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18490 F->insert(MBBIter, XMMSaveMBB);
18491 F->insert(MBBIter, EndMBB);
18493 // Transfer the remainder of MBB and its successor edges to EndMBB.
18494 EndMBB->splice(EndMBB->begin(), MBB,
18495 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18496 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18498 // The original block will now fall through to the XMM save block.
18499 MBB->addSuccessor(XMMSaveMBB);
18500 // The XMMSaveMBB will fall through to the end block.
18501 XMMSaveMBB->addSuccessor(EndMBB);
18503 // Now add the instructions.
18504 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18505 DebugLoc DL = MI->getDebugLoc();
18507 unsigned CountReg = MI->getOperand(0).getReg();
18508 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18509 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18511 if (!Subtarget->isTargetWin64()) {
18512 // If %al is 0, branch around the XMM save block.
18513 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18514 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18515 MBB->addSuccessor(EndMBB);
18518 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18519 // that was just emitted, but clearly shouldn't be "saved".
18520 assert((MI->getNumOperands() <= 3 ||
18521 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18522 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18523 && "Expected last argument to be EFLAGS");
18524 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18525 // In the XMM save block, save all the XMM argument registers.
18526 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18527 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18528 MachineMemOperand *MMO =
18529 F->getMachineMemOperand(
18530 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18531 MachineMemOperand::MOStore,
18532 /*Size=*/16, /*Align=*/16);
18533 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18534 .addFrameIndex(RegSaveFrameIndex)
18535 .addImm(/*Scale=*/1)
18536 .addReg(/*IndexReg=*/0)
18537 .addImm(/*Disp=*/Offset)
18538 .addReg(/*Segment=*/0)
18539 .addReg(MI->getOperand(i).getReg())
18540 .addMemOperand(MMO);
18543 MI->eraseFromParent(); // The pseudo instruction is gone now.
18548 // The EFLAGS operand of SelectItr might be missing a kill marker
18549 // because there were multiple uses of EFLAGS, and ISel didn't know
18550 // which to mark. Figure out whether SelectItr should have had a
18551 // kill marker, and set it if it should. Returns the correct kill
18553 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18554 MachineBasicBlock* BB,
18555 const TargetRegisterInfo* TRI) {
18556 // Scan forward through BB for a use/def of EFLAGS.
18557 MachineBasicBlock::iterator miI(std::next(SelectItr));
18558 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18559 const MachineInstr& mi = *miI;
18560 if (mi.readsRegister(X86::EFLAGS))
18562 if (mi.definesRegister(X86::EFLAGS))
18563 break; // Should have kill-flag - update below.
18566 // If we hit the end of the block, check whether EFLAGS is live into a
18568 if (miI == BB->end()) {
18569 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18570 sEnd = BB->succ_end();
18571 sItr != sEnd; ++sItr) {
18572 MachineBasicBlock* succ = *sItr;
18573 if (succ->isLiveIn(X86::EFLAGS))
18578 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18579 // out. SelectMI should have a kill flag on EFLAGS.
18580 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18584 MachineBasicBlock *
18585 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18586 MachineBasicBlock *BB) const {
18587 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18588 DebugLoc DL = MI->getDebugLoc();
18590 // To "insert" a SELECT_CC instruction, we actually have to insert the
18591 // diamond control-flow pattern. The incoming instruction knows the
18592 // destination vreg to set, the condition code register to branch on, the
18593 // true/false values to select between, and a branch opcode to use.
18594 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18595 MachineFunction::iterator It = BB;
18601 // cmpTY ccX, r1, r2
18603 // fallthrough --> copy0MBB
18604 MachineBasicBlock *thisMBB = BB;
18605 MachineFunction *F = BB->getParent();
18607 // We also lower double CMOVs:
18608 // (CMOV (CMOV F, T, cc1), T, cc2)
18609 // to two successives branches. For that, we look for another CMOV as the
18610 // following instruction.
18612 // Without this, we would add a PHI between the two jumps, which ends up
18613 // creating a few copies all around. For instance, for
18615 // (sitofp (zext (fcmp une)))
18617 // we would generate:
18619 // ucomiss %xmm1, %xmm0
18620 // movss <1.0f>, %xmm0
18621 // movaps %xmm0, %xmm1
18623 // xorps %xmm1, %xmm1
18626 // movaps %xmm1, %xmm0
18630 // because this custom-inserter would have generated:
18642 // A: X = ...; Y = ...
18644 // C: Z = PHI [X, A], [Y, B]
18646 // E: PHI [X, C], [Z, D]
18648 // If we lower both CMOVs in a single step, we can instead generate:
18660 // A: X = ...; Y = ...
18662 // E: PHI [X, A], [X, C], [Y, D]
18664 // Which, in our sitofp/fcmp example, gives us something like:
18666 // ucomiss %xmm1, %xmm0
18667 // movss <1.0f>, %xmm0
18670 // xorps %xmm0, %xmm0
18674 MachineInstr *NextCMOV = nullptr;
18675 MachineBasicBlock::iterator NextMIIt =
18676 std::next(MachineBasicBlock::iterator(MI));
18677 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
18678 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
18679 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
18680 NextCMOV = &*NextMIIt;
18682 MachineBasicBlock *jcc1MBB = nullptr;
18684 // If we have a double CMOV, we lower it to two successive branches to
18685 // the same block. EFLAGS is used by both, so mark it as live in the second.
18687 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
18688 F->insert(It, jcc1MBB);
18689 jcc1MBB->addLiveIn(X86::EFLAGS);
18692 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18693 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18694 F->insert(It, copy0MBB);
18695 F->insert(It, sinkMBB);
18697 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18698 // live into the sink and copy blocks.
18699 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18701 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
18702 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
18703 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
18704 copy0MBB->addLiveIn(X86::EFLAGS);
18705 sinkMBB->addLiveIn(X86::EFLAGS);
18708 // Transfer the remainder of BB and its successor edges to sinkMBB.
18709 sinkMBB->splice(sinkMBB->begin(), BB,
18710 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18711 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18713 // Add the true and fallthrough blocks as its successors.
18715 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
18716 BB->addSuccessor(jcc1MBB);
18718 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
18719 // jump to the sinkMBB.
18720 jcc1MBB->addSuccessor(copy0MBB);
18721 jcc1MBB->addSuccessor(sinkMBB);
18723 BB->addSuccessor(copy0MBB);
18726 // The true block target of the first (or only) branch is always sinkMBB.
18727 BB->addSuccessor(sinkMBB);
18729 // Create the conditional branch instruction.
18731 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18732 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18735 unsigned Opc2 = X86::GetCondBranchFromCond(
18736 (X86::CondCode)NextCMOV->getOperand(3).getImm());
18737 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
18741 // %FalseValue = ...
18742 // # fallthrough to sinkMBB
18743 copy0MBB->addSuccessor(sinkMBB);
18746 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18748 MachineInstrBuilder MIB =
18749 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
18750 MI->getOperand(0).getReg())
18751 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18752 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18754 // If we have a double CMOV, the second Jcc provides the same incoming
18755 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
18757 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
18758 // Copy the PHI result to the register defined by the second CMOV.
18759 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
18760 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
18761 .addReg(MI->getOperand(0).getReg());
18762 NextCMOV->eraseFromParent();
18765 MI->eraseFromParent(); // The pseudo instruction is gone now.
18769 MachineBasicBlock *
18770 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18771 MachineBasicBlock *BB) const {
18772 MachineFunction *MF = BB->getParent();
18773 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18774 DebugLoc DL = MI->getDebugLoc();
18775 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18777 assert(MF->shouldSplitStack());
18779 const bool Is64Bit = Subtarget->is64Bit();
18780 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18782 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18783 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18786 // ... [Till the alloca]
18787 // If stacklet is not large enough, jump to mallocMBB
18790 // Allocate by subtracting from RSP
18791 // Jump to continueMBB
18794 // Allocate by call to runtime
18798 // [rest of original BB]
18801 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18802 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18803 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18805 MachineRegisterInfo &MRI = MF->getRegInfo();
18806 const TargetRegisterClass *AddrRegClass =
18807 getRegClassFor(getPointerTy());
18809 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18810 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18811 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18812 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18813 sizeVReg = MI->getOperand(1).getReg(),
18814 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18816 MachineFunction::iterator MBBIter = BB;
18819 MF->insert(MBBIter, bumpMBB);
18820 MF->insert(MBBIter, mallocMBB);
18821 MF->insert(MBBIter, continueMBB);
18823 continueMBB->splice(continueMBB->begin(), BB,
18824 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18825 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18827 // Add code to the main basic block to check if the stack limit has been hit,
18828 // and if so, jump to mallocMBB otherwise to bumpMBB.
18829 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18830 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18831 .addReg(tmpSPVReg).addReg(sizeVReg);
18832 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18833 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18834 .addReg(SPLimitVReg);
18835 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18837 // bumpMBB simply decreases the stack pointer, since we know the current
18838 // stacklet has enough space.
18839 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18840 .addReg(SPLimitVReg);
18841 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18842 .addReg(SPLimitVReg);
18843 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18845 // Calls into a routine in libgcc to allocate more space from the heap.
18846 const uint32_t *RegMask =
18847 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
18849 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18851 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18852 .addExternalSymbol("__morestack_allocate_stack_space")
18853 .addRegMask(RegMask)
18854 .addReg(X86::RDI, RegState::Implicit)
18855 .addReg(X86::RAX, RegState::ImplicitDefine);
18856 } else if (Is64Bit) {
18857 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
18859 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18860 .addExternalSymbol("__morestack_allocate_stack_space")
18861 .addRegMask(RegMask)
18862 .addReg(X86::EDI, RegState::Implicit)
18863 .addReg(X86::EAX, RegState::ImplicitDefine);
18865 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18867 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18868 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18869 .addExternalSymbol("__morestack_allocate_stack_space")
18870 .addRegMask(RegMask)
18871 .addReg(X86::EAX, RegState::ImplicitDefine);
18875 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18878 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18879 .addReg(IsLP64 ? X86::RAX : X86::EAX);
18880 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18882 // Set up the CFG correctly.
18883 BB->addSuccessor(bumpMBB);
18884 BB->addSuccessor(mallocMBB);
18885 mallocMBB->addSuccessor(continueMBB);
18886 bumpMBB->addSuccessor(continueMBB);
18888 // Take care of the PHI nodes.
18889 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18890 MI->getOperand(0).getReg())
18891 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18892 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18894 // Delete the original pseudo instruction.
18895 MI->eraseFromParent();
18898 return continueMBB;
18901 MachineBasicBlock *
18902 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18903 MachineBasicBlock *BB) const {
18904 DebugLoc DL = MI->getDebugLoc();
18906 assert(!Subtarget->isTargetMachO());
18908 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
18910 MI->eraseFromParent(); // The pseudo instruction is gone now.
18914 MachineBasicBlock *
18915 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18916 MachineBasicBlock *BB) const {
18917 // This is pretty easy. We're taking the value that we received from
18918 // our load from the relocation, sticking it in either RDI (x86-64)
18919 // or EAX and doing an indirect call. The return value will then
18920 // be in the normal return register.
18921 MachineFunction *F = BB->getParent();
18922 const X86InstrInfo *TII = Subtarget->getInstrInfo();
18923 DebugLoc DL = MI->getDebugLoc();
18925 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18926 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18928 // Get a register mask for the lowered call.
18929 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18930 // proper register mask.
18931 const uint32_t *RegMask =
18932 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
18933 if (Subtarget->is64Bit()) {
18934 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18935 TII->get(X86::MOV64rm), X86::RDI)
18937 .addImm(0).addReg(0)
18938 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18939 MI->getOperand(3).getTargetFlags())
18941 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18942 addDirectMem(MIB, X86::RDI);
18943 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18944 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18945 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18946 TII->get(X86::MOV32rm), X86::EAX)
18948 .addImm(0).addReg(0)
18949 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18950 MI->getOperand(3).getTargetFlags())
18952 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18953 addDirectMem(MIB, X86::EAX);
18954 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18956 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18957 TII->get(X86::MOV32rm), X86::EAX)
18958 .addReg(TII->getGlobalBaseReg(F))
18959 .addImm(0).addReg(0)
18960 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18961 MI->getOperand(3).getTargetFlags())
18963 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18964 addDirectMem(MIB, X86::EAX);
18965 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18968 MI->eraseFromParent(); // The pseudo instruction is gone now.
18972 MachineBasicBlock *
18973 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18974 MachineBasicBlock *MBB) const {
18975 DebugLoc DL = MI->getDebugLoc();
18976 MachineFunction *MF = MBB->getParent();
18977 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18978 MachineRegisterInfo &MRI = MF->getRegInfo();
18980 const BasicBlock *BB = MBB->getBasicBlock();
18981 MachineFunction::iterator I = MBB;
18984 // Memory Reference
18985 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18986 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18989 unsigned MemOpndSlot = 0;
18991 unsigned CurOp = 0;
18993 DstReg = MI->getOperand(CurOp++).getReg();
18994 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18995 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18996 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18997 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18999 MemOpndSlot = CurOp;
19001 MVT PVT = getPointerTy();
19002 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19003 "Invalid Pointer Size!");
19005 // For v = setjmp(buf), we generate
19008 // buf[LabelOffset] = restoreMBB
19009 // SjLjSetup restoreMBB
19015 // v = phi(main, restore)
19018 // if base pointer being used, load it from frame
19021 MachineBasicBlock *thisMBB = MBB;
19022 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19023 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19024 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19025 MF->insert(I, mainMBB);
19026 MF->insert(I, sinkMBB);
19027 MF->push_back(restoreMBB);
19029 MachineInstrBuilder MIB;
19031 // Transfer the remainder of BB and its successor edges to sinkMBB.
19032 sinkMBB->splice(sinkMBB->begin(), MBB,
19033 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19034 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19037 unsigned PtrStoreOpc = 0;
19038 unsigned LabelReg = 0;
19039 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19040 Reloc::Model RM = MF->getTarget().getRelocationModel();
19041 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19042 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19044 // Prepare IP either in reg or imm.
19045 if (!UseImmLabel) {
19046 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19047 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19048 LabelReg = MRI.createVirtualRegister(PtrRC);
19049 if (Subtarget->is64Bit()) {
19050 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19054 .addMBB(restoreMBB)
19057 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19058 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19059 .addReg(XII->getGlobalBaseReg(MF))
19062 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19066 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19068 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19069 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19070 if (i == X86::AddrDisp)
19071 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19073 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19076 MIB.addReg(LabelReg);
19078 MIB.addMBB(restoreMBB);
19079 MIB.setMemRefs(MMOBegin, MMOEnd);
19081 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19082 .addMBB(restoreMBB);
19084 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19085 MIB.addRegMask(RegInfo->getNoPreservedMask());
19086 thisMBB->addSuccessor(mainMBB);
19087 thisMBB->addSuccessor(restoreMBB);
19091 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19092 mainMBB->addSuccessor(sinkMBB);
19095 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19096 TII->get(X86::PHI), DstReg)
19097 .addReg(mainDstReg).addMBB(mainMBB)
19098 .addReg(restoreDstReg).addMBB(restoreMBB);
19101 if (RegInfo->hasBasePointer(*MF)) {
19102 const bool Uses64BitFramePtr =
19103 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19104 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19105 X86FI->setRestoreBasePointer(MF);
19106 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19107 unsigned BasePtr = RegInfo->getBaseRegister();
19108 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19109 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19110 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19111 .setMIFlag(MachineInstr::FrameSetup);
19113 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19114 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19115 restoreMBB->addSuccessor(sinkMBB);
19117 MI->eraseFromParent();
19121 MachineBasicBlock *
19122 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19123 MachineBasicBlock *MBB) const {
19124 DebugLoc DL = MI->getDebugLoc();
19125 MachineFunction *MF = MBB->getParent();
19126 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19127 MachineRegisterInfo &MRI = MF->getRegInfo();
19129 // Memory Reference
19130 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19131 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19133 MVT PVT = getPointerTy();
19134 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19135 "Invalid Pointer Size!");
19137 const TargetRegisterClass *RC =
19138 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19139 unsigned Tmp = MRI.createVirtualRegister(RC);
19140 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19141 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19142 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19143 unsigned SP = RegInfo->getStackRegister();
19145 MachineInstrBuilder MIB;
19147 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19148 const int64_t SPOffset = 2 * PVT.getStoreSize();
19150 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19151 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19154 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19155 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19156 MIB.addOperand(MI->getOperand(i));
19157 MIB.setMemRefs(MMOBegin, MMOEnd);
19159 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19160 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19161 if (i == X86::AddrDisp)
19162 MIB.addDisp(MI->getOperand(i), LabelOffset);
19164 MIB.addOperand(MI->getOperand(i));
19166 MIB.setMemRefs(MMOBegin, MMOEnd);
19168 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19169 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19170 if (i == X86::AddrDisp)
19171 MIB.addDisp(MI->getOperand(i), SPOffset);
19173 MIB.addOperand(MI->getOperand(i));
19175 MIB.setMemRefs(MMOBegin, MMOEnd);
19177 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19179 MI->eraseFromParent();
19183 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19184 // accumulator loops. Writing back to the accumulator allows the coalescer
19185 // to remove extra copies in the loop.
19186 MachineBasicBlock *
19187 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19188 MachineBasicBlock *MBB) const {
19189 MachineOperand &AddendOp = MI->getOperand(3);
19191 // Bail out early if the addend isn't a register - we can't switch these.
19192 if (!AddendOp.isReg())
19195 MachineFunction &MF = *MBB->getParent();
19196 MachineRegisterInfo &MRI = MF.getRegInfo();
19198 // Check whether the addend is defined by a PHI:
19199 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19200 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19201 if (!AddendDef.isPHI())
19204 // Look for the following pattern:
19206 // %addend = phi [%entry, 0], [%loop, %result]
19208 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19212 // %addend = phi [%entry, 0], [%loop, %result]
19214 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19216 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19217 assert(AddendDef.getOperand(i).isReg());
19218 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19219 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19220 if (&PHISrcInst == MI) {
19221 // Found a matching instruction.
19222 unsigned NewFMAOpc = 0;
19223 switch (MI->getOpcode()) {
19224 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19225 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19226 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19227 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19228 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19229 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19230 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19231 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19232 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19233 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19234 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19235 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19236 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19237 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19238 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19239 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19240 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19241 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19242 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19243 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19245 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19246 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19247 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19248 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19249 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19250 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19251 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19252 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19253 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19254 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19255 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19256 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19257 default: llvm_unreachable("Unrecognized FMA variant.");
19260 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19261 MachineInstrBuilder MIB =
19262 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19263 .addOperand(MI->getOperand(0))
19264 .addOperand(MI->getOperand(3))
19265 .addOperand(MI->getOperand(2))
19266 .addOperand(MI->getOperand(1));
19267 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19268 MI->eraseFromParent();
19275 MachineBasicBlock *
19276 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19277 MachineBasicBlock *BB) const {
19278 switch (MI->getOpcode()) {
19279 default: llvm_unreachable("Unexpected instr type to insert");
19280 case X86::TAILJMPd64:
19281 case X86::TAILJMPr64:
19282 case X86::TAILJMPm64:
19283 case X86::TAILJMPd64_REX:
19284 case X86::TAILJMPr64_REX:
19285 case X86::TAILJMPm64_REX:
19286 llvm_unreachable("TAILJMP64 would not be touched here.");
19287 case X86::TCRETURNdi64:
19288 case X86::TCRETURNri64:
19289 case X86::TCRETURNmi64:
19291 case X86::WIN_ALLOCA:
19292 return EmitLoweredWinAlloca(MI, BB);
19293 case X86::SEG_ALLOCA_32:
19294 case X86::SEG_ALLOCA_64:
19295 return EmitLoweredSegAlloca(MI, BB);
19296 case X86::TLSCall_32:
19297 case X86::TLSCall_64:
19298 return EmitLoweredTLSCall(MI, BB);
19299 case X86::CMOV_GR8:
19300 case X86::CMOV_FR32:
19301 case X86::CMOV_FR64:
19302 case X86::CMOV_V4F32:
19303 case X86::CMOV_V2F64:
19304 case X86::CMOV_V2I64:
19305 case X86::CMOV_V8F32:
19306 case X86::CMOV_V4F64:
19307 case X86::CMOV_V4I64:
19308 case X86::CMOV_V16F32:
19309 case X86::CMOV_V8F64:
19310 case X86::CMOV_V8I64:
19311 case X86::CMOV_GR16:
19312 case X86::CMOV_GR32:
19313 case X86::CMOV_RFP32:
19314 case X86::CMOV_RFP64:
19315 case X86::CMOV_RFP80:
19316 return EmitLoweredSelect(MI, BB);
19318 case X86::FP32_TO_INT16_IN_MEM:
19319 case X86::FP32_TO_INT32_IN_MEM:
19320 case X86::FP32_TO_INT64_IN_MEM:
19321 case X86::FP64_TO_INT16_IN_MEM:
19322 case X86::FP64_TO_INT32_IN_MEM:
19323 case X86::FP64_TO_INT64_IN_MEM:
19324 case X86::FP80_TO_INT16_IN_MEM:
19325 case X86::FP80_TO_INT32_IN_MEM:
19326 case X86::FP80_TO_INT64_IN_MEM: {
19327 MachineFunction *F = BB->getParent();
19328 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19329 DebugLoc DL = MI->getDebugLoc();
19331 // Change the floating point control register to use "round towards zero"
19332 // mode when truncating to an integer value.
19333 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19334 addFrameReference(BuildMI(*BB, MI, DL,
19335 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19337 // Load the old value of the high byte of the control word...
19339 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19340 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19343 // Set the high part to be round to zero...
19344 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19347 // Reload the modified control word now...
19348 addFrameReference(BuildMI(*BB, MI, DL,
19349 TII->get(X86::FLDCW16m)), CWFrameIdx);
19351 // Restore the memory image of control word to original value
19352 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19355 // Get the X86 opcode to use.
19357 switch (MI->getOpcode()) {
19358 default: llvm_unreachable("illegal opcode!");
19359 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19360 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19361 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19362 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19363 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19364 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19365 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19366 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19367 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19371 MachineOperand &Op = MI->getOperand(0);
19373 AM.BaseType = X86AddressMode::RegBase;
19374 AM.Base.Reg = Op.getReg();
19376 AM.BaseType = X86AddressMode::FrameIndexBase;
19377 AM.Base.FrameIndex = Op.getIndex();
19379 Op = MI->getOperand(1);
19381 AM.Scale = Op.getImm();
19382 Op = MI->getOperand(2);
19384 AM.IndexReg = Op.getImm();
19385 Op = MI->getOperand(3);
19386 if (Op.isGlobal()) {
19387 AM.GV = Op.getGlobal();
19389 AM.Disp = Op.getImm();
19391 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19392 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19394 // Reload the original control word now.
19395 addFrameReference(BuildMI(*BB, MI, DL,
19396 TII->get(X86::FLDCW16m)), CWFrameIdx);
19398 MI->eraseFromParent(); // The pseudo instruction is gone now.
19401 // String/text processing lowering.
19402 case X86::PCMPISTRM128REG:
19403 case X86::VPCMPISTRM128REG:
19404 case X86::PCMPISTRM128MEM:
19405 case X86::VPCMPISTRM128MEM:
19406 case X86::PCMPESTRM128REG:
19407 case X86::VPCMPESTRM128REG:
19408 case X86::PCMPESTRM128MEM:
19409 case X86::VPCMPESTRM128MEM:
19410 assert(Subtarget->hasSSE42() &&
19411 "Target must have SSE4.2 or AVX features enabled");
19412 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19414 // String/text processing lowering.
19415 case X86::PCMPISTRIREG:
19416 case X86::VPCMPISTRIREG:
19417 case X86::PCMPISTRIMEM:
19418 case X86::VPCMPISTRIMEM:
19419 case X86::PCMPESTRIREG:
19420 case X86::VPCMPESTRIREG:
19421 case X86::PCMPESTRIMEM:
19422 case X86::VPCMPESTRIMEM:
19423 assert(Subtarget->hasSSE42() &&
19424 "Target must have SSE4.2 or AVX features enabled");
19425 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19427 // Thread synchronization.
19429 return EmitMonitor(MI, BB, Subtarget);
19433 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19435 case X86::VASTART_SAVE_XMM_REGS:
19436 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19438 case X86::VAARG_64:
19439 return EmitVAARG64WithCustomInserter(MI, BB);
19441 case X86::EH_SjLj_SetJmp32:
19442 case X86::EH_SjLj_SetJmp64:
19443 return emitEHSjLjSetJmp(MI, BB);
19445 case X86::EH_SjLj_LongJmp32:
19446 case X86::EH_SjLj_LongJmp64:
19447 return emitEHSjLjLongJmp(MI, BB);
19449 case TargetOpcode::STATEPOINT:
19450 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19451 // this point in the process. We diverge later.
19452 return emitPatchPoint(MI, BB);
19454 case TargetOpcode::STACKMAP:
19455 case TargetOpcode::PATCHPOINT:
19456 return emitPatchPoint(MI, BB);
19458 case X86::VFMADDPDr213r:
19459 case X86::VFMADDPSr213r:
19460 case X86::VFMADDSDr213r:
19461 case X86::VFMADDSSr213r:
19462 case X86::VFMSUBPDr213r:
19463 case X86::VFMSUBPSr213r:
19464 case X86::VFMSUBSDr213r:
19465 case X86::VFMSUBSSr213r:
19466 case X86::VFNMADDPDr213r:
19467 case X86::VFNMADDPSr213r:
19468 case X86::VFNMADDSDr213r:
19469 case X86::VFNMADDSSr213r:
19470 case X86::VFNMSUBPDr213r:
19471 case X86::VFNMSUBPSr213r:
19472 case X86::VFNMSUBSDr213r:
19473 case X86::VFNMSUBSSr213r:
19474 case X86::VFMADDSUBPDr213r:
19475 case X86::VFMADDSUBPSr213r:
19476 case X86::VFMSUBADDPDr213r:
19477 case X86::VFMSUBADDPSr213r:
19478 case X86::VFMADDPDr213rY:
19479 case X86::VFMADDPSr213rY:
19480 case X86::VFMSUBPDr213rY:
19481 case X86::VFMSUBPSr213rY:
19482 case X86::VFNMADDPDr213rY:
19483 case X86::VFNMADDPSr213rY:
19484 case X86::VFNMSUBPDr213rY:
19485 case X86::VFNMSUBPSr213rY:
19486 case X86::VFMADDSUBPDr213rY:
19487 case X86::VFMADDSUBPSr213rY:
19488 case X86::VFMSUBADDPDr213rY:
19489 case X86::VFMSUBADDPSr213rY:
19490 return emitFMA3Instr(MI, BB);
19494 //===----------------------------------------------------------------------===//
19495 // X86 Optimization Hooks
19496 //===----------------------------------------------------------------------===//
19498 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19501 const SelectionDAG &DAG,
19502 unsigned Depth) const {
19503 unsigned BitWidth = KnownZero.getBitWidth();
19504 unsigned Opc = Op.getOpcode();
19505 assert((Opc >= ISD::BUILTIN_OP_END ||
19506 Opc == ISD::INTRINSIC_WO_CHAIN ||
19507 Opc == ISD::INTRINSIC_W_CHAIN ||
19508 Opc == ISD::INTRINSIC_VOID) &&
19509 "Should use MaskedValueIsZero if you don't know whether Op"
19510 " is a target node!");
19512 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19526 // These nodes' second result is a boolean.
19527 if (Op.getResNo() == 0)
19530 case X86ISD::SETCC:
19531 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19533 case ISD::INTRINSIC_WO_CHAIN: {
19534 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19535 unsigned NumLoBits = 0;
19538 case Intrinsic::x86_sse_movmsk_ps:
19539 case Intrinsic::x86_avx_movmsk_ps_256:
19540 case Intrinsic::x86_sse2_movmsk_pd:
19541 case Intrinsic::x86_avx_movmsk_pd_256:
19542 case Intrinsic::x86_mmx_pmovmskb:
19543 case Intrinsic::x86_sse2_pmovmskb_128:
19544 case Intrinsic::x86_avx2_pmovmskb: {
19545 // High bits of movmskp{s|d}, pmovmskb are known zero.
19547 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19548 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19549 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19550 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19551 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19552 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19553 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19554 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19556 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19565 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19567 const SelectionDAG &,
19568 unsigned Depth) const {
19569 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19570 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19571 return Op.getValueType().getScalarType().getSizeInBits();
19577 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19578 /// node is a GlobalAddress + offset.
19579 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19580 const GlobalValue* &GA,
19581 int64_t &Offset) const {
19582 if (N->getOpcode() == X86ISD::Wrapper) {
19583 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19584 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19585 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19589 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19592 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19593 /// same as extracting the high 128-bit part of 256-bit vector and then
19594 /// inserting the result into the low part of a new 256-bit vector
19595 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19596 EVT VT = SVOp->getValueType(0);
19597 unsigned NumElems = VT.getVectorNumElements();
19599 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19600 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19601 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19602 SVOp->getMaskElt(j) >= 0)
19608 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19609 /// same as extracting the low 128-bit part of 256-bit vector and then
19610 /// inserting the result into the high part of a new 256-bit vector
19611 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19612 EVT VT = SVOp->getValueType(0);
19613 unsigned NumElems = VT.getVectorNumElements();
19615 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19616 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19617 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19618 SVOp->getMaskElt(j) >= 0)
19624 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19625 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19626 TargetLowering::DAGCombinerInfo &DCI,
19627 const X86Subtarget* Subtarget) {
19629 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19630 SDValue V1 = SVOp->getOperand(0);
19631 SDValue V2 = SVOp->getOperand(1);
19632 EVT VT = SVOp->getValueType(0);
19633 unsigned NumElems = VT.getVectorNumElements();
19635 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19636 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19640 // V UNDEF BUILD_VECTOR UNDEF
19642 // CONCAT_VECTOR CONCAT_VECTOR
19645 // RESULT: V + zero extended
19647 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19648 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19649 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19652 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19655 // To match the shuffle mask, the first half of the mask should
19656 // be exactly the first vector, and all the rest a splat with the
19657 // first element of the second one.
19658 for (unsigned i = 0; i != NumElems/2; ++i)
19659 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19660 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19663 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19664 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19665 if (Ld->hasNUsesOfValue(1, 0)) {
19666 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19667 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19669 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19671 Ld->getPointerInfo(),
19672 Ld->getAlignment(),
19673 false/*isVolatile*/, true/*ReadMem*/,
19674 false/*WriteMem*/);
19676 // Make sure the newly-created LOAD is in the same position as Ld in
19677 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19678 // and update uses of Ld's output chain to use the TokenFactor.
19679 if (Ld->hasAnyUseOfValue(1)) {
19680 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19681 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19682 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19683 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19684 SDValue(ResNode.getNode(), 1));
19687 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19691 // Emit a zeroed vector and insert the desired subvector on its
19693 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19694 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19695 return DCI.CombineTo(N, InsV);
19698 //===--------------------------------------------------------------------===//
19699 // Combine some shuffles into subvector extracts and inserts:
19702 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19703 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19704 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19705 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19706 return DCI.CombineTo(N, InsV);
19709 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19710 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19711 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19712 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19713 return DCI.CombineTo(N, InsV);
19719 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19722 /// This is the leaf of the recursive combinine below. When we have found some
19723 /// chain of single-use x86 shuffle instructions and accumulated the combined
19724 /// shuffle mask represented by them, this will try to pattern match that mask
19725 /// into either a single instruction if there is a special purpose instruction
19726 /// for this operation, or into a PSHUFB instruction which is a fully general
19727 /// instruction but should only be used to replace chains over a certain depth.
19728 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19729 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19730 TargetLowering::DAGCombinerInfo &DCI,
19731 const X86Subtarget *Subtarget) {
19732 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19734 // Find the operand that enters the chain. Note that multiple uses are OK
19735 // here, we're not going to remove the operand we find.
19736 SDValue Input = Op.getOperand(0);
19737 while (Input.getOpcode() == ISD::BITCAST)
19738 Input = Input.getOperand(0);
19740 MVT VT = Input.getSimpleValueType();
19741 MVT RootVT = Root.getSimpleValueType();
19744 // Just remove no-op shuffle masks.
19745 if (Mask.size() == 1) {
19746 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19751 // Use the float domain if the operand type is a floating point type.
19752 bool FloatDomain = VT.isFloatingPoint();
19754 // For floating point shuffles, we don't have free copies in the shuffle
19755 // instructions or the ability to load as part of the instruction, so
19756 // canonicalize their shuffles to UNPCK or MOV variants.
19758 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19759 // vectors because it can have a load folded into it that UNPCK cannot. This
19760 // doesn't preclude something switching to the shorter encoding post-RA.
19762 // FIXME: Should teach these routines about AVX vector widths.
19763 if (FloatDomain && VT.getSizeInBits() == 128) {
19764 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
19765 bool Lo = Mask.equals({0, 0});
19768 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19769 // is no slower than UNPCKLPD but has the option to fold the input operand
19770 // into even an unaligned memory load.
19771 if (Lo && Subtarget->hasSSE3()) {
19772 Shuffle = X86ISD::MOVDDUP;
19773 ShuffleVT = MVT::v2f64;
19775 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19776 // than the UNPCK variants.
19777 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19778 ShuffleVT = MVT::v4f32;
19780 if (Depth == 1 && Root->getOpcode() == Shuffle)
19781 return false; // Nothing to do!
19782 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19783 DCI.AddToWorklist(Op.getNode());
19784 if (Shuffle == X86ISD::MOVDDUP)
19785 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19787 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19788 DCI.AddToWorklist(Op.getNode());
19789 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19793 if (Subtarget->hasSSE3() &&
19794 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
19795 bool Lo = Mask.equals({0, 0, 2, 2});
19796 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19797 MVT ShuffleVT = MVT::v4f32;
19798 if (Depth == 1 && Root->getOpcode() == Shuffle)
19799 return false; // Nothing to do!
19800 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19801 DCI.AddToWorklist(Op.getNode());
19802 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19803 DCI.AddToWorklist(Op.getNode());
19804 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19808 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
19809 bool Lo = Mask.equals({0, 0, 1, 1});
19810 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19811 MVT ShuffleVT = MVT::v4f32;
19812 if (Depth == 1 && Root->getOpcode() == Shuffle)
19813 return false; // Nothing to do!
19814 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19815 DCI.AddToWorklist(Op.getNode());
19816 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19817 DCI.AddToWorklist(Op.getNode());
19818 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19824 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19825 // variants as none of these have single-instruction variants that are
19826 // superior to the UNPCK formulation.
19827 if (!FloatDomain && VT.getSizeInBits() == 128 &&
19828 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
19829 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
19830 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
19832 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
19833 bool Lo = Mask[0] == 0;
19834 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19835 if (Depth == 1 && Root->getOpcode() == Shuffle)
19836 return false; // Nothing to do!
19838 switch (Mask.size()) {
19840 ShuffleVT = MVT::v8i16;
19843 ShuffleVT = MVT::v16i8;
19846 llvm_unreachable("Impossible mask size!");
19848 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19849 DCI.AddToWorklist(Op.getNode());
19850 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19851 DCI.AddToWorklist(Op.getNode());
19852 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19857 // Don't try to re-form single instruction chains under any circumstances now
19858 // that we've done encoding canonicalization for them.
19862 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19863 // can replace them with a single PSHUFB instruction profitably. Intel's
19864 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19865 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19866 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19867 SmallVector<SDValue, 16> PSHUFBMask;
19868 int NumBytes = VT.getSizeInBits() / 8;
19869 int Ratio = NumBytes / Mask.size();
19870 for (int i = 0; i < NumBytes; ++i) {
19871 if (Mask[i / Ratio] == SM_SentinelUndef) {
19872 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
19875 int M = Mask[i / Ratio] != SM_SentinelZero
19876 ? Ratio * Mask[i / Ratio] + i % Ratio
19878 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
19880 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
19881 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
19882 DCI.AddToWorklist(Op.getNode());
19883 SDValue PSHUFBMaskOp =
19884 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
19885 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19886 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
19887 DCI.AddToWorklist(Op.getNode());
19888 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19893 // Failed to find any combines.
19897 /// \brief Fully generic combining of x86 shuffle instructions.
19899 /// This should be the last combine run over the x86 shuffle instructions. Once
19900 /// they have been fully optimized, this will recursively consider all chains
19901 /// of single-use shuffle instructions, build a generic model of the cumulative
19902 /// shuffle operation, and check for simpler instructions which implement this
19903 /// operation. We use this primarily for two purposes:
19905 /// 1) Collapse generic shuffles to specialized single instructions when
19906 /// equivalent. In most cases, this is just an encoding size win, but
19907 /// sometimes we will collapse multiple generic shuffles into a single
19908 /// special-purpose shuffle.
19909 /// 2) Look for sequences of shuffle instructions with 3 or more total
19910 /// instructions, and replace them with the slightly more expensive SSSE3
19911 /// PSHUFB instruction if available. We do this as the last combining step
19912 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19913 /// a suitable short sequence of other instructions. The PHUFB will either
19914 /// use a register or have to read from memory and so is slightly (but only
19915 /// slightly) more expensive than the other shuffle instructions.
19917 /// Because this is inherently a quadratic operation (for each shuffle in
19918 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19919 /// This should never be an issue in practice as the shuffle lowering doesn't
19920 /// produce sequences of more than 8 instructions.
19922 /// FIXME: We will currently miss some cases where the redundant shuffling
19923 /// would simplify under the threshold for PSHUFB formation because of
19924 /// combine-ordering. To fix this, we should do the redundant instruction
19925 /// combining in this recursive walk.
19926 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19927 ArrayRef<int> RootMask,
19928 int Depth, bool HasPSHUFB,
19930 TargetLowering::DAGCombinerInfo &DCI,
19931 const X86Subtarget *Subtarget) {
19932 // Bound the depth of our recursive combine because this is ultimately
19933 // quadratic in nature.
19937 // Directly rip through bitcasts to find the underlying operand.
19938 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19939 Op = Op.getOperand(0);
19941 MVT VT = Op.getSimpleValueType();
19942 if (!VT.isVector())
19943 return false; // Bail if we hit a non-vector.
19945 assert(Root.getSimpleValueType().isVector() &&
19946 "Shuffles operate on vector types!");
19947 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19948 "Can only combine shuffles of the same vector register size.");
19950 if (!isTargetShuffle(Op.getOpcode()))
19952 SmallVector<int, 16> OpMask;
19954 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19955 // We only can combine unary shuffles which we can decode the mask for.
19956 if (!HaveMask || !IsUnary)
19959 assert(VT.getVectorNumElements() == OpMask.size() &&
19960 "Different mask size from vector size!");
19961 assert(((RootMask.size() > OpMask.size() &&
19962 RootMask.size() % OpMask.size() == 0) ||
19963 (OpMask.size() > RootMask.size() &&
19964 OpMask.size() % RootMask.size() == 0) ||
19965 OpMask.size() == RootMask.size()) &&
19966 "The smaller number of elements must divide the larger.");
19967 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19968 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19969 assert(((RootRatio == 1 && OpRatio == 1) ||
19970 (RootRatio == 1) != (OpRatio == 1)) &&
19971 "Must not have a ratio for both incoming and op masks!");
19973 SmallVector<int, 16> Mask;
19974 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19976 // Merge this shuffle operation's mask into our accumulated mask. Note that
19977 // this shuffle's mask will be the first applied to the input, followed by the
19978 // root mask to get us all the way to the root value arrangement. The reason
19979 // for this order is that we are recursing up the operation chain.
19980 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19981 int RootIdx = i / RootRatio;
19982 if (RootMask[RootIdx] < 0) {
19983 // This is a zero or undef lane, we're done.
19984 Mask.push_back(RootMask[RootIdx]);
19988 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19989 int OpIdx = RootMaskedIdx / OpRatio;
19990 if (OpMask[OpIdx] < 0) {
19991 // The incoming lanes are zero or undef, it doesn't matter which ones we
19993 Mask.push_back(OpMask[OpIdx]);
19997 // Ok, we have non-zero lanes, map them through.
19998 Mask.push_back(OpMask[OpIdx] * OpRatio +
19999 RootMaskedIdx % OpRatio);
20002 // See if we can recurse into the operand to combine more things.
20003 switch (Op.getOpcode()) {
20004 case X86ISD::PSHUFB:
20006 case X86ISD::PSHUFD:
20007 case X86ISD::PSHUFHW:
20008 case X86ISD::PSHUFLW:
20009 if (Op.getOperand(0).hasOneUse() &&
20010 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20011 HasPSHUFB, DAG, DCI, Subtarget))
20015 case X86ISD::UNPCKL:
20016 case X86ISD::UNPCKH:
20017 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20018 // We can't check for single use, we have to check that this shuffle is the only user.
20019 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20020 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20021 HasPSHUFB, DAG, DCI, Subtarget))
20026 // Minor canonicalization of the accumulated shuffle mask to make it easier
20027 // to match below. All this does is detect masks with squential pairs of
20028 // elements, and shrink them to the half-width mask. It does this in a loop
20029 // so it will reduce the size of the mask to the minimal width mask which
20030 // performs an equivalent shuffle.
20031 SmallVector<int, 16> WidenedMask;
20032 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20033 Mask = std::move(WidenedMask);
20034 WidenedMask.clear();
20037 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20041 /// \brief Get the PSHUF-style mask from PSHUF node.
20043 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20044 /// PSHUF-style masks that can be reused with such instructions.
20045 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20046 MVT VT = N.getSimpleValueType();
20047 SmallVector<int, 4> Mask;
20049 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20053 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20054 // matter. Check that the upper masks are repeats and remove them.
20055 if (VT.getSizeInBits() > 128) {
20056 int LaneElts = 128 / VT.getScalarSizeInBits();
20058 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20059 for (int j = 0; j < LaneElts; ++j)
20060 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
20061 "Mask doesn't repeat in high 128-bit lanes!");
20063 Mask.resize(LaneElts);
20066 switch (N.getOpcode()) {
20067 case X86ISD::PSHUFD:
20069 case X86ISD::PSHUFLW:
20072 case X86ISD::PSHUFHW:
20073 Mask.erase(Mask.begin(), Mask.begin() + 4);
20074 for (int &M : Mask)
20078 llvm_unreachable("No valid shuffle instruction found!");
20082 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20084 /// We walk up the chain and look for a combinable shuffle, skipping over
20085 /// shuffles that we could hoist this shuffle's transformation past without
20086 /// altering anything.
20088 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20090 TargetLowering::DAGCombinerInfo &DCI) {
20091 assert(N.getOpcode() == X86ISD::PSHUFD &&
20092 "Called with something other than an x86 128-bit half shuffle!");
20095 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20096 // of the shuffles in the chain so that we can form a fresh chain to replace
20098 SmallVector<SDValue, 8> Chain;
20099 SDValue V = N.getOperand(0);
20100 for (; V.hasOneUse(); V = V.getOperand(0)) {
20101 switch (V.getOpcode()) {
20103 return SDValue(); // Nothing combined!
20106 // Skip bitcasts as we always know the type for the target specific
20110 case X86ISD::PSHUFD:
20111 // Found another dword shuffle.
20114 case X86ISD::PSHUFLW:
20115 // Check that the low words (being shuffled) are the identity in the
20116 // dword shuffle, and the high words are self-contained.
20117 if (Mask[0] != 0 || Mask[1] != 1 ||
20118 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20121 Chain.push_back(V);
20124 case X86ISD::PSHUFHW:
20125 // Check that the high words (being shuffled) are the identity in the
20126 // dword shuffle, and the low words are self-contained.
20127 if (Mask[2] != 2 || Mask[3] != 3 ||
20128 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20131 Chain.push_back(V);
20134 case X86ISD::UNPCKL:
20135 case X86ISD::UNPCKH:
20136 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20137 // shuffle into a preceding word shuffle.
20138 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20139 V.getSimpleValueType().getScalarType() != MVT::i16)
20142 // Search for a half-shuffle which we can combine with.
20143 unsigned CombineOp =
20144 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20145 if (V.getOperand(0) != V.getOperand(1) ||
20146 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20148 Chain.push_back(V);
20149 V = V.getOperand(0);
20151 switch (V.getOpcode()) {
20153 return SDValue(); // Nothing to combine.
20155 case X86ISD::PSHUFLW:
20156 case X86ISD::PSHUFHW:
20157 if (V.getOpcode() == CombineOp)
20160 Chain.push_back(V);
20164 V = V.getOperand(0);
20168 } while (V.hasOneUse());
20171 // Break out of the loop if we break out of the switch.
20175 if (!V.hasOneUse())
20176 // We fell out of the loop without finding a viable combining instruction.
20179 // Merge this node's mask and our incoming mask.
20180 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20181 for (int &M : Mask)
20183 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20184 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20186 // Rebuild the chain around this new shuffle.
20187 while (!Chain.empty()) {
20188 SDValue W = Chain.pop_back_val();
20190 if (V.getValueType() != W.getOperand(0).getValueType())
20191 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
20193 switch (W.getOpcode()) {
20195 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20197 case X86ISD::UNPCKL:
20198 case X86ISD::UNPCKH:
20199 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20202 case X86ISD::PSHUFD:
20203 case X86ISD::PSHUFLW:
20204 case X86ISD::PSHUFHW:
20205 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20209 if (V.getValueType() != N.getValueType())
20210 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20212 // Return the new chain to replace N.
20216 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20218 /// We walk up the chain, skipping shuffles of the other half and looking
20219 /// through shuffles which switch halves trying to find a shuffle of the same
20220 /// pair of dwords.
20221 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20223 TargetLowering::DAGCombinerInfo &DCI) {
20225 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20226 "Called with something other than an x86 128-bit half shuffle!");
20228 unsigned CombineOpcode = N.getOpcode();
20230 // Walk up a single-use chain looking for a combinable shuffle.
20231 SDValue V = N.getOperand(0);
20232 for (; V.hasOneUse(); V = V.getOperand(0)) {
20233 switch (V.getOpcode()) {
20235 return false; // Nothing combined!
20238 // Skip bitcasts as we always know the type for the target specific
20242 case X86ISD::PSHUFLW:
20243 case X86ISD::PSHUFHW:
20244 if (V.getOpcode() == CombineOpcode)
20247 // Other-half shuffles are no-ops.
20250 // Break out of the loop if we break out of the switch.
20254 if (!V.hasOneUse())
20255 // We fell out of the loop without finding a viable combining instruction.
20258 // Combine away the bottom node as its shuffle will be accumulated into
20259 // a preceding shuffle.
20260 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20262 // Record the old value.
20265 // Merge this node's mask and our incoming mask (adjusted to account for all
20266 // the pshufd instructions encountered).
20267 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20268 for (int &M : Mask)
20270 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20271 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20273 // Check that the shuffles didn't cancel each other out. If not, we need to
20274 // combine to the new one.
20276 // Replace the combinable shuffle with the combined one, updating all users
20277 // so that we re-evaluate the chain here.
20278 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20283 /// \brief Try to combine x86 target specific shuffles.
20284 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20285 TargetLowering::DAGCombinerInfo &DCI,
20286 const X86Subtarget *Subtarget) {
20288 MVT VT = N.getSimpleValueType();
20289 SmallVector<int, 4> Mask;
20291 switch (N.getOpcode()) {
20292 case X86ISD::PSHUFD:
20293 case X86ISD::PSHUFLW:
20294 case X86ISD::PSHUFHW:
20295 Mask = getPSHUFShuffleMask(N);
20296 assert(Mask.size() == 4);
20302 // Nuke no-op shuffles that show up after combining.
20303 if (isNoopShuffleMask(Mask))
20304 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20306 // Look for simplifications involving one or two shuffle instructions.
20307 SDValue V = N.getOperand(0);
20308 switch (N.getOpcode()) {
20311 case X86ISD::PSHUFLW:
20312 case X86ISD::PSHUFHW:
20313 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20315 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20316 return SDValue(); // We combined away this shuffle, so we're done.
20318 // See if this reduces to a PSHUFD which is no more expensive and can
20319 // combine with more operations. Note that it has to at least flip the
20320 // dwords as otherwise it would have been removed as a no-op.
20321 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20322 int DMask[] = {0, 1, 2, 3};
20323 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20324 DMask[DOffset + 0] = DOffset + 1;
20325 DMask[DOffset + 1] = DOffset + 0;
20326 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20327 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20328 DCI.AddToWorklist(V.getNode());
20329 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20330 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20331 DCI.AddToWorklist(V.getNode());
20332 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20335 // Look for shuffle patterns which can be implemented as a single unpack.
20336 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20337 // only works when we have a PSHUFD followed by two half-shuffles.
20338 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20339 (V.getOpcode() == X86ISD::PSHUFLW ||
20340 V.getOpcode() == X86ISD::PSHUFHW) &&
20341 V.getOpcode() != N.getOpcode() &&
20343 SDValue D = V.getOperand(0);
20344 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20345 D = D.getOperand(0);
20346 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20347 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20348 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20349 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20350 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20352 for (int i = 0; i < 4; ++i) {
20353 WordMask[i + NOffset] = Mask[i] + NOffset;
20354 WordMask[i + VOffset] = VMask[i] + VOffset;
20356 // Map the word mask through the DWord mask.
20358 for (int i = 0; i < 8; ++i)
20359 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20360 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20361 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20362 // We can replace all three shuffles with an unpack.
20363 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20364 DCI.AddToWorklist(V.getNode());
20365 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20374 case X86ISD::PSHUFD:
20375 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20384 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20386 /// We combine this directly on the abstract vector shuffle nodes so it is
20387 /// easier to generically match. We also insert dummy vector shuffle nodes for
20388 /// the operands which explicitly discard the lanes which are unused by this
20389 /// operation to try to flow through the rest of the combiner the fact that
20390 /// they're unused.
20391 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20393 EVT VT = N->getValueType(0);
20395 // We only handle target-independent shuffles.
20396 // FIXME: It would be easy and harmless to use the target shuffle mask
20397 // extraction tool to support more.
20398 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20401 auto *SVN = cast<ShuffleVectorSDNode>(N);
20402 ArrayRef<int> Mask = SVN->getMask();
20403 SDValue V1 = N->getOperand(0);
20404 SDValue V2 = N->getOperand(1);
20406 // We require the first shuffle operand to be the SUB node, and the second to
20407 // be the ADD node.
20408 // FIXME: We should support the commuted patterns.
20409 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20412 // If there are other uses of these operations we can't fold them.
20413 if (!V1->hasOneUse() || !V2->hasOneUse())
20416 // Ensure that both operations have the same operands. Note that we can
20417 // commute the FADD operands.
20418 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20419 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20420 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20423 // We're looking for blends between FADD and FSUB nodes. We insist on these
20424 // nodes being lined up in a specific expected pattern.
20425 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20426 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20427 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20430 // Only specific types are legal at this point, assert so we notice if and
20431 // when these change.
20432 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20433 VT == MVT::v4f64) &&
20434 "Unknown vector type encountered!");
20436 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20439 /// PerformShuffleCombine - Performs several different shuffle combines.
20440 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20441 TargetLowering::DAGCombinerInfo &DCI,
20442 const X86Subtarget *Subtarget) {
20444 SDValue N0 = N->getOperand(0);
20445 SDValue N1 = N->getOperand(1);
20446 EVT VT = N->getValueType(0);
20448 // Don't create instructions with illegal types after legalize types has run.
20449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20450 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20453 // If we have legalized the vector types, look for blends of FADD and FSUB
20454 // nodes that we can fuse into an ADDSUB node.
20455 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20456 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20459 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20460 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20461 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20462 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20464 // During Type Legalization, when promoting illegal vector types,
20465 // the backend might introduce new shuffle dag nodes and bitcasts.
20467 // This code performs the following transformation:
20468 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20469 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20471 // We do this only if both the bitcast and the BINOP dag nodes have
20472 // one use. Also, perform this transformation only if the new binary
20473 // operation is legal. This is to avoid introducing dag nodes that
20474 // potentially need to be further expanded (or custom lowered) into a
20475 // less optimal sequence of dag nodes.
20476 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20477 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20478 N0.getOpcode() == ISD::BITCAST) {
20479 SDValue BC0 = N0.getOperand(0);
20480 EVT SVT = BC0.getValueType();
20481 unsigned Opcode = BC0.getOpcode();
20482 unsigned NumElts = VT.getVectorNumElements();
20484 if (BC0.hasOneUse() && SVT.isVector() &&
20485 SVT.getVectorNumElements() * 2 == NumElts &&
20486 TLI.isOperationLegal(Opcode, VT)) {
20487 bool CanFold = false;
20499 unsigned SVTNumElts = SVT.getVectorNumElements();
20500 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20501 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20502 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20503 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20504 CanFold = SVOp->getMaskElt(i) < 0;
20507 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20508 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20509 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20510 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20515 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20516 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20517 // consecutive, non-overlapping, and in the right order.
20518 SmallVector<SDValue, 16> Elts;
20519 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20520 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20522 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20526 if (isTargetShuffle(N->getOpcode())) {
20528 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20529 if (Shuffle.getNode())
20532 // Try recursively combining arbitrary sequences of x86 shuffle
20533 // instructions into higher-order shuffles. We do this after combining
20534 // specific PSHUF instruction sequences into their minimal form so that we
20535 // can evaluate how many specialized shuffle instructions are involved in
20536 // a particular chain.
20537 SmallVector<int, 1> NonceMask; // Just a placeholder.
20538 NonceMask.push_back(0);
20539 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20540 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20542 return SDValue(); // This routine will use CombineTo to replace N.
20548 /// PerformTruncateCombine - Converts truncate operation to
20549 /// a sequence of vector shuffle operations.
20550 /// It is possible when we truncate 256-bit vector to 128-bit vector
20551 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20552 TargetLowering::DAGCombinerInfo &DCI,
20553 const X86Subtarget *Subtarget) {
20557 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20558 /// specific shuffle of a load can be folded into a single element load.
20559 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20560 /// shuffles have been custom lowered so we need to handle those here.
20561 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20562 TargetLowering::DAGCombinerInfo &DCI) {
20563 if (DCI.isBeforeLegalizeOps())
20566 SDValue InVec = N->getOperand(0);
20567 SDValue EltNo = N->getOperand(1);
20569 if (!isa<ConstantSDNode>(EltNo))
20572 EVT OriginalVT = InVec.getValueType();
20574 if (InVec.getOpcode() == ISD::BITCAST) {
20575 // Don't duplicate a load with other uses.
20576 if (!InVec.hasOneUse())
20578 EVT BCVT = InVec.getOperand(0).getValueType();
20579 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20581 InVec = InVec.getOperand(0);
20584 EVT CurrentVT = InVec.getValueType();
20586 if (!isTargetShuffle(InVec.getOpcode()))
20589 // Don't duplicate a load with other uses.
20590 if (!InVec.hasOneUse())
20593 SmallVector<int, 16> ShuffleMask;
20595 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20596 ShuffleMask, UnaryShuffle))
20599 // Select the input vector, guarding against out of range extract vector.
20600 unsigned NumElems = CurrentVT.getVectorNumElements();
20601 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20602 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20603 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20604 : InVec.getOperand(1);
20606 // If inputs to shuffle are the same for both ops, then allow 2 uses
20607 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20608 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20610 if (LdNode.getOpcode() == ISD::BITCAST) {
20611 // Don't duplicate a load with other uses.
20612 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20615 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20616 LdNode = LdNode.getOperand(0);
20619 if (!ISD::isNormalLoad(LdNode.getNode()))
20622 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20624 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20627 EVT EltVT = N->getValueType(0);
20628 // If there's a bitcast before the shuffle, check if the load type and
20629 // alignment is valid.
20630 unsigned Align = LN0->getAlignment();
20631 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20632 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20633 EltVT.getTypeForEVT(*DAG.getContext()));
20635 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20638 // All checks match so transform back to vector_shuffle so that DAG combiner
20639 // can finish the job
20642 // Create shuffle node taking into account the case that its a unary shuffle
20643 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20644 : InVec.getOperand(1);
20645 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20646 InVec.getOperand(0), Shuffle,
20648 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20649 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20653 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20654 /// special and don't usually play with other vector types, it's better to
20655 /// handle them early to be sure we emit efficient code by avoiding
20656 /// store-load conversions.
20657 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20658 if (N->getValueType(0) != MVT::x86mmx ||
20659 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
20660 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20663 SDValue V = N->getOperand(0);
20664 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20665 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20666 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20667 N->getValueType(0), V.getOperand(0));
20672 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20673 /// generation and convert it from being a bunch of shuffles and extracts
20674 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20675 /// storing the value and loading scalars back, while for x64 we should
20676 /// use 64-bit extracts and shifts.
20677 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20678 TargetLowering::DAGCombinerInfo &DCI) {
20679 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20680 if (NewOp.getNode())
20683 SDValue InputVector = N->getOperand(0);
20685 // Detect mmx to i32 conversion through a v2i32 elt extract.
20686 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20687 N->getValueType(0) == MVT::i32 &&
20688 InputVector.getValueType() == MVT::v2i32) {
20690 // The bitcast source is a direct mmx result.
20691 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20692 if (MMXSrc.getValueType() == MVT::x86mmx)
20693 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20694 N->getValueType(0),
20695 InputVector.getNode()->getOperand(0));
20697 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20698 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20699 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20700 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20701 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20702 MMXSrcOp.getValueType() == MVT::v1i64 &&
20703 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20704 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20705 N->getValueType(0),
20706 MMXSrcOp.getOperand(0));
20709 // Only operate on vectors of 4 elements, where the alternative shuffling
20710 // gets to be more expensive.
20711 if (InputVector.getValueType() != MVT::v4i32)
20714 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20715 // single use which is a sign-extend or zero-extend, and all elements are
20717 SmallVector<SDNode *, 4> Uses;
20718 unsigned ExtractedElements = 0;
20719 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20720 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20721 if (UI.getUse().getResNo() != InputVector.getResNo())
20724 SDNode *Extract = *UI;
20725 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20728 if (Extract->getValueType(0) != MVT::i32)
20730 if (!Extract->hasOneUse())
20732 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20733 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20735 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20738 // Record which element was extracted.
20739 ExtractedElements |=
20740 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20742 Uses.push_back(Extract);
20745 // If not all the elements were used, this may not be worthwhile.
20746 if (ExtractedElements != 15)
20749 // Ok, we've now decided to do the transformation.
20750 // If 64-bit shifts are legal, use the extract-shift sequence,
20751 // otherwise bounce the vector off the cache.
20752 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20754 SDLoc dl(InputVector);
20756 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20757 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20758 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20759 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20760 DAG.getConstant(0, dl, VecIdxTy));
20761 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20762 DAG.getConstant(1, dl, VecIdxTy));
20764 SDValue ShAmt = DAG.getConstant(32, dl,
20765 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20766 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20767 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20768 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20769 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20770 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20771 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20773 // Store the value to a temporary stack slot.
20774 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20775 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20776 MachinePointerInfo(), false, false, 0);
20778 EVT ElementType = InputVector.getValueType().getVectorElementType();
20779 unsigned EltSize = ElementType.getSizeInBits() / 8;
20781 // Replace each use (extract) with a load of the appropriate element.
20782 for (unsigned i = 0; i < 4; ++i) {
20783 uint64_t Offset = EltSize * i;
20784 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
20786 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20787 StackPtr, OffsetVal);
20789 // Load the scalar.
20790 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20791 ScalarAddr, MachinePointerInfo(),
20792 false, false, false, 0);
20797 // Replace the extracts
20798 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20799 UE = Uses.end(); UI != UE; ++UI) {
20800 SDNode *Extract = *UI;
20802 SDValue Idx = Extract->getOperand(1);
20803 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20804 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20807 // The replacement was made in place; don't return anything.
20811 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20812 static std::pair<unsigned, bool>
20813 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20814 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20815 if (!VT.isVector())
20816 return std::make_pair(0, false);
20818 bool NeedSplit = false;
20819 switch (VT.getSimpleVT().SimpleTy) {
20820 default: return std::make_pair(0, false);
20823 if (!Subtarget->hasVLX())
20824 return std::make_pair(0, false);
20828 if (!Subtarget->hasBWI())
20829 return std::make_pair(0, false);
20833 if (!Subtarget->hasAVX512())
20834 return std::make_pair(0, false);
20839 if (!Subtarget->hasAVX2())
20841 if (!Subtarget->hasAVX())
20842 return std::make_pair(0, false);
20847 if (!Subtarget->hasSSE2())
20848 return std::make_pair(0, false);
20851 // SSE2 has only a small subset of the operations.
20852 bool hasUnsigned = Subtarget->hasSSE41() ||
20853 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20854 bool hasSigned = Subtarget->hasSSE41() ||
20855 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20857 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20860 // Check for x CC y ? x : y.
20861 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20862 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20867 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20870 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20873 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20876 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20878 // Check for x CC y ? y : x -- a min/max with reversed arms.
20879 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20880 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20885 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20888 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20891 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20894 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20898 return std::make_pair(Opc, NeedSplit);
20902 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20903 const X86Subtarget *Subtarget) {
20905 SDValue Cond = N->getOperand(0);
20906 SDValue LHS = N->getOperand(1);
20907 SDValue RHS = N->getOperand(2);
20909 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20910 SDValue CondSrc = Cond->getOperand(0);
20911 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20912 Cond = CondSrc->getOperand(0);
20915 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20918 // A vselect where all conditions and data are constants can be optimized into
20919 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20920 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20921 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20924 unsigned MaskValue = 0;
20925 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20928 MVT VT = N->getSimpleValueType(0);
20929 unsigned NumElems = VT.getVectorNumElements();
20930 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20931 for (unsigned i = 0; i < NumElems; ++i) {
20932 // Be sure we emit undef where we can.
20933 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20934 ShuffleMask[i] = -1;
20936 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20939 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20940 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
20942 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20945 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20947 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20948 TargetLowering::DAGCombinerInfo &DCI,
20949 const X86Subtarget *Subtarget) {
20951 SDValue Cond = N->getOperand(0);
20952 // Get the LHS/RHS of the select.
20953 SDValue LHS = N->getOperand(1);
20954 SDValue RHS = N->getOperand(2);
20955 EVT VT = LHS.getValueType();
20956 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20958 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20959 // instructions match the semantics of the common C idiom x<y?x:y but not
20960 // x<=y?x:y, because of how they handle negative zero (which can be
20961 // ignored in unsafe-math mode).
20962 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
20963 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20964 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
20965 (Subtarget->hasSSE2() ||
20966 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20967 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20969 unsigned Opcode = 0;
20970 // Check for x CC y ? x : y.
20971 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20972 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20976 // Converting this to a min would handle NaNs incorrectly, and swapping
20977 // the operands would cause it to handle comparisons between positive
20978 // and negative zero incorrectly.
20979 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20980 if (!DAG.getTarget().Options.UnsafeFPMath &&
20981 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20983 std::swap(LHS, RHS);
20985 Opcode = X86ISD::FMIN;
20988 // Converting this to a min would handle comparisons between positive
20989 // and negative zero incorrectly.
20990 if (!DAG.getTarget().Options.UnsafeFPMath &&
20991 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20993 Opcode = X86ISD::FMIN;
20996 // Converting this to a min would handle both negative zeros and NaNs
20997 // incorrectly, but we can swap the operands to fix both.
20998 std::swap(LHS, RHS);
21002 Opcode = X86ISD::FMIN;
21006 // Converting this to a max would handle comparisons between positive
21007 // and negative zero incorrectly.
21008 if (!DAG.getTarget().Options.UnsafeFPMath &&
21009 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21011 Opcode = X86ISD::FMAX;
21014 // Converting this to a max would handle NaNs incorrectly, and swapping
21015 // the operands would cause it to handle comparisons between positive
21016 // and negative zero incorrectly.
21017 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21018 if (!DAG.getTarget().Options.UnsafeFPMath &&
21019 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21021 std::swap(LHS, RHS);
21023 Opcode = X86ISD::FMAX;
21026 // Converting this to a max would handle both negative zeros and NaNs
21027 // incorrectly, but we can swap the operands to fix both.
21028 std::swap(LHS, RHS);
21032 Opcode = X86ISD::FMAX;
21035 // Check for x CC y ? y : x -- a min/max with reversed arms.
21036 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21037 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21041 // Converting this to a min would handle comparisons between positive
21042 // and negative zero incorrectly, and swapping the operands would
21043 // cause it to handle NaNs incorrectly.
21044 if (!DAG.getTarget().Options.UnsafeFPMath &&
21045 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21046 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21048 std::swap(LHS, RHS);
21050 Opcode = X86ISD::FMIN;
21053 // Converting this to a min would handle NaNs incorrectly.
21054 if (!DAG.getTarget().Options.UnsafeFPMath &&
21055 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21057 Opcode = X86ISD::FMIN;
21060 // Converting this to a min would handle both negative zeros and NaNs
21061 // incorrectly, but we can swap the operands to fix both.
21062 std::swap(LHS, RHS);
21066 Opcode = X86ISD::FMIN;
21070 // Converting this to a max would handle NaNs incorrectly.
21071 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21073 Opcode = X86ISD::FMAX;
21076 // Converting this to a max would handle comparisons between positive
21077 // and negative zero incorrectly, and swapping the operands would
21078 // cause it to handle NaNs incorrectly.
21079 if (!DAG.getTarget().Options.UnsafeFPMath &&
21080 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21081 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21083 std::swap(LHS, RHS);
21085 Opcode = X86ISD::FMAX;
21088 // Converting this to a max would handle both negative zeros and NaNs
21089 // incorrectly, but we can swap the operands to fix both.
21090 std::swap(LHS, RHS);
21094 Opcode = X86ISD::FMAX;
21100 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21103 EVT CondVT = Cond.getValueType();
21104 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21105 CondVT.getVectorElementType() == MVT::i1) {
21106 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21107 // lowering on KNL. In this case we convert it to
21108 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21109 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21110 // Since SKX these selects have a proper lowering.
21111 EVT OpVT = LHS.getValueType();
21112 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21113 (OpVT.getVectorElementType() == MVT::i8 ||
21114 OpVT.getVectorElementType() == MVT::i16) &&
21115 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21116 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21117 DCI.AddToWorklist(Cond.getNode());
21118 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21121 // If this is a select between two integer constants, try to do some
21123 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21124 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21125 // Don't do this for crazy integer types.
21126 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21127 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21128 // so that TrueC (the true value) is larger than FalseC.
21129 bool NeedsCondInvert = false;
21131 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21132 // Efficiently invertible.
21133 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21134 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21135 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21136 NeedsCondInvert = true;
21137 std::swap(TrueC, FalseC);
21140 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21141 if (FalseC->getAPIntValue() == 0 &&
21142 TrueC->getAPIntValue().isPowerOf2()) {
21143 if (NeedsCondInvert) // Invert the condition if needed.
21144 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21145 DAG.getConstant(1, DL, Cond.getValueType()));
21147 // Zero extend the condition if needed.
21148 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21150 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21151 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21152 DAG.getConstant(ShAmt, DL, MVT::i8));
21155 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21156 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21157 if (NeedsCondInvert) // Invert the condition if needed.
21158 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21159 DAG.getConstant(1, DL, Cond.getValueType()));
21161 // Zero extend the condition if needed.
21162 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21163 FalseC->getValueType(0), Cond);
21164 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21165 SDValue(FalseC, 0));
21168 // Optimize cases that will turn into an LEA instruction. This requires
21169 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21170 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21171 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21172 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21174 bool isFastMultiplier = false;
21176 switch ((unsigned char)Diff) {
21178 case 1: // result = add base, cond
21179 case 2: // result = lea base( , cond*2)
21180 case 3: // result = lea base(cond, cond*2)
21181 case 4: // result = lea base( , cond*4)
21182 case 5: // result = lea base(cond, cond*4)
21183 case 8: // result = lea base( , cond*8)
21184 case 9: // result = lea base(cond, cond*8)
21185 isFastMultiplier = true;
21190 if (isFastMultiplier) {
21191 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21192 if (NeedsCondInvert) // Invert the condition if needed.
21193 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21194 DAG.getConstant(1, DL, Cond.getValueType()));
21196 // Zero extend the condition if needed.
21197 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21199 // Scale the condition by the difference.
21201 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21202 DAG.getConstant(Diff, DL,
21203 Cond.getValueType()));
21205 // Add the base if non-zero.
21206 if (FalseC->getAPIntValue() != 0)
21207 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21208 SDValue(FalseC, 0));
21215 // Canonicalize max and min:
21216 // (x > y) ? x : y -> (x >= y) ? x : y
21217 // (x < y) ? x : y -> (x <= y) ? x : y
21218 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21219 // the need for an extra compare
21220 // against zero. e.g.
21221 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21223 // testl %edi, %edi
21225 // cmovgl %edi, %eax
21229 // cmovsl %eax, %edi
21230 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21231 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21232 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21233 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21238 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21239 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21240 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21241 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21246 // Early exit check
21247 if (!TLI.isTypeLegal(VT))
21250 // Match VSELECTs into subs with unsigned saturation.
21251 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21252 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21253 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21254 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21255 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21257 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21258 // left side invert the predicate to simplify logic below.
21260 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21262 CC = ISD::getSetCCInverse(CC, true);
21263 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21267 if (Other.getNode() && Other->getNumOperands() == 2 &&
21268 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21269 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21270 SDValue CondRHS = Cond->getOperand(1);
21272 // Look for a general sub with unsigned saturation first.
21273 // x >= y ? x-y : 0 --> subus x, y
21274 // x > y ? x-y : 0 --> subus x, y
21275 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21276 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21277 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21279 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21280 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21281 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21282 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21283 // If the RHS is a constant we have to reverse the const
21284 // canonicalization.
21285 // x > C-1 ? x+-C : 0 --> subus x, C
21286 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21287 CondRHSConst->getAPIntValue() ==
21288 (-OpRHSConst->getAPIntValue() - 1))
21289 return DAG.getNode(
21290 X86ISD::SUBUS, DL, VT, OpLHS,
21291 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21293 // Another special case: If C was a sign bit, the sub has been
21294 // canonicalized into a xor.
21295 // FIXME: Would it be better to use computeKnownBits to determine
21296 // whether it's safe to decanonicalize the xor?
21297 // x s< 0 ? x^C : 0 --> subus x, C
21298 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21299 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21300 OpRHSConst->getAPIntValue().isSignBit())
21301 // Note that we have to rebuild the RHS constant here to ensure we
21302 // don't rely on particular values of undef lanes.
21303 return DAG.getNode(
21304 X86ISD::SUBUS, DL, VT, OpLHS,
21305 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21310 // Try to match a min/max vector operation.
21311 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21312 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21313 unsigned Opc = ret.first;
21314 bool NeedSplit = ret.second;
21316 if (Opc && NeedSplit) {
21317 unsigned NumElems = VT.getVectorNumElements();
21318 // Extract the LHS vectors
21319 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21320 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21322 // Extract the RHS vectors
21323 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21324 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21326 // Create min/max for each subvector
21327 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21328 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21330 // Merge the result
21331 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21333 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21336 // Simplify vector selection if condition value type matches vselect
21338 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21339 assert(Cond.getValueType().isVector() &&
21340 "vector select expects a vector selector!");
21342 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21343 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21345 // Try invert the condition if true value is not all 1s and false value
21347 if (!TValIsAllOnes && !FValIsAllZeros &&
21348 // Check if the selector will be produced by CMPP*/PCMP*
21349 Cond.getOpcode() == ISD::SETCC &&
21350 // Check if SETCC has already been promoted
21351 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21352 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21353 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21355 if (TValIsAllZeros || FValIsAllOnes) {
21356 SDValue CC = Cond.getOperand(2);
21357 ISD::CondCode NewCC =
21358 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21359 Cond.getOperand(0).getValueType().isInteger());
21360 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21361 std::swap(LHS, RHS);
21362 TValIsAllOnes = FValIsAllOnes;
21363 FValIsAllZeros = TValIsAllZeros;
21367 if (TValIsAllOnes || FValIsAllZeros) {
21370 if (TValIsAllOnes && FValIsAllZeros)
21372 else if (TValIsAllOnes)
21373 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21374 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21375 else if (FValIsAllZeros)
21376 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21377 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21379 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21383 // We should generate an X86ISD::BLENDI from a vselect if its argument
21384 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21385 // constants. This specific pattern gets generated when we split a
21386 // selector for a 512 bit vector in a machine without AVX512 (but with
21387 // 256-bit vectors), during legalization:
21389 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21391 // Iff we find this pattern and the build_vectors are built from
21392 // constants, we translate the vselect into a shuffle_vector that we
21393 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21394 if ((N->getOpcode() == ISD::VSELECT ||
21395 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21396 !DCI.isBeforeLegalize()) {
21397 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21398 if (Shuffle.getNode())
21402 // If this is a *dynamic* select (non-constant condition) and we can match
21403 // this node with one of the variable blend instructions, restructure the
21404 // condition so that the blends can use the high bit of each element and use
21405 // SimplifyDemandedBits to simplify the condition operand.
21406 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21407 !DCI.isBeforeLegalize() &&
21408 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21409 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21411 // Don't optimize vector selects that map to mask-registers.
21415 // We can only handle the cases where VSELECT is directly legal on the
21416 // subtarget. We custom lower VSELECT nodes with constant conditions and
21417 // this makes it hard to see whether a dynamic VSELECT will correctly
21418 // lower, so we both check the operation's status and explicitly handle the
21419 // cases where a *dynamic* blend will fail even though a constant-condition
21420 // blend could be custom lowered.
21421 // FIXME: We should find a better way to handle this class of problems.
21422 // Potentially, we should combine constant-condition vselect nodes
21423 // pre-legalization into shuffles and not mark as many types as custom
21425 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21427 // FIXME: We don't support i16-element blends currently. We could and
21428 // should support them by making *all* the bits in the condition be set
21429 // rather than just the high bit and using an i8-element blend.
21430 if (VT.getScalarType() == MVT::i16)
21432 // Dynamic blending was only available from SSE4.1 onward.
21433 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21435 // Byte blends are only available in AVX2
21436 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21437 !Subtarget->hasAVX2())
21440 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21441 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21443 APInt KnownZero, KnownOne;
21444 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21445 DCI.isBeforeLegalizeOps());
21446 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21447 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21449 // If we changed the computation somewhere in the DAG, this change
21450 // will affect all users of Cond.
21451 // Make sure it is fine and update all the nodes so that we do not
21452 // use the generic VSELECT anymore. Otherwise, we may perform
21453 // wrong optimizations as we messed up with the actual expectation
21454 // for the vector boolean values.
21455 if (Cond != TLO.Old) {
21456 // Check all uses of that condition operand to check whether it will be
21457 // consumed by non-BLEND instructions, which may depend on all bits are
21459 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21461 if (I->getOpcode() != ISD::VSELECT)
21462 // TODO: Add other opcodes eventually lowered into BLEND.
21465 // Update all the users of the condition, before committing the change,
21466 // so that the VSELECT optimizations that expect the correct vector
21467 // boolean value will not be triggered.
21468 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21470 DAG.ReplaceAllUsesOfValueWith(
21472 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21473 Cond, I->getOperand(1), I->getOperand(2)));
21474 DCI.CommitTargetLoweringOpt(TLO);
21477 // At this point, only Cond is changed. Change the condition
21478 // just for N to keep the opportunity to optimize all other
21479 // users their own way.
21480 DAG.ReplaceAllUsesOfValueWith(
21482 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21483 TLO.New, N->getOperand(1), N->getOperand(2)));
21491 // Check whether a boolean test is testing a boolean value generated by
21492 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21495 // Simplify the following patterns:
21496 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21497 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21498 // to (Op EFLAGS Cond)
21500 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21501 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21502 // to (Op EFLAGS !Cond)
21504 // where Op could be BRCOND or CMOV.
21506 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21507 // Quit if not CMP and SUB with its value result used.
21508 if (Cmp.getOpcode() != X86ISD::CMP &&
21509 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21512 // Quit if not used as a boolean value.
21513 if (CC != X86::COND_E && CC != X86::COND_NE)
21516 // Check CMP operands. One of them should be 0 or 1 and the other should be
21517 // an SetCC or extended from it.
21518 SDValue Op1 = Cmp.getOperand(0);
21519 SDValue Op2 = Cmp.getOperand(1);
21522 const ConstantSDNode* C = nullptr;
21523 bool needOppositeCond = (CC == X86::COND_E);
21524 bool checkAgainstTrue = false; // Is it a comparison against 1?
21526 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21528 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21530 else // Quit if all operands are not constants.
21533 if (C->getZExtValue() == 1) {
21534 needOppositeCond = !needOppositeCond;
21535 checkAgainstTrue = true;
21536 } else if (C->getZExtValue() != 0)
21537 // Quit if the constant is neither 0 or 1.
21540 bool truncatedToBoolWithAnd = false;
21541 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21542 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21543 SetCC.getOpcode() == ISD::TRUNCATE ||
21544 SetCC.getOpcode() == ISD::AND) {
21545 if (SetCC.getOpcode() == ISD::AND) {
21547 ConstantSDNode *CS;
21548 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21549 CS->getZExtValue() == 1)
21551 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21552 CS->getZExtValue() == 1)
21556 SetCC = SetCC.getOperand(OpIdx);
21557 truncatedToBoolWithAnd = true;
21559 SetCC = SetCC.getOperand(0);
21562 switch (SetCC.getOpcode()) {
21563 case X86ISD::SETCC_CARRY:
21564 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21565 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21566 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21567 // truncated to i1 using 'and'.
21568 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21570 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21571 "Invalid use of SETCC_CARRY!");
21573 case X86ISD::SETCC:
21574 // Set the condition code or opposite one if necessary.
21575 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21576 if (needOppositeCond)
21577 CC = X86::GetOppositeBranchCondition(CC);
21578 return SetCC.getOperand(1);
21579 case X86ISD::CMOV: {
21580 // Check whether false/true value has canonical one, i.e. 0 or 1.
21581 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21582 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21583 // Quit if true value is not a constant.
21586 // Quit if false value is not a constant.
21588 SDValue Op = SetCC.getOperand(0);
21589 // Skip 'zext' or 'trunc' node.
21590 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21591 Op.getOpcode() == ISD::TRUNCATE)
21592 Op = Op.getOperand(0);
21593 // A special case for rdrand/rdseed, where 0 is set if false cond is
21595 if ((Op.getOpcode() != X86ISD::RDRAND &&
21596 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21599 // Quit if false value is not the constant 0 or 1.
21600 bool FValIsFalse = true;
21601 if (FVal && FVal->getZExtValue() != 0) {
21602 if (FVal->getZExtValue() != 1)
21604 // If FVal is 1, opposite cond is needed.
21605 needOppositeCond = !needOppositeCond;
21606 FValIsFalse = false;
21608 // Quit if TVal is not the constant opposite of FVal.
21609 if (FValIsFalse && TVal->getZExtValue() != 1)
21611 if (!FValIsFalse && TVal->getZExtValue() != 0)
21613 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21614 if (needOppositeCond)
21615 CC = X86::GetOppositeBranchCondition(CC);
21616 return SetCC.getOperand(3);
21623 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21625 /// (X86or (X86setcc) (X86setcc))
21626 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21627 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21628 X86::CondCode &CC1, SDValue &Flags,
21630 if (Cond->getOpcode() == X86ISD::CMP) {
21631 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21632 if (!CondOp1C || !CondOp1C->isNullValue())
21635 Cond = Cond->getOperand(0);
21640 SDValue SetCC0, SetCC1;
21641 switch (Cond->getOpcode()) {
21642 default: return false;
21649 SetCC0 = Cond->getOperand(0);
21650 SetCC1 = Cond->getOperand(1);
21654 // Make sure we have SETCC nodes, using the same flags value.
21655 if (SetCC0.getOpcode() != X86ISD::SETCC ||
21656 SetCC1.getOpcode() != X86ISD::SETCC ||
21657 SetCC0->getOperand(1) != SetCC1->getOperand(1))
21660 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
21661 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
21662 Flags = SetCC0->getOperand(1);
21666 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21667 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21668 TargetLowering::DAGCombinerInfo &DCI,
21669 const X86Subtarget *Subtarget) {
21672 // If the flag operand isn't dead, don't touch this CMOV.
21673 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21676 SDValue FalseOp = N->getOperand(0);
21677 SDValue TrueOp = N->getOperand(1);
21678 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21679 SDValue Cond = N->getOperand(3);
21681 if (CC == X86::COND_E || CC == X86::COND_NE) {
21682 switch (Cond.getOpcode()) {
21686 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21687 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21688 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21694 Flags = checkBoolTestSetCCCombine(Cond, CC);
21695 if (Flags.getNode() &&
21696 // Extra check as FCMOV only supports a subset of X86 cond.
21697 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21698 SDValue Ops[] = { FalseOp, TrueOp,
21699 DAG.getConstant(CC, DL, MVT::i8), Flags };
21700 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21703 // If this is a select between two integer constants, try to do some
21704 // optimizations. Note that the operands are ordered the opposite of SELECT
21706 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21707 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21708 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21709 // larger than FalseC (the false value).
21710 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21711 CC = X86::GetOppositeBranchCondition(CC);
21712 std::swap(TrueC, FalseC);
21713 std::swap(TrueOp, FalseOp);
21716 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21717 // This is efficient for any integer data type (including i8/i16) and
21719 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21720 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21721 DAG.getConstant(CC, DL, MVT::i8), Cond);
21723 // Zero extend the condition if needed.
21724 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21726 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21727 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21728 DAG.getConstant(ShAmt, DL, MVT::i8));
21729 if (N->getNumValues() == 2) // Dead flag value?
21730 return DCI.CombineTo(N, Cond, SDValue());
21734 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21735 // for any integer data type, including i8/i16.
21736 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21737 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21738 DAG.getConstant(CC, DL, MVT::i8), Cond);
21740 // Zero extend the condition if needed.
21741 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21742 FalseC->getValueType(0), Cond);
21743 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21744 SDValue(FalseC, 0));
21746 if (N->getNumValues() == 2) // Dead flag value?
21747 return DCI.CombineTo(N, Cond, SDValue());
21751 // Optimize cases that will turn into an LEA instruction. This requires
21752 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21753 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21754 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21755 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21757 bool isFastMultiplier = false;
21759 switch ((unsigned char)Diff) {
21761 case 1: // result = add base, cond
21762 case 2: // result = lea base( , cond*2)
21763 case 3: // result = lea base(cond, cond*2)
21764 case 4: // result = lea base( , cond*4)
21765 case 5: // result = lea base(cond, cond*4)
21766 case 8: // result = lea base( , cond*8)
21767 case 9: // result = lea base(cond, cond*8)
21768 isFastMultiplier = true;
21773 if (isFastMultiplier) {
21774 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21775 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21776 DAG.getConstant(CC, DL, MVT::i8), Cond);
21777 // Zero extend the condition if needed.
21778 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21780 // Scale the condition by the difference.
21782 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21783 DAG.getConstant(Diff, DL, Cond.getValueType()));
21785 // Add the base if non-zero.
21786 if (FalseC->getAPIntValue() != 0)
21787 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21788 SDValue(FalseC, 0));
21789 if (N->getNumValues() == 2) // Dead flag value?
21790 return DCI.CombineTo(N, Cond, SDValue());
21797 // Handle these cases:
21798 // (select (x != c), e, c) -> select (x != c), e, x),
21799 // (select (x == c), c, e) -> select (x == c), x, e)
21800 // where the c is an integer constant, and the "select" is the combination
21801 // of CMOV and CMP.
21803 // The rationale for this change is that the conditional-move from a constant
21804 // needs two instructions, however, conditional-move from a register needs
21805 // only one instruction.
21807 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21808 // some instruction-combining opportunities. This opt needs to be
21809 // postponed as late as possible.
21811 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21812 // the DCI.xxxx conditions are provided to postpone the optimization as
21813 // late as possible.
21815 ConstantSDNode *CmpAgainst = nullptr;
21816 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21817 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21818 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21820 if (CC == X86::COND_NE &&
21821 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21822 CC = X86::GetOppositeBranchCondition(CC);
21823 std::swap(TrueOp, FalseOp);
21826 if (CC == X86::COND_E &&
21827 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21828 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21829 DAG.getConstant(CC, DL, MVT::i8), Cond };
21830 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21835 // Fold and/or of setcc's to double CMOV:
21836 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
21837 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
21839 // This combine lets us generate:
21840 // cmovcc1 (jcc1 if we don't have CMOV)
21846 // cmovne (jne if we don't have CMOV)
21847 // When we can't use the CMOV instruction, it might increase branch
21849 // When we can use CMOV, or when there is no mispredict, this improves
21850 // throughput and reduces register pressure.
21852 if (CC == X86::COND_NE) {
21854 X86::CondCode CC0, CC1;
21856 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
21858 std::swap(FalseOp, TrueOp);
21859 CC0 = X86::GetOppositeBranchCondition(CC0);
21860 CC1 = X86::GetOppositeBranchCondition(CC1);
21863 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
21865 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
21866 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
21867 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21868 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
21876 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21877 const X86Subtarget *Subtarget) {
21878 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21880 default: return SDValue();
21881 // SSE/AVX/AVX2 blend intrinsics.
21882 case Intrinsic::x86_avx2_pblendvb:
21883 // Don't try to simplify this intrinsic if we don't have AVX2.
21884 if (!Subtarget->hasAVX2())
21887 case Intrinsic::x86_avx_blendv_pd_256:
21888 case Intrinsic::x86_avx_blendv_ps_256:
21889 // Don't try to simplify this intrinsic if we don't have AVX.
21890 if (!Subtarget->hasAVX())
21893 case Intrinsic::x86_sse41_blendvps:
21894 case Intrinsic::x86_sse41_blendvpd:
21895 case Intrinsic::x86_sse41_pblendvb: {
21896 SDValue Op0 = N->getOperand(1);
21897 SDValue Op1 = N->getOperand(2);
21898 SDValue Mask = N->getOperand(3);
21900 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21901 if (!Subtarget->hasSSE41())
21904 // fold (blend A, A, Mask) -> A
21907 // fold (blend A, B, allZeros) -> A
21908 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21910 // fold (blend A, B, allOnes) -> B
21911 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21914 // Simplify the case where the mask is a constant i32 value.
21915 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21916 if (C->isNullValue())
21918 if (C->isAllOnesValue())
21925 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21926 case Intrinsic::x86_sse2_psrai_w:
21927 case Intrinsic::x86_sse2_psrai_d:
21928 case Intrinsic::x86_avx2_psrai_w:
21929 case Intrinsic::x86_avx2_psrai_d:
21930 case Intrinsic::x86_sse2_psra_w:
21931 case Intrinsic::x86_sse2_psra_d:
21932 case Intrinsic::x86_avx2_psra_w:
21933 case Intrinsic::x86_avx2_psra_d: {
21934 SDValue Op0 = N->getOperand(1);
21935 SDValue Op1 = N->getOperand(2);
21936 EVT VT = Op0.getValueType();
21937 assert(VT.isVector() && "Expected a vector type!");
21939 if (isa<BuildVectorSDNode>(Op1))
21940 Op1 = Op1.getOperand(0);
21942 if (!isa<ConstantSDNode>(Op1))
21945 EVT SVT = VT.getVectorElementType();
21946 unsigned SVTBits = SVT.getSizeInBits();
21948 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21949 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21950 uint64_t ShAmt = C.getZExtValue();
21952 // Don't try to convert this shift into a ISD::SRA if the shift
21953 // count is bigger than or equal to the element size.
21954 if (ShAmt >= SVTBits)
21957 // Trivial case: if the shift count is zero, then fold this
21958 // into the first operand.
21962 // Replace this packed shift intrinsic with a target independent
21965 SDValue Splat = DAG.getConstant(C, DL, VT);
21966 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
21971 /// PerformMulCombine - Optimize a single multiply with constant into two
21972 /// in order to implement it with two cheaper instructions, e.g.
21973 /// LEA + SHL, LEA + LEA.
21974 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21975 TargetLowering::DAGCombinerInfo &DCI) {
21976 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21979 EVT VT = N->getValueType(0);
21980 if (VT != MVT::i64 && VT != MVT::i32)
21983 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21986 uint64_t MulAmt = C->getZExtValue();
21987 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21990 uint64_t MulAmt1 = 0;
21991 uint64_t MulAmt2 = 0;
21992 if ((MulAmt % 9) == 0) {
21994 MulAmt2 = MulAmt / 9;
21995 } else if ((MulAmt % 5) == 0) {
21997 MulAmt2 = MulAmt / 5;
21998 } else if ((MulAmt % 3) == 0) {
22000 MulAmt2 = MulAmt / 3;
22003 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22006 if (isPowerOf2_64(MulAmt2) &&
22007 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22008 // If second multiplifer is pow2, issue it first. We want the multiply by
22009 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22011 std::swap(MulAmt1, MulAmt2);
22014 if (isPowerOf2_64(MulAmt1))
22015 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22016 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22018 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22019 DAG.getConstant(MulAmt1, DL, VT));
22021 if (isPowerOf2_64(MulAmt2))
22022 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22023 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22025 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22026 DAG.getConstant(MulAmt2, DL, VT));
22028 // Do not add new nodes to DAG combiner worklist.
22029 DCI.CombineTo(N, NewMul, false);
22034 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22035 SDValue N0 = N->getOperand(0);
22036 SDValue N1 = N->getOperand(1);
22037 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22038 EVT VT = N0.getValueType();
22040 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22041 // since the result of setcc_c is all zero's or all ones.
22042 if (VT.isInteger() && !VT.isVector() &&
22043 N1C && N0.getOpcode() == ISD::AND &&
22044 N0.getOperand(1).getOpcode() == ISD::Constant) {
22045 SDValue N00 = N0.getOperand(0);
22046 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22047 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22048 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22049 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22050 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22051 APInt ShAmt = N1C->getAPIntValue();
22052 Mask = Mask.shl(ShAmt);
22055 return DAG.getNode(ISD::AND, DL, VT,
22056 N00, DAG.getConstant(Mask, DL, VT));
22061 // Hardware support for vector shifts is sparse which makes us scalarize the
22062 // vector operations in many cases. Also, on sandybridge ADD is faster than
22064 // (shl V, 1) -> add V,V
22065 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22066 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22067 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22068 // We shift all of the values by one. In many cases we do not have
22069 // hardware support for this operation. This is better expressed as an ADD
22071 if (N1SplatC->getZExtValue() == 1)
22072 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22078 /// \brief Returns a vector of 0s if the node in input is a vector logical
22079 /// shift by a constant amount which is known to be bigger than or equal
22080 /// to the vector element size in bits.
22081 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22082 const X86Subtarget *Subtarget) {
22083 EVT VT = N->getValueType(0);
22085 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22086 (!Subtarget->hasInt256() ||
22087 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22090 SDValue Amt = N->getOperand(1);
22092 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22093 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22094 APInt ShiftAmt = AmtSplat->getAPIntValue();
22095 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22097 // SSE2/AVX2 logical shifts always return a vector of 0s
22098 // if the shift amount is bigger than or equal to
22099 // the element size. The constant shift amount will be
22100 // encoded as a 8-bit immediate.
22101 if (ShiftAmt.trunc(8).uge(MaxAmount))
22102 return getZeroVector(VT, Subtarget, DAG, DL);
22108 /// PerformShiftCombine - Combine shifts.
22109 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22110 TargetLowering::DAGCombinerInfo &DCI,
22111 const X86Subtarget *Subtarget) {
22112 if (N->getOpcode() == ISD::SHL) {
22113 SDValue V = PerformSHLCombine(N, DAG);
22114 if (V.getNode()) return V;
22117 if (N->getOpcode() != ISD::SRA) {
22118 // Try to fold this logical shift into a zero vector.
22119 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
22120 if (V.getNode()) return V;
22126 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22127 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22128 // and friends. Likewise for OR -> CMPNEQSS.
22129 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22130 TargetLowering::DAGCombinerInfo &DCI,
22131 const X86Subtarget *Subtarget) {
22134 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22135 // we're requiring SSE2 for both.
22136 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22137 SDValue N0 = N->getOperand(0);
22138 SDValue N1 = N->getOperand(1);
22139 SDValue CMP0 = N0->getOperand(1);
22140 SDValue CMP1 = N1->getOperand(1);
22143 // The SETCCs should both refer to the same CMP.
22144 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22147 SDValue CMP00 = CMP0->getOperand(0);
22148 SDValue CMP01 = CMP0->getOperand(1);
22149 EVT VT = CMP00.getValueType();
22151 if (VT == MVT::f32 || VT == MVT::f64) {
22152 bool ExpectingFlags = false;
22153 // Check for any users that want flags:
22154 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22155 !ExpectingFlags && UI != UE; ++UI)
22156 switch (UI->getOpcode()) {
22161 ExpectingFlags = true;
22163 case ISD::CopyToReg:
22164 case ISD::SIGN_EXTEND:
22165 case ISD::ZERO_EXTEND:
22166 case ISD::ANY_EXTEND:
22170 if (!ExpectingFlags) {
22171 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22172 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22174 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22175 X86::CondCode tmp = cc0;
22180 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22181 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22182 // FIXME: need symbolic constants for these magic numbers.
22183 // See X86ATTInstPrinter.cpp:printSSECC().
22184 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22185 if (Subtarget->hasAVX512()) {
22186 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22188 DAG.getConstant(x86cc, DL, MVT::i8));
22189 if (N->getValueType(0) != MVT::i1)
22190 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22194 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22195 CMP00.getValueType(), CMP00, CMP01,
22196 DAG.getConstant(x86cc, DL,
22199 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22200 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22202 if (is64BitFP && !Subtarget->is64Bit()) {
22203 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22204 // 64-bit integer, since that's not a legal type. Since
22205 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22206 // bits, but can do this little dance to extract the lowest 32 bits
22207 // and work with those going forward.
22208 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22210 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22212 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22213 Vector32, DAG.getIntPtrConstant(0, DL));
22217 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
22219 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22220 DAG.getConstant(1, DL, IntVT));
22221 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22223 return OneBitOfTruth;
22231 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22232 /// so it can be folded inside ANDNP.
22233 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22234 EVT VT = N->getValueType(0);
22236 // Match direct AllOnes for 128 and 256-bit vectors
22237 if (ISD::isBuildVectorAllOnes(N))
22240 // Look through a bit convert.
22241 if (N->getOpcode() == ISD::BITCAST)
22242 N = N->getOperand(0).getNode();
22244 // Sometimes the operand may come from a insert_subvector building a 256-bit
22246 if (VT.is256BitVector() &&
22247 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22248 SDValue V1 = N->getOperand(0);
22249 SDValue V2 = N->getOperand(1);
22251 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22252 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22253 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22254 ISD::isBuildVectorAllOnes(V2.getNode()))
22261 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22262 // register. In most cases we actually compare or select YMM-sized registers
22263 // and mixing the two types creates horrible code. This method optimizes
22264 // some of the transition sequences.
22265 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22266 TargetLowering::DAGCombinerInfo &DCI,
22267 const X86Subtarget *Subtarget) {
22268 EVT VT = N->getValueType(0);
22269 if (!VT.is256BitVector())
22272 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22273 N->getOpcode() == ISD::ZERO_EXTEND ||
22274 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22276 SDValue Narrow = N->getOperand(0);
22277 EVT NarrowVT = Narrow->getValueType(0);
22278 if (!NarrowVT.is128BitVector())
22281 if (Narrow->getOpcode() != ISD::XOR &&
22282 Narrow->getOpcode() != ISD::AND &&
22283 Narrow->getOpcode() != ISD::OR)
22286 SDValue N0 = Narrow->getOperand(0);
22287 SDValue N1 = Narrow->getOperand(1);
22290 // The Left side has to be a trunc.
22291 if (N0.getOpcode() != ISD::TRUNCATE)
22294 // The type of the truncated inputs.
22295 EVT WideVT = N0->getOperand(0)->getValueType(0);
22299 // The right side has to be a 'trunc' or a constant vector.
22300 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22301 ConstantSDNode *RHSConstSplat = nullptr;
22302 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22303 RHSConstSplat = RHSBV->getConstantSplatNode();
22304 if (!RHSTrunc && !RHSConstSplat)
22307 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22309 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22312 // Set N0 and N1 to hold the inputs to the new wide operation.
22313 N0 = N0->getOperand(0);
22314 if (RHSConstSplat) {
22315 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22316 SDValue(RHSConstSplat, 0));
22317 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22318 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22319 } else if (RHSTrunc) {
22320 N1 = N1->getOperand(0);
22323 // Generate the wide operation.
22324 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22325 unsigned Opcode = N->getOpcode();
22327 case ISD::ANY_EXTEND:
22329 case ISD::ZERO_EXTEND: {
22330 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22331 APInt Mask = APInt::getAllOnesValue(InBits);
22332 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22333 return DAG.getNode(ISD::AND, DL, VT,
22334 Op, DAG.getConstant(Mask, DL, VT));
22336 case ISD::SIGN_EXTEND:
22337 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22338 Op, DAG.getValueType(NarrowVT));
22340 llvm_unreachable("Unexpected opcode");
22344 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22345 TargetLowering::DAGCombinerInfo &DCI,
22346 const X86Subtarget *Subtarget) {
22347 SDValue N0 = N->getOperand(0);
22348 SDValue N1 = N->getOperand(1);
22351 // A vector zext_in_reg may be represented as a shuffle,
22352 // feeding into a bitcast (this represents anyext) feeding into
22353 // an and with a mask.
22354 // We'd like to try to combine that into a shuffle with zero
22355 // plus a bitcast, removing the and.
22356 if (N0.getOpcode() != ISD::BITCAST ||
22357 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22360 // The other side of the AND should be a splat of 2^C, where C
22361 // is the number of bits in the source type.
22362 if (N1.getOpcode() == ISD::BITCAST)
22363 N1 = N1.getOperand(0);
22364 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22366 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22368 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22369 EVT SrcType = Shuffle->getValueType(0);
22371 // We expect a single-source shuffle
22372 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22375 unsigned SrcSize = SrcType.getScalarSizeInBits();
22377 APInt SplatValue, SplatUndef;
22378 unsigned SplatBitSize;
22380 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22381 SplatBitSize, HasAnyUndefs))
22384 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22385 // Make sure the splat matches the mask we expect
22386 if (SplatBitSize > ResSize ||
22387 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22390 // Make sure the input and output size make sense
22391 if (SrcSize >= ResSize || ResSize % SrcSize)
22394 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22395 // The number of u's between each two values depends on the ratio between
22396 // the source and dest type.
22397 unsigned ZextRatio = ResSize / SrcSize;
22398 bool IsZext = true;
22399 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22400 if (i % ZextRatio) {
22401 if (Shuffle->getMaskElt(i) > 0) {
22407 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22408 // Expected element number
22418 // Ok, perform the transformation - replace the shuffle with
22419 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22420 // (instead of undef) where the k elements come from the zero vector.
22421 SmallVector<int, 8> Mask;
22422 unsigned NumElems = SrcType.getVectorNumElements();
22423 for (unsigned i = 0; i < NumElems; ++i)
22425 Mask.push_back(NumElems);
22427 Mask.push_back(i / ZextRatio);
22429 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22430 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
22431 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22434 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22435 TargetLowering::DAGCombinerInfo &DCI,
22436 const X86Subtarget *Subtarget) {
22437 if (DCI.isBeforeLegalizeOps())
22440 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22443 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22446 EVT VT = N->getValueType(0);
22447 SDValue N0 = N->getOperand(0);
22448 SDValue N1 = N->getOperand(1);
22451 // Create BEXTR instructions
22452 // BEXTR is ((X >> imm) & (2**size-1))
22453 if (VT == MVT::i32 || VT == MVT::i64) {
22454 // Check for BEXTR.
22455 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22456 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22457 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22458 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22459 if (MaskNode && ShiftNode) {
22460 uint64_t Mask = MaskNode->getZExtValue();
22461 uint64_t Shift = ShiftNode->getZExtValue();
22462 if (isMask_64(Mask)) {
22463 uint64_t MaskSize = countPopulation(Mask);
22464 if (Shift + MaskSize <= VT.getSizeInBits())
22465 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22466 DAG.getConstant(Shift | (MaskSize << 8), DL,
22475 // Want to form ANDNP nodes:
22476 // 1) In the hopes of then easily combining them with OR and AND nodes
22477 // to form PBLEND/PSIGN.
22478 // 2) To match ANDN packed intrinsics
22479 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22482 // Check LHS for vnot
22483 if (N0.getOpcode() == ISD::XOR &&
22484 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22485 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22486 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22488 // Check RHS for vnot
22489 if (N1.getOpcode() == ISD::XOR &&
22490 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22491 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22492 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22497 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22498 TargetLowering::DAGCombinerInfo &DCI,
22499 const X86Subtarget *Subtarget) {
22500 if (DCI.isBeforeLegalizeOps())
22503 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22507 SDValue N0 = N->getOperand(0);
22508 SDValue N1 = N->getOperand(1);
22509 EVT VT = N->getValueType(0);
22511 // look for psign/blend
22512 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22513 if (!Subtarget->hasSSSE3() ||
22514 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22517 // Canonicalize pandn to RHS
22518 if (N0.getOpcode() == X86ISD::ANDNP)
22520 // or (and (m, y), (pandn m, x))
22521 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22522 SDValue Mask = N1.getOperand(0);
22523 SDValue X = N1.getOperand(1);
22525 if (N0.getOperand(0) == Mask)
22526 Y = N0.getOperand(1);
22527 if (N0.getOperand(1) == Mask)
22528 Y = N0.getOperand(0);
22530 // Check to see if the mask appeared in both the AND and ANDNP and
22534 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22535 // Look through mask bitcast.
22536 if (Mask.getOpcode() == ISD::BITCAST)
22537 Mask = Mask.getOperand(0);
22538 if (X.getOpcode() == ISD::BITCAST)
22539 X = X.getOperand(0);
22540 if (Y.getOpcode() == ISD::BITCAST)
22541 Y = Y.getOperand(0);
22543 EVT MaskVT = Mask.getValueType();
22545 // Validate that the Mask operand is a vector sra node.
22546 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22547 // there is no psrai.b
22548 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22549 unsigned SraAmt = ~0;
22550 if (Mask.getOpcode() == ISD::SRA) {
22551 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22552 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22553 SraAmt = AmtConst->getZExtValue();
22554 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22555 SDValue SraC = Mask.getOperand(1);
22556 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22558 if ((SraAmt + 1) != EltBits)
22563 // Now we know we at least have a plendvb with the mask val. See if
22564 // we can form a psignb/w/d.
22565 // psign = x.type == y.type == mask.type && y = sub(0, x);
22566 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22567 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22568 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22569 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22570 "Unsupported VT for PSIGN");
22571 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22572 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22574 // PBLENDVB only available on SSE 4.1
22575 if (!Subtarget->hasSSE41())
22578 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22580 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22581 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22582 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22583 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22584 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22588 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22591 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22592 MachineFunction &MF = DAG.getMachineFunction();
22594 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22596 // SHLD/SHRD instructions have lower register pressure, but on some
22597 // platforms they have higher latency than the equivalent
22598 // series of shifts/or that would otherwise be generated.
22599 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22600 // have higher latencies and we are not optimizing for size.
22601 if (!OptForSize && Subtarget->isSHLDSlow())
22604 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22606 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22608 if (!N0.hasOneUse() || !N1.hasOneUse())
22611 SDValue ShAmt0 = N0.getOperand(1);
22612 if (ShAmt0.getValueType() != MVT::i8)
22614 SDValue ShAmt1 = N1.getOperand(1);
22615 if (ShAmt1.getValueType() != MVT::i8)
22617 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22618 ShAmt0 = ShAmt0.getOperand(0);
22619 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22620 ShAmt1 = ShAmt1.getOperand(0);
22623 unsigned Opc = X86ISD::SHLD;
22624 SDValue Op0 = N0.getOperand(0);
22625 SDValue Op1 = N1.getOperand(0);
22626 if (ShAmt0.getOpcode() == ISD::SUB) {
22627 Opc = X86ISD::SHRD;
22628 std::swap(Op0, Op1);
22629 std::swap(ShAmt0, ShAmt1);
22632 unsigned Bits = VT.getSizeInBits();
22633 if (ShAmt1.getOpcode() == ISD::SUB) {
22634 SDValue Sum = ShAmt1.getOperand(0);
22635 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22636 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22637 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22638 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22639 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22640 return DAG.getNode(Opc, DL, VT,
22642 DAG.getNode(ISD::TRUNCATE, DL,
22645 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22646 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22648 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22649 return DAG.getNode(Opc, DL, VT,
22650 N0.getOperand(0), N1.getOperand(0),
22651 DAG.getNode(ISD::TRUNCATE, DL,
22658 // Generate NEG and CMOV for integer abs.
22659 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22660 EVT VT = N->getValueType(0);
22662 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22663 // 8-bit integer abs to NEG and CMOV.
22664 if (VT.isInteger() && VT.getSizeInBits() == 8)
22667 SDValue N0 = N->getOperand(0);
22668 SDValue N1 = N->getOperand(1);
22671 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22672 // and change it to SUB and CMOV.
22673 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22674 N0.getOpcode() == ISD::ADD &&
22675 N0.getOperand(1) == N1 &&
22676 N1.getOpcode() == ISD::SRA &&
22677 N1.getOperand(0) == N0.getOperand(0))
22678 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22679 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22680 // Generate SUB & CMOV.
22681 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22682 DAG.getConstant(0, DL, VT), N0.getOperand(0));
22684 SDValue Ops[] = { N0.getOperand(0), Neg,
22685 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
22686 SDValue(Neg.getNode(), 1) };
22687 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22692 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22693 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22694 TargetLowering::DAGCombinerInfo &DCI,
22695 const X86Subtarget *Subtarget) {
22696 if (DCI.isBeforeLegalizeOps())
22699 if (Subtarget->hasCMov()) {
22700 SDValue RV = performIntegerAbsCombine(N, DAG);
22708 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22709 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22710 TargetLowering::DAGCombinerInfo &DCI,
22711 const X86Subtarget *Subtarget) {
22712 LoadSDNode *Ld = cast<LoadSDNode>(N);
22713 EVT RegVT = Ld->getValueType(0);
22714 EVT MemVT = Ld->getMemoryVT();
22716 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22718 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
22719 // into two 16-byte operations.
22720 ISD::LoadExtType Ext = Ld->getExtensionType();
22721 unsigned Alignment = Ld->getAlignment();
22722 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22723 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22724 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22725 unsigned NumElems = RegVT.getVectorNumElements();
22729 SDValue Ptr = Ld->getBasePtr();
22730 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
22732 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22734 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22735 Ld->getPointerInfo(), Ld->isVolatile(),
22736 Ld->isNonTemporal(), Ld->isInvariant(),
22738 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22739 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22740 Ld->getPointerInfo(), Ld->isVolatile(),
22741 Ld->isNonTemporal(), Ld->isInvariant(),
22742 std::min(16U, Alignment));
22743 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22745 Load2.getValue(1));
22747 SDValue NewVec = DAG.getUNDEF(RegVT);
22748 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22749 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22750 return DCI.CombineTo(N, NewVec, TF, true);
22756 /// PerformMLOADCombine - Resolve extending loads
22757 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22758 TargetLowering::DAGCombinerInfo &DCI,
22759 const X86Subtarget *Subtarget) {
22760 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22761 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22764 EVT VT = Mld->getValueType(0);
22765 unsigned NumElems = VT.getVectorNumElements();
22766 EVT LdVT = Mld->getMemoryVT();
22769 assert(LdVT != VT && "Cannot extend to the same type");
22770 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22771 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22772 // From, To sizes and ElemCount must be pow of two
22773 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22774 "Unexpected size for extending masked load");
22776 unsigned SizeRatio = ToSz / FromSz;
22777 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22779 // Create a type on which we perform the shuffle
22780 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22781 LdVT.getScalarType(), NumElems*SizeRatio);
22782 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22784 // Convert Src0 value
22785 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22786 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22787 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22788 for (unsigned i = 0; i != NumElems; ++i)
22789 ShuffleVec[i] = i * SizeRatio;
22791 // Can't shuffle using an illegal type.
22792 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22793 && "WideVecVT should be legal");
22794 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22795 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22797 // Prepare the new mask
22799 SDValue Mask = Mld->getMask();
22800 if (Mask.getValueType() == VT) {
22801 // Mask and original value have the same type
22802 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22803 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22804 for (unsigned i = 0; i != NumElems; ++i)
22805 ShuffleVec[i] = i * SizeRatio;
22806 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22807 ShuffleVec[i] = NumElems*SizeRatio;
22808 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22809 DAG.getConstant(0, dl, WideVecVT),
22813 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22814 unsigned WidenNumElts = NumElems*SizeRatio;
22815 unsigned MaskNumElts = VT.getVectorNumElements();
22816 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22819 unsigned NumConcat = WidenNumElts / MaskNumElts;
22820 SmallVector<SDValue, 16> Ops(NumConcat);
22821 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
22823 for (unsigned i = 1; i != NumConcat; ++i)
22826 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22829 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22830 Mld->getBasePtr(), NewMask, WideSrc0,
22831 Mld->getMemoryVT(), Mld->getMemOperand(),
22833 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22834 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22837 /// PerformMSTORECombine - Resolve truncating stores
22838 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22839 const X86Subtarget *Subtarget) {
22840 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22841 if (!Mst->isTruncatingStore())
22844 EVT VT = Mst->getValue().getValueType();
22845 unsigned NumElems = VT.getVectorNumElements();
22846 EVT StVT = Mst->getMemoryVT();
22849 assert(StVT != VT && "Cannot truncate to the same type");
22850 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22851 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22853 // From, To sizes and ElemCount must be pow of two
22854 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22855 "Unexpected size for truncating masked store");
22856 // We are going to use the original vector elt for storing.
22857 // Accumulated smaller vector elements must be a multiple of the store size.
22858 assert (((NumElems * FromSz) % ToSz) == 0 &&
22859 "Unexpected ratio for truncating masked store");
22861 unsigned SizeRatio = FromSz / ToSz;
22862 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22864 // Create a type on which we perform the shuffle
22865 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22866 StVT.getScalarType(), NumElems*SizeRatio);
22868 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22870 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
22871 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22872 for (unsigned i = 0; i != NumElems; ++i)
22873 ShuffleVec[i] = i * SizeRatio;
22875 // Can't shuffle using an illegal type.
22876 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22877 && "WideVecVT should be legal");
22879 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22880 DAG.getUNDEF(WideVecVT),
22884 SDValue Mask = Mst->getMask();
22885 if (Mask.getValueType() == VT) {
22886 // Mask and original value have the same type
22887 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22888 for (unsigned i = 0; i != NumElems; ++i)
22889 ShuffleVec[i] = i * SizeRatio;
22890 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22891 ShuffleVec[i] = NumElems*SizeRatio;
22892 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22893 DAG.getConstant(0, dl, WideVecVT),
22897 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22898 unsigned WidenNumElts = NumElems*SizeRatio;
22899 unsigned MaskNumElts = VT.getVectorNumElements();
22900 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22903 unsigned NumConcat = WidenNumElts / MaskNumElts;
22904 SmallVector<SDValue, 16> Ops(NumConcat);
22905 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
22907 for (unsigned i = 1; i != NumConcat; ++i)
22910 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22913 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
22914 NewMask, StVT, Mst->getMemOperand(), false);
22916 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22917 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22918 const X86Subtarget *Subtarget) {
22919 StoreSDNode *St = cast<StoreSDNode>(N);
22920 EVT VT = St->getValue().getValueType();
22921 EVT StVT = St->getMemoryVT();
22923 SDValue StoredVal = St->getOperand(1);
22924 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22926 // If we are saving a concatenation of two XMM registers and 32-byte stores
22927 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
22928 unsigned Alignment = St->getAlignment();
22929 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22930 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22931 StVT == VT && !IsAligned) {
22932 unsigned NumElems = VT.getVectorNumElements();
22936 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22937 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22939 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
22940 SDValue Ptr0 = St->getBasePtr();
22941 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22943 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22944 St->getPointerInfo(), St->isVolatile(),
22945 St->isNonTemporal(), Alignment);
22946 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22947 St->getPointerInfo(), St->isVolatile(),
22948 St->isNonTemporal(),
22949 std::min(16U, Alignment));
22950 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22953 // Optimize trunc store (of multiple scalars) to shuffle and store.
22954 // First, pack all of the elements in one place. Next, store to memory
22955 // in fewer chunks.
22956 if (St->isTruncatingStore() && VT.isVector()) {
22957 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22958 unsigned NumElems = VT.getVectorNumElements();
22959 assert(StVT != VT && "Cannot truncate to the same type");
22960 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22961 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22963 // From, To sizes and ElemCount must be pow of two
22964 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22965 // We are going to use the original vector elt for storing.
22966 // Accumulated smaller vector elements must be a multiple of the store size.
22967 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22969 unsigned SizeRatio = FromSz / ToSz;
22971 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22973 // Create a type on which we perform the shuffle
22974 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22975 StVT.getScalarType(), NumElems*SizeRatio);
22977 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22979 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22980 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22981 for (unsigned i = 0; i != NumElems; ++i)
22982 ShuffleVec[i] = i * SizeRatio;
22984 // Can't shuffle using an illegal type.
22985 if (!TLI.isTypeLegal(WideVecVT))
22988 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22989 DAG.getUNDEF(WideVecVT),
22991 // At this point all of the data is stored at the bottom of the
22992 // register. We now need to save it to mem.
22994 // Find the largest store unit
22995 MVT StoreType = MVT::i8;
22996 for (MVT Tp : MVT::integer_valuetypes()) {
22997 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23001 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23002 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23003 (64 <= NumElems * ToSz))
23004 StoreType = MVT::f64;
23006 // Bitcast the original vector into a vector of store-size units
23007 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23008 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23009 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23010 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23011 SmallVector<SDValue, 8> Chains;
23012 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23013 TLI.getPointerTy());
23014 SDValue Ptr = St->getBasePtr();
23016 // Perform one or more big stores into memory.
23017 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23018 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23019 StoreType, ShuffWide,
23020 DAG.getIntPtrConstant(i, dl));
23021 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23022 St->getPointerInfo(), St->isVolatile(),
23023 St->isNonTemporal(), St->getAlignment());
23024 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23025 Chains.push_back(Ch);
23028 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23031 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23032 // the FP state in cases where an emms may be missing.
23033 // A preferable solution to the general problem is to figure out the right
23034 // places to insert EMMS. This qualifies as a quick hack.
23036 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23037 if (VT.getSizeInBits() != 64)
23040 const Function *F = DAG.getMachineFunction().getFunction();
23041 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23042 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23043 && Subtarget->hasSSE2();
23044 if ((VT.isVector() ||
23045 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23046 isa<LoadSDNode>(St->getValue()) &&
23047 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23048 St->getChain().hasOneUse() && !St->isVolatile()) {
23049 SDNode* LdVal = St->getValue().getNode();
23050 LoadSDNode *Ld = nullptr;
23051 int TokenFactorIndex = -1;
23052 SmallVector<SDValue, 8> Ops;
23053 SDNode* ChainVal = St->getChain().getNode();
23054 // Must be a store of a load. We currently handle two cases: the load
23055 // is a direct child, and it's under an intervening TokenFactor. It is
23056 // possible to dig deeper under nested TokenFactors.
23057 if (ChainVal == LdVal)
23058 Ld = cast<LoadSDNode>(St->getChain());
23059 else if (St->getValue().hasOneUse() &&
23060 ChainVal->getOpcode() == ISD::TokenFactor) {
23061 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23062 if (ChainVal->getOperand(i).getNode() == LdVal) {
23063 TokenFactorIndex = i;
23064 Ld = cast<LoadSDNode>(St->getValue());
23066 Ops.push_back(ChainVal->getOperand(i));
23070 if (!Ld || !ISD::isNormalLoad(Ld))
23073 // If this is not the MMX case, i.e. we are just turning i64 load/store
23074 // into f64 load/store, avoid the transformation if there are multiple
23075 // uses of the loaded value.
23076 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23081 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23082 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23084 if (Subtarget->is64Bit() || F64IsLegal) {
23085 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23086 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23087 Ld->getPointerInfo(), Ld->isVolatile(),
23088 Ld->isNonTemporal(), Ld->isInvariant(),
23089 Ld->getAlignment());
23090 SDValue NewChain = NewLd.getValue(1);
23091 if (TokenFactorIndex != -1) {
23092 Ops.push_back(NewChain);
23093 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23095 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23096 St->getPointerInfo(),
23097 St->isVolatile(), St->isNonTemporal(),
23098 St->getAlignment());
23101 // Otherwise, lower to two pairs of 32-bit loads / stores.
23102 SDValue LoAddr = Ld->getBasePtr();
23103 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23104 DAG.getConstant(4, LdDL, MVT::i32));
23106 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23107 Ld->getPointerInfo(),
23108 Ld->isVolatile(), Ld->isNonTemporal(),
23109 Ld->isInvariant(), Ld->getAlignment());
23110 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23111 Ld->getPointerInfo().getWithOffset(4),
23112 Ld->isVolatile(), Ld->isNonTemporal(),
23114 MinAlign(Ld->getAlignment(), 4));
23116 SDValue NewChain = LoLd.getValue(1);
23117 if (TokenFactorIndex != -1) {
23118 Ops.push_back(LoLd);
23119 Ops.push_back(HiLd);
23120 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23123 LoAddr = St->getBasePtr();
23124 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23125 DAG.getConstant(4, StDL, MVT::i32));
23127 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23128 St->getPointerInfo(),
23129 St->isVolatile(), St->isNonTemporal(),
23130 St->getAlignment());
23131 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23132 St->getPointerInfo().getWithOffset(4),
23134 St->isNonTemporal(),
23135 MinAlign(St->getAlignment(), 4));
23136 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23139 // This is similar to the above case, but here we handle a scalar 64-bit
23140 // integer store that is extracted from a vector on a 32-bit target.
23141 // If we have SSE2, then we can treat it like a floating-point double
23142 // to get past legalization. The execution dependencies fixup pass will
23143 // choose the optimal machine instruction for the store if this really is
23144 // an integer or v2f32 rather than an f64.
23145 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23146 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23147 SDValue OldExtract = St->getOperand(1);
23148 SDValue ExtOp0 = OldExtract.getOperand(0);
23149 unsigned VecSize = ExtOp0.getValueSizeInBits();
23150 MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64);
23151 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
23152 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23153 BitCast, OldExtract.getOperand(1));
23154 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23155 St->getPointerInfo(), St->isVolatile(),
23156 St->isNonTemporal(), St->getAlignment());
23162 /// Return 'true' if this vector operation is "horizontal"
23163 /// and return the operands for the horizontal operation in LHS and RHS. A
23164 /// horizontal operation performs the binary operation on successive elements
23165 /// of its first operand, then on successive elements of its second operand,
23166 /// returning the resulting values in a vector. For example, if
23167 /// A = < float a0, float a1, float a2, float a3 >
23169 /// B = < float b0, float b1, float b2, float b3 >
23170 /// then the result of doing a horizontal operation on A and B is
23171 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23172 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23173 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23174 /// set to A, RHS to B, and the routine returns 'true'.
23175 /// Note that the binary operation should have the property that if one of the
23176 /// operands is UNDEF then the result is UNDEF.
23177 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23178 // Look for the following pattern: if
23179 // A = < float a0, float a1, float a2, float a3 >
23180 // B = < float b0, float b1, float b2, float b3 >
23182 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23183 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23184 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23185 // which is A horizontal-op B.
23187 // At least one of the operands should be a vector shuffle.
23188 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23189 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23192 MVT VT = LHS.getSimpleValueType();
23194 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23195 "Unsupported vector type for horizontal add/sub");
23197 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23198 // operate independently on 128-bit lanes.
23199 unsigned NumElts = VT.getVectorNumElements();
23200 unsigned NumLanes = VT.getSizeInBits()/128;
23201 unsigned NumLaneElts = NumElts / NumLanes;
23202 assert((NumLaneElts % 2 == 0) &&
23203 "Vector type should have an even number of elements in each lane");
23204 unsigned HalfLaneElts = NumLaneElts/2;
23206 // View LHS in the form
23207 // LHS = VECTOR_SHUFFLE A, B, LMask
23208 // If LHS is not a shuffle then pretend it is the shuffle
23209 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23210 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23213 SmallVector<int, 16> LMask(NumElts);
23214 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23215 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23216 A = LHS.getOperand(0);
23217 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23218 B = LHS.getOperand(1);
23219 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23220 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23222 if (LHS.getOpcode() != ISD::UNDEF)
23224 for (unsigned i = 0; i != NumElts; ++i)
23228 // Likewise, view RHS in the form
23229 // RHS = VECTOR_SHUFFLE C, D, RMask
23231 SmallVector<int, 16> RMask(NumElts);
23232 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23233 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23234 C = RHS.getOperand(0);
23235 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23236 D = RHS.getOperand(1);
23237 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23238 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23240 if (RHS.getOpcode() != ISD::UNDEF)
23242 for (unsigned i = 0; i != NumElts; ++i)
23246 // Check that the shuffles are both shuffling the same vectors.
23247 if (!(A == C && B == D) && !(A == D && B == C))
23250 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23251 if (!A.getNode() && !B.getNode())
23254 // If A and B occur in reverse order in RHS, then "swap" them (which means
23255 // rewriting the mask).
23257 ShuffleVectorSDNode::commuteMask(RMask);
23259 // At this point LHS and RHS are equivalent to
23260 // LHS = VECTOR_SHUFFLE A, B, LMask
23261 // RHS = VECTOR_SHUFFLE A, B, RMask
23262 // Check that the masks correspond to performing a horizontal operation.
23263 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23264 for (unsigned i = 0; i != NumLaneElts; ++i) {
23265 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23267 // Ignore any UNDEF components.
23268 if (LIdx < 0 || RIdx < 0 ||
23269 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23270 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23273 // Check that successive elements are being operated on. If not, this is
23274 // not a horizontal operation.
23275 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23276 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23277 if (!(LIdx == Index && RIdx == Index + 1) &&
23278 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23283 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23284 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23288 /// Do target-specific dag combines on floating point adds.
23289 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23290 const X86Subtarget *Subtarget) {
23291 EVT VT = N->getValueType(0);
23292 SDValue LHS = N->getOperand(0);
23293 SDValue RHS = N->getOperand(1);
23295 // Try to synthesize horizontal adds from adds of shuffles.
23296 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23297 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23298 isHorizontalBinOp(LHS, RHS, true))
23299 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23303 /// Do target-specific dag combines on floating point subs.
23304 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23305 const X86Subtarget *Subtarget) {
23306 EVT VT = N->getValueType(0);
23307 SDValue LHS = N->getOperand(0);
23308 SDValue RHS = N->getOperand(1);
23310 // Try to synthesize horizontal subs from subs of shuffles.
23311 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23312 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23313 isHorizontalBinOp(LHS, RHS, false))
23314 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23318 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23319 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23320 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23322 // F[X]OR(0.0, x) -> x
23323 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23324 if (C->getValueAPF().isPosZero())
23325 return N->getOperand(1);
23327 // F[X]OR(x, 0.0) -> x
23328 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23329 if (C->getValueAPF().isPosZero())
23330 return N->getOperand(0);
23334 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23335 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23336 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23338 // Only perform optimizations if UnsafeMath is used.
23339 if (!DAG.getTarget().Options.UnsafeFPMath)
23342 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23343 // into FMINC and FMAXC, which are Commutative operations.
23344 unsigned NewOp = 0;
23345 switch (N->getOpcode()) {
23346 default: llvm_unreachable("unknown opcode");
23347 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23348 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23351 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23352 N->getOperand(0), N->getOperand(1));
23355 /// Do target-specific dag combines on X86ISD::FAND nodes.
23356 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23357 // FAND(0.0, x) -> 0.0
23358 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23359 if (C->getValueAPF().isPosZero())
23360 return N->getOperand(0);
23362 // FAND(x, 0.0) -> 0.0
23363 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23364 if (C->getValueAPF().isPosZero())
23365 return N->getOperand(1);
23370 /// Do target-specific dag combines on X86ISD::FANDN nodes
23371 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23372 // FANDN(0.0, x) -> x
23373 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23374 if (C->getValueAPF().isPosZero())
23375 return N->getOperand(1);
23377 // FANDN(x, 0.0) -> 0.0
23378 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23379 if (C->getValueAPF().isPosZero())
23380 return N->getOperand(1);
23385 static SDValue PerformBTCombine(SDNode *N,
23387 TargetLowering::DAGCombinerInfo &DCI) {
23388 // BT ignores high bits in the bit index operand.
23389 SDValue Op1 = N->getOperand(1);
23390 if (Op1.hasOneUse()) {
23391 unsigned BitWidth = Op1.getValueSizeInBits();
23392 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23393 APInt KnownZero, KnownOne;
23394 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23395 !DCI.isBeforeLegalizeOps());
23396 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23397 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23398 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23399 DCI.CommitTargetLoweringOpt(TLO);
23404 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23405 SDValue Op = N->getOperand(0);
23406 if (Op.getOpcode() == ISD::BITCAST)
23407 Op = Op.getOperand(0);
23408 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23409 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23410 VT.getVectorElementType().getSizeInBits() ==
23411 OpVT.getVectorElementType().getSizeInBits()) {
23412 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23417 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23418 const X86Subtarget *Subtarget) {
23419 EVT VT = N->getValueType(0);
23420 if (!VT.isVector())
23423 SDValue N0 = N->getOperand(0);
23424 SDValue N1 = N->getOperand(1);
23425 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23428 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23429 // both SSE and AVX2 since there is no sign-extended shift right
23430 // operation on a vector with 64-bit elements.
23431 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23432 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23433 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23434 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23435 SDValue N00 = N0.getOperand(0);
23437 // EXTLOAD has a better solution on AVX2,
23438 // it may be replaced with X86ISD::VSEXT node.
23439 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23440 if (!ISD::isNormalLoad(N00.getNode()))
23443 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23444 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23446 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23452 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23453 TargetLowering::DAGCombinerInfo &DCI,
23454 const X86Subtarget *Subtarget) {
23455 SDValue N0 = N->getOperand(0);
23456 EVT VT = N->getValueType(0);
23458 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23459 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23460 // This exposes the sext to the sdivrem lowering, so that it directly extends
23461 // from AH (which we otherwise need to do contortions to access).
23462 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23463 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
23465 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23466 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
23467 N0.getOperand(0), N0.getOperand(1));
23468 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23469 return R.getValue(1);
23472 if (!DCI.isBeforeLegalizeOps())
23475 if (!Subtarget->hasFp256())
23478 if (VT.isVector() && VT.getSizeInBits() == 256) {
23479 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23487 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23488 const X86Subtarget* Subtarget) {
23490 EVT VT = N->getValueType(0);
23492 // Let legalize expand this if it isn't a legal type yet.
23493 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23496 EVT ScalarVT = VT.getScalarType();
23497 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23498 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23501 SDValue A = N->getOperand(0);
23502 SDValue B = N->getOperand(1);
23503 SDValue C = N->getOperand(2);
23505 bool NegA = (A.getOpcode() == ISD::FNEG);
23506 bool NegB = (B.getOpcode() == ISD::FNEG);
23507 bool NegC = (C.getOpcode() == ISD::FNEG);
23509 // Negative multiplication when NegA xor NegB
23510 bool NegMul = (NegA != NegB);
23512 A = A.getOperand(0);
23514 B = B.getOperand(0);
23516 C = C.getOperand(0);
23520 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23522 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23524 return DAG.getNode(Opcode, dl, VT, A, B, C);
23527 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23528 TargetLowering::DAGCombinerInfo &DCI,
23529 const X86Subtarget *Subtarget) {
23530 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23531 // (and (i32 x86isd::setcc_carry), 1)
23532 // This eliminates the zext. This transformation is necessary because
23533 // ISD::SETCC is always legalized to i8.
23535 SDValue N0 = N->getOperand(0);
23536 EVT VT = N->getValueType(0);
23538 if (N0.getOpcode() == ISD::AND &&
23540 N0.getOperand(0).hasOneUse()) {
23541 SDValue N00 = N0.getOperand(0);
23542 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23543 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23544 if (!C || C->getZExtValue() != 1)
23546 return DAG.getNode(ISD::AND, dl, VT,
23547 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23548 N00.getOperand(0), N00.getOperand(1)),
23549 DAG.getConstant(1, dl, VT));
23553 if (N0.getOpcode() == ISD::TRUNCATE &&
23555 N0.getOperand(0).hasOneUse()) {
23556 SDValue N00 = N0.getOperand(0);
23557 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23558 return DAG.getNode(ISD::AND, dl, VT,
23559 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23560 N00.getOperand(0), N00.getOperand(1)),
23561 DAG.getConstant(1, dl, VT));
23564 if (VT.is256BitVector()) {
23565 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23570 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23571 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23572 // This exposes the zext to the udivrem lowering, so that it directly extends
23573 // from AH (which we otherwise need to do contortions to access).
23574 if (N0.getOpcode() == ISD::UDIVREM &&
23575 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23576 (VT == MVT::i32 || VT == MVT::i64)) {
23577 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23578 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23579 N0.getOperand(0), N0.getOperand(1));
23580 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23581 return R.getValue(1);
23587 // Optimize x == -y --> x+y == 0
23588 // x != -y --> x+y != 0
23589 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23590 const X86Subtarget* Subtarget) {
23591 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23592 SDValue LHS = N->getOperand(0);
23593 SDValue RHS = N->getOperand(1);
23594 EVT VT = N->getValueType(0);
23597 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23598 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23599 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23600 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
23601 LHS.getOperand(1));
23602 return DAG.getSetCC(DL, N->getValueType(0), addV,
23603 DAG.getConstant(0, DL, addV.getValueType()), CC);
23605 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23606 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23607 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23608 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
23609 RHS.getOperand(1));
23610 return DAG.getSetCC(DL, N->getValueType(0), addV,
23611 DAG.getConstant(0, DL, addV.getValueType()), CC);
23614 if (VT.getScalarType() == MVT::i1 &&
23615 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
23617 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23618 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23619 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23621 if (!IsSEXT0 || !IsVZero1) {
23622 // Swap the operands and update the condition code.
23623 std::swap(LHS, RHS);
23624 CC = ISD::getSetCCSwappedOperands(CC);
23626 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23627 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23628 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23631 if (IsSEXT0 && IsVZero1) {
23632 assert(VT == LHS.getOperand(0).getValueType() &&
23633 "Uexpected operand type");
23634 if (CC == ISD::SETGT)
23635 return DAG.getConstant(0, DL, VT);
23636 if (CC == ISD::SETLE)
23637 return DAG.getConstant(1, DL, VT);
23638 if (CC == ISD::SETEQ || CC == ISD::SETGE)
23639 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23641 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
23642 "Unexpected condition code!");
23643 return LHS.getOperand(0);
23650 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
23651 SelectionDAG &DAG) {
23653 MVT VT = Load->getSimpleValueType(0);
23654 MVT EVT = VT.getVectorElementType();
23655 SDValue Addr = Load->getOperand(1);
23656 SDValue NewAddr = DAG.getNode(
23657 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
23658 DAG.getConstant(Index * EVT.getStoreSize(), dl,
23659 Addr.getSimpleValueType()));
23662 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
23663 DAG.getMachineFunction().getMachineMemOperand(
23664 Load->getMemOperand(), 0, EVT.getStoreSize()));
23668 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23669 const X86Subtarget *Subtarget) {
23671 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23672 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23673 "X86insertps is only defined for v4x32");
23675 SDValue Ld = N->getOperand(1);
23676 if (MayFoldLoad(Ld)) {
23677 // Extract the countS bits from the immediate so we can get the proper
23678 // address when narrowing the vector load to a specific element.
23679 // When the second source op is a memory address, insertps doesn't use
23680 // countS and just gets an f32 from that address.
23681 unsigned DestIndex =
23682 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23684 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23686 // Create this as a scalar to vector to match the instruction pattern.
23687 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23688 // countS bits are ignored when loading from memory on insertps, which
23689 // means we don't need to explicitly set them to 0.
23690 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23691 LoadScalarToVector, N->getOperand(2));
23696 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
23697 SDValue V0 = N->getOperand(0);
23698 SDValue V1 = N->getOperand(1);
23700 EVT VT = N->getValueType(0);
23702 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23703 // operands and changing the mask to 1. This saves us a bunch of
23704 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23705 // x86InstrInfo knows how to commute this back after instruction selection
23706 // if it would help register allocation.
23708 // TODO: If optimizing for size or a processor that doesn't suffer from
23709 // partial register update stalls, this should be transformed into a MOVSD
23710 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23712 if (VT == MVT::v2f64)
23713 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23714 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23715 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
23716 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23722 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23723 // as "sbb reg,reg", since it can be extended without zext and produces
23724 // an all-ones bit which is more useful than 0/1 in some cases.
23725 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23728 return DAG.getNode(ISD::AND, DL, VT,
23729 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23730 DAG.getConstant(X86::COND_B, DL, MVT::i8),
23732 DAG.getConstant(1, DL, VT));
23733 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23734 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23735 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23736 DAG.getConstant(X86::COND_B, DL, MVT::i8),
23740 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23741 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23742 TargetLowering::DAGCombinerInfo &DCI,
23743 const X86Subtarget *Subtarget) {
23745 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23746 SDValue EFLAGS = N->getOperand(1);
23748 if (CC == X86::COND_A) {
23749 // Try to convert COND_A into COND_B in an attempt to facilitate
23750 // materializing "setb reg".
23752 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23753 // cannot take an immediate as its first operand.
23755 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23756 EFLAGS.getValueType().isInteger() &&
23757 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23758 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23759 EFLAGS.getNode()->getVTList(),
23760 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23761 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23762 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23766 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23767 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23769 if (CC == X86::COND_B)
23770 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23774 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23775 if (Flags.getNode()) {
23776 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
23777 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23783 // Optimize branch condition evaluation.
23785 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23786 TargetLowering::DAGCombinerInfo &DCI,
23787 const X86Subtarget *Subtarget) {
23789 SDValue Chain = N->getOperand(0);
23790 SDValue Dest = N->getOperand(1);
23791 SDValue EFLAGS = N->getOperand(3);
23792 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23796 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23797 if (Flags.getNode()) {
23798 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
23799 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23806 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23807 SelectionDAG &DAG) {
23808 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23809 // optimize away operation when it's from a constant.
23811 // The general transformation is:
23812 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23813 // AND(VECTOR_CMP(x,y), constant2)
23814 // constant2 = UNARYOP(constant)
23816 // Early exit if this isn't a vector operation, the operand of the
23817 // unary operation isn't a bitwise AND, or if the sizes of the operations
23818 // aren't the same.
23819 EVT VT = N->getValueType(0);
23820 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23821 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23822 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23825 // Now check that the other operand of the AND is a constant. We could
23826 // make the transformation for non-constant splats as well, but it's unclear
23827 // that would be a benefit as it would not eliminate any operations, just
23828 // perform one more step in scalar code before moving to the vector unit.
23829 if (BuildVectorSDNode *BV =
23830 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23831 // Bail out if the vector isn't a constant.
23832 if (!BV->isConstant())
23835 // Everything checks out. Build up the new and improved node.
23837 EVT IntVT = BV->getValueType(0);
23838 // Create a new constant of the appropriate type for the transformed
23840 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23841 // The AND node needs bitcasts to/from an integer vector type around it.
23842 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23843 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23844 N->getOperand(0)->getOperand(0), MaskConst);
23845 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23852 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23853 const X86Subtarget *Subtarget) {
23854 // First try to optimize away the conversion entirely when it's
23855 // conditionally from a constant. Vectors only.
23856 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23857 if (Res != SDValue())
23860 // Now move on to more general possibilities.
23861 SDValue Op0 = N->getOperand(0);
23862 EVT InVT = Op0->getValueType(0);
23864 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23865 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23867 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23868 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23869 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23872 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23873 // a 32-bit target where SSE doesn't support i64->FP operations.
23874 if (Op0.getOpcode() == ISD::LOAD) {
23875 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23876 EVT VT = Ld->getValueType(0);
23877 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23878 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23879 !Subtarget->is64Bit() && VT == MVT::i64) {
23880 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
23881 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
23882 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23889 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23890 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23891 X86TargetLowering::DAGCombinerInfo &DCI) {
23892 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23893 // the result is either zero or one (depending on the input carry bit).
23894 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23895 if (X86::isZeroNode(N->getOperand(0)) &&
23896 X86::isZeroNode(N->getOperand(1)) &&
23897 // We don't have a good way to replace an EFLAGS use, so only do this when
23899 SDValue(N, 1).use_empty()) {
23901 EVT VT = N->getValueType(0);
23902 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
23903 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23904 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23905 DAG.getConstant(X86::COND_B, DL,
23908 DAG.getConstant(1, DL, VT));
23909 return DCI.CombineTo(N, Res1, CarryOut);
23915 // fold (add Y, (sete X, 0)) -> adc 0, Y
23916 // (add Y, (setne X, 0)) -> sbb -1, Y
23917 // (sub (sete X, 0), Y) -> sbb 0, Y
23918 // (sub (setne X, 0), Y) -> adc -1, Y
23919 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23922 // Look through ZExts.
23923 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23924 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23927 SDValue SetCC = Ext.getOperand(0);
23928 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23931 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23932 if (CC != X86::COND_E && CC != X86::COND_NE)
23935 SDValue Cmp = SetCC.getOperand(1);
23936 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23937 !X86::isZeroNode(Cmp.getOperand(1)) ||
23938 !Cmp.getOperand(0).getValueType().isInteger())
23941 SDValue CmpOp0 = Cmp.getOperand(0);
23942 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23943 DAG.getConstant(1, DL, CmpOp0.getValueType()));
23945 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23946 if (CC == X86::COND_NE)
23947 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23948 DL, OtherVal.getValueType(), OtherVal,
23949 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
23951 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23952 DL, OtherVal.getValueType(), OtherVal,
23953 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
23956 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23957 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23958 const X86Subtarget *Subtarget) {
23959 EVT VT = N->getValueType(0);
23960 SDValue Op0 = N->getOperand(0);
23961 SDValue Op1 = N->getOperand(1);
23963 // Try to synthesize horizontal adds from adds of shuffles.
23964 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23965 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23966 isHorizontalBinOp(Op0, Op1, true))
23967 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23969 return OptimizeConditionalInDecrement(N, DAG);
23972 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23973 const X86Subtarget *Subtarget) {
23974 SDValue Op0 = N->getOperand(0);
23975 SDValue Op1 = N->getOperand(1);
23977 // X86 can't encode an immediate LHS of a sub. See if we can push the
23978 // negation into a preceding instruction.
23979 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23980 // If the RHS of the sub is a XOR with one use and a constant, invert the
23981 // immediate. Then add one to the LHS of the sub so we can turn
23982 // X-Y -> X+~Y+1, saving one register.
23983 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23984 isa<ConstantSDNode>(Op1.getOperand(1))) {
23985 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23986 EVT VT = Op0.getValueType();
23987 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23989 DAG.getConstant(~XorC, SDLoc(Op1), VT));
23990 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23991 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
23995 // Try to synthesize horizontal adds from adds of shuffles.
23996 EVT VT = N->getValueType(0);
23997 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23998 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23999 isHorizontalBinOp(Op0, Op1, true))
24000 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24002 return OptimizeConditionalInDecrement(N, DAG);
24005 /// performVZEXTCombine - Performs build vector combines
24006 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24007 TargetLowering::DAGCombinerInfo &DCI,
24008 const X86Subtarget *Subtarget) {
24010 MVT VT = N->getSimpleValueType(0);
24011 SDValue Op = N->getOperand(0);
24012 MVT OpVT = Op.getSimpleValueType();
24013 MVT OpEltVT = OpVT.getVectorElementType();
24014 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24016 // (vzext (bitcast (vzext (x)) -> (vzext x)
24018 while (V.getOpcode() == ISD::BITCAST)
24019 V = V.getOperand(0);
24021 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24022 MVT InnerVT = V.getSimpleValueType();
24023 MVT InnerEltVT = InnerVT.getVectorElementType();
24025 // If the element sizes match exactly, we can just do one larger vzext. This
24026 // is always an exact type match as vzext operates on integer types.
24027 if (OpEltVT == InnerEltVT) {
24028 assert(OpVT == InnerVT && "Types must match for vzext!");
24029 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24032 // The only other way we can combine them is if only a single element of the
24033 // inner vzext is used in the input to the outer vzext.
24034 if (InnerEltVT.getSizeInBits() < InputBits)
24037 // In this case, the inner vzext is completely dead because we're going to
24038 // only look at bits inside of the low element. Just do the outer vzext on
24039 // a bitcast of the input to the inner.
24040 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24041 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24044 // Check if we can bypass extracting and re-inserting an element of an input
24045 // vector. Essentialy:
24046 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24047 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24048 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24049 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24050 SDValue ExtractedV = V.getOperand(0);
24051 SDValue OrigV = ExtractedV.getOperand(0);
24052 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24053 if (ExtractIdx->getZExtValue() == 0) {
24054 MVT OrigVT = OrigV.getSimpleValueType();
24055 // Extract a subvector if necessary...
24056 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24057 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24058 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24059 OrigVT.getVectorNumElements() / Ratio);
24060 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24061 DAG.getIntPtrConstant(0, DL));
24063 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24064 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24071 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24072 DAGCombinerInfo &DCI) const {
24073 SelectionDAG &DAG = DCI.DAG;
24074 switch (N->getOpcode()) {
24076 case ISD::EXTRACT_VECTOR_ELT:
24077 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24080 case X86ISD::SHRUNKBLEND:
24081 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24082 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24083 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24084 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24085 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24086 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24087 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24090 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24091 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24092 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24093 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24094 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24095 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24096 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24097 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24098 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24099 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24100 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24102 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24104 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24105 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24106 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24107 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24108 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24109 case ISD::ANY_EXTEND:
24110 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24111 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24112 case ISD::SIGN_EXTEND_INREG:
24113 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24114 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24115 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24116 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24117 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24118 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24119 case X86ISD::SHUFP: // Handle all target specific shuffles
24120 case X86ISD::PALIGNR:
24121 case X86ISD::UNPCKH:
24122 case X86ISD::UNPCKL:
24123 case X86ISD::MOVHLPS:
24124 case X86ISD::MOVLHPS:
24125 case X86ISD::PSHUFB:
24126 case X86ISD::PSHUFD:
24127 case X86ISD::PSHUFHW:
24128 case X86ISD::PSHUFLW:
24129 case X86ISD::MOVSS:
24130 case X86ISD::MOVSD:
24131 case X86ISD::VPERMILPI:
24132 case X86ISD::VPERM2X128:
24133 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24134 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24135 case ISD::INTRINSIC_WO_CHAIN:
24136 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24137 case X86ISD::INSERTPS: {
24138 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24139 return PerformINSERTPSCombine(N, DAG, Subtarget);
24142 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24148 /// isTypeDesirableForOp - Return true if the target has native support for
24149 /// the specified value type and it is 'desirable' to use the type for the
24150 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24151 /// instruction encodings are longer and some i16 instructions are slow.
24152 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24153 if (!isTypeLegal(VT))
24155 if (VT != MVT::i16)
24162 case ISD::SIGN_EXTEND:
24163 case ISD::ZERO_EXTEND:
24164 case ISD::ANY_EXTEND:
24177 /// IsDesirableToPromoteOp - This method query the target whether it is
24178 /// beneficial for dag combiner to promote the specified node. If true, it
24179 /// should return the desired promotion type by reference.
24180 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24181 EVT VT = Op.getValueType();
24182 if (VT != MVT::i16)
24185 bool Promote = false;
24186 bool Commute = false;
24187 switch (Op.getOpcode()) {
24190 LoadSDNode *LD = cast<LoadSDNode>(Op);
24191 // If the non-extending load has a single use and it's not live out, then it
24192 // might be folded.
24193 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24194 Op.hasOneUse()*/) {
24195 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24196 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24197 // The only case where we'd want to promote LOAD (rather then it being
24198 // promoted as an operand is when it's only use is liveout.
24199 if (UI->getOpcode() != ISD::CopyToReg)
24206 case ISD::SIGN_EXTEND:
24207 case ISD::ZERO_EXTEND:
24208 case ISD::ANY_EXTEND:
24213 SDValue N0 = Op.getOperand(0);
24214 // Look out for (store (shl (load), x)).
24215 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24228 SDValue N0 = Op.getOperand(0);
24229 SDValue N1 = Op.getOperand(1);
24230 if (!Commute && MayFoldLoad(N1))
24232 // Avoid disabling potential load folding opportunities.
24233 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24235 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24245 //===----------------------------------------------------------------------===//
24246 // X86 Inline Assembly Support
24247 //===----------------------------------------------------------------------===//
24249 // Helper to match a string separated by whitespace.
24250 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24251 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24253 for (StringRef Piece : Pieces) {
24254 if (!S.startswith(Piece)) // Check if the piece matches.
24257 S = S.substr(Piece.size());
24258 StringRef::size_type Pos = S.find_first_not_of(" \t");
24259 if (Pos == 0) // We matched a prefix.
24268 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24270 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24271 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24272 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24273 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24275 if (AsmPieces.size() == 3)
24277 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24284 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24285 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24287 std::string AsmStr = IA->getAsmString();
24289 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24290 if (!Ty || Ty->getBitWidth() % 16 != 0)
24293 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24294 SmallVector<StringRef, 4> AsmPieces;
24295 SplitString(AsmStr, AsmPieces, ";\n");
24297 switch (AsmPieces.size()) {
24298 default: return false;
24300 // FIXME: this should verify that we are targeting a 486 or better. If not,
24301 // we will turn this bswap into something that will be lowered to logical
24302 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24303 // lower so don't worry about this.
24305 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24306 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24307 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24308 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24309 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24310 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24311 // No need to check constraints, nothing other than the equivalent of
24312 // "=r,0" would be valid here.
24313 return IntrinsicLowering::LowerToByteSwap(CI);
24316 // rorw $$8, ${0:w} --> llvm.bswap.i16
24317 if (CI->getType()->isIntegerTy(16) &&
24318 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24319 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24320 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24322 const std::string &ConstraintsStr = IA->getConstraintString();
24323 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24324 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24325 if (clobbersFlagRegisters(AsmPieces))
24326 return IntrinsicLowering::LowerToByteSwap(CI);
24330 if (CI->getType()->isIntegerTy(32) &&
24331 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24332 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24333 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24334 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24336 const std::string &ConstraintsStr = IA->getConstraintString();
24337 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24338 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24339 if (clobbersFlagRegisters(AsmPieces))
24340 return IntrinsicLowering::LowerToByteSwap(CI);
24343 if (CI->getType()->isIntegerTy(64)) {
24344 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24345 if (Constraints.size() >= 2 &&
24346 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24347 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24348 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24349 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24350 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24351 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24352 return IntrinsicLowering::LowerToByteSwap(CI);
24360 /// getConstraintType - Given a constraint letter, return the type of
24361 /// constraint it is for this target.
24362 X86TargetLowering::ConstraintType
24363 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24364 if (Constraint.size() == 1) {
24365 switch (Constraint[0]) {
24376 return C_RegisterClass;
24400 return TargetLowering::getConstraintType(Constraint);
24403 /// Examine constraint type and operand type and determine a weight value.
24404 /// This object must already have been set up with the operand type
24405 /// and the current alternative constraint selected.
24406 TargetLowering::ConstraintWeight
24407 X86TargetLowering::getSingleConstraintMatchWeight(
24408 AsmOperandInfo &info, const char *constraint) const {
24409 ConstraintWeight weight = CW_Invalid;
24410 Value *CallOperandVal = info.CallOperandVal;
24411 // If we don't have a value, we can't do a match,
24412 // but allow it at the lowest weight.
24413 if (!CallOperandVal)
24415 Type *type = CallOperandVal->getType();
24416 // Look at the constraint type.
24417 switch (*constraint) {
24419 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24430 if (CallOperandVal->getType()->isIntegerTy())
24431 weight = CW_SpecificReg;
24436 if (type->isFloatingPointTy())
24437 weight = CW_SpecificReg;
24440 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24441 weight = CW_SpecificReg;
24445 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24446 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24447 weight = CW_Register;
24450 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24451 if (C->getZExtValue() <= 31)
24452 weight = CW_Constant;
24456 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24457 if (C->getZExtValue() <= 63)
24458 weight = CW_Constant;
24462 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24463 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24464 weight = CW_Constant;
24468 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24469 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24470 weight = CW_Constant;
24474 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24475 if (C->getZExtValue() <= 3)
24476 weight = CW_Constant;
24480 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24481 if (C->getZExtValue() <= 0xff)
24482 weight = CW_Constant;
24487 if (isa<ConstantFP>(CallOperandVal)) {
24488 weight = CW_Constant;
24492 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24493 if ((C->getSExtValue() >= -0x80000000LL) &&
24494 (C->getSExtValue() <= 0x7fffffffLL))
24495 weight = CW_Constant;
24499 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24500 if (C->getZExtValue() <= 0xffffffff)
24501 weight = CW_Constant;
24508 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24509 /// with another that has more specific requirements based on the type of the
24510 /// corresponding operand.
24511 const char *X86TargetLowering::
24512 LowerXConstraint(EVT ConstraintVT) const {
24513 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24514 // 'f' like normal targets.
24515 if (ConstraintVT.isFloatingPoint()) {
24516 if (Subtarget->hasSSE2())
24518 if (Subtarget->hasSSE1())
24522 return TargetLowering::LowerXConstraint(ConstraintVT);
24525 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24526 /// vector. If it is invalid, don't add anything to Ops.
24527 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24528 std::string &Constraint,
24529 std::vector<SDValue>&Ops,
24530 SelectionDAG &DAG) const {
24533 // Only support length 1 constraints for now.
24534 if (Constraint.length() > 1) return;
24536 char ConstraintLetter = Constraint[0];
24537 switch (ConstraintLetter) {
24540 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24541 if (C->getZExtValue() <= 31) {
24542 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24543 Op.getValueType());
24549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24550 if (C->getZExtValue() <= 63) {
24551 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24552 Op.getValueType());
24558 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24559 if (isInt<8>(C->getSExtValue())) {
24560 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24561 Op.getValueType());
24567 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24568 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24569 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24570 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
24571 Op.getValueType());
24577 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24578 if (C->getZExtValue() <= 3) {
24579 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24580 Op.getValueType());
24586 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24587 if (C->getZExtValue() <= 255) {
24588 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24589 Op.getValueType());
24595 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24596 if (C->getZExtValue() <= 127) {
24597 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24598 Op.getValueType());
24604 // 32-bit signed value
24605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24606 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24607 C->getSExtValue())) {
24608 // Widen to 64 bits here to get it sign extended.
24609 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
24612 // FIXME gcc accepts some relocatable values here too, but only in certain
24613 // memory models; it's complicated.
24618 // 32-bit unsigned value
24619 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24620 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24621 C->getZExtValue())) {
24622 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
24623 Op.getValueType());
24627 // FIXME gcc accepts some relocatable values here too, but only in certain
24628 // memory models; it's complicated.
24632 // Literal immediates are always ok.
24633 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24634 // Widen to 64 bits here to get it sign extended.
24635 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
24639 // In any sort of PIC mode addresses need to be computed at runtime by
24640 // adding in a register or some sort of table lookup. These can't
24641 // be used as immediates.
24642 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24645 // If we are in non-pic codegen mode, we allow the address of a global (with
24646 // an optional displacement) to be used with 'i'.
24647 GlobalAddressSDNode *GA = nullptr;
24648 int64_t Offset = 0;
24650 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24652 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24653 Offset += GA->getOffset();
24655 } else if (Op.getOpcode() == ISD::ADD) {
24656 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24657 Offset += C->getZExtValue();
24658 Op = Op.getOperand(0);
24661 } else if (Op.getOpcode() == ISD::SUB) {
24662 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24663 Offset += -C->getZExtValue();
24664 Op = Op.getOperand(0);
24669 // Otherwise, this isn't something we can handle, reject it.
24673 const GlobalValue *GV = GA->getGlobal();
24674 // If we require an extra load to get this address, as in PIC mode, we
24675 // can't accept it.
24676 if (isGlobalStubReference(
24677 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24680 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24681 GA->getValueType(0), Offset);
24686 if (Result.getNode()) {
24687 Ops.push_back(Result);
24690 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24693 std::pair<unsigned, const TargetRegisterClass *>
24694 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
24695 const std::string &Constraint,
24697 // First, see if this is a constraint that directly corresponds to an LLVM
24699 if (Constraint.size() == 1) {
24700 // GCC Constraint Letters
24701 switch (Constraint[0]) {
24703 // TODO: Slight differences here in allocation order and leaving
24704 // RIP in the class. Do they matter any more here than they do
24705 // in the normal allocation?
24706 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24707 if (Subtarget->is64Bit()) {
24708 if (VT == MVT::i32 || VT == MVT::f32)
24709 return std::make_pair(0U, &X86::GR32RegClass);
24710 if (VT == MVT::i16)
24711 return std::make_pair(0U, &X86::GR16RegClass);
24712 if (VT == MVT::i8 || VT == MVT::i1)
24713 return std::make_pair(0U, &X86::GR8RegClass);
24714 if (VT == MVT::i64 || VT == MVT::f64)
24715 return std::make_pair(0U, &X86::GR64RegClass);
24718 // 32-bit fallthrough
24719 case 'Q': // Q_REGS
24720 if (VT == MVT::i32 || VT == MVT::f32)
24721 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24722 if (VT == MVT::i16)
24723 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24724 if (VT == MVT::i8 || VT == MVT::i1)
24725 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24726 if (VT == MVT::i64)
24727 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24729 case 'r': // GENERAL_REGS
24730 case 'l': // INDEX_REGS
24731 if (VT == MVT::i8 || VT == MVT::i1)
24732 return std::make_pair(0U, &X86::GR8RegClass);
24733 if (VT == MVT::i16)
24734 return std::make_pair(0U, &X86::GR16RegClass);
24735 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24736 return std::make_pair(0U, &X86::GR32RegClass);
24737 return std::make_pair(0U, &X86::GR64RegClass);
24738 case 'R': // LEGACY_REGS
24739 if (VT == MVT::i8 || VT == MVT::i1)
24740 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24741 if (VT == MVT::i16)
24742 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24743 if (VT == MVT::i32 || !Subtarget->is64Bit())
24744 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24745 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24746 case 'f': // FP Stack registers.
24747 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24748 // value to the correct fpstack register class.
24749 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24750 return std::make_pair(0U, &X86::RFP32RegClass);
24751 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24752 return std::make_pair(0U, &X86::RFP64RegClass);
24753 return std::make_pair(0U, &X86::RFP80RegClass);
24754 case 'y': // MMX_REGS if MMX allowed.
24755 if (!Subtarget->hasMMX()) break;
24756 return std::make_pair(0U, &X86::VR64RegClass);
24757 case 'Y': // SSE_REGS if SSE2 allowed
24758 if (!Subtarget->hasSSE2()) break;
24760 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24761 if (!Subtarget->hasSSE1()) break;
24763 switch (VT.SimpleTy) {
24765 // Scalar SSE types.
24768 return std::make_pair(0U, &X86::FR32RegClass);
24771 return std::make_pair(0U, &X86::FR64RegClass);
24779 return std::make_pair(0U, &X86::VR128RegClass);
24787 return std::make_pair(0U, &X86::VR256RegClass);
24792 return std::make_pair(0U, &X86::VR512RegClass);
24798 // Use the default implementation in TargetLowering to convert the register
24799 // constraint into a member of a register class.
24800 std::pair<unsigned, const TargetRegisterClass*> Res;
24801 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
24803 // Not found as a standard register?
24805 // Map st(0) -> st(7) -> ST0
24806 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24807 tolower(Constraint[1]) == 's' &&
24808 tolower(Constraint[2]) == 't' &&
24809 Constraint[3] == '(' &&
24810 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24811 Constraint[5] == ')' &&
24812 Constraint[6] == '}') {
24814 Res.first = X86::FP0+Constraint[4]-'0';
24815 Res.second = &X86::RFP80RegClass;
24819 // GCC allows "st(0)" to be called just plain "st".
24820 if (StringRef("{st}").equals_lower(Constraint)) {
24821 Res.first = X86::FP0;
24822 Res.second = &X86::RFP80RegClass;
24827 if (StringRef("{flags}").equals_lower(Constraint)) {
24828 Res.first = X86::EFLAGS;
24829 Res.second = &X86::CCRRegClass;
24833 // 'A' means EAX + EDX.
24834 if (Constraint == "A") {
24835 Res.first = X86::EAX;
24836 Res.second = &X86::GR32_ADRegClass;
24842 // Otherwise, check to see if this is a register class of the wrong value
24843 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24844 // turn into {ax},{dx}.
24845 if (Res.second->hasType(VT))
24846 return Res; // Correct type already, nothing to do.
24848 // All of the single-register GCC register classes map their values onto
24849 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24850 // really want an 8-bit or 32-bit register, map to the appropriate register
24851 // class and return the appropriate register.
24852 if (Res.second == &X86::GR16RegClass) {
24853 if (VT == MVT::i8 || VT == MVT::i1) {
24854 unsigned DestReg = 0;
24855 switch (Res.first) {
24857 case X86::AX: DestReg = X86::AL; break;
24858 case X86::DX: DestReg = X86::DL; break;
24859 case X86::CX: DestReg = X86::CL; break;
24860 case X86::BX: DestReg = X86::BL; break;
24863 Res.first = DestReg;
24864 Res.second = &X86::GR8RegClass;
24866 } else if (VT == MVT::i32 || VT == MVT::f32) {
24867 unsigned DestReg = 0;
24868 switch (Res.first) {
24870 case X86::AX: DestReg = X86::EAX; break;
24871 case X86::DX: DestReg = X86::EDX; break;
24872 case X86::CX: DestReg = X86::ECX; break;
24873 case X86::BX: DestReg = X86::EBX; break;
24874 case X86::SI: DestReg = X86::ESI; break;
24875 case X86::DI: DestReg = X86::EDI; break;
24876 case X86::BP: DestReg = X86::EBP; break;
24877 case X86::SP: DestReg = X86::ESP; break;
24880 Res.first = DestReg;
24881 Res.second = &X86::GR32RegClass;
24883 } else if (VT == MVT::i64 || VT == MVT::f64) {
24884 unsigned DestReg = 0;
24885 switch (Res.first) {
24887 case X86::AX: DestReg = X86::RAX; break;
24888 case X86::DX: DestReg = X86::RDX; break;
24889 case X86::CX: DestReg = X86::RCX; break;
24890 case X86::BX: DestReg = X86::RBX; break;
24891 case X86::SI: DestReg = X86::RSI; break;
24892 case X86::DI: DestReg = X86::RDI; break;
24893 case X86::BP: DestReg = X86::RBP; break;
24894 case X86::SP: DestReg = X86::RSP; break;
24897 Res.first = DestReg;
24898 Res.second = &X86::GR64RegClass;
24901 } else if (Res.second == &X86::FR32RegClass ||
24902 Res.second == &X86::FR64RegClass ||
24903 Res.second == &X86::VR128RegClass ||
24904 Res.second == &X86::VR256RegClass ||
24905 Res.second == &X86::FR32XRegClass ||
24906 Res.second == &X86::FR64XRegClass ||
24907 Res.second == &X86::VR128XRegClass ||
24908 Res.second == &X86::VR256XRegClass ||
24909 Res.second == &X86::VR512RegClass) {
24910 // Handle references to XMM physical registers that got mapped into the
24911 // wrong class. This can happen with constraints like {xmm0} where the
24912 // target independent register mapper will just pick the first match it can
24913 // find, ignoring the required type.
24915 if (VT == MVT::f32 || VT == MVT::i32)
24916 Res.second = &X86::FR32RegClass;
24917 else if (VT == MVT::f64 || VT == MVT::i64)
24918 Res.second = &X86::FR64RegClass;
24919 else if (X86::VR128RegClass.hasType(VT))
24920 Res.second = &X86::VR128RegClass;
24921 else if (X86::VR256RegClass.hasType(VT))
24922 Res.second = &X86::VR256RegClass;
24923 else if (X86::VR512RegClass.hasType(VT))
24924 Res.second = &X86::VR512RegClass;
24930 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24932 // Scaling factors are not free at all.
24933 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24934 // will take 2 allocations in the out of order engine instead of 1
24935 // for plain addressing mode, i.e. inst (reg1).
24937 // vaddps (%rsi,%drx), %ymm0, %ymm1
24938 // Requires two allocations (one for the load, one for the computation)
24940 // vaddps (%rsi), %ymm0, %ymm1
24941 // Requires just 1 allocation, i.e., freeing allocations for other operations
24942 // and having less micro operations to execute.
24944 // For some X86 architectures, this is even worse because for instance for
24945 // stores, the complex addressing mode forces the instruction to use the
24946 // "load" ports instead of the dedicated "store" port.
24947 // E.g., on Haswell:
24948 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24949 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24950 if (isLegalAddressingMode(AM, Ty))
24951 // Scale represents reg2 * scale, thus account for 1
24952 // as soon as we use a second register.
24953 return AM.Scale != 0;
24957 bool X86TargetLowering::isTargetFTOL() const {
24958 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();