1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
184 // For 64-bit since we have so many registers use the ILP scheduler, for
185 // 32-bit code use the register pressure specific scheduling.
186 if (Subtarget->is64Bit())
187 setSchedulingPreference(Sched::ILP);
189 setSchedulingPreference(Sched::RegPressure);
190 setStackPointerRegisterToSaveRestore(X86StackPtr);
192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
193 // Setup Windows compiler runtime calls.
194 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
196 setLibcallName(RTLIB::SREM_I64, "_allrem");
197 setLibcallName(RTLIB::UREM_I64, "_aullrem");
198 setLibcallName(RTLIB::MUL_I64, "_allmul");
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
210 if (Subtarget->isTargetDarwin()) {
211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
212 setUseUnderscoreSetJmp(false);
213 setUseUnderscoreLongJmp(false);
214 } else if (Subtarget->isTargetMingw()) {
215 // MS runtime is weird: it exports _setjmp, but longjmp!
216 setUseUnderscoreSetJmp(true);
217 setUseUnderscoreLongJmp(false);
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(true);
223 // Set up the register classes.
224 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
225 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
226 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
227 if (Subtarget->is64Bit())
228 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232 // We don't accept any truncstore of integer registers.
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
240 // SETOEQ and SETUNE require checking two conditions.
241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
257 } else if (!UseSoftFloat) {
258 // We have an algorithm for SSE2->double, and we turn this into a
259 // 64-bit FILD followed by conditional FADD for other targets.
260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
261 // We have an algorithm for SSE2, and we turn this into a 64-bit
262 // FILD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
272 // SSE has no i16 to fp conversion, only i32
273 if (X86ScalarSSEf32) {
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
275 // f32 and f64 cases are Legal, f80 case is not
276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 // are Legal, f80 is custom lowered.
288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
296 if (X86ScalarSSEf32) {
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
298 // f32 and f64 cases are Legal, f80 case is not
299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
305 // Handle FP_TO_UINT by promoting the destination to a larger signed
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
314 } else if (!UseSoftFloat) {
315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasXMM())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
455 // On X86 and X86-64, atomic operations are lowered to locked instructions.
456 // Locked instructions, in turn, have implicit fence semantics (all memory
457 // operations are flushed before issuing the locked instruction, and they
458 // are not buffered), so we can fold away the common pattern of
459 // fence-atomic-fence.
460 setShouldFoldAtomicFences(true);
462 // Expand certain atomics
463 for (unsigned i = 0, e = 4; i != e; ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 if (!Subtarget->is64Bit()) {
470 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
471 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
479 // FIXME - use subtarget debug flags
480 if (!Subtarget->isTargetDarwin() &&
481 !Subtarget->isTargetELF() &&
482 !Subtarget->isTargetCygMing()) {
483 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
486 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
487 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
488 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
489 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
490 if (Subtarget->is64Bit()) {
491 setExceptionPointerRegister(X86::RAX);
492 setExceptionSelectorRegister(X86::RDX);
494 setExceptionPointerRegister(X86::EAX);
495 setExceptionSelectorRegister(X86::EDX);
497 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
498 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
500 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
502 setOperationAction(ISD::TRAP, MVT::Other, Legal);
504 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
505 setOperationAction(ISD::VASTART , MVT::Other, Custom);
506 setOperationAction(ISD::VAEND , MVT::Other, Expand);
507 if (Subtarget->is64Bit()) {
508 setOperationAction(ISD::VAARG , MVT::Other, Custom);
509 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
511 setOperationAction(ISD::VAARG , MVT::Other, Expand);
512 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
515 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
516 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
517 setOperationAction(ISD::DYNAMIC_STACKALLOC,
518 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
519 (Subtarget->isTargetCOFF()
520 && !Subtarget->isTargetEnvMacho()
523 if (!UseSoftFloat && X86ScalarSSEf64) {
524 // f32 and f64 use SSE.
525 // Set up the FP register classes.
526 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
527 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
529 // Use ANDPD to simulate FABS.
530 setOperationAction(ISD::FABS , MVT::f64, Custom);
531 setOperationAction(ISD::FABS , MVT::f32, Custom);
533 // Use XORP to simulate FNEG.
534 setOperationAction(ISD::FNEG , MVT::f64, Custom);
535 setOperationAction(ISD::FNEG , MVT::f32, Custom);
537 // Use ANDPD and ORPD to simulate FCOPYSIGN.
538 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
539 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
541 // Lower this to FGETSIGNx86 plus an AND.
542 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
543 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
545 // We don't support sin/cos/fmod
546 setOperationAction(ISD::FSIN , MVT::f64, Expand);
547 setOperationAction(ISD::FCOS , MVT::f64, Expand);
548 setOperationAction(ISD::FSIN , MVT::f32, Expand);
549 setOperationAction(ISD::FCOS , MVT::f32, Expand);
551 // Expand FP immediates into loads from the stack, except for the special
553 addLegalFPImmediate(APFloat(+0.0)); // xorpd
554 addLegalFPImmediate(APFloat(+0.0f)); // xorps
555 } else if (!UseSoftFloat && X86ScalarSSEf32) {
556 // Use SSE for f32, x87 for f64.
557 // Set up the FP register classes.
558 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
559 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
561 // Use ANDPS to simulate FABS.
562 setOperationAction(ISD::FABS , MVT::f32, Custom);
564 // Use XORP to simulate FNEG.
565 setOperationAction(ISD::FNEG , MVT::f32, Custom);
567 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
569 // Use ANDPS and ORPS to simulate FCOPYSIGN.
570 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
571 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
573 // We don't support sin/cos/fmod
574 setOperationAction(ISD::FSIN , MVT::f32, Expand);
575 setOperationAction(ISD::FCOS , MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
585 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
586 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
588 } else if (!UseSoftFloat) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
592 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
601 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
603 addLegalFPImmediate(APFloat(+0.0)); // FLD0
604 addLegalFPImmediate(APFloat(+1.0)); // FLD1
605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
607 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
613 // We don't support FMA.
614 setOperationAction(ISD::FMA, MVT::f64, Expand);
615 setOperationAction(ISD::FMA, MVT::f32, Expand);
617 // Long double always uses X87.
619 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
620 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
621 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
623 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
624 addLegalFPImmediate(TmpFlt); // FLD0
626 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
629 APFloat TmpFlt2(+1.0);
630 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
632 addLegalFPImmediate(TmpFlt2); // FLD1
633 TmpFlt2.changeSign();
634 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
639 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
642 setOperationAction(ISD::FMA, MVT::f80, Expand);
645 // Always use a library call for pow.
646 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
647 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
648 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
650 setOperationAction(ISD::FLOG, MVT::f80, Expand);
651 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
652 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
653 setOperationAction(ISD::FEXP, MVT::f80, Expand);
654 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
656 // First set operation action for all vector types to either promote
657 // (for widening) or expand (for scalarization). Then we will selectively
658 // turn on ones that can be effectively codegen'd.
659 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
660 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
661 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
662 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
663 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
664 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
665 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
666 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
667 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
668 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
669 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
670 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
671 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
672 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
673 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
676 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
678 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
679 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
711 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
715 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
716 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
717 setTruncStoreAction((MVT::SimpleValueType)VT,
718 (MVT::SimpleValueType)InnerVT, Expand);
719 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
720 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
721 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
724 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
725 // with -msoft-float, disable use of MMX as well.
726 if (!UseSoftFloat && Subtarget->hasMMX()) {
727 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
728 // No operations on x86mmx supported, everything uses intrinsics.
731 // MMX-sized vectors (other than x86mmx) are expected to be expanded
732 // into smaller operations.
733 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
734 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
735 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
736 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
737 setOperationAction(ISD::AND, MVT::v8i8, Expand);
738 setOperationAction(ISD::AND, MVT::v4i16, Expand);
739 setOperationAction(ISD::AND, MVT::v2i32, Expand);
740 setOperationAction(ISD::AND, MVT::v1i64, Expand);
741 setOperationAction(ISD::OR, MVT::v8i8, Expand);
742 setOperationAction(ISD::OR, MVT::v4i16, Expand);
743 setOperationAction(ISD::OR, MVT::v2i32, Expand);
744 setOperationAction(ISD::OR, MVT::v1i64, Expand);
745 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
746 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
747 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
748 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
750 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
754 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
755 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
756 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
757 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
758 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
759 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
760 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
761 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
763 if (!UseSoftFloat && Subtarget->hasXMM()) {
764 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
766 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
767 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
768 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
769 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
770 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
771 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
772 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
773 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
774 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
776 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
777 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
780 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
781 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
783 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
784 // registers cannot be used even for integer operations.
785 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
786 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
787 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
788 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
790 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
791 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
792 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
793 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
794 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
795 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
796 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
797 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
798 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
799 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
800 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
801 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
802 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
803 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
804 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
805 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
807 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
808 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
809 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
810 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
812 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
813 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
821 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
822 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
824 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
825 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
826 EVT VT = (MVT::SimpleValueType)i;
827 // Do not attempt to custom lower non-power-of-2 vectors
828 if (!isPowerOf2_32(VT.getVectorNumElements()))
830 // Do not attempt to custom lower non-128-bit vectors
831 if (!VT.is128BitVector())
833 setOperationAction(ISD::BUILD_VECTOR,
834 VT.getSimpleVT().SimpleTy, Custom);
835 setOperationAction(ISD::VECTOR_SHUFFLE,
836 VT.getSimpleVT().SimpleTy, Custom);
837 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
838 VT.getSimpleVT().SimpleTy, Custom);
841 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
842 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
843 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
844 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
848 if (Subtarget->is64Bit()) {
849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
853 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
854 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
855 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
858 // Do not attempt to promote non-128-bit vectors
859 if (!VT.is128BitVector())
862 setOperationAction(ISD::AND, SVT, Promote);
863 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
864 setOperationAction(ISD::OR, SVT, Promote);
865 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
866 setOperationAction(ISD::XOR, SVT, Promote);
867 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
868 setOperationAction(ISD::LOAD, SVT, Promote);
869 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
870 setOperationAction(ISD::SELECT, SVT, Promote);
871 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
874 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
876 // Custom lower v2i64 and v2f64 selects.
877 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
878 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
879 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
882 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
883 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
886 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
887 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
888 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
889 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
890 setOperationAction(ISD::FRINT, MVT::f32, Legal);
891 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
892 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
893 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
894 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
895 setOperationAction(ISD::FRINT, MVT::f64, Legal);
896 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
898 // FIXME: Do we need to handle scalar-to-vector here?
899 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
901 // Can turn SHL into an integer multiply.
902 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
903 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
905 // i8 and i16 vectors are custom , because the source register and source
906 // source memory operand types are not the same width. f32 vectors are
907 // custom since the immediate controlling the insert encodes additional
909 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
914 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
916 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
919 if (Subtarget->is64Bit()) {
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
925 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
926 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
927 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
928 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
929 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
931 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
932 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
933 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
935 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
936 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
939 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
940 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
942 if (!UseSoftFloat && Subtarget->hasAVX()) {
943 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
944 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
945 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
946 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
947 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
948 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
950 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
951 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
952 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
954 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
955 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
956 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
957 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
958 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
959 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
961 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
962 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
963 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
964 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
965 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
966 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
968 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
969 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
970 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
972 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
973 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
974 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
975 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
976 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
977 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
980 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
981 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
982 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
984 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
985 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
986 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
987 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
989 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
990 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
992 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
993 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
995 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
996 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
997 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
999 // Custom lower several nodes for 256-bit types.
1000 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1001 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1002 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1005 // Extract subvector is special because the value type
1006 // (result) is 128-bit but the source is 256-bit wide.
1007 if (VT.is128BitVector())
1008 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1010 // Do not attempt to custom lower other non-256-bit vectors
1011 if (!VT.is256BitVector())
1014 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1015 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1016 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1018 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1019 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1022 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1023 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1024 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1027 // Do not attempt to promote non-256-bit vectors
1028 if (!VT.is256BitVector())
1031 setOperationAction(ISD::AND, SVT, Promote);
1032 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1033 setOperationAction(ISD::OR, SVT, Promote);
1034 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1035 setOperationAction(ISD::XOR, SVT, Promote);
1036 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1037 setOperationAction(ISD::LOAD, SVT, Promote);
1038 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1039 setOperationAction(ISD::SELECT, SVT, Promote);
1040 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1044 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1045 // of this type with custom code.
1046 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1047 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1048 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1051 // We want to custom lower some of our intrinsics.
1052 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1055 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1056 // handle type legalization for these operations here.
1058 // FIXME: We really should do custom legalization for addition and
1059 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1060 // than generic legalization for 64-bit multiplication-with-overflow, though.
1061 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1062 // Add/Sub/Mul with overflow operations are custom lowered.
1064 setOperationAction(ISD::SADDO, VT, Custom);
1065 setOperationAction(ISD::UADDO, VT, Custom);
1066 setOperationAction(ISD::SSUBO, VT, Custom);
1067 setOperationAction(ISD::USUBO, VT, Custom);
1068 setOperationAction(ISD::SMULO, VT, Custom);
1069 setOperationAction(ISD::UMULO, VT, Custom);
1072 // There are no 8-bit 3-address imul/mul instructions
1073 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1074 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1076 if (!Subtarget->is64Bit()) {
1077 // These libcalls are not available in 32-bit.
1078 setLibcallName(RTLIB::SHL_I128, 0);
1079 setLibcallName(RTLIB::SRL_I128, 0);
1080 setLibcallName(RTLIB::SRA_I128, 0);
1083 // We have target-specific dag combine patterns for the following nodes:
1084 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1085 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1086 setTargetDAGCombine(ISD::BUILD_VECTOR);
1087 setTargetDAGCombine(ISD::SELECT);
1088 setTargetDAGCombine(ISD::SHL);
1089 setTargetDAGCombine(ISD::SRA);
1090 setTargetDAGCombine(ISD::SRL);
1091 setTargetDAGCombine(ISD::OR);
1092 setTargetDAGCombine(ISD::AND);
1093 setTargetDAGCombine(ISD::ADD);
1094 setTargetDAGCombine(ISD::SUB);
1095 setTargetDAGCombine(ISD::STORE);
1096 setTargetDAGCombine(ISD::ZERO_EXTEND);
1097 setTargetDAGCombine(ISD::SINT_TO_FP);
1098 if (Subtarget->is64Bit())
1099 setTargetDAGCombine(ISD::MUL);
1101 computeRegisterProperties();
1103 // On Darwin, -Os means optimize for size without hurting performance,
1104 // do not reduce the limit.
1105 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1106 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1107 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1108 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1109 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1110 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1111 setPrefLoopAlignment(16);
1112 benefitFromCodePlacementOpt = true;
1114 setPrefFunctionAlignment(4);
1118 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1123 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1124 /// the desired ByVal argument alignment.
1125 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1128 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1129 if (VTy->getBitWidth() == 128)
1131 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1132 unsigned EltAlign = 0;
1133 getMaxByValAlign(ATy->getElementType(), EltAlign);
1134 if (EltAlign > MaxAlign)
1135 MaxAlign = EltAlign;
1136 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1137 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1138 unsigned EltAlign = 0;
1139 getMaxByValAlign(STy->getElementType(i), EltAlign);
1140 if (EltAlign > MaxAlign)
1141 MaxAlign = EltAlign;
1149 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1150 /// function arguments in the caller parameter area. For X86, aggregates
1151 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1152 /// are at 4-byte boundaries.
1153 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1154 if (Subtarget->is64Bit()) {
1155 // Max of 8 and alignment of type.
1156 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1163 if (Subtarget->hasXMM())
1164 getMaxByValAlign(Ty, Align);
1168 /// getOptimalMemOpType - Returns the target specific optimal type for load
1169 /// and store operations as a result of memset, memcpy, and memmove
1170 /// lowering. If DstAlign is zero that means it's safe to destination
1171 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1172 /// means there isn't a need to check it against alignment requirement,
1173 /// probably because the source does not need to be loaded. If
1174 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1175 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1176 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1177 /// constant so it does not need to be loaded.
1178 /// It returns EVT::Other if the type should be determined using generic
1179 /// target-independent logic.
1181 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1182 unsigned DstAlign, unsigned SrcAlign,
1183 bool NonScalarIntSafe,
1185 MachineFunction &MF) const {
1186 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1187 // linux. This is because the stack realignment code can't handle certain
1188 // cases like PR2962. This should be removed when PR2962 is fixed.
1189 const Function *F = MF.getFunction();
1190 if (NonScalarIntSafe &&
1191 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1193 (Subtarget->isUnalignedMemAccessFast() ||
1194 ((DstAlign == 0 || DstAlign >= 16) &&
1195 (SrcAlign == 0 || SrcAlign >= 16))) &&
1196 Subtarget->getStackAlignment() >= 16) {
1197 if (Subtarget->hasSSE2())
1199 if (Subtarget->hasSSE1())
1201 } else if (!MemcpyStrSrc && Size >= 8 &&
1202 !Subtarget->is64Bit() &&
1203 Subtarget->getStackAlignment() >= 8 &&
1204 Subtarget->hasXMMInt()) {
1205 // Do not use f64 to lower memcpy if source is string constant. It's
1206 // better to use i32 to avoid the loads.
1210 if (Subtarget->is64Bit() && Size >= 8)
1215 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1216 /// current function. The returned value is a member of the
1217 /// MachineJumpTableInfo::JTEntryKind enum.
1218 unsigned X86TargetLowering::getJumpTableEncoding() const {
1219 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1221 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1222 Subtarget->isPICStyleGOT())
1223 return MachineJumpTableInfo::EK_Custom32;
1225 // Otherwise, use the normal jump table encoding heuristics.
1226 return TargetLowering::getJumpTableEncoding();
1230 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1231 const MachineBasicBlock *MBB,
1232 unsigned uid,MCContext &Ctx) const{
1233 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1234 Subtarget->isPICStyleGOT());
1235 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1237 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1238 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1241 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1243 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1244 SelectionDAG &DAG) const {
1245 if (!Subtarget->is64Bit())
1246 // This doesn't have DebugLoc associated with it, but is not really the
1247 // same as a Register.
1248 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1252 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1253 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1255 const MCExpr *X86TargetLowering::
1256 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1257 MCContext &Ctx) const {
1258 // X86-64 uses RIP relative addressing based on the jump table label.
1259 if (Subtarget->isPICStyleRIPRel())
1260 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1262 // Otherwise, the reference is relative to the PIC base.
1263 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1266 // FIXME: Why this routine is here? Move to RegInfo!
1267 std::pair<const TargetRegisterClass*, uint8_t>
1268 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1269 const TargetRegisterClass *RRC = 0;
1271 switch (VT.getSimpleVT().SimpleTy) {
1273 return TargetLowering::findRepresentativeClass(VT);
1274 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1275 RRC = (Subtarget->is64Bit()
1276 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1279 RRC = X86::VR64RegisterClass;
1281 case MVT::f32: case MVT::f64:
1282 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1283 case MVT::v4f32: case MVT::v2f64:
1284 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1286 RRC = X86::VR128RegisterClass;
1289 return std::make_pair(RRC, Cost);
1292 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1293 unsigned &Offset) const {
1294 if (!Subtarget->isTargetLinux())
1297 if (Subtarget->is64Bit()) {
1298 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1300 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1313 //===----------------------------------------------------------------------===//
1314 // Return Value Calling Convention Implementation
1315 //===----------------------------------------------------------------------===//
1317 #include "X86GenCallingConv.inc"
1320 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1321 MachineFunction &MF, bool isVarArg,
1322 const SmallVectorImpl<ISD::OutputArg> &Outs,
1323 LLVMContext &Context) const {
1324 SmallVector<CCValAssign, 16> RVLocs;
1325 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1327 return CCInfo.CheckReturn(Outs, RetCC_X86);
1331 X86TargetLowering::LowerReturn(SDValue Chain,
1332 CallingConv::ID CallConv, bool isVarArg,
1333 const SmallVectorImpl<ISD::OutputArg> &Outs,
1334 const SmallVectorImpl<SDValue> &OutVals,
1335 DebugLoc dl, SelectionDAG &DAG) const {
1336 MachineFunction &MF = DAG.getMachineFunction();
1337 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1339 SmallVector<CCValAssign, 16> RVLocs;
1340 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1341 RVLocs, *DAG.getContext());
1342 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1344 // Add the regs to the liveout set for the function.
1345 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1346 for (unsigned i = 0; i != RVLocs.size(); ++i)
1347 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1348 MRI.addLiveOut(RVLocs[i].getLocReg());
1352 SmallVector<SDValue, 6> RetOps;
1353 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1354 // Operand #1 = Bytes To Pop
1355 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1358 // Copy the result values into the output registers.
1359 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1360 CCValAssign &VA = RVLocs[i];
1361 assert(VA.isRegLoc() && "Can only return in registers!");
1362 SDValue ValToCopy = OutVals[i];
1363 EVT ValVT = ValToCopy.getValueType();
1365 // If this is x86-64, and we disabled SSE, we can't return FP values,
1366 // or SSE or MMX vectors.
1367 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1368 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1369 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1370 report_fatal_error("SSE register return with SSE disabled");
1372 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1373 // llvm-gcc has never done it right and no one has noticed, so this
1374 // should be OK for now.
1375 if (ValVT == MVT::f64 &&
1376 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1377 report_fatal_error("SSE2 register return with SSE2 disabled");
1379 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1380 // the RET instruction and handled by the FP Stackifier.
1381 if (VA.getLocReg() == X86::ST0 ||
1382 VA.getLocReg() == X86::ST1) {
1383 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1384 // change the value to the FP stack register class.
1385 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1386 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1387 RetOps.push_back(ValToCopy);
1388 // Don't emit a copytoreg.
1392 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1393 // which is returned in RAX / RDX.
1394 if (Subtarget->is64Bit()) {
1395 if (ValVT == MVT::x86mmx) {
1396 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1397 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1398 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1400 // If we don't have SSE2 available, convert to v4f32 so the generated
1401 // register is legal.
1402 if (!Subtarget->hasSSE2())
1403 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1408 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1409 Flag = Chain.getValue(1);
1412 // The x86-64 ABI for returning structs by value requires that we copy
1413 // the sret argument into %rax for the return. We saved the argument into
1414 // a virtual register in the entry block, so now we copy the value out
1416 if (Subtarget->is64Bit() &&
1417 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1418 MachineFunction &MF = DAG.getMachineFunction();
1419 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1420 unsigned Reg = FuncInfo->getSRetReturnReg();
1422 "SRetReturnReg should have been set in LowerFormalArguments().");
1423 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1425 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1426 Flag = Chain.getValue(1);
1428 // RAX now acts like a return value.
1429 MRI.addLiveOut(X86::RAX);
1432 RetOps[0] = Chain; // Update chain.
1434 // Add the flag if we have it.
1436 RetOps.push_back(Flag);
1438 return DAG.getNode(X86ISD::RET_FLAG, dl,
1439 MVT::Other, &RetOps[0], RetOps.size());
1442 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1443 if (N->getNumValues() != 1)
1445 if (!N->hasNUsesOfValue(1, 0))
1448 SDNode *Copy = *N->use_begin();
1449 if (Copy->getOpcode() != ISD::CopyToReg &&
1450 Copy->getOpcode() != ISD::FP_EXTEND)
1453 bool HasRet = false;
1454 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1456 if (UI->getOpcode() != X86ISD::RET_FLAG)
1465 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1466 ISD::NodeType ExtendKind) const {
1468 // TODO: Is this also valid on 32-bit?
1469 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1470 ReturnMVT = MVT::i8;
1472 ReturnMVT = MVT::i32;
1474 EVT MinVT = getRegisterType(Context, ReturnMVT);
1475 return VT.bitsLT(MinVT) ? MinVT : VT;
1478 /// LowerCallResult - Lower the result values of a call into the
1479 /// appropriate copies out of appropriate physical registers.
1482 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1483 CallingConv::ID CallConv, bool isVarArg,
1484 const SmallVectorImpl<ISD::InputArg> &Ins,
1485 DebugLoc dl, SelectionDAG &DAG,
1486 SmallVectorImpl<SDValue> &InVals) const {
1488 // Assign locations to each value returned by this call.
1489 SmallVector<CCValAssign, 16> RVLocs;
1490 bool Is64Bit = Subtarget->is64Bit();
1491 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1492 getTargetMachine(), RVLocs, *DAG.getContext());
1493 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1495 // Copy all of the result registers out of their specified physreg.
1496 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1497 CCValAssign &VA = RVLocs[i];
1498 EVT CopyVT = VA.getValVT();
1500 // If this is x86-64, and we disabled SSE, we can't return FP values
1501 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1502 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1503 report_fatal_error("SSE register return with SSE disabled");
1508 // If this is a call to a function that returns an fp value on the floating
1509 // point stack, we must guarantee the the value is popped from the stack, so
1510 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1511 // if the return value is not used. We use the FpPOP_RETVAL instruction
1513 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1514 // If we prefer to use the value in xmm registers, copy it out as f80 and
1515 // use a truncate to move it from fp stack reg to xmm reg.
1516 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1517 SDValue Ops[] = { Chain, InFlag };
1518 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1519 MVT::Other, MVT::Glue, Ops, 2), 1);
1520 Val = Chain.getValue(0);
1522 // Round the f80 to the right size, which also moves it to the appropriate
1524 if (CopyVT != VA.getValVT())
1525 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1526 // This truncation won't change the value.
1527 DAG.getIntPtrConstant(1));
1529 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1530 CopyVT, InFlag).getValue(1);
1531 Val = Chain.getValue(0);
1533 InFlag = Chain.getValue(2);
1534 InVals.push_back(Val);
1541 //===----------------------------------------------------------------------===//
1542 // C & StdCall & Fast Calling Convention implementation
1543 //===----------------------------------------------------------------------===//
1544 // StdCall calling convention seems to be standard for many Windows' API
1545 // routines and around. It differs from C calling convention just a little:
1546 // callee should clean up the stack, not caller. Symbols should be also
1547 // decorated in some fancy way :) It doesn't support any vector arguments.
1548 // For info on fast calling convention see Fast Calling Convention (tail call)
1549 // implementation LowerX86_32FastCCCallTo.
1551 /// CallIsStructReturn - Determines whether a call uses struct return
1553 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1557 return Outs[0].Flags.isSRet();
1560 /// ArgsAreStructReturn - Determines whether a function uses struct
1561 /// return semantics.
1563 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1567 return Ins[0].Flags.isSRet();
1570 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1571 /// by "Src" to address "Dst" with size and alignment information specified by
1572 /// the specific parameter attribute. The copy will be passed as a byval
1573 /// function parameter.
1575 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1576 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1578 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1580 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1581 /*isVolatile*/false, /*AlwaysInline=*/true,
1582 MachinePointerInfo(), MachinePointerInfo());
1585 /// IsTailCallConvention - Return true if the calling convention is one that
1586 /// supports tail call optimization.
1587 static bool IsTailCallConvention(CallingConv::ID CC) {
1588 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1591 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1592 if (!CI->isTailCall())
1596 CallingConv::ID CalleeCC = CS.getCallingConv();
1597 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1603 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1604 /// a tailcall target by changing its ABI.
1605 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1606 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1610 X86TargetLowering::LowerMemArgument(SDValue Chain,
1611 CallingConv::ID CallConv,
1612 const SmallVectorImpl<ISD::InputArg> &Ins,
1613 DebugLoc dl, SelectionDAG &DAG,
1614 const CCValAssign &VA,
1615 MachineFrameInfo *MFI,
1617 // Create the nodes corresponding to a load from this parameter slot.
1618 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1619 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1620 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1623 // If value is passed by pointer we have address passed instead of the value
1625 if (VA.getLocInfo() == CCValAssign::Indirect)
1626 ValVT = VA.getLocVT();
1628 ValVT = VA.getValVT();
1630 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1631 // changed with more analysis.
1632 // In case of tail call optimization mark all arguments mutable. Since they
1633 // could be overwritten by lowering of arguments in case of a tail call.
1634 if (Flags.isByVal()) {
1635 unsigned Bytes = Flags.getByValSize();
1636 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1637 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1638 return DAG.getFrameIndex(FI, getPointerTy());
1640 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1641 VA.getLocMemOffset(), isImmutable);
1642 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1643 return DAG.getLoad(ValVT, dl, Chain, FIN,
1644 MachinePointerInfo::getFixedStack(FI),
1650 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1651 CallingConv::ID CallConv,
1653 const SmallVectorImpl<ISD::InputArg> &Ins,
1656 SmallVectorImpl<SDValue> &InVals)
1658 MachineFunction &MF = DAG.getMachineFunction();
1659 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1661 const Function* Fn = MF.getFunction();
1662 if (Fn->hasExternalLinkage() &&
1663 Subtarget->isTargetCygMing() &&
1664 Fn->getName() == "main")
1665 FuncInfo->setForceFramePointer(true);
1667 MachineFrameInfo *MFI = MF.getFrameInfo();
1668 bool Is64Bit = Subtarget->is64Bit();
1669 bool IsWin64 = Subtarget->isTargetWin64();
1671 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1672 "Var args not supported with calling convention fastcc or ghc");
1674 // Assign locations to all of the incoming arguments.
1675 SmallVector<CCValAssign, 16> ArgLocs;
1676 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1677 ArgLocs, *DAG.getContext());
1679 // Allocate shadow area for Win64
1681 CCInfo.AllocateStack(32, 8);
1684 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1686 unsigned LastVal = ~0U;
1688 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1689 CCValAssign &VA = ArgLocs[i];
1690 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1692 assert(VA.getValNo() != LastVal &&
1693 "Don't support value assigned to multiple locs yet");
1694 LastVal = VA.getValNo();
1696 if (VA.isRegLoc()) {
1697 EVT RegVT = VA.getLocVT();
1698 TargetRegisterClass *RC = NULL;
1699 if (RegVT == MVT::i32)
1700 RC = X86::GR32RegisterClass;
1701 else if (Is64Bit && RegVT == MVT::i64)
1702 RC = X86::GR64RegisterClass;
1703 else if (RegVT == MVT::f32)
1704 RC = X86::FR32RegisterClass;
1705 else if (RegVT == MVT::f64)
1706 RC = X86::FR64RegisterClass;
1707 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1708 RC = X86::VR256RegisterClass;
1709 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1710 RC = X86::VR128RegisterClass;
1711 else if (RegVT == MVT::x86mmx)
1712 RC = X86::VR64RegisterClass;
1714 llvm_unreachable("Unknown argument type!");
1716 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1717 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1719 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1720 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1722 if (VA.getLocInfo() == CCValAssign::SExt)
1723 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1724 DAG.getValueType(VA.getValVT()));
1725 else if (VA.getLocInfo() == CCValAssign::ZExt)
1726 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1727 DAG.getValueType(VA.getValVT()));
1728 else if (VA.getLocInfo() == CCValAssign::BCvt)
1729 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1731 if (VA.isExtInLoc()) {
1732 // Handle MMX values passed in XMM regs.
1733 if (RegVT.isVector()) {
1734 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1737 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1740 assert(VA.isMemLoc());
1741 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1744 // If value is passed via pointer - do a load.
1745 if (VA.getLocInfo() == CCValAssign::Indirect)
1746 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1747 MachinePointerInfo(), false, false, 0);
1749 InVals.push_back(ArgValue);
1752 // The x86-64 ABI for returning structs by value requires that we copy
1753 // the sret argument into %rax for the return. Save the argument into
1754 // a virtual register so that we can access it from the return points.
1755 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1756 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1757 unsigned Reg = FuncInfo->getSRetReturnReg();
1759 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1760 FuncInfo->setSRetReturnReg(Reg);
1762 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1763 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1766 unsigned StackSize = CCInfo.getNextStackOffset();
1767 // Align stack specially for tail calls.
1768 if (FuncIsMadeTailCallSafe(CallConv))
1769 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1771 // If the function takes variable number of arguments, make a frame index for
1772 // the start of the first vararg value... for expansion of llvm.va_start.
1774 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1775 CallConv != CallingConv::X86_ThisCall)) {
1776 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1779 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1781 // FIXME: We should really autogenerate these arrays
1782 static const unsigned GPR64ArgRegsWin64[] = {
1783 X86::RCX, X86::RDX, X86::R8, X86::R9
1785 static const unsigned GPR64ArgRegs64Bit[] = {
1786 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1788 static const unsigned XMMArgRegs64Bit[] = {
1789 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1790 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1792 const unsigned *GPR64ArgRegs;
1793 unsigned NumXMMRegs = 0;
1796 // The XMM registers which might contain var arg parameters are shadowed
1797 // in their paired GPR. So we only need to save the GPR to their home
1799 TotalNumIntRegs = 4;
1800 GPR64ArgRegs = GPR64ArgRegsWin64;
1802 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1803 GPR64ArgRegs = GPR64ArgRegs64Bit;
1805 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1807 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1810 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1811 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1812 "SSE register cannot be used when SSE is disabled!");
1813 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1814 "SSE register cannot be used when SSE is disabled!");
1815 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1816 // Kernel mode asks for SSE to be disabled, so don't push them
1818 TotalNumXMMRegs = 0;
1821 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1822 // Get to the caller-allocated home save location. Add 8 to account
1823 // for the return address.
1824 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1825 FuncInfo->setRegSaveFrameIndex(
1826 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1827 // Fixup to set vararg frame on shadow area (4 x i64).
1829 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1831 // For X86-64, if there are vararg parameters that are passed via
1832 // registers, then we must store them to their spots on the stack so they
1833 // may be loaded by deferencing the result of va_next.
1834 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1835 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1836 FuncInfo->setRegSaveFrameIndex(
1837 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1841 // Store the integer parameter registers.
1842 SmallVector<SDValue, 8> MemOps;
1843 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1845 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1846 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1847 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1848 DAG.getIntPtrConstant(Offset));
1849 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1850 X86::GR64RegisterClass);
1851 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1853 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1854 MachinePointerInfo::getFixedStack(
1855 FuncInfo->getRegSaveFrameIndex(), Offset),
1857 MemOps.push_back(Store);
1861 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1862 // Now store the XMM (fp + vector) parameter registers.
1863 SmallVector<SDValue, 11> SaveXMMOps;
1864 SaveXMMOps.push_back(Chain);
1866 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1867 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1868 SaveXMMOps.push_back(ALVal);
1870 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1871 FuncInfo->getRegSaveFrameIndex()));
1872 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1873 FuncInfo->getVarArgsFPOffset()));
1875 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1876 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1877 X86::VR128RegisterClass);
1878 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1879 SaveXMMOps.push_back(Val);
1881 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1883 &SaveXMMOps[0], SaveXMMOps.size()));
1886 if (!MemOps.empty())
1887 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1888 &MemOps[0], MemOps.size());
1892 // Some CCs need callee pop.
1893 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1894 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1896 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1897 // If this is an sret function, the return should pop the hidden pointer.
1898 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1899 FuncInfo->setBytesToPopOnReturn(4);
1903 // RegSaveFrameIndex is X86-64 only.
1904 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1905 if (CallConv == CallingConv::X86_FastCall ||
1906 CallConv == CallingConv::X86_ThisCall)
1907 // fastcc functions can't have varargs.
1908 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1915 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1916 SDValue StackPtr, SDValue Arg,
1917 DebugLoc dl, SelectionDAG &DAG,
1918 const CCValAssign &VA,
1919 ISD::ArgFlagsTy Flags) const {
1920 unsigned LocMemOffset = VA.getLocMemOffset();
1921 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1922 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1923 if (Flags.isByVal())
1924 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1926 return DAG.getStore(Chain, dl, Arg, PtrOff,
1927 MachinePointerInfo::getStack(LocMemOffset),
1931 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1932 /// optimization is performed and it is required.
1934 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1935 SDValue &OutRetAddr, SDValue Chain,
1936 bool IsTailCall, bool Is64Bit,
1937 int FPDiff, DebugLoc dl) const {
1938 // Adjust the Return address stack slot.
1939 EVT VT = getPointerTy();
1940 OutRetAddr = getReturnAddressFrameIndex(DAG);
1942 // Load the "old" Return address.
1943 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1945 return SDValue(OutRetAddr.getNode(), 1);
1948 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1949 /// optimization is performed and it is required (FPDiff!=0).
1951 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1952 SDValue Chain, SDValue RetAddrFrIdx,
1953 bool Is64Bit, int FPDiff, DebugLoc dl) {
1954 // Store the return address to the appropriate stack slot.
1955 if (!FPDiff) return Chain;
1956 // Calculate the new stack slot for the return address.
1957 int SlotSize = Is64Bit ? 8 : 4;
1958 int NewReturnAddrFI =
1959 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1960 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1961 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1962 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1963 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1969 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1970 CallingConv::ID CallConv, bool isVarArg,
1972 const SmallVectorImpl<ISD::OutputArg> &Outs,
1973 const SmallVectorImpl<SDValue> &OutVals,
1974 const SmallVectorImpl<ISD::InputArg> &Ins,
1975 DebugLoc dl, SelectionDAG &DAG,
1976 SmallVectorImpl<SDValue> &InVals) const {
1977 MachineFunction &MF = DAG.getMachineFunction();
1978 bool Is64Bit = Subtarget->is64Bit();
1979 bool IsWin64 = Subtarget->isTargetWin64();
1980 bool IsStructRet = CallIsStructReturn(Outs);
1981 bool IsSibcall = false;
1984 // Check if it's really possible to do a tail call.
1985 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1986 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1987 Outs, OutVals, Ins, DAG);
1989 // Sibcalls are automatically detected tailcalls which do not require
1991 if (!GuaranteedTailCallOpt && isTailCall)
1998 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1999 "Var args not supported with calling convention fastcc or ghc");
2001 // Analyze operands of the call, assigning locations to each operand.
2002 SmallVector<CCValAssign, 16> ArgLocs;
2003 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2004 ArgLocs, *DAG.getContext());
2006 // Allocate shadow area for Win64
2008 CCInfo.AllocateStack(32, 8);
2011 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2013 // Get a count of how many bytes are to be pushed on the stack.
2014 unsigned NumBytes = CCInfo.getNextStackOffset();
2016 // This is a sibcall. The memory operands are available in caller's
2017 // own caller's stack.
2019 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2020 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2023 if (isTailCall && !IsSibcall) {
2024 // Lower arguments at fp - stackoffset + fpdiff.
2025 unsigned NumBytesCallerPushed =
2026 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2027 FPDiff = NumBytesCallerPushed - NumBytes;
2029 // Set the delta of movement of the returnaddr stackslot.
2030 // But only set if delta is greater than previous delta.
2031 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2032 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2036 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2038 SDValue RetAddrFrIdx;
2039 // Load return address for tail calls.
2040 if (isTailCall && FPDiff)
2041 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2042 Is64Bit, FPDiff, dl);
2044 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2045 SmallVector<SDValue, 8> MemOpChains;
2048 // Walk the register/memloc assignments, inserting copies/loads. In the case
2049 // of tail call optimization arguments are handle later.
2050 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2051 CCValAssign &VA = ArgLocs[i];
2052 EVT RegVT = VA.getLocVT();
2053 SDValue Arg = OutVals[i];
2054 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2055 bool isByVal = Flags.isByVal();
2057 // Promote the value if needed.
2058 switch (VA.getLocInfo()) {
2059 default: llvm_unreachable("Unknown loc info!");
2060 case CCValAssign::Full: break;
2061 case CCValAssign::SExt:
2062 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2064 case CCValAssign::ZExt:
2065 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2067 case CCValAssign::AExt:
2068 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2069 // Special case: passing MMX values in XMM registers.
2070 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2071 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2072 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2074 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2076 case CCValAssign::BCvt:
2077 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2079 case CCValAssign::Indirect: {
2080 // Store the argument.
2081 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2082 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2083 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2084 MachinePointerInfo::getFixedStack(FI),
2091 if (VA.isRegLoc()) {
2092 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2093 if (isVarArg && IsWin64) {
2094 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2095 // shadow reg if callee is a varargs function.
2096 unsigned ShadowReg = 0;
2097 switch (VA.getLocReg()) {
2098 case X86::XMM0: ShadowReg = X86::RCX; break;
2099 case X86::XMM1: ShadowReg = X86::RDX; break;
2100 case X86::XMM2: ShadowReg = X86::R8; break;
2101 case X86::XMM3: ShadowReg = X86::R9; break;
2104 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2106 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2107 assert(VA.isMemLoc());
2108 if (StackPtr.getNode() == 0)
2109 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2110 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2111 dl, DAG, VA, Flags));
2115 if (!MemOpChains.empty())
2116 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2117 &MemOpChains[0], MemOpChains.size());
2119 // Build a sequence of copy-to-reg nodes chained together with token chain
2120 // and flag operands which copy the outgoing args into registers.
2122 // Tail call byval lowering might overwrite argument registers so in case of
2123 // tail call optimization the copies to registers are lowered later.
2125 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2126 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2127 RegsToPass[i].second, InFlag);
2128 InFlag = Chain.getValue(1);
2131 if (Subtarget->isPICStyleGOT()) {
2132 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2135 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2136 DAG.getNode(X86ISD::GlobalBaseReg,
2137 DebugLoc(), getPointerTy()),
2139 InFlag = Chain.getValue(1);
2141 // If we are tail calling and generating PIC/GOT style code load the
2142 // address of the callee into ECX. The value in ecx is used as target of
2143 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2144 // for tail calls on PIC/GOT architectures. Normally we would just put the
2145 // address of GOT into ebx and then call target@PLT. But for tail calls
2146 // ebx would be restored (since ebx is callee saved) before jumping to the
2149 // Note: The actual moving to ECX is done further down.
2150 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2151 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2152 !G->getGlobal()->hasProtectedVisibility())
2153 Callee = LowerGlobalAddress(Callee, DAG);
2154 else if (isa<ExternalSymbolSDNode>(Callee))
2155 Callee = LowerExternalSymbol(Callee, DAG);
2159 if (Is64Bit && isVarArg && !IsWin64) {
2160 // From AMD64 ABI document:
2161 // For calls that may call functions that use varargs or stdargs
2162 // (prototype-less calls or calls to functions containing ellipsis (...) in
2163 // the declaration) %al is used as hidden argument to specify the number
2164 // of SSE registers used. The contents of %al do not need to match exactly
2165 // the number of registers, but must be an ubound on the number of SSE
2166 // registers used and is in the range 0 - 8 inclusive.
2168 // Count the number of XMM registers allocated.
2169 static const unsigned XMMArgRegs[] = {
2170 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2171 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2173 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2174 assert((Subtarget->hasXMM() || !NumXMMRegs)
2175 && "SSE registers cannot be used when SSE is disabled");
2177 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2178 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2179 InFlag = Chain.getValue(1);
2183 // For tail calls lower the arguments to the 'real' stack slot.
2185 // Force all the incoming stack arguments to be loaded from the stack
2186 // before any new outgoing arguments are stored to the stack, because the
2187 // outgoing stack slots may alias the incoming argument stack slots, and
2188 // the alias isn't otherwise explicit. This is slightly more conservative
2189 // than necessary, because it means that each store effectively depends
2190 // on every argument instead of just those arguments it would clobber.
2191 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2193 SmallVector<SDValue, 8> MemOpChains2;
2196 // Do not flag preceding copytoreg stuff together with the following stuff.
2198 if (GuaranteedTailCallOpt) {
2199 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2200 CCValAssign &VA = ArgLocs[i];
2203 assert(VA.isMemLoc());
2204 SDValue Arg = OutVals[i];
2205 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2206 // Create frame index.
2207 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2208 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2209 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2210 FIN = DAG.getFrameIndex(FI, getPointerTy());
2212 if (Flags.isByVal()) {
2213 // Copy relative to framepointer.
2214 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2215 if (StackPtr.getNode() == 0)
2216 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2218 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2220 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2224 // Store relative to framepointer.
2225 MemOpChains2.push_back(
2226 DAG.getStore(ArgChain, dl, Arg, FIN,
2227 MachinePointerInfo::getFixedStack(FI),
2233 if (!MemOpChains2.empty())
2234 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2235 &MemOpChains2[0], MemOpChains2.size());
2237 // Copy arguments to their registers.
2238 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2239 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2240 RegsToPass[i].second, InFlag);
2241 InFlag = Chain.getValue(1);
2245 // Store the return address to the appropriate stack slot.
2246 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2250 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2251 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2252 // In the 64-bit large code model, we have to make all calls
2253 // through a register, since the call instruction's 32-bit
2254 // pc-relative offset may not be large enough to hold the whole
2256 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2257 // If the callee is a GlobalAddress node (quite common, every direct call
2258 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2261 // We should use extra load for direct calls to dllimported functions in
2263 const GlobalValue *GV = G->getGlobal();
2264 if (!GV->hasDLLImportLinkage()) {
2265 unsigned char OpFlags = 0;
2266 bool ExtraLoad = false;
2267 unsigned WrapperKind = ISD::DELETED_NODE;
2269 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2270 // external symbols most go through the PLT in PIC mode. If the symbol
2271 // has hidden or protected visibility, or if it is static or local, then
2272 // we don't need to use the PLT - we can directly call it.
2273 if (Subtarget->isTargetELF() &&
2274 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2275 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2276 OpFlags = X86II::MO_PLT;
2277 } else if (Subtarget->isPICStyleStubAny() &&
2278 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2279 (!Subtarget->getTargetTriple().isMacOSX() ||
2280 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2281 // PC-relative references to external symbols should go through $stub,
2282 // unless we're building with the leopard linker or later, which
2283 // automatically synthesizes these stubs.
2284 OpFlags = X86II::MO_DARWIN_STUB;
2285 } else if (Subtarget->isPICStyleRIPRel() &&
2286 isa<Function>(GV) &&
2287 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2288 // If the function is marked as non-lazy, generate an indirect call
2289 // which loads from the GOT directly. This avoids runtime overhead
2290 // at the cost of eager binding (and one extra byte of encoding).
2291 OpFlags = X86II::MO_GOTPCREL;
2292 WrapperKind = X86ISD::WrapperRIP;
2296 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2297 G->getOffset(), OpFlags);
2299 // Add a wrapper if needed.
2300 if (WrapperKind != ISD::DELETED_NODE)
2301 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2302 // Add extra indirection if needed.
2304 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2305 MachinePointerInfo::getGOT(),
2308 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2309 unsigned char OpFlags = 0;
2311 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2312 // external symbols should go through the PLT.
2313 if (Subtarget->isTargetELF() &&
2314 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2315 OpFlags = X86II::MO_PLT;
2316 } else if (Subtarget->isPICStyleStubAny() &&
2317 (!Subtarget->getTargetTriple().isMacOSX() ||
2318 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2319 // PC-relative references to external symbols should go through $stub,
2320 // unless we're building with the leopard linker or later, which
2321 // automatically synthesizes these stubs.
2322 OpFlags = X86II::MO_DARWIN_STUB;
2325 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2329 // Returns a chain & a flag for retval copy to use.
2330 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2331 SmallVector<SDValue, 8> Ops;
2333 if (!IsSibcall && isTailCall) {
2334 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2335 DAG.getIntPtrConstant(0, true), InFlag);
2336 InFlag = Chain.getValue(1);
2339 Ops.push_back(Chain);
2340 Ops.push_back(Callee);
2343 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2345 // Add argument registers to the end of the list so that they are known live
2347 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2348 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2349 RegsToPass[i].second.getValueType()));
2351 // Add an implicit use GOT pointer in EBX.
2352 if (!isTailCall && Subtarget->isPICStyleGOT())
2353 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2355 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2356 if (Is64Bit && isVarArg && !IsWin64)
2357 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2359 if (InFlag.getNode())
2360 Ops.push_back(InFlag);
2364 //// If this is the first return lowered for this function, add the regs
2365 //// to the liveout set for the function.
2366 // This isn't right, although it's probably harmless on x86; liveouts
2367 // should be computed from returns not tail calls. Consider a void
2368 // function making a tail call to a function returning int.
2369 return DAG.getNode(X86ISD::TC_RETURN, dl,
2370 NodeTys, &Ops[0], Ops.size());
2373 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2374 InFlag = Chain.getValue(1);
2376 // Create the CALLSEQ_END node.
2377 unsigned NumBytesForCalleeToPush;
2378 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2379 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2380 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2381 // If this is a call to a struct-return function, the callee
2382 // pops the hidden struct pointer, so we have to push it back.
2383 // This is common for Darwin/X86, Linux & Mingw32 targets.
2384 NumBytesForCalleeToPush = 4;
2386 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2388 // Returns a flag for retval copy to use.
2390 Chain = DAG.getCALLSEQ_END(Chain,
2391 DAG.getIntPtrConstant(NumBytes, true),
2392 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2395 InFlag = Chain.getValue(1);
2398 // Handle result values, copying them out of physregs into vregs that we
2400 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2401 Ins, dl, DAG, InVals);
2405 //===----------------------------------------------------------------------===//
2406 // Fast Calling Convention (tail call) implementation
2407 //===----------------------------------------------------------------------===//
2409 // Like std call, callee cleans arguments, convention except that ECX is
2410 // reserved for storing the tail called function address. Only 2 registers are
2411 // free for argument passing (inreg). Tail call optimization is performed
2413 // * tailcallopt is enabled
2414 // * caller/callee are fastcc
2415 // On X86_64 architecture with GOT-style position independent code only local
2416 // (within module) calls are supported at the moment.
2417 // To keep the stack aligned according to platform abi the function
2418 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2419 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2420 // If a tail called function callee has more arguments than the caller the
2421 // caller needs to make sure that there is room to move the RETADDR to. This is
2422 // achieved by reserving an area the size of the argument delta right after the
2423 // original REtADDR, but before the saved framepointer or the spilled registers
2424 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2436 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2437 /// for a 16 byte align requirement.
2439 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2440 SelectionDAG& DAG) const {
2441 MachineFunction &MF = DAG.getMachineFunction();
2442 const TargetMachine &TM = MF.getTarget();
2443 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2444 unsigned StackAlignment = TFI.getStackAlignment();
2445 uint64_t AlignMask = StackAlignment - 1;
2446 int64_t Offset = StackSize;
2447 uint64_t SlotSize = TD->getPointerSize();
2448 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2449 // Number smaller than 12 so just add the difference.
2450 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2452 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2453 Offset = ((~AlignMask) & Offset) + StackAlignment +
2454 (StackAlignment-SlotSize);
2459 /// MatchingStackOffset - Return true if the given stack call argument is
2460 /// already available in the same position (relatively) of the caller's
2461 /// incoming argument stack.
2463 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2464 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2465 const X86InstrInfo *TII) {
2466 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2468 if (Arg.getOpcode() == ISD::CopyFromReg) {
2469 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2470 if (!TargetRegisterInfo::isVirtualRegister(VR))
2472 MachineInstr *Def = MRI->getVRegDef(VR);
2475 if (!Flags.isByVal()) {
2476 if (!TII->isLoadFromStackSlot(Def, FI))
2479 unsigned Opcode = Def->getOpcode();
2480 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2481 Def->getOperand(1).isFI()) {
2482 FI = Def->getOperand(1).getIndex();
2483 Bytes = Flags.getByValSize();
2487 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2488 if (Flags.isByVal())
2489 // ByVal argument is passed in as a pointer but it's now being
2490 // dereferenced. e.g.
2491 // define @foo(%struct.X* %A) {
2492 // tail call @bar(%struct.X* byval %A)
2495 SDValue Ptr = Ld->getBasePtr();
2496 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2499 FI = FINode->getIndex();
2500 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2501 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2502 FI = FINode->getIndex();
2503 Bytes = Flags.getByValSize();
2507 assert(FI != INT_MAX);
2508 if (!MFI->isFixedObjectIndex(FI))
2510 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2513 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2514 /// for tail call optimization. Targets which want to do tail call
2515 /// optimization should implement this function.
2517 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2518 CallingConv::ID CalleeCC,
2520 bool isCalleeStructRet,
2521 bool isCallerStructRet,
2522 const SmallVectorImpl<ISD::OutputArg> &Outs,
2523 const SmallVectorImpl<SDValue> &OutVals,
2524 const SmallVectorImpl<ISD::InputArg> &Ins,
2525 SelectionDAG& DAG) const {
2526 if (!IsTailCallConvention(CalleeCC) &&
2527 CalleeCC != CallingConv::C)
2530 // If -tailcallopt is specified, make fastcc functions tail-callable.
2531 const MachineFunction &MF = DAG.getMachineFunction();
2532 const Function *CallerF = DAG.getMachineFunction().getFunction();
2533 CallingConv::ID CallerCC = CallerF->getCallingConv();
2534 bool CCMatch = CallerCC == CalleeCC;
2536 if (GuaranteedTailCallOpt) {
2537 if (IsTailCallConvention(CalleeCC) && CCMatch)
2542 // Look for obvious safe cases to perform tail call optimization that do not
2543 // require ABI changes. This is what gcc calls sibcall.
2545 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2546 // emit a special epilogue.
2547 if (RegInfo->needsStackRealignment(MF))
2550 // Also avoid sibcall optimization if either caller or callee uses struct
2551 // return semantics.
2552 if (isCalleeStructRet || isCallerStructRet)
2555 // An stdcall caller is expected to clean up its arguments; the callee
2556 // isn't going to do that.
2557 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2560 // Do not sibcall optimize vararg calls unless all arguments are passed via
2562 if (isVarArg && !Outs.empty()) {
2564 // Optimizing for varargs on Win64 is unlikely to be safe without
2565 // additional testing.
2566 if (Subtarget->isTargetWin64())
2569 SmallVector<CCValAssign, 16> ArgLocs;
2570 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2571 getTargetMachine(), ArgLocs, *DAG.getContext());
2573 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2574 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2575 if (!ArgLocs[i].isRegLoc())
2579 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2580 // Therefore if it's not used by the call it is not safe to optimize this into
2582 bool Unused = false;
2583 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2590 SmallVector<CCValAssign, 16> RVLocs;
2591 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2592 getTargetMachine(), RVLocs, *DAG.getContext());
2593 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2594 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2595 CCValAssign &VA = RVLocs[i];
2596 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2601 // If the calling conventions do not match, then we'd better make sure the
2602 // results are returned in the same way as what the caller expects.
2604 SmallVector<CCValAssign, 16> RVLocs1;
2605 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2606 getTargetMachine(), RVLocs1, *DAG.getContext());
2607 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2609 SmallVector<CCValAssign, 16> RVLocs2;
2610 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2611 getTargetMachine(), RVLocs2, *DAG.getContext());
2612 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2614 if (RVLocs1.size() != RVLocs2.size())
2616 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2617 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2619 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2621 if (RVLocs1[i].isRegLoc()) {
2622 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2625 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2631 // If the callee takes no arguments then go on to check the results of the
2633 if (!Outs.empty()) {
2634 // Check if stack adjustment is needed. For now, do not do this if any
2635 // argument is passed on the stack.
2636 SmallVector<CCValAssign, 16> ArgLocs;
2637 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2638 getTargetMachine(), ArgLocs, *DAG.getContext());
2640 // Allocate shadow area for Win64
2641 if (Subtarget->isTargetWin64()) {
2642 CCInfo.AllocateStack(32, 8);
2645 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2646 if (CCInfo.getNextStackOffset()) {
2647 MachineFunction &MF = DAG.getMachineFunction();
2648 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2651 // Check if the arguments are already laid out in the right way as
2652 // the caller's fixed stack objects.
2653 MachineFrameInfo *MFI = MF.getFrameInfo();
2654 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2655 const X86InstrInfo *TII =
2656 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2657 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2658 CCValAssign &VA = ArgLocs[i];
2659 SDValue Arg = OutVals[i];
2660 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2661 if (VA.getLocInfo() == CCValAssign::Indirect)
2663 if (!VA.isRegLoc()) {
2664 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2671 // If the tailcall address may be in a register, then make sure it's
2672 // possible to register allocate for it. In 32-bit, the call address can
2673 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2674 // callee-saved registers are restored. These happen to be the same
2675 // registers used to pass 'inreg' arguments so watch out for those.
2676 if (!Subtarget->is64Bit() &&
2677 !isa<GlobalAddressSDNode>(Callee) &&
2678 !isa<ExternalSymbolSDNode>(Callee)) {
2679 unsigned NumInRegs = 0;
2680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2681 CCValAssign &VA = ArgLocs[i];
2684 unsigned Reg = VA.getLocReg();
2687 case X86::EAX: case X86::EDX: case X86::ECX:
2688 if (++NumInRegs == 3)
2700 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2701 return X86::createFastISel(funcInfo);
2705 //===----------------------------------------------------------------------===//
2706 // Other Lowering Hooks
2707 //===----------------------------------------------------------------------===//
2709 static bool MayFoldLoad(SDValue Op) {
2710 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2713 static bool MayFoldIntoStore(SDValue Op) {
2714 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2717 static bool isTargetShuffle(unsigned Opcode) {
2719 default: return false;
2720 case X86ISD::PSHUFD:
2721 case X86ISD::PSHUFHW:
2722 case X86ISD::PSHUFLW:
2723 case X86ISD::SHUFPD:
2724 case X86ISD::PALIGN:
2725 case X86ISD::SHUFPS:
2726 case X86ISD::MOVLHPS:
2727 case X86ISD::MOVLHPD:
2728 case X86ISD::MOVHLPS:
2729 case X86ISD::MOVLPS:
2730 case X86ISD::MOVLPD:
2731 case X86ISD::MOVSHDUP:
2732 case X86ISD::MOVSLDUP:
2733 case X86ISD::MOVDDUP:
2736 case X86ISD::UNPCKLPS:
2737 case X86ISD::UNPCKLPD:
2738 case X86ISD::VUNPCKLPSY:
2739 case X86ISD::VUNPCKLPDY:
2740 case X86ISD::PUNPCKLWD:
2741 case X86ISD::PUNPCKLBW:
2742 case X86ISD::PUNPCKLDQ:
2743 case X86ISD::PUNPCKLQDQ:
2744 case X86ISD::UNPCKHPS:
2745 case X86ISD::UNPCKHPD:
2746 case X86ISD::VUNPCKHPSY:
2747 case X86ISD::VUNPCKHPDY:
2748 case X86ISD::PUNPCKHWD:
2749 case X86ISD::PUNPCKHBW:
2750 case X86ISD::PUNPCKHDQ:
2751 case X86ISD::PUNPCKHQDQ:
2752 case X86ISD::VPERMILPS:
2753 case X86ISD::VPERMILPSY:
2754 case X86ISD::VPERMILPD:
2755 case X86ISD::VPERMILPDY:
2756 case X86ISD::VPERM2F128:
2762 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2763 SDValue V1, SelectionDAG &DAG) {
2765 default: llvm_unreachable("Unknown x86 shuffle node");
2766 case X86ISD::MOVSHDUP:
2767 case X86ISD::MOVSLDUP:
2768 case X86ISD::MOVDDUP:
2769 return DAG.getNode(Opc, dl, VT, V1);
2775 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2776 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2778 default: llvm_unreachable("Unknown x86 shuffle node");
2779 case X86ISD::PSHUFD:
2780 case X86ISD::PSHUFHW:
2781 case X86ISD::PSHUFLW:
2782 case X86ISD::VPERMILPS:
2783 case X86ISD::VPERMILPSY:
2784 case X86ISD::VPERMILPD:
2785 case X86ISD::VPERMILPDY:
2786 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2792 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2793 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2795 default: llvm_unreachable("Unknown x86 shuffle node");
2796 case X86ISD::PALIGN:
2797 case X86ISD::SHUFPD:
2798 case X86ISD::SHUFPS:
2799 case X86ISD::VPERM2F128:
2800 return DAG.getNode(Opc, dl, VT, V1, V2,
2801 DAG.getConstant(TargetMask, MVT::i8));
2806 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2807 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2809 default: llvm_unreachable("Unknown x86 shuffle node");
2810 case X86ISD::MOVLHPS:
2811 case X86ISD::MOVLHPD:
2812 case X86ISD::MOVHLPS:
2813 case X86ISD::MOVLPS:
2814 case X86ISD::MOVLPD:
2817 case X86ISD::UNPCKLPS:
2818 case X86ISD::UNPCKLPD:
2819 case X86ISD::VUNPCKLPSY:
2820 case X86ISD::VUNPCKLPDY:
2821 case X86ISD::PUNPCKLWD:
2822 case X86ISD::PUNPCKLBW:
2823 case X86ISD::PUNPCKLDQ:
2824 case X86ISD::PUNPCKLQDQ:
2825 case X86ISD::UNPCKHPS:
2826 case X86ISD::UNPCKHPD:
2827 case X86ISD::VUNPCKHPSY:
2828 case X86ISD::VUNPCKHPDY:
2829 case X86ISD::PUNPCKHWD:
2830 case X86ISD::PUNPCKHBW:
2831 case X86ISD::PUNPCKHDQ:
2832 case X86ISD::PUNPCKHQDQ:
2833 return DAG.getNode(Opc, dl, VT, V1, V2);
2838 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2839 MachineFunction &MF = DAG.getMachineFunction();
2840 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2841 int ReturnAddrIndex = FuncInfo->getRAIndex();
2843 if (ReturnAddrIndex == 0) {
2844 // Set up a frame object for the return address.
2845 uint64_t SlotSize = TD->getPointerSize();
2846 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2848 FuncInfo->setRAIndex(ReturnAddrIndex);
2851 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2855 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2856 bool hasSymbolicDisplacement) {
2857 // Offset should fit into 32 bit immediate field.
2858 if (!isInt<32>(Offset))
2861 // If we don't have a symbolic displacement - we don't have any extra
2863 if (!hasSymbolicDisplacement)
2866 // FIXME: Some tweaks might be needed for medium code model.
2867 if (M != CodeModel::Small && M != CodeModel::Kernel)
2870 // For small code model we assume that latest object is 16MB before end of 31
2871 // bits boundary. We may also accept pretty large negative constants knowing
2872 // that all objects are in the positive half of address space.
2873 if (M == CodeModel::Small && Offset < 16*1024*1024)
2876 // For kernel code model we know that all object resist in the negative half
2877 // of 32bits address space. We may not accept negative offsets, since they may
2878 // be just off and we may accept pretty large positive ones.
2879 if (M == CodeModel::Kernel && Offset > 0)
2885 /// isCalleePop - Determines whether the callee is required to pop its
2886 /// own arguments. Callee pop is necessary to support tail calls.
2887 bool X86::isCalleePop(CallingConv::ID CallingConv,
2888 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2892 switch (CallingConv) {
2895 case CallingConv::X86_StdCall:
2897 case CallingConv::X86_FastCall:
2899 case CallingConv::X86_ThisCall:
2901 case CallingConv::Fast:
2903 case CallingConv::GHC:
2908 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2909 /// specific condition code, returning the condition code and the LHS/RHS of the
2910 /// comparison to make.
2911 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2912 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2914 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2915 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2916 // X > -1 -> X == 0, jump !sign.
2917 RHS = DAG.getConstant(0, RHS.getValueType());
2918 return X86::COND_NS;
2919 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2920 // X < 0 -> X == 0, jump on sign.
2922 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2924 RHS = DAG.getConstant(0, RHS.getValueType());
2925 return X86::COND_LE;
2929 switch (SetCCOpcode) {
2930 default: llvm_unreachable("Invalid integer condition!");
2931 case ISD::SETEQ: return X86::COND_E;
2932 case ISD::SETGT: return X86::COND_G;
2933 case ISD::SETGE: return X86::COND_GE;
2934 case ISD::SETLT: return X86::COND_L;
2935 case ISD::SETLE: return X86::COND_LE;
2936 case ISD::SETNE: return X86::COND_NE;
2937 case ISD::SETULT: return X86::COND_B;
2938 case ISD::SETUGT: return X86::COND_A;
2939 case ISD::SETULE: return X86::COND_BE;
2940 case ISD::SETUGE: return X86::COND_AE;
2944 // First determine if it is required or is profitable to flip the operands.
2946 // If LHS is a foldable load, but RHS is not, flip the condition.
2947 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2948 !ISD::isNON_EXTLoad(RHS.getNode())) {
2949 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2950 std::swap(LHS, RHS);
2953 switch (SetCCOpcode) {
2959 std::swap(LHS, RHS);
2963 // On a floating point condition, the flags are set as follows:
2965 // 0 | 0 | 0 | X > Y
2966 // 0 | 0 | 1 | X < Y
2967 // 1 | 0 | 0 | X == Y
2968 // 1 | 1 | 1 | unordered
2969 switch (SetCCOpcode) {
2970 default: llvm_unreachable("Condcode should be pre-legalized away");
2972 case ISD::SETEQ: return X86::COND_E;
2973 case ISD::SETOLT: // flipped
2975 case ISD::SETGT: return X86::COND_A;
2976 case ISD::SETOLE: // flipped
2978 case ISD::SETGE: return X86::COND_AE;
2979 case ISD::SETUGT: // flipped
2981 case ISD::SETLT: return X86::COND_B;
2982 case ISD::SETUGE: // flipped
2984 case ISD::SETLE: return X86::COND_BE;
2986 case ISD::SETNE: return X86::COND_NE;
2987 case ISD::SETUO: return X86::COND_P;
2988 case ISD::SETO: return X86::COND_NP;
2990 case ISD::SETUNE: return X86::COND_INVALID;
2994 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2995 /// code. Current x86 isa includes the following FP cmov instructions:
2996 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2997 static bool hasFPCMov(unsigned X86CC) {
3013 /// isFPImmLegal - Returns true if the target can instruction select the
3014 /// specified FP immediate natively. If false, the legalizer will
3015 /// materialize the FP immediate as a load from a constant pool.
3016 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3017 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3018 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3024 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3025 /// the specified range (L, H].
3026 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3027 return (Val < 0) || (Val >= Low && Val < Hi);
3030 /// isUndefOrInRange - Return true if every element in Mask, begining
3031 /// from position Pos and ending in Pos+Size, falls within the specified
3032 /// range (L, L+Pos]. or is undef.
3033 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3034 int Pos, int Size, int Low, int Hi) {
3035 for (int i = Pos, e = Pos+Size; i != e; ++i)
3036 if (!isUndefOrInRange(Mask[i], Low, Hi))
3041 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3042 /// specified value.
3043 static bool isUndefOrEqual(int Val, int CmpVal) {
3044 if (Val < 0 || Val == CmpVal)
3049 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3050 /// from position Pos and ending in Pos+Size, falls within the specified
3051 /// sequential range (L, L+Pos]. or is undef.
3052 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3053 int Pos, int Size, int Low) {
3054 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3055 if (!isUndefOrEqual(Mask[i], Low))
3060 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3061 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3062 /// the second operand.
3063 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3064 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3065 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3066 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3067 return (Mask[0] < 2 && Mask[1] < 2);
3071 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3072 SmallVector<int, 8> M;
3074 return ::isPSHUFDMask(M, N->getValueType(0));
3077 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3078 /// is suitable for input to PSHUFHW.
3079 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3080 if (VT != MVT::v8i16)
3083 // Lower quadword copied in order or undef.
3084 for (int i = 0; i != 4; ++i)
3085 if (Mask[i] >= 0 && Mask[i] != i)
3088 // Upper quadword shuffled.
3089 for (int i = 4; i != 8; ++i)
3090 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3096 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3097 SmallVector<int, 8> M;
3099 return ::isPSHUFHWMask(M, N->getValueType(0));
3102 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3103 /// is suitable for input to PSHUFLW.
3104 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3105 if (VT != MVT::v8i16)
3108 // Upper quadword copied in order.
3109 for (int i = 4; i != 8; ++i)
3110 if (Mask[i] >= 0 && Mask[i] != i)
3113 // Lower quadword shuffled.
3114 for (int i = 0; i != 4; ++i)
3121 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3122 SmallVector<int, 8> M;
3124 return ::isPSHUFLWMask(M, N->getValueType(0));
3127 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3128 /// is suitable for input to PALIGNR.
3129 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3131 int i, e = VT.getVectorNumElements();
3132 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3135 // Do not handle v2i64 / v2f64 shuffles with palignr.
3136 if (e < 4 || !hasSSSE3)
3139 for (i = 0; i != e; ++i)
3143 // All undef, not a palignr.
3147 // Make sure we're shifting in the right direction.
3151 int s = Mask[i] - i;
3153 // Check the rest of the elements to see if they are consecutive.
3154 for (++i; i != e; ++i) {
3156 if (m >= 0 && m != s+i)
3162 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3163 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
3164 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3165 int NumElems = VT.getVectorNumElements();
3166 if (NumElems != 2 && NumElems != 4)
3169 int Half = NumElems / 2;
3170 for (int i = 0; i < Half; ++i)
3171 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3173 for (int i = Half; i < NumElems; ++i)
3174 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3180 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3181 SmallVector<int, 8> M;
3183 return ::isSHUFPMask(M, N->getValueType(0));
3186 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3187 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3188 /// half elements to come from vector 1 (which would equal the dest.) and
3189 /// the upper half to come from vector 2.
3190 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3191 int NumElems = VT.getVectorNumElements();
3193 if (NumElems != 2 && NumElems != 4)
3196 int Half = NumElems / 2;
3197 for (int i = 0; i < Half; ++i)
3198 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3200 for (int i = Half; i < NumElems; ++i)
3201 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3206 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3207 SmallVector<int, 8> M;
3209 return isCommutedSHUFPMask(M, N->getValueType(0));
3212 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3213 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3214 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3215 EVT VT = N->getValueType(0);
3216 unsigned NumElems = VT.getVectorNumElements();
3218 if (VT.getSizeInBits() != 128)
3224 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3225 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3226 isUndefOrEqual(N->getMaskElt(1), 7) &&
3227 isUndefOrEqual(N->getMaskElt(2), 2) &&
3228 isUndefOrEqual(N->getMaskElt(3), 3);
3231 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3232 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3234 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3235 EVT VT = N->getValueType(0);
3236 unsigned NumElems = VT.getVectorNumElements();
3238 if (VT.getSizeInBits() != 128)
3244 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3245 isUndefOrEqual(N->getMaskElt(1), 3) &&
3246 isUndefOrEqual(N->getMaskElt(2), 2) &&
3247 isUndefOrEqual(N->getMaskElt(3), 3);
3250 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3251 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3252 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3253 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3255 if (NumElems != 2 && NumElems != 4)
3258 for (unsigned i = 0; i < NumElems/2; ++i)
3259 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3262 for (unsigned i = NumElems/2; i < NumElems; ++i)
3263 if (!isUndefOrEqual(N->getMaskElt(i), i))
3269 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3270 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3271 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3272 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3274 if ((NumElems != 2 && NumElems != 4)
3275 || N->getValueType(0).getSizeInBits() > 128)
3278 for (unsigned i = 0; i < NumElems/2; ++i)
3279 if (!isUndefOrEqual(N->getMaskElt(i), i))
3282 for (unsigned i = 0; i < NumElems/2; ++i)
3283 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3289 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3290 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3291 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3292 bool V2IsSplat = false) {
3293 int NumElts = VT.getVectorNumElements();
3295 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3296 "Unsupported vector type for unpckh");
3298 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3301 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3302 // independently on 128-bit lanes.
3303 unsigned NumLanes = VT.getSizeInBits()/128;
3304 unsigned NumLaneElts = NumElts/NumLanes;
3307 unsigned End = NumLaneElts;
3308 for (unsigned s = 0; s < NumLanes; ++s) {
3309 for (unsigned i = Start, j = s * NumLaneElts;
3313 int BitI1 = Mask[i+1];
3314 if (!isUndefOrEqual(BitI, j))
3317 if (!isUndefOrEqual(BitI1, NumElts))
3320 if (!isUndefOrEqual(BitI1, j + NumElts))
3324 // Process the next 128 bits.
3325 Start += NumLaneElts;
3332 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3333 SmallVector<int, 8> M;
3335 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3338 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3339 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3340 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3341 bool V2IsSplat = false) {
3342 int NumElts = VT.getVectorNumElements();
3344 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3345 "Unsupported vector type for unpckh");
3347 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3350 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3351 // independently on 128-bit lanes.
3352 unsigned NumLanes = VT.getSizeInBits()/128;
3353 unsigned NumLaneElts = NumElts/NumLanes;
3356 unsigned End = NumLaneElts;
3357 for (unsigned l = 0; l != NumLanes; ++l) {
3358 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3359 i != End; i += 2, ++j) {
3361 int BitI1 = Mask[i+1];
3362 if (!isUndefOrEqual(BitI, j))
3365 if (isUndefOrEqual(BitI1, NumElts))
3368 if (!isUndefOrEqual(BitI1, j+NumElts))
3372 // Process the next 128 bits.
3373 Start += NumLaneElts;
3379 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3380 SmallVector<int, 8> M;
3382 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3385 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3386 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3388 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3389 int NumElems = VT.getVectorNumElements();
3390 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3393 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3394 // independently on 128-bit lanes.
3395 unsigned NumLanes = VT.getSizeInBits() / 128;
3396 unsigned NumLaneElts = NumElems / NumLanes;
3398 for (unsigned s = 0; s < NumLanes; ++s) {
3399 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3400 i != NumLaneElts * (s + 1);
3403 int BitI1 = Mask[i+1];
3405 if (!isUndefOrEqual(BitI, j))
3407 if (!isUndefOrEqual(BitI1, j))
3415 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3416 SmallVector<int, 8> M;
3418 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3421 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3422 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3424 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3425 int NumElems = VT.getVectorNumElements();
3426 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3429 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3431 int BitI1 = Mask[i+1];
3432 if (!isUndefOrEqual(BitI, j))
3434 if (!isUndefOrEqual(BitI1, j))
3440 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3441 SmallVector<int, 8> M;
3443 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3446 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3447 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3448 /// MOVSD, and MOVD, i.e. setting the lowest element.
3449 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3450 if (VT.getVectorElementType().getSizeInBits() < 32)
3453 int NumElts = VT.getVectorNumElements();
3455 if (!isUndefOrEqual(Mask[0], NumElts))
3458 for (int i = 1; i < NumElts; ++i)
3459 if (!isUndefOrEqual(Mask[i], i))
3465 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3466 SmallVector<int, 8> M;
3468 return ::isMOVLMask(M, N->getValueType(0));
3471 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3472 /// as permutations between 128-bit chunks or halves. As an example: this
3474 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3475 /// The first half comes from the second half of V1 and the second half from the
3476 /// the second half of V2.
3477 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3478 const X86Subtarget *Subtarget) {
3479 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3482 // The shuffle result is divided into half A and half B. In total the two
3483 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3484 // B must come from C, D, E or F.
3485 int HalfSize = VT.getVectorNumElements()/2;
3486 bool MatchA = false, MatchB = false;
3488 // Check if A comes from one of C, D, E, F.
3489 for (int Half = 0; Half < 4; ++Half) {
3490 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3496 // Check if B comes from one of C, D, E, F.
3497 for (int Half = 0; Half < 4; ++Half) {
3498 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3504 return MatchA && MatchB;
3507 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3508 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3509 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3510 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3511 EVT VT = SVOp->getValueType(0);
3513 int HalfSize = VT.getVectorNumElements()/2;
3515 int FstHalf = 0, SndHalf = 0;
3516 for (int i = 0; i < HalfSize; ++i) {
3517 if (SVOp->getMaskElt(i) > 0) {
3518 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3522 for (int i = HalfSize; i < HalfSize*2; ++i) {
3523 if (SVOp->getMaskElt(i) > 0) {
3524 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3529 return (FstHalf | (SndHalf << 4));
3532 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3533 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3534 /// Note that VPERMIL mask matching is different depending whether theunderlying
3535 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3536 /// to the same elements of the low, but to the higher half of the source.
3537 /// In VPERMILPD the two lanes could be shuffled independently of each other
3538 /// with the same restriction that lanes can't be crossed.
3539 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3540 const X86Subtarget *Subtarget) {
3541 int NumElts = VT.getVectorNumElements();
3542 int NumLanes = VT.getSizeInBits()/128;
3544 if (!Subtarget->hasAVX())
3547 // Match any permutation of 128-bit vector with 64-bit types
3548 if (NumLanes == 1 && NumElts != 2)
3551 // Only match 256-bit with 32 types
3552 if (VT.getSizeInBits() == 256 && NumElts != 4)
3555 // The mask on the high lane is independent of the low. Both can match
3556 // any element in inside its own lane, but can't cross.
3557 int LaneSize = NumElts/NumLanes;
3558 for (int l = 0; l < NumLanes; ++l)
3559 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3560 int LaneStart = l*LaneSize;
3561 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3568 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3569 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3570 /// Note that VPERMIL mask matching is different depending whether theunderlying
3571 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3572 /// to the same elements of the low, but to the higher half of the source.
3573 /// In VPERMILPD the two lanes could be shuffled independently of each other
3574 /// with the same restriction that lanes can't be crossed.
3575 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3576 const X86Subtarget *Subtarget) {
3577 unsigned NumElts = VT.getVectorNumElements();
3578 unsigned NumLanes = VT.getSizeInBits()/128;
3580 if (!Subtarget->hasAVX())
3583 // Match any permutation of 128-bit vector with 32-bit types
3584 if (NumLanes == 1 && NumElts != 4)
3587 // Only match 256-bit with 32 types
3588 if (VT.getSizeInBits() == 256 && NumElts != 8)
3591 // The mask on the high lane should be the same as the low. Actually,
3592 // they can differ if any of the corresponding index in a lane is undef
3593 // and the other stays in range.
3594 int LaneSize = NumElts/NumLanes;
3595 for (int i = 0; i < LaneSize; ++i) {
3596 int HighElt = i+LaneSize;
3597 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3598 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3600 if (!HighValid || !LowValid)
3602 if (Mask[i] < 0 || Mask[HighElt] < 0)
3604 if (Mask[HighElt]-Mask[i] != LaneSize)
3611 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3612 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3613 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3614 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3615 EVT VT = SVOp->getValueType(0);
3617 int NumElts = VT.getVectorNumElements();
3618 int NumLanes = VT.getSizeInBits()/128;
3619 int LaneSize = NumElts/NumLanes;
3621 // Although the mask is equal for both lanes do it twice to get the cases
3622 // where a mask will match because the same mask element is undef on the
3623 // first half but valid on the second. This would get pathological cases
3624 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3626 for (int l = 0; l < NumLanes; ++l) {
3627 for (int i = 0; i < LaneSize; ++i) {
3628 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3631 if (MaskElt >= LaneSize)
3632 MaskElt -= LaneSize;
3633 Mask |= MaskElt << (i*2);
3640 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3641 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3642 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3643 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3644 EVT VT = SVOp->getValueType(0);
3646 int NumElts = VT.getVectorNumElements();
3647 int NumLanes = VT.getSizeInBits()/128;
3650 int LaneSize = NumElts/NumLanes;
3651 for (int l = 0; l < NumLanes; ++l)
3652 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3653 int MaskElt = SVOp->getMaskElt(i);
3656 Mask |= (MaskElt-l*LaneSize) << i;
3662 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3663 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3664 /// element of vector 2 and the other elements to come from vector 1 in order.
3665 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3666 bool V2IsSplat = false, bool V2IsUndef = false) {
3667 int NumOps = VT.getVectorNumElements();
3668 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3671 if (!isUndefOrEqual(Mask[0], 0))
3674 for (int i = 1; i < NumOps; ++i)
3675 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3676 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3677 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3683 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3684 bool V2IsUndef = false) {
3685 SmallVector<int, 8> M;
3687 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3690 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3691 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3692 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3693 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3694 const X86Subtarget *Subtarget) {
3695 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3698 // The second vector must be undef
3699 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3702 EVT VT = N->getValueType(0);
3703 unsigned NumElems = VT.getVectorNumElements();
3705 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3706 (VT.getSizeInBits() == 256 && NumElems != 8))
3709 // "i+1" is the value the indexed mask element must have
3710 for (unsigned i = 0; i < NumElems; i += 2)
3711 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3712 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3718 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3719 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3720 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3721 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3722 const X86Subtarget *Subtarget) {
3723 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3726 // The second vector must be undef
3727 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3730 EVT VT = N->getValueType(0);
3731 unsigned NumElems = VT.getVectorNumElements();
3733 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3734 (VT.getSizeInBits() == 256 && NumElems != 8))
3737 // "i" is the value the indexed mask element must have
3738 for (unsigned i = 0; i < NumElems; i += 2)
3739 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3740 !isUndefOrEqual(N->getMaskElt(i+1), i))
3746 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3747 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3748 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3749 int e = N->getValueType(0).getVectorNumElements() / 2;
3751 for (int i = 0; i < e; ++i)
3752 if (!isUndefOrEqual(N->getMaskElt(i), i))
3754 for (int i = 0; i < e; ++i)
3755 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3760 /// isVEXTRACTF128Index - Return true if the specified
3761 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3762 /// suitable for input to VEXTRACTF128.
3763 bool X86::isVEXTRACTF128Index(SDNode *N) {
3764 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3767 // The index should be aligned on a 128-bit boundary.
3769 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3771 unsigned VL = N->getValueType(0).getVectorNumElements();
3772 unsigned VBits = N->getValueType(0).getSizeInBits();
3773 unsigned ElSize = VBits / VL;
3774 bool Result = (Index * ElSize) % 128 == 0;
3779 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3780 /// operand specifies a subvector insert that is suitable for input to
3782 bool X86::isVINSERTF128Index(SDNode *N) {
3783 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3786 // The index should be aligned on a 128-bit boundary.
3788 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3790 unsigned VL = N->getValueType(0).getVectorNumElements();
3791 unsigned VBits = N->getValueType(0).getSizeInBits();
3792 unsigned ElSize = VBits / VL;
3793 bool Result = (Index * ElSize) % 128 == 0;
3798 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3799 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3800 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3801 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3802 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3804 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3806 for (int i = 0; i < NumOperands; ++i) {
3807 int Val = SVOp->getMaskElt(NumOperands-i-1);
3808 if (Val < 0) Val = 0;
3809 if (Val >= NumOperands) Val -= NumOperands;
3811 if (i != NumOperands - 1)
3817 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3818 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3819 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3820 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3822 // 8 nodes, but we only care about the last 4.
3823 for (unsigned i = 7; i >= 4; --i) {
3824 int Val = SVOp->getMaskElt(i);
3833 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3834 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3835 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3836 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3838 // 8 nodes, but we only care about the first 4.
3839 for (int i = 3; i >= 0; --i) {
3840 int Val = SVOp->getMaskElt(i);
3849 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3850 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3851 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3852 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3853 EVT VVT = N->getValueType(0);
3854 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3858 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3859 Val = SVOp->getMaskElt(i);
3863 assert(Val - i > 0 && "PALIGNR imm should be positive");
3864 return (Val - i) * EltSize;
3867 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3868 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3870 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3871 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3872 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3875 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3877 EVT VecVT = N->getOperand(0).getValueType();
3878 EVT ElVT = VecVT.getVectorElementType();
3880 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3881 return Index / NumElemsPerChunk;
3884 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3885 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3887 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3888 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3889 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3892 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3894 EVT VecVT = N->getValueType(0);
3895 EVT ElVT = VecVT.getVectorElementType();
3897 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3898 return Index / NumElemsPerChunk;
3901 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3903 bool X86::isZeroNode(SDValue Elt) {
3904 return ((isa<ConstantSDNode>(Elt) &&
3905 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3906 (isa<ConstantFPSDNode>(Elt) &&
3907 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3910 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3911 /// their permute mask.
3912 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3913 SelectionDAG &DAG) {
3914 EVT VT = SVOp->getValueType(0);
3915 unsigned NumElems = VT.getVectorNumElements();
3916 SmallVector<int, 8> MaskVec;
3918 for (unsigned i = 0; i != NumElems; ++i) {
3919 int idx = SVOp->getMaskElt(i);
3921 MaskVec.push_back(idx);
3922 else if (idx < (int)NumElems)
3923 MaskVec.push_back(idx + NumElems);
3925 MaskVec.push_back(idx - NumElems);
3927 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3928 SVOp->getOperand(0), &MaskVec[0]);
3931 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3932 /// the two vector operands have swapped position.
3933 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3934 unsigned NumElems = VT.getVectorNumElements();
3935 for (unsigned i = 0; i != NumElems; ++i) {
3939 else if (idx < (int)NumElems)
3940 Mask[i] = idx + NumElems;
3942 Mask[i] = idx - NumElems;
3946 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3947 /// match movhlps. The lower half elements should come from upper half of
3948 /// V1 (and in order), and the upper half elements should come from the upper
3949 /// half of V2 (and in order).
3950 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3951 EVT VT = Op->getValueType(0);
3952 if (VT.getSizeInBits() != 128)
3954 if (VT.getVectorNumElements() != 4)
3956 for (unsigned i = 0, e = 2; i != e; ++i)
3957 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3959 for (unsigned i = 2; i != 4; ++i)
3960 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3965 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3966 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3968 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3969 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3971 N = N->getOperand(0).getNode();
3972 if (!ISD::isNON_EXTLoad(N))
3975 *LD = cast<LoadSDNode>(N);
3979 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3980 /// match movlp{s|d}. The lower half elements should come from lower half of
3981 /// V1 (and in order), and the upper half elements should come from the upper
3982 /// half of V2 (and in order). And since V1 will become the source of the
3983 /// MOVLP, it must be either a vector load or a scalar load to vector.
3984 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3985 ShuffleVectorSDNode *Op) {
3986 EVT VT = Op->getValueType(0);
3987 if (VT.getSizeInBits() != 128)
3990 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3992 // Is V2 is a vector load, don't do this transformation. We will try to use
3993 // load folding shufps op.
3994 if (ISD::isNON_EXTLoad(V2))
3997 unsigned NumElems = VT.getVectorNumElements();
3999 if (NumElems != 2 && NumElems != 4)
4001 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4002 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4004 for (unsigned i = NumElems/2; i != NumElems; ++i)
4005 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4010 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4012 static bool isSplatVector(SDNode *N) {
4013 if (N->getOpcode() != ISD::BUILD_VECTOR)
4016 SDValue SplatValue = N->getOperand(0);
4017 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4018 if (N->getOperand(i) != SplatValue)
4023 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4024 /// to an zero vector.
4025 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4026 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4027 SDValue V1 = N->getOperand(0);
4028 SDValue V2 = N->getOperand(1);
4029 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4030 for (unsigned i = 0; i != NumElems; ++i) {
4031 int Idx = N->getMaskElt(i);
4032 if (Idx >= (int)NumElems) {
4033 unsigned Opc = V2.getOpcode();
4034 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4036 if (Opc != ISD::BUILD_VECTOR ||
4037 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4039 } else if (Idx >= 0) {
4040 unsigned Opc = V1.getOpcode();
4041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4043 if (Opc != ISD::BUILD_VECTOR ||
4044 !X86::isZeroNode(V1.getOperand(Idx)))
4051 /// getZeroVector - Returns a vector of specified type with all zero elements.
4053 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4055 assert(VT.isVector() && "Expected a vector type");
4057 // Always build SSE zero vectors as <4 x i32> bitcasted
4058 // to their dest type. This ensures they get CSE'd.
4060 if (VT.getSizeInBits() == 128) { // SSE
4061 if (HasSSE2) { // SSE2
4062 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4063 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4065 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4066 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4068 } else if (VT.getSizeInBits() == 256) { // AVX
4069 // 256-bit logic and arithmetic instructions in AVX are
4070 // all floating-point, no support for integer ops. Default
4071 // to emitting fp zeroed vectors then.
4072 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4073 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4074 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4076 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4079 /// getOnesVector - Returns a vector of specified type with all bits set.
4080 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4081 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4082 /// original type, ensuring they get CSE'd.
4083 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4084 assert(VT.isVector() && "Expected a vector type");
4085 assert((VT.is128BitVector() || VT.is256BitVector())
4086 && "Expected a 128-bit or 256-bit vector type");
4088 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4089 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4090 Cst, Cst, Cst, Cst);
4092 if (VT.is256BitVector()) {
4093 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4094 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4095 Vec = Insert128BitVector(InsV, Vec,
4096 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4099 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4102 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4103 /// that point to V2 points to its first element.
4104 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4105 EVT VT = SVOp->getValueType(0);
4106 unsigned NumElems = VT.getVectorNumElements();
4108 bool Changed = false;
4109 SmallVector<int, 8> MaskVec;
4110 SVOp->getMask(MaskVec);
4112 for (unsigned i = 0; i != NumElems; ++i) {
4113 if (MaskVec[i] > (int)NumElems) {
4114 MaskVec[i] = NumElems;
4119 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4120 SVOp->getOperand(1), &MaskVec[0]);
4121 return SDValue(SVOp, 0);
4124 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4125 /// operation of specified width.
4126 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4128 unsigned NumElems = VT.getVectorNumElements();
4129 SmallVector<int, 8> Mask;
4130 Mask.push_back(NumElems);
4131 for (unsigned i = 1; i != NumElems; ++i)
4133 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4136 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4137 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4139 unsigned NumElems = VT.getVectorNumElements();
4140 SmallVector<int, 8> Mask;
4141 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4143 Mask.push_back(i + NumElems);
4145 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4148 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4149 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4151 unsigned NumElems = VT.getVectorNumElements();
4152 unsigned Half = NumElems/2;
4153 SmallVector<int, 8> Mask;
4154 for (unsigned i = 0; i != Half; ++i) {
4155 Mask.push_back(i + Half);
4156 Mask.push_back(i + NumElems + Half);
4158 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4161 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4162 // a generic shuffle instruction because the target has no such instructions.
4163 // Generate shuffles which repeat i16 and i8 several times until they can be
4164 // represented by v4f32 and then be manipulated by target suported shuffles.
4165 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4166 EVT VT = V.getValueType();
4167 int NumElems = VT.getVectorNumElements();
4168 DebugLoc dl = V.getDebugLoc();
4170 while (NumElems > 4) {
4171 if (EltNo < NumElems/2) {
4172 V = getUnpackl(DAG, dl, VT, V, V);
4174 V = getUnpackh(DAG, dl, VT, V, V);
4175 EltNo -= NumElems/2;
4182 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4183 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4184 EVT VT = V.getValueType();
4185 DebugLoc dl = V.getDebugLoc();
4186 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4187 && "Vector size not supported");
4189 bool Is128 = VT.getSizeInBits() == 128;
4190 EVT NVT = Is128 ? MVT::v4f32 : MVT::v8f32;
4191 V = DAG.getNode(ISD::BITCAST, dl, NVT, V);
4194 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4195 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
4197 // The second half of indicies refer to the higher part, which is a
4198 // duplication of the lower one. This makes this shuffle a perfect match
4199 // for the VPERM instruction.
4200 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4201 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4202 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
4205 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4208 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4209 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4210 EVT SrcVT = SV->getValueType(0);
4211 SDValue V1 = SV->getOperand(0);
4212 DebugLoc dl = SV->getDebugLoc();
4214 int EltNo = SV->getSplatIndex();
4215 int NumElems = SrcVT.getVectorNumElements();
4216 unsigned Size = SrcVT.getSizeInBits();
4218 // Extract the 128-bit part containing the splat element and update
4219 // the splat element index when it refers to the higher register.
4221 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4222 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4224 EltNo -= NumElems/2;
4227 // All i16 and i8 vector types can't be used directly by a generic shuffle
4228 // instruction because the target has no such instruction. Generate shuffles
4229 // which repeat i16 and i8 several times until they fit in i32, and then can
4230 // be manipulated by target suported shuffles. After the insertion of the
4231 // necessary shuffles, the result is bitcasted back to v4f32 or v8f32.
4232 EVT EltVT = SrcVT.getVectorElementType();
4233 if (NumElems > 4 && (EltVT == MVT::i8 || EltVT == MVT::i16))
4234 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4236 // Recreate the 256-bit vector and place the same 128-bit vector
4237 // into the low and high part. This is necessary because we want
4238 // to use VPERM to shuffle the v8f32 vector, and VPERM only shuffles
4239 // inside each separate v4f32 lane.
4241 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4242 DAG.getConstant(0, MVT::i32), DAG, dl);
4243 V1 = Insert128BitVector(InsV, V1,
4244 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4247 return getLegalSplat(DAG, V1, EltNo);
4250 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4251 /// vector of zero or undef vector. This produces a shuffle where the low
4252 /// element of V2 is swizzled into the zero/undef vector, landing at element
4253 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4254 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4255 bool isZero, bool HasSSE2,
4256 SelectionDAG &DAG) {
4257 EVT VT = V2.getValueType();
4259 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4260 unsigned NumElems = VT.getVectorNumElements();
4261 SmallVector<int, 16> MaskVec;
4262 for (unsigned i = 0; i != NumElems; ++i)
4263 // If this is the insertion idx, put the low elt of V2 here.
4264 MaskVec.push_back(i == Idx ? NumElems : i);
4265 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4268 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4269 /// element of the result of the vector shuffle.
4270 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4273 return SDValue(); // Limit search depth.
4275 SDValue V = SDValue(N, 0);
4276 EVT VT = V.getValueType();
4277 unsigned Opcode = V.getOpcode();
4279 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4280 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4281 Index = SV->getMaskElt(Index);
4284 return DAG.getUNDEF(VT.getVectorElementType());
4286 int NumElems = VT.getVectorNumElements();
4287 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4288 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4291 // Recurse into target specific vector shuffles to find scalars.
4292 if (isTargetShuffle(Opcode)) {
4293 int NumElems = VT.getVectorNumElements();
4294 SmallVector<unsigned, 16> ShuffleMask;
4298 case X86ISD::SHUFPS:
4299 case X86ISD::SHUFPD:
4300 ImmN = N->getOperand(N->getNumOperands()-1);
4301 DecodeSHUFPSMask(NumElems,
4302 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4305 case X86ISD::PUNPCKHBW:
4306 case X86ISD::PUNPCKHWD:
4307 case X86ISD::PUNPCKHDQ:
4308 case X86ISD::PUNPCKHQDQ:
4309 DecodePUNPCKHMask(NumElems, ShuffleMask);
4311 case X86ISD::UNPCKHPS:
4312 case X86ISD::UNPCKHPD:
4313 case X86ISD::VUNPCKHPSY:
4314 case X86ISD::VUNPCKHPDY:
4315 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4317 case X86ISD::PUNPCKLBW:
4318 case X86ISD::PUNPCKLWD:
4319 case X86ISD::PUNPCKLDQ:
4320 case X86ISD::PUNPCKLQDQ:
4321 DecodePUNPCKLMask(VT, ShuffleMask);
4323 case X86ISD::UNPCKLPS:
4324 case X86ISD::UNPCKLPD:
4325 case X86ISD::VUNPCKLPSY:
4326 case X86ISD::VUNPCKLPDY:
4327 DecodeUNPCKLPMask(VT, ShuffleMask);
4329 case X86ISD::MOVHLPS:
4330 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4332 case X86ISD::MOVLHPS:
4333 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4335 case X86ISD::PSHUFD:
4336 ImmN = N->getOperand(N->getNumOperands()-1);
4337 DecodePSHUFMask(NumElems,
4338 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4341 case X86ISD::PSHUFHW:
4342 ImmN = N->getOperand(N->getNumOperands()-1);
4343 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4346 case X86ISD::PSHUFLW:
4347 ImmN = N->getOperand(N->getNumOperands()-1);
4348 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4352 case X86ISD::MOVSD: {
4353 // The index 0 always comes from the first element of the second source,
4354 // this is why MOVSS and MOVSD are used in the first place. The other
4355 // elements come from the other positions of the first source vector.
4356 unsigned OpNum = (Index == 0) ? 1 : 0;
4357 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4360 case X86ISD::VPERMILPS:
4361 ImmN = N->getOperand(N->getNumOperands()-1);
4362 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4365 case X86ISD::VPERMILPSY:
4366 ImmN = N->getOperand(N->getNumOperands()-1);
4367 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4370 case X86ISD::VPERMILPD:
4371 ImmN = N->getOperand(N->getNumOperands()-1);
4372 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4375 case X86ISD::VPERMILPDY:
4376 ImmN = N->getOperand(N->getNumOperands()-1);
4377 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4380 case X86ISD::VPERM2F128:
4381 ImmN = N->getOperand(N->getNumOperands()-1);
4382 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4386 assert("not implemented for target shuffle node");
4390 Index = ShuffleMask[Index];
4392 return DAG.getUNDEF(VT.getVectorElementType());
4394 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4395 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4399 // Actual nodes that may contain scalar elements
4400 if (Opcode == ISD::BITCAST) {
4401 V = V.getOperand(0);
4402 EVT SrcVT = V.getValueType();
4403 unsigned NumElems = VT.getVectorNumElements();
4405 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4409 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4410 return (Index == 0) ? V.getOperand(0)
4411 : DAG.getUNDEF(VT.getVectorElementType());
4413 if (V.getOpcode() == ISD::BUILD_VECTOR)
4414 return V.getOperand(Index);
4419 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4420 /// shuffle operation which come from a consecutively from a zero. The
4421 /// search can start in two different directions, from left or right.
4423 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4424 bool ZerosFromLeft, SelectionDAG &DAG) {
4427 while (i < NumElems) {
4428 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4429 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4430 if (!(Elt.getNode() &&
4431 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4439 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4440 /// MaskE correspond consecutively to elements from one of the vector operands,
4441 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4443 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4444 int OpIdx, int NumElems, unsigned &OpNum) {
4445 bool SeenV1 = false;
4446 bool SeenV2 = false;
4448 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4449 int Idx = SVOp->getMaskElt(i);
4450 // Ignore undef indicies
4459 // Only accept consecutive elements from the same vector
4460 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4464 OpNum = SeenV1 ? 0 : 1;
4468 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4469 /// logical left shift of a vector.
4470 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4471 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4472 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4473 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4474 false /* check zeros from right */, DAG);
4480 // Considering the elements in the mask that are not consecutive zeros,
4481 // check if they consecutively come from only one of the source vectors.
4483 // V1 = {X, A, B, C} 0
4485 // vector_shuffle V1, V2 <1, 2, 3, X>
4487 if (!isShuffleMaskConsecutive(SVOp,
4488 0, // Mask Start Index
4489 NumElems-NumZeros-1, // Mask End Index
4490 NumZeros, // Where to start looking in the src vector
4491 NumElems, // Number of elements in vector
4492 OpSrc)) // Which source operand ?
4497 ShVal = SVOp->getOperand(OpSrc);
4501 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4502 /// logical left shift of a vector.
4503 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4504 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4505 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4506 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4507 true /* check zeros from left */, DAG);
4513 // Considering the elements in the mask that are not consecutive zeros,
4514 // check if they consecutively come from only one of the source vectors.
4516 // 0 { A, B, X, X } = V2
4518 // vector_shuffle V1, V2 <X, X, 4, 5>
4520 if (!isShuffleMaskConsecutive(SVOp,
4521 NumZeros, // Mask Start Index
4522 NumElems-1, // Mask End Index
4523 0, // Where to start looking in the src vector
4524 NumElems, // Number of elements in vector
4525 OpSrc)) // Which source operand ?
4530 ShVal = SVOp->getOperand(OpSrc);
4534 /// isVectorShift - Returns true if the shuffle can be implemented as a
4535 /// logical left or right shift of a vector.
4536 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4537 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4538 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4539 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4545 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4547 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4548 unsigned NumNonZero, unsigned NumZero,
4550 const TargetLowering &TLI) {
4554 DebugLoc dl = Op.getDebugLoc();
4557 for (unsigned i = 0; i < 16; ++i) {
4558 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4559 if (ThisIsNonZero && First) {
4561 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4563 V = DAG.getUNDEF(MVT::v8i16);
4568 SDValue ThisElt(0, 0), LastElt(0, 0);
4569 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4570 if (LastIsNonZero) {
4571 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4572 MVT::i16, Op.getOperand(i-1));
4574 if (ThisIsNonZero) {
4575 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4576 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4577 ThisElt, DAG.getConstant(8, MVT::i8));
4579 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4583 if (ThisElt.getNode())
4584 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4585 DAG.getIntPtrConstant(i/2));
4589 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4592 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4594 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4595 unsigned NumNonZero, unsigned NumZero,
4597 const TargetLowering &TLI) {
4601 DebugLoc dl = Op.getDebugLoc();
4604 for (unsigned i = 0; i < 8; ++i) {
4605 bool isNonZero = (NonZeros & (1 << i)) != 0;
4609 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4611 V = DAG.getUNDEF(MVT::v8i16);
4614 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4615 MVT::v8i16, V, Op.getOperand(i),
4616 DAG.getIntPtrConstant(i));
4623 /// getVShift - Return a vector logical shift node.
4625 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4626 unsigned NumBits, SelectionDAG &DAG,
4627 const TargetLowering &TLI, DebugLoc dl) {
4628 EVT ShVT = MVT::v2i64;
4629 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4630 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4631 return DAG.getNode(ISD::BITCAST, dl, VT,
4632 DAG.getNode(Opc, dl, ShVT, SrcOp,
4633 DAG.getConstant(NumBits,
4634 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4638 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4639 SelectionDAG &DAG) const {
4641 // Check if the scalar load can be widened into a vector load. And if
4642 // the address is "base + cst" see if the cst can be "absorbed" into
4643 // the shuffle mask.
4644 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4645 SDValue Ptr = LD->getBasePtr();
4646 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4648 EVT PVT = LD->getValueType(0);
4649 if (PVT != MVT::i32 && PVT != MVT::f32)
4654 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4655 FI = FINode->getIndex();
4657 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4658 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4659 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4660 Offset = Ptr.getConstantOperandVal(1);
4661 Ptr = Ptr.getOperand(0);
4666 // FIXME: 256-bit vector instructions don't require a strict alignment,
4667 // improve this code to support it better.
4668 unsigned RequiredAlign = VT.getSizeInBits()/8;
4669 SDValue Chain = LD->getChain();
4670 // Make sure the stack object alignment is at least 16 or 32.
4671 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4672 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4673 if (MFI->isFixedObjectIndex(FI)) {
4674 // Can't change the alignment. FIXME: It's possible to compute
4675 // the exact stack offset and reference FI + adjust offset instead.
4676 // If someone *really* cares about this. That's the way to implement it.
4679 MFI->setObjectAlignment(FI, RequiredAlign);
4683 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4684 // Ptr + (Offset & ~15).
4687 if ((Offset % RequiredAlign) & 3)
4689 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4691 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4692 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4694 int EltNo = (Offset - StartOffset) >> 2;
4695 int NumElems = VT.getVectorNumElements();
4697 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4698 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4699 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4700 LD->getPointerInfo().getWithOffset(StartOffset),
4703 // Canonicalize it to a v4i32 or v8i32 shuffle.
4704 SmallVector<int, 8> Mask;
4705 for (int i = 0; i < NumElems; ++i)
4706 Mask.push_back(EltNo);
4708 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4709 return DAG.getNode(ISD::BITCAST, dl, NVT,
4710 DAG.getVectorShuffle(CanonVT, dl, V1,
4711 DAG.getUNDEF(CanonVT),&Mask[0]));
4717 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4718 /// vector of type 'VT', see if the elements can be replaced by a single large
4719 /// load which has the same value as a build_vector whose operands are 'elts'.
4721 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4723 /// FIXME: we'd also like to handle the case where the last elements are zero
4724 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4725 /// There's even a handy isZeroNode for that purpose.
4726 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4727 DebugLoc &DL, SelectionDAG &DAG) {
4728 EVT EltVT = VT.getVectorElementType();
4729 unsigned NumElems = Elts.size();
4731 LoadSDNode *LDBase = NULL;
4732 unsigned LastLoadedElt = -1U;
4734 // For each element in the initializer, see if we've found a load or an undef.
4735 // If we don't find an initial load element, or later load elements are
4736 // non-consecutive, bail out.
4737 for (unsigned i = 0; i < NumElems; ++i) {
4738 SDValue Elt = Elts[i];
4740 if (!Elt.getNode() ||
4741 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4744 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4746 LDBase = cast<LoadSDNode>(Elt.getNode());
4750 if (Elt.getOpcode() == ISD::UNDEF)
4753 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4754 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4759 // If we have found an entire vector of loads and undefs, then return a large
4760 // load of the entire vector width starting at the base pointer. If we found
4761 // consecutive loads for the low half, generate a vzext_load node.
4762 if (LastLoadedElt == NumElems - 1) {
4763 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4764 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4765 LDBase->getPointerInfo(),
4766 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4767 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4768 LDBase->getPointerInfo(),
4769 LDBase->isVolatile(), LDBase->isNonTemporal(),
4770 LDBase->getAlignment());
4771 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4772 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4773 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4774 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4775 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4777 LDBase->getMemOperand());
4778 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4784 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4785 DebugLoc dl = Op.getDebugLoc();
4787 EVT VT = Op.getValueType();
4788 EVT ExtVT = VT.getVectorElementType();
4789 unsigned NumElems = Op.getNumOperands();
4791 // Vectors containing all zeros can be matched by pxor and xorps later
4792 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4793 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4794 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4795 if (Op.getValueType() == MVT::v4i32 ||
4796 Op.getValueType() == MVT::v8i32)
4799 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4802 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4803 // vectors or broken into v4i32 operations on 256-bit vectors.
4804 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4805 if (Op.getValueType() == MVT::v4i32)
4808 return getOnesVector(Op.getValueType(), DAG, dl);
4811 unsigned EVTBits = ExtVT.getSizeInBits();
4813 unsigned NumZero = 0;
4814 unsigned NumNonZero = 0;
4815 unsigned NonZeros = 0;
4816 bool IsAllConstants = true;
4817 SmallSet<SDValue, 8> Values;
4818 for (unsigned i = 0; i < NumElems; ++i) {
4819 SDValue Elt = Op.getOperand(i);
4820 if (Elt.getOpcode() == ISD::UNDEF)
4823 if (Elt.getOpcode() != ISD::Constant &&
4824 Elt.getOpcode() != ISD::ConstantFP)
4825 IsAllConstants = false;
4826 if (X86::isZeroNode(Elt))
4829 NonZeros |= (1 << i);
4834 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4835 if (NumNonZero == 0)
4836 return DAG.getUNDEF(VT);
4838 // Special case for single non-zero, non-undef, element.
4839 if (NumNonZero == 1) {
4840 unsigned Idx = CountTrailingZeros_32(NonZeros);
4841 SDValue Item = Op.getOperand(Idx);
4843 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4844 // the value are obviously zero, truncate the value to i32 and do the
4845 // insertion that way. Only do this if the value is non-constant or if the
4846 // value is a constant being inserted into element 0. It is cheaper to do
4847 // a constant pool load than it is to do a movd + shuffle.
4848 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4849 (!IsAllConstants || Idx == 0)) {
4850 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4852 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4853 EVT VecVT = MVT::v4i32;
4854 unsigned VecElts = 4;
4856 // Truncate the value (which may itself be a constant) to i32, and
4857 // convert it to a vector with movd (S2V+shuffle to zero extend).
4858 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4859 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4860 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4861 Subtarget->hasSSE2(), DAG);
4863 // Now we have our 32-bit value zero extended in the low element of
4864 // a vector. If Idx != 0, swizzle it into place.
4866 SmallVector<int, 4> Mask;
4867 Mask.push_back(Idx);
4868 for (unsigned i = 1; i != VecElts; ++i)
4870 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4871 DAG.getUNDEF(Item.getValueType()),
4874 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4878 // If we have a constant or non-constant insertion into the low element of
4879 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4880 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4881 // depending on what the source datatype is.
4884 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4885 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4886 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4887 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4888 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4889 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4891 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4892 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4893 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4894 EVT MiddleVT = MVT::v4i32;
4895 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4896 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4897 Subtarget->hasSSE2(), DAG);
4898 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4902 // Is it a vector logical left shift?
4903 if (NumElems == 2 && Idx == 1 &&
4904 X86::isZeroNode(Op.getOperand(0)) &&
4905 !X86::isZeroNode(Op.getOperand(1))) {
4906 unsigned NumBits = VT.getSizeInBits();
4907 return getVShift(true, VT,
4908 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4909 VT, Op.getOperand(1)),
4910 NumBits/2, DAG, *this, dl);
4913 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4916 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4917 // is a non-constant being inserted into an element other than the low one,
4918 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4919 // movd/movss) to move this into the low element, then shuffle it into
4921 if (EVTBits == 32) {
4922 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4924 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4925 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4926 Subtarget->hasSSE2(), DAG);
4927 SmallVector<int, 8> MaskVec;
4928 for (unsigned i = 0; i < NumElems; i++)
4929 MaskVec.push_back(i == Idx ? 0 : 1);
4930 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4934 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4935 if (Values.size() == 1) {
4936 if (EVTBits == 32) {
4937 // Instead of a shuffle like this:
4938 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4939 // Check if it's possible to issue this instead.
4940 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4941 unsigned Idx = CountTrailingZeros_32(NonZeros);
4942 SDValue Item = Op.getOperand(Idx);
4943 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4944 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4949 // A vector full of immediates; various special cases are already
4950 // handled, so this is best done with a single constant-pool load.
4954 // For AVX-length vectors, build the individual 128-bit pieces and use
4955 // shuffles to put them in place.
4956 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
4957 SmallVector<SDValue, 32> V;
4958 for (unsigned i = 0; i < NumElems; ++i)
4959 V.push_back(Op.getOperand(i));
4961 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
4963 // Build both the lower and upper subvector.
4964 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
4965 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
4968 // Recreate the wider vector with the lower and upper part.
4969 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
4970 DAG.getConstant(0, MVT::i32), DAG, dl);
4971 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
4975 // Let legalizer expand 2-wide build_vectors.
4976 if (EVTBits == 64) {
4977 if (NumNonZero == 1) {
4978 // One half is zero or undef.
4979 unsigned Idx = CountTrailingZeros_32(NonZeros);
4980 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4981 Op.getOperand(Idx));
4982 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4983 Subtarget->hasSSE2(), DAG);
4988 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4989 if (EVTBits == 8 && NumElems == 16) {
4990 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4992 if (V.getNode()) return V;
4995 if (EVTBits == 16 && NumElems == 8) {
4996 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4998 if (V.getNode()) return V;
5001 // If element VT is == 32 bits, turn it into a number of shuffles.
5002 SmallVector<SDValue, 8> V;
5004 if (NumElems == 4 && NumZero > 0) {
5005 for (unsigned i = 0; i < 4; ++i) {
5006 bool isZero = !(NonZeros & (1 << i));
5008 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5010 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5013 for (unsigned i = 0; i < 2; ++i) {
5014 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5017 V[i] = V[i*2]; // Must be a zero vector.
5020 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5023 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5026 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5031 SmallVector<int, 8> MaskVec;
5032 bool Reverse = (NonZeros & 0x3) == 2;
5033 for (unsigned i = 0; i < 2; ++i)
5034 MaskVec.push_back(Reverse ? 1-i : i);
5035 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5036 for (unsigned i = 0; i < 2; ++i)
5037 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5038 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5041 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5042 // Check for a build vector of consecutive loads.
5043 for (unsigned i = 0; i < NumElems; ++i)
5044 V[i] = Op.getOperand(i);
5046 // Check for elements which are consecutive loads.
5047 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5051 // For SSE 4.1, use insertps to put the high elements into the low element.
5052 if (getSubtarget()->hasSSE41()) {
5054 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5055 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5057 Result = DAG.getUNDEF(VT);
5059 for (unsigned i = 1; i < NumElems; ++i) {
5060 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5061 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5062 Op.getOperand(i), DAG.getIntPtrConstant(i));
5067 // Otherwise, expand into a number of unpckl*, start by extending each of
5068 // our (non-undef) elements to the full vector width with the element in the
5069 // bottom slot of the vector (which generates no code for SSE).
5070 for (unsigned i = 0; i < NumElems; ++i) {
5071 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5072 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5074 V[i] = DAG.getUNDEF(VT);
5077 // Next, we iteratively mix elements, e.g. for v4f32:
5078 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5079 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5080 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5081 unsigned EltStride = NumElems >> 1;
5082 while (EltStride != 0) {
5083 for (unsigned i = 0; i < EltStride; ++i) {
5084 // If V[i+EltStride] is undef and this is the first round of mixing,
5085 // then it is safe to just drop this shuffle: V[i] is already in the
5086 // right place, the one element (since it's the first round) being
5087 // inserted as undef can be dropped. This isn't safe for successive
5088 // rounds because they will permute elements within both vectors.
5089 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5090 EltStride == NumElems/2)
5093 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5102 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5103 // them in a MMX register. This is better than doing a stack convert.
5104 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5105 DebugLoc dl = Op.getDebugLoc();
5106 EVT ResVT = Op.getValueType();
5108 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5109 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5111 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5112 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5113 InVec = Op.getOperand(1);
5114 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5115 unsigned NumElts = ResVT.getVectorNumElements();
5116 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5117 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5118 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5120 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5121 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5122 Mask[0] = 0; Mask[1] = 2;
5123 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5125 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5128 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5129 // to create 256-bit vectors from two other 128-bit ones.
5130 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5131 DebugLoc dl = Op.getDebugLoc();
5132 EVT ResVT = Op.getValueType();
5134 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5136 SDValue V1 = Op.getOperand(0);
5137 SDValue V2 = Op.getOperand(1);
5138 unsigned NumElems = ResVT.getVectorNumElements();
5140 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5141 DAG.getConstant(0, MVT::i32), DAG, dl);
5142 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5147 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5148 EVT ResVT = Op.getValueType();
5150 assert(Op.getNumOperands() == 2);
5151 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5152 "Unsupported CONCAT_VECTORS for value type");
5154 // We support concatenate two MMX registers and place them in a MMX register.
5155 // This is better than doing a stack convert.
5156 if (ResVT.is128BitVector())
5157 return LowerMMXCONCAT_VECTORS(Op, DAG);
5159 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5160 // from two other 128-bit ones.
5161 return LowerAVXCONCAT_VECTORS(Op, DAG);
5164 // v8i16 shuffles - Prefer shuffles in the following order:
5165 // 1. [all] pshuflw, pshufhw, optional move
5166 // 2. [ssse3] 1 x pshufb
5167 // 3. [ssse3] 2 x pshufb + 1 x por
5168 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5170 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5171 SelectionDAG &DAG) const {
5172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5173 SDValue V1 = SVOp->getOperand(0);
5174 SDValue V2 = SVOp->getOperand(1);
5175 DebugLoc dl = SVOp->getDebugLoc();
5176 SmallVector<int, 8> MaskVals;
5178 // Determine if more than 1 of the words in each of the low and high quadwords
5179 // of the result come from the same quadword of one of the two inputs. Undef
5180 // mask values count as coming from any quadword, for better codegen.
5181 SmallVector<unsigned, 4> LoQuad(4);
5182 SmallVector<unsigned, 4> HiQuad(4);
5183 BitVector InputQuads(4);
5184 for (unsigned i = 0; i < 8; ++i) {
5185 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5186 int EltIdx = SVOp->getMaskElt(i);
5187 MaskVals.push_back(EltIdx);
5196 InputQuads.set(EltIdx / 4);
5199 int BestLoQuad = -1;
5200 unsigned MaxQuad = 1;
5201 for (unsigned i = 0; i < 4; ++i) {
5202 if (LoQuad[i] > MaxQuad) {
5204 MaxQuad = LoQuad[i];
5208 int BestHiQuad = -1;
5210 for (unsigned i = 0; i < 4; ++i) {
5211 if (HiQuad[i] > MaxQuad) {
5213 MaxQuad = HiQuad[i];
5217 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5218 // of the two input vectors, shuffle them into one input vector so only a
5219 // single pshufb instruction is necessary. If There are more than 2 input
5220 // quads, disable the next transformation since it does not help SSSE3.
5221 bool V1Used = InputQuads[0] || InputQuads[1];
5222 bool V2Used = InputQuads[2] || InputQuads[3];
5223 if (Subtarget->hasSSSE3()) {
5224 if (InputQuads.count() == 2 && V1Used && V2Used) {
5225 BestLoQuad = InputQuads.find_first();
5226 BestHiQuad = InputQuads.find_next(BestLoQuad);
5228 if (InputQuads.count() > 2) {
5234 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5235 // the shuffle mask. If a quad is scored as -1, that means that it contains
5236 // words from all 4 input quadwords.
5238 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5239 SmallVector<int, 8> MaskV;
5240 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5241 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5242 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5243 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5244 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5245 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5247 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5248 // source words for the shuffle, to aid later transformations.
5249 bool AllWordsInNewV = true;
5250 bool InOrder[2] = { true, true };
5251 for (unsigned i = 0; i != 8; ++i) {
5252 int idx = MaskVals[i];
5254 InOrder[i/4] = false;
5255 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5257 AllWordsInNewV = false;
5261 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5262 if (AllWordsInNewV) {
5263 for (int i = 0; i != 8; ++i) {
5264 int idx = MaskVals[i];
5267 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5268 if ((idx != i) && idx < 4)
5270 if ((idx != i) && idx > 3)
5279 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5280 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5281 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5282 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5283 unsigned TargetMask = 0;
5284 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5285 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5286 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5287 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5288 V1 = NewV.getOperand(0);
5289 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5293 // If we have SSSE3, and all words of the result are from 1 input vector,
5294 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5295 // is present, fall back to case 4.
5296 if (Subtarget->hasSSSE3()) {
5297 SmallVector<SDValue,16> pshufbMask;
5299 // If we have elements from both input vectors, set the high bit of the
5300 // shuffle mask element to zero out elements that come from V2 in the V1
5301 // mask, and elements that come from V1 in the V2 mask, so that the two
5302 // results can be OR'd together.
5303 bool TwoInputs = V1Used && V2Used;
5304 for (unsigned i = 0; i != 8; ++i) {
5305 int EltIdx = MaskVals[i] * 2;
5306 if (TwoInputs && (EltIdx >= 16)) {
5307 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5308 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5311 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5312 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5314 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5315 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5316 DAG.getNode(ISD::BUILD_VECTOR, dl,
5317 MVT::v16i8, &pshufbMask[0], 16));
5319 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5321 // Calculate the shuffle mask for the second input, shuffle it, and
5322 // OR it with the first shuffled input.
5324 for (unsigned i = 0; i != 8; ++i) {
5325 int EltIdx = MaskVals[i] * 2;
5327 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5328 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5331 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5332 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5334 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5335 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5336 DAG.getNode(ISD::BUILD_VECTOR, dl,
5337 MVT::v16i8, &pshufbMask[0], 16));
5338 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5339 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5342 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5343 // and update MaskVals with new element order.
5344 BitVector InOrder(8);
5345 if (BestLoQuad >= 0) {
5346 SmallVector<int, 8> MaskV;
5347 for (int i = 0; i != 4; ++i) {
5348 int idx = MaskVals[i];
5350 MaskV.push_back(-1);
5352 } else if ((idx / 4) == BestLoQuad) {
5353 MaskV.push_back(idx & 3);
5356 MaskV.push_back(-1);
5359 for (unsigned i = 4; i != 8; ++i)
5361 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5364 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5365 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5367 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5371 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5372 // and update MaskVals with the new element order.
5373 if (BestHiQuad >= 0) {
5374 SmallVector<int, 8> MaskV;
5375 for (unsigned i = 0; i != 4; ++i)
5377 for (unsigned i = 4; i != 8; ++i) {
5378 int idx = MaskVals[i];
5380 MaskV.push_back(-1);
5382 } else if ((idx / 4) == BestHiQuad) {
5383 MaskV.push_back((idx & 3) + 4);
5386 MaskV.push_back(-1);
5389 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5392 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5393 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5395 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5399 // In case BestHi & BestLo were both -1, which means each quadword has a word
5400 // from each of the four input quadwords, calculate the InOrder bitvector now
5401 // before falling through to the insert/extract cleanup.
5402 if (BestLoQuad == -1 && BestHiQuad == -1) {
5404 for (int i = 0; i != 8; ++i)
5405 if (MaskVals[i] < 0 || MaskVals[i] == i)
5409 // The other elements are put in the right place using pextrw and pinsrw.
5410 for (unsigned i = 0; i != 8; ++i) {
5413 int EltIdx = MaskVals[i];
5416 SDValue ExtOp = (EltIdx < 8)
5417 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5418 DAG.getIntPtrConstant(EltIdx))
5419 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5420 DAG.getIntPtrConstant(EltIdx - 8));
5421 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5422 DAG.getIntPtrConstant(i));
5427 // v16i8 shuffles - Prefer shuffles in the following order:
5428 // 1. [ssse3] 1 x pshufb
5429 // 2. [ssse3] 2 x pshufb + 1 x por
5430 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5432 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5434 const X86TargetLowering &TLI) {
5435 SDValue V1 = SVOp->getOperand(0);
5436 SDValue V2 = SVOp->getOperand(1);
5437 DebugLoc dl = SVOp->getDebugLoc();
5438 SmallVector<int, 16> MaskVals;
5439 SVOp->getMask(MaskVals);
5441 // If we have SSSE3, case 1 is generated when all result bytes come from
5442 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5443 // present, fall back to case 3.
5444 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5447 for (unsigned i = 0; i < 16; ++i) {
5448 int EltIdx = MaskVals[i];
5457 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5458 if (TLI.getSubtarget()->hasSSSE3()) {
5459 SmallVector<SDValue,16> pshufbMask;
5461 // If all result elements are from one input vector, then only translate
5462 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5464 // Otherwise, we have elements from both input vectors, and must zero out
5465 // elements that come from V2 in the first mask, and V1 in the second mask
5466 // so that we can OR them together.
5467 bool TwoInputs = !(V1Only || V2Only);
5468 for (unsigned i = 0; i != 16; ++i) {
5469 int EltIdx = MaskVals[i];
5470 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5471 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5474 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5476 // If all the elements are from V2, assign it to V1 and return after
5477 // building the first pshufb.
5480 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5481 DAG.getNode(ISD::BUILD_VECTOR, dl,
5482 MVT::v16i8, &pshufbMask[0], 16));
5486 // Calculate the shuffle mask for the second input, shuffle it, and
5487 // OR it with the first shuffled input.
5489 for (unsigned i = 0; i != 16; ++i) {
5490 int EltIdx = MaskVals[i];
5492 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5495 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5497 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5498 DAG.getNode(ISD::BUILD_VECTOR, dl,
5499 MVT::v16i8, &pshufbMask[0], 16));
5500 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5503 // No SSSE3 - Calculate in place words and then fix all out of place words
5504 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5505 // the 16 different words that comprise the two doublequadword input vectors.
5506 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5507 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5508 SDValue NewV = V2Only ? V2 : V1;
5509 for (int i = 0; i != 8; ++i) {
5510 int Elt0 = MaskVals[i*2];
5511 int Elt1 = MaskVals[i*2+1];
5513 // This word of the result is all undef, skip it.
5514 if (Elt0 < 0 && Elt1 < 0)
5517 // This word of the result is already in the correct place, skip it.
5518 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5520 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5523 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5524 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5527 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5528 // using a single extract together, load it and store it.
5529 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5530 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5531 DAG.getIntPtrConstant(Elt1 / 2));
5532 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5533 DAG.getIntPtrConstant(i));
5537 // If Elt1 is defined, extract it from the appropriate source. If the
5538 // source byte is not also odd, shift the extracted word left 8 bits
5539 // otherwise clear the bottom 8 bits if we need to do an or.
5541 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5542 DAG.getIntPtrConstant(Elt1 / 2));
5543 if ((Elt1 & 1) == 0)
5544 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5546 TLI.getShiftAmountTy(InsElt.getValueType())));
5548 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5549 DAG.getConstant(0xFF00, MVT::i16));
5551 // If Elt0 is defined, extract it from the appropriate source. If the
5552 // source byte is not also even, shift the extracted word right 8 bits. If
5553 // Elt1 was also defined, OR the extracted values together before
5554 // inserting them in the result.
5556 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5557 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5558 if ((Elt0 & 1) != 0)
5559 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5561 TLI.getShiftAmountTy(InsElt0.getValueType())));
5563 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5564 DAG.getConstant(0x00FF, MVT::i16));
5565 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5568 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5569 DAG.getIntPtrConstant(i));
5571 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5574 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5575 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5576 /// done when every pair / quad of shuffle mask elements point to elements in
5577 /// the right sequence. e.g.
5578 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5580 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5581 SelectionDAG &DAG, DebugLoc dl) {
5582 EVT VT = SVOp->getValueType(0);
5583 SDValue V1 = SVOp->getOperand(0);
5584 SDValue V2 = SVOp->getOperand(1);
5585 unsigned NumElems = VT.getVectorNumElements();
5586 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5588 switch (VT.getSimpleVT().SimpleTy) {
5589 default: assert(false && "Unexpected!");
5590 case MVT::v4f32: NewVT = MVT::v2f64; break;
5591 case MVT::v4i32: NewVT = MVT::v2i64; break;
5592 case MVT::v8i16: NewVT = MVT::v4i32; break;
5593 case MVT::v16i8: NewVT = MVT::v4i32; break;
5596 int Scale = NumElems / NewWidth;
5597 SmallVector<int, 8> MaskVec;
5598 for (unsigned i = 0; i < NumElems; i += Scale) {
5600 for (int j = 0; j < Scale; ++j) {
5601 int EltIdx = SVOp->getMaskElt(i+j);
5605 StartIdx = EltIdx - (EltIdx % Scale);
5606 if (EltIdx != StartIdx + j)
5610 MaskVec.push_back(-1);
5612 MaskVec.push_back(StartIdx / Scale);
5615 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5616 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5617 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5620 /// getVZextMovL - Return a zero-extending vector move low node.
5622 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5623 SDValue SrcOp, SelectionDAG &DAG,
5624 const X86Subtarget *Subtarget, DebugLoc dl) {
5625 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5626 LoadSDNode *LD = NULL;
5627 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5628 LD = dyn_cast<LoadSDNode>(SrcOp);
5630 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5632 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5633 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5634 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5635 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5636 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5638 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5639 return DAG.getNode(ISD::BITCAST, dl, VT,
5640 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5641 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5649 return DAG.getNode(ISD::BITCAST, dl, VT,
5650 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5651 DAG.getNode(ISD::BITCAST, dl,
5655 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5656 /// shuffle node referes to only one lane in the sources.
5657 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5658 EVT VT = SVOp->getValueType(0);
5659 int NumElems = VT.getVectorNumElements();
5660 int HalfSize = NumElems/2;
5661 SmallVector<int, 16> M;
5663 bool MatchA = false, MatchB = false;
5665 for (int l = 0; l < NumElems*2; l += HalfSize) {
5666 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5672 for (int l = 0; l < NumElems*2; l += HalfSize) {
5673 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5679 return MatchA && MatchB;
5682 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5683 /// which could not be matched by any known target speficic shuffle
5685 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5686 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5687 // If each half of a vector shuffle node referes to only one lane in the
5688 // source vectors, extract each used 128-bit lane and shuffle them using
5689 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5690 // the work to the legalizer.
5691 DebugLoc dl = SVOp->getDebugLoc();
5692 EVT VT = SVOp->getValueType(0);
5693 int NumElems = VT.getVectorNumElements();
5694 int HalfSize = NumElems/2;
5696 // Extract the reference for each half
5697 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5698 int FstVecOpNum = 0, SndVecOpNum = 0;
5699 for (int i = 0; i < HalfSize; ++i) {
5700 int Elt = SVOp->getMaskElt(i);
5701 if (SVOp->getMaskElt(i) < 0)
5703 FstVecOpNum = Elt/NumElems;
5704 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5707 for (int i = HalfSize; i < NumElems; ++i) {
5708 int Elt = SVOp->getMaskElt(i);
5709 if (SVOp->getMaskElt(i) < 0)
5711 SndVecOpNum = Elt/NumElems;
5712 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5716 // Extract the subvectors
5717 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5718 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5719 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5720 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5722 // Generate 128-bit shuffles
5723 SmallVector<int, 16> MaskV1, MaskV2;
5724 for (int i = 0; i < HalfSize; ++i) {
5725 int Elt = SVOp->getMaskElt(i);
5726 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5728 for (int i = HalfSize; i < NumElems; ++i) {
5729 int Elt = SVOp->getMaskElt(i);
5730 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5733 EVT NVT = V1.getValueType();
5734 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5735 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5737 // Concatenate the result back
5738 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5739 DAG.getConstant(0, MVT::i32), DAG, dl);
5740 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5747 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5748 /// 4 elements, and match them with several different shuffle types.
5750 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5751 SDValue V1 = SVOp->getOperand(0);
5752 SDValue V2 = SVOp->getOperand(1);
5753 DebugLoc dl = SVOp->getDebugLoc();
5754 EVT VT = SVOp->getValueType(0);
5756 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5758 SmallVector<std::pair<int, int>, 8> Locs;
5760 SmallVector<int, 8> Mask1(4U, -1);
5761 SmallVector<int, 8> PermMask;
5762 SVOp->getMask(PermMask);
5766 for (unsigned i = 0; i != 4; ++i) {
5767 int Idx = PermMask[i];
5769 Locs[i] = std::make_pair(-1, -1);
5771 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5773 Locs[i] = std::make_pair(0, NumLo);
5777 Locs[i] = std::make_pair(1, NumHi);
5779 Mask1[2+NumHi] = Idx;
5785 if (NumLo <= 2 && NumHi <= 2) {
5786 // If no more than two elements come from either vector. This can be
5787 // implemented with two shuffles. First shuffle gather the elements.
5788 // The second shuffle, which takes the first shuffle as both of its
5789 // vector operands, put the elements into the right order.
5790 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5792 SmallVector<int, 8> Mask2(4U, -1);
5794 for (unsigned i = 0; i != 4; ++i) {
5795 if (Locs[i].first == -1)
5798 unsigned Idx = (i < 2) ? 0 : 4;
5799 Idx += Locs[i].first * 2 + Locs[i].second;
5804 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5805 } else if (NumLo == 3 || NumHi == 3) {
5806 // Otherwise, we must have three elements from one vector, call it X, and
5807 // one element from the other, call it Y. First, use a shufps to build an
5808 // intermediate vector with the one element from Y and the element from X
5809 // that will be in the same half in the final destination (the indexes don't
5810 // matter). Then, use a shufps to build the final vector, taking the half
5811 // containing the element from Y from the intermediate, and the other half
5814 // Normalize it so the 3 elements come from V1.
5815 CommuteVectorShuffleMask(PermMask, VT);
5819 // Find the element from V2.
5821 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5822 int Val = PermMask[HiIndex];
5829 Mask1[0] = PermMask[HiIndex];
5831 Mask1[2] = PermMask[HiIndex^1];
5833 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5836 Mask1[0] = PermMask[0];
5837 Mask1[1] = PermMask[1];
5838 Mask1[2] = HiIndex & 1 ? 6 : 4;
5839 Mask1[3] = HiIndex & 1 ? 4 : 6;
5840 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5842 Mask1[0] = HiIndex & 1 ? 2 : 0;
5843 Mask1[1] = HiIndex & 1 ? 0 : 2;
5844 Mask1[2] = PermMask[2];
5845 Mask1[3] = PermMask[3];
5850 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5854 // Break it into (shuffle shuffle_hi, shuffle_lo).
5857 SmallVector<int,8> LoMask(4U, -1);
5858 SmallVector<int,8> HiMask(4U, -1);
5860 SmallVector<int,8> *MaskPtr = &LoMask;
5861 unsigned MaskIdx = 0;
5864 for (unsigned i = 0; i != 4; ++i) {
5871 int Idx = PermMask[i];
5873 Locs[i] = std::make_pair(-1, -1);
5874 } else if (Idx < 4) {
5875 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5876 (*MaskPtr)[LoIdx] = Idx;
5879 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5880 (*MaskPtr)[HiIdx] = Idx;
5885 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5886 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5887 SmallVector<int, 8> MaskOps;
5888 for (unsigned i = 0; i != 4; ++i) {
5889 if (Locs[i].first == -1) {
5890 MaskOps.push_back(-1);
5892 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5893 MaskOps.push_back(Idx);
5896 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5899 static bool MayFoldVectorLoad(SDValue V) {
5900 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5901 V = V.getOperand(0);
5902 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5903 V = V.getOperand(0);
5909 // FIXME: the version above should always be used. Since there's
5910 // a bug where several vector shuffles can't be folded because the
5911 // DAG is not updated during lowering and a node claims to have two
5912 // uses while it only has one, use this version, and let isel match
5913 // another instruction if the load really happens to have more than
5914 // one use. Remove this version after this bug get fixed.
5915 // rdar://8434668, PR8156
5916 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5917 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5918 V = V.getOperand(0);
5919 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5920 V = V.getOperand(0);
5921 if (ISD::isNormalLoad(V.getNode()))
5926 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5927 /// a vector extract, and if both can be later optimized into a single load.
5928 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5929 /// here because otherwise a target specific shuffle node is going to be
5930 /// emitted for this shuffle, and the optimization not done.
5931 /// FIXME: This is probably not the best approach, but fix the problem
5932 /// until the right path is decided.
5934 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5935 const TargetLowering &TLI) {
5936 EVT VT = V.getValueType();
5937 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5939 // Be sure that the vector shuffle is present in a pattern like this:
5940 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5944 SDNode *N = *V.getNode()->use_begin();
5945 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5948 SDValue EltNo = N->getOperand(1);
5949 if (!isa<ConstantSDNode>(EltNo))
5952 // If the bit convert changed the number of elements, it is unsafe
5953 // to examine the mask.
5954 bool HasShuffleIntoBitcast = false;
5955 if (V.getOpcode() == ISD::BITCAST) {
5956 EVT SrcVT = V.getOperand(0).getValueType();
5957 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5959 V = V.getOperand(0);
5960 HasShuffleIntoBitcast = true;
5963 // Select the input vector, guarding against out of range extract vector.
5964 unsigned NumElems = VT.getVectorNumElements();
5965 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5966 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5967 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5969 // Skip one more bit_convert if necessary
5970 if (V.getOpcode() == ISD::BITCAST)
5971 V = V.getOperand(0);
5973 if (ISD::isNormalLoad(V.getNode())) {
5974 // Is the original load suitable?
5975 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5977 // FIXME: avoid the multi-use bug that is preventing lots of
5978 // of foldings to be detected, this is still wrong of course, but
5979 // give the temporary desired behavior, and if it happens that
5980 // the load has real more uses, during isel it will not fold, and
5981 // will generate poor code.
5982 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5985 if (!HasShuffleIntoBitcast)
5988 // If there's a bitcast before the shuffle, check if the load type and
5989 // alignment is valid.
5990 unsigned Align = LN0->getAlignment();
5992 TLI.getTargetData()->getABITypeAlignment(
5993 VT.getTypeForEVT(*DAG.getContext()));
5995 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6003 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6004 EVT VT = Op.getValueType();
6006 // Canonizalize to v2f64.
6007 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6008 return DAG.getNode(ISD::BITCAST, dl, VT,
6009 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6014 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6016 SDValue V1 = Op.getOperand(0);
6017 SDValue V2 = Op.getOperand(1);
6018 EVT VT = Op.getValueType();
6020 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6022 if (HasSSE2 && VT == MVT::v2f64)
6023 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6026 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
6030 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6031 SDValue V1 = Op.getOperand(0);
6032 SDValue V2 = Op.getOperand(1);
6033 EVT VT = Op.getValueType();
6035 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6036 "unsupported shuffle type");
6038 if (V2.getOpcode() == ISD::UNDEF)
6042 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6046 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6047 SDValue V1 = Op.getOperand(0);
6048 SDValue V2 = Op.getOperand(1);
6049 EVT VT = Op.getValueType();
6050 unsigned NumElems = VT.getVectorNumElements();
6052 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6053 // operand of these instructions is only memory, so check if there's a
6054 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6056 bool CanFoldLoad = false;
6058 // Trivial case, when V2 comes from a load.
6059 if (MayFoldVectorLoad(V2))
6062 // When V1 is a load, it can be folded later into a store in isel, example:
6063 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6065 // (MOVLPSmr addr:$src1, VR128:$src2)
6066 // So, recognize this potential and also use MOVLPS or MOVLPD
6067 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6070 // Both of them can't be memory operations though.
6071 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6072 CanFoldLoad = false;
6075 if (HasSSE2 && NumElems == 2)
6076 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6079 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6082 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6083 // movl and movlp will both match v2i64, but v2i64 is never matched by
6084 // movl earlier because we make it strict to avoid messing with the movlp load
6085 // folding logic (see the code above getMOVLP call). Match it here then,
6086 // this is horrible, but will stay like this until we move all shuffle
6087 // matching to x86 specific nodes. Note that for the 1st condition all
6088 // types are matched with movsd.
6089 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
6090 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6092 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6095 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6097 // Invert the operand order and use SHUFPS to match it.
6098 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
6099 X86::getShuffleSHUFImmediate(SVOp), DAG);
6102 static inline unsigned getUNPCKLOpcode(EVT VT) {
6103 switch(VT.getSimpleVT().SimpleTy) {
6104 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6105 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6106 case MVT::v4f32: return X86ISD::UNPCKLPS;
6107 case MVT::v2f64: return X86ISD::UNPCKLPD;
6108 case MVT::v8i32: // Use fp unit for int unpack.
6109 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6110 case MVT::v4i64: // Use fp unit for int unpack.
6111 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6112 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6113 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6115 llvm_unreachable("Unknown type for unpckl");
6120 static inline unsigned getUNPCKHOpcode(EVT VT) {
6121 switch(VT.getSimpleVT().SimpleTy) {
6122 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6123 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6124 case MVT::v4f32: return X86ISD::UNPCKHPS;
6125 case MVT::v2f64: return X86ISD::UNPCKHPD;
6126 case MVT::v8i32: // Use fp unit for int unpack.
6127 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6128 case MVT::v4i64: // Use fp unit for int unpack.
6129 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6130 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6131 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6133 llvm_unreachable("Unknown type for unpckh");
6138 static inline unsigned getVPERMILOpcode(EVT VT) {
6139 switch(VT.getSimpleVT().SimpleTy) {
6141 case MVT::v4f32: return X86ISD::VPERMILPS;
6143 case MVT::v2f64: return X86ISD::VPERMILPD;
6145 case MVT::v8f32: return X86ISD::VPERMILPSY;
6147 case MVT::v4f64: return X86ISD::VPERMILPDY;
6149 llvm_unreachable("Unknown type for vpermil");
6154 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6155 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6156 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6157 static bool isVectorBroadcast(SDValue &Op) {
6158 EVT VT = Op.getValueType();
6159 bool Is256 = VT.getSizeInBits() == 256;
6161 assert((VT.getSizeInBits() == 128 || Is256) &&
6162 "Unsupported type for vbroadcast node");
6165 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6166 V = V.getOperand(0);
6168 if (Is256 && !(V.hasOneUse() &&
6169 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6170 V.getOperand(0).getOpcode() == ISD::UNDEF))
6174 V = V.getOperand(1);
6175 if (V.hasOneUse() && V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6178 // Check the source scalar_to_vector type. 256-bit broadcasts are
6179 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6180 // for 32-bit scalars.
6181 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6182 if (ScalarSize != 32 && ScalarSize != 64)
6184 if (!Is256 && ScalarSize == 64)
6187 V = V.getOperand(0);
6188 if (!MayFoldLoad(V))
6191 // Return the load node
6197 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6198 const TargetLowering &TLI,
6199 const X86Subtarget *Subtarget) {
6200 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6201 EVT VT = Op.getValueType();
6202 DebugLoc dl = Op.getDebugLoc();
6203 SDValue V1 = Op.getOperand(0);
6204 SDValue V2 = Op.getOperand(1);
6206 if (isZeroShuffle(SVOp))
6207 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6209 // Handle splat operations
6210 if (SVOp->isSplat()) {
6211 unsigned NumElem = VT.getVectorNumElements();
6212 // Special case, this is the only place now where it's allowed to return
6213 // a vector_shuffle operation without using a target specific node, because
6214 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6215 // this be moved to DAGCombine instead?
6216 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6219 // Use vbroadcast whenever the splat comes from a foldable load
6220 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6221 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6223 // Handle splats by matching through known shuffle masks
6224 if (VT.is128BitVector() && NumElem <= 4)
6227 // All remaning splats are promoted to target supported vector shuffles.
6228 return PromoteSplat(SVOp, DAG);
6231 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6233 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6234 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6235 if (NewOp.getNode())
6236 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6237 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6238 // FIXME: Figure out a cleaner way to do this.
6239 // Try to make use of movq to zero out the top part.
6240 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6241 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6242 if (NewOp.getNode()) {
6243 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6244 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6245 DAG, Subtarget, dl);
6247 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6248 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6249 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6250 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6251 DAG, Subtarget, dl);
6258 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6259 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6260 SDValue V1 = Op.getOperand(0);
6261 SDValue V2 = Op.getOperand(1);
6262 EVT VT = Op.getValueType();
6263 DebugLoc dl = Op.getDebugLoc();
6264 unsigned NumElems = VT.getVectorNumElements();
6265 bool isMMX = VT.getSizeInBits() == 64;
6266 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6267 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6268 bool V1IsSplat = false;
6269 bool V2IsSplat = false;
6270 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6271 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6272 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6273 MachineFunction &MF = DAG.getMachineFunction();
6274 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6276 // Shuffle operations on MMX not supported.
6280 // Vector shuffle lowering takes 3 steps:
6282 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6283 // narrowing and commutation of operands should be handled.
6284 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6286 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6287 // so the shuffle can be broken into other shuffles and the legalizer can
6288 // try the lowering again.
6290 // The general ideia is that no vector_shuffle operation should be left to
6291 // be matched during isel, all of them must be converted to a target specific
6294 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6295 // narrowing and commutation of operands should be handled. The actual code
6296 // doesn't include all of those, work in progress...
6297 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6298 if (NewOp.getNode())
6301 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6302 // unpckh_undef). Only use pshufd if speed is more important than size.
6303 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6304 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6305 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6306 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6308 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6309 RelaxedMayFoldVectorLoad(V1))
6310 return getMOVDDup(Op, dl, V1, DAG);
6312 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6313 return getMOVHighToLow(Op, dl, DAG);
6315 // Use to match splats
6316 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6317 (VT == MVT::v2f64 || VT == MVT::v2i64))
6318 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6320 if (X86::isPSHUFDMask(SVOp)) {
6321 // The actual implementation will match the mask in the if above and then
6322 // during isel it can match several different instructions, not only pshufd
6323 // as its name says, sad but true, emulate the behavior for now...
6324 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6325 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6327 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6329 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6330 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6332 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6333 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
6336 if (VT == MVT::v4f32)
6337 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
6341 // Check if this can be converted into a logical shift.
6342 bool isLeft = false;
6345 bool isShift = getSubtarget()->hasSSE2() &&
6346 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6347 if (isShift && ShVal.hasOneUse()) {
6348 // If the shifted value has multiple uses, it may be cheaper to use
6349 // v_set0 + movlhps or movhlps, etc.
6350 EVT EltVT = VT.getVectorElementType();
6351 ShAmt *= EltVT.getSizeInBits();
6352 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6355 if (X86::isMOVLMask(SVOp)) {
6358 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6359 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6360 if (!X86::isMOVLPMask(SVOp)) {
6361 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6362 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6364 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6365 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6369 // FIXME: fold these into legal mask.
6370 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6371 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6373 if (X86::isMOVHLPSMask(SVOp))
6374 return getMOVHighToLow(Op, dl, DAG);
6376 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6377 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6379 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6380 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6382 if (X86::isMOVLPMask(SVOp))
6383 return getMOVLP(Op, dl, DAG, HasSSE2);
6385 if (ShouldXformToMOVHLPS(SVOp) ||
6386 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6387 return CommuteVectorShuffle(SVOp, DAG);
6390 // No better options. Use a vshl / vsrl.
6391 EVT EltVT = VT.getVectorElementType();
6392 ShAmt *= EltVT.getSizeInBits();
6393 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6396 bool Commuted = false;
6397 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6398 // 1,1,1,1 -> v8i16 though.
6399 V1IsSplat = isSplatVector(V1.getNode());
6400 V2IsSplat = isSplatVector(V2.getNode());
6402 // Canonicalize the splat or undef, if present, to be on the RHS.
6403 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6404 Op = CommuteVectorShuffle(SVOp, DAG);
6405 SVOp = cast<ShuffleVectorSDNode>(Op);
6406 V1 = SVOp->getOperand(0);
6407 V2 = SVOp->getOperand(1);
6408 std::swap(V1IsSplat, V2IsSplat);
6409 std::swap(V1IsUndef, V2IsUndef);
6413 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6414 // Shuffling low element of v1 into undef, just return v1.
6417 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6418 // the instruction selector will not match, so get a canonical MOVL with
6419 // swapped operands to undo the commute.
6420 return getMOVL(DAG, dl, VT, V2, V1);
6423 if (X86::isUNPCKLMask(SVOp))
6424 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6426 if (X86::isUNPCKHMask(SVOp))
6427 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6430 // Normalize mask so all entries that point to V2 points to its first
6431 // element then try to match unpck{h|l} again. If match, return a
6432 // new vector_shuffle with the corrected mask.
6433 SDValue NewMask = NormalizeMask(SVOp, DAG);
6434 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6435 if (NSVOp != SVOp) {
6436 if (X86::isUNPCKLMask(NSVOp, true)) {
6438 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6445 // Commute is back and try unpck* again.
6446 // FIXME: this seems wrong.
6447 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6448 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6450 if (X86::isUNPCKLMask(NewSVOp))
6451 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6453 if (X86::isUNPCKHMask(NewSVOp))
6454 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6457 // Normalize the node to match x86 shuffle ops if needed
6458 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6459 return CommuteVectorShuffle(SVOp, DAG);
6461 // The checks below are all present in isShuffleMaskLegal, but they are
6462 // inlined here right now to enable us to directly emit target specific
6463 // nodes, and remove one by one until they don't return Op anymore.
6464 SmallVector<int, 16> M;
6467 if (isPALIGNRMask(M, VT, HasSSSE3))
6468 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6469 X86::getShufflePALIGNRImmediate(SVOp),
6472 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6473 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6474 if (VT == MVT::v2f64)
6475 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6476 if (VT == MVT::v2i64)
6477 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6480 if (isPSHUFHWMask(M, VT))
6481 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6482 X86::getShufflePSHUFHWImmediate(SVOp),
6485 if (isPSHUFLWMask(M, VT))
6486 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6487 X86::getShufflePSHUFLWImmediate(SVOp),
6490 if (isSHUFPMask(M, VT)) {
6491 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6492 if (VT == MVT::v4f32 || VT == MVT::v4i32)
6493 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
6495 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6496 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
6500 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6501 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6502 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6503 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6505 //===--------------------------------------------------------------------===//
6506 // Generate target specific nodes for 128 or 256-bit shuffles only
6507 // supported in the AVX instruction set.
6510 // Handle VPERMILPS* permutations
6511 if (isVPERMILPSMask(M, VT, Subtarget))
6512 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6513 getShuffleVPERMILPSImmediate(SVOp), DAG);
6515 // Handle VPERMILPD* permutations
6516 if (isVPERMILPDMask(M, VT, Subtarget))
6517 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6518 getShuffleVPERMILPDImmediate(SVOp), DAG);
6520 // Handle VPERM2F128 permutations
6521 if (isVPERM2F128Mask(M, VT, Subtarget))
6522 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6523 getShuffleVPERM2F128Immediate(SVOp), DAG);
6525 //===--------------------------------------------------------------------===//
6526 // Since no target specific shuffle was selected for this generic one,
6527 // lower it into other known shuffles. FIXME: this isn't true yet, but
6528 // this is the plan.
6531 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6532 if (VT == MVT::v8i16) {
6533 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6534 if (NewOp.getNode())
6538 if (VT == MVT::v16i8) {
6539 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6540 if (NewOp.getNode())
6544 // Handle all 128-bit wide vectors with 4 elements, and match them with
6545 // several different shuffle types.
6546 if (NumElems == 4 && VT.getSizeInBits() == 128)
6547 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6549 // Handle general 256-bit shuffles
6550 if (VT.is256BitVector())
6551 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6557 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6558 SelectionDAG &DAG) const {
6559 EVT VT = Op.getValueType();
6560 DebugLoc dl = Op.getDebugLoc();
6562 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6565 if (VT.getSizeInBits() == 8) {
6566 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6567 Op.getOperand(0), Op.getOperand(1));
6568 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6569 DAG.getValueType(VT));
6570 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6571 } else if (VT.getSizeInBits() == 16) {
6572 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6573 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6575 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6576 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6577 DAG.getNode(ISD::BITCAST, dl,
6581 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6582 Op.getOperand(0), Op.getOperand(1));
6583 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6584 DAG.getValueType(VT));
6585 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6586 } else if (VT == MVT::f32) {
6587 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6588 // the result back to FR32 register. It's only worth matching if the
6589 // result has a single use which is a store or a bitcast to i32. And in
6590 // the case of a store, it's not worth it if the index is a constant 0,
6591 // because a MOVSSmr can be used instead, which is smaller and faster.
6592 if (!Op.hasOneUse())
6594 SDNode *User = *Op.getNode()->use_begin();
6595 if ((User->getOpcode() != ISD::STORE ||
6596 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6597 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6598 (User->getOpcode() != ISD::BITCAST ||
6599 User->getValueType(0) != MVT::i32))
6601 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6602 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6605 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6606 } else if (VT == MVT::i32) {
6607 // ExtractPS works with constant index.
6608 if (isa<ConstantSDNode>(Op.getOperand(1)))
6616 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6617 SelectionDAG &DAG) const {
6618 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6621 SDValue Vec = Op.getOperand(0);
6622 EVT VecVT = Vec.getValueType();
6624 // If this is a 256-bit vector result, first extract the 128-bit vector and
6625 // then extract the element from the 128-bit vector.
6626 if (VecVT.getSizeInBits() == 256) {
6627 DebugLoc dl = Op.getNode()->getDebugLoc();
6628 unsigned NumElems = VecVT.getVectorNumElements();
6629 SDValue Idx = Op.getOperand(1);
6630 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6632 // Get the 128-bit vector.
6633 bool Upper = IdxVal >= NumElems/2;
6634 Vec = Extract128BitVector(Vec,
6635 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6637 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6638 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6641 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6643 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6644 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6649 EVT VT = Op.getValueType();
6650 DebugLoc dl = Op.getDebugLoc();
6651 // TODO: handle v16i8.
6652 if (VT.getSizeInBits() == 16) {
6653 SDValue Vec = Op.getOperand(0);
6654 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6656 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6657 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6658 DAG.getNode(ISD::BITCAST, dl,
6661 // Transform it so it match pextrw which produces a 32-bit result.
6662 EVT EltVT = MVT::i32;
6663 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6664 Op.getOperand(0), Op.getOperand(1));
6665 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6666 DAG.getValueType(VT));
6667 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6668 } else if (VT.getSizeInBits() == 32) {
6669 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6673 // SHUFPS the element to the lowest double word, then movss.
6674 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6675 EVT VVT = Op.getOperand(0).getValueType();
6676 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6677 DAG.getUNDEF(VVT), Mask);
6678 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6679 DAG.getIntPtrConstant(0));
6680 } else if (VT.getSizeInBits() == 64) {
6681 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6682 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6683 // to match extract_elt for f64.
6684 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6688 // UNPCKHPD the element to the lowest double word, then movsd.
6689 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6690 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6691 int Mask[2] = { 1, -1 };
6692 EVT VVT = Op.getOperand(0).getValueType();
6693 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6694 DAG.getUNDEF(VVT), Mask);
6695 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6696 DAG.getIntPtrConstant(0));
6703 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6704 SelectionDAG &DAG) const {
6705 EVT VT = Op.getValueType();
6706 EVT EltVT = VT.getVectorElementType();
6707 DebugLoc dl = Op.getDebugLoc();
6709 SDValue N0 = Op.getOperand(0);
6710 SDValue N1 = Op.getOperand(1);
6711 SDValue N2 = Op.getOperand(2);
6713 if (VT.getSizeInBits() == 256)
6716 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6717 isa<ConstantSDNode>(N2)) {
6719 if (VT == MVT::v8i16)
6720 Opc = X86ISD::PINSRW;
6721 else if (VT == MVT::v16i8)
6722 Opc = X86ISD::PINSRB;
6724 Opc = X86ISD::PINSRB;
6726 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6728 if (N1.getValueType() != MVT::i32)
6729 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6730 if (N2.getValueType() != MVT::i32)
6731 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6732 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6733 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6734 // Bits [7:6] of the constant are the source select. This will always be
6735 // zero here. The DAG Combiner may combine an extract_elt index into these
6736 // bits. For example (insert (extract, 3), 2) could be matched by putting
6737 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6738 // Bits [5:4] of the constant are the destination select. This is the
6739 // value of the incoming immediate.
6740 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6741 // combine either bitwise AND or insert of float 0.0 to set these bits.
6742 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6743 // Create this as a scalar to vector..
6744 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6745 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6746 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6747 // PINSR* works with constant index.
6754 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6755 EVT VT = Op.getValueType();
6756 EVT EltVT = VT.getVectorElementType();
6758 DebugLoc dl = Op.getDebugLoc();
6759 SDValue N0 = Op.getOperand(0);
6760 SDValue N1 = Op.getOperand(1);
6761 SDValue N2 = Op.getOperand(2);
6763 // If this is a 256-bit vector result, first extract the 128-bit vector,
6764 // insert the element into the extracted half and then place it back.
6765 if (VT.getSizeInBits() == 256) {
6766 if (!isa<ConstantSDNode>(N2))
6769 // Get the desired 128-bit vector half.
6770 unsigned NumElems = VT.getVectorNumElements();
6771 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6772 bool Upper = IdxVal >= NumElems/2;
6773 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6774 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6776 // Insert the element into the desired half.
6777 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6778 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6780 // Insert the changed part back to the 256-bit vector
6781 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6784 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
6785 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6787 if (EltVT == MVT::i8)
6790 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6791 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6792 // as its second argument.
6793 if (N1.getValueType() != MVT::i32)
6794 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6795 if (N2.getValueType() != MVT::i32)
6796 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6797 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6803 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6804 LLVMContext *Context = DAG.getContext();
6805 DebugLoc dl = Op.getDebugLoc();
6806 EVT OpVT = Op.getValueType();
6808 // If this is a 256-bit vector result, first insert into a 128-bit
6809 // vector and then insert into the 256-bit vector.
6810 if (OpVT.getSizeInBits() > 128) {
6811 // Insert into a 128-bit vector.
6812 EVT VT128 = EVT::getVectorVT(*Context,
6813 OpVT.getVectorElementType(),
6814 OpVT.getVectorNumElements() / 2);
6816 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6818 // Insert the 128-bit vector.
6819 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6820 DAG.getConstant(0, MVT::i32),
6824 if (Op.getValueType() == MVT::v1i64 &&
6825 Op.getOperand(0).getValueType() == MVT::i64)
6826 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6828 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6829 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6830 "Expected an SSE type!");
6831 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6832 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6835 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6836 // a simple subregister reference or explicit instructions to grab
6837 // upper bits of a vector.
6839 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6840 if (Subtarget->hasAVX()) {
6841 DebugLoc dl = Op.getNode()->getDebugLoc();
6842 SDValue Vec = Op.getNode()->getOperand(0);
6843 SDValue Idx = Op.getNode()->getOperand(1);
6845 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6846 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6847 return Extract128BitVector(Vec, Idx, DAG, dl);
6853 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6854 // simple superregister reference or explicit instructions to insert
6855 // the upper bits of a vector.
6857 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6858 if (Subtarget->hasAVX()) {
6859 DebugLoc dl = Op.getNode()->getDebugLoc();
6860 SDValue Vec = Op.getNode()->getOperand(0);
6861 SDValue SubVec = Op.getNode()->getOperand(1);
6862 SDValue Idx = Op.getNode()->getOperand(2);
6864 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6865 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6866 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6872 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6873 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6874 // one of the above mentioned nodes. It has to be wrapped because otherwise
6875 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6876 // be used to form addressing mode. These wrapped nodes will be selected
6879 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6880 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6882 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6884 unsigned char OpFlag = 0;
6885 unsigned WrapperKind = X86ISD::Wrapper;
6886 CodeModel::Model M = getTargetMachine().getCodeModel();
6888 if (Subtarget->isPICStyleRIPRel() &&
6889 (M == CodeModel::Small || M == CodeModel::Kernel))
6890 WrapperKind = X86ISD::WrapperRIP;
6891 else if (Subtarget->isPICStyleGOT())
6892 OpFlag = X86II::MO_GOTOFF;
6893 else if (Subtarget->isPICStyleStubPIC())
6894 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6896 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6898 CP->getOffset(), OpFlag);
6899 DebugLoc DL = CP->getDebugLoc();
6900 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6901 // With PIC, the address is actually $g + Offset.
6903 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6904 DAG.getNode(X86ISD::GlobalBaseReg,
6905 DebugLoc(), getPointerTy()),
6912 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6913 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6915 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6917 unsigned char OpFlag = 0;
6918 unsigned WrapperKind = X86ISD::Wrapper;
6919 CodeModel::Model M = getTargetMachine().getCodeModel();
6921 if (Subtarget->isPICStyleRIPRel() &&
6922 (M == CodeModel::Small || M == CodeModel::Kernel))
6923 WrapperKind = X86ISD::WrapperRIP;
6924 else if (Subtarget->isPICStyleGOT())
6925 OpFlag = X86II::MO_GOTOFF;
6926 else if (Subtarget->isPICStyleStubPIC())
6927 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6929 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6931 DebugLoc DL = JT->getDebugLoc();
6932 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6934 // With PIC, the address is actually $g + Offset.
6936 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6937 DAG.getNode(X86ISD::GlobalBaseReg,
6938 DebugLoc(), getPointerTy()),
6945 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
6946 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
6948 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6950 unsigned char OpFlag = 0;
6951 unsigned WrapperKind = X86ISD::Wrapper;
6952 CodeModel::Model M = getTargetMachine().getCodeModel();
6954 if (Subtarget->isPICStyleRIPRel() &&
6955 (M == CodeModel::Small || M == CodeModel::Kernel)) {
6956 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
6957 OpFlag = X86II::MO_GOTPCREL;
6958 WrapperKind = X86ISD::WrapperRIP;
6959 } else if (Subtarget->isPICStyleGOT()) {
6960 OpFlag = X86II::MO_GOT;
6961 } else if (Subtarget->isPICStyleStubPIC()) {
6962 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
6963 } else if (Subtarget->isPICStyleStubNoDynamic()) {
6964 OpFlag = X86II::MO_DARWIN_NONLAZY;
6967 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
6969 DebugLoc DL = Op.getDebugLoc();
6970 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6973 // With PIC, the address is actually $g + Offset.
6974 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
6975 !Subtarget->is64Bit()) {
6976 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6977 DAG.getNode(X86ISD::GlobalBaseReg,
6978 DebugLoc(), getPointerTy()),
6982 // For symbols that require a load from a stub to get the address, emit the
6984 if (isGlobalStubReference(OpFlag))
6985 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
6986 MachinePointerInfo::getGOT(), false, false, 0);
6992 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
6993 // Create the TargetBlockAddressAddress node.
6994 unsigned char OpFlags =
6995 Subtarget->ClassifyBlockAddressReference();
6996 CodeModel::Model M = getTargetMachine().getCodeModel();
6997 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
6998 DebugLoc dl = Op.getDebugLoc();
6999 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7000 /*isTarget=*/true, OpFlags);
7002 if (Subtarget->isPICStyleRIPRel() &&
7003 (M == CodeModel::Small || M == CodeModel::Kernel))
7004 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7006 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7008 // With PIC, the address is actually $g + Offset.
7009 if (isGlobalRelativeToPICBase(OpFlags)) {
7010 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7011 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7019 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7021 SelectionDAG &DAG) const {
7022 // Create the TargetGlobalAddress node, folding in the constant
7023 // offset if it is legal.
7024 unsigned char OpFlags =
7025 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7026 CodeModel::Model M = getTargetMachine().getCodeModel();
7028 if (OpFlags == X86II::MO_NO_FLAG &&
7029 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7030 // A direct static reference to a global.
7031 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7034 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7037 if (Subtarget->isPICStyleRIPRel() &&
7038 (M == CodeModel::Small || M == CodeModel::Kernel))
7039 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7041 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7043 // With PIC, the address is actually $g + Offset.
7044 if (isGlobalRelativeToPICBase(OpFlags)) {
7045 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7046 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7050 // For globals that require a load from a stub to get the address, emit the
7052 if (isGlobalStubReference(OpFlags))
7053 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7054 MachinePointerInfo::getGOT(), false, false, 0);
7056 // If there was a non-zero offset that we didn't fold, create an explicit
7059 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7060 DAG.getConstant(Offset, getPointerTy()));
7066 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7067 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7068 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7069 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7073 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7074 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7075 unsigned char OperandFlags) {
7076 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7077 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7078 DebugLoc dl = GA->getDebugLoc();
7079 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7080 GA->getValueType(0),
7084 SDValue Ops[] = { Chain, TGA, *InFlag };
7085 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7087 SDValue Ops[] = { Chain, TGA };
7088 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7091 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7092 MFI->setAdjustsStack(true);
7094 SDValue Flag = Chain.getValue(1);
7095 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7098 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7100 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7103 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7104 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7105 DAG.getNode(X86ISD::GlobalBaseReg,
7106 DebugLoc(), PtrVT), InFlag);
7107 InFlag = Chain.getValue(1);
7109 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7112 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7114 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7116 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7117 X86::RAX, X86II::MO_TLSGD);
7120 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7121 // "local exec" model.
7122 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7123 const EVT PtrVT, TLSModel::Model model,
7125 DebugLoc dl = GA->getDebugLoc();
7127 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7128 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7129 is64Bit ? 257 : 256));
7131 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7132 DAG.getIntPtrConstant(0),
7133 MachinePointerInfo(Ptr), false, false, 0);
7135 unsigned char OperandFlags = 0;
7136 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7138 unsigned WrapperKind = X86ISD::Wrapper;
7139 if (model == TLSModel::LocalExec) {
7140 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7141 } else if (is64Bit) {
7142 assert(model == TLSModel::InitialExec);
7143 OperandFlags = X86II::MO_GOTTPOFF;
7144 WrapperKind = X86ISD::WrapperRIP;
7146 assert(model == TLSModel::InitialExec);
7147 OperandFlags = X86II::MO_INDNTPOFF;
7150 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7152 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7153 GA->getValueType(0),
7154 GA->getOffset(), OperandFlags);
7155 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7157 if (model == TLSModel::InitialExec)
7158 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7159 MachinePointerInfo::getGOT(), false, false, 0);
7161 // The address of the thread local variable is the add of the thread
7162 // pointer with the offset of the variable.
7163 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7167 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7169 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7170 const GlobalValue *GV = GA->getGlobal();
7172 if (Subtarget->isTargetELF()) {
7173 // TODO: implement the "local dynamic" model
7174 // TODO: implement the "initial exec"model for pic executables
7176 // If GV is an alias then use the aliasee for determining
7177 // thread-localness.
7178 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7179 GV = GA->resolveAliasedGlobal(false);
7181 TLSModel::Model model
7182 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7185 case TLSModel::GeneralDynamic:
7186 case TLSModel::LocalDynamic: // not implemented
7187 if (Subtarget->is64Bit())
7188 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7189 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7191 case TLSModel::InitialExec:
7192 case TLSModel::LocalExec:
7193 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7194 Subtarget->is64Bit());
7196 } else if (Subtarget->isTargetDarwin()) {
7197 // Darwin only has one model of TLS. Lower to that.
7198 unsigned char OpFlag = 0;
7199 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7200 X86ISD::WrapperRIP : X86ISD::Wrapper;
7202 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7204 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7205 !Subtarget->is64Bit();
7207 OpFlag = X86II::MO_TLVP_PIC_BASE;
7209 OpFlag = X86II::MO_TLVP;
7210 DebugLoc DL = Op.getDebugLoc();
7211 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7212 GA->getValueType(0),
7213 GA->getOffset(), OpFlag);
7214 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7216 // With PIC32, the address is actually $g + Offset.
7218 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7219 DAG.getNode(X86ISD::GlobalBaseReg,
7220 DebugLoc(), getPointerTy()),
7223 // Lowering the machine isd will make sure everything is in the right
7225 SDValue Chain = DAG.getEntryNode();
7226 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7227 SDValue Args[] = { Chain, Offset };
7228 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7230 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7231 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7232 MFI->setAdjustsStack(true);
7234 // And our return value (tls address) is in the standard call return value
7236 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7237 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7241 "TLS not implemented for this target.");
7243 llvm_unreachable("Unreachable");
7248 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7249 /// take a 2 x i32 value to shift plus a shift amount.
7250 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7251 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7252 EVT VT = Op.getValueType();
7253 unsigned VTBits = VT.getSizeInBits();
7254 DebugLoc dl = Op.getDebugLoc();
7255 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7256 SDValue ShOpLo = Op.getOperand(0);
7257 SDValue ShOpHi = Op.getOperand(1);
7258 SDValue ShAmt = Op.getOperand(2);
7259 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7260 DAG.getConstant(VTBits - 1, MVT::i8))
7261 : DAG.getConstant(0, VT);
7264 if (Op.getOpcode() == ISD::SHL_PARTS) {
7265 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7266 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7268 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7269 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7272 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7273 DAG.getConstant(VTBits, MVT::i8));
7274 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7275 AndNode, DAG.getConstant(0, MVT::i8));
7278 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7279 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7280 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7282 if (Op.getOpcode() == ISD::SHL_PARTS) {
7283 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7284 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7286 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7287 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7290 SDValue Ops[2] = { Lo, Hi };
7291 return DAG.getMergeValues(Ops, 2, dl);
7294 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7295 SelectionDAG &DAG) const {
7296 EVT SrcVT = Op.getOperand(0).getValueType();
7298 if (SrcVT.isVector())
7301 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7302 "Unknown SINT_TO_FP to lower!");
7304 // These are really Legal; return the operand so the caller accepts it as
7306 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7308 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7309 Subtarget->is64Bit()) {
7313 DebugLoc dl = Op.getDebugLoc();
7314 unsigned Size = SrcVT.getSizeInBits()/8;
7315 MachineFunction &MF = DAG.getMachineFunction();
7316 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7317 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7318 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7320 MachinePointerInfo::getFixedStack(SSFI),
7322 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7325 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7327 SelectionDAG &DAG) const {
7329 DebugLoc DL = Op.getDebugLoc();
7331 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7333 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7335 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7337 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7339 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7340 MachineMemOperand *MMO;
7342 int SSFI = FI->getIndex();
7344 DAG.getMachineFunction()
7345 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7346 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7348 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7349 StackSlot = StackSlot.getOperand(1);
7351 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7352 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7354 Tys, Ops, array_lengthof(Ops),
7358 Chain = Result.getValue(1);
7359 SDValue InFlag = Result.getValue(2);
7361 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7362 // shouldn't be necessary except that RFP cannot be live across
7363 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7364 MachineFunction &MF = DAG.getMachineFunction();
7365 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7366 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7367 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7368 Tys = DAG.getVTList(MVT::Other);
7370 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7372 MachineMemOperand *MMO =
7373 DAG.getMachineFunction()
7374 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7375 MachineMemOperand::MOStore, SSFISize, SSFISize);
7377 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7378 Ops, array_lengthof(Ops),
7379 Op.getValueType(), MMO);
7380 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7381 MachinePointerInfo::getFixedStack(SSFI),
7388 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7389 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7390 SelectionDAG &DAG) const {
7391 // This algorithm is not obvious. Here it is in C code, more or less:
7393 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7394 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7395 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7397 // Copy ints to xmm registers.
7398 __m128i xh = _mm_cvtsi32_si128( hi );
7399 __m128i xl = _mm_cvtsi32_si128( lo );
7401 // Combine into low half of a single xmm register.
7402 __m128i x = _mm_unpacklo_epi32( xh, xl );
7406 // Merge in appropriate exponents to give the integer bits the right
7408 x = _mm_unpacklo_epi32( x, exp );
7410 // Subtract away the biases to deal with the IEEE-754 double precision
7412 d = _mm_sub_pd( (__m128d) x, bias );
7414 // All conversions up to here are exact. The correctly rounded result is
7415 // calculated using the current rounding mode using the following
7417 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7418 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7419 // store doesn't really need to be here (except
7420 // maybe to zero the other double)
7425 DebugLoc dl = Op.getDebugLoc();
7426 LLVMContext *Context = DAG.getContext();
7428 // Build some magic constants.
7429 std::vector<Constant*> CV0;
7430 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7431 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7432 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7433 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7434 Constant *C0 = ConstantVector::get(CV0);
7435 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7437 std::vector<Constant*> CV1;
7439 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7441 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7442 Constant *C1 = ConstantVector::get(CV1);
7443 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7445 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7446 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7448 DAG.getIntPtrConstant(1)));
7449 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7450 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7452 DAG.getIntPtrConstant(0)));
7453 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7454 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7455 MachinePointerInfo::getConstantPool(),
7457 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7458 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7459 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7460 MachinePointerInfo::getConstantPool(),
7462 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7464 // Add the halves; easiest way is to swap them into another reg first.
7465 int ShufMask[2] = { 1, -1 };
7466 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7467 DAG.getUNDEF(MVT::v2f64), ShufMask);
7468 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7469 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7470 DAG.getIntPtrConstant(0));
7473 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7474 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7475 SelectionDAG &DAG) const {
7476 DebugLoc dl = Op.getDebugLoc();
7477 // FP constant to bias correct the final result.
7478 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7481 // Load the 32-bit value into an XMM register.
7482 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7485 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7486 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7487 DAG.getIntPtrConstant(0));
7489 // Or the load with the bias.
7490 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7491 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7492 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7494 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7495 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7496 MVT::v2f64, Bias)));
7497 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7498 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7499 DAG.getIntPtrConstant(0));
7501 // Subtract the bias.
7502 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7504 // Handle final rounding.
7505 EVT DestVT = Op.getValueType();
7507 if (DestVT.bitsLT(MVT::f64)) {
7508 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7509 DAG.getIntPtrConstant(0));
7510 } else if (DestVT.bitsGT(MVT::f64)) {
7511 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7514 // Handle final rounding.
7518 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7519 SelectionDAG &DAG) const {
7520 SDValue N0 = Op.getOperand(0);
7521 DebugLoc dl = Op.getDebugLoc();
7523 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7524 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7525 // the optimization here.
7526 if (DAG.SignBitIsZero(N0))
7527 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7529 EVT SrcVT = N0.getValueType();
7530 EVT DstVT = Op.getValueType();
7531 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7532 return LowerUINT_TO_FP_i64(Op, DAG);
7533 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7534 return LowerUINT_TO_FP_i32(Op, DAG);
7536 // Make a 64-bit buffer, and use it to build an FILD.
7537 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7538 if (SrcVT == MVT::i32) {
7539 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7540 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7541 getPointerTy(), StackSlot, WordOff);
7542 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7543 StackSlot, MachinePointerInfo(),
7545 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7546 OffsetSlot, MachinePointerInfo(),
7548 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7552 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7553 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7554 StackSlot, MachinePointerInfo(),
7556 // For i64 source, we need to add the appropriate power of 2 if the input
7557 // was negative. This is the same as the optimization in
7558 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7559 // we must be careful to do the computation in x87 extended precision, not
7560 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7561 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7562 MachineMemOperand *MMO =
7563 DAG.getMachineFunction()
7564 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7565 MachineMemOperand::MOLoad, 8, 8);
7567 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7568 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7569 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7572 APInt FF(32, 0x5F800000ULL);
7574 // Check whether the sign bit is set.
7575 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7576 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7579 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7580 SDValue FudgePtr = DAG.getConstantPool(
7581 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7584 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7585 SDValue Zero = DAG.getIntPtrConstant(0);
7586 SDValue Four = DAG.getIntPtrConstant(4);
7587 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7589 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7591 // Load the value out, extending it from f32 to f80.
7592 // FIXME: Avoid the extend by constructing the right constant pool?
7593 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7594 FudgePtr, MachinePointerInfo::getConstantPool(),
7595 MVT::f32, false, false, 4);
7596 // Extend everything to 80 bits to force it to be done on x87.
7597 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7598 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7601 std::pair<SDValue,SDValue> X86TargetLowering::
7602 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7603 DebugLoc DL = Op.getDebugLoc();
7605 EVT DstTy = Op.getValueType();
7608 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7612 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7613 DstTy.getSimpleVT() >= MVT::i16 &&
7614 "Unknown FP_TO_SINT to lower!");
7616 // These are really Legal.
7617 if (DstTy == MVT::i32 &&
7618 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7619 return std::make_pair(SDValue(), SDValue());
7620 if (Subtarget->is64Bit() &&
7621 DstTy == MVT::i64 &&
7622 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7623 return std::make_pair(SDValue(), SDValue());
7625 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7627 MachineFunction &MF = DAG.getMachineFunction();
7628 unsigned MemSize = DstTy.getSizeInBits()/8;
7629 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7630 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7635 switch (DstTy.getSimpleVT().SimpleTy) {
7636 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7637 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7638 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7639 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7642 SDValue Chain = DAG.getEntryNode();
7643 SDValue Value = Op.getOperand(0);
7644 EVT TheVT = Op.getOperand(0).getValueType();
7645 if (isScalarFPTypeInSSEReg(TheVT)) {
7646 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7647 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7648 MachinePointerInfo::getFixedStack(SSFI),
7650 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7652 Chain, StackSlot, DAG.getValueType(TheVT)
7655 MachineMemOperand *MMO =
7656 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7657 MachineMemOperand::MOLoad, MemSize, MemSize);
7658 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7660 Chain = Value.getValue(1);
7661 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7662 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7665 MachineMemOperand *MMO =
7666 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7667 MachineMemOperand::MOStore, MemSize, MemSize);
7669 // Build the FP_TO_INT*_IN_MEM
7670 SDValue Ops[] = { Chain, Value, StackSlot };
7671 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7672 Ops, 3, DstTy, MMO);
7674 return std::make_pair(FIST, StackSlot);
7677 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7678 SelectionDAG &DAG) const {
7679 if (Op.getValueType().isVector())
7682 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7683 SDValue FIST = Vals.first, StackSlot = Vals.second;
7684 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7685 if (FIST.getNode() == 0) return Op;
7688 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7689 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7692 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7693 SelectionDAG &DAG) const {
7694 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7695 SDValue FIST = Vals.first, StackSlot = Vals.second;
7696 assert(FIST.getNode() && "Unexpected failure");
7699 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7700 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7703 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7704 SelectionDAG &DAG) const {
7705 LLVMContext *Context = DAG.getContext();
7706 DebugLoc dl = Op.getDebugLoc();
7707 EVT VT = Op.getValueType();
7710 EltVT = VT.getVectorElementType();
7711 std::vector<Constant*> CV;
7712 if (EltVT == MVT::f64) {
7713 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7717 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7723 Constant *C = ConstantVector::get(CV);
7724 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7725 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7726 MachinePointerInfo::getConstantPool(),
7728 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7731 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7732 LLVMContext *Context = DAG.getContext();
7733 DebugLoc dl = Op.getDebugLoc();
7734 EVT VT = Op.getValueType();
7737 EltVT = VT.getVectorElementType();
7738 std::vector<Constant*> CV;
7739 if (EltVT == MVT::f64) {
7740 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7744 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7750 Constant *C = ConstantVector::get(CV);
7751 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7752 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7753 MachinePointerInfo::getConstantPool(),
7755 if (VT.isVector()) {
7756 return DAG.getNode(ISD::BITCAST, dl, VT,
7757 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7758 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7760 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7762 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7766 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7767 LLVMContext *Context = DAG.getContext();
7768 SDValue Op0 = Op.getOperand(0);
7769 SDValue Op1 = Op.getOperand(1);
7770 DebugLoc dl = Op.getDebugLoc();
7771 EVT VT = Op.getValueType();
7772 EVT SrcVT = Op1.getValueType();
7774 // If second operand is smaller, extend it first.
7775 if (SrcVT.bitsLT(VT)) {
7776 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7779 // And if it is bigger, shrink it first.
7780 if (SrcVT.bitsGT(VT)) {
7781 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7785 // At this point the operands and the result should have the same
7786 // type, and that won't be f80 since that is not custom lowered.
7788 // First get the sign bit of second operand.
7789 std::vector<Constant*> CV;
7790 if (SrcVT == MVT::f64) {
7791 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7792 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7794 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7795 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7796 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7797 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7799 Constant *C = ConstantVector::get(CV);
7800 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7801 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7802 MachinePointerInfo::getConstantPool(),
7804 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7806 // Shift sign bit right or left if the two operands have different types.
7807 if (SrcVT.bitsGT(VT)) {
7808 // Op0 is MVT::f32, Op1 is MVT::f64.
7809 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7810 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7811 DAG.getConstant(32, MVT::i32));
7812 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7813 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7814 DAG.getIntPtrConstant(0));
7817 // Clear first operand sign bit.
7819 if (VT == MVT::f64) {
7820 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7821 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7823 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7824 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7825 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7826 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7828 C = ConstantVector::get(CV);
7829 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7830 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7831 MachinePointerInfo::getConstantPool(),
7833 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7835 // Or the value with the sign bit.
7836 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7839 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7840 SDValue N0 = Op.getOperand(0);
7841 DebugLoc dl = Op.getDebugLoc();
7842 EVT VT = Op.getValueType();
7844 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7845 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7846 DAG.getConstant(1, VT));
7847 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7850 /// Emit nodes that will be selected as "test Op0,Op0", or something
7852 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7853 SelectionDAG &DAG) const {
7854 DebugLoc dl = Op.getDebugLoc();
7856 // CF and OF aren't always set the way we want. Determine which
7857 // of these we need.
7858 bool NeedCF = false;
7859 bool NeedOF = false;
7862 case X86::COND_A: case X86::COND_AE:
7863 case X86::COND_B: case X86::COND_BE:
7866 case X86::COND_G: case X86::COND_GE:
7867 case X86::COND_L: case X86::COND_LE:
7868 case X86::COND_O: case X86::COND_NO:
7873 // See if we can use the EFLAGS value from the operand instead of
7874 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
7875 // we prove that the arithmetic won't overflow, we can't use OF or CF.
7876 if (Op.getResNo() != 0 || NeedOF || NeedCF)
7877 // Emit a CMP with 0, which is the TEST pattern.
7878 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7879 DAG.getConstant(0, Op.getValueType()));
7881 unsigned Opcode = 0;
7882 unsigned NumOperands = 0;
7883 switch (Op.getNode()->getOpcode()) {
7885 // Due to an isel shortcoming, be conservative if this add is likely to be
7886 // selected as part of a load-modify-store instruction. When the root node
7887 // in a match is a store, isel doesn't know how to remap non-chain non-flag
7888 // uses of other nodes in the match, such as the ADD in this case. This
7889 // leads to the ADD being left around and reselected, with the result being
7890 // two adds in the output. Alas, even if none our users are stores, that
7891 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
7892 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7893 // climbing the DAG back to the root, and it doesn't seem to be worth the
7895 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7896 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7897 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
7900 if (ConstantSDNode *C =
7901 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
7902 // An add of one will be selected as an INC.
7903 if (C->getAPIntValue() == 1) {
7904 Opcode = X86ISD::INC;
7909 // An add of negative one (subtract of one) will be selected as a DEC.
7910 if (C->getAPIntValue().isAllOnesValue()) {
7911 Opcode = X86ISD::DEC;
7917 // Otherwise use a regular EFLAGS-setting add.
7918 Opcode = X86ISD::ADD;
7922 // If the primary and result isn't used, don't bother using X86ISD::AND,
7923 // because a TEST instruction will be better.
7924 bool NonFlagUse = false;
7925 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7926 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
7928 unsigned UOpNo = UI.getOperandNo();
7929 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
7930 // Look pass truncate.
7931 UOpNo = User->use_begin().getOperandNo();
7932 User = *User->use_begin();
7935 if (User->getOpcode() != ISD::BRCOND &&
7936 User->getOpcode() != ISD::SETCC &&
7937 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
7950 // Due to the ISEL shortcoming noted above, be conservative if this op is
7951 // likely to be selected as part of a load-modify-store instruction.
7952 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7953 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7954 if (UI->getOpcode() == ISD::STORE)
7957 // Otherwise use a regular EFLAGS-setting instruction.
7958 switch (Op.getNode()->getOpcode()) {
7959 default: llvm_unreachable("unexpected operator!");
7960 case ISD::SUB: Opcode = X86ISD::SUB; break;
7961 case ISD::OR: Opcode = X86ISD::OR; break;
7962 case ISD::XOR: Opcode = X86ISD::XOR; break;
7963 case ISD::AND: Opcode = X86ISD::AND; break;
7975 return SDValue(Op.getNode(), 1);
7982 // Emit a CMP with 0, which is the TEST pattern.
7983 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7984 DAG.getConstant(0, Op.getValueType()));
7986 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
7987 SmallVector<SDValue, 4> Ops;
7988 for (unsigned i = 0; i != NumOperands; ++i)
7989 Ops.push_back(Op.getOperand(i));
7991 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
7992 DAG.ReplaceAllUsesWith(Op, New);
7993 return SDValue(New.getNode(), 1);
7996 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
7998 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
7999 SelectionDAG &DAG) const {
8000 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8001 if (C->getAPIntValue() == 0)
8002 return EmitTest(Op0, X86CC, DAG);
8004 DebugLoc dl = Op0.getDebugLoc();
8005 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8008 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8009 /// if it's possible.
8010 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8011 DebugLoc dl, SelectionDAG &DAG) const {
8012 SDValue Op0 = And.getOperand(0);
8013 SDValue Op1 = And.getOperand(1);
8014 if (Op0.getOpcode() == ISD::TRUNCATE)
8015 Op0 = Op0.getOperand(0);
8016 if (Op1.getOpcode() == ISD::TRUNCATE)
8017 Op1 = Op1.getOperand(0);
8020 if (Op1.getOpcode() == ISD::SHL)
8021 std::swap(Op0, Op1);
8022 if (Op0.getOpcode() == ISD::SHL) {
8023 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8024 if (And00C->getZExtValue() == 1) {
8025 // If we looked past a truncate, check that it's only truncating away
8027 unsigned BitWidth = Op0.getValueSizeInBits();
8028 unsigned AndBitWidth = And.getValueSizeInBits();
8029 if (BitWidth > AndBitWidth) {
8030 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8031 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8032 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8036 RHS = Op0.getOperand(1);
8038 } else if (Op1.getOpcode() == ISD::Constant) {
8039 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8040 SDValue AndLHS = Op0;
8041 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8042 LHS = AndLHS.getOperand(0);
8043 RHS = AndLHS.getOperand(1);
8047 if (LHS.getNode()) {
8048 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8049 // instruction. Since the shift amount is in-range-or-undefined, we know
8050 // that doing a bittest on the i32 value is ok. We extend to i32 because
8051 // the encoding for the i16 version is larger than the i32 version.
8052 // Also promote i16 to i32 for performance / code size reason.
8053 if (LHS.getValueType() == MVT::i8 ||
8054 LHS.getValueType() == MVT::i16)
8055 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8057 // If the operand types disagree, extend the shift amount to match. Since
8058 // BT ignores high bits (like shifts) we can use anyextend.
8059 if (LHS.getValueType() != RHS.getValueType())
8060 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8062 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8063 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8064 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8065 DAG.getConstant(Cond, MVT::i8), BT);
8071 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8072 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8073 SDValue Op0 = Op.getOperand(0);
8074 SDValue Op1 = Op.getOperand(1);
8075 DebugLoc dl = Op.getDebugLoc();
8076 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8078 // Optimize to BT if possible.
8079 // Lower (X & (1 << N)) == 0 to BT(X, N).
8080 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8081 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8082 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8083 Op1.getOpcode() == ISD::Constant &&
8084 cast<ConstantSDNode>(Op1)->isNullValue() &&
8085 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8086 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8087 if (NewSetCC.getNode())
8091 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8093 if (Op1.getOpcode() == ISD::Constant &&
8094 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8095 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8096 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8098 // If the input is a setcc, then reuse the input setcc or use a new one with
8099 // the inverted condition.
8100 if (Op0.getOpcode() == X86ISD::SETCC) {
8101 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8102 bool Invert = (CC == ISD::SETNE) ^
8103 cast<ConstantSDNode>(Op1)->isNullValue();
8104 if (!Invert) return Op0;
8106 CCode = X86::GetOppositeBranchCondition(CCode);
8107 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8108 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8112 bool isFP = Op1.getValueType().isFloatingPoint();
8113 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8114 if (X86CC == X86::COND_INVALID)
8117 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8118 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8119 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8122 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8123 // ones, and then concatenate the result back.
8124 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8125 EVT VT = Op.getValueType();
8127 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
8128 "Unsupported value type for operation");
8130 int NumElems = VT.getVectorNumElements();
8131 DebugLoc dl = Op.getDebugLoc();
8132 SDValue CC = Op.getOperand(2);
8133 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8134 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8136 // Extract the LHS vectors
8137 SDValue LHS = Op.getOperand(0);
8138 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8139 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8141 // Extract the RHS vectors
8142 SDValue RHS = Op.getOperand(1);
8143 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8144 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8146 // Issue the operation on the smaller types and concatenate the result back
8147 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8148 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8149 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8150 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8151 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8155 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8157 SDValue Op0 = Op.getOperand(0);
8158 SDValue Op1 = Op.getOperand(1);
8159 SDValue CC = Op.getOperand(2);
8160 EVT VT = Op.getValueType();
8161 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8162 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8163 DebugLoc dl = Op.getDebugLoc();
8167 EVT EltVT = Op0.getValueType().getVectorElementType();
8168 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8170 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8173 switch (SetCCOpcode) {
8176 case ISD::SETEQ: SSECC = 0; break;
8178 case ISD::SETGT: Swap = true; // Fallthrough
8180 case ISD::SETOLT: SSECC = 1; break;
8182 case ISD::SETGE: Swap = true; // Fallthrough
8184 case ISD::SETOLE: SSECC = 2; break;
8185 case ISD::SETUO: SSECC = 3; break;
8187 case ISD::SETNE: SSECC = 4; break;
8188 case ISD::SETULE: Swap = true;
8189 case ISD::SETUGE: SSECC = 5; break;
8190 case ISD::SETULT: Swap = true;
8191 case ISD::SETUGT: SSECC = 6; break;
8192 case ISD::SETO: SSECC = 7; break;
8195 std::swap(Op0, Op1);
8197 // In the two special cases we can't handle, emit two comparisons.
8199 if (SetCCOpcode == ISD::SETUEQ) {
8201 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8202 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8203 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8205 else if (SetCCOpcode == ISD::SETONE) {
8207 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8208 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8209 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8211 llvm_unreachable("Illegal FP comparison");
8213 // Handle all other FP comparisons here.
8214 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8217 // Break 256-bit integer vector compare into smaller ones.
8218 if (!isFP && VT.getSizeInBits() == 256)
8219 return Lower256IntVETCC(Op, DAG);
8221 // We are handling one of the integer comparisons here. Since SSE only has
8222 // GT and EQ comparisons for integer, swapping operands and multiple
8223 // operations may be required for some comparisons.
8224 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8225 bool Swap = false, Invert = false, FlipSigns = false;
8227 switch (VT.getSimpleVT().SimpleTy) {
8229 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8230 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8231 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8232 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8235 switch (SetCCOpcode) {
8237 case ISD::SETNE: Invert = true;
8238 case ISD::SETEQ: Opc = EQOpc; break;
8239 case ISD::SETLT: Swap = true;
8240 case ISD::SETGT: Opc = GTOpc; break;
8241 case ISD::SETGE: Swap = true;
8242 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8243 case ISD::SETULT: Swap = true;
8244 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8245 case ISD::SETUGE: Swap = true;
8246 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8249 std::swap(Op0, Op1);
8251 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8252 // bits of the inputs before performing those operations.
8254 EVT EltVT = VT.getVectorElementType();
8255 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8257 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8258 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8260 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8261 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8264 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8266 // If the logical-not of the result is required, perform that now.
8268 Result = DAG.getNOT(dl, Result, VT);
8273 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8274 static bool isX86LogicalCmp(SDValue Op) {
8275 unsigned Opc = Op.getNode()->getOpcode();
8276 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8278 if (Op.getResNo() == 1 &&
8279 (Opc == X86ISD::ADD ||
8280 Opc == X86ISD::SUB ||
8281 Opc == X86ISD::ADC ||
8282 Opc == X86ISD::SBB ||
8283 Opc == X86ISD::SMUL ||
8284 Opc == X86ISD::UMUL ||
8285 Opc == X86ISD::INC ||
8286 Opc == X86ISD::DEC ||
8287 Opc == X86ISD::OR ||
8288 Opc == X86ISD::XOR ||
8289 Opc == X86ISD::AND))
8292 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8298 static bool isZero(SDValue V) {
8299 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8300 return C && C->isNullValue();
8303 static bool isAllOnes(SDValue V) {
8304 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8305 return C && C->isAllOnesValue();
8308 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8309 bool addTest = true;
8310 SDValue Cond = Op.getOperand(0);
8311 SDValue Op1 = Op.getOperand(1);
8312 SDValue Op2 = Op.getOperand(2);
8313 DebugLoc DL = Op.getDebugLoc();
8316 if (Cond.getOpcode() == ISD::SETCC) {
8317 SDValue NewCond = LowerSETCC(Cond, DAG);
8318 if (NewCond.getNode())
8322 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8323 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8324 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8325 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8326 if (Cond.getOpcode() == X86ISD::SETCC &&
8327 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8328 isZero(Cond.getOperand(1).getOperand(1))) {
8329 SDValue Cmp = Cond.getOperand(1);
8331 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8333 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8334 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8335 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8337 SDValue CmpOp0 = Cmp.getOperand(0);
8338 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8339 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8341 SDValue Res = // Res = 0 or -1.
8342 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8343 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8345 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8346 Res = DAG.getNOT(DL, Res, Res.getValueType());
8348 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8349 if (N2C == 0 || !N2C->isNullValue())
8350 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8355 // Look past (and (setcc_carry (cmp ...)), 1).
8356 if (Cond.getOpcode() == ISD::AND &&
8357 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8358 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8359 if (C && C->getAPIntValue() == 1)
8360 Cond = Cond.getOperand(0);
8363 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8364 // setting operand in place of the X86ISD::SETCC.
8365 if (Cond.getOpcode() == X86ISD::SETCC ||
8366 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8367 CC = Cond.getOperand(0);
8369 SDValue Cmp = Cond.getOperand(1);
8370 unsigned Opc = Cmp.getOpcode();
8371 EVT VT = Op.getValueType();
8373 bool IllegalFPCMov = false;
8374 if (VT.isFloatingPoint() && !VT.isVector() &&
8375 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8376 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8378 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8379 Opc == X86ISD::BT) { // FIXME
8386 // Look pass the truncate.
8387 if (Cond.getOpcode() == ISD::TRUNCATE)
8388 Cond = Cond.getOperand(0);
8390 // We know the result of AND is compared against zero. Try to match
8392 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8393 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8394 if (NewSetCC.getNode()) {
8395 CC = NewSetCC.getOperand(0);
8396 Cond = NewSetCC.getOperand(1);
8403 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8404 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8407 // a < b ? -1 : 0 -> RES = ~setcc_carry
8408 // a < b ? 0 : -1 -> RES = setcc_carry
8409 // a >= b ? -1 : 0 -> RES = setcc_carry
8410 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8411 if (Cond.getOpcode() == X86ISD::CMP) {
8412 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8414 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8415 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8416 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8417 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8418 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8419 return DAG.getNOT(DL, Res, Res.getValueType());
8424 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8425 // condition is true.
8426 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8427 SDValue Ops[] = { Op2, Op1, CC, Cond };
8428 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8431 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8432 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8433 // from the AND / OR.
8434 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8435 Opc = Op.getOpcode();
8436 if (Opc != ISD::OR && Opc != ISD::AND)
8438 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8439 Op.getOperand(0).hasOneUse() &&
8440 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8441 Op.getOperand(1).hasOneUse());
8444 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8445 // 1 and that the SETCC node has a single use.
8446 static bool isXor1OfSetCC(SDValue Op) {
8447 if (Op.getOpcode() != ISD::XOR)
8449 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8450 if (N1C && N1C->getAPIntValue() == 1) {
8451 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8452 Op.getOperand(0).hasOneUse();
8457 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8458 bool addTest = true;
8459 SDValue Chain = Op.getOperand(0);
8460 SDValue Cond = Op.getOperand(1);
8461 SDValue Dest = Op.getOperand(2);
8462 DebugLoc dl = Op.getDebugLoc();
8465 if (Cond.getOpcode() == ISD::SETCC) {
8466 SDValue NewCond = LowerSETCC(Cond, DAG);
8467 if (NewCond.getNode())
8471 // FIXME: LowerXALUO doesn't handle these!!
8472 else if (Cond.getOpcode() == X86ISD::ADD ||
8473 Cond.getOpcode() == X86ISD::SUB ||
8474 Cond.getOpcode() == X86ISD::SMUL ||
8475 Cond.getOpcode() == X86ISD::UMUL)
8476 Cond = LowerXALUO(Cond, DAG);
8479 // Look pass (and (setcc_carry (cmp ...)), 1).
8480 if (Cond.getOpcode() == ISD::AND &&
8481 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8482 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8483 if (C && C->getAPIntValue() == 1)
8484 Cond = Cond.getOperand(0);
8487 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8488 // setting operand in place of the X86ISD::SETCC.
8489 if (Cond.getOpcode() == X86ISD::SETCC ||
8490 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8491 CC = Cond.getOperand(0);
8493 SDValue Cmp = Cond.getOperand(1);
8494 unsigned Opc = Cmp.getOpcode();
8495 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8496 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8500 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8504 // These can only come from an arithmetic instruction with overflow,
8505 // e.g. SADDO, UADDO.
8506 Cond = Cond.getNode()->getOperand(1);
8513 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8514 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8515 if (CondOpc == ISD::OR) {
8516 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8517 // two branches instead of an explicit OR instruction with a
8519 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8520 isX86LogicalCmp(Cmp)) {
8521 CC = Cond.getOperand(0).getOperand(0);
8522 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8523 Chain, Dest, CC, Cmp);
8524 CC = Cond.getOperand(1).getOperand(0);
8528 } else { // ISD::AND
8529 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8530 // two branches instead of an explicit AND instruction with a
8531 // separate test. However, we only do this if this block doesn't
8532 // have a fall-through edge, because this requires an explicit
8533 // jmp when the condition is false.
8534 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8535 isX86LogicalCmp(Cmp) &&
8536 Op.getNode()->hasOneUse()) {
8537 X86::CondCode CCode =
8538 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8539 CCode = X86::GetOppositeBranchCondition(CCode);
8540 CC = DAG.getConstant(CCode, MVT::i8);
8541 SDNode *User = *Op.getNode()->use_begin();
8542 // Look for an unconditional branch following this conditional branch.
8543 // We need this because we need to reverse the successors in order
8544 // to implement FCMP_OEQ.
8545 if (User->getOpcode() == ISD::BR) {
8546 SDValue FalseBB = User->getOperand(1);
8548 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8549 assert(NewBR == User);
8553 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8554 Chain, Dest, CC, Cmp);
8555 X86::CondCode CCode =
8556 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8557 CCode = X86::GetOppositeBranchCondition(CCode);
8558 CC = DAG.getConstant(CCode, MVT::i8);
8564 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8565 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8566 // It should be transformed during dag combiner except when the condition
8567 // is set by a arithmetics with overflow node.
8568 X86::CondCode CCode =
8569 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8570 CCode = X86::GetOppositeBranchCondition(CCode);
8571 CC = DAG.getConstant(CCode, MVT::i8);
8572 Cond = Cond.getOperand(0).getOperand(1);
8578 // Look pass the truncate.
8579 if (Cond.getOpcode() == ISD::TRUNCATE)
8580 Cond = Cond.getOperand(0);
8582 // We know the result of AND is compared against zero. Try to match
8584 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8585 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8586 if (NewSetCC.getNode()) {
8587 CC = NewSetCC.getOperand(0);
8588 Cond = NewSetCC.getOperand(1);
8595 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8596 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8598 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8599 Chain, Dest, CC, Cond);
8603 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8604 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8605 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8606 // that the guard pages used by the OS virtual memory manager are allocated in
8607 // correct sequence.
8609 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8610 SelectionDAG &DAG) const {
8611 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
8612 "This should be used only on Windows targets");
8613 assert(!Subtarget->isTargetEnvMacho());
8614 DebugLoc dl = Op.getDebugLoc();
8617 SDValue Chain = Op.getOperand(0);
8618 SDValue Size = Op.getOperand(1);
8619 // FIXME: Ensure alignment here
8623 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
8624 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8626 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8627 Flag = Chain.getValue(1);
8629 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8631 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8632 Flag = Chain.getValue(1);
8634 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8636 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8637 return DAG.getMergeValues(Ops1, 2, dl);
8640 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8641 MachineFunction &MF = DAG.getMachineFunction();
8642 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8644 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8645 DebugLoc DL = Op.getDebugLoc();
8647 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8648 // vastart just stores the address of the VarArgsFrameIndex slot into the
8649 // memory location argument.
8650 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8652 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8653 MachinePointerInfo(SV), false, false, 0);
8657 // gp_offset (0 - 6 * 8)
8658 // fp_offset (48 - 48 + 8 * 16)
8659 // overflow_arg_area (point to parameters coming in memory).
8661 SmallVector<SDValue, 8> MemOps;
8662 SDValue FIN = Op.getOperand(1);
8664 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8665 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8667 FIN, MachinePointerInfo(SV), false, false, 0);
8668 MemOps.push_back(Store);
8671 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8672 FIN, DAG.getIntPtrConstant(4));
8673 Store = DAG.getStore(Op.getOperand(0), DL,
8674 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8676 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8677 MemOps.push_back(Store);
8679 // Store ptr to overflow_arg_area
8680 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8681 FIN, DAG.getIntPtrConstant(4));
8682 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8684 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8685 MachinePointerInfo(SV, 8),
8687 MemOps.push_back(Store);
8689 // Store ptr to reg_save_area.
8690 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8691 FIN, DAG.getIntPtrConstant(8));
8692 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8694 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8695 MachinePointerInfo(SV, 16), false, false, 0);
8696 MemOps.push_back(Store);
8697 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8698 &MemOps[0], MemOps.size());
8701 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8702 assert(Subtarget->is64Bit() &&
8703 "LowerVAARG only handles 64-bit va_arg!");
8704 assert((Subtarget->isTargetLinux() ||
8705 Subtarget->isTargetDarwin()) &&
8706 "Unhandled target in LowerVAARG");
8707 assert(Op.getNode()->getNumOperands() == 4);
8708 SDValue Chain = Op.getOperand(0);
8709 SDValue SrcPtr = Op.getOperand(1);
8710 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8711 unsigned Align = Op.getConstantOperandVal(3);
8712 DebugLoc dl = Op.getDebugLoc();
8714 EVT ArgVT = Op.getNode()->getValueType(0);
8715 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8716 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8719 // Decide which area this value should be read from.
8720 // TODO: Implement the AMD64 ABI in its entirety. This simple
8721 // selection mechanism works only for the basic types.
8722 if (ArgVT == MVT::f80) {
8723 llvm_unreachable("va_arg for f80 not yet implemented");
8724 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8725 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8726 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8727 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8729 llvm_unreachable("Unhandled argument type in LowerVAARG");
8733 // Sanity Check: Make sure using fp_offset makes sense.
8734 assert(!UseSoftFloat &&
8735 !(DAG.getMachineFunction()
8736 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8737 Subtarget->hasXMM());
8740 // Insert VAARG_64 node into the DAG
8741 // VAARG_64 returns two values: Variable Argument Address, Chain
8742 SmallVector<SDValue, 11> InstOps;
8743 InstOps.push_back(Chain);
8744 InstOps.push_back(SrcPtr);
8745 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8746 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8747 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8748 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8749 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8750 VTs, &InstOps[0], InstOps.size(),
8752 MachinePointerInfo(SV),
8757 Chain = VAARG.getValue(1);
8759 // Load the next argument and return it
8760 return DAG.getLoad(ArgVT, dl,
8763 MachinePointerInfo(),
8767 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
8768 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
8769 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
8770 SDValue Chain = Op.getOperand(0);
8771 SDValue DstPtr = Op.getOperand(1);
8772 SDValue SrcPtr = Op.getOperand(2);
8773 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
8774 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8775 DebugLoc DL = Op.getDebugLoc();
8777 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
8778 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
8780 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
8784 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
8785 DebugLoc dl = Op.getDebugLoc();
8786 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8788 default: return SDValue(); // Don't custom lower most intrinsics.
8789 // Comparison intrinsics.
8790 case Intrinsic::x86_sse_comieq_ss:
8791 case Intrinsic::x86_sse_comilt_ss:
8792 case Intrinsic::x86_sse_comile_ss:
8793 case Intrinsic::x86_sse_comigt_ss:
8794 case Intrinsic::x86_sse_comige_ss:
8795 case Intrinsic::x86_sse_comineq_ss:
8796 case Intrinsic::x86_sse_ucomieq_ss:
8797 case Intrinsic::x86_sse_ucomilt_ss:
8798 case Intrinsic::x86_sse_ucomile_ss:
8799 case Intrinsic::x86_sse_ucomigt_ss:
8800 case Intrinsic::x86_sse_ucomige_ss:
8801 case Intrinsic::x86_sse_ucomineq_ss:
8802 case Intrinsic::x86_sse2_comieq_sd:
8803 case Intrinsic::x86_sse2_comilt_sd:
8804 case Intrinsic::x86_sse2_comile_sd:
8805 case Intrinsic::x86_sse2_comigt_sd:
8806 case Intrinsic::x86_sse2_comige_sd:
8807 case Intrinsic::x86_sse2_comineq_sd:
8808 case Intrinsic::x86_sse2_ucomieq_sd:
8809 case Intrinsic::x86_sse2_ucomilt_sd:
8810 case Intrinsic::x86_sse2_ucomile_sd:
8811 case Intrinsic::x86_sse2_ucomigt_sd:
8812 case Intrinsic::x86_sse2_ucomige_sd:
8813 case Intrinsic::x86_sse2_ucomineq_sd: {
8815 ISD::CondCode CC = ISD::SETCC_INVALID;
8818 case Intrinsic::x86_sse_comieq_ss:
8819 case Intrinsic::x86_sse2_comieq_sd:
8823 case Intrinsic::x86_sse_comilt_ss:
8824 case Intrinsic::x86_sse2_comilt_sd:
8828 case Intrinsic::x86_sse_comile_ss:
8829 case Intrinsic::x86_sse2_comile_sd:
8833 case Intrinsic::x86_sse_comigt_ss:
8834 case Intrinsic::x86_sse2_comigt_sd:
8838 case Intrinsic::x86_sse_comige_ss:
8839 case Intrinsic::x86_sse2_comige_sd:
8843 case Intrinsic::x86_sse_comineq_ss:
8844 case Intrinsic::x86_sse2_comineq_sd:
8848 case Intrinsic::x86_sse_ucomieq_ss:
8849 case Intrinsic::x86_sse2_ucomieq_sd:
8850 Opc = X86ISD::UCOMI;
8853 case Intrinsic::x86_sse_ucomilt_ss:
8854 case Intrinsic::x86_sse2_ucomilt_sd:
8855 Opc = X86ISD::UCOMI;
8858 case Intrinsic::x86_sse_ucomile_ss:
8859 case Intrinsic::x86_sse2_ucomile_sd:
8860 Opc = X86ISD::UCOMI;
8863 case Intrinsic::x86_sse_ucomigt_ss:
8864 case Intrinsic::x86_sse2_ucomigt_sd:
8865 Opc = X86ISD::UCOMI;
8868 case Intrinsic::x86_sse_ucomige_ss:
8869 case Intrinsic::x86_sse2_ucomige_sd:
8870 Opc = X86ISD::UCOMI;
8873 case Intrinsic::x86_sse_ucomineq_ss:
8874 case Intrinsic::x86_sse2_ucomineq_sd:
8875 Opc = X86ISD::UCOMI;
8880 SDValue LHS = Op.getOperand(1);
8881 SDValue RHS = Op.getOperand(2);
8882 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
8883 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
8884 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
8885 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8886 DAG.getConstant(X86CC, MVT::i8), Cond);
8887 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8889 // ptest and testp intrinsics. The intrinsic these come from are designed to
8890 // return an integer value, not just an instruction so lower it to the ptest
8891 // or testp pattern and a setcc for the result.
8892 case Intrinsic::x86_sse41_ptestz:
8893 case Intrinsic::x86_sse41_ptestc:
8894 case Intrinsic::x86_sse41_ptestnzc:
8895 case Intrinsic::x86_avx_ptestz_256:
8896 case Intrinsic::x86_avx_ptestc_256:
8897 case Intrinsic::x86_avx_ptestnzc_256:
8898 case Intrinsic::x86_avx_vtestz_ps:
8899 case Intrinsic::x86_avx_vtestc_ps:
8900 case Intrinsic::x86_avx_vtestnzc_ps:
8901 case Intrinsic::x86_avx_vtestz_pd:
8902 case Intrinsic::x86_avx_vtestc_pd:
8903 case Intrinsic::x86_avx_vtestnzc_pd:
8904 case Intrinsic::x86_avx_vtestz_ps_256:
8905 case Intrinsic::x86_avx_vtestc_ps_256:
8906 case Intrinsic::x86_avx_vtestnzc_ps_256:
8907 case Intrinsic::x86_avx_vtestz_pd_256:
8908 case Intrinsic::x86_avx_vtestc_pd_256:
8909 case Intrinsic::x86_avx_vtestnzc_pd_256: {
8910 bool IsTestPacked = false;
8913 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
8914 case Intrinsic::x86_avx_vtestz_ps:
8915 case Intrinsic::x86_avx_vtestz_pd:
8916 case Intrinsic::x86_avx_vtestz_ps_256:
8917 case Intrinsic::x86_avx_vtestz_pd_256:
8918 IsTestPacked = true; // Fallthrough
8919 case Intrinsic::x86_sse41_ptestz:
8920 case Intrinsic::x86_avx_ptestz_256:
8922 X86CC = X86::COND_E;
8924 case Intrinsic::x86_avx_vtestc_ps:
8925 case Intrinsic::x86_avx_vtestc_pd:
8926 case Intrinsic::x86_avx_vtestc_ps_256:
8927 case Intrinsic::x86_avx_vtestc_pd_256:
8928 IsTestPacked = true; // Fallthrough
8929 case Intrinsic::x86_sse41_ptestc:
8930 case Intrinsic::x86_avx_ptestc_256:
8932 X86CC = X86::COND_B;
8934 case Intrinsic::x86_avx_vtestnzc_ps:
8935 case Intrinsic::x86_avx_vtestnzc_pd:
8936 case Intrinsic::x86_avx_vtestnzc_ps_256:
8937 case Intrinsic::x86_avx_vtestnzc_pd_256:
8938 IsTestPacked = true; // Fallthrough
8939 case Intrinsic::x86_sse41_ptestnzc:
8940 case Intrinsic::x86_avx_ptestnzc_256:
8942 X86CC = X86::COND_A;
8946 SDValue LHS = Op.getOperand(1);
8947 SDValue RHS = Op.getOperand(2);
8948 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
8949 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
8950 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
8951 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
8952 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8955 // Fix vector shift instructions where the last operand is a non-immediate
8957 case Intrinsic::x86_sse2_pslli_w:
8958 case Intrinsic::x86_sse2_pslli_d:
8959 case Intrinsic::x86_sse2_pslli_q:
8960 case Intrinsic::x86_sse2_psrli_w:
8961 case Intrinsic::x86_sse2_psrli_d:
8962 case Intrinsic::x86_sse2_psrli_q:
8963 case Intrinsic::x86_sse2_psrai_w:
8964 case Intrinsic::x86_sse2_psrai_d:
8965 case Intrinsic::x86_mmx_pslli_w:
8966 case Intrinsic::x86_mmx_pslli_d:
8967 case Intrinsic::x86_mmx_pslli_q:
8968 case Intrinsic::x86_mmx_psrli_w:
8969 case Intrinsic::x86_mmx_psrli_d:
8970 case Intrinsic::x86_mmx_psrli_q:
8971 case Intrinsic::x86_mmx_psrai_w:
8972 case Intrinsic::x86_mmx_psrai_d: {
8973 SDValue ShAmt = Op.getOperand(2);
8974 if (isa<ConstantSDNode>(ShAmt))
8977 unsigned NewIntNo = 0;
8978 EVT ShAmtVT = MVT::v4i32;
8980 case Intrinsic::x86_sse2_pslli_w:
8981 NewIntNo = Intrinsic::x86_sse2_psll_w;
8983 case Intrinsic::x86_sse2_pslli_d:
8984 NewIntNo = Intrinsic::x86_sse2_psll_d;
8986 case Intrinsic::x86_sse2_pslli_q:
8987 NewIntNo = Intrinsic::x86_sse2_psll_q;
8989 case Intrinsic::x86_sse2_psrli_w:
8990 NewIntNo = Intrinsic::x86_sse2_psrl_w;
8992 case Intrinsic::x86_sse2_psrli_d:
8993 NewIntNo = Intrinsic::x86_sse2_psrl_d;
8995 case Intrinsic::x86_sse2_psrli_q:
8996 NewIntNo = Intrinsic::x86_sse2_psrl_q;
8998 case Intrinsic::x86_sse2_psrai_w:
8999 NewIntNo = Intrinsic::x86_sse2_psra_w;
9001 case Intrinsic::x86_sse2_psrai_d:
9002 NewIntNo = Intrinsic::x86_sse2_psra_d;
9005 ShAmtVT = MVT::v2i32;
9007 case Intrinsic::x86_mmx_pslli_w:
9008 NewIntNo = Intrinsic::x86_mmx_psll_w;
9010 case Intrinsic::x86_mmx_pslli_d:
9011 NewIntNo = Intrinsic::x86_mmx_psll_d;
9013 case Intrinsic::x86_mmx_pslli_q:
9014 NewIntNo = Intrinsic::x86_mmx_psll_q;
9016 case Intrinsic::x86_mmx_psrli_w:
9017 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9019 case Intrinsic::x86_mmx_psrli_d:
9020 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9022 case Intrinsic::x86_mmx_psrli_q:
9023 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9025 case Intrinsic::x86_mmx_psrai_w:
9026 NewIntNo = Intrinsic::x86_mmx_psra_w;
9028 case Intrinsic::x86_mmx_psrai_d:
9029 NewIntNo = Intrinsic::x86_mmx_psra_d;
9031 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9037 // The vector shift intrinsics with scalars uses 32b shift amounts but
9038 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9042 ShOps[1] = DAG.getConstant(0, MVT::i32);
9043 if (ShAmtVT == MVT::v4i32) {
9044 ShOps[2] = DAG.getUNDEF(MVT::i32);
9045 ShOps[3] = DAG.getUNDEF(MVT::i32);
9046 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9048 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9049 // FIXME this must be lowered to get rid of the invalid type.
9052 EVT VT = Op.getValueType();
9053 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9054 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9055 DAG.getConstant(NewIntNo, MVT::i32),
9056 Op.getOperand(1), ShAmt);
9061 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9062 SelectionDAG &DAG) const {
9063 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9064 MFI->setReturnAddressIsTaken(true);
9066 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9067 DebugLoc dl = Op.getDebugLoc();
9070 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9072 DAG.getConstant(TD->getPointerSize(),
9073 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9074 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9075 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9077 MachinePointerInfo(), false, false, 0);
9080 // Just load the return address.
9081 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9082 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9083 RetAddrFI, MachinePointerInfo(), false, false, 0);
9086 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9087 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9088 MFI->setFrameAddressIsTaken(true);
9090 EVT VT = Op.getValueType();
9091 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9092 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9093 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9094 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9096 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9097 MachinePointerInfo(),
9102 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9103 SelectionDAG &DAG) const {
9104 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9107 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9108 MachineFunction &MF = DAG.getMachineFunction();
9109 SDValue Chain = Op.getOperand(0);
9110 SDValue Offset = Op.getOperand(1);
9111 SDValue Handler = Op.getOperand(2);
9112 DebugLoc dl = Op.getDebugLoc();
9114 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9115 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9117 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9119 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9120 DAG.getIntPtrConstant(TD->getPointerSize()));
9121 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9122 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9124 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9125 MF.getRegInfo().addLiveOut(StoreAddrReg);
9127 return DAG.getNode(X86ISD::EH_RETURN, dl,
9129 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9132 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
9133 SelectionDAG &DAG) const {
9134 SDValue Root = Op.getOperand(0);
9135 SDValue Trmp = Op.getOperand(1); // trampoline
9136 SDValue FPtr = Op.getOperand(2); // nested function
9137 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9138 DebugLoc dl = Op.getDebugLoc();
9140 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9142 if (Subtarget->is64Bit()) {
9143 SDValue OutChains[6];
9145 // Large code-model.
9146 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9147 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9149 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9150 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9152 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9154 // Load the pointer to the nested function into R11.
9155 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9156 SDValue Addr = Trmp;
9157 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9158 Addr, MachinePointerInfo(TrmpAddr),
9161 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9162 DAG.getConstant(2, MVT::i64));
9163 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9164 MachinePointerInfo(TrmpAddr, 2),
9167 // Load the 'nest' parameter value into R10.
9168 // R10 is specified in X86CallingConv.td
9169 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9170 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9171 DAG.getConstant(10, MVT::i64));
9172 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9173 Addr, MachinePointerInfo(TrmpAddr, 10),
9176 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9177 DAG.getConstant(12, MVT::i64));
9178 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9179 MachinePointerInfo(TrmpAddr, 12),
9182 // Jump to the nested function.
9183 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9184 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9185 DAG.getConstant(20, MVT::i64));
9186 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9187 Addr, MachinePointerInfo(TrmpAddr, 20),
9190 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9191 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9192 DAG.getConstant(22, MVT::i64));
9193 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9194 MachinePointerInfo(TrmpAddr, 22),
9198 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
9199 return DAG.getMergeValues(Ops, 2, dl);
9201 const Function *Func =
9202 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9203 CallingConv::ID CC = Func->getCallingConv();
9208 llvm_unreachable("Unsupported calling convention");
9209 case CallingConv::C:
9210 case CallingConv::X86_StdCall: {
9211 // Pass 'nest' parameter in ECX.
9212 // Must be kept in sync with X86CallingConv.td
9215 // Check that ECX wasn't needed by an 'inreg' parameter.
9216 FunctionType *FTy = Func->getFunctionType();
9217 const AttrListPtr &Attrs = Func->getAttributes();
9219 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9220 unsigned InRegCount = 0;
9223 for (FunctionType::param_iterator I = FTy->param_begin(),
9224 E = FTy->param_end(); I != E; ++I, ++Idx)
9225 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9226 // FIXME: should only count parameters that are lowered to integers.
9227 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9229 if (InRegCount > 2) {
9230 report_fatal_error("Nest register in use - reduce number of inreg"
9236 case CallingConv::X86_FastCall:
9237 case CallingConv::X86_ThisCall:
9238 case CallingConv::Fast:
9239 // Pass 'nest' parameter in EAX.
9240 // Must be kept in sync with X86CallingConv.td
9245 SDValue OutChains[4];
9248 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9249 DAG.getConstant(10, MVT::i32));
9250 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9252 // This is storing the opcode for MOV32ri.
9253 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9254 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9255 OutChains[0] = DAG.getStore(Root, dl,
9256 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9257 Trmp, MachinePointerInfo(TrmpAddr),
9260 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9261 DAG.getConstant(1, MVT::i32));
9262 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9263 MachinePointerInfo(TrmpAddr, 1),
9266 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9267 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9268 DAG.getConstant(5, MVT::i32));
9269 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9270 MachinePointerInfo(TrmpAddr, 5),
9273 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9274 DAG.getConstant(6, MVT::i32));
9275 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9276 MachinePointerInfo(TrmpAddr, 6),
9280 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
9281 return DAG.getMergeValues(Ops, 2, dl);
9285 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9286 SelectionDAG &DAG) const {
9288 The rounding mode is in bits 11:10 of FPSR, and has the following
9295 FLT_ROUNDS, on the other hand, expects the following:
9302 To perform the conversion, we do:
9303 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9306 MachineFunction &MF = DAG.getMachineFunction();
9307 const TargetMachine &TM = MF.getTarget();
9308 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9309 unsigned StackAlignment = TFI.getStackAlignment();
9310 EVT VT = Op.getValueType();
9311 DebugLoc DL = Op.getDebugLoc();
9313 // Save FP Control Word to stack slot
9314 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9315 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9318 MachineMemOperand *MMO =
9319 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9320 MachineMemOperand::MOStore, 2, 2);
9322 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9323 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9324 DAG.getVTList(MVT::Other),
9325 Ops, 2, MVT::i16, MMO);
9327 // Load FP Control Word from stack slot
9328 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9329 MachinePointerInfo(), false, false, 0);
9331 // Transform as necessary
9333 DAG.getNode(ISD::SRL, DL, MVT::i16,
9334 DAG.getNode(ISD::AND, DL, MVT::i16,
9335 CWD, DAG.getConstant(0x800, MVT::i16)),
9336 DAG.getConstant(11, MVT::i8));
9338 DAG.getNode(ISD::SRL, DL, MVT::i16,
9339 DAG.getNode(ISD::AND, DL, MVT::i16,
9340 CWD, DAG.getConstant(0x400, MVT::i16)),
9341 DAG.getConstant(9, MVT::i8));
9344 DAG.getNode(ISD::AND, DL, MVT::i16,
9345 DAG.getNode(ISD::ADD, DL, MVT::i16,
9346 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9347 DAG.getConstant(1, MVT::i16)),
9348 DAG.getConstant(3, MVT::i16));
9351 return DAG.getNode((VT.getSizeInBits() < 16 ?
9352 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9355 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9356 EVT VT = Op.getValueType();
9358 unsigned NumBits = VT.getSizeInBits();
9359 DebugLoc dl = Op.getDebugLoc();
9361 Op = Op.getOperand(0);
9362 if (VT == MVT::i8) {
9363 // Zero extend to i32 since there is not an i8 bsr.
9365 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9368 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9369 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9370 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9372 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9375 DAG.getConstant(NumBits+NumBits-1, OpVT),
9376 DAG.getConstant(X86::COND_E, MVT::i8),
9379 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9381 // Finally xor with NumBits-1.
9382 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9385 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9389 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9390 EVT VT = Op.getValueType();
9392 unsigned NumBits = VT.getSizeInBits();
9393 DebugLoc dl = Op.getDebugLoc();
9395 Op = Op.getOperand(0);
9396 if (VT == MVT::i8) {
9398 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9401 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9402 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9403 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9405 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9408 DAG.getConstant(NumBits, OpVT),
9409 DAG.getConstant(X86::COND_E, MVT::i8),
9412 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9415 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9419 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
9420 EVT VT = Op.getValueType();
9421 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9422 DebugLoc dl = Op.getDebugLoc();
9424 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9425 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9426 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9427 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9428 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9430 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9431 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9432 // return AloBlo + AloBhi + AhiBlo;
9434 SDValue A = Op.getOperand(0);
9435 SDValue B = Op.getOperand(1);
9437 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9438 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9439 A, DAG.getConstant(32, MVT::i32));
9440 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9441 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9442 B, DAG.getConstant(32, MVT::i32));
9443 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9444 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9446 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9447 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9449 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9450 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9452 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9453 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9454 AloBhi, DAG.getConstant(32, MVT::i32));
9455 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9456 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9457 AhiBlo, DAG.getConstant(32, MVT::i32));
9458 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9459 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9463 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9465 EVT VT = Op.getValueType();
9466 DebugLoc dl = Op.getDebugLoc();
9467 SDValue R = Op.getOperand(0);
9468 SDValue Amt = Op.getOperand(1);
9469 LLVMContext *Context = DAG.getContext();
9471 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9474 // Decompose 256-bit shifts into smaller 128-bit shifts.
9475 if (VT.getSizeInBits() == 256) {
9476 int NumElems = VT.getVectorNumElements();
9477 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9478 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9480 // Extract the two vectors
9481 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9482 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9485 // Recreate the shift amount vectors
9487 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9488 // Constant shift amount
9489 SmallVector<SDValue, 4> Amt1Csts;
9490 SmallVector<SDValue, 4> Amt2Csts;
9491 for (int i = 0; i < NumElems/2; ++i)
9492 Amt1Csts.push_back(Amt->getOperand(i));
9493 for (int i = NumElems/2; i < NumElems; ++i)
9494 Amt2Csts.push_back(Amt->getOperand(i));
9496 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9497 &Amt1Csts[0], NumElems/2);
9498 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9499 &Amt2Csts[0], NumElems/2);
9501 // Variable shift amount
9502 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9503 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9507 // Issue new vector shifts for the smaller types
9508 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9509 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9511 // Concatenate the result back
9512 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9515 // Optimize shl/srl/sra with constant shift amount.
9516 if (isSplatVector(Amt.getNode())) {
9517 SDValue SclrAmt = Amt->getOperand(0);
9518 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9519 uint64_t ShiftAmt = C->getZExtValue();
9521 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9522 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9523 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9524 R, DAG.getConstant(ShiftAmt, MVT::i32));
9526 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9527 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9528 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9529 R, DAG.getConstant(ShiftAmt, MVT::i32));
9531 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9532 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9533 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9534 R, DAG.getConstant(ShiftAmt, MVT::i32));
9536 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9537 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9538 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9539 R, DAG.getConstant(ShiftAmt, MVT::i32));
9541 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9542 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9543 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9544 R, DAG.getConstant(ShiftAmt, MVT::i32));
9546 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9547 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9548 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9549 R, DAG.getConstant(ShiftAmt, MVT::i32));
9551 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9552 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9553 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9554 R, DAG.getConstant(ShiftAmt, MVT::i32));
9556 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9557 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9558 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9559 R, DAG.getConstant(ShiftAmt, MVT::i32));
9563 // Lower SHL with variable shift amount.
9564 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9565 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9566 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9567 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9569 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9571 std::vector<Constant*> CV(4, CI);
9572 Constant *C = ConstantVector::get(CV);
9573 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9574 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9575 MachinePointerInfo::getConstantPool(),
9578 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9579 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9580 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9581 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9583 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9585 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9586 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9587 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9589 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9590 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9592 std::vector<Constant*> CVM1(16, CM1);
9593 std::vector<Constant*> CVM2(16, CM2);
9594 Constant *C = ConstantVector::get(CVM1);
9595 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9596 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9597 MachinePointerInfo::getConstantPool(),
9600 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9601 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9602 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9603 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9604 DAG.getConstant(4, MVT::i32));
9605 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9607 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9609 C = ConstantVector::get(CVM2);
9610 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9611 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9612 MachinePointerInfo::getConstantPool(),
9615 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9616 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9617 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9618 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9619 DAG.getConstant(2, MVT::i32));
9620 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9622 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9624 // return pblendv(r, r+r, a);
9625 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9626 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9632 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9633 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9634 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9635 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9636 // has only one use.
9637 SDNode *N = Op.getNode();
9638 SDValue LHS = N->getOperand(0);
9639 SDValue RHS = N->getOperand(1);
9640 unsigned BaseOp = 0;
9642 DebugLoc DL = Op.getDebugLoc();
9643 switch (Op.getOpcode()) {
9644 default: llvm_unreachable("Unknown ovf instruction!");
9646 // A subtract of one will be selected as a INC. Note that INC doesn't
9647 // set CF, so we can't do this for UADDO.
9648 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9650 BaseOp = X86ISD::INC;
9654 BaseOp = X86ISD::ADD;
9658 BaseOp = X86ISD::ADD;
9662 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9663 // set CF, so we can't do this for USUBO.
9664 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9666 BaseOp = X86ISD::DEC;
9670 BaseOp = X86ISD::SUB;
9674 BaseOp = X86ISD::SUB;
9678 BaseOp = X86ISD::SMUL;
9681 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
9682 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
9684 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
9687 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9688 DAG.getConstant(X86::COND_O, MVT::i32),
9689 SDValue(Sum.getNode(), 2));
9691 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9695 // Also sets EFLAGS.
9696 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
9697 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
9700 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9701 DAG.getConstant(Cond, MVT::i32),
9702 SDValue(Sum.getNode(), 1));
9704 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9707 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
9708 DebugLoc dl = Op.getDebugLoc();
9709 SDNode* Node = Op.getNode();
9710 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
9711 EVT VT = Node->getValueType(0);
9713 if (Subtarget->hasSSE2() && VT.isVector()) {
9714 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
9715 ExtraVT.getScalarType().getSizeInBits();
9716 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
9718 unsigned SHLIntrinsicsID = 0;
9719 unsigned SRAIntrinsicsID = 0;
9720 switch (VT.getSimpleVT().SimpleTy) {
9724 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
9725 SRAIntrinsicsID = 0;
9729 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
9730 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
9734 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
9735 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
9740 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9741 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
9742 Node->getOperand(0), ShAmt);
9744 // In case of 1 bit sext, no need to shr
9745 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
9747 if (SRAIntrinsicsID) {
9748 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9749 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
9759 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
9760 DebugLoc dl = Op.getDebugLoc();
9762 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
9763 // There isn't any reason to disable it if the target processor supports it.
9764 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
9765 SDValue Chain = Op.getOperand(0);
9766 SDValue Zero = DAG.getConstant(0, MVT::i32);
9768 DAG.getRegister(X86::ESP, MVT::i32), // Base
9769 DAG.getTargetConstant(1, MVT::i8), // Scale
9770 DAG.getRegister(0, MVT::i32), // Index
9771 DAG.getTargetConstant(0, MVT::i32), // Disp
9772 DAG.getRegister(0, MVT::i32), // Segment.
9777 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9778 array_lengthof(Ops));
9779 return SDValue(Res, 0);
9782 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
9784 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9786 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9787 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
9788 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
9789 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
9791 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
9792 if (!Op1 && !Op2 && !Op3 && Op4)
9793 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
9795 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
9796 if (Op1 && !Op2 && !Op3 && !Op4)
9797 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
9799 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
9801 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9804 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
9805 SelectionDAG &DAG) const {
9806 DebugLoc dl = Op.getDebugLoc();
9807 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
9808 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
9809 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
9810 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
9812 // The only fence that needs an instruction is a sequentially-consistent
9813 // cross-thread fence.
9814 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
9815 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
9816 // no-sse2). There isn't any reason to disable it if the target processor
9818 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
9819 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9821 SDValue Chain = Op.getOperand(0);
9822 SDValue Zero = DAG.getConstant(0, MVT::i32);
9824 DAG.getRegister(X86::ESP, MVT::i32), // Base
9825 DAG.getTargetConstant(1, MVT::i8), // Scale
9826 DAG.getRegister(0, MVT::i32), // Index
9827 DAG.getTargetConstant(0, MVT::i32), // Disp
9828 DAG.getRegister(0, MVT::i32), // Segment.
9833 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9834 array_lengthof(Ops));
9835 return SDValue(Res, 0);
9838 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
9839 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9843 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
9844 EVT T = Op.getValueType();
9845 DebugLoc DL = Op.getDebugLoc();
9848 switch(T.getSimpleVT().SimpleTy) {
9850 assert(false && "Invalid value type!");
9851 case MVT::i8: Reg = X86::AL; size = 1; break;
9852 case MVT::i16: Reg = X86::AX; size = 2; break;
9853 case MVT::i32: Reg = X86::EAX; size = 4; break;
9855 assert(Subtarget->is64Bit() && "Node not type legal!");
9856 Reg = X86::RAX; size = 8;
9859 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
9860 Op.getOperand(2), SDValue());
9861 SDValue Ops[] = { cpIn.getValue(0),
9864 DAG.getTargetConstant(size, MVT::i8),
9866 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9867 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
9868 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
9871 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
9875 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
9876 SelectionDAG &DAG) const {
9877 assert(Subtarget->is64Bit() && "Result not type legalized?");
9878 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9879 SDValue TheChain = Op.getOperand(0);
9880 DebugLoc dl = Op.getDebugLoc();
9881 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9882 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
9883 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
9885 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
9886 DAG.getConstant(32, MVT::i8));
9888 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
9891 return DAG.getMergeValues(Ops, 2, dl);
9894 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
9895 SelectionDAG &DAG) const {
9896 EVT SrcVT = Op.getOperand(0).getValueType();
9897 EVT DstVT = Op.getValueType();
9898 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
9899 Subtarget->hasMMX() && "Unexpected custom BITCAST");
9900 assert((DstVT == MVT::i64 ||
9901 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
9902 "Unexpected custom BITCAST");
9903 // i64 <=> MMX conversions are Legal.
9904 if (SrcVT==MVT::i64 && DstVT.isVector())
9906 if (DstVT==MVT::i64 && SrcVT.isVector())
9908 // MMX <=> MMX conversions are Legal.
9909 if (SrcVT.isVector() && DstVT.isVector())
9911 // All other conversions need to be expanded.
9915 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
9916 SDNode *Node = Op.getNode();
9917 DebugLoc dl = Node->getDebugLoc();
9918 EVT T = Node->getValueType(0);
9919 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
9920 DAG.getConstant(0, T), Node->getOperand(2));
9921 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
9922 cast<AtomicSDNode>(Node)->getMemoryVT(),
9923 Node->getOperand(0),
9924 Node->getOperand(1), negOp,
9925 cast<AtomicSDNode>(Node)->getSrcValue(),
9926 cast<AtomicSDNode>(Node)->getAlignment(),
9927 cast<AtomicSDNode>(Node)->getOrdering(),
9928 cast<AtomicSDNode>(Node)->getSynchScope());
9931 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
9932 EVT VT = Op.getNode()->getValueType(0);
9934 // Let legalize expand this if it isn't a legal type yet.
9935 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
9938 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9941 bool ExtraOp = false;
9942 switch (Op.getOpcode()) {
9943 default: assert(0 && "Invalid code");
9944 case ISD::ADDC: Opc = X86ISD::ADD; break;
9945 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
9946 case ISD::SUBC: Opc = X86ISD::SUB; break;
9947 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
9951 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9953 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9954 Op.getOperand(1), Op.getOperand(2));
9957 /// LowerOperation - Provide custom lowering hooks for some operations.
9959 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
9960 switch (Op.getOpcode()) {
9961 default: llvm_unreachable("Should not custom lower this!");
9962 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
9963 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
9964 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
9965 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
9966 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
9967 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
9968 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
9969 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
9970 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
9971 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
9972 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
9973 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
9974 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
9975 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
9976 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
9977 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
9978 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
9979 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
9980 case ISD::SHL_PARTS:
9981 case ISD::SRA_PARTS:
9982 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
9983 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
9984 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
9985 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
9986 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
9987 case ISD::FABS: return LowerFABS(Op, DAG);
9988 case ISD::FNEG: return LowerFNEG(Op, DAG);
9989 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
9990 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
9991 case ISD::SETCC: return LowerSETCC(Op, DAG);
9992 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
9993 case ISD::SELECT: return LowerSELECT(Op, DAG);
9994 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
9995 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
9996 case ISD::VASTART: return LowerVASTART(Op, DAG);
9997 case ISD::VAARG: return LowerVAARG(Op, DAG);
9998 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
9999 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10000 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10001 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10002 case ISD::FRAME_TO_ARGS_OFFSET:
10003 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10004 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10005 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10006 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
10007 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10008 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10009 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10010 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
10013 case ISD::SHL: return LowerShift(Op, DAG);
10019 case ISD::UMULO: return LowerXALUO(Op, DAG);
10020 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10021 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10025 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10029 void X86TargetLowering::
10030 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10031 SelectionDAG &DAG, unsigned NewOp) const {
10032 EVT T = Node->getValueType(0);
10033 DebugLoc dl = Node->getDebugLoc();
10034 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10036 SDValue Chain = Node->getOperand(0);
10037 SDValue In1 = Node->getOperand(1);
10038 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10039 Node->getOperand(2), DAG.getIntPtrConstant(0));
10040 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10041 Node->getOperand(2), DAG.getIntPtrConstant(1));
10042 SDValue Ops[] = { Chain, In1, In2L, In2H };
10043 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10045 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10046 cast<MemSDNode>(Node)->getMemOperand());
10047 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10048 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10049 Results.push_back(Result.getValue(2));
10052 /// ReplaceNodeResults - Replace a node with an illegal result type
10053 /// with a new node built out of custom code.
10054 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10055 SmallVectorImpl<SDValue>&Results,
10056 SelectionDAG &DAG) const {
10057 DebugLoc dl = N->getDebugLoc();
10058 switch (N->getOpcode()) {
10060 assert(false && "Do not know how to custom type legalize this operation!");
10062 case ISD::SIGN_EXTEND_INREG:
10067 // We don't want to expand or promote these.
10069 case ISD::FP_TO_SINT: {
10070 std::pair<SDValue,SDValue> Vals =
10071 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10072 SDValue FIST = Vals.first, StackSlot = Vals.second;
10073 if (FIST.getNode() != 0) {
10074 EVT VT = N->getValueType(0);
10075 // Return a load from the stack slot.
10076 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10077 MachinePointerInfo(), false, false, 0));
10081 case ISD::READCYCLECOUNTER: {
10082 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10083 SDValue TheChain = N->getOperand(0);
10084 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10085 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10087 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10089 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10090 SDValue Ops[] = { eax, edx };
10091 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10092 Results.push_back(edx.getValue(1));
10095 case ISD::ATOMIC_CMP_SWAP: {
10096 EVT T = N->getValueType(0);
10097 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
10098 SDValue cpInL, cpInH;
10099 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
10100 DAG.getConstant(0, MVT::i32));
10101 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
10102 DAG.getConstant(1, MVT::i32));
10103 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
10104 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
10105 cpInL.getValue(1));
10106 SDValue swapInL, swapInH;
10107 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
10108 DAG.getConstant(0, MVT::i32));
10109 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
10110 DAG.getConstant(1, MVT::i32));
10111 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
10112 cpInH.getValue(1));
10113 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
10114 swapInL.getValue(1));
10115 SDValue Ops[] = { swapInH.getValue(0),
10117 swapInH.getValue(1) };
10118 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10119 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10120 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
10122 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
10123 MVT::i32, Result.getValue(1));
10124 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
10125 MVT::i32, cpOutL.getValue(2));
10126 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10127 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10128 Results.push_back(cpOutH.getValue(1));
10131 case ISD::ATOMIC_LOAD_ADD:
10132 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10134 case ISD::ATOMIC_LOAD_AND:
10135 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10137 case ISD::ATOMIC_LOAD_NAND:
10138 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10140 case ISD::ATOMIC_LOAD_OR:
10141 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10143 case ISD::ATOMIC_LOAD_SUB:
10144 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10146 case ISD::ATOMIC_LOAD_XOR:
10147 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10149 case ISD::ATOMIC_SWAP:
10150 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10155 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10157 default: return NULL;
10158 case X86ISD::BSF: return "X86ISD::BSF";
10159 case X86ISD::BSR: return "X86ISD::BSR";
10160 case X86ISD::SHLD: return "X86ISD::SHLD";
10161 case X86ISD::SHRD: return "X86ISD::SHRD";
10162 case X86ISD::FAND: return "X86ISD::FAND";
10163 case X86ISD::FOR: return "X86ISD::FOR";
10164 case X86ISD::FXOR: return "X86ISD::FXOR";
10165 case X86ISD::FSRL: return "X86ISD::FSRL";
10166 case X86ISD::FILD: return "X86ISD::FILD";
10167 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10168 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10169 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10170 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10171 case X86ISD::FLD: return "X86ISD::FLD";
10172 case X86ISD::FST: return "X86ISD::FST";
10173 case X86ISD::CALL: return "X86ISD::CALL";
10174 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10175 case X86ISD::BT: return "X86ISD::BT";
10176 case X86ISD::CMP: return "X86ISD::CMP";
10177 case X86ISD::COMI: return "X86ISD::COMI";
10178 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10179 case X86ISD::SETCC: return "X86ISD::SETCC";
10180 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10181 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10182 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10183 case X86ISD::CMOV: return "X86ISD::CMOV";
10184 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10185 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10186 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10187 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10188 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10189 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10190 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10191 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10192 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10193 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10194 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10195 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10196 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10197 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10198 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10199 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10200 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10201 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
10202 case X86ISD::FMAX: return "X86ISD::FMAX";
10203 case X86ISD::FMIN: return "X86ISD::FMIN";
10204 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10205 case X86ISD::FRCP: return "X86ISD::FRCP";
10206 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10207 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10208 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10209 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10210 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10211 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10212 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10213 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10214 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10215 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10216 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10217 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10218 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10219 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10220 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10221 case X86ISD::VSHL: return "X86ISD::VSHL";
10222 case X86ISD::VSRL: return "X86ISD::VSRL";
10223 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10224 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10225 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10226 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10227 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10228 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10229 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10230 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10231 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10232 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10233 case X86ISD::ADD: return "X86ISD::ADD";
10234 case X86ISD::SUB: return "X86ISD::SUB";
10235 case X86ISD::ADC: return "X86ISD::ADC";
10236 case X86ISD::SBB: return "X86ISD::SBB";
10237 case X86ISD::SMUL: return "X86ISD::SMUL";
10238 case X86ISD::UMUL: return "X86ISD::UMUL";
10239 case X86ISD::INC: return "X86ISD::INC";
10240 case X86ISD::DEC: return "X86ISD::DEC";
10241 case X86ISD::OR: return "X86ISD::OR";
10242 case X86ISD::XOR: return "X86ISD::XOR";
10243 case X86ISD::AND: return "X86ISD::AND";
10244 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10245 case X86ISD::PTEST: return "X86ISD::PTEST";
10246 case X86ISD::TESTP: return "X86ISD::TESTP";
10247 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10248 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10249 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10250 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10251 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10252 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10253 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10254 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10255 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10256 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10257 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10258 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10259 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10260 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10261 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10262 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10263 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10264 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10265 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10266 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10267 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10268 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10269 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10270 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10271 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10272 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10273 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10274 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10275 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10276 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10277 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10278 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10279 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10280 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10281 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10282 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10283 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10284 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10285 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10286 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10287 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10288 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10289 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10290 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10294 // isLegalAddressingMode - Return true if the addressing mode represented
10295 // by AM is legal for this target, for a load/store of the specified type.
10296 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10298 // X86 supports extremely general addressing modes.
10299 CodeModel::Model M = getTargetMachine().getCodeModel();
10300 Reloc::Model R = getTargetMachine().getRelocationModel();
10302 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10303 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10308 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10310 // If a reference to this global requires an extra load, we can't fold it.
10311 if (isGlobalStubReference(GVFlags))
10314 // If BaseGV requires a register for the PIC base, we cannot also have a
10315 // BaseReg specified.
10316 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10319 // If lower 4G is not available, then we must use rip-relative addressing.
10320 if ((M != CodeModel::Small || R != Reloc::Static) &&
10321 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10325 switch (AM.Scale) {
10331 // These scales always work.
10336 // These scales are formed with basereg+scalereg. Only accept if there is
10341 default: // Other stuff never works.
10349 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10350 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10352 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10353 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10354 if (NumBits1 <= NumBits2)
10359 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10360 if (!VT1.isInteger() || !VT2.isInteger())
10362 unsigned NumBits1 = VT1.getSizeInBits();
10363 unsigned NumBits2 = VT2.getSizeInBits();
10364 if (NumBits1 <= NumBits2)
10369 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10370 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10371 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10374 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10375 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10376 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10379 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10380 // i16 instructions are longer (0x66 prefix) and potentially slower.
10381 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10384 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10385 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10386 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10387 /// are assumed to be legal.
10389 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10391 // Very little shuffling can be done for 64-bit vectors right now.
10392 if (VT.getSizeInBits() == 64)
10393 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10395 // FIXME: pshufb, blends, shifts.
10396 return (VT.getVectorNumElements() == 2 ||
10397 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10398 isMOVLMask(M, VT) ||
10399 isSHUFPMask(M, VT) ||
10400 isPSHUFDMask(M, VT) ||
10401 isPSHUFHWMask(M, VT) ||
10402 isPSHUFLWMask(M, VT) ||
10403 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10404 isUNPCKLMask(M, VT) ||
10405 isUNPCKHMask(M, VT) ||
10406 isUNPCKL_v_undef_Mask(M, VT) ||
10407 isUNPCKH_v_undef_Mask(M, VT));
10411 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10413 unsigned NumElts = VT.getVectorNumElements();
10414 // FIXME: This collection of masks seems suspect.
10417 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10418 return (isMOVLMask(Mask, VT) ||
10419 isCommutedMOVLMask(Mask, VT, true) ||
10420 isSHUFPMask(Mask, VT) ||
10421 isCommutedSHUFPMask(Mask, VT));
10426 //===----------------------------------------------------------------------===//
10427 // X86 Scheduler Hooks
10428 //===----------------------------------------------------------------------===//
10430 // private utility function
10431 MachineBasicBlock *
10432 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10433 MachineBasicBlock *MBB,
10440 TargetRegisterClass *RC,
10441 bool invSrc) const {
10442 // For the atomic bitwise operator, we generate
10445 // ld t1 = [bitinstr.addr]
10446 // op t2 = t1, [bitinstr.val]
10448 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10450 // fallthrough -->nextMBB
10451 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10452 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10453 MachineFunction::iterator MBBIter = MBB;
10456 /// First build the CFG
10457 MachineFunction *F = MBB->getParent();
10458 MachineBasicBlock *thisMBB = MBB;
10459 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10460 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10461 F->insert(MBBIter, newMBB);
10462 F->insert(MBBIter, nextMBB);
10464 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10465 nextMBB->splice(nextMBB->begin(), thisMBB,
10466 llvm::next(MachineBasicBlock::iterator(bInstr)),
10468 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10470 // Update thisMBB to fall through to newMBB
10471 thisMBB->addSuccessor(newMBB);
10473 // newMBB jumps to itself and fall through to nextMBB
10474 newMBB->addSuccessor(nextMBB);
10475 newMBB->addSuccessor(newMBB);
10477 // Insert instructions into newMBB based on incoming instruction
10478 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10479 "unexpected number of operands");
10480 DebugLoc dl = bInstr->getDebugLoc();
10481 MachineOperand& destOper = bInstr->getOperand(0);
10482 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10483 int numArgs = bInstr->getNumOperands() - 1;
10484 for (int i=0; i < numArgs; ++i)
10485 argOpers[i] = &bInstr->getOperand(i+1);
10487 // x86 address has 4 operands: base, index, scale, and displacement
10488 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10489 int valArgIndx = lastAddrIndx + 1;
10491 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10492 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10493 for (int i=0; i <= lastAddrIndx; ++i)
10494 (*MIB).addOperand(*argOpers[i]);
10496 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10498 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10503 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10504 assert((argOpers[valArgIndx]->isReg() ||
10505 argOpers[valArgIndx]->isImm()) &&
10506 "invalid operand");
10507 if (argOpers[valArgIndx]->isReg())
10508 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10510 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10512 (*MIB).addOperand(*argOpers[valArgIndx]);
10514 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10517 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10518 for (int i=0; i <= lastAddrIndx; ++i)
10519 (*MIB).addOperand(*argOpers[i]);
10521 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10522 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10523 bInstr->memoperands_end());
10525 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10526 MIB.addReg(EAXreg);
10529 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10531 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10535 // private utility function: 64 bit atomics on 32 bit host.
10536 MachineBasicBlock *
10537 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10538 MachineBasicBlock *MBB,
10543 bool invSrc) const {
10544 // For the atomic bitwise operator, we generate
10545 // thisMBB (instructions are in pairs, except cmpxchg8b)
10546 // ld t1,t2 = [bitinstr.addr]
10548 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10549 // op t5, t6 <- out1, out2, [bitinstr.val]
10550 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10551 // mov ECX, EBX <- t5, t6
10552 // mov EAX, EDX <- t1, t2
10553 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10554 // mov t3, t4 <- EAX, EDX
10556 // result in out1, out2
10557 // fallthrough -->nextMBB
10559 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10560 const unsigned LoadOpc = X86::MOV32rm;
10561 const unsigned NotOpc = X86::NOT32r;
10562 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10563 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10564 MachineFunction::iterator MBBIter = MBB;
10567 /// First build the CFG
10568 MachineFunction *F = MBB->getParent();
10569 MachineBasicBlock *thisMBB = MBB;
10570 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10571 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10572 F->insert(MBBIter, newMBB);
10573 F->insert(MBBIter, nextMBB);
10575 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10576 nextMBB->splice(nextMBB->begin(), thisMBB,
10577 llvm::next(MachineBasicBlock::iterator(bInstr)),
10579 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10581 // Update thisMBB to fall through to newMBB
10582 thisMBB->addSuccessor(newMBB);
10584 // newMBB jumps to itself and fall through to nextMBB
10585 newMBB->addSuccessor(nextMBB);
10586 newMBB->addSuccessor(newMBB);
10588 DebugLoc dl = bInstr->getDebugLoc();
10589 // Insert instructions into newMBB based on incoming instruction
10590 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10591 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10592 "unexpected number of operands");
10593 MachineOperand& dest1Oper = bInstr->getOperand(0);
10594 MachineOperand& dest2Oper = bInstr->getOperand(1);
10595 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10596 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10597 argOpers[i] = &bInstr->getOperand(i+2);
10599 // We use some of the operands multiple times, so conservatively just
10600 // clear any kill flags that might be present.
10601 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10602 argOpers[i]->setIsKill(false);
10605 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10606 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10608 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10609 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
10610 for (int i=0; i <= lastAddrIndx; ++i)
10611 (*MIB).addOperand(*argOpers[i]);
10612 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10613 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
10614 // add 4 to displacement.
10615 for (int i=0; i <= lastAddrIndx-2; ++i)
10616 (*MIB).addOperand(*argOpers[i]);
10617 MachineOperand newOp3 = *(argOpers[3]);
10618 if (newOp3.isImm())
10619 newOp3.setImm(newOp3.getImm()+4);
10621 newOp3.setOffset(newOp3.getOffset()+4);
10622 (*MIB).addOperand(newOp3);
10623 (*MIB).addOperand(*argOpers[lastAddrIndx]);
10625 // t3/4 are defined later, at the bottom of the loop
10626 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
10627 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
10628 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
10629 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
10630 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
10631 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
10633 // The subsequent operations should be using the destination registers of
10634 //the PHI instructions.
10636 t1 = F->getRegInfo().createVirtualRegister(RC);
10637 t2 = F->getRegInfo().createVirtualRegister(RC);
10638 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
10639 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
10641 t1 = dest1Oper.getReg();
10642 t2 = dest2Oper.getReg();
10645 int valArgIndx = lastAddrIndx + 1;
10646 assert((argOpers[valArgIndx]->isReg() ||
10647 argOpers[valArgIndx]->isImm()) &&
10648 "invalid operand");
10649 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
10650 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
10651 if (argOpers[valArgIndx]->isReg())
10652 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
10654 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
10655 if (regOpcL != X86::MOV32rr)
10657 (*MIB).addOperand(*argOpers[valArgIndx]);
10658 assert(argOpers[valArgIndx + 1]->isReg() ==
10659 argOpers[valArgIndx]->isReg());
10660 assert(argOpers[valArgIndx + 1]->isImm() ==
10661 argOpers[valArgIndx]->isImm());
10662 if (argOpers[valArgIndx + 1]->isReg())
10663 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
10665 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
10666 if (regOpcH != X86::MOV32rr)
10668 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
10670 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10672 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
10675 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
10677 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
10680 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
10681 for (int i=0; i <= lastAddrIndx; ++i)
10682 (*MIB).addOperand(*argOpers[i]);
10684 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10685 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10686 bInstr->memoperands_end());
10688 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
10689 MIB.addReg(X86::EAX);
10690 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
10691 MIB.addReg(X86::EDX);
10694 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10696 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10700 // private utility function
10701 MachineBasicBlock *
10702 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
10703 MachineBasicBlock *MBB,
10704 unsigned cmovOpc) const {
10705 // For the atomic min/max operator, we generate
10708 // ld t1 = [min/max.addr]
10709 // mov t2 = [min/max.val]
10711 // cmov[cond] t2 = t1
10713 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10715 // fallthrough -->nextMBB
10717 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10718 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10719 MachineFunction::iterator MBBIter = MBB;
10722 /// First build the CFG
10723 MachineFunction *F = MBB->getParent();
10724 MachineBasicBlock *thisMBB = MBB;
10725 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10726 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10727 F->insert(MBBIter, newMBB);
10728 F->insert(MBBIter, nextMBB);
10730 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10731 nextMBB->splice(nextMBB->begin(), thisMBB,
10732 llvm::next(MachineBasicBlock::iterator(mInstr)),
10734 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10736 // Update thisMBB to fall through to newMBB
10737 thisMBB->addSuccessor(newMBB);
10739 // newMBB jumps to newMBB and fall through to nextMBB
10740 newMBB->addSuccessor(nextMBB);
10741 newMBB->addSuccessor(newMBB);
10743 DebugLoc dl = mInstr->getDebugLoc();
10744 // Insert instructions into newMBB based on incoming instruction
10745 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10746 "unexpected number of operands");
10747 MachineOperand& destOper = mInstr->getOperand(0);
10748 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10749 int numArgs = mInstr->getNumOperands() - 1;
10750 for (int i=0; i < numArgs; ++i)
10751 argOpers[i] = &mInstr->getOperand(i+1);
10753 // x86 address has 4 operands: base, index, scale, and displacement
10754 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10755 int valArgIndx = lastAddrIndx + 1;
10757 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10758 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
10759 for (int i=0; i <= lastAddrIndx; ++i)
10760 (*MIB).addOperand(*argOpers[i]);
10762 // We only support register and immediate values
10763 assert((argOpers[valArgIndx]->isReg() ||
10764 argOpers[valArgIndx]->isImm()) &&
10765 "invalid operand");
10767 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10768 if (argOpers[valArgIndx]->isReg())
10769 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
10771 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
10772 (*MIB).addOperand(*argOpers[valArgIndx]);
10774 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10777 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
10782 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10783 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
10787 // Cmp and exchange if none has modified the memory location
10788 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
10789 for (int i=0; i <= lastAddrIndx; ++i)
10790 (*MIB).addOperand(*argOpers[i]);
10792 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10793 (*MIB).setMemRefs(mInstr->memoperands_begin(),
10794 mInstr->memoperands_end());
10796 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10797 MIB.addReg(X86::EAX);
10800 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10802 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
10806 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
10807 // or XMM0_V32I8 in AVX all of this code can be replaced with that
10808 // in the .td file.
10809 MachineBasicBlock *
10810 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
10811 unsigned numArgs, bool memArg) const {
10812 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
10813 "Target must have SSE4.2 or AVX features enabled");
10815 DebugLoc dl = MI->getDebugLoc();
10816 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10818 if (!Subtarget->hasAVX()) {
10820 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
10822 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
10825 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
10827 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
10830 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
10831 for (unsigned i = 0; i < numArgs; ++i) {
10832 MachineOperand &Op = MI->getOperand(i+1);
10833 if (!(Op.isReg() && Op.isImplicit()))
10834 MIB.addOperand(Op);
10836 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
10837 .addReg(X86::XMM0);
10839 MI->eraseFromParent();
10843 MachineBasicBlock *
10844 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
10845 DebugLoc dl = MI->getDebugLoc();
10846 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10848 // Address into RAX/EAX, other two args into ECX, EDX.
10849 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
10850 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10851 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
10852 for (int i = 0; i < X86::AddrNumOperands; ++i)
10853 MIB.addOperand(MI->getOperand(i));
10855 unsigned ValOps = X86::AddrNumOperands;
10856 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10857 .addReg(MI->getOperand(ValOps).getReg());
10858 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
10859 .addReg(MI->getOperand(ValOps+1).getReg());
10861 // The instruction doesn't actually take any operands though.
10862 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
10864 MI->eraseFromParent(); // The pseudo is gone now.
10868 MachineBasicBlock *
10869 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
10870 DebugLoc dl = MI->getDebugLoc();
10871 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10873 // First arg in ECX, the second in EAX.
10874 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10875 .addReg(MI->getOperand(0).getReg());
10876 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
10877 .addReg(MI->getOperand(1).getReg());
10879 // The instruction doesn't actually take any operands though.
10880 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
10882 MI->eraseFromParent(); // The pseudo is gone now.
10886 MachineBasicBlock *
10887 X86TargetLowering::EmitVAARG64WithCustomInserter(
10889 MachineBasicBlock *MBB) const {
10890 // Emit va_arg instruction on X86-64.
10892 // Operands to this pseudo-instruction:
10893 // 0 ) Output : destination address (reg)
10894 // 1-5) Input : va_list address (addr, i64mem)
10895 // 6 ) ArgSize : Size (in bytes) of vararg type
10896 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
10897 // 8 ) Align : Alignment of type
10898 // 9 ) EFLAGS (implicit-def)
10900 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
10901 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
10903 unsigned DestReg = MI->getOperand(0).getReg();
10904 MachineOperand &Base = MI->getOperand(1);
10905 MachineOperand &Scale = MI->getOperand(2);
10906 MachineOperand &Index = MI->getOperand(3);
10907 MachineOperand &Disp = MI->getOperand(4);
10908 MachineOperand &Segment = MI->getOperand(5);
10909 unsigned ArgSize = MI->getOperand(6).getImm();
10910 unsigned ArgMode = MI->getOperand(7).getImm();
10911 unsigned Align = MI->getOperand(8).getImm();
10913 // Memory Reference
10914 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
10915 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
10916 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
10918 // Machine Information
10919 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10920 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
10921 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
10922 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
10923 DebugLoc DL = MI->getDebugLoc();
10925 // struct va_list {
10928 // i64 overflow_area (address)
10929 // i64 reg_save_area (address)
10931 // sizeof(va_list) = 24
10932 // alignment(va_list) = 8
10934 unsigned TotalNumIntRegs = 6;
10935 unsigned TotalNumXMMRegs = 8;
10936 bool UseGPOffset = (ArgMode == 1);
10937 bool UseFPOffset = (ArgMode == 2);
10938 unsigned MaxOffset = TotalNumIntRegs * 8 +
10939 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
10941 /* Align ArgSize to a multiple of 8 */
10942 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
10943 bool NeedsAlign = (Align > 8);
10945 MachineBasicBlock *thisMBB = MBB;
10946 MachineBasicBlock *overflowMBB;
10947 MachineBasicBlock *offsetMBB;
10948 MachineBasicBlock *endMBB;
10950 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
10951 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
10952 unsigned OffsetReg = 0;
10954 if (!UseGPOffset && !UseFPOffset) {
10955 // If we only pull from the overflow region, we don't create a branch.
10956 // We don't need to alter control flow.
10957 OffsetDestReg = 0; // unused
10958 OverflowDestReg = DestReg;
10961 overflowMBB = thisMBB;
10964 // First emit code to check if gp_offset (or fp_offset) is below the bound.
10965 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
10966 // If not, pull from overflow_area. (branch to overflowMBB)
10971 // offsetMBB overflowMBB
10976 // Registers for the PHI in endMBB
10977 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
10978 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
10980 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10981 MachineFunction *MF = MBB->getParent();
10982 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10983 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10984 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10986 MachineFunction::iterator MBBIter = MBB;
10989 // Insert the new basic blocks
10990 MF->insert(MBBIter, offsetMBB);
10991 MF->insert(MBBIter, overflowMBB);
10992 MF->insert(MBBIter, endMBB);
10994 // Transfer the remainder of MBB and its successor edges to endMBB.
10995 endMBB->splice(endMBB->begin(), thisMBB,
10996 llvm::next(MachineBasicBlock::iterator(MI)),
10998 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11000 // Make offsetMBB and overflowMBB successors of thisMBB
11001 thisMBB->addSuccessor(offsetMBB);
11002 thisMBB->addSuccessor(overflowMBB);
11004 // endMBB is a successor of both offsetMBB and overflowMBB
11005 offsetMBB->addSuccessor(endMBB);
11006 overflowMBB->addSuccessor(endMBB);
11008 // Load the offset value into a register
11009 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11010 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11014 .addDisp(Disp, UseFPOffset ? 4 : 0)
11015 .addOperand(Segment)
11016 .setMemRefs(MMOBegin, MMOEnd);
11018 // Check if there is enough room left to pull this argument.
11019 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11021 .addImm(MaxOffset + 8 - ArgSizeA8);
11023 // Branch to "overflowMBB" if offset >= max
11024 // Fall through to "offsetMBB" otherwise
11025 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11026 .addMBB(overflowMBB);
11029 // In offsetMBB, emit code to use the reg_save_area.
11031 assert(OffsetReg != 0);
11033 // Read the reg_save_area address.
11034 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11035 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11040 .addOperand(Segment)
11041 .setMemRefs(MMOBegin, MMOEnd);
11043 // Zero-extend the offset
11044 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11045 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11048 .addImm(X86::sub_32bit);
11050 // Add the offset to the reg_save_area to get the final address.
11051 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11052 .addReg(OffsetReg64)
11053 .addReg(RegSaveReg);
11055 // Compute the offset for the next argument
11056 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11057 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11059 .addImm(UseFPOffset ? 16 : 8);
11061 // Store it back into the va_list.
11062 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11066 .addDisp(Disp, UseFPOffset ? 4 : 0)
11067 .addOperand(Segment)
11068 .addReg(NextOffsetReg)
11069 .setMemRefs(MMOBegin, MMOEnd);
11072 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11077 // Emit code to use overflow area
11080 // Load the overflow_area address into a register.
11081 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11082 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11087 .addOperand(Segment)
11088 .setMemRefs(MMOBegin, MMOEnd);
11090 // If we need to align it, do so. Otherwise, just copy the address
11091 // to OverflowDestReg.
11093 // Align the overflow address
11094 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11095 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11097 // aligned_addr = (addr + (align-1)) & ~(align-1)
11098 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11099 .addReg(OverflowAddrReg)
11102 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11104 .addImm(~(uint64_t)(Align-1));
11106 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11107 .addReg(OverflowAddrReg);
11110 // Compute the next overflow address after this argument.
11111 // (the overflow address should be kept 8-byte aligned)
11112 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11113 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11114 .addReg(OverflowDestReg)
11115 .addImm(ArgSizeA8);
11117 // Store the new overflow address.
11118 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11123 .addOperand(Segment)
11124 .addReg(NextAddrReg)
11125 .setMemRefs(MMOBegin, MMOEnd);
11127 // If we branched, emit the PHI to the front of endMBB.
11129 BuildMI(*endMBB, endMBB->begin(), DL,
11130 TII->get(X86::PHI), DestReg)
11131 .addReg(OffsetDestReg).addMBB(offsetMBB)
11132 .addReg(OverflowDestReg).addMBB(overflowMBB);
11135 // Erase the pseudo instruction
11136 MI->eraseFromParent();
11141 MachineBasicBlock *
11142 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11144 MachineBasicBlock *MBB) const {
11145 // Emit code to save XMM registers to the stack. The ABI says that the
11146 // number of registers to save is given in %al, so it's theoretically
11147 // possible to do an indirect jump trick to avoid saving all of them,
11148 // however this code takes a simpler approach and just executes all
11149 // of the stores if %al is non-zero. It's less code, and it's probably
11150 // easier on the hardware branch predictor, and stores aren't all that
11151 // expensive anyway.
11153 // Create the new basic blocks. One block contains all the XMM stores,
11154 // and one block is the final destination regardless of whether any
11155 // stores were performed.
11156 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11157 MachineFunction *F = MBB->getParent();
11158 MachineFunction::iterator MBBIter = MBB;
11160 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11161 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11162 F->insert(MBBIter, XMMSaveMBB);
11163 F->insert(MBBIter, EndMBB);
11165 // Transfer the remainder of MBB and its successor edges to EndMBB.
11166 EndMBB->splice(EndMBB->begin(), MBB,
11167 llvm::next(MachineBasicBlock::iterator(MI)),
11169 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11171 // The original block will now fall through to the XMM save block.
11172 MBB->addSuccessor(XMMSaveMBB);
11173 // The XMMSaveMBB will fall through to the end block.
11174 XMMSaveMBB->addSuccessor(EndMBB);
11176 // Now add the instructions.
11177 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11178 DebugLoc DL = MI->getDebugLoc();
11180 unsigned CountReg = MI->getOperand(0).getReg();
11181 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11182 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11184 if (!Subtarget->isTargetWin64()) {
11185 // If %al is 0, branch around the XMM save block.
11186 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11187 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11188 MBB->addSuccessor(EndMBB);
11191 // In the XMM save block, save all the XMM argument registers.
11192 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11193 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11194 MachineMemOperand *MMO =
11195 F->getMachineMemOperand(
11196 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11197 MachineMemOperand::MOStore,
11198 /*Size=*/16, /*Align=*/16);
11199 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
11200 .addFrameIndex(RegSaveFrameIndex)
11201 .addImm(/*Scale=*/1)
11202 .addReg(/*IndexReg=*/0)
11203 .addImm(/*Disp=*/Offset)
11204 .addReg(/*Segment=*/0)
11205 .addReg(MI->getOperand(i).getReg())
11206 .addMemOperand(MMO);
11209 MI->eraseFromParent(); // The pseudo instruction is gone now.
11214 MachineBasicBlock *
11215 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11216 MachineBasicBlock *BB) const {
11217 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11218 DebugLoc DL = MI->getDebugLoc();
11220 // To "insert" a SELECT_CC instruction, we actually have to insert the
11221 // diamond control-flow pattern. The incoming instruction knows the
11222 // destination vreg to set, the condition code register to branch on, the
11223 // true/false values to select between, and a branch opcode to use.
11224 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11225 MachineFunction::iterator It = BB;
11231 // cmpTY ccX, r1, r2
11233 // fallthrough --> copy0MBB
11234 MachineBasicBlock *thisMBB = BB;
11235 MachineFunction *F = BB->getParent();
11236 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11237 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11238 F->insert(It, copy0MBB);
11239 F->insert(It, sinkMBB);
11241 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11242 // live into the sink and copy blocks.
11243 const MachineFunction *MF = BB->getParent();
11244 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
11245 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
11247 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
11248 const MachineOperand &MO = MI->getOperand(I);
11249 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
11250 unsigned Reg = MO.getReg();
11251 if (Reg != X86::EFLAGS) continue;
11252 copy0MBB->addLiveIn(Reg);
11253 sinkMBB->addLiveIn(Reg);
11256 // Transfer the remainder of BB and its successor edges to sinkMBB.
11257 sinkMBB->splice(sinkMBB->begin(), BB,
11258 llvm::next(MachineBasicBlock::iterator(MI)),
11260 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11262 // Add the true and fallthrough blocks as its successors.
11263 BB->addSuccessor(copy0MBB);
11264 BB->addSuccessor(sinkMBB);
11266 // Create the conditional branch instruction.
11268 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11269 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11272 // %FalseValue = ...
11273 // # fallthrough to sinkMBB
11274 copy0MBB->addSuccessor(sinkMBB);
11277 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11279 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11280 TII->get(X86::PHI), MI->getOperand(0).getReg())
11281 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11282 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11284 MI->eraseFromParent(); // The pseudo instruction is gone now.
11288 MachineBasicBlock *
11289 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11290 MachineBasicBlock *BB) const {
11291 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11292 DebugLoc DL = MI->getDebugLoc();
11294 assert(!Subtarget->isTargetEnvMacho());
11296 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11297 // non-trivial part is impdef of ESP.
11299 if (Subtarget->isTargetWin64()) {
11300 if (Subtarget->isTargetCygMing()) {
11301 // ___chkstk(Mingw64):
11302 // Clobbers R10, R11, RAX and EFLAGS.
11304 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11305 .addExternalSymbol("___chkstk")
11306 .addReg(X86::RAX, RegState::Implicit)
11307 .addReg(X86::RSP, RegState::Implicit)
11308 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11309 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11310 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11312 // __chkstk(MSVCRT): does not update stack pointer.
11313 // Clobbers R10, R11 and EFLAGS.
11314 // FIXME: RAX(allocated size) might be reused and not killed.
11315 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11316 .addExternalSymbol("__chkstk")
11317 .addReg(X86::RAX, RegState::Implicit)
11318 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11319 // RAX has the offset to subtracted from RSP.
11320 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11325 const char *StackProbeSymbol =
11326 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11328 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11329 .addExternalSymbol(StackProbeSymbol)
11330 .addReg(X86::EAX, RegState::Implicit)
11331 .addReg(X86::ESP, RegState::Implicit)
11332 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11333 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11334 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11337 MI->eraseFromParent(); // The pseudo instruction is gone now.
11341 MachineBasicBlock *
11342 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11343 MachineBasicBlock *BB) const {
11344 // This is pretty easy. We're taking the value that we received from
11345 // our load from the relocation, sticking it in either RDI (x86-64)
11346 // or EAX and doing an indirect call. The return value will then
11347 // be in the normal return register.
11348 const X86InstrInfo *TII
11349 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11350 DebugLoc DL = MI->getDebugLoc();
11351 MachineFunction *F = BB->getParent();
11353 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11354 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11356 if (Subtarget->is64Bit()) {
11357 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11358 TII->get(X86::MOV64rm), X86::RDI)
11360 .addImm(0).addReg(0)
11361 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11362 MI->getOperand(3).getTargetFlags())
11364 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11365 addDirectMem(MIB, X86::RDI);
11366 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11367 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11368 TII->get(X86::MOV32rm), X86::EAX)
11370 .addImm(0).addReg(0)
11371 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11372 MI->getOperand(3).getTargetFlags())
11374 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11375 addDirectMem(MIB, X86::EAX);
11377 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11378 TII->get(X86::MOV32rm), X86::EAX)
11379 .addReg(TII->getGlobalBaseReg(F))
11380 .addImm(0).addReg(0)
11381 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11382 MI->getOperand(3).getTargetFlags())
11384 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11385 addDirectMem(MIB, X86::EAX);
11388 MI->eraseFromParent(); // The pseudo instruction is gone now.
11392 MachineBasicBlock *
11393 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11394 MachineBasicBlock *BB) const {
11395 switch (MI->getOpcode()) {
11396 default: assert(false && "Unexpected instr type to insert");
11397 case X86::TAILJMPd64:
11398 case X86::TAILJMPr64:
11399 case X86::TAILJMPm64:
11400 assert(!"TAILJMP64 would not be touched here.");
11401 case X86::TCRETURNdi64:
11402 case X86::TCRETURNri64:
11403 case X86::TCRETURNmi64:
11404 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11405 // On AMD64, additional defs should be added before register allocation.
11406 if (!Subtarget->isTargetWin64()) {
11407 MI->addRegisterDefined(X86::RSI);
11408 MI->addRegisterDefined(X86::RDI);
11409 MI->addRegisterDefined(X86::XMM6);
11410 MI->addRegisterDefined(X86::XMM7);
11411 MI->addRegisterDefined(X86::XMM8);
11412 MI->addRegisterDefined(X86::XMM9);
11413 MI->addRegisterDefined(X86::XMM10);
11414 MI->addRegisterDefined(X86::XMM11);
11415 MI->addRegisterDefined(X86::XMM12);
11416 MI->addRegisterDefined(X86::XMM13);
11417 MI->addRegisterDefined(X86::XMM14);
11418 MI->addRegisterDefined(X86::XMM15);
11421 case X86::WIN_ALLOCA:
11422 return EmitLoweredWinAlloca(MI, BB);
11423 case X86::TLSCall_32:
11424 case X86::TLSCall_64:
11425 return EmitLoweredTLSCall(MI, BB);
11426 case X86::CMOV_GR8:
11427 case X86::CMOV_FR32:
11428 case X86::CMOV_FR64:
11429 case X86::CMOV_V4F32:
11430 case X86::CMOV_V2F64:
11431 case X86::CMOV_V2I64:
11432 case X86::CMOV_V8F32:
11433 case X86::CMOV_V4F64:
11434 case X86::CMOV_V4I64:
11435 case X86::CMOV_GR16:
11436 case X86::CMOV_GR32:
11437 case X86::CMOV_RFP32:
11438 case X86::CMOV_RFP64:
11439 case X86::CMOV_RFP80:
11440 return EmitLoweredSelect(MI, BB);
11442 case X86::FP32_TO_INT16_IN_MEM:
11443 case X86::FP32_TO_INT32_IN_MEM:
11444 case X86::FP32_TO_INT64_IN_MEM:
11445 case X86::FP64_TO_INT16_IN_MEM:
11446 case X86::FP64_TO_INT32_IN_MEM:
11447 case X86::FP64_TO_INT64_IN_MEM:
11448 case X86::FP80_TO_INT16_IN_MEM:
11449 case X86::FP80_TO_INT32_IN_MEM:
11450 case X86::FP80_TO_INT64_IN_MEM: {
11451 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11452 DebugLoc DL = MI->getDebugLoc();
11454 // Change the floating point control register to use "round towards zero"
11455 // mode when truncating to an integer value.
11456 MachineFunction *F = BB->getParent();
11457 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11458 addFrameReference(BuildMI(*BB, MI, DL,
11459 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11461 // Load the old value of the high byte of the control word...
11463 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11464 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11467 // Set the high part to be round to zero...
11468 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11471 // Reload the modified control word now...
11472 addFrameReference(BuildMI(*BB, MI, DL,
11473 TII->get(X86::FLDCW16m)), CWFrameIdx);
11475 // Restore the memory image of control word to original value
11476 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11479 // Get the X86 opcode to use.
11481 switch (MI->getOpcode()) {
11482 default: llvm_unreachable("illegal opcode!");
11483 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11484 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11485 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11486 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11487 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11488 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11489 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
11490 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
11491 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
11495 MachineOperand &Op = MI->getOperand(0);
11497 AM.BaseType = X86AddressMode::RegBase;
11498 AM.Base.Reg = Op.getReg();
11500 AM.BaseType = X86AddressMode::FrameIndexBase;
11501 AM.Base.FrameIndex = Op.getIndex();
11503 Op = MI->getOperand(1);
11505 AM.Scale = Op.getImm();
11506 Op = MI->getOperand(2);
11508 AM.IndexReg = Op.getImm();
11509 Op = MI->getOperand(3);
11510 if (Op.isGlobal()) {
11511 AM.GV = Op.getGlobal();
11513 AM.Disp = Op.getImm();
11515 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
11516 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
11518 // Reload the original control word now.
11519 addFrameReference(BuildMI(*BB, MI, DL,
11520 TII->get(X86::FLDCW16m)), CWFrameIdx);
11522 MI->eraseFromParent(); // The pseudo instruction is gone now.
11525 // String/text processing lowering.
11526 case X86::PCMPISTRM128REG:
11527 case X86::VPCMPISTRM128REG:
11528 return EmitPCMP(MI, BB, 3, false /* in-mem */);
11529 case X86::PCMPISTRM128MEM:
11530 case X86::VPCMPISTRM128MEM:
11531 return EmitPCMP(MI, BB, 3, true /* in-mem */);
11532 case X86::PCMPESTRM128REG:
11533 case X86::VPCMPESTRM128REG:
11534 return EmitPCMP(MI, BB, 5, false /* in mem */);
11535 case X86::PCMPESTRM128MEM:
11536 case X86::VPCMPESTRM128MEM:
11537 return EmitPCMP(MI, BB, 5, true /* in mem */);
11539 // Thread synchronization.
11541 return EmitMonitor(MI, BB);
11543 return EmitMwait(MI, BB);
11545 // Atomic Lowering.
11546 case X86::ATOMAND32:
11547 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11548 X86::AND32ri, X86::MOV32rm,
11550 X86::NOT32r, X86::EAX,
11551 X86::GR32RegisterClass);
11552 case X86::ATOMOR32:
11553 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
11554 X86::OR32ri, X86::MOV32rm,
11556 X86::NOT32r, X86::EAX,
11557 X86::GR32RegisterClass);
11558 case X86::ATOMXOR32:
11559 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
11560 X86::XOR32ri, X86::MOV32rm,
11562 X86::NOT32r, X86::EAX,
11563 X86::GR32RegisterClass);
11564 case X86::ATOMNAND32:
11565 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11566 X86::AND32ri, X86::MOV32rm,
11568 X86::NOT32r, X86::EAX,
11569 X86::GR32RegisterClass, true);
11570 case X86::ATOMMIN32:
11571 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
11572 case X86::ATOMMAX32:
11573 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
11574 case X86::ATOMUMIN32:
11575 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
11576 case X86::ATOMUMAX32:
11577 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
11579 case X86::ATOMAND16:
11580 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11581 X86::AND16ri, X86::MOV16rm,
11583 X86::NOT16r, X86::AX,
11584 X86::GR16RegisterClass);
11585 case X86::ATOMOR16:
11586 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
11587 X86::OR16ri, X86::MOV16rm,
11589 X86::NOT16r, X86::AX,
11590 X86::GR16RegisterClass);
11591 case X86::ATOMXOR16:
11592 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
11593 X86::XOR16ri, X86::MOV16rm,
11595 X86::NOT16r, X86::AX,
11596 X86::GR16RegisterClass);
11597 case X86::ATOMNAND16:
11598 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11599 X86::AND16ri, X86::MOV16rm,
11601 X86::NOT16r, X86::AX,
11602 X86::GR16RegisterClass, true);
11603 case X86::ATOMMIN16:
11604 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
11605 case X86::ATOMMAX16:
11606 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
11607 case X86::ATOMUMIN16:
11608 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
11609 case X86::ATOMUMAX16:
11610 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
11612 case X86::ATOMAND8:
11613 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11614 X86::AND8ri, X86::MOV8rm,
11616 X86::NOT8r, X86::AL,
11617 X86::GR8RegisterClass);
11619 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
11620 X86::OR8ri, X86::MOV8rm,
11622 X86::NOT8r, X86::AL,
11623 X86::GR8RegisterClass);
11624 case X86::ATOMXOR8:
11625 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
11626 X86::XOR8ri, X86::MOV8rm,
11628 X86::NOT8r, X86::AL,
11629 X86::GR8RegisterClass);
11630 case X86::ATOMNAND8:
11631 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11632 X86::AND8ri, X86::MOV8rm,
11634 X86::NOT8r, X86::AL,
11635 X86::GR8RegisterClass, true);
11636 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
11637 // This group is for 64-bit host.
11638 case X86::ATOMAND64:
11639 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11640 X86::AND64ri32, X86::MOV64rm,
11642 X86::NOT64r, X86::RAX,
11643 X86::GR64RegisterClass);
11644 case X86::ATOMOR64:
11645 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
11646 X86::OR64ri32, X86::MOV64rm,
11648 X86::NOT64r, X86::RAX,
11649 X86::GR64RegisterClass);
11650 case X86::ATOMXOR64:
11651 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
11652 X86::XOR64ri32, X86::MOV64rm,
11654 X86::NOT64r, X86::RAX,
11655 X86::GR64RegisterClass);
11656 case X86::ATOMNAND64:
11657 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11658 X86::AND64ri32, X86::MOV64rm,
11660 X86::NOT64r, X86::RAX,
11661 X86::GR64RegisterClass, true);
11662 case X86::ATOMMIN64:
11663 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
11664 case X86::ATOMMAX64:
11665 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
11666 case X86::ATOMUMIN64:
11667 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
11668 case X86::ATOMUMAX64:
11669 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
11671 // This group does 64-bit operations on a 32-bit host.
11672 case X86::ATOMAND6432:
11673 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11674 X86::AND32rr, X86::AND32rr,
11675 X86::AND32ri, X86::AND32ri,
11677 case X86::ATOMOR6432:
11678 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11679 X86::OR32rr, X86::OR32rr,
11680 X86::OR32ri, X86::OR32ri,
11682 case X86::ATOMXOR6432:
11683 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11684 X86::XOR32rr, X86::XOR32rr,
11685 X86::XOR32ri, X86::XOR32ri,
11687 case X86::ATOMNAND6432:
11688 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11689 X86::AND32rr, X86::AND32rr,
11690 X86::AND32ri, X86::AND32ri,
11692 case X86::ATOMADD6432:
11693 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11694 X86::ADD32rr, X86::ADC32rr,
11695 X86::ADD32ri, X86::ADC32ri,
11697 case X86::ATOMSUB6432:
11698 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11699 X86::SUB32rr, X86::SBB32rr,
11700 X86::SUB32ri, X86::SBB32ri,
11702 case X86::ATOMSWAP6432:
11703 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11704 X86::MOV32rr, X86::MOV32rr,
11705 X86::MOV32ri, X86::MOV32ri,
11707 case X86::VASTART_SAVE_XMM_REGS:
11708 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
11710 case X86::VAARG_64:
11711 return EmitVAARG64WithCustomInserter(MI, BB);
11715 //===----------------------------------------------------------------------===//
11716 // X86 Optimization Hooks
11717 //===----------------------------------------------------------------------===//
11719 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
11723 const SelectionDAG &DAG,
11724 unsigned Depth) const {
11725 unsigned Opc = Op.getOpcode();
11726 assert((Opc >= ISD::BUILTIN_OP_END ||
11727 Opc == ISD::INTRINSIC_WO_CHAIN ||
11728 Opc == ISD::INTRINSIC_W_CHAIN ||
11729 Opc == ISD::INTRINSIC_VOID) &&
11730 "Should use MaskedValueIsZero if you don't know whether Op"
11731 " is a target node!");
11733 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
11747 // These nodes' second result is a boolean.
11748 if (Op.getResNo() == 0)
11751 case X86ISD::SETCC:
11752 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
11753 Mask.getBitWidth() - 1);
11758 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
11759 unsigned Depth) const {
11760 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
11761 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
11762 return Op.getValueType().getScalarType().getSizeInBits();
11768 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
11769 /// node is a GlobalAddress + offset.
11770 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
11771 const GlobalValue* &GA,
11772 int64_t &Offset) const {
11773 if (N->getOpcode() == X86ISD::Wrapper) {
11774 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
11775 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
11776 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
11780 return TargetLowering::isGAPlusOffset(N, GA, Offset);
11783 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
11784 /// same as extracting the high 128-bit part of 256-bit vector and then
11785 /// inserting the result into the low part of a new 256-bit vector
11786 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
11787 EVT VT = SVOp->getValueType(0);
11788 int NumElems = VT.getVectorNumElements();
11790 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
11791 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
11792 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
11793 SVOp->getMaskElt(j) >= 0)
11799 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
11800 /// same as extracting the low 128-bit part of 256-bit vector and then
11801 /// inserting the result into the high part of a new 256-bit vector
11802 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
11803 EVT VT = SVOp->getValueType(0);
11804 int NumElems = VT.getVectorNumElements();
11806 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
11807 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
11808 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
11809 SVOp->getMaskElt(j) >= 0)
11815 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
11816 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
11817 TargetLowering::DAGCombinerInfo &DCI) {
11818 DebugLoc dl = N->getDebugLoc();
11819 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
11820 SDValue V1 = SVOp->getOperand(0);
11821 SDValue V2 = SVOp->getOperand(1);
11822 EVT VT = SVOp->getValueType(0);
11823 int NumElems = VT.getVectorNumElements();
11825 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
11826 V2.getOpcode() == ISD::CONCAT_VECTORS) {
11830 // V UNDEF BUILD_VECTOR UNDEF
11832 // CONCAT_VECTOR CONCAT_VECTOR
11835 // RESULT: V + zero extended
11837 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
11838 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
11839 V1.getOperand(1).getOpcode() != ISD::UNDEF)
11842 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
11845 // To match the shuffle mask, the first half of the mask should
11846 // be exactly the first vector, and all the rest a splat with the
11847 // first element of the second one.
11848 for (int i = 0; i < NumElems/2; ++i)
11849 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
11850 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
11853 // Emit a zeroed vector and insert the desired subvector on its
11855 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
11856 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
11857 DAG.getConstant(0, MVT::i32), DAG, dl);
11858 return DCI.CombineTo(N, InsV);
11861 //===--------------------------------------------------------------------===//
11862 // Combine some shuffles into subvector extracts and inserts:
11865 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
11866 if (isShuffleHigh128VectorInsertLow(SVOp)) {
11867 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
11869 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
11870 V, DAG.getConstant(0, MVT::i32), DAG, dl);
11871 return DCI.CombineTo(N, InsV);
11874 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
11875 if (isShuffleLow128VectorInsertHigh(SVOp)) {
11876 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
11877 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
11878 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
11879 return DCI.CombineTo(N, InsV);
11885 /// PerformShuffleCombine - Performs several different shuffle combines.
11886 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
11887 TargetLowering::DAGCombinerInfo &DCI,
11888 const X86Subtarget *Subtarget) {
11889 DebugLoc dl = N->getDebugLoc();
11890 EVT VT = N->getValueType(0);
11892 // Don't create instructions with illegal types after legalize types has run.
11893 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11894 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
11897 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
11898 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
11899 N->getOpcode() == ISD::VECTOR_SHUFFLE)
11900 return PerformShuffleCombine256(N, DAG, DCI);
11902 // Only handle 128 wide vector from here on.
11903 if (VT.getSizeInBits() != 128)
11906 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
11907 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
11908 // consecutive, non-overlapping, and in the right order.
11909 SmallVector<SDValue, 16> Elts;
11910 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
11911 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
11913 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
11916 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
11917 /// generation and convert it from being a bunch of shuffles and extracts
11918 /// to a simple store and scalar loads to extract the elements.
11919 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
11920 const TargetLowering &TLI) {
11921 SDValue InputVector = N->getOperand(0);
11923 // Only operate on vectors of 4 elements, where the alternative shuffling
11924 // gets to be more expensive.
11925 if (InputVector.getValueType() != MVT::v4i32)
11928 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
11929 // single use which is a sign-extend or zero-extend, and all elements are
11931 SmallVector<SDNode *, 4> Uses;
11932 unsigned ExtractedElements = 0;
11933 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
11934 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
11935 if (UI.getUse().getResNo() != InputVector.getResNo())
11938 SDNode *Extract = *UI;
11939 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11942 if (Extract->getValueType(0) != MVT::i32)
11944 if (!Extract->hasOneUse())
11946 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
11947 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
11949 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
11952 // Record which element was extracted.
11953 ExtractedElements |=
11954 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
11956 Uses.push_back(Extract);
11959 // If not all the elements were used, this may not be worthwhile.
11960 if (ExtractedElements != 15)
11963 // Ok, we've now decided to do the transformation.
11964 DebugLoc dl = InputVector.getDebugLoc();
11966 // Store the value to a temporary stack slot.
11967 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
11968 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
11969 MachinePointerInfo(), false, false, 0);
11971 // Replace each use (extract) with a load of the appropriate element.
11972 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
11973 UE = Uses.end(); UI != UE; ++UI) {
11974 SDNode *Extract = *UI;
11976 // cOMpute the element's address.
11977 SDValue Idx = Extract->getOperand(1);
11979 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
11980 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
11981 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
11983 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
11984 StackPtr, OffsetVal);
11986 // Load the scalar.
11987 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
11988 ScalarAddr, MachinePointerInfo(),
11991 // Replace the exact with the load.
11992 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
11995 // The replacement was made in place; don't return anything.
11999 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12000 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12001 const X86Subtarget *Subtarget) {
12002 DebugLoc DL = N->getDebugLoc();
12003 SDValue Cond = N->getOperand(0);
12004 // Get the LHS/RHS of the select.
12005 SDValue LHS = N->getOperand(1);
12006 SDValue RHS = N->getOperand(2);
12008 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12009 // instructions match the semantics of the common C idiom x<y?x:y but not
12010 // x<=y?x:y, because of how they handle negative zero (which can be
12011 // ignored in unsafe-math mode).
12012 if (Subtarget->hasSSE2() &&
12013 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12014 Cond.getOpcode() == ISD::SETCC) {
12015 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12017 unsigned Opcode = 0;
12018 // Check for x CC y ? x : y.
12019 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12020 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12024 // Converting this to a min would handle NaNs incorrectly, and swapping
12025 // the operands would cause it to handle comparisons between positive
12026 // and negative zero incorrectly.
12027 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12028 if (!UnsafeFPMath &&
12029 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12031 std::swap(LHS, RHS);
12033 Opcode = X86ISD::FMIN;
12036 // Converting this to a min would handle comparisons between positive
12037 // and negative zero incorrectly.
12038 if (!UnsafeFPMath &&
12039 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12041 Opcode = X86ISD::FMIN;
12044 // Converting this to a min would handle both negative zeros and NaNs
12045 // incorrectly, but we can swap the operands to fix both.
12046 std::swap(LHS, RHS);
12050 Opcode = X86ISD::FMIN;
12054 // Converting this to a max would handle comparisons between positive
12055 // and negative zero incorrectly.
12056 if (!UnsafeFPMath &&
12057 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12059 Opcode = X86ISD::FMAX;
12062 // Converting this to a max would handle NaNs incorrectly, and swapping
12063 // the operands would cause it to handle comparisons between positive
12064 // and negative zero incorrectly.
12065 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12066 if (!UnsafeFPMath &&
12067 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12069 std::swap(LHS, RHS);
12071 Opcode = X86ISD::FMAX;
12074 // Converting this to a max would handle both negative zeros and NaNs
12075 // incorrectly, but we can swap the operands to fix both.
12076 std::swap(LHS, RHS);
12080 Opcode = X86ISD::FMAX;
12083 // Check for x CC y ? y : x -- a min/max with reversed arms.
12084 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12085 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12089 // Converting this to a min would handle comparisons between positive
12090 // and negative zero incorrectly, and swapping the operands would
12091 // cause it to handle NaNs incorrectly.
12092 if (!UnsafeFPMath &&
12093 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12094 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12096 std::swap(LHS, RHS);
12098 Opcode = X86ISD::FMIN;
12101 // Converting this to a min would handle NaNs incorrectly.
12102 if (!UnsafeFPMath &&
12103 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12105 Opcode = X86ISD::FMIN;
12108 // Converting this to a min would handle both negative zeros and NaNs
12109 // incorrectly, but we can swap the operands to fix both.
12110 std::swap(LHS, RHS);
12114 Opcode = X86ISD::FMIN;
12118 // Converting this to a max would handle NaNs incorrectly.
12119 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12121 Opcode = X86ISD::FMAX;
12124 // Converting this to a max would handle comparisons between positive
12125 // and negative zero incorrectly, and swapping the operands would
12126 // cause it to handle NaNs incorrectly.
12127 if (!UnsafeFPMath &&
12128 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12129 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12131 std::swap(LHS, RHS);
12133 Opcode = X86ISD::FMAX;
12136 // Converting this to a max would handle both negative zeros and NaNs
12137 // incorrectly, but we can swap the operands to fix both.
12138 std::swap(LHS, RHS);
12142 Opcode = X86ISD::FMAX;
12148 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12151 // If this is a select between two integer constants, try to do some
12153 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12154 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12155 // Don't do this for crazy integer types.
12156 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12157 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12158 // so that TrueC (the true value) is larger than FalseC.
12159 bool NeedsCondInvert = false;
12161 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12162 // Efficiently invertible.
12163 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12164 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12165 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12166 NeedsCondInvert = true;
12167 std::swap(TrueC, FalseC);
12170 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12171 if (FalseC->getAPIntValue() == 0 &&
12172 TrueC->getAPIntValue().isPowerOf2()) {
12173 if (NeedsCondInvert) // Invert the condition if needed.
12174 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12175 DAG.getConstant(1, Cond.getValueType()));
12177 // Zero extend the condition if needed.
12178 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12180 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12181 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12182 DAG.getConstant(ShAmt, MVT::i8));
12185 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12186 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12187 if (NeedsCondInvert) // Invert the condition if needed.
12188 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12189 DAG.getConstant(1, Cond.getValueType()));
12191 // Zero extend the condition if needed.
12192 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12193 FalseC->getValueType(0), Cond);
12194 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12195 SDValue(FalseC, 0));
12198 // Optimize cases that will turn into an LEA instruction. This requires
12199 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12200 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12201 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12202 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12204 bool isFastMultiplier = false;
12206 switch ((unsigned char)Diff) {
12208 case 1: // result = add base, cond
12209 case 2: // result = lea base( , cond*2)
12210 case 3: // result = lea base(cond, cond*2)
12211 case 4: // result = lea base( , cond*4)
12212 case 5: // result = lea base(cond, cond*4)
12213 case 8: // result = lea base( , cond*8)
12214 case 9: // result = lea base(cond, cond*8)
12215 isFastMultiplier = true;
12220 if (isFastMultiplier) {
12221 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12222 if (NeedsCondInvert) // Invert the condition if needed.
12223 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12224 DAG.getConstant(1, Cond.getValueType()));
12226 // Zero extend the condition if needed.
12227 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12229 // Scale the condition by the difference.
12231 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12232 DAG.getConstant(Diff, Cond.getValueType()));
12234 // Add the base if non-zero.
12235 if (FalseC->getAPIntValue() != 0)
12236 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12237 SDValue(FalseC, 0));
12247 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12248 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12249 TargetLowering::DAGCombinerInfo &DCI) {
12250 DebugLoc DL = N->getDebugLoc();
12252 // If the flag operand isn't dead, don't touch this CMOV.
12253 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12256 SDValue FalseOp = N->getOperand(0);
12257 SDValue TrueOp = N->getOperand(1);
12258 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12259 SDValue Cond = N->getOperand(3);
12260 if (CC == X86::COND_E || CC == X86::COND_NE) {
12261 switch (Cond.getOpcode()) {
12265 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12266 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12267 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12271 // If this is a select between two integer constants, try to do some
12272 // optimizations. Note that the operands are ordered the opposite of SELECT
12274 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12275 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12276 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12277 // larger than FalseC (the false value).
12278 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12279 CC = X86::GetOppositeBranchCondition(CC);
12280 std::swap(TrueC, FalseC);
12283 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12284 // This is efficient for any integer data type (including i8/i16) and
12286 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12287 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12288 DAG.getConstant(CC, MVT::i8), Cond);
12290 // Zero extend the condition if needed.
12291 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12293 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12294 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12295 DAG.getConstant(ShAmt, MVT::i8));
12296 if (N->getNumValues() == 2) // Dead flag value?
12297 return DCI.CombineTo(N, Cond, SDValue());
12301 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12302 // for any integer data type, including i8/i16.
12303 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12304 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12305 DAG.getConstant(CC, MVT::i8), Cond);
12307 // Zero extend the condition if needed.
12308 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12309 FalseC->getValueType(0), Cond);
12310 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12311 SDValue(FalseC, 0));
12313 if (N->getNumValues() == 2) // Dead flag value?
12314 return DCI.CombineTo(N, Cond, SDValue());
12318 // Optimize cases that will turn into an LEA instruction. This requires
12319 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12320 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12321 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12322 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12324 bool isFastMultiplier = false;
12326 switch ((unsigned char)Diff) {
12328 case 1: // result = add base, cond
12329 case 2: // result = lea base( , cond*2)
12330 case 3: // result = lea base(cond, cond*2)
12331 case 4: // result = lea base( , cond*4)
12332 case 5: // result = lea base(cond, cond*4)
12333 case 8: // result = lea base( , cond*8)
12334 case 9: // result = lea base(cond, cond*8)
12335 isFastMultiplier = true;
12340 if (isFastMultiplier) {
12341 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12342 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12343 DAG.getConstant(CC, MVT::i8), Cond);
12344 // Zero extend the condition if needed.
12345 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12347 // Scale the condition by the difference.
12349 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12350 DAG.getConstant(Diff, Cond.getValueType()));
12352 // Add the base if non-zero.
12353 if (FalseC->getAPIntValue() != 0)
12354 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12355 SDValue(FalseC, 0));
12356 if (N->getNumValues() == 2) // Dead flag value?
12357 return DCI.CombineTo(N, Cond, SDValue());
12367 /// PerformMulCombine - Optimize a single multiply with constant into two
12368 /// in order to implement it with two cheaper instructions, e.g.
12369 /// LEA + SHL, LEA + LEA.
12370 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12371 TargetLowering::DAGCombinerInfo &DCI) {
12372 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12375 EVT VT = N->getValueType(0);
12376 if (VT != MVT::i64)
12379 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12382 uint64_t MulAmt = C->getZExtValue();
12383 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12386 uint64_t MulAmt1 = 0;
12387 uint64_t MulAmt2 = 0;
12388 if ((MulAmt % 9) == 0) {
12390 MulAmt2 = MulAmt / 9;
12391 } else if ((MulAmt % 5) == 0) {
12393 MulAmt2 = MulAmt / 5;
12394 } else if ((MulAmt % 3) == 0) {
12396 MulAmt2 = MulAmt / 3;
12399 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12400 DebugLoc DL = N->getDebugLoc();
12402 if (isPowerOf2_64(MulAmt2) &&
12403 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12404 // If second multiplifer is pow2, issue it first. We want the multiply by
12405 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12407 std::swap(MulAmt1, MulAmt2);
12410 if (isPowerOf2_64(MulAmt1))
12411 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12412 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12414 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12415 DAG.getConstant(MulAmt1, VT));
12417 if (isPowerOf2_64(MulAmt2))
12418 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12419 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12421 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12422 DAG.getConstant(MulAmt2, VT));
12424 // Do not add new nodes to DAG combiner worklist.
12425 DCI.CombineTo(N, NewMul, false);
12430 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12431 SDValue N0 = N->getOperand(0);
12432 SDValue N1 = N->getOperand(1);
12433 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12434 EVT VT = N0.getValueType();
12436 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12437 // since the result of setcc_c is all zero's or all ones.
12438 if (N1C && N0.getOpcode() == ISD::AND &&
12439 N0.getOperand(1).getOpcode() == ISD::Constant) {
12440 SDValue N00 = N0.getOperand(0);
12441 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12442 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12443 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12444 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12445 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12446 APInt ShAmt = N1C->getAPIntValue();
12447 Mask = Mask.shl(ShAmt);
12449 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12450 N00, DAG.getConstant(Mask, VT));
12457 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12459 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12460 const X86Subtarget *Subtarget) {
12461 EVT VT = N->getValueType(0);
12462 if (!VT.isVector() && VT.isInteger() &&
12463 N->getOpcode() == ISD::SHL)
12464 return PerformSHLCombine(N, DAG);
12466 // On X86 with SSE2 support, we can transform this to a vector shift if
12467 // all elements are shifted by the same amount. We can't do this in legalize
12468 // because the a constant vector is typically transformed to a constant pool
12469 // so we have no knowledge of the shift amount.
12470 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
12473 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
12476 SDValue ShAmtOp = N->getOperand(1);
12477 EVT EltVT = VT.getVectorElementType();
12478 DebugLoc DL = N->getDebugLoc();
12479 SDValue BaseShAmt = SDValue();
12480 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
12481 unsigned NumElts = VT.getVectorNumElements();
12483 for (; i != NumElts; ++i) {
12484 SDValue Arg = ShAmtOp.getOperand(i);
12485 if (Arg.getOpcode() == ISD::UNDEF) continue;
12489 for (; i != NumElts; ++i) {
12490 SDValue Arg = ShAmtOp.getOperand(i);
12491 if (Arg.getOpcode() == ISD::UNDEF) continue;
12492 if (Arg != BaseShAmt) {
12496 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
12497 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
12498 SDValue InVec = ShAmtOp.getOperand(0);
12499 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12500 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12502 for (; i != NumElts; ++i) {
12503 SDValue Arg = InVec.getOperand(i);
12504 if (Arg.getOpcode() == ISD::UNDEF) continue;
12508 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12509 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12510 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
12511 if (C->getZExtValue() == SplatIdx)
12512 BaseShAmt = InVec.getOperand(1);
12515 if (BaseShAmt.getNode() == 0)
12516 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
12517 DAG.getIntPtrConstant(0));
12521 // The shift amount is an i32.
12522 if (EltVT.bitsGT(MVT::i32))
12523 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
12524 else if (EltVT.bitsLT(MVT::i32))
12525 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
12527 // The shift amount is identical so we can do a vector shift.
12528 SDValue ValOp = N->getOperand(0);
12529 switch (N->getOpcode()) {
12531 llvm_unreachable("Unknown shift opcode!");
12534 if (VT == MVT::v2i64)
12535 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12536 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
12538 if (VT == MVT::v4i32)
12539 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12540 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
12542 if (VT == MVT::v8i16)
12543 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12544 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
12548 if (VT == MVT::v4i32)
12549 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12550 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
12552 if (VT == MVT::v8i16)
12553 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12554 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
12558 if (VT == MVT::v2i64)
12559 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12560 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
12562 if (VT == MVT::v4i32)
12563 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12564 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
12566 if (VT == MVT::v8i16)
12567 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12568 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
12576 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12577 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
12578 // and friends. Likewise for OR -> CMPNEQSS.
12579 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
12580 TargetLowering::DAGCombinerInfo &DCI,
12581 const X86Subtarget *Subtarget) {
12584 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
12585 // we're requiring SSE2 for both.
12586 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
12587 SDValue N0 = N->getOperand(0);
12588 SDValue N1 = N->getOperand(1);
12589 SDValue CMP0 = N0->getOperand(1);
12590 SDValue CMP1 = N1->getOperand(1);
12591 DebugLoc DL = N->getDebugLoc();
12593 // The SETCCs should both refer to the same CMP.
12594 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
12597 SDValue CMP00 = CMP0->getOperand(0);
12598 SDValue CMP01 = CMP0->getOperand(1);
12599 EVT VT = CMP00.getValueType();
12601 if (VT == MVT::f32 || VT == MVT::f64) {
12602 bool ExpectingFlags = false;
12603 // Check for any users that want flags:
12604 for (SDNode::use_iterator UI = N->use_begin(),
12606 !ExpectingFlags && UI != UE; ++UI)
12607 switch (UI->getOpcode()) {
12612 ExpectingFlags = true;
12614 case ISD::CopyToReg:
12615 case ISD::SIGN_EXTEND:
12616 case ISD::ZERO_EXTEND:
12617 case ISD::ANY_EXTEND:
12621 if (!ExpectingFlags) {
12622 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
12623 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
12625 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
12626 X86::CondCode tmp = cc0;
12631 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
12632 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
12633 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
12634 X86ISD::NodeType NTOperator = is64BitFP ?
12635 X86ISD::FSETCCsd : X86ISD::FSETCCss;
12636 // FIXME: need symbolic constants for these magic numbers.
12637 // See X86ATTInstPrinter.cpp:printSSECC().
12638 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
12639 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
12640 DAG.getConstant(x86cc, MVT::i8));
12641 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
12643 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
12644 DAG.getConstant(1, MVT::i32));
12645 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
12646 return OneBitOfTruth;
12654 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
12655 /// so it can be folded inside ANDNP.
12656 static bool CanFoldXORWithAllOnes(const SDNode *N) {
12657 EVT VT = N->getValueType(0);
12659 // Match direct AllOnes for 128 and 256-bit vectors
12660 if (ISD::isBuildVectorAllOnes(N))
12663 // Look through a bit convert.
12664 if (N->getOpcode() == ISD::BITCAST)
12665 N = N->getOperand(0).getNode();
12667 // Sometimes the operand may come from a insert_subvector building a 256-bit
12669 if (VT.getSizeInBits() == 256 &&
12670 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
12671 SDValue V1 = N->getOperand(0);
12672 SDValue V2 = N->getOperand(1);
12674 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
12675 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
12676 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
12677 ISD::isBuildVectorAllOnes(V2.getNode()))
12684 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
12685 TargetLowering::DAGCombinerInfo &DCI,
12686 const X86Subtarget *Subtarget) {
12687 if (DCI.isBeforeLegalizeOps())
12690 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12694 // Want to form ANDNP nodes:
12695 // 1) In the hopes of then easily combining them with OR and AND nodes
12696 // to form PBLEND/PSIGN.
12697 // 2) To match ANDN packed intrinsics
12698 EVT VT = N->getValueType(0);
12699 if (VT != MVT::v2i64 && VT != MVT::v4i64)
12702 SDValue N0 = N->getOperand(0);
12703 SDValue N1 = N->getOperand(1);
12704 DebugLoc DL = N->getDebugLoc();
12706 // Check LHS for vnot
12707 if (N0.getOpcode() == ISD::XOR &&
12708 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
12709 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
12710 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
12712 // Check RHS for vnot
12713 if (N1.getOpcode() == ISD::XOR &&
12714 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
12715 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
12716 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
12721 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
12722 TargetLowering::DAGCombinerInfo &DCI,
12723 const X86Subtarget *Subtarget) {
12724 if (DCI.isBeforeLegalizeOps())
12727 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12731 EVT VT = N->getValueType(0);
12732 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
12735 SDValue N0 = N->getOperand(0);
12736 SDValue N1 = N->getOperand(1);
12738 // look for psign/blend
12739 if (Subtarget->hasSSSE3()) {
12740 if (VT == MVT::v2i64) {
12741 // Canonicalize pandn to RHS
12742 if (N0.getOpcode() == X86ISD::ANDNP)
12744 // or (and (m, x), (pandn m, y))
12745 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
12746 SDValue Mask = N1.getOperand(0);
12747 SDValue X = N1.getOperand(1);
12749 if (N0.getOperand(0) == Mask)
12750 Y = N0.getOperand(1);
12751 if (N0.getOperand(1) == Mask)
12752 Y = N0.getOperand(0);
12754 // Check to see if the mask appeared in both the AND and ANDNP and
12758 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
12759 if (Mask.getOpcode() != ISD::BITCAST ||
12760 X.getOpcode() != ISD::BITCAST ||
12761 Y.getOpcode() != ISD::BITCAST)
12764 // Look through mask bitcast.
12765 Mask = Mask.getOperand(0);
12766 EVT MaskVT = Mask.getValueType();
12768 // Validate that the Mask operand is a vector sra node. The sra node
12769 // will be an intrinsic.
12770 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
12773 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
12774 // there is no psrai.b
12775 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
12776 case Intrinsic::x86_sse2_psrai_w:
12777 case Intrinsic::x86_sse2_psrai_d:
12779 default: return SDValue();
12782 // Check that the SRA is all signbits.
12783 SDValue SraC = Mask.getOperand(2);
12784 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
12785 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
12786 if ((SraAmt + 1) != EltBits)
12789 DebugLoc DL = N->getDebugLoc();
12791 // Now we know we at least have a plendvb with the mask val. See if
12792 // we can form a psignb/w/d.
12793 // psign = x.type == y.type == mask.type && y = sub(0, x);
12794 X = X.getOperand(0);
12795 Y = Y.getOperand(0);
12796 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
12797 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
12798 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
12801 case 8: Opc = X86ISD::PSIGNB; break;
12802 case 16: Opc = X86ISD::PSIGNW; break;
12803 case 32: Opc = X86ISD::PSIGND; break;
12807 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
12808 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
12811 // PBLENDVB only available on SSE 4.1
12812 if (!Subtarget->hasSSE41())
12815 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
12816 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
12817 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
12818 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
12819 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
12824 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
12825 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
12827 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
12829 if (!N0.hasOneUse() || !N1.hasOneUse())
12832 SDValue ShAmt0 = N0.getOperand(1);
12833 if (ShAmt0.getValueType() != MVT::i8)
12835 SDValue ShAmt1 = N1.getOperand(1);
12836 if (ShAmt1.getValueType() != MVT::i8)
12838 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
12839 ShAmt0 = ShAmt0.getOperand(0);
12840 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
12841 ShAmt1 = ShAmt1.getOperand(0);
12843 DebugLoc DL = N->getDebugLoc();
12844 unsigned Opc = X86ISD::SHLD;
12845 SDValue Op0 = N0.getOperand(0);
12846 SDValue Op1 = N1.getOperand(0);
12847 if (ShAmt0.getOpcode() == ISD::SUB) {
12848 Opc = X86ISD::SHRD;
12849 std::swap(Op0, Op1);
12850 std::swap(ShAmt0, ShAmt1);
12853 unsigned Bits = VT.getSizeInBits();
12854 if (ShAmt1.getOpcode() == ISD::SUB) {
12855 SDValue Sum = ShAmt1.getOperand(0);
12856 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
12857 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
12858 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
12859 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
12860 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
12861 return DAG.getNode(Opc, DL, VT,
12863 DAG.getNode(ISD::TRUNCATE, DL,
12866 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
12867 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
12869 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
12870 return DAG.getNode(Opc, DL, VT,
12871 N0.getOperand(0), N1.getOperand(0),
12872 DAG.getNode(ISD::TRUNCATE, DL,
12879 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
12880 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
12881 const X86Subtarget *Subtarget) {
12882 StoreSDNode *St = cast<StoreSDNode>(N);
12883 EVT VT = St->getValue().getValueType();
12884 EVT StVT = St->getMemoryVT();
12885 DebugLoc dl = St->getDebugLoc();
12886 SDValue StoredVal = St->getOperand(1);
12887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12889 // If we are saving a concatination of two XMM registers, perform two stores.
12890 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
12891 // 128-bit ones. If in the future the cost becomes only one memory access the
12892 // first version would be better.
12893 if (VT.getSizeInBits() == 256 &&
12894 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
12895 StoredVal.getNumOperands() == 2) {
12897 SDValue Value0 = StoredVal.getOperand(0);
12898 SDValue Value1 = StoredVal.getOperand(1);
12900 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
12901 SDValue Ptr0 = St->getBasePtr();
12902 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
12904 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
12905 St->getPointerInfo(), St->isVolatile(),
12906 St->isNonTemporal(), St->getAlignment());
12907 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
12908 St->getPointerInfo(), St->isVolatile(),
12909 St->isNonTemporal(), St->getAlignment());
12910 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
12913 // Optimize trunc store (of multiple scalars) to shuffle and store.
12914 // First, pack all of the elements in one place. Next, store to memory
12915 // in fewer chunks.
12916 if (St->isTruncatingStore() && VT.isVector()) {
12917 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12918 unsigned NumElems = VT.getVectorNumElements();
12919 assert(StVT != VT && "Cannot truncate to the same type");
12920 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
12921 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
12923 // From, To sizes and ElemCount must be pow of two
12924 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
12925 // We are going to use the original vector elt for storing.
12926 // accumulated smaller vector elements must be a multiple of bigger size.
12927 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
12928 unsigned SizeRatio = FromSz / ToSz;
12930 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
12932 // Create a type on which we perform the shuffle
12933 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
12934 StVT.getScalarType(), NumElems*SizeRatio);
12936 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
12938 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
12939 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
12940 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
12942 // Can't shuffle using an illegal type
12943 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
12945 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
12946 DAG.getUNDEF(WideVec.getValueType()),
12947 ShuffleVec.data());
12948 // At this point all of the data is stored at the bottom of the
12949 // register. We now need to save it to mem.
12951 // Find the largest store unit
12952 MVT StoreType = MVT::i8;
12953 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
12954 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
12955 MVT Tp = (MVT::SimpleValueType)tp;
12956 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
12960 // Bitcast the original vector into a vector of store-size units
12961 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
12962 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
12963 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
12964 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
12965 SmallVector<SDValue, 8> Chains;
12966 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
12967 TLI.getPointerTy());
12968 SDValue Ptr = St->getBasePtr();
12970 // Perform one or more big stores into memory.
12971 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
12972 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12973 StoreType, ShuffWide,
12974 DAG.getIntPtrConstant(i));
12975 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
12976 St->getPointerInfo(), St->isVolatile(),
12977 St->isNonTemporal(), St->getAlignment());
12978 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
12979 Chains.push_back(Ch);
12982 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
12987 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
12988 // the FP state in cases where an emms may be missing.
12989 // A preferable solution to the general problem is to figure out the right
12990 // places to insert EMMS. This qualifies as a quick hack.
12992 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
12993 if (VT.getSizeInBits() != 64)
12996 const Function *F = DAG.getMachineFunction().getFunction();
12997 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
12998 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
12999 && Subtarget->hasSSE2();
13000 if ((VT.isVector() ||
13001 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13002 isa<LoadSDNode>(St->getValue()) &&
13003 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13004 St->getChain().hasOneUse() && !St->isVolatile()) {
13005 SDNode* LdVal = St->getValue().getNode();
13006 LoadSDNode *Ld = 0;
13007 int TokenFactorIndex = -1;
13008 SmallVector<SDValue, 8> Ops;
13009 SDNode* ChainVal = St->getChain().getNode();
13010 // Must be a store of a load. We currently handle two cases: the load
13011 // is a direct child, and it's under an intervening TokenFactor. It is
13012 // possible to dig deeper under nested TokenFactors.
13013 if (ChainVal == LdVal)
13014 Ld = cast<LoadSDNode>(St->getChain());
13015 else if (St->getValue().hasOneUse() &&
13016 ChainVal->getOpcode() == ISD::TokenFactor) {
13017 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13018 if (ChainVal->getOperand(i).getNode() == LdVal) {
13019 TokenFactorIndex = i;
13020 Ld = cast<LoadSDNode>(St->getValue());
13022 Ops.push_back(ChainVal->getOperand(i));
13026 if (!Ld || !ISD::isNormalLoad(Ld))
13029 // If this is not the MMX case, i.e. we are just turning i64 load/store
13030 // into f64 load/store, avoid the transformation if there are multiple
13031 // uses of the loaded value.
13032 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13035 DebugLoc LdDL = Ld->getDebugLoc();
13036 DebugLoc StDL = N->getDebugLoc();
13037 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13038 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13040 if (Subtarget->is64Bit() || F64IsLegal) {
13041 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13042 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13043 Ld->getPointerInfo(), Ld->isVolatile(),
13044 Ld->isNonTemporal(), Ld->getAlignment());
13045 SDValue NewChain = NewLd.getValue(1);
13046 if (TokenFactorIndex != -1) {
13047 Ops.push_back(NewChain);
13048 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13051 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13052 St->getPointerInfo(),
13053 St->isVolatile(), St->isNonTemporal(),
13054 St->getAlignment());
13057 // Otherwise, lower to two pairs of 32-bit loads / stores.
13058 SDValue LoAddr = Ld->getBasePtr();
13059 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13060 DAG.getConstant(4, MVT::i32));
13062 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13063 Ld->getPointerInfo(),
13064 Ld->isVolatile(), Ld->isNonTemporal(),
13065 Ld->getAlignment());
13066 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13067 Ld->getPointerInfo().getWithOffset(4),
13068 Ld->isVolatile(), Ld->isNonTemporal(),
13069 MinAlign(Ld->getAlignment(), 4));
13071 SDValue NewChain = LoLd.getValue(1);
13072 if (TokenFactorIndex != -1) {
13073 Ops.push_back(LoLd);
13074 Ops.push_back(HiLd);
13075 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13079 LoAddr = St->getBasePtr();
13080 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13081 DAG.getConstant(4, MVT::i32));
13083 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13084 St->getPointerInfo(),
13085 St->isVolatile(), St->isNonTemporal(),
13086 St->getAlignment());
13087 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13088 St->getPointerInfo().getWithOffset(4),
13090 St->isNonTemporal(),
13091 MinAlign(St->getAlignment(), 4));
13092 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13097 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13098 /// X86ISD::FXOR nodes.
13099 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13100 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13101 // F[X]OR(0.0, x) -> x
13102 // F[X]OR(x, 0.0) -> x
13103 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13104 if (C->getValueAPF().isPosZero())
13105 return N->getOperand(1);
13106 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13107 if (C->getValueAPF().isPosZero())
13108 return N->getOperand(0);
13112 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13113 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13114 // FAND(0.0, x) -> 0.0
13115 // FAND(x, 0.0) -> 0.0
13116 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13117 if (C->getValueAPF().isPosZero())
13118 return N->getOperand(0);
13119 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13120 if (C->getValueAPF().isPosZero())
13121 return N->getOperand(1);
13125 static SDValue PerformBTCombine(SDNode *N,
13127 TargetLowering::DAGCombinerInfo &DCI) {
13128 // BT ignores high bits in the bit index operand.
13129 SDValue Op1 = N->getOperand(1);
13130 if (Op1.hasOneUse()) {
13131 unsigned BitWidth = Op1.getValueSizeInBits();
13132 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13133 APInt KnownZero, KnownOne;
13134 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13135 !DCI.isBeforeLegalizeOps());
13136 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13137 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13138 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13139 DCI.CommitTargetLoweringOpt(TLO);
13144 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13145 SDValue Op = N->getOperand(0);
13146 if (Op.getOpcode() == ISD::BITCAST)
13147 Op = Op.getOperand(0);
13148 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13149 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13150 VT.getVectorElementType().getSizeInBits() ==
13151 OpVT.getVectorElementType().getSizeInBits()) {
13152 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13157 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13158 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13159 // (and (i32 x86isd::setcc_carry), 1)
13160 // This eliminates the zext. This transformation is necessary because
13161 // ISD::SETCC is always legalized to i8.
13162 DebugLoc dl = N->getDebugLoc();
13163 SDValue N0 = N->getOperand(0);
13164 EVT VT = N->getValueType(0);
13165 if (N0.getOpcode() == ISD::AND &&
13167 N0.getOperand(0).hasOneUse()) {
13168 SDValue N00 = N0.getOperand(0);
13169 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13171 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13172 if (!C || C->getZExtValue() != 1)
13174 return DAG.getNode(ISD::AND, dl, VT,
13175 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13176 N00.getOperand(0), N00.getOperand(1)),
13177 DAG.getConstant(1, VT));
13183 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13184 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13185 unsigned X86CC = N->getConstantOperandVal(0);
13186 SDValue EFLAG = N->getOperand(1);
13187 DebugLoc DL = N->getDebugLoc();
13189 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13190 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13192 if (X86CC == X86::COND_B)
13193 return DAG.getNode(ISD::AND, DL, MVT::i8,
13194 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13195 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13196 DAG.getConstant(1, MVT::i8));
13201 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13202 const X86TargetLowering *XTLI) {
13203 SDValue Op0 = N->getOperand(0);
13204 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13205 // a 32-bit target where SSE doesn't support i64->FP operations.
13206 if (Op0.getOpcode() == ISD::LOAD) {
13207 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13208 EVT VT = Ld->getValueType(0);
13209 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13210 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13211 !XTLI->getSubtarget()->is64Bit() &&
13212 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13213 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13214 Ld->getChain(), Op0, DAG);
13215 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13222 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13223 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13224 X86TargetLowering::DAGCombinerInfo &DCI) {
13225 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13226 // the result is either zero or one (depending on the input carry bit).
13227 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13228 if (X86::isZeroNode(N->getOperand(0)) &&
13229 X86::isZeroNode(N->getOperand(1)) &&
13230 // We don't have a good way to replace an EFLAGS use, so only do this when
13232 SDValue(N, 1).use_empty()) {
13233 DebugLoc DL = N->getDebugLoc();
13234 EVT VT = N->getValueType(0);
13235 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13236 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13237 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13238 DAG.getConstant(X86::COND_B,MVT::i8),
13240 DAG.getConstant(1, VT));
13241 return DCI.CombineTo(N, Res1, CarryOut);
13247 // fold (add Y, (sete X, 0)) -> adc 0, Y
13248 // (add Y, (setne X, 0)) -> sbb -1, Y
13249 // (sub (sete X, 0), Y) -> sbb 0, Y
13250 // (sub (setne X, 0), Y) -> adc -1, Y
13251 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13252 DebugLoc DL = N->getDebugLoc();
13254 // Look through ZExts.
13255 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13256 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13259 SDValue SetCC = Ext.getOperand(0);
13260 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13263 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13264 if (CC != X86::COND_E && CC != X86::COND_NE)
13267 SDValue Cmp = SetCC.getOperand(1);
13268 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13269 !X86::isZeroNode(Cmp.getOperand(1)) ||
13270 !Cmp.getOperand(0).getValueType().isInteger())
13273 SDValue CmpOp0 = Cmp.getOperand(0);
13274 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13275 DAG.getConstant(1, CmpOp0.getValueType()));
13277 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13278 if (CC == X86::COND_NE)
13279 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13280 DL, OtherVal.getValueType(), OtherVal,
13281 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13282 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13283 DL, OtherVal.getValueType(), OtherVal,
13284 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13287 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13288 SDValue Op0 = N->getOperand(0);
13289 SDValue Op1 = N->getOperand(1);
13291 // X86 can't encode an immediate LHS of a sub. See if we can push the
13292 // negation into a preceding instruction.
13293 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13294 uint64_t Op0C = C->getSExtValue();
13296 // If the RHS of the sub is a XOR with one use and a constant, invert the
13297 // immediate. Then add one to the LHS of the sub so we can turn
13298 // X-Y -> X+~Y+1, saving one register.
13299 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13300 isa<ConstantSDNode>(Op1.getOperand(1))) {
13301 uint64_t XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getSExtValue();
13302 EVT VT = Op0.getValueType();
13303 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13305 DAG.getConstant(~XorC, VT));
13306 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13307 DAG.getConstant(Op0C+1, VT));
13311 return OptimizeConditionalInDecrement(N, DAG);
13314 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13315 DAGCombinerInfo &DCI) const {
13316 SelectionDAG &DAG = DCI.DAG;
13317 switch (N->getOpcode()) {
13319 case ISD::EXTRACT_VECTOR_ELT:
13320 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13321 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13322 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13323 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13324 case ISD::SUB: return PerformSubCombine(N, DAG);
13325 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13326 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13329 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13330 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13331 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13332 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13333 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13335 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13336 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13337 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13338 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13339 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13340 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13341 case X86ISD::SHUFPS: // Handle all target specific shuffles
13342 case X86ISD::SHUFPD:
13343 case X86ISD::PALIGN:
13344 case X86ISD::PUNPCKHBW:
13345 case X86ISD::PUNPCKHWD:
13346 case X86ISD::PUNPCKHDQ:
13347 case X86ISD::PUNPCKHQDQ:
13348 case X86ISD::UNPCKHPS:
13349 case X86ISD::UNPCKHPD:
13350 case X86ISD::VUNPCKHPSY:
13351 case X86ISD::VUNPCKHPDY:
13352 case X86ISD::PUNPCKLBW:
13353 case X86ISD::PUNPCKLWD:
13354 case X86ISD::PUNPCKLDQ:
13355 case X86ISD::PUNPCKLQDQ:
13356 case X86ISD::UNPCKLPS:
13357 case X86ISD::UNPCKLPD:
13358 case X86ISD::VUNPCKLPSY:
13359 case X86ISD::VUNPCKLPDY:
13360 case X86ISD::MOVHLPS:
13361 case X86ISD::MOVLHPS:
13362 case X86ISD::PSHUFD:
13363 case X86ISD::PSHUFHW:
13364 case X86ISD::PSHUFLW:
13365 case X86ISD::MOVSS:
13366 case X86ISD::MOVSD:
13367 case X86ISD::VPERMILPS:
13368 case X86ISD::VPERMILPSY:
13369 case X86ISD::VPERMILPD:
13370 case X86ISD::VPERMILPDY:
13371 case X86ISD::VPERM2F128:
13372 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13378 /// isTypeDesirableForOp - Return true if the target has native support for
13379 /// the specified value type and it is 'desirable' to use the type for the
13380 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13381 /// instruction encodings are longer and some i16 instructions are slow.
13382 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13383 if (!isTypeLegal(VT))
13385 if (VT != MVT::i16)
13392 case ISD::SIGN_EXTEND:
13393 case ISD::ZERO_EXTEND:
13394 case ISD::ANY_EXTEND:
13407 /// IsDesirableToPromoteOp - This method query the target whether it is
13408 /// beneficial for dag combiner to promote the specified node. If true, it
13409 /// should return the desired promotion type by reference.
13410 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13411 EVT VT = Op.getValueType();
13412 if (VT != MVT::i16)
13415 bool Promote = false;
13416 bool Commute = false;
13417 switch (Op.getOpcode()) {
13420 LoadSDNode *LD = cast<LoadSDNode>(Op);
13421 // If the non-extending load has a single use and it's not live out, then it
13422 // might be folded.
13423 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13424 Op.hasOneUse()*/) {
13425 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13426 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13427 // The only case where we'd want to promote LOAD (rather then it being
13428 // promoted as an operand is when it's only use is liveout.
13429 if (UI->getOpcode() != ISD::CopyToReg)
13436 case ISD::SIGN_EXTEND:
13437 case ISD::ZERO_EXTEND:
13438 case ISD::ANY_EXTEND:
13443 SDValue N0 = Op.getOperand(0);
13444 // Look out for (store (shl (load), x)).
13445 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13458 SDValue N0 = Op.getOperand(0);
13459 SDValue N1 = Op.getOperand(1);
13460 if (!Commute && MayFoldLoad(N1))
13462 // Avoid disabling potential load folding opportunities.
13463 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
13465 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
13475 //===----------------------------------------------------------------------===//
13476 // X86 Inline Assembly Support
13477 //===----------------------------------------------------------------------===//
13479 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
13480 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13482 std::string AsmStr = IA->getAsmString();
13484 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
13485 SmallVector<StringRef, 4> AsmPieces;
13486 SplitString(AsmStr, AsmPieces, ";\n");
13488 switch (AsmPieces.size()) {
13489 default: return false;
13491 AsmStr = AsmPieces[0];
13493 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
13495 // FIXME: this should verify that we are targeting a 486 or better. If not,
13496 // we will turn this bswap into something that will be lowered to logical ops
13497 // instead of emitting the bswap asm. For now, we don't support 486 or lower
13498 // so don't worry about this.
13500 if (AsmPieces.size() == 2 &&
13501 (AsmPieces[0] == "bswap" ||
13502 AsmPieces[0] == "bswapq" ||
13503 AsmPieces[0] == "bswapl") &&
13504 (AsmPieces[1] == "$0" ||
13505 AsmPieces[1] == "${0:q}")) {
13506 // No need to check constraints, nothing other than the equivalent of
13507 // "=r,0" would be valid here.
13508 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13509 if (!Ty || Ty->getBitWidth() % 16 != 0)
13511 return IntrinsicLowering::LowerToByteSwap(CI);
13513 // rorw $$8, ${0:w} --> llvm.bswap.i16
13514 if (CI->getType()->isIntegerTy(16) &&
13515 AsmPieces.size() == 3 &&
13516 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
13517 AsmPieces[1] == "$$8," &&
13518 AsmPieces[2] == "${0:w}" &&
13519 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13521 const std::string &ConstraintsStr = IA->getConstraintString();
13522 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13523 std::sort(AsmPieces.begin(), AsmPieces.end());
13524 if (AsmPieces.size() == 4 &&
13525 AsmPieces[0] == "~{cc}" &&
13526 AsmPieces[1] == "~{dirflag}" &&
13527 AsmPieces[2] == "~{flags}" &&
13528 AsmPieces[3] == "~{fpsr}") {
13529 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13530 if (!Ty || Ty->getBitWidth() % 16 != 0)
13532 return IntrinsicLowering::LowerToByteSwap(CI);
13537 if (CI->getType()->isIntegerTy(32) &&
13538 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13539 SmallVector<StringRef, 4> Words;
13540 SplitString(AsmPieces[0], Words, " \t,");
13541 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13542 Words[2] == "${0:w}") {
13544 SplitString(AsmPieces[1], Words, " \t,");
13545 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
13546 Words[2] == "$0") {
13548 SplitString(AsmPieces[2], Words, " \t,");
13549 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13550 Words[2] == "${0:w}") {
13552 const std::string &ConstraintsStr = IA->getConstraintString();
13553 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13554 std::sort(AsmPieces.begin(), AsmPieces.end());
13555 if (AsmPieces.size() == 4 &&
13556 AsmPieces[0] == "~{cc}" &&
13557 AsmPieces[1] == "~{dirflag}" &&
13558 AsmPieces[2] == "~{flags}" &&
13559 AsmPieces[3] == "~{fpsr}") {
13560 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13561 if (!Ty || Ty->getBitWidth() % 16 != 0)
13563 return IntrinsicLowering::LowerToByteSwap(CI);
13570 if (CI->getType()->isIntegerTy(64)) {
13571 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
13572 if (Constraints.size() >= 2 &&
13573 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
13574 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
13575 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
13576 SmallVector<StringRef, 4> Words;
13577 SplitString(AsmPieces[0], Words, " \t");
13578 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
13580 SplitString(AsmPieces[1], Words, " \t");
13581 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
13583 SplitString(AsmPieces[2], Words, " \t,");
13584 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
13585 Words[2] == "%edx") {
13586 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13587 if (!Ty || Ty->getBitWidth() % 16 != 0)
13589 return IntrinsicLowering::LowerToByteSwap(CI);
13602 /// getConstraintType - Given a constraint letter, return the type of
13603 /// constraint it is for this target.
13604 X86TargetLowering::ConstraintType
13605 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
13606 if (Constraint.size() == 1) {
13607 switch (Constraint[0]) {
13618 return C_RegisterClass;
13642 return TargetLowering::getConstraintType(Constraint);
13645 /// Examine constraint type and operand type and determine a weight value.
13646 /// This object must already have been set up with the operand type
13647 /// and the current alternative constraint selected.
13648 TargetLowering::ConstraintWeight
13649 X86TargetLowering::getSingleConstraintMatchWeight(
13650 AsmOperandInfo &info, const char *constraint) const {
13651 ConstraintWeight weight = CW_Invalid;
13652 Value *CallOperandVal = info.CallOperandVal;
13653 // If we don't have a value, we can't do a match,
13654 // but allow it at the lowest weight.
13655 if (CallOperandVal == NULL)
13657 Type *type = CallOperandVal->getType();
13658 // Look at the constraint type.
13659 switch (*constraint) {
13661 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
13672 if (CallOperandVal->getType()->isIntegerTy())
13673 weight = CW_SpecificReg;
13678 if (type->isFloatingPointTy())
13679 weight = CW_SpecificReg;
13682 if (type->isX86_MMXTy() && Subtarget->hasMMX())
13683 weight = CW_SpecificReg;
13687 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
13688 weight = CW_Register;
13691 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
13692 if (C->getZExtValue() <= 31)
13693 weight = CW_Constant;
13697 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13698 if (C->getZExtValue() <= 63)
13699 weight = CW_Constant;
13703 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13704 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
13705 weight = CW_Constant;
13709 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13710 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
13711 weight = CW_Constant;
13715 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13716 if (C->getZExtValue() <= 3)
13717 weight = CW_Constant;
13721 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13722 if (C->getZExtValue() <= 0xff)
13723 weight = CW_Constant;
13728 if (dyn_cast<ConstantFP>(CallOperandVal)) {
13729 weight = CW_Constant;
13733 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13734 if ((C->getSExtValue() >= -0x80000000LL) &&
13735 (C->getSExtValue() <= 0x7fffffffLL))
13736 weight = CW_Constant;
13740 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13741 if (C->getZExtValue() <= 0xffffffff)
13742 weight = CW_Constant;
13749 /// LowerXConstraint - try to replace an X constraint, which matches anything,
13750 /// with another that has more specific requirements based on the type of the
13751 /// corresponding operand.
13752 const char *X86TargetLowering::
13753 LowerXConstraint(EVT ConstraintVT) const {
13754 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
13755 // 'f' like normal targets.
13756 if (ConstraintVT.isFloatingPoint()) {
13757 if (Subtarget->hasXMMInt())
13759 if (Subtarget->hasXMM())
13763 return TargetLowering::LowerXConstraint(ConstraintVT);
13766 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
13767 /// vector. If it is invalid, don't add anything to Ops.
13768 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
13769 std::string &Constraint,
13770 std::vector<SDValue>&Ops,
13771 SelectionDAG &DAG) const {
13772 SDValue Result(0, 0);
13774 // Only support length 1 constraints for now.
13775 if (Constraint.length() > 1) return;
13777 char ConstraintLetter = Constraint[0];
13778 switch (ConstraintLetter) {
13781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13782 if (C->getZExtValue() <= 31) {
13783 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13790 if (C->getZExtValue() <= 63) {
13791 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13798 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
13799 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13805 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13806 if (C->getZExtValue() <= 255) {
13807 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13813 // 32-bit signed value
13814 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13815 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13816 C->getSExtValue())) {
13817 // Widen to 64 bits here to get it sign extended.
13818 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
13821 // FIXME gcc accepts some relocatable values here too, but only in certain
13822 // memory models; it's complicated.
13827 // 32-bit unsigned value
13828 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13829 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13830 C->getZExtValue())) {
13831 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13835 // FIXME gcc accepts some relocatable values here too, but only in certain
13836 // memory models; it's complicated.
13840 // Literal immediates are always ok.
13841 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
13842 // Widen to 64 bits here to get it sign extended.
13843 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
13847 // In any sort of PIC mode addresses need to be computed at runtime by
13848 // adding in a register or some sort of table lookup. These can't
13849 // be used as immediates.
13850 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
13853 // If we are in non-pic codegen mode, we allow the address of a global (with
13854 // an optional displacement) to be used with 'i'.
13855 GlobalAddressSDNode *GA = 0;
13856 int64_t Offset = 0;
13858 // Match either (GA), (GA+C), (GA+C1+C2), etc.
13860 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
13861 Offset += GA->getOffset();
13863 } else if (Op.getOpcode() == ISD::ADD) {
13864 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13865 Offset += C->getZExtValue();
13866 Op = Op.getOperand(0);
13869 } else if (Op.getOpcode() == ISD::SUB) {
13870 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13871 Offset += -C->getZExtValue();
13872 Op = Op.getOperand(0);
13877 // Otherwise, this isn't something we can handle, reject it.
13881 const GlobalValue *GV = GA->getGlobal();
13882 // If we require an extra load to get this address, as in PIC mode, we
13883 // can't accept it.
13884 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
13885 getTargetMachine())))
13888 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
13889 GA->getValueType(0), Offset);
13894 if (Result.getNode()) {
13895 Ops.push_back(Result);
13898 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
13901 std::pair<unsigned, const TargetRegisterClass*>
13902 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
13904 // First, see if this is a constraint that directly corresponds to an LLVM
13906 if (Constraint.size() == 1) {
13907 // GCC Constraint Letters
13908 switch (Constraint[0]) {
13910 // TODO: Slight differences here in allocation order and leaving
13911 // RIP in the class. Do they matter any more here than they do
13912 // in the normal allocation?
13913 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
13914 if (Subtarget->is64Bit()) {
13915 if (VT == MVT::i32 || VT == MVT::f32)
13916 return std::make_pair(0U, X86::GR32RegisterClass);
13917 else if (VT == MVT::i16)
13918 return std::make_pair(0U, X86::GR16RegisterClass);
13919 else if (VT == MVT::i8 || VT == MVT::i1)
13920 return std::make_pair(0U, X86::GR8RegisterClass);
13921 else if (VT == MVT::i64 || VT == MVT::f64)
13922 return std::make_pair(0U, X86::GR64RegisterClass);
13925 // 32-bit fallthrough
13926 case 'Q': // Q_REGS
13927 if (VT == MVT::i32 || VT == MVT::f32)
13928 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
13929 else if (VT == MVT::i16)
13930 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
13931 else if (VT == MVT::i8 || VT == MVT::i1)
13932 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
13933 else if (VT == MVT::i64)
13934 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
13936 case 'r': // GENERAL_REGS
13937 case 'l': // INDEX_REGS
13938 if (VT == MVT::i8 || VT == MVT::i1)
13939 return std::make_pair(0U, X86::GR8RegisterClass);
13940 if (VT == MVT::i16)
13941 return std::make_pair(0U, X86::GR16RegisterClass);
13942 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
13943 return std::make_pair(0U, X86::GR32RegisterClass);
13944 return std::make_pair(0U, X86::GR64RegisterClass);
13945 case 'R': // LEGACY_REGS
13946 if (VT == MVT::i8 || VT == MVT::i1)
13947 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
13948 if (VT == MVT::i16)
13949 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
13950 if (VT == MVT::i32 || !Subtarget->is64Bit())
13951 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
13952 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
13953 case 'f': // FP Stack registers.
13954 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
13955 // value to the correct fpstack register class.
13956 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
13957 return std::make_pair(0U, X86::RFP32RegisterClass);
13958 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
13959 return std::make_pair(0U, X86::RFP64RegisterClass);
13960 return std::make_pair(0U, X86::RFP80RegisterClass);
13961 case 'y': // MMX_REGS if MMX allowed.
13962 if (!Subtarget->hasMMX()) break;
13963 return std::make_pair(0U, X86::VR64RegisterClass);
13964 case 'Y': // SSE_REGS if SSE2 allowed
13965 if (!Subtarget->hasXMMInt()) break;
13967 case 'x': // SSE_REGS if SSE1 allowed
13968 if (!Subtarget->hasXMM()) break;
13970 switch (VT.getSimpleVT().SimpleTy) {
13972 // Scalar SSE types.
13975 return std::make_pair(0U, X86::FR32RegisterClass);
13978 return std::make_pair(0U, X86::FR64RegisterClass);
13986 return std::make_pair(0U, X86::VR128RegisterClass);
13992 // Use the default implementation in TargetLowering to convert the register
13993 // constraint into a member of a register class.
13994 std::pair<unsigned, const TargetRegisterClass*> Res;
13995 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
13997 // Not found as a standard register?
13998 if (Res.second == 0) {
13999 // Map st(0) -> st(7) -> ST0
14000 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14001 tolower(Constraint[1]) == 's' &&
14002 tolower(Constraint[2]) == 't' &&
14003 Constraint[3] == '(' &&
14004 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14005 Constraint[5] == ')' &&
14006 Constraint[6] == '}') {
14008 Res.first = X86::ST0+Constraint[4]-'0';
14009 Res.second = X86::RFP80RegisterClass;
14013 // GCC allows "st(0)" to be called just plain "st".
14014 if (StringRef("{st}").equals_lower(Constraint)) {
14015 Res.first = X86::ST0;
14016 Res.second = X86::RFP80RegisterClass;
14021 if (StringRef("{flags}").equals_lower(Constraint)) {
14022 Res.first = X86::EFLAGS;
14023 Res.second = X86::CCRRegisterClass;
14027 // 'A' means EAX + EDX.
14028 if (Constraint == "A") {
14029 Res.first = X86::EAX;
14030 Res.second = X86::GR32_ADRegisterClass;
14036 // Otherwise, check to see if this is a register class of the wrong value
14037 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14038 // turn into {ax},{dx}.
14039 if (Res.second->hasType(VT))
14040 return Res; // Correct type already, nothing to do.
14042 // All of the single-register GCC register classes map their values onto
14043 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14044 // really want an 8-bit or 32-bit register, map to the appropriate register
14045 // class and return the appropriate register.
14046 if (Res.second == X86::GR16RegisterClass) {
14047 if (VT == MVT::i8) {
14048 unsigned DestReg = 0;
14049 switch (Res.first) {
14051 case X86::AX: DestReg = X86::AL; break;
14052 case X86::DX: DestReg = X86::DL; break;
14053 case X86::CX: DestReg = X86::CL; break;
14054 case X86::BX: DestReg = X86::BL; break;
14057 Res.first = DestReg;
14058 Res.second = X86::GR8RegisterClass;
14060 } else if (VT == MVT::i32) {
14061 unsigned DestReg = 0;
14062 switch (Res.first) {
14064 case X86::AX: DestReg = X86::EAX; break;
14065 case X86::DX: DestReg = X86::EDX; break;
14066 case X86::CX: DestReg = X86::ECX; break;
14067 case X86::BX: DestReg = X86::EBX; break;
14068 case X86::SI: DestReg = X86::ESI; break;
14069 case X86::DI: DestReg = X86::EDI; break;
14070 case X86::BP: DestReg = X86::EBP; break;
14071 case X86::SP: DestReg = X86::ESP; break;
14074 Res.first = DestReg;
14075 Res.second = X86::GR32RegisterClass;
14077 } else if (VT == MVT::i64) {
14078 unsigned DestReg = 0;
14079 switch (Res.first) {
14081 case X86::AX: DestReg = X86::RAX; break;
14082 case X86::DX: DestReg = X86::RDX; break;
14083 case X86::CX: DestReg = X86::RCX; break;
14084 case X86::BX: DestReg = X86::RBX; break;
14085 case X86::SI: DestReg = X86::RSI; break;
14086 case X86::DI: DestReg = X86::RDI; break;
14087 case X86::BP: DestReg = X86::RBP; break;
14088 case X86::SP: DestReg = X86::RSP; break;
14091 Res.first = DestReg;
14092 Res.second = X86::GR64RegisterClass;
14095 } else if (Res.second == X86::FR32RegisterClass ||
14096 Res.second == X86::FR64RegisterClass ||
14097 Res.second == X86::VR128RegisterClass) {
14098 // Handle references to XMM physical registers that got mapped into the
14099 // wrong class. This can happen with constraints like {xmm0} where the
14100 // target independent register mapper will just pick the first match it can
14101 // find, ignoring the required type.
14102 if (VT == MVT::f32)
14103 Res.second = X86::FR32RegisterClass;
14104 else if (VT == MVT::f64)
14105 Res.second = X86::FR64RegisterClass;
14106 else if (X86::VR128RegisterClass->hasType(VT))
14107 Res.second = X86::VR128RegisterClass;