1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!TM.Options.UseSoftFloat) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!TM.Options.UseSoftFloat) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!TM.Options.UseSoftFloat) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!TM.Options.UseSoftFloat) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!TM.Options.UseSoftFloat) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
752 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
753 // with -msoft-float, disable use of MMX as well.
754 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
755 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
756 // No operations on x86mmx supported, everything uses intrinsics.
759 // MMX-sized vectors (other than x86mmx) are expected to be expanded
760 // into smaller operations.
761 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
762 setOperationAction(ISD::MULHS, MMXTy, Expand);
763 setOperationAction(ISD::AND, MMXTy, Expand);
764 setOperationAction(ISD::OR, MMXTy, Expand);
765 setOperationAction(ISD::XOR, MMXTy, Expand);
766 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
767 setOperationAction(ISD::SELECT, MMXTy, Expand);
768 setOperationAction(ISD::BITCAST, MMXTy, Expand);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
772 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
773 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
775 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
776 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
777 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
778 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
780 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
781 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
782 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
783 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
785 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
787 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
788 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
791 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
792 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
794 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
795 // registers cannot be used even for integer operations.
796 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
797 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
798 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
799 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
801 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
802 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
803 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
804 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
805 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
806 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
807 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
808 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
809 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
810 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
811 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
812 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
813 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
814 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
815 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
816 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
817 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
818 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
819 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
820 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
821 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
822 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
824 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
825 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
826 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
827 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
831 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
835 // Only provide customized ctpop vector bit twiddling for vector types we
836 // know to perform better than using the popcnt instructions on each vector
837 // element. If popcnt isn't supported, always provide the custom version.
838 if (!Subtarget->hasPOPCNT()) {
839 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
843 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
844 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
845 MVT VT = (MVT::SimpleValueType)i;
846 // Do not attempt to custom lower non-power-of-2 vectors
847 if (!isPowerOf2_32(VT.getVectorNumElements()))
849 // Do not attempt to custom lower non-128-bit vectors
850 if (!VT.is128BitVector())
852 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
853 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
854 setOperationAction(ISD::VSELECT, VT, Custom);
855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
858 // We support custom legalizing of sext and anyext loads for specific
859 // memory vector types which we can load as a scalar (or sequence of
860 // scalars) and extend in-register to a legal 128-bit vector type. For sext
861 // loads these must work with a single scalar load.
862 for (MVT VT : MVT::integer_vector_valuetypes()) {
863 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
866 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
874 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
876 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
878 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
881 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
883 if (Subtarget->is64Bit()) {
884 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
888 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
889 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
890 MVT VT = (MVT::SimpleValueType)i;
892 // Do not attempt to promote non-128-bit vectors
893 if (!VT.is128BitVector())
896 setOperationAction(ISD::AND, VT, Promote);
897 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
898 setOperationAction(ISD::OR, VT, Promote);
899 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
900 setOperationAction(ISD::XOR, VT, Promote);
901 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
902 setOperationAction(ISD::LOAD, VT, Promote);
903 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
904 setOperationAction(ISD::SELECT, VT, Promote);
905 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
908 // Custom lower v2i64 and v2f64 selects.
909 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
910 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
911 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
912 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
914 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
915 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
917 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
918 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
919 // As there is no 64-bit GPR available, we need build a special custom
920 // sequence to convert from v2i32 to v2f32.
921 if (!Subtarget->is64Bit())
922 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
924 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
925 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
927 for (MVT VT : MVT::fp_vector_valuetypes())
928 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
930 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
931 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
932 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
935 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
936 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
937 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
938 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
939 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
940 setOperationAction(ISD::FRINT, RoundedTy, Legal);
941 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
944 // FIXME: Do we need to handle scalar-to-vector here?
945 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
947 // We directly match byte blends in the backend as they match the VSELECT
949 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
951 // SSE41 brings specific instructions for doing vector sign extend even in
952 // cases where we don't have SRA.
953 for (MVT VT : MVT::integer_vector_valuetypes()) {
954 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
955 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
956 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
959 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
960 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
961 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
962 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
967 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
968 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
969 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
974 // i8 and i16 vectors are custom because the source register and source
975 // source memory operand types are not the same width. f32 vectors are
976 // custom since the immediate controlling the insert encodes additional
978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
988 // FIXME: these should be Legal, but that's only for the case where
989 // the index is constant. For now custom expand to deal with that.
990 if (Subtarget->is64Bit()) {
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
996 if (Subtarget->hasSSE2()) {
997 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
998 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1000 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1001 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1003 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1004 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1006 // In the customized shift lowering, the legal cases in AVX2 will be
1008 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1009 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1011 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1012 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1014 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1017 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1018 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1019 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1020 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1021 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1022 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1023 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1025 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1026 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1027 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1029 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1032 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1033 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1034 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1035 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1036 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1040 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1043 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1044 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1045 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1046 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1047 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1048 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1049 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1053 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1055 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1056 // even though v8i16 is a legal type.
1057 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1058 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1061 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1063 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1065 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1066 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1068 for (MVT VT : MVT::fp_vector_valuetypes())
1069 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1071 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1072 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1074 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1075 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1077 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1078 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1080 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1081 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1083 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1085 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1086 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1087 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1089 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1090 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1091 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1092 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1093 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1094 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1095 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1098 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1099 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1100 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1102 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1103 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1104 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1105 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FMA, MVT::f32, Legal);
1108 setOperationAction(ISD::FMA, MVT::f64, Legal);
1111 if (Subtarget->hasInt256()) {
1112 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1113 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1114 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1115 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1117 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1118 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1119 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1120 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1122 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1123 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1124 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1125 // Don't lower v32i8 because there is no 128-bit byte mul
1127 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1128 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1129 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1130 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1132 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1133 // when we have a 256bit-wide blend with immediate.
1134 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1136 // Only provide customized ctpop vector bit twiddling for vector types we
1137 // know to perform better than using the popcnt instructions on each
1138 // vector element. If popcnt isn't supported, always provide the custom
1140 if (!Subtarget->hasPOPCNT())
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 // Custom CTPOP always performs better on natively supported v8i32
1144 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1146 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1147 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1148 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1154 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1155 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1161 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1174 // Don't lower v32i8 because there is no 128-bit byte mul
1177 // In the customized shift lowering, the legal cases in AVX2 will be
1179 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1180 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1182 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1185 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1187 // Custom lower several nodes for 256-bit types.
1188 for (MVT VT : MVT::vector_valuetypes()) {
1189 if (VT.getScalarSizeInBits() >= 32) {
1190 setOperationAction(ISD::MLOAD, VT, Legal);
1191 setOperationAction(ISD::MSTORE, VT, Legal);
1193 // Extract subvector is special because the value type
1194 // (result) is 128-bit but the source is 256-bit wide.
1195 if (VT.is128BitVector()) {
1196 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1198 // Do not attempt to custom lower other non-256-bit vectors
1199 if (!VT.is256BitVector())
1202 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1203 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1204 setOperationAction(ISD::VSELECT, VT, Custom);
1205 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1206 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1207 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1208 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1209 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1212 if (Subtarget->hasInt256())
1213 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1216 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1217 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1218 MVT VT = (MVT::SimpleValueType)i;
1220 // Do not attempt to promote non-256-bit vectors
1221 if (!VT.is256BitVector())
1224 setOperationAction(ISD::AND, VT, Promote);
1225 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1226 setOperationAction(ISD::OR, VT, Promote);
1227 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1228 setOperationAction(ISD::XOR, VT, Promote);
1229 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1230 setOperationAction(ISD::LOAD, VT, Promote);
1231 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1232 setOperationAction(ISD::SELECT, VT, Promote);
1233 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1237 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1238 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1239 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1240 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1243 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1244 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1245 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1247 for (MVT VT : MVT::fp_vector_valuetypes())
1248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1250 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1251 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1252 setOperationAction(ISD::XOR, MVT::i1, Legal);
1253 setOperationAction(ISD::OR, MVT::i1, Legal);
1254 setOperationAction(ISD::AND, MVT::i1, Legal);
1255 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1256 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1257 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1258 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1259 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1261 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1262 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1263 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1264 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1265 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1266 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1268 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1269 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1270 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1271 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1272 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1273 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1274 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1275 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1277 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1278 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1279 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1280 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1281 if (Subtarget->is64Bit()) {
1282 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1283 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1284 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1285 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1287 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1288 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1289 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1290 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1291 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1292 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1293 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1294 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1295 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1296 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1297 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1298 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1299 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1300 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1302 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1303 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1304 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1305 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1306 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1307 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1308 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1309 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1310 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1311 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1312 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1313 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1314 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1316 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1318 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1320 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1322 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1327 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1328 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1329 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1330 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1331 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1333 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1334 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1339 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1340 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1341 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1342 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1343 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1344 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1345 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1346 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1348 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1349 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1351 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1352 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1354 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1356 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1357 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1359 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1360 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1362 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1363 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1365 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1366 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1367 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1368 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1369 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1370 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1372 if (Subtarget->hasCDI()) {
1373 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1374 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1377 // Custom lower several nodes.
1378 for (MVT VT : MVT::vector_valuetypes()) {
1379 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1380 // Extract subvector is special because the value type
1381 // (result) is 256/128-bit but the source is 512-bit wide.
1382 if (VT.is128BitVector() || VT.is256BitVector()) {
1383 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1385 if (VT.getVectorElementType() == MVT::i1)
1386 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1388 // Do not attempt to custom lower other non-512-bit vectors
1389 if (!VT.is512BitVector())
1392 if ( EltSize >= 32) {
1393 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1394 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1395 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1396 setOperationAction(ISD::VSELECT, VT, Legal);
1397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1398 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1399 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1400 setOperationAction(ISD::MLOAD, VT, Legal);
1401 setOperationAction(ISD::MSTORE, VT, Legal);
1404 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1405 MVT VT = (MVT::SimpleValueType)i;
1407 // Do not attempt to promote non-512-bit vectors.
1408 if (!VT.is512BitVector())
1411 setOperationAction(ISD::SELECT, VT, Promote);
1412 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1416 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1417 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1418 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1420 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1421 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1423 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1424 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1425 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1426 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1427 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1428 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1429 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1430 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1431 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1432 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1433 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1434 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1435 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1437 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1438 const MVT VT = (MVT::SimpleValueType)i;
1440 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1442 // Do not attempt to promote non-512-bit vectors.
1443 if (!VT.is512BitVector())
1447 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1448 setOperationAction(ISD::VSELECT, VT, Legal);
1453 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1454 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1455 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1457 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1458 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1461 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1462 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1464 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1465 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1466 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1467 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1468 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1469 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1472 // We want to custom lower some of our intrinsics.
1473 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1474 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1475 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1476 if (!Subtarget->is64Bit())
1477 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1479 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1480 // handle type legalization for these operations here.
1482 // FIXME: We really should do custom legalization for addition and
1483 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1484 // than generic legalization for 64-bit multiplication-with-overflow, though.
1485 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1486 // Add/Sub/Mul with overflow operations are custom lowered.
1488 setOperationAction(ISD::SADDO, VT, Custom);
1489 setOperationAction(ISD::UADDO, VT, Custom);
1490 setOperationAction(ISD::SSUBO, VT, Custom);
1491 setOperationAction(ISD::USUBO, VT, Custom);
1492 setOperationAction(ISD::SMULO, VT, Custom);
1493 setOperationAction(ISD::UMULO, VT, Custom);
1497 if (!Subtarget->is64Bit()) {
1498 // These libcalls are not available in 32-bit.
1499 setLibcallName(RTLIB::SHL_I128, nullptr);
1500 setLibcallName(RTLIB::SRL_I128, nullptr);
1501 setLibcallName(RTLIB::SRA_I128, nullptr);
1504 // Combine sin / cos into one node or libcall if possible.
1505 if (Subtarget->hasSinCos()) {
1506 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1507 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1508 if (Subtarget->isTargetDarwin()) {
1509 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1510 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1511 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1512 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1516 if (Subtarget->isTargetWin64()) {
1517 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1518 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1519 setOperationAction(ISD::SREM, MVT::i128, Custom);
1520 setOperationAction(ISD::UREM, MVT::i128, Custom);
1521 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1522 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1525 // We have target-specific dag combine patterns for the following nodes:
1526 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1527 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1528 setTargetDAGCombine(ISD::BITCAST);
1529 setTargetDAGCombine(ISD::VSELECT);
1530 setTargetDAGCombine(ISD::SELECT);
1531 setTargetDAGCombine(ISD::SHL);
1532 setTargetDAGCombine(ISD::SRA);
1533 setTargetDAGCombine(ISD::SRL);
1534 setTargetDAGCombine(ISD::OR);
1535 setTargetDAGCombine(ISD::AND);
1536 setTargetDAGCombine(ISD::ADD);
1537 setTargetDAGCombine(ISD::FADD);
1538 setTargetDAGCombine(ISD::FSUB);
1539 setTargetDAGCombine(ISD::FMA);
1540 setTargetDAGCombine(ISD::SUB);
1541 setTargetDAGCombine(ISD::LOAD);
1542 setTargetDAGCombine(ISD::MLOAD);
1543 setTargetDAGCombine(ISD::STORE);
1544 setTargetDAGCombine(ISD::MSTORE);
1545 setTargetDAGCombine(ISD::ZERO_EXTEND);
1546 setTargetDAGCombine(ISD::ANY_EXTEND);
1547 setTargetDAGCombine(ISD::SIGN_EXTEND);
1548 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1549 setTargetDAGCombine(ISD::TRUNCATE);
1550 setTargetDAGCombine(ISD::SINT_TO_FP);
1551 setTargetDAGCombine(ISD::SETCC);
1552 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1553 setTargetDAGCombine(ISD::BUILD_VECTOR);
1554 setTargetDAGCombine(ISD::MUL);
1555 setTargetDAGCombine(ISD::XOR);
1557 computeRegisterProperties(Subtarget->getRegisterInfo());
1559 // On Darwin, -Os means optimize for size without hurting performance,
1560 // do not reduce the limit.
1561 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1562 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1563 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1564 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1565 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1566 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1567 setPrefLoopAlignment(4); // 2^4 bytes.
1569 // Predictable cmov don't hurt on atom because it's in-order.
1570 PredictableSelectIsExpensive = !Subtarget->isAtom();
1571 EnableExtLdPromotion = true;
1572 setPrefFunctionAlignment(4); // 2^4 bytes.
1574 verifyIntrinsicTables();
1577 // This has so far only been implemented for 64-bit MachO.
1578 bool X86TargetLowering::useLoadStackGuardNode() const {
1579 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1582 TargetLoweringBase::LegalizeTypeAction
1583 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1584 if (ExperimentalVectorWideningLegalization &&
1585 VT.getVectorNumElements() != 1 &&
1586 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1587 return TypeWidenVector;
1589 return TargetLoweringBase::getPreferredVectorAction(VT);
1592 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1594 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1596 const unsigned NumElts = VT.getVectorNumElements();
1597 const EVT EltVT = VT.getVectorElementType();
1598 if (VT.is512BitVector()) {
1599 if (Subtarget->hasAVX512())
1600 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1601 EltVT == MVT::f32 || EltVT == MVT::f64)
1603 case 8: return MVT::v8i1;
1604 case 16: return MVT::v16i1;
1606 if (Subtarget->hasBWI())
1607 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1609 case 32: return MVT::v32i1;
1610 case 64: return MVT::v64i1;
1614 if (VT.is256BitVector() || VT.is128BitVector()) {
1615 if (Subtarget->hasVLX())
1616 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1617 EltVT == MVT::f32 || EltVT == MVT::f64)
1619 case 2: return MVT::v2i1;
1620 case 4: return MVT::v4i1;
1621 case 8: return MVT::v8i1;
1623 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1624 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1626 case 8: return MVT::v8i1;
1627 case 16: return MVT::v16i1;
1628 case 32: return MVT::v32i1;
1632 return VT.changeVectorElementTypeToInteger();
1635 /// Helper for getByValTypeAlignment to determine
1636 /// the desired ByVal argument alignment.
1637 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1640 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1641 if (VTy->getBitWidth() == 128)
1643 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1644 unsigned EltAlign = 0;
1645 getMaxByValAlign(ATy->getElementType(), EltAlign);
1646 if (EltAlign > MaxAlign)
1647 MaxAlign = EltAlign;
1648 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1649 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1650 unsigned EltAlign = 0;
1651 getMaxByValAlign(STy->getElementType(i), EltAlign);
1652 if (EltAlign > MaxAlign)
1653 MaxAlign = EltAlign;
1660 /// Return the desired alignment for ByVal aggregate
1661 /// function arguments in the caller parameter area. For X86, aggregates
1662 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1663 /// are at 4-byte boundaries.
1664 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1665 if (Subtarget->is64Bit()) {
1666 // Max of 8 and alignment of type.
1667 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1674 if (Subtarget->hasSSE1())
1675 getMaxByValAlign(Ty, Align);
1679 /// Returns the target specific optimal type for load
1680 /// and store operations as a result of memset, memcpy, and memmove
1681 /// lowering. If DstAlign is zero that means it's safe to destination
1682 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1683 /// means there isn't a need to check it against alignment requirement,
1684 /// probably because the source does not need to be loaded. If 'IsMemset' is
1685 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1686 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1687 /// source is constant so it does not need to be loaded.
1688 /// It returns EVT::Other if the type should be determined using generic
1689 /// target-independent logic.
1691 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1692 unsigned DstAlign, unsigned SrcAlign,
1693 bool IsMemset, bool ZeroMemset,
1695 MachineFunction &MF) const {
1696 const Function *F = MF.getFunction();
1697 if ((!IsMemset || ZeroMemset) &&
1698 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1700 (Subtarget->isUnalignedMemAccessFast() ||
1701 ((DstAlign == 0 || DstAlign >= 16) &&
1702 (SrcAlign == 0 || SrcAlign >= 16)))) {
1704 if (Subtarget->hasInt256())
1706 if (Subtarget->hasFp256())
1709 if (Subtarget->hasSSE2())
1711 if (Subtarget->hasSSE1())
1713 } else if (!MemcpyStrSrc && Size >= 8 &&
1714 !Subtarget->is64Bit() &&
1715 Subtarget->hasSSE2()) {
1716 // Do not use f64 to lower memcpy if source is string constant. It's
1717 // better to use i32 to avoid the loads.
1721 if (Subtarget->is64Bit() && Size >= 8)
1726 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1728 return X86ScalarSSEf32;
1729 else if (VT == MVT::f64)
1730 return X86ScalarSSEf64;
1735 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1740 *Fast = Subtarget->isUnalignedMemAccessFast();
1744 /// Return the entry encoding for a jump table in the
1745 /// current function. The returned value is a member of the
1746 /// MachineJumpTableInfo::JTEntryKind enum.
1747 unsigned X86TargetLowering::getJumpTableEncoding() const {
1748 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1750 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1751 Subtarget->isPICStyleGOT())
1752 return MachineJumpTableInfo::EK_Custom32;
1754 // Otherwise, use the normal jump table encoding heuristics.
1755 return TargetLowering::getJumpTableEncoding();
1759 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1760 const MachineBasicBlock *MBB,
1761 unsigned uid,MCContext &Ctx) const{
1762 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1763 Subtarget->isPICStyleGOT());
1764 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1766 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1767 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1770 /// Returns relocation base for the given PIC jumptable.
1771 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1772 SelectionDAG &DAG) const {
1773 if (!Subtarget->is64Bit())
1774 // This doesn't have SDLoc associated with it, but is not really the
1775 // same as a Register.
1776 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1780 /// This returns the relocation base for the given PIC jumptable,
1781 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1782 const MCExpr *X86TargetLowering::
1783 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1784 MCContext &Ctx) const {
1785 // X86-64 uses RIP relative addressing based on the jump table label.
1786 if (Subtarget->isPICStyleRIPRel())
1787 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1789 // Otherwise, the reference is relative to the PIC base.
1790 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1793 std::pair<const TargetRegisterClass *, uint8_t>
1794 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1796 const TargetRegisterClass *RRC = nullptr;
1798 switch (VT.SimpleTy) {
1800 return TargetLowering::findRepresentativeClass(TRI, VT);
1801 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1802 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1805 RRC = &X86::VR64RegClass;
1807 case MVT::f32: case MVT::f64:
1808 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1809 case MVT::v4f32: case MVT::v2f64:
1810 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1812 RRC = &X86::VR128RegClass;
1815 return std::make_pair(RRC, Cost);
1818 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1819 unsigned &Offset) const {
1820 if (!Subtarget->isTargetLinux())
1823 if (Subtarget->is64Bit()) {
1824 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1826 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1838 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1839 unsigned DestAS) const {
1840 assert(SrcAS != DestAS && "Expected different address spaces!");
1842 return SrcAS < 256 && DestAS < 256;
1845 //===----------------------------------------------------------------------===//
1846 // Return Value Calling Convention Implementation
1847 //===----------------------------------------------------------------------===//
1849 #include "X86GenCallingConv.inc"
1852 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1853 MachineFunction &MF, bool isVarArg,
1854 const SmallVectorImpl<ISD::OutputArg> &Outs,
1855 LLVMContext &Context) const {
1856 SmallVector<CCValAssign, 16> RVLocs;
1857 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1858 return CCInfo.CheckReturn(Outs, RetCC_X86);
1861 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1862 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1867 X86TargetLowering::LowerReturn(SDValue Chain,
1868 CallingConv::ID CallConv, bool isVarArg,
1869 const SmallVectorImpl<ISD::OutputArg> &Outs,
1870 const SmallVectorImpl<SDValue> &OutVals,
1871 SDLoc dl, SelectionDAG &DAG) const {
1872 MachineFunction &MF = DAG.getMachineFunction();
1873 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1875 SmallVector<CCValAssign, 16> RVLocs;
1876 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1877 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1880 SmallVector<SDValue, 6> RetOps;
1881 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1882 // Operand #1 = Bytes To Pop
1883 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1886 // Copy the result values into the output registers.
1887 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1888 CCValAssign &VA = RVLocs[i];
1889 assert(VA.isRegLoc() && "Can only return in registers!");
1890 SDValue ValToCopy = OutVals[i];
1891 EVT ValVT = ValToCopy.getValueType();
1893 // Promote values to the appropriate types.
1894 if (VA.getLocInfo() == CCValAssign::SExt)
1895 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1896 else if (VA.getLocInfo() == CCValAssign::ZExt)
1897 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1898 else if (VA.getLocInfo() == CCValAssign::AExt)
1899 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1900 else if (VA.getLocInfo() == CCValAssign::BCvt)
1901 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1903 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1904 "Unexpected FP-extend for return value.");
1906 // If this is x86-64, and we disabled SSE, we can't return FP values,
1907 // or SSE or MMX vectors.
1908 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1909 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1910 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1911 report_fatal_error("SSE register return with SSE disabled");
1913 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1914 // llvm-gcc has never done it right and no one has noticed, so this
1915 // should be OK for now.
1916 if (ValVT == MVT::f64 &&
1917 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1918 report_fatal_error("SSE2 register return with SSE2 disabled");
1920 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1921 // the RET instruction and handled by the FP Stackifier.
1922 if (VA.getLocReg() == X86::FP0 ||
1923 VA.getLocReg() == X86::FP1) {
1924 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1925 // change the value to the FP stack register class.
1926 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1927 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1928 RetOps.push_back(ValToCopy);
1929 // Don't emit a copytoreg.
1933 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1934 // which is returned in RAX / RDX.
1935 if (Subtarget->is64Bit()) {
1936 if (ValVT == MVT::x86mmx) {
1937 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1938 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1939 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1941 // If we don't have SSE2 available, convert to v4f32 so the generated
1942 // register is legal.
1943 if (!Subtarget->hasSSE2())
1944 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1949 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1950 Flag = Chain.getValue(1);
1951 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1954 // The x86-64 ABIs require that for returning structs by value we copy
1955 // the sret argument into %rax/%eax (depending on ABI) for the return.
1956 // Win32 requires us to put the sret argument to %eax as well.
1957 // We saved the argument into a virtual register in the entry block,
1958 // so now we copy the value out and into %rax/%eax.
1960 // Checking Function.hasStructRetAttr() here is insufficient because the IR
1961 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
1962 // false, then an sret argument may be implicitly inserted in the SelDAG. In
1963 // either case FuncInfo->setSRetReturnReg() will have been called.
1964 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
1965 assert((Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) &&
1966 "No need for an sret register");
1967 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
1970 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1971 X86::RAX : X86::EAX;
1972 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1973 Flag = Chain.getValue(1);
1975 // RAX/EAX now acts like a return value.
1976 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1979 RetOps[0] = Chain; // Update chain.
1981 // Add the flag if we have it.
1983 RetOps.push_back(Flag);
1985 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1988 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1989 if (N->getNumValues() != 1)
1991 if (!N->hasNUsesOfValue(1, 0))
1994 SDValue TCChain = Chain;
1995 SDNode *Copy = *N->use_begin();
1996 if (Copy->getOpcode() == ISD::CopyToReg) {
1997 // If the copy has a glue operand, we conservatively assume it isn't safe to
1998 // perform a tail call.
1999 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2001 TCChain = Copy->getOperand(0);
2002 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2005 bool HasRet = false;
2006 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2008 if (UI->getOpcode() != X86ISD::RET_FLAG)
2010 // If we are returning more than one value, we can definitely
2011 // not make a tail call see PR19530
2012 if (UI->getNumOperands() > 4)
2014 if (UI->getNumOperands() == 4 &&
2015 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2028 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2029 ISD::NodeType ExtendKind) const {
2031 // TODO: Is this also valid on 32-bit?
2032 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2033 ReturnMVT = MVT::i8;
2035 ReturnMVT = MVT::i32;
2037 EVT MinVT = getRegisterType(Context, ReturnMVT);
2038 return VT.bitsLT(MinVT) ? MinVT : VT;
2041 /// Lower the result values of a call into the
2042 /// appropriate copies out of appropriate physical registers.
2045 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2046 CallingConv::ID CallConv, bool isVarArg,
2047 const SmallVectorImpl<ISD::InputArg> &Ins,
2048 SDLoc dl, SelectionDAG &DAG,
2049 SmallVectorImpl<SDValue> &InVals) const {
2051 // Assign locations to each value returned by this call.
2052 SmallVector<CCValAssign, 16> RVLocs;
2053 bool Is64Bit = Subtarget->is64Bit();
2054 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2056 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2058 // Copy all of the result registers out of their specified physreg.
2059 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2060 CCValAssign &VA = RVLocs[i];
2061 EVT CopyVT = VA.getValVT();
2063 // If this is x86-64, and we disabled SSE, we can't return FP values
2064 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2065 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2066 report_fatal_error("SSE register return with SSE disabled");
2069 // If we prefer to use the value in xmm registers, copy it out as f80 and
2070 // use a truncate to move it from fp stack reg to xmm reg.
2071 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2072 isScalarFPTypeInSSEReg(VA.getValVT()))
2075 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2076 CopyVT, InFlag).getValue(1);
2077 SDValue Val = Chain.getValue(0);
2079 if (CopyVT != VA.getValVT())
2080 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2081 // This truncation won't change the value.
2082 DAG.getIntPtrConstant(1));
2084 InFlag = Chain.getValue(2);
2085 InVals.push_back(Val);
2091 //===----------------------------------------------------------------------===//
2092 // C & StdCall & Fast Calling Convention implementation
2093 //===----------------------------------------------------------------------===//
2094 // StdCall calling convention seems to be standard for many Windows' API
2095 // routines and around. It differs from C calling convention just a little:
2096 // callee should clean up the stack, not caller. Symbols should be also
2097 // decorated in some fancy way :) It doesn't support any vector arguments.
2098 // For info on fast calling convention see Fast Calling Convention (tail call)
2099 // implementation LowerX86_32FastCCCallTo.
2101 /// CallIsStructReturn - Determines whether a call uses struct return
2103 enum StructReturnType {
2108 static StructReturnType
2109 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2111 return NotStructReturn;
2113 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2114 if (!Flags.isSRet())
2115 return NotStructReturn;
2116 if (Flags.isInReg())
2117 return RegStructReturn;
2118 return StackStructReturn;
2121 /// Determines whether a function uses struct return semantics.
2122 static StructReturnType
2123 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2125 return NotStructReturn;
2127 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2128 if (!Flags.isSRet())
2129 return NotStructReturn;
2130 if (Flags.isInReg())
2131 return RegStructReturn;
2132 return StackStructReturn;
2135 /// Make a copy of an aggregate at address specified by "Src" to address
2136 /// "Dst" with size and alignment information specified by the specific
2137 /// parameter attribute. The copy will be passed as a byval function parameter.
2139 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2140 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2142 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2144 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2145 /*isVolatile*/false, /*AlwaysInline=*/true,
2146 MachinePointerInfo(), MachinePointerInfo());
2149 /// Return true if the calling convention is one that
2150 /// supports tail call optimization.
2151 static bool IsTailCallConvention(CallingConv::ID CC) {
2152 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2153 CC == CallingConv::HiPE);
2156 /// \brief Return true if the calling convention is a C calling convention.
2157 static bool IsCCallConvention(CallingConv::ID CC) {
2158 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2159 CC == CallingConv::X86_64_SysV);
2162 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2163 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2167 CallingConv::ID CalleeCC = CS.getCallingConv();
2168 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2174 /// Return true if the function is being made into
2175 /// a tailcall target by changing its ABI.
2176 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2177 bool GuaranteedTailCallOpt) {
2178 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2182 X86TargetLowering::LowerMemArgument(SDValue Chain,
2183 CallingConv::ID CallConv,
2184 const SmallVectorImpl<ISD::InputArg> &Ins,
2185 SDLoc dl, SelectionDAG &DAG,
2186 const CCValAssign &VA,
2187 MachineFrameInfo *MFI,
2189 // Create the nodes corresponding to a load from this parameter slot.
2190 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2191 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2192 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2193 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2196 // If value is passed by pointer we have address passed instead of the value
2198 if (VA.getLocInfo() == CCValAssign::Indirect)
2199 ValVT = VA.getLocVT();
2201 ValVT = VA.getValVT();
2203 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2204 // changed with more analysis.
2205 // In case of tail call optimization mark all arguments mutable. Since they
2206 // could be overwritten by lowering of arguments in case of a tail call.
2207 if (Flags.isByVal()) {
2208 unsigned Bytes = Flags.getByValSize();
2209 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2210 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2211 return DAG.getFrameIndex(FI, getPointerTy());
2213 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2214 VA.getLocMemOffset(), isImmutable);
2215 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2216 return DAG.getLoad(ValVT, dl, Chain, FIN,
2217 MachinePointerInfo::getFixedStack(FI),
2218 false, false, false, 0);
2222 // FIXME: Get this from tablegen.
2223 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2224 const X86Subtarget *Subtarget) {
2225 assert(Subtarget->is64Bit());
2227 if (Subtarget->isCallingConvWin64(CallConv)) {
2228 static const MCPhysReg GPR64ArgRegsWin64[] = {
2229 X86::RCX, X86::RDX, X86::R8, X86::R9
2231 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2234 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2235 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2237 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2240 // FIXME: Get this from tablegen.
2241 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2242 CallingConv::ID CallConv,
2243 const X86Subtarget *Subtarget) {
2244 assert(Subtarget->is64Bit());
2245 if (Subtarget->isCallingConvWin64(CallConv)) {
2246 // The XMM registers which might contain var arg parameters are shadowed
2247 // in their paired GPR. So we only need to save the GPR to their home
2249 // TODO: __vectorcall will change this.
2253 const Function *Fn = MF.getFunction();
2254 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2255 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2256 "SSE register cannot be used when SSE is disabled!");
2257 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2258 !Subtarget->hasSSE1())
2259 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2263 static const MCPhysReg XMMArgRegs64Bit[] = {
2264 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2265 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2267 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2271 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2272 CallingConv::ID CallConv,
2274 const SmallVectorImpl<ISD::InputArg> &Ins,
2277 SmallVectorImpl<SDValue> &InVals)
2279 MachineFunction &MF = DAG.getMachineFunction();
2280 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2281 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2283 const Function* Fn = MF.getFunction();
2284 if (Fn->hasExternalLinkage() &&
2285 Subtarget->isTargetCygMing() &&
2286 Fn->getName() == "main")
2287 FuncInfo->setForceFramePointer(true);
2289 MachineFrameInfo *MFI = MF.getFrameInfo();
2290 bool Is64Bit = Subtarget->is64Bit();
2291 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2293 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2294 "Var args not supported with calling convention fastcc, ghc or hipe");
2296 // Assign locations to all of the incoming arguments.
2297 SmallVector<CCValAssign, 16> ArgLocs;
2298 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2300 // Allocate shadow area for Win64
2302 CCInfo.AllocateStack(32, 8);
2304 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2306 unsigned LastVal = ~0U;
2308 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2309 CCValAssign &VA = ArgLocs[i];
2310 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2312 assert(VA.getValNo() != LastVal &&
2313 "Don't support value assigned to multiple locs yet");
2315 LastVal = VA.getValNo();
2317 if (VA.isRegLoc()) {
2318 EVT RegVT = VA.getLocVT();
2319 const TargetRegisterClass *RC;
2320 if (RegVT == MVT::i32)
2321 RC = &X86::GR32RegClass;
2322 else if (Is64Bit && RegVT == MVT::i64)
2323 RC = &X86::GR64RegClass;
2324 else if (RegVT == MVT::f32)
2325 RC = &X86::FR32RegClass;
2326 else if (RegVT == MVT::f64)
2327 RC = &X86::FR64RegClass;
2328 else if (RegVT.is512BitVector())
2329 RC = &X86::VR512RegClass;
2330 else if (RegVT.is256BitVector())
2331 RC = &X86::VR256RegClass;
2332 else if (RegVT.is128BitVector())
2333 RC = &X86::VR128RegClass;
2334 else if (RegVT == MVT::x86mmx)
2335 RC = &X86::VR64RegClass;
2336 else if (RegVT == MVT::i1)
2337 RC = &X86::VK1RegClass;
2338 else if (RegVT == MVT::v8i1)
2339 RC = &X86::VK8RegClass;
2340 else if (RegVT == MVT::v16i1)
2341 RC = &X86::VK16RegClass;
2342 else if (RegVT == MVT::v32i1)
2343 RC = &X86::VK32RegClass;
2344 else if (RegVT == MVT::v64i1)
2345 RC = &X86::VK64RegClass;
2347 llvm_unreachable("Unknown argument type!");
2349 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2350 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2352 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2353 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2355 if (VA.getLocInfo() == CCValAssign::SExt)
2356 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2357 DAG.getValueType(VA.getValVT()));
2358 else if (VA.getLocInfo() == CCValAssign::ZExt)
2359 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2360 DAG.getValueType(VA.getValVT()));
2361 else if (VA.getLocInfo() == CCValAssign::BCvt)
2362 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2364 if (VA.isExtInLoc()) {
2365 // Handle MMX values passed in XMM regs.
2366 if (RegVT.isVector())
2367 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2369 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2372 assert(VA.isMemLoc());
2373 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2376 // If value is passed via pointer - do a load.
2377 if (VA.getLocInfo() == CCValAssign::Indirect)
2378 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2379 MachinePointerInfo(), false, false, false, 0);
2381 InVals.push_back(ArgValue);
2384 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2385 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2386 // The x86-64 ABIs require that for returning structs by value we copy
2387 // the sret argument into %rax/%eax (depending on ABI) for the return.
2388 // Win32 requires us to put the sret argument to %eax as well.
2389 // Save the argument into a virtual register so that we can access it
2390 // from the return points.
2391 if (Ins[i].Flags.isSRet()) {
2392 unsigned Reg = FuncInfo->getSRetReturnReg();
2394 MVT PtrTy = getPointerTy();
2395 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2396 FuncInfo->setSRetReturnReg(Reg);
2398 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2399 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2405 unsigned StackSize = CCInfo.getNextStackOffset();
2406 // Align stack specially for tail calls.
2407 if (FuncIsMadeTailCallSafe(CallConv,
2408 MF.getTarget().Options.GuaranteedTailCallOpt))
2409 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2411 // If the function takes variable number of arguments, make a frame index for
2412 // the start of the first vararg value... for expansion of llvm.va_start. We
2413 // can skip this if there are no va_start calls.
2414 if (MFI->hasVAStart() &&
2415 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2416 CallConv != CallingConv::X86_ThisCall))) {
2417 FuncInfo->setVarArgsFrameIndex(
2418 MFI->CreateFixedObject(1, StackSize, true));
2421 MachineModuleInfo &MMI = MF.getMMI();
2422 const Function *WinEHParent = nullptr;
2423 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2424 WinEHParent = MMI.getWinEHParent(Fn);
2425 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2426 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2428 // Figure out if XMM registers are in use.
2429 assert(!(MF.getTarget().Options.UseSoftFloat &&
2430 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2431 "SSE register cannot be used when SSE is disabled!");
2433 // 64-bit calling conventions support varargs and register parameters, so we
2434 // have to do extra work to spill them in the prologue.
2435 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2436 // Find the first unallocated argument registers.
2437 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2438 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2439 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2440 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2441 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2442 "SSE register cannot be used when SSE is disabled!");
2444 // Gather all the live in physical registers.
2445 SmallVector<SDValue, 6> LiveGPRs;
2446 SmallVector<SDValue, 8> LiveXMMRegs;
2448 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2449 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2451 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2453 if (!ArgXMMs.empty()) {
2454 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2455 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2456 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2457 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2458 LiveXMMRegs.push_back(
2459 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2464 // Get to the caller-allocated home save location. Add 8 to account
2465 // for the return address.
2466 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2467 FuncInfo->setRegSaveFrameIndex(
2468 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2469 // Fixup to set vararg frame on shadow area (4 x i64).
2471 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2473 // For X86-64, if there are vararg parameters that are passed via
2474 // registers, then we must store them to their spots on the stack so
2475 // they may be loaded by deferencing the result of va_next.
2476 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2477 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2478 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2479 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2482 // Store the integer parameter registers.
2483 SmallVector<SDValue, 8> MemOps;
2484 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2486 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2487 for (SDValue Val : LiveGPRs) {
2488 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2489 DAG.getIntPtrConstant(Offset));
2491 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2492 MachinePointerInfo::getFixedStack(
2493 FuncInfo->getRegSaveFrameIndex(), Offset),
2495 MemOps.push_back(Store);
2499 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2500 // Now store the XMM (fp + vector) parameter registers.
2501 SmallVector<SDValue, 12> SaveXMMOps;
2502 SaveXMMOps.push_back(Chain);
2503 SaveXMMOps.push_back(ALVal);
2504 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2505 FuncInfo->getRegSaveFrameIndex()));
2506 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2507 FuncInfo->getVarArgsFPOffset()));
2508 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2510 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2511 MVT::Other, SaveXMMOps));
2514 if (!MemOps.empty())
2515 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2516 } else if (IsWinEHOutlined) {
2517 // Get to the caller-allocated home save location. Add 8 to account
2518 // for the return address.
2519 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2520 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2521 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2523 MMI.getWinEHFuncInfo(Fn)
2524 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2525 FuncInfo->getRegSaveFrameIndex();
2527 // Store the second integer parameter (rdx) into rsp+16 relative to the
2528 // stack pointer at the entry of the function.
2530 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2531 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2532 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2533 Chain = DAG.getStore(
2534 Val.getValue(1), dl, Val, RSFIN,
2535 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2536 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2539 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2540 // Find the largest legal vector type.
2541 MVT VecVT = MVT::Other;
2542 // FIXME: Only some x86_32 calling conventions support AVX512.
2543 if (Subtarget->hasAVX512() &&
2544 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2545 CallConv == CallingConv::Intel_OCL_BI)))
2546 VecVT = MVT::v16f32;
2547 else if (Subtarget->hasAVX())
2549 else if (Subtarget->hasSSE2())
2552 // We forward some GPRs and some vector types.
2553 SmallVector<MVT, 2> RegParmTypes;
2554 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2555 RegParmTypes.push_back(IntVT);
2556 if (VecVT != MVT::Other)
2557 RegParmTypes.push_back(VecVT);
2559 // Compute the set of forwarded registers. The rest are scratch.
2560 SmallVectorImpl<ForwardedRegister> &Forwards =
2561 FuncInfo->getForwardedMustTailRegParms();
2562 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2564 // Conservatively forward AL on x86_64, since it might be used for varargs.
2565 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2566 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2567 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2570 // Copy all forwards from physical to virtual registers.
2571 for (ForwardedRegister &F : Forwards) {
2572 // FIXME: Can we use a less constrained schedule?
2573 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2574 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2575 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2579 // Some CCs need callee pop.
2580 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2581 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2582 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2584 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2585 // If this is an sret function, the return should pop the hidden pointer.
2586 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2587 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2588 argsAreStructReturn(Ins) == StackStructReturn)
2589 FuncInfo->setBytesToPopOnReturn(4);
2593 // RegSaveFrameIndex is X86-64 only.
2594 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2595 if (CallConv == CallingConv::X86_FastCall ||
2596 CallConv == CallingConv::X86_ThisCall)
2597 // fastcc functions can't have varargs.
2598 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2601 FuncInfo->setArgumentStackSize(StackSize);
2603 if (IsWinEHParent) {
2604 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2605 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2606 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2607 SDValue Neg2 = DAG.getConstant(-2, MVT::i64);
2608 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2609 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2610 /*isVolatile=*/true,
2611 /*isNonTemporal=*/false, /*Alignment=*/0);
2618 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2619 SDValue StackPtr, SDValue Arg,
2620 SDLoc dl, SelectionDAG &DAG,
2621 const CCValAssign &VA,
2622 ISD::ArgFlagsTy Flags) const {
2623 unsigned LocMemOffset = VA.getLocMemOffset();
2624 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2625 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2626 if (Flags.isByVal())
2627 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2629 return DAG.getStore(Chain, dl, Arg, PtrOff,
2630 MachinePointerInfo::getStack(LocMemOffset),
2634 /// Emit a load of return address if tail call
2635 /// optimization is performed and it is required.
2637 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2638 SDValue &OutRetAddr, SDValue Chain,
2639 bool IsTailCall, bool Is64Bit,
2640 int FPDiff, SDLoc dl) const {
2641 // Adjust the Return address stack slot.
2642 EVT VT = getPointerTy();
2643 OutRetAddr = getReturnAddressFrameIndex(DAG);
2645 // Load the "old" Return address.
2646 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2647 false, false, false, 0);
2648 return SDValue(OutRetAddr.getNode(), 1);
2651 /// Emit a store of the return address if tail call
2652 /// optimization is performed and it is required (FPDiff!=0).
2653 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2654 SDValue Chain, SDValue RetAddrFrIdx,
2655 EVT PtrVT, unsigned SlotSize,
2656 int FPDiff, SDLoc dl) {
2657 // Store the return address to the appropriate stack slot.
2658 if (!FPDiff) return Chain;
2659 // Calculate the new stack slot for the return address.
2660 int NewReturnAddrFI =
2661 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2663 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2664 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2665 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2671 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2672 SmallVectorImpl<SDValue> &InVals) const {
2673 SelectionDAG &DAG = CLI.DAG;
2675 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2676 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2677 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2678 SDValue Chain = CLI.Chain;
2679 SDValue Callee = CLI.Callee;
2680 CallingConv::ID CallConv = CLI.CallConv;
2681 bool &isTailCall = CLI.IsTailCall;
2682 bool isVarArg = CLI.IsVarArg;
2684 MachineFunction &MF = DAG.getMachineFunction();
2685 bool Is64Bit = Subtarget->is64Bit();
2686 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2687 StructReturnType SR = callIsStructReturn(Outs);
2688 bool IsSibcall = false;
2689 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2691 if (MF.getTarget().Options.DisableTailCalls)
2694 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2696 // Force this to be a tail call. The verifier rules are enough to ensure
2697 // that we can lower this successfully without moving the return address
2700 } else if (isTailCall) {
2701 // Check if it's really possible to do a tail call.
2702 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2703 isVarArg, SR != NotStructReturn,
2704 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2705 Outs, OutVals, Ins, DAG);
2707 // Sibcalls are automatically detected tailcalls which do not require
2709 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2716 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2717 "Var args not supported with calling convention fastcc, ghc or hipe");
2719 // Analyze operands of the call, assigning locations to each operand.
2720 SmallVector<CCValAssign, 16> ArgLocs;
2721 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2723 // Allocate shadow area for Win64
2725 CCInfo.AllocateStack(32, 8);
2727 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2729 // Get a count of how many bytes are to be pushed on the stack.
2730 unsigned NumBytes = CCInfo.getNextStackOffset();
2732 // This is a sibcall. The memory operands are available in caller's
2733 // own caller's stack.
2735 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2736 IsTailCallConvention(CallConv))
2737 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2740 if (isTailCall && !IsSibcall && !IsMustTail) {
2741 // Lower arguments at fp - stackoffset + fpdiff.
2742 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2744 FPDiff = NumBytesCallerPushed - NumBytes;
2746 // Set the delta of movement of the returnaddr stackslot.
2747 // But only set if delta is greater than previous delta.
2748 if (FPDiff < X86Info->getTCReturnAddrDelta())
2749 X86Info->setTCReturnAddrDelta(FPDiff);
2752 unsigned NumBytesToPush = NumBytes;
2753 unsigned NumBytesToPop = NumBytes;
2755 // If we have an inalloca argument, all stack space has already been allocated
2756 // for us and be right at the top of the stack. We don't support multiple
2757 // arguments passed in memory when using inalloca.
2758 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2760 if (!ArgLocs.back().isMemLoc())
2761 report_fatal_error("cannot use inalloca attribute on a register "
2763 if (ArgLocs.back().getLocMemOffset() != 0)
2764 report_fatal_error("any parameter with the inalloca attribute must be "
2765 "the only memory argument");
2769 Chain = DAG.getCALLSEQ_START(
2770 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2772 SDValue RetAddrFrIdx;
2773 // Load return address for tail calls.
2774 if (isTailCall && FPDiff)
2775 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2776 Is64Bit, FPDiff, dl);
2778 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2779 SmallVector<SDValue, 8> MemOpChains;
2782 // Walk the register/memloc assignments, inserting copies/loads. In the case
2783 // of tail call optimization arguments are handle later.
2784 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2785 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2786 // Skip inalloca arguments, they have already been written.
2787 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2788 if (Flags.isInAlloca())
2791 CCValAssign &VA = ArgLocs[i];
2792 EVT RegVT = VA.getLocVT();
2793 SDValue Arg = OutVals[i];
2794 bool isByVal = Flags.isByVal();
2796 // Promote the value if needed.
2797 switch (VA.getLocInfo()) {
2798 default: llvm_unreachable("Unknown loc info!");
2799 case CCValAssign::Full: break;
2800 case CCValAssign::SExt:
2801 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2803 case CCValAssign::ZExt:
2804 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2806 case CCValAssign::AExt:
2807 if (RegVT.is128BitVector()) {
2808 // Special case: passing MMX values in XMM registers.
2809 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2810 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2811 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2813 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2815 case CCValAssign::BCvt:
2816 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2818 case CCValAssign::Indirect: {
2819 // Store the argument.
2820 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2821 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2822 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2823 MachinePointerInfo::getFixedStack(FI),
2830 if (VA.isRegLoc()) {
2831 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2832 if (isVarArg && IsWin64) {
2833 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2834 // shadow reg if callee is a varargs function.
2835 unsigned ShadowReg = 0;
2836 switch (VA.getLocReg()) {
2837 case X86::XMM0: ShadowReg = X86::RCX; break;
2838 case X86::XMM1: ShadowReg = X86::RDX; break;
2839 case X86::XMM2: ShadowReg = X86::R8; break;
2840 case X86::XMM3: ShadowReg = X86::R9; break;
2843 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2845 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2846 assert(VA.isMemLoc());
2847 if (!StackPtr.getNode())
2848 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2850 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2851 dl, DAG, VA, Flags));
2855 if (!MemOpChains.empty())
2856 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2858 if (Subtarget->isPICStyleGOT()) {
2859 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2862 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2863 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2865 // If we are tail calling and generating PIC/GOT style code load the
2866 // address of the callee into ECX. The value in ecx is used as target of
2867 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2868 // for tail calls on PIC/GOT architectures. Normally we would just put the
2869 // address of GOT into ebx and then call target@PLT. But for tail calls
2870 // ebx would be restored (since ebx is callee saved) before jumping to the
2873 // Note: The actual moving to ECX is done further down.
2874 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2875 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2876 !G->getGlobal()->hasProtectedVisibility())
2877 Callee = LowerGlobalAddress(Callee, DAG);
2878 else if (isa<ExternalSymbolSDNode>(Callee))
2879 Callee = LowerExternalSymbol(Callee, DAG);
2883 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2884 // From AMD64 ABI document:
2885 // For calls that may call functions that use varargs or stdargs
2886 // (prototype-less calls or calls to functions containing ellipsis (...) in
2887 // the declaration) %al is used as hidden argument to specify the number
2888 // of SSE registers used. The contents of %al do not need to match exactly
2889 // the number of registers, but must be an ubound on the number of SSE
2890 // registers used and is in the range 0 - 8 inclusive.
2892 // Count the number of XMM registers allocated.
2893 static const MCPhysReg XMMArgRegs[] = {
2894 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2895 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2897 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2898 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2899 && "SSE registers cannot be used when SSE is disabled");
2901 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2902 DAG.getConstant(NumXMMRegs, MVT::i8)));
2905 if (isVarArg && IsMustTail) {
2906 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2907 for (const auto &F : Forwards) {
2908 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2909 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2913 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2914 // don't need this because the eligibility check rejects calls that require
2915 // shuffling arguments passed in memory.
2916 if (!IsSibcall && isTailCall) {
2917 // Force all the incoming stack arguments to be loaded from the stack
2918 // before any new outgoing arguments are stored to the stack, because the
2919 // outgoing stack slots may alias the incoming argument stack slots, and
2920 // the alias isn't otherwise explicit. This is slightly more conservative
2921 // than necessary, because it means that each store effectively depends
2922 // on every argument instead of just those arguments it would clobber.
2923 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2925 SmallVector<SDValue, 8> MemOpChains2;
2928 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2929 CCValAssign &VA = ArgLocs[i];
2932 assert(VA.isMemLoc());
2933 SDValue Arg = OutVals[i];
2934 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2935 // Skip inalloca arguments. They don't require any work.
2936 if (Flags.isInAlloca())
2938 // Create frame index.
2939 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2940 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2941 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2942 FIN = DAG.getFrameIndex(FI, getPointerTy());
2944 if (Flags.isByVal()) {
2945 // Copy relative to framepointer.
2946 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2947 if (!StackPtr.getNode())
2948 StackPtr = DAG.getCopyFromReg(Chain, dl,
2949 RegInfo->getStackRegister(),
2951 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2953 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2957 // Store relative to framepointer.
2958 MemOpChains2.push_back(
2959 DAG.getStore(ArgChain, dl, Arg, FIN,
2960 MachinePointerInfo::getFixedStack(FI),
2965 if (!MemOpChains2.empty())
2966 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2968 // Store the return address to the appropriate stack slot.
2969 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2970 getPointerTy(), RegInfo->getSlotSize(),
2974 // Build a sequence of copy-to-reg nodes chained together with token chain
2975 // and flag operands which copy the outgoing args into registers.
2977 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2978 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2979 RegsToPass[i].second, InFlag);
2980 InFlag = Chain.getValue(1);
2983 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2984 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2985 // In the 64-bit large code model, we have to make all calls
2986 // through a register, since the call instruction's 32-bit
2987 // pc-relative offset may not be large enough to hold the whole
2989 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
2990 // If the callee is a GlobalAddress node (quite common, every direct call
2991 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2993 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
2995 // We should use extra load for direct calls to dllimported functions in
2997 const GlobalValue *GV = G->getGlobal();
2998 if (!GV->hasDLLImportStorageClass()) {
2999 unsigned char OpFlags = 0;
3000 bool ExtraLoad = false;
3001 unsigned WrapperKind = ISD::DELETED_NODE;
3003 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3004 // external symbols most go through the PLT in PIC mode. If the symbol
3005 // has hidden or protected visibility, or if it is static or local, then
3006 // we don't need to use the PLT - we can directly call it.
3007 if (Subtarget->isTargetELF() &&
3008 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3009 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3010 OpFlags = X86II::MO_PLT;
3011 } else if (Subtarget->isPICStyleStubAny() &&
3012 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3013 (!Subtarget->getTargetTriple().isMacOSX() ||
3014 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3015 // PC-relative references to external symbols should go through $stub,
3016 // unless we're building with the leopard linker or later, which
3017 // automatically synthesizes these stubs.
3018 OpFlags = X86II::MO_DARWIN_STUB;
3019 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3020 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3021 // If the function is marked as non-lazy, generate an indirect call
3022 // which loads from the GOT directly. This avoids runtime overhead
3023 // at the cost of eager binding (and one extra byte of encoding).
3024 OpFlags = X86II::MO_GOTPCREL;
3025 WrapperKind = X86ISD::WrapperRIP;
3029 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3030 G->getOffset(), OpFlags);
3032 // Add a wrapper if needed.
3033 if (WrapperKind != ISD::DELETED_NODE)
3034 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3035 // Add extra indirection if needed.
3037 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3038 MachinePointerInfo::getGOT(),
3039 false, false, false, 0);
3041 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3042 unsigned char OpFlags = 0;
3044 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3045 // external symbols should go through the PLT.
3046 if (Subtarget->isTargetELF() &&
3047 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3048 OpFlags = X86II::MO_PLT;
3049 } else if (Subtarget->isPICStyleStubAny() &&
3050 (!Subtarget->getTargetTriple().isMacOSX() ||
3051 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3052 // PC-relative references to external symbols should go through $stub,
3053 // unless we're building with the leopard linker or later, which
3054 // automatically synthesizes these stubs.
3055 OpFlags = X86II::MO_DARWIN_STUB;
3058 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3060 } else if (Subtarget->isTarget64BitILP32() &&
3061 Callee->getValueType(0) == MVT::i32) {
3062 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3063 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3066 // Returns a chain & a flag for retval copy to use.
3067 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3068 SmallVector<SDValue, 8> Ops;
3070 if (!IsSibcall && isTailCall) {
3071 Chain = DAG.getCALLSEQ_END(Chain,
3072 DAG.getIntPtrConstant(NumBytesToPop, true),
3073 DAG.getIntPtrConstant(0, true), InFlag, dl);
3074 InFlag = Chain.getValue(1);
3077 Ops.push_back(Chain);
3078 Ops.push_back(Callee);
3081 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3083 // Add argument registers to the end of the list so that they are known live
3085 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3086 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3087 RegsToPass[i].second.getValueType()));
3089 // Add a register mask operand representing the call-preserved registers.
3090 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3091 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3092 assert(Mask && "Missing call preserved mask for calling convention");
3093 Ops.push_back(DAG.getRegisterMask(Mask));
3095 if (InFlag.getNode())
3096 Ops.push_back(InFlag);
3100 //// If this is the first return lowered for this function, add the regs
3101 //// to the liveout set for the function.
3102 // This isn't right, although it's probably harmless on x86; liveouts
3103 // should be computed from returns not tail calls. Consider a void
3104 // function making a tail call to a function returning int.
3105 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3108 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3109 InFlag = Chain.getValue(1);
3111 // Create the CALLSEQ_END node.
3112 unsigned NumBytesForCalleeToPop;
3113 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3114 DAG.getTarget().Options.GuaranteedTailCallOpt))
3115 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3116 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3117 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3118 SR == StackStructReturn)
3119 // If this is a call to a struct-return function, the callee
3120 // pops the hidden struct pointer, so we have to push it back.
3121 // This is common for Darwin/X86, Linux & Mingw32 targets.
3122 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3123 NumBytesForCalleeToPop = 4;
3125 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3127 // Returns a flag for retval copy to use.
3129 Chain = DAG.getCALLSEQ_END(Chain,
3130 DAG.getIntPtrConstant(NumBytesToPop, true),
3131 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3134 InFlag = Chain.getValue(1);
3137 // Handle result values, copying them out of physregs into vregs that we
3139 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3140 Ins, dl, DAG, InVals);
3143 //===----------------------------------------------------------------------===//
3144 // Fast Calling Convention (tail call) implementation
3145 //===----------------------------------------------------------------------===//
3147 // Like std call, callee cleans arguments, convention except that ECX is
3148 // reserved for storing the tail called function address. Only 2 registers are
3149 // free for argument passing (inreg). Tail call optimization is performed
3151 // * tailcallopt is enabled
3152 // * caller/callee are fastcc
3153 // On X86_64 architecture with GOT-style position independent code only local
3154 // (within module) calls are supported at the moment.
3155 // To keep the stack aligned according to platform abi the function
3156 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3157 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3158 // If a tail called function callee has more arguments than the caller the
3159 // caller needs to make sure that there is room to move the RETADDR to. This is
3160 // achieved by reserving an area the size of the argument delta right after the
3161 // original RETADDR, but before the saved framepointer or the spilled registers
3162 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3174 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3175 /// for a 16 byte align requirement.
3177 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3178 SelectionDAG& DAG) const {
3179 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3180 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3181 unsigned StackAlignment = TFI.getStackAlignment();
3182 uint64_t AlignMask = StackAlignment - 1;
3183 int64_t Offset = StackSize;
3184 unsigned SlotSize = RegInfo->getSlotSize();
3185 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3186 // Number smaller than 12 so just add the difference.
3187 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3189 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3190 Offset = ((~AlignMask) & Offset) + StackAlignment +
3191 (StackAlignment-SlotSize);
3196 /// MatchingStackOffset - Return true if the given stack call argument is
3197 /// already available in the same position (relatively) of the caller's
3198 /// incoming argument stack.
3200 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3201 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3202 const X86InstrInfo *TII) {
3203 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3205 if (Arg.getOpcode() == ISD::CopyFromReg) {
3206 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3207 if (!TargetRegisterInfo::isVirtualRegister(VR))
3209 MachineInstr *Def = MRI->getVRegDef(VR);
3212 if (!Flags.isByVal()) {
3213 if (!TII->isLoadFromStackSlot(Def, FI))
3216 unsigned Opcode = Def->getOpcode();
3217 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3218 Opcode == X86::LEA64_32r) &&
3219 Def->getOperand(1).isFI()) {
3220 FI = Def->getOperand(1).getIndex();
3221 Bytes = Flags.getByValSize();
3225 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3226 if (Flags.isByVal())
3227 // ByVal argument is passed in as a pointer but it's now being
3228 // dereferenced. e.g.
3229 // define @foo(%struct.X* %A) {
3230 // tail call @bar(%struct.X* byval %A)
3233 SDValue Ptr = Ld->getBasePtr();
3234 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3237 FI = FINode->getIndex();
3238 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3239 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3240 FI = FINode->getIndex();
3241 Bytes = Flags.getByValSize();
3245 assert(FI != INT_MAX);
3246 if (!MFI->isFixedObjectIndex(FI))
3248 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3251 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3252 /// for tail call optimization. Targets which want to do tail call
3253 /// optimization should implement this function.
3255 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3256 CallingConv::ID CalleeCC,
3258 bool isCalleeStructRet,
3259 bool isCallerStructRet,
3261 const SmallVectorImpl<ISD::OutputArg> &Outs,
3262 const SmallVectorImpl<SDValue> &OutVals,
3263 const SmallVectorImpl<ISD::InputArg> &Ins,
3264 SelectionDAG &DAG) const {
3265 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3268 // If -tailcallopt is specified, make fastcc functions tail-callable.
3269 const MachineFunction &MF = DAG.getMachineFunction();
3270 const Function *CallerF = MF.getFunction();
3272 // If the function return type is x86_fp80 and the callee return type is not,
3273 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3274 // perform a tailcall optimization here.
3275 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3278 CallingConv::ID CallerCC = CallerF->getCallingConv();
3279 bool CCMatch = CallerCC == CalleeCC;
3280 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3281 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3283 // Win64 functions have extra shadow space for argument homing. Don't do the
3284 // sibcall if the caller and callee have mismatched expectations for this
3286 if (IsCalleeWin64 != IsCallerWin64)
3289 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3290 if (IsTailCallConvention(CalleeCC) && CCMatch)
3295 // Look for obvious safe cases to perform tail call optimization that do not
3296 // require ABI changes. This is what gcc calls sibcall.
3298 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3299 // emit a special epilogue.
3300 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3301 if (RegInfo->needsStackRealignment(MF))
3304 // Also avoid sibcall optimization if either caller or callee uses struct
3305 // return semantics.
3306 if (isCalleeStructRet || isCallerStructRet)
3309 // An stdcall/thiscall caller is expected to clean up its arguments; the
3310 // callee isn't going to do that.
3311 // FIXME: this is more restrictive than needed. We could produce a tailcall
3312 // when the stack adjustment matches. For example, with a thiscall that takes
3313 // only one argument.
3314 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3315 CallerCC == CallingConv::X86_ThisCall))
3318 // Do not sibcall optimize vararg calls unless all arguments are passed via
3320 if (isVarArg && !Outs.empty()) {
3322 // Optimizing for varargs on Win64 is unlikely to be safe without
3323 // additional testing.
3324 if (IsCalleeWin64 || IsCallerWin64)
3327 SmallVector<CCValAssign, 16> ArgLocs;
3328 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3331 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3332 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3333 if (!ArgLocs[i].isRegLoc())
3337 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3338 // stack. Therefore, if it's not used by the call it is not safe to optimize
3339 // this into a sibcall.
3340 bool Unused = false;
3341 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3348 SmallVector<CCValAssign, 16> RVLocs;
3349 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3351 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3352 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3353 CCValAssign &VA = RVLocs[i];
3354 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3359 // If the calling conventions do not match, then we'd better make sure the
3360 // results are returned in the same way as what the caller expects.
3362 SmallVector<CCValAssign, 16> RVLocs1;
3363 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3365 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3367 SmallVector<CCValAssign, 16> RVLocs2;
3368 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3370 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3372 if (RVLocs1.size() != RVLocs2.size())
3374 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3375 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3377 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3379 if (RVLocs1[i].isRegLoc()) {
3380 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3383 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3389 // If the callee takes no arguments then go on to check the results of the
3391 if (!Outs.empty()) {
3392 // Check if stack adjustment is needed. For now, do not do this if any
3393 // argument is passed on the stack.
3394 SmallVector<CCValAssign, 16> ArgLocs;
3395 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3398 // Allocate shadow area for Win64
3400 CCInfo.AllocateStack(32, 8);
3402 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3403 if (CCInfo.getNextStackOffset()) {
3404 MachineFunction &MF = DAG.getMachineFunction();
3405 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3408 // Check if the arguments are already laid out in the right way as
3409 // the caller's fixed stack objects.
3410 MachineFrameInfo *MFI = MF.getFrameInfo();
3411 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3412 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3413 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3414 CCValAssign &VA = ArgLocs[i];
3415 SDValue Arg = OutVals[i];
3416 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3417 if (VA.getLocInfo() == CCValAssign::Indirect)
3419 if (!VA.isRegLoc()) {
3420 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3427 // If the tailcall address may be in a register, then make sure it's
3428 // possible to register allocate for it. In 32-bit, the call address can
3429 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3430 // callee-saved registers are restored. These happen to be the same
3431 // registers used to pass 'inreg' arguments so watch out for those.
3432 if (!Subtarget->is64Bit() &&
3433 ((!isa<GlobalAddressSDNode>(Callee) &&
3434 !isa<ExternalSymbolSDNode>(Callee)) ||
3435 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3436 unsigned NumInRegs = 0;
3437 // In PIC we need an extra register to formulate the address computation
3439 unsigned MaxInRegs =
3440 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3442 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3443 CCValAssign &VA = ArgLocs[i];
3446 unsigned Reg = VA.getLocReg();
3449 case X86::EAX: case X86::EDX: case X86::ECX:
3450 if (++NumInRegs == MaxInRegs)
3462 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3463 const TargetLibraryInfo *libInfo) const {
3464 return X86::createFastISel(funcInfo, libInfo);
3467 //===----------------------------------------------------------------------===//
3468 // Other Lowering Hooks
3469 //===----------------------------------------------------------------------===//
3471 static bool MayFoldLoad(SDValue Op) {
3472 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3475 static bool MayFoldIntoStore(SDValue Op) {
3476 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3479 static bool isTargetShuffle(unsigned Opcode) {
3481 default: return false;
3482 case X86ISD::BLENDI:
3483 case X86ISD::PSHUFB:
3484 case X86ISD::PSHUFD:
3485 case X86ISD::PSHUFHW:
3486 case X86ISD::PSHUFLW:
3488 case X86ISD::PALIGNR:
3489 case X86ISD::MOVLHPS:
3490 case X86ISD::MOVLHPD:
3491 case X86ISD::MOVHLPS:
3492 case X86ISD::MOVLPS:
3493 case X86ISD::MOVLPD:
3494 case X86ISD::MOVSHDUP:
3495 case X86ISD::MOVSLDUP:
3496 case X86ISD::MOVDDUP:
3499 case X86ISD::UNPCKL:
3500 case X86ISD::UNPCKH:
3501 case X86ISD::VPERMILPI:
3502 case X86ISD::VPERM2X128:
3503 case X86ISD::VPERMI:
3508 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3509 SDValue V1, unsigned TargetMask,
3510 SelectionDAG &DAG) {
3512 default: llvm_unreachable("Unknown x86 shuffle node");
3513 case X86ISD::PSHUFD:
3514 case X86ISD::PSHUFHW:
3515 case X86ISD::PSHUFLW:
3516 case X86ISD::VPERMILPI:
3517 case X86ISD::VPERMI:
3518 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3522 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3523 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3525 default: llvm_unreachable("Unknown x86 shuffle node");
3526 case X86ISD::MOVLHPS:
3527 case X86ISD::MOVLHPD:
3528 case X86ISD::MOVHLPS:
3529 case X86ISD::MOVLPS:
3530 case X86ISD::MOVLPD:
3533 case X86ISD::UNPCKL:
3534 case X86ISD::UNPCKH:
3535 return DAG.getNode(Opc, dl, VT, V1, V2);
3539 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3540 MachineFunction &MF = DAG.getMachineFunction();
3541 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3542 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3543 int ReturnAddrIndex = FuncInfo->getRAIndex();
3545 if (ReturnAddrIndex == 0) {
3546 // Set up a frame object for the return address.
3547 unsigned SlotSize = RegInfo->getSlotSize();
3548 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3551 FuncInfo->setRAIndex(ReturnAddrIndex);
3554 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3557 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3558 bool hasSymbolicDisplacement) {
3559 // Offset should fit into 32 bit immediate field.
3560 if (!isInt<32>(Offset))
3563 // If we don't have a symbolic displacement - we don't have any extra
3565 if (!hasSymbolicDisplacement)
3568 // FIXME: Some tweaks might be needed for medium code model.
3569 if (M != CodeModel::Small && M != CodeModel::Kernel)
3572 // For small code model we assume that latest object is 16MB before end of 31
3573 // bits boundary. We may also accept pretty large negative constants knowing
3574 // that all objects are in the positive half of address space.
3575 if (M == CodeModel::Small && Offset < 16*1024*1024)
3578 // For kernel code model we know that all object resist in the negative half
3579 // of 32bits address space. We may not accept negative offsets, since they may
3580 // be just off and we may accept pretty large positive ones.
3581 if (M == CodeModel::Kernel && Offset >= 0)
3587 /// isCalleePop - Determines whether the callee is required to pop its
3588 /// own arguments. Callee pop is necessary to support tail calls.
3589 bool X86::isCalleePop(CallingConv::ID CallingConv,
3590 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3591 switch (CallingConv) {
3594 case CallingConv::X86_StdCall:
3595 case CallingConv::X86_FastCall:
3596 case CallingConv::X86_ThisCall:
3598 case CallingConv::Fast:
3599 case CallingConv::GHC:
3600 case CallingConv::HiPE:
3607 /// \brief Return true if the condition is an unsigned comparison operation.
3608 static bool isX86CCUnsigned(unsigned X86CC) {
3610 default: llvm_unreachable("Invalid integer condition!");
3611 case X86::COND_E: return true;
3612 case X86::COND_G: return false;
3613 case X86::COND_GE: return false;
3614 case X86::COND_L: return false;
3615 case X86::COND_LE: return false;
3616 case X86::COND_NE: return true;
3617 case X86::COND_B: return true;
3618 case X86::COND_A: return true;
3619 case X86::COND_BE: return true;
3620 case X86::COND_AE: return true;
3622 llvm_unreachable("covered switch fell through?!");
3625 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3626 /// specific condition code, returning the condition code and the LHS/RHS of the
3627 /// comparison to make.
3628 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3629 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3631 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3632 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3633 // X > -1 -> X == 0, jump !sign.
3634 RHS = DAG.getConstant(0, RHS.getValueType());
3635 return X86::COND_NS;
3637 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3638 // X < 0 -> X == 0, jump on sign.
3641 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3643 RHS = DAG.getConstant(0, RHS.getValueType());
3644 return X86::COND_LE;
3648 switch (SetCCOpcode) {
3649 default: llvm_unreachable("Invalid integer condition!");
3650 case ISD::SETEQ: return X86::COND_E;
3651 case ISD::SETGT: return X86::COND_G;
3652 case ISD::SETGE: return X86::COND_GE;
3653 case ISD::SETLT: return X86::COND_L;
3654 case ISD::SETLE: return X86::COND_LE;
3655 case ISD::SETNE: return X86::COND_NE;
3656 case ISD::SETULT: return X86::COND_B;
3657 case ISD::SETUGT: return X86::COND_A;
3658 case ISD::SETULE: return X86::COND_BE;
3659 case ISD::SETUGE: return X86::COND_AE;
3663 // First determine if it is required or is profitable to flip the operands.
3665 // If LHS is a foldable load, but RHS is not, flip the condition.
3666 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3667 !ISD::isNON_EXTLoad(RHS.getNode())) {
3668 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3669 std::swap(LHS, RHS);
3672 switch (SetCCOpcode) {
3678 std::swap(LHS, RHS);
3682 // On a floating point condition, the flags are set as follows:
3684 // 0 | 0 | 0 | X > Y
3685 // 0 | 0 | 1 | X < Y
3686 // 1 | 0 | 0 | X == Y
3687 // 1 | 1 | 1 | unordered
3688 switch (SetCCOpcode) {
3689 default: llvm_unreachable("Condcode should be pre-legalized away");
3691 case ISD::SETEQ: return X86::COND_E;
3692 case ISD::SETOLT: // flipped
3694 case ISD::SETGT: return X86::COND_A;
3695 case ISD::SETOLE: // flipped
3697 case ISD::SETGE: return X86::COND_AE;
3698 case ISD::SETUGT: // flipped
3700 case ISD::SETLT: return X86::COND_B;
3701 case ISD::SETUGE: // flipped
3703 case ISD::SETLE: return X86::COND_BE;
3705 case ISD::SETNE: return X86::COND_NE;
3706 case ISD::SETUO: return X86::COND_P;
3707 case ISD::SETO: return X86::COND_NP;
3709 case ISD::SETUNE: return X86::COND_INVALID;
3713 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3714 /// code. Current x86 isa includes the following FP cmov instructions:
3715 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3716 static bool hasFPCMov(unsigned X86CC) {
3732 /// isFPImmLegal - Returns true if the target can instruction select the
3733 /// specified FP immediate natively. If false, the legalizer will
3734 /// materialize the FP immediate as a load from a constant pool.
3735 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3736 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3737 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3743 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3744 ISD::LoadExtType ExtTy,
3746 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3747 // relocation target a movq or addq instruction: don't let the load shrink.
3748 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3749 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3750 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3751 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3755 /// \brief Returns true if it is beneficial to convert a load of a constant
3756 /// to just the constant itself.
3757 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3759 assert(Ty->isIntegerTy());
3761 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3762 if (BitSize == 0 || BitSize > 64)
3767 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3768 unsigned Index) const {
3769 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3772 return (Index == 0 || Index == ResVT.getVectorNumElements());
3775 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3776 // Speculate cttz only if we can directly use TZCNT.
3777 return Subtarget->hasBMI();
3780 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3781 // Speculate ctlz only if we can directly use LZCNT.
3782 return Subtarget->hasLZCNT();
3785 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3786 /// the specified range (L, H].
3787 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3788 return (Val < 0) || (Val >= Low && Val < Hi);
3791 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3792 /// specified value.
3793 static bool isUndefOrEqual(int Val, int CmpVal) {
3794 return (Val < 0 || Val == CmpVal);
3797 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3798 /// from position Pos and ending in Pos+Size, falls within the specified
3799 /// sequential range (Low, Low+Size]. or is undef.
3800 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3801 unsigned Pos, unsigned Size, int Low) {
3802 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3803 if (!isUndefOrEqual(Mask[i], Low))
3808 /// isVEXTRACTIndex - Return true if the specified
3809 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3810 /// suitable for instruction that extract 128 or 256 bit vectors
3811 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3812 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3813 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3816 // The index should be aligned on a vecWidth-bit boundary.
3818 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3820 MVT VT = N->getSimpleValueType(0);
3821 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3822 bool Result = (Index * ElSize) % vecWidth == 0;
3827 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3828 /// operand specifies a subvector insert that is suitable for input to
3829 /// insertion of 128 or 256-bit subvectors
3830 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3831 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3832 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3834 // The index should be aligned on a vecWidth-bit boundary.
3836 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3838 MVT VT = N->getSimpleValueType(0);
3839 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3840 bool Result = (Index * ElSize) % vecWidth == 0;
3845 bool X86::isVINSERT128Index(SDNode *N) {
3846 return isVINSERTIndex(N, 128);
3849 bool X86::isVINSERT256Index(SDNode *N) {
3850 return isVINSERTIndex(N, 256);
3853 bool X86::isVEXTRACT128Index(SDNode *N) {
3854 return isVEXTRACTIndex(N, 128);
3857 bool X86::isVEXTRACT256Index(SDNode *N) {
3858 return isVEXTRACTIndex(N, 256);
3861 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3862 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3863 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3864 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3867 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3869 MVT VecVT = N->getOperand(0).getSimpleValueType();
3870 MVT ElVT = VecVT.getVectorElementType();
3872 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3873 return Index / NumElemsPerChunk;
3876 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3877 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3878 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3879 llvm_unreachable("Illegal insert subvector for VINSERT");
3882 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3884 MVT VecVT = N->getSimpleValueType(0);
3885 MVT ElVT = VecVT.getVectorElementType();
3887 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3888 return Index / NumElemsPerChunk;
3891 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3892 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3893 /// and VINSERTI128 instructions.
3894 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3895 return getExtractVEXTRACTImmediate(N, 128);
3898 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3899 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3900 /// and VINSERTI64x4 instructions.
3901 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3902 return getExtractVEXTRACTImmediate(N, 256);
3905 /// getInsertVINSERT128Immediate - Return the appropriate immediate
3906 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3907 /// and VINSERTI128 instructions.
3908 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
3909 return getInsertVINSERTImmediate(N, 128);
3912 /// getInsertVINSERT256Immediate - Return the appropriate immediate
3913 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
3914 /// and VINSERTI64x4 instructions.
3915 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
3916 return getInsertVINSERTImmediate(N, 256);
3919 /// isZero - Returns true if Elt is a constant integer zero
3920 static bool isZero(SDValue V) {
3921 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
3922 return C && C->isNullValue();
3925 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3927 bool X86::isZeroNode(SDValue Elt) {
3930 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
3931 return CFP->getValueAPF().isPosZero();
3935 /// getZeroVector - Returns a vector of specified type with all zero elements.
3937 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
3938 SelectionDAG &DAG, SDLoc dl) {
3939 assert(VT.isVector() && "Expected a vector type");
3941 // Always build SSE zero vectors as <4 x i32> bitcasted
3942 // to their dest type. This ensures they get CSE'd.
3944 if (VT.is128BitVector()) { // SSE
3945 if (Subtarget->hasSSE2()) { // SSE2
3946 SDValue Cst = DAG.getConstant(0, MVT::i32);
3947 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3949 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
3950 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3952 } else if (VT.is256BitVector()) { // AVX
3953 if (Subtarget->hasInt256()) { // AVX2
3954 SDValue Cst = DAG.getConstant(0, MVT::i32);
3955 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3956 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
3958 // 256-bit logic and arithmetic instructions in AVX are all
3959 // floating-point, no support for integer ops. Emit fp zeroed vectors.
3960 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
3961 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3962 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
3964 } else if (VT.is512BitVector()) { // AVX-512
3965 SDValue Cst = DAG.getConstant(0, MVT::i32);
3966 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
3967 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3968 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
3969 } else if (VT.getScalarType() == MVT::i1) {
3971 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
3972 && "Unexpected vector type");
3973 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
3974 && "Unexpected vector type");
3975 SDValue Cst = DAG.getConstant(0, MVT::i1);
3976 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
3977 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3979 llvm_unreachable("Unexpected vector type");
3981 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3984 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
3985 SelectionDAG &DAG, SDLoc dl,
3986 unsigned vectorWidth) {
3987 assert((vectorWidth == 128 || vectorWidth == 256) &&
3988 "Unsupported vector width");
3989 EVT VT = Vec.getValueType();
3990 EVT ElVT = VT.getVectorElementType();
3991 unsigned Factor = VT.getSizeInBits()/vectorWidth;
3992 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
3993 VT.getVectorNumElements()/Factor);
3995 // Extract from UNDEF is UNDEF.
3996 if (Vec.getOpcode() == ISD::UNDEF)
3997 return DAG.getUNDEF(ResultVT);
3999 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4000 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4002 // This is the index of the first element of the vectorWidth-bit chunk
4004 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4007 // If the input is a buildvector just emit a smaller one.
4008 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4009 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4010 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4013 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
4014 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4017 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4018 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4019 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4020 /// instructions or a simple subregister reference. Idx is an index in the
4021 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4022 /// lowering EXTRACT_VECTOR_ELT operations easier.
4023 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4024 SelectionDAG &DAG, SDLoc dl) {
4025 assert((Vec.getValueType().is256BitVector() ||
4026 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4027 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4030 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4031 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4032 SelectionDAG &DAG, SDLoc dl) {
4033 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4034 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4037 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4038 unsigned IdxVal, SelectionDAG &DAG,
4039 SDLoc dl, unsigned vectorWidth) {
4040 assert((vectorWidth == 128 || vectorWidth == 256) &&
4041 "Unsupported vector width");
4042 // Inserting UNDEF is Result
4043 if (Vec.getOpcode() == ISD::UNDEF)
4045 EVT VT = Vec.getValueType();
4046 EVT ElVT = VT.getVectorElementType();
4047 EVT ResultVT = Result.getValueType();
4049 // Insert the relevant vectorWidth bits.
4050 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4052 // This is the index of the first element of the vectorWidth-bit chunk
4054 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4057 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
4058 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4061 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4062 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4063 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4064 /// simple superregister reference. Idx is an index in the 128 bits
4065 /// we want. It need not be aligned to a 128-bit boundary. That makes
4066 /// lowering INSERT_VECTOR_ELT operations easier.
4067 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4068 SelectionDAG &DAG, SDLoc dl) {
4069 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4071 // For insertion into the zero index (low half) of a 256-bit vector, it is
4072 // more efficient to generate a blend with immediate instead of an insert*128.
4073 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4074 // extend the subvector to the size of the result vector. Make sure that
4075 // we are not recursing on that node by checking for undef here.
4076 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4077 Result.getOpcode() != ISD::UNDEF) {
4078 EVT ResultVT = Result.getValueType();
4079 SDValue ZeroIndex = DAG.getIntPtrConstant(0);
4080 SDValue Undef = DAG.getUNDEF(ResultVT);
4081 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4084 // The blend instruction, and therefore its mask, depend on the data type.
4085 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4086 if (ScalarType.isFloatingPoint()) {
4087 // Choose either vblendps (float) or vblendpd (double).
4088 unsigned ScalarSize = ScalarType.getSizeInBits();
4089 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4090 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4091 SDValue Mask = DAG.getConstant(MaskVal, MVT::i8);
4092 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4095 const X86Subtarget &Subtarget =
4096 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4098 // AVX2 is needed for 256-bit integer blend support.
4099 // Integers must be cast to 32-bit because there is only vpblendd;
4100 // vpblendw can't be used for this because it has a handicapped mask.
4102 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4103 // is still more efficient than using the wrong domain vinsertf128 that
4104 // will be created by InsertSubVector().
4105 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4107 SDValue Mask = DAG.getConstant(0x0f, MVT::i8);
4108 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4109 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4110 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4113 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4116 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4117 SelectionDAG &DAG, SDLoc dl) {
4118 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4119 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4122 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4123 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4124 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4125 /// large BUILD_VECTORS.
4126 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4127 unsigned NumElems, SelectionDAG &DAG,
4129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4133 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4134 unsigned NumElems, SelectionDAG &DAG,
4136 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4137 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4140 /// getOnesVector - Returns a vector of specified type with all bits set.
4141 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4142 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4143 /// Then bitcast to their original type, ensuring they get CSE'd.
4144 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4146 assert(VT.isVector() && "Expected a vector type");
4148 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
4150 if (VT.is256BitVector()) {
4151 if (HasInt256) { // AVX2
4152 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4153 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4155 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4156 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4158 } else if (VT.is128BitVector()) {
4159 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4161 llvm_unreachable("Unexpected vector type");
4163 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4166 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4167 /// operation of specified width.
4168 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4170 unsigned NumElems = VT.getVectorNumElements();
4171 SmallVector<int, 8> Mask;
4172 Mask.push_back(NumElems);
4173 for (unsigned i = 1; i != NumElems; ++i)
4175 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4178 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4179 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4181 unsigned NumElems = VT.getVectorNumElements();
4182 SmallVector<int, 8> Mask;
4183 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4185 Mask.push_back(i + NumElems);
4187 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4190 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4191 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4193 unsigned NumElems = VT.getVectorNumElements();
4194 SmallVector<int, 8> Mask;
4195 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4196 Mask.push_back(i + Half);
4197 Mask.push_back(i + NumElems + Half);
4199 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4202 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4203 /// vector of zero or undef vector. This produces a shuffle where the low
4204 /// element of V2 is swizzled into the zero/undef vector, landing at element
4205 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4206 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4208 const X86Subtarget *Subtarget,
4209 SelectionDAG &DAG) {
4210 MVT VT = V2.getSimpleValueType();
4212 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4213 unsigned NumElems = VT.getVectorNumElements();
4214 SmallVector<int, 16> MaskVec;
4215 for (unsigned i = 0; i != NumElems; ++i)
4216 // If this is the insertion idx, put the low elt of V2 here.
4217 MaskVec.push_back(i == Idx ? NumElems : i);
4218 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4221 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4222 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4223 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4224 /// shuffles which use a single input multiple times, and in those cases it will
4225 /// adjust the mask to only have indices within that single input.
4226 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4227 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4228 unsigned NumElems = VT.getVectorNumElements();
4232 bool IsFakeUnary = false;
4233 switch(N->getOpcode()) {
4234 case X86ISD::BLENDI:
4235 ImmN = N->getOperand(N->getNumOperands()-1);
4236 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4239 ImmN = N->getOperand(N->getNumOperands()-1);
4240 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4241 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4243 case X86ISD::UNPCKH:
4244 DecodeUNPCKHMask(VT, Mask);
4245 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4247 case X86ISD::UNPCKL:
4248 DecodeUNPCKLMask(VT, Mask);
4249 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4251 case X86ISD::MOVHLPS:
4252 DecodeMOVHLPSMask(NumElems, Mask);
4253 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4255 case X86ISD::MOVLHPS:
4256 DecodeMOVLHPSMask(NumElems, Mask);
4257 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4259 case X86ISD::PALIGNR:
4260 ImmN = N->getOperand(N->getNumOperands()-1);
4261 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4263 case X86ISD::PSHUFD:
4264 case X86ISD::VPERMILPI:
4265 ImmN = N->getOperand(N->getNumOperands()-1);
4266 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4269 case X86ISD::PSHUFHW:
4270 ImmN = N->getOperand(N->getNumOperands()-1);
4271 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4274 case X86ISD::PSHUFLW:
4275 ImmN = N->getOperand(N->getNumOperands()-1);
4276 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4279 case X86ISD::PSHUFB: {
4281 SDValue MaskNode = N->getOperand(1);
4282 while (MaskNode->getOpcode() == ISD::BITCAST)
4283 MaskNode = MaskNode->getOperand(0);
4285 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4286 // If we have a build-vector, then things are easy.
4287 EVT VT = MaskNode.getValueType();
4288 assert(VT.isVector() &&
4289 "Can't produce a non-vector with a build_vector!");
4290 if (!VT.isInteger())
4293 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4295 SmallVector<uint64_t, 32> RawMask;
4296 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4297 SDValue Op = MaskNode->getOperand(i);
4298 if (Op->getOpcode() == ISD::UNDEF) {
4299 RawMask.push_back((uint64_t)SM_SentinelUndef);
4302 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4305 APInt MaskElement = CN->getAPIntValue();
4307 // We now have to decode the element which could be any integer size and
4308 // extract each byte of it.
4309 for (int j = 0; j < NumBytesPerElement; ++j) {
4310 // Note that this is x86 and so always little endian: the low byte is
4311 // the first byte of the mask.
4312 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4313 MaskElement = MaskElement.lshr(8);
4316 DecodePSHUFBMask(RawMask, Mask);
4320 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4324 SDValue Ptr = MaskLoad->getBasePtr();
4325 if (Ptr->getOpcode() == X86ISD::Wrapper)
4326 Ptr = Ptr->getOperand(0);
4328 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4329 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4332 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4333 DecodePSHUFBMask(C, Mask);
4341 case X86ISD::VPERMI:
4342 ImmN = N->getOperand(N->getNumOperands()-1);
4343 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4348 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4350 case X86ISD::VPERM2X128:
4351 ImmN = N->getOperand(N->getNumOperands()-1);
4352 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4353 if (Mask.empty()) return false;
4355 case X86ISD::MOVSLDUP:
4356 DecodeMOVSLDUPMask(VT, Mask);
4359 case X86ISD::MOVSHDUP:
4360 DecodeMOVSHDUPMask(VT, Mask);
4363 case X86ISD::MOVDDUP:
4364 DecodeMOVDDUPMask(VT, Mask);
4367 case X86ISD::MOVLHPD:
4368 case X86ISD::MOVLPD:
4369 case X86ISD::MOVLPS:
4370 // Not yet implemented
4372 default: llvm_unreachable("unknown target shuffle node");
4375 // If we have a fake unary shuffle, the shuffle mask is spread across two
4376 // inputs that are actually the same node. Re-map the mask to always point
4377 // into the first input.
4380 if (M >= (int)Mask.size())
4386 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4387 /// element of the result of the vector shuffle.
4388 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4391 return SDValue(); // Limit search depth.
4393 SDValue V = SDValue(N, 0);
4394 EVT VT = V.getValueType();
4395 unsigned Opcode = V.getOpcode();
4397 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4398 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4399 int Elt = SV->getMaskElt(Index);
4402 return DAG.getUNDEF(VT.getVectorElementType());
4404 unsigned NumElems = VT.getVectorNumElements();
4405 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4406 : SV->getOperand(1);
4407 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4410 // Recurse into target specific vector shuffles to find scalars.
4411 if (isTargetShuffle(Opcode)) {
4412 MVT ShufVT = V.getSimpleValueType();
4413 unsigned NumElems = ShufVT.getVectorNumElements();
4414 SmallVector<int, 16> ShuffleMask;
4417 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4420 int Elt = ShuffleMask[Index];
4422 return DAG.getUNDEF(ShufVT.getVectorElementType());
4424 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4426 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4430 // Actual nodes that may contain scalar elements
4431 if (Opcode == ISD::BITCAST) {
4432 V = V.getOperand(0);
4433 EVT SrcVT = V.getValueType();
4434 unsigned NumElems = VT.getVectorNumElements();
4436 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4440 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4441 return (Index == 0) ? V.getOperand(0)
4442 : DAG.getUNDEF(VT.getVectorElementType());
4444 if (V.getOpcode() == ISD::BUILD_VECTOR)
4445 return V.getOperand(Index);
4450 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4452 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4453 unsigned NumNonZero, unsigned NumZero,
4455 const X86Subtarget* Subtarget,
4456 const TargetLowering &TLI) {
4464 // SSE4.1 - use PINSRB to insert each byte directly.
4465 if (Subtarget->hasSSE41()) {
4466 for (unsigned i = 0; i < 16; ++i) {
4467 bool isNonZero = (NonZeros & (1 << i)) != 0;
4471 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4473 V = DAG.getUNDEF(MVT::v16i8);
4476 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4477 MVT::v16i8, V, Op.getOperand(i),
4478 DAG.getIntPtrConstant(i));
4485 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4486 for (unsigned i = 0; i < 16; ++i) {
4487 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4488 if (ThisIsNonZero && First) {
4490 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4492 V = DAG.getUNDEF(MVT::v8i16);
4497 SDValue ThisElt, LastElt;
4498 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4499 if (LastIsNonZero) {
4500 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4501 MVT::i16, Op.getOperand(i-1));
4503 if (ThisIsNonZero) {
4504 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4505 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4506 ThisElt, DAG.getConstant(8, MVT::i8));
4508 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4512 if (ThisElt.getNode())
4513 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4514 DAG.getIntPtrConstant(i/2));
4518 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4521 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4523 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4524 unsigned NumNonZero, unsigned NumZero,
4526 const X86Subtarget* Subtarget,
4527 const TargetLowering &TLI) {
4534 for (unsigned i = 0; i < 8; ++i) {
4535 bool isNonZero = (NonZeros & (1 << i)) != 0;
4539 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4541 V = DAG.getUNDEF(MVT::v8i16);
4544 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4545 MVT::v8i16, V, Op.getOperand(i),
4546 DAG.getIntPtrConstant(i));
4553 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4554 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4555 const X86Subtarget *Subtarget,
4556 const TargetLowering &TLI) {
4557 // Find all zeroable elements.
4558 std::bitset<4> Zeroable;
4559 for (int i=0; i < 4; ++i) {
4560 SDValue Elt = Op->getOperand(i);
4561 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4563 assert(Zeroable.size() - Zeroable.count() > 1 &&
4564 "We expect at least two non-zero elements!");
4566 // We only know how to deal with build_vector nodes where elements are either
4567 // zeroable or extract_vector_elt with constant index.
4568 SDValue FirstNonZero;
4569 unsigned FirstNonZeroIdx;
4570 for (unsigned i=0; i < 4; ++i) {
4573 SDValue Elt = Op->getOperand(i);
4574 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4575 !isa<ConstantSDNode>(Elt.getOperand(1)))
4577 // Make sure that this node is extracting from a 128-bit vector.
4578 MVT VT = Elt.getOperand(0).getSimpleValueType();
4579 if (!VT.is128BitVector())
4581 if (!FirstNonZero.getNode()) {
4583 FirstNonZeroIdx = i;
4587 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4588 SDValue V1 = FirstNonZero.getOperand(0);
4589 MVT VT = V1.getSimpleValueType();
4591 // See if this build_vector can be lowered as a blend with zero.
4593 unsigned EltMaskIdx, EltIdx;
4595 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4596 if (Zeroable[EltIdx]) {
4597 // The zero vector will be on the right hand side.
4598 Mask[EltIdx] = EltIdx+4;
4602 Elt = Op->getOperand(EltIdx);
4603 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4604 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4605 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4607 Mask[EltIdx] = EltIdx;
4611 // Let the shuffle legalizer deal with blend operations.
4612 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4613 if (V1.getSimpleValueType() != VT)
4614 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4615 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4618 // See if we can lower this build_vector to a INSERTPS.
4619 if (!Subtarget->hasSSE41())
4622 SDValue V2 = Elt.getOperand(0);
4623 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4626 bool CanFold = true;
4627 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4631 SDValue Current = Op->getOperand(i);
4632 SDValue SrcVector = Current->getOperand(0);
4635 CanFold = SrcVector == V1 &&
4636 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4642 assert(V1.getNode() && "Expected at least two non-zero elements!");
4643 if (V1.getSimpleValueType() != MVT::v4f32)
4644 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4645 if (V2.getSimpleValueType() != MVT::v4f32)
4646 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4648 // Ok, we can emit an INSERTPS instruction.
4649 unsigned ZMask = Zeroable.to_ulong();
4651 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4652 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4653 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
4654 DAG.getIntPtrConstant(InsertPSMask));
4655 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
4658 /// Return a vector logical shift node.
4659 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4660 unsigned NumBits, SelectionDAG &DAG,
4661 const TargetLowering &TLI, SDLoc dl) {
4662 assert(VT.is128BitVector() && "Unknown type for VShift");
4663 MVT ShVT = MVT::v2i64;
4664 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4665 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4666 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4667 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4668 SDValue ShiftVal = DAG.getConstant(NumBits/8, ScalarShiftTy);
4669 return DAG.getNode(ISD::BITCAST, dl, VT,
4670 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4674 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4676 // Check if the scalar load can be widened into a vector load. And if
4677 // the address is "base + cst" see if the cst can be "absorbed" into
4678 // the shuffle mask.
4679 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4680 SDValue Ptr = LD->getBasePtr();
4681 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4683 EVT PVT = LD->getValueType(0);
4684 if (PVT != MVT::i32 && PVT != MVT::f32)
4689 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4690 FI = FINode->getIndex();
4692 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4693 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4694 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4695 Offset = Ptr.getConstantOperandVal(1);
4696 Ptr = Ptr.getOperand(0);
4701 // FIXME: 256-bit vector instructions don't require a strict alignment,
4702 // improve this code to support it better.
4703 unsigned RequiredAlign = VT.getSizeInBits()/8;
4704 SDValue Chain = LD->getChain();
4705 // Make sure the stack object alignment is at least 16 or 32.
4706 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4707 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4708 if (MFI->isFixedObjectIndex(FI)) {
4709 // Can't change the alignment. FIXME: It's possible to compute
4710 // the exact stack offset and reference FI + adjust offset instead.
4711 // If someone *really* cares about this. That's the way to implement it.
4714 MFI->setObjectAlignment(FI, RequiredAlign);
4718 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4719 // Ptr + (Offset & ~15).
4722 if ((Offset % RequiredAlign) & 3)
4724 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4726 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
4727 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4729 int EltNo = (Offset - StartOffset) >> 2;
4730 unsigned NumElems = VT.getVectorNumElements();
4732 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4733 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4734 LD->getPointerInfo().getWithOffset(StartOffset),
4735 false, false, false, 0);
4737 SmallVector<int, 8> Mask(NumElems, EltNo);
4739 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4745 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4746 /// elements can be replaced by a single large load which has the same value as
4747 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4749 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4751 /// FIXME: we'd also like to handle the case where the last elements are zero
4752 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4753 /// There's even a handy isZeroNode for that purpose.
4754 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4755 SDLoc &DL, SelectionDAG &DAG,
4756 bool isAfterLegalize) {
4757 unsigned NumElems = Elts.size();
4759 LoadSDNode *LDBase = nullptr;
4760 unsigned LastLoadedElt = -1U;
4762 // For each element in the initializer, see if we've found a load or an undef.
4763 // If we don't find an initial load element, or later load elements are
4764 // non-consecutive, bail out.
4765 for (unsigned i = 0; i < NumElems; ++i) {
4766 SDValue Elt = Elts[i];
4767 // Look through a bitcast.
4768 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4769 Elt = Elt.getOperand(0);
4770 if (!Elt.getNode() ||
4771 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4774 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4776 LDBase = cast<LoadSDNode>(Elt.getNode());
4780 if (Elt.getOpcode() == ISD::UNDEF)
4783 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4784 EVT LdVT = Elt.getValueType();
4785 // Each loaded element must be the correct fractional portion of the
4786 // requested vector load.
4787 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4789 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4794 // If we have found an entire vector of loads and undefs, then return a large
4795 // load of the entire vector width starting at the base pointer. If we found
4796 // consecutive loads for the low half, generate a vzext_load node.
4797 if (LastLoadedElt == NumElems - 1) {
4798 assert(LDBase && "Did not find base load for merging consecutive loads");
4799 EVT EltVT = LDBase->getValueType(0);
4800 // Ensure that the input vector size for the merged loads matches the
4801 // cumulative size of the input elements.
4802 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4805 if (isAfterLegalize &&
4806 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4809 SDValue NewLd = SDValue();
4811 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4812 LDBase->getPointerInfo(), LDBase->isVolatile(),
4813 LDBase->isNonTemporal(), LDBase->isInvariant(),
4814 LDBase->getAlignment());
4816 if (LDBase->hasAnyUseOfValue(1)) {
4817 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4819 SDValue(NewLd.getNode(), 1));
4820 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4821 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4822 SDValue(NewLd.getNode(), 1));
4828 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4829 //of a v4i32 / v4f32. It's probably worth generalizing.
4830 EVT EltVT = VT.getVectorElementType();
4831 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4832 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4833 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4834 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4836 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4837 LDBase->getPointerInfo(),
4838 LDBase->getAlignment(),
4839 false/*isVolatile*/, true/*ReadMem*/,
4842 // Make sure the newly-created LOAD is in the same position as LDBase in
4843 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4844 // update uses of LDBase's output chain to use the TokenFactor.
4845 if (LDBase->hasAnyUseOfValue(1)) {
4846 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4847 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4848 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4849 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4850 SDValue(ResNode.getNode(), 1));
4853 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4858 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4859 /// to generate a splat value for the following cases:
4860 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4861 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4862 /// a scalar load, or a constant.
4863 /// The VBROADCAST node is returned when a pattern is found,
4864 /// or SDValue() otherwise.
4865 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4866 SelectionDAG &DAG) {
4867 // VBROADCAST requires AVX.
4868 // TODO: Splats could be generated for non-AVX CPUs using SSE
4869 // instructions, but there's less potential gain for only 128-bit vectors.
4870 if (!Subtarget->hasAVX())
4873 MVT VT = Op.getSimpleValueType();
4876 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4877 "Unsupported vector type for broadcast.");
4882 switch (Op.getOpcode()) {
4884 // Unknown pattern found.
4887 case ISD::BUILD_VECTOR: {
4888 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4889 BitVector UndefElements;
4890 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4892 // We need a splat of a single value to use broadcast, and it doesn't
4893 // make any sense if the value is only in one element of the vector.
4894 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4898 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4899 Ld.getOpcode() == ISD::ConstantFP);
4901 // Make sure that all of the users of a non-constant load are from the
4902 // BUILD_VECTOR node.
4903 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4908 case ISD::VECTOR_SHUFFLE: {
4909 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4911 // Shuffles must have a splat mask where the first element is
4913 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4916 SDValue Sc = Op.getOperand(0);
4917 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4918 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4920 if (!Subtarget->hasInt256())
4923 // Use the register form of the broadcast instruction available on AVX2.
4924 if (VT.getSizeInBits() >= 256)
4925 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4926 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4929 Ld = Sc.getOperand(0);
4930 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4931 Ld.getOpcode() == ISD::ConstantFP);
4933 // The scalar_to_vector node and the suspected
4934 // load node must have exactly one user.
4935 // Constants may have multiple users.
4937 // AVX-512 has register version of the broadcast
4938 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
4939 Ld.getValueType().getSizeInBits() >= 32;
4940 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
4947 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4948 bool IsGE256 = (VT.getSizeInBits() >= 256);
4950 // When optimizing for size, generate up to 5 extra bytes for a broadcast
4951 // instruction to save 8 or more bytes of constant pool data.
4952 // TODO: If multiple splats are generated to load the same constant,
4953 // it may be detrimental to overall size. There needs to be a way to detect
4954 // that condition to know if this is truly a size win.
4955 const Function *F = DAG.getMachineFunction().getFunction();
4956 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
4958 // Handle broadcasting a single constant scalar from the constant pool
4960 // On Sandybridge (no AVX2), it is still better to load a constant vector
4961 // from the constant pool and not to broadcast it from a scalar.
4962 // But override that restriction when optimizing for size.
4963 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
4964 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
4965 EVT CVT = Ld.getValueType();
4966 assert(!CVT.isVector() && "Must not broadcast a vector type");
4968 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
4969 // For size optimization, also splat v2f64 and v2i64, and for size opt
4970 // with AVX2, also splat i8 and i16.
4971 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
4972 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
4973 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
4974 const Constant *C = nullptr;
4975 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4976 C = CI->getConstantIntValue();
4977 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4978 C = CF->getConstantFPValue();
4980 assert(C && "Invalid constant type");
4982 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4983 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
4984 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4985 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4986 MachinePointerInfo::getConstantPool(),
4987 false, false, false, Alignment);
4989 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4993 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
4995 // Handle AVX2 in-register broadcasts.
4996 if (!IsLoad && Subtarget->hasInt256() &&
4997 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
4998 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5000 // The scalar source must be a normal load.
5004 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5005 (Subtarget->hasVLX() && ScalarSize == 64))
5006 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5008 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5009 // double since there is no vbroadcastsd xmm
5010 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5011 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5012 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5015 // Unsupported broadcast.
5019 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5020 /// underlying vector and index.
5022 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5024 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5026 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5027 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5030 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5032 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5034 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5035 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5038 // In this case the vector is the extract_subvector expression and the index
5039 // is 2, as specified by the shuffle.
5040 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5041 SDValue ShuffleVec = SVOp->getOperand(0);
5042 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5043 assert(ShuffleVecVT.getVectorElementType() ==
5044 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5046 int ShuffleIdx = SVOp->getMaskElt(Idx);
5047 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5048 ExtractedFromVec = ShuffleVec;
5054 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5055 MVT VT = Op.getSimpleValueType();
5057 // Skip if insert_vec_elt is not supported.
5058 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5059 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5063 unsigned NumElems = Op.getNumOperands();
5067 SmallVector<unsigned, 4> InsertIndices;
5068 SmallVector<int, 8> Mask(NumElems, -1);
5070 for (unsigned i = 0; i != NumElems; ++i) {
5071 unsigned Opc = Op.getOperand(i).getOpcode();
5073 if (Opc == ISD::UNDEF)
5076 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5077 // Quit if more than 1 elements need inserting.
5078 if (InsertIndices.size() > 1)
5081 InsertIndices.push_back(i);
5085 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5086 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5087 // Quit if non-constant index.
5088 if (!isa<ConstantSDNode>(ExtIdx))
5090 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5092 // Quit if extracted from vector of different type.
5093 if (ExtractedFromVec.getValueType() != VT)
5096 if (!VecIn1.getNode())
5097 VecIn1 = ExtractedFromVec;
5098 else if (VecIn1 != ExtractedFromVec) {
5099 if (!VecIn2.getNode())
5100 VecIn2 = ExtractedFromVec;
5101 else if (VecIn2 != ExtractedFromVec)
5102 // Quit if more than 2 vectors to shuffle
5106 if (ExtractedFromVec == VecIn1)
5108 else if (ExtractedFromVec == VecIn2)
5109 Mask[i] = Idx + NumElems;
5112 if (!VecIn1.getNode())
5115 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5116 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5117 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5118 unsigned Idx = InsertIndices[i];
5119 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5120 DAG.getIntPtrConstant(Idx));
5126 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5128 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5130 MVT VT = Op.getSimpleValueType();
5131 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5132 "Unexpected type in LowerBUILD_VECTORvXi1!");
5135 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5136 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5137 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5138 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5141 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5142 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5143 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5144 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5147 bool AllContants = true;
5148 uint64_t Immediate = 0;
5149 int NonConstIdx = -1;
5150 bool IsSplat = true;
5151 unsigned NumNonConsts = 0;
5152 unsigned NumConsts = 0;
5153 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5154 SDValue In = Op.getOperand(idx);
5155 if (In.getOpcode() == ISD::UNDEF)
5157 if (!isa<ConstantSDNode>(In)) {
5158 AllContants = false;
5163 if (cast<ConstantSDNode>(In)->getZExtValue())
5164 Immediate |= (1ULL << idx);
5166 if (In != Op.getOperand(0))
5171 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5172 DAG.getConstant(Immediate, MVT::i16));
5173 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5174 DAG.getIntPtrConstant(0));
5177 if (NumNonConsts == 1 && NonConstIdx != 0) {
5180 SDValue VecAsImm = DAG.getConstant(Immediate,
5181 MVT::getIntegerVT(VT.getSizeInBits()));
5182 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5185 DstVec = DAG.getUNDEF(VT);
5186 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5187 Op.getOperand(NonConstIdx),
5188 DAG.getIntPtrConstant(NonConstIdx));
5190 if (!IsSplat && (NonConstIdx != 0))
5191 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5192 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5195 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5196 DAG.getConstant(-1, SelectVT),
5197 DAG.getConstant(0, SelectVT));
5199 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5200 DAG.getConstant((Immediate | 1), SelectVT),
5201 DAG.getConstant(Immediate, SelectVT));
5202 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5205 /// \brief Return true if \p N implements a horizontal binop and return the
5206 /// operands for the horizontal binop into V0 and V1.
5208 /// This is a helper function of PerformBUILD_VECTORCombine.
5209 /// This function checks that the build_vector \p N in input implements a
5210 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5211 /// operation to match.
5212 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5213 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5214 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5217 /// This function only analyzes elements of \p N whose indices are
5218 /// in range [BaseIdx, LastIdx).
5219 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5221 unsigned BaseIdx, unsigned LastIdx,
5222 SDValue &V0, SDValue &V1) {
5223 EVT VT = N->getValueType(0);
5225 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5226 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5227 "Invalid Vector in input!");
5229 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5230 bool CanFold = true;
5231 unsigned ExpectedVExtractIdx = BaseIdx;
5232 unsigned NumElts = LastIdx - BaseIdx;
5233 V0 = DAG.getUNDEF(VT);
5234 V1 = DAG.getUNDEF(VT);
5236 // Check if N implements a horizontal binop.
5237 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5238 SDValue Op = N->getOperand(i + BaseIdx);
5241 if (Op->getOpcode() == ISD::UNDEF) {
5242 // Update the expected vector extract index.
5243 if (i * 2 == NumElts)
5244 ExpectedVExtractIdx = BaseIdx;
5245 ExpectedVExtractIdx += 2;
5249 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5254 SDValue Op0 = Op.getOperand(0);
5255 SDValue Op1 = Op.getOperand(1);
5257 // Try to match the following pattern:
5258 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5259 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5260 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5261 Op0.getOperand(0) == Op1.getOperand(0) &&
5262 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5263 isa<ConstantSDNode>(Op1.getOperand(1)));
5267 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5268 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5270 if (i * 2 < NumElts) {
5271 if (V0.getOpcode() == ISD::UNDEF)
5272 V0 = Op0.getOperand(0);
5274 if (V1.getOpcode() == ISD::UNDEF)
5275 V1 = Op0.getOperand(0);
5276 if (i * 2 == NumElts)
5277 ExpectedVExtractIdx = BaseIdx;
5280 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5281 if (I0 == ExpectedVExtractIdx)
5282 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5283 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5284 // Try to match the following dag sequence:
5285 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5286 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5290 ExpectedVExtractIdx += 2;
5296 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5297 /// a concat_vector.
5299 /// This is a helper function of PerformBUILD_VECTORCombine.
5300 /// This function expects two 256-bit vectors called V0 and V1.
5301 /// At first, each vector is split into two separate 128-bit vectors.
5302 /// Then, the resulting 128-bit vectors are used to implement two
5303 /// horizontal binary operations.
5305 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5307 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5308 /// the two new horizontal binop.
5309 /// When Mode is set, the first horizontal binop dag node would take as input
5310 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5311 /// horizontal binop dag node would take as input the lower 128-bit of V1
5312 /// and the upper 128-bit of V1.
5314 /// HADD V0_LO, V0_HI
5315 /// HADD V1_LO, V1_HI
5317 /// Otherwise, the first horizontal binop dag node takes as input the lower
5318 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5319 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5321 /// HADD V0_LO, V1_LO
5322 /// HADD V0_HI, V1_HI
5324 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5325 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5326 /// the upper 128-bits of the result.
5327 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5328 SDLoc DL, SelectionDAG &DAG,
5329 unsigned X86Opcode, bool Mode,
5330 bool isUndefLO, bool isUndefHI) {
5331 EVT VT = V0.getValueType();
5332 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5333 "Invalid nodes in input!");
5335 unsigned NumElts = VT.getVectorNumElements();
5336 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5337 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5338 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5339 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5340 EVT NewVT = V0_LO.getValueType();
5342 SDValue LO = DAG.getUNDEF(NewVT);
5343 SDValue HI = DAG.getUNDEF(NewVT);
5346 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5347 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5348 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5349 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5350 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5352 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5353 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5354 V1_LO->getOpcode() != ISD::UNDEF))
5355 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5357 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5358 V1_HI->getOpcode() != ISD::UNDEF))
5359 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5362 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5365 /// \brief Try to fold a build_vector that performs an 'addsub' into the
5366 /// sequence of 'vadd + vsub + blendi'.
5367 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
5368 const X86Subtarget *Subtarget) {
5370 EVT VT = BV->getValueType(0);
5371 unsigned NumElts = VT.getVectorNumElements();
5372 SDValue InVec0 = DAG.getUNDEF(VT);
5373 SDValue InVec1 = DAG.getUNDEF(VT);
5375 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5376 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5378 // Odd-numbered elements in the input build vector are obtained from
5379 // adding two integer/float elements.
5380 // Even-numbered elements in the input build vector are obtained from
5381 // subtracting two integer/float elements.
5382 unsigned ExpectedOpcode = ISD::FSUB;
5383 unsigned NextExpectedOpcode = ISD::FADD;
5384 bool AddFound = false;
5385 bool SubFound = false;
5387 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5388 SDValue Op = BV->getOperand(i);
5390 // Skip 'undef' values.
5391 unsigned Opcode = Op.getOpcode();
5392 if (Opcode == ISD::UNDEF) {
5393 std::swap(ExpectedOpcode, NextExpectedOpcode);
5397 // Early exit if we found an unexpected opcode.
5398 if (Opcode != ExpectedOpcode)
5401 SDValue Op0 = Op.getOperand(0);
5402 SDValue Op1 = Op.getOperand(1);
5404 // Try to match the following pattern:
5405 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5406 // Early exit if we cannot match that sequence.
5407 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5408 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5409 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5410 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5411 Op0.getOperand(1) != Op1.getOperand(1))
5414 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5418 // We found a valid add/sub node. Update the information accordingly.
5424 // Update InVec0 and InVec1.
5425 if (InVec0.getOpcode() == ISD::UNDEF)
5426 InVec0 = Op0.getOperand(0);
5427 if (InVec1.getOpcode() == ISD::UNDEF)
5428 InVec1 = Op1.getOperand(0);
5430 // Make sure that operands in input to each add/sub node always
5431 // come from a same pair of vectors.
5432 if (InVec0 != Op0.getOperand(0)) {
5433 if (ExpectedOpcode == ISD::FSUB)
5436 // FADD is commutable. Try to commute the operands
5437 // and then test again.
5438 std::swap(Op0, Op1);
5439 if (InVec0 != Op0.getOperand(0))
5443 if (InVec1 != Op1.getOperand(0))
5446 // Update the pair of expected opcodes.
5447 std::swap(ExpectedOpcode, NextExpectedOpcode);
5450 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5451 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5452 InVec1.getOpcode() != ISD::UNDEF)
5453 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5458 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
5459 const X86Subtarget *Subtarget) {
5461 EVT VT = N->getValueType(0);
5462 unsigned NumElts = VT.getVectorNumElements();
5463 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
5464 SDValue InVec0, InVec1;
5466 // Try to match an ADDSUB.
5467 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
5468 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
5469 SDValue Value = matchAddSub(BV, DAG, Subtarget);
5470 if (Value.getNode())
5474 // Try to match horizontal ADD/SUB.
5475 unsigned NumUndefsLO = 0;
5476 unsigned NumUndefsHI = 0;
5477 unsigned Half = NumElts/2;
5479 // Count the number of UNDEF operands in the build_vector in input.
5480 for (unsigned i = 0, e = Half; i != e; ++i)
5481 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5484 for (unsigned i = Half, e = NumElts; i != e; ++i)
5485 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5488 // Early exit if this is either a build_vector of all UNDEFs or all the
5489 // operands but one are UNDEF.
5490 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5493 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5494 // Try to match an SSE3 float HADD/HSUB.
5495 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5496 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5498 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5499 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5500 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5501 // Try to match an SSSE3 integer HADD/HSUB.
5502 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5503 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5505 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5506 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5509 if (!Subtarget->hasAVX())
5512 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5513 // Try to match an AVX horizontal add/sub of packed single/double
5514 // precision floating point values from 256-bit vectors.
5515 SDValue InVec2, InVec3;
5516 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5517 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5518 ((InVec0.getOpcode() == ISD::UNDEF ||
5519 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5520 ((InVec1.getOpcode() == ISD::UNDEF ||
5521 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5522 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5524 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5525 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5526 ((InVec0.getOpcode() == ISD::UNDEF ||
5527 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5528 ((InVec1.getOpcode() == ISD::UNDEF ||
5529 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5530 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5531 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5532 // Try to match an AVX2 horizontal add/sub of signed integers.
5533 SDValue InVec2, InVec3;
5535 bool CanFold = true;
5537 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5538 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5539 ((InVec0.getOpcode() == ISD::UNDEF ||
5540 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5541 ((InVec1.getOpcode() == ISD::UNDEF ||
5542 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5543 X86Opcode = X86ISD::HADD;
5544 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5545 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5546 ((InVec0.getOpcode() == ISD::UNDEF ||
5547 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5548 ((InVec1.getOpcode() == ISD::UNDEF ||
5549 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5550 X86Opcode = X86ISD::HSUB;
5555 // Fold this build_vector into a single horizontal add/sub.
5556 // Do this only if the target has AVX2.
5557 if (Subtarget->hasAVX2())
5558 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5560 // Do not try to expand this build_vector into a pair of horizontal
5561 // add/sub if we can emit a pair of scalar add/sub.
5562 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5565 // Convert this build_vector into a pair of horizontal binop followed by
5567 bool isUndefLO = NumUndefsLO == Half;
5568 bool isUndefHI = NumUndefsHI == Half;
5569 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5570 isUndefLO, isUndefHI);
5574 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5575 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5577 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5578 X86Opcode = X86ISD::HADD;
5579 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5580 X86Opcode = X86ISD::HSUB;
5581 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5582 X86Opcode = X86ISD::FHADD;
5583 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5584 X86Opcode = X86ISD::FHSUB;
5588 // Don't try to expand this build_vector into a pair of horizontal add/sub
5589 // if we can simply emit a pair of scalar add/sub.
5590 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5593 // Convert this build_vector into two horizontal add/sub followed by
5595 bool isUndefLO = NumUndefsLO == Half;
5596 bool isUndefHI = NumUndefsHI == Half;
5597 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5598 isUndefLO, isUndefHI);
5605 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5608 MVT VT = Op.getSimpleValueType();
5609 MVT ExtVT = VT.getVectorElementType();
5610 unsigned NumElems = Op.getNumOperands();
5612 // Generate vectors for predicate vectors.
5613 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5614 return LowerBUILD_VECTORvXi1(Op, DAG);
5616 // Vectors containing all zeros can be matched by pxor and xorps later
5617 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5618 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5619 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5620 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5623 return getZeroVector(VT, Subtarget, DAG, dl);
5626 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5627 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5628 // vpcmpeqd on 256-bit vectors.
5629 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5630 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5633 if (!VT.is512BitVector())
5634 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5637 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5640 unsigned EVTBits = ExtVT.getSizeInBits();
5642 unsigned NumZero = 0;
5643 unsigned NumNonZero = 0;
5644 unsigned NonZeros = 0;
5645 bool IsAllConstants = true;
5646 SmallSet<SDValue, 8> Values;
5647 for (unsigned i = 0; i < NumElems; ++i) {
5648 SDValue Elt = Op.getOperand(i);
5649 if (Elt.getOpcode() == ISD::UNDEF)
5652 if (Elt.getOpcode() != ISD::Constant &&
5653 Elt.getOpcode() != ISD::ConstantFP)
5654 IsAllConstants = false;
5655 if (X86::isZeroNode(Elt))
5658 NonZeros |= (1 << i);
5663 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5664 if (NumNonZero == 0)
5665 return DAG.getUNDEF(VT);
5667 // Special case for single non-zero, non-undef, element.
5668 if (NumNonZero == 1) {
5669 unsigned Idx = countTrailingZeros(NonZeros);
5670 SDValue Item = Op.getOperand(Idx);
5672 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5673 // the value are obviously zero, truncate the value to i32 and do the
5674 // insertion that way. Only do this if the value is non-constant or if the
5675 // value is a constant being inserted into element 0. It is cheaper to do
5676 // a constant pool load than it is to do a movd + shuffle.
5677 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5678 (!IsAllConstants || Idx == 0)) {
5679 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5681 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5682 EVT VecVT = MVT::v4i32;
5684 // Truncate the value (which may itself be a constant) to i32, and
5685 // convert it to a vector with movd (S2V+shuffle to zero extend).
5686 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5687 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5689 ISD::BITCAST, dl, VT,
5690 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5694 // If we have a constant or non-constant insertion into the low element of
5695 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5696 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5697 // depending on what the source datatype is.
5700 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5702 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5703 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5704 if (VT.is512BitVector()) {
5705 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5706 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5707 Item, DAG.getIntPtrConstant(0));
5709 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5710 "Expected an SSE value type!");
5711 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5712 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5713 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5716 // We can't directly insert an i8 or i16 into a vector, so zero extend
5718 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5719 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5720 if (VT.is256BitVector()) {
5721 if (Subtarget->hasAVX()) {
5722 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5723 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5725 // Without AVX, we need to extend to a 128-bit vector and then
5726 // insert into the 256-bit vector.
5727 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5728 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5729 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5732 assert(VT.is128BitVector() && "Expected an SSE value type!");
5733 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5734 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5736 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5740 // Is it a vector logical left shift?
5741 if (NumElems == 2 && Idx == 1 &&
5742 X86::isZeroNode(Op.getOperand(0)) &&
5743 !X86::isZeroNode(Op.getOperand(1))) {
5744 unsigned NumBits = VT.getSizeInBits();
5745 return getVShift(true, VT,
5746 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5747 VT, Op.getOperand(1)),
5748 NumBits/2, DAG, *this, dl);
5751 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5754 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5755 // is a non-constant being inserted into an element other than the low one,
5756 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5757 // movd/movss) to move this into the low element, then shuffle it into
5759 if (EVTBits == 32) {
5760 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5761 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5765 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5766 if (Values.size() == 1) {
5767 if (EVTBits == 32) {
5768 // Instead of a shuffle like this:
5769 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5770 // Check if it's possible to issue this instead.
5771 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5772 unsigned Idx = countTrailingZeros(NonZeros);
5773 SDValue Item = Op.getOperand(Idx);
5774 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5775 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5780 // A vector full of immediates; various special cases are already
5781 // handled, so this is best done with a single constant-pool load.
5785 // For AVX-length vectors, see if we can use a vector load to get all of the
5786 // elements, otherwise build the individual 128-bit pieces and use
5787 // shuffles to put them in place.
5788 if (VT.is256BitVector() || VT.is512BitVector()) {
5789 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5791 // Check for a build vector of consecutive loads.
5792 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5795 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5797 // Build both the lower and upper subvector.
5798 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5799 makeArrayRef(&V[0], NumElems/2));
5800 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5801 makeArrayRef(&V[NumElems / 2], NumElems/2));
5803 // Recreate the wider vector with the lower and upper part.
5804 if (VT.is256BitVector())
5805 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5806 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5809 // Let legalizer expand 2-wide build_vectors.
5810 if (EVTBits == 64) {
5811 if (NumNonZero == 1) {
5812 // One half is zero or undef.
5813 unsigned Idx = countTrailingZeros(NonZeros);
5814 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5815 Op.getOperand(Idx));
5816 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5821 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5822 if (EVTBits == 8 && NumElems == 16)
5823 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5827 if (EVTBits == 16 && NumElems == 8)
5828 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5832 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5833 if (EVTBits == 32 && NumElems == 4)
5834 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5837 // If element VT is == 32 bits, turn it into a number of shuffles.
5838 SmallVector<SDValue, 8> V(NumElems);
5839 if (NumElems == 4 && NumZero > 0) {
5840 for (unsigned i = 0; i < 4; ++i) {
5841 bool isZero = !(NonZeros & (1 << i));
5843 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5845 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5848 for (unsigned i = 0; i < 2; ++i) {
5849 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5852 V[i] = V[i*2]; // Must be a zero vector.
5855 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5858 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5861 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5866 bool Reverse1 = (NonZeros & 0x3) == 2;
5867 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5871 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5872 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5874 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5877 if (Values.size() > 1 && VT.is128BitVector()) {
5878 // Check for a build vector of consecutive loads.
5879 for (unsigned i = 0; i < NumElems; ++i)
5880 V[i] = Op.getOperand(i);
5882 // Check for elements which are consecutive loads.
5883 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5886 // Check for a build vector from mostly shuffle plus few inserting.
5887 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
5890 // For SSE 4.1, use insertps to put the high elements into the low element.
5891 if (Subtarget->hasSSE41()) {
5893 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5894 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5896 Result = DAG.getUNDEF(VT);
5898 for (unsigned i = 1; i < NumElems; ++i) {
5899 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5900 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5901 Op.getOperand(i), DAG.getIntPtrConstant(i));
5906 // Otherwise, expand into a number of unpckl*, start by extending each of
5907 // our (non-undef) elements to the full vector width with the element in the
5908 // bottom slot of the vector (which generates no code for SSE).
5909 for (unsigned i = 0; i < NumElems; ++i) {
5910 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5911 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5913 V[i] = DAG.getUNDEF(VT);
5916 // Next, we iteratively mix elements, e.g. for v4f32:
5917 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5918 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5919 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5920 unsigned EltStride = NumElems >> 1;
5921 while (EltStride != 0) {
5922 for (unsigned i = 0; i < EltStride; ++i) {
5923 // If V[i+EltStride] is undef and this is the first round of mixing,
5924 // then it is safe to just drop this shuffle: V[i] is already in the
5925 // right place, the one element (since it's the first round) being
5926 // inserted as undef can be dropped. This isn't safe for successive
5927 // rounds because they will permute elements within both vectors.
5928 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5929 EltStride == NumElems/2)
5932 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5941 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5942 // to create 256-bit vectors from two other 128-bit ones.
5943 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5945 MVT ResVT = Op.getSimpleValueType();
5947 assert((ResVT.is256BitVector() ||
5948 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
5950 SDValue V1 = Op.getOperand(0);
5951 SDValue V2 = Op.getOperand(1);
5952 unsigned NumElems = ResVT.getVectorNumElements();
5953 if (ResVT.is256BitVector())
5954 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5956 if (Op.getNumOperands() == 4) {
5957 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5958 ResVT.getVectorNumElements()/2);
5959 SDValue V3 = Op.getOperand(2);
5960 SDValue V4 = Op.getOperand(3);
5961 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
5962 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
5964 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5967 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
5968 const X86Subtarget *Subtarget,
5969 SelectionDAG & DAG) {
5971 MVT ResVT = Op.getSimpleValueType();
5972 unsigned NumOfOperands = Op.getNumOperands();
5974 assert(isPowerOf2_32(NumOfOperands) &&
5975 "Unexpected number of operands in CONCAT_VECTORS");
5977 if (NumOfOperands > 2) {
5978 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5979 ResVT.getVectorNumElements()/2);
5980 SmallVector<SDValue, 2> Ops;
5981 for (unsigned i = 0; i < NumOfOperands/2; i++)
5982 Ops.push_back(Op.getOperand(i));
5983 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
5985 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
5986 Ops.push_back(Op.getOperand(i));
5987 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
5988 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
5991 SDValue V1 = Op.getOperand(0);
5992 SDValue V2 = Op.getOperand(1);
5993 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
5994 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
5996 if (IsZeroV1 && IsZeroV2)
5997 return getZeroVector(ResVT, Subtarget, DAG, dl);
5999 SDValue ZeroIdx = DAG.getIntPtrConstant(0);
6000 SDValue Undef = DAG.getUNDEF(ResVT);
6001 unsigned NumElems = ResVT.getVectorNumElements();
6002 SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);
6004 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6005 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6009 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6010 // Zero the upper bits of V1
6011 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6012 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6015 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6018 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6019 const X86Subtarget *Subtarget,
6020 SelectionDAG &DAG) {
6021 MVT VT = Op.getSimpleValueType();
6022 if (VT.getVectorElementType() == MVT::i1)
6023 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6025 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6026 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6027 Op.getNumOperands() == 4)));
6029 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6030 // from two other 128-bit ones.
6032 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6033 return LowerAVXCONCAT_VECTORS(Op, DAG);
6037 //===----------------------------------------------------------------------===//
6038 // Vector shuffle lowering
6040 // This is an experimental code path for lowering vector shuffles on x86. It is
6041 // designed to handle arbitrary vector shuffles and blends, gracefully
6042 // degrading performance as necessary. It works hard to recognize idiomatic
6043 // shuffles and lower them to optimal instruction patterns without leaving
6044 // a framework that allows reasonably efficient handling of all vector shuffle
6046 //===----------------------------------------------------------------------===//
6048 /// \brief Tiny helper function to identify a no-op mask.
6050 /// This is a somewhat boring predicate function. It checks whether the mask
6051 /// array input, which is assumed to be a single-input shuffle mask of the kind
6052 /// used by the X86 shuffle instructions (not a fully general
6053 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6054 /// in-place shuffle are 'no-op's.
6055 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6056 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6057 if (Mask[i] != -1 && Mask[i] != i)
6062 /// \brief Helper function to classify a mask as a single-input mask.
6064 /// This isn't a generic single-input test because in the vector shuffle
6065 /// lowering we canonicalize single inputs to be the first input operand. This
6066 /// means we can more quickly test for a single input by only checking whether
6067 /// an input from the second operand exists. We also assume that the size of
6068 /// mask corresponds to the size of the input vectors which isn't true in the
6069 /// fully general case.
6070 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6072 if (M >= (int)Mask.size())
6077 /// \brief Test whether there are elements crossing 128-bit lanes in this
6080 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6081 /// and we routinely test for these.
6082 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6083 int LaneSize = 128 / VT.getScalarSizeInBits();
6084 int Size = Mask.size();
6085 for (int i = 0; i < Size; ++i)
6086 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6091 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6093 /// This checks a shuffle mask to see if it is performing the same
6094 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6095 /// that it is also not lane-crossing. It may however involve a blend from the
6096 /// same lane of a second vector.
6098 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6099 /// non-trivial to compute in the face of undef lanes. The representation is
6100 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6101 /// entries from both V1 and V2 inputs to the wider mask.
6103 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6104 SmallVectorImpl<int> &RepeatedMask) {
6105 int LaneSize = 128 / VT.getScalarSizeInBits();
6106 RepeatedMask.resize(LaneSize, -1);
6107 int Size = Mask.size();
6108 for (int i = 0; i < Size; ++i) {
6111 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6112 // This entry crosses lanes, so there is no way to model this shuffle.
6115 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6116 if (RepeatedMask[i % LaneSize] == -1)
6117 // This is the first non-undef entry in this slot of a 128-bit lane.
6118 RepeatedMask[i % LaneSize] =
6119 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6120 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6121 // Found a mismatch with the repeated mask.
6127 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6130 /// This is a fast way to test a shuffle mask against a fixed pattern:
6132 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6134 /// It returns true if the mask is exactly as wide as the argument list, and
6135 /// each element of the mask is either -1 (signifying undef) or the value given
6136 /// in the argument.
6137 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6138 ArrayRef<int> ExpectedMask) {
6139 if (Mask.size() != ExpectedMask.size())
6142 int Size = Mask.size();
6144 // If the values are build vectors, we can look through them to find
6145 // equivalent inputs that make the shuffles equivalent.
6146 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6147 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6149 for (int i = 0; i < Size; ++i)
6150 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6151 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6152 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6153 if (!MaskBV || !ExpectedBV ||
6154 MaskBV->getOperand(Mask[i] % Size) !=
6155 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6162 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6164 /// This helper function produces an 8-bit shuffle immediate corresponding to
6165 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6166 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6169 /// NB: We rely heavily on "undef" masks preserving the input lane.
6170 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6171 SelectionDAG &DAG) {
6172 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6173 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6174 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6175 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6176 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6179 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6180 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6181 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6182 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6183 return DAG.getConstant(Imm, MVT::i8);
6186 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6188 /// This is used as a fallback approach when first class blend instructions are
6189 /// unavailable. Currently it is only suitable for integer vectors, but could
6190 /// be generalized for floating point vectors if desirable.
6191 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6192 SDValue V2, ArrayRef<int> Mask,
6193 SelectionDAG &DAG) {
6194 assert(VT.isInteger() && "Only supports integer vector types!");
6195 MVT EltVT = VT.getScalarType();
6196 int NumEltBits = EltVT.getSizeInBits();
6197 SDValue Zero = DAG.getConstant(0, EltVT);
6198 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), EltVT);
6199 SmallVector<SDValue, 16> MaskOps;
6200 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6201 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6202 return SDValue(); // Shuffled input!
6203 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6206 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6207 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6208 // We have to cast V2 around.
6209 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6210 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6211 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6212 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6213 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6214 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6217 /// \brief Try to emit a blend instruction for a shuffle.
6219 /// This doesn't do any checks for the availability of instructions for blending
6220 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6221 /// be matched in the backend with the type given. What it does check for is
6222 /// that the shuffle mask is in fact a blend.
6223 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6224 SDValue V2, ArrayRef<int> Mask,
6225 const X86Subtarget *Subtarget,
6226 SelectionDAG &DAG) {
6227 unsigned BlendMask = 0;
6228 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6229 if (Mask[i] >= Size) {
6230 if (Mask[i] != i + Size)
6231 return SDValue(); // Shuffled V2 input!
6232 BlendMask |= 1u << i;
6235 if (Mask[i] >= 0 && Mask[i] != i)
6236 return SDValue(); // Shuffled V1 input!
6238 switch (VT.SimpleTy) {
6243 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6244 DAG.getConstant(BlendMask, MVT::i8));
6248 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6252 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6253 // that instruction.
6254 if (Subtarget->hasAVX2()) {
6255 // Scale the blend by the number of 32-bit dwords per element.
6256 int Scale = VT.getScalarSizeInBits() / 32;
6258 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6259 if (Mask[i] >= Size)
6260 for (int j = 0; j < Scale; ++j)
6261 BlendMask |= 1u << (i * Scale + j);
6263 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6264 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6265 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6266 return DAG.getNode(ISD::BITCAST, DL, VT,
6267 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6268 DAG.getConstant(BlendMask, MVT::i8)));
6272 // For integer shuffles we need to expand the mask and cast the inputs to
6273 // v8i16s prior to blending.
6274 int Scale = 8 / VT.getVectorNumElements();
6276 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6277 if (Mask[i] >= Size)
6278 for (int j = 0; j < Scale; ++j)
6279 BlendMask |= 1u << (i * Scale + j);
6281 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6282 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6283 return DAG.getNode(ISD::BITCAST, DL, VT,
6284 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6285 DAG.getConstant(BlendMask, MVT::i8)));
6289 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6290 SmallVector<int, 8> RepeatedMask;
6291 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6292 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6293 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6295 for (int i = 0; i < 8; ++i)
6296 if (RepeatedMask[i] >= 16)
6297 BlendMask |= 1u << i;
6298 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6299 DAG.getConstant(BlendMask, MVT::i8));
6305 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6306 "256-bit byte-blends require AVX2 support!");
6308 // Scale the blend by the number of bytes per element.
6309 int Scale = VT.getScalarSizeInBits() / 8;
6311 // This form of blend is always done on bytes. Compute the byte vector
6313 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6315 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6316 // mix of LLVM's code generator and the x86 backend. We tell the code
6317 // generator that boolean values in the elements of an x86 vector register
6318 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6319 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6320 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6321 // of the element (the remaining are ignored) and 0 in that high bit would
6322 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6323 // the LLVM model for boolean values in vector elements gets the relevant
6324 // bit set, it is set backwards and over constrained relative to x86's
6326 SmallVector<SDValue, 32> VSELECTMask;
6327 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6328 for (int j = 0; j < Scale; ++j)
6329 VSELECTMask.push_back(
6330 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6331 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8));
6333 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6334 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6336 ISD::BITCAST, DL, VT,
6337 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6338 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6343 llvm_unreachable("Not a supported integer vector type!");
6347 /// \brief Try to lower as a blend of elements from two inputs followed by
6348 /// a single-input permutation.
6350 /// This matches the pattern where we can blend elements from two inputs and
6351 /// then reduce the shuffle to a single-input permutation.
6352 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6355 SelectionDAG &DAG) {
6356 // We build up the blend mask while checking whether a blend is a viable way
6357 // to reduce the shuffle.
6358 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6359 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6361 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6365 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6367 if (BlendMask[Mask[i] % Size] == -1)
6368 BlendMask[Mask[i] % Size] = Mask[i];
6369 else if (BlendMask[Mask[i] % Size] != Mask[i])
6370 return SDValue(); // Can't blend in the needed input!
6372 PermuteMask[i] = Mask[i] % Size;
6375 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6376 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6379 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6380 /// blends and permutes.
6382 /// This matches the extremely common pattern for handling combined
6383 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6384 /// operations. It will try to pick the best arrangement of shuffles and
6386 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6390 SelectionDAG &DAG) {
6391 // Shuffle the input elements into the desired positions in V1 and V2 and
6392 // blend them together.
6393 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6394 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6395 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6396 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6397 if (Mask[i] >= 0 && Mask[i] < Size) {
6398 V1Mask[i] = Mask[i];
6400 } else if (Mask[i] >= Size) {
6401 V2Mask[i] = Mask[i] - Size;
6402 BlendMask[i] = i + Size;
6405 // Try to lower with the simpler initial blend strategy unless one of the
6406 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6407 // shuffle may be able to fold with a load or other benefit. However, when
6408 // we'll have to do 2x as many shuffles in order to achieve this, blending
6409 // first is a better strategy.
6410 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6411 if (SDValue BlendPerm =
6412 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6415 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6416 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6417 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6420 /// \brief Try to lower a vector shuffle as a byte rotation.
6422 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6423 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6424 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6425 /// try to generically lower a vector shuffle through such an pattern. It
6426 /// does not check for the profitability of lowering either as PALIGNR or
6427 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6428 /// This matches shuffle vectors that look like:
6430 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6432 /// Essentially it concatenates V1 and V2, shifts right by some number of
6433 /// elements, and takes the low elements as the result. Note that while this is
6434 /// specified as a *right shift* because x86 is little-endian, it is a *left
6435 /// rotate* of the vector lanes.
6436 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6439 const X86Subtarget *Subtarget,
6440 SelectionDAG &DAG) {
6441 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6443 int NumElts = Mask.size();
6444 int NumLanes = VT.getSizeInBits() / 128;
6445 int NumLaneElts = NumElts / NumLanes;
6447 // We need to detect various ways of spelling a rotation:
6448 // [11, 12, 13, 14, 15, 0, 1, 2]
6449 // [-1, 12, 13, 14, -1, -1, 1, -1]
6450 // [-1, -1, -1, -1, -1, -1, 1, 2]
6451 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6452 // [-1, 4, 5, 6, -1, -1, 9, -1]
6453 // [-1, 4, 5, 6, -1, -1, -1, -1]
6456 for (int l = 0; l < NumElts; l += NumLaneElts) {
6457 for (int i = 0; i < NumLaneElts; ++i) {
6458 if (Mask[l + i] == -1)
6460 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6462 // Get the mod-Size index and lane correct it.
6463 int LaneIdx = (Mask[l + i] % NumElts) - l;
6464 // Make sure it was in this lane.
6465 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6468 // Determine where a rotated vector would have started.
6469 int StartIdx = i - LaneIdx;
6471 // The identity rotation isn't interesting, stop.
6474 // If we found the tail of a vector the rotation must be the missing
6475 // front. If we found the head of a vector, it must be how much of the
6477 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6480 Rotation = CandidateRotation;
6481 else if (Rotation != CandidateRotation)
6482 // The rotations don't match, so we can't match this mask.
6485 // Compute which value this mask is pointing at.
6486 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6488 // Compute which of the two target values this index should be assigned
6489 // to. This reflects whether the high elements are remaining or the low
6490 // elements are remaining.
6491 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6493 // Either set up this value if we've not encountered it before, or check
6494 // that it remains consistent.
6497 else if (TargetV != MaskV)
6498 // This may be a rotation, but it pulls from the inputs in some
6499 // unsupported interleaving.
6504 // Check that we successfully analyzed the mask, and normalize the results.
6505 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6506 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6512 // The actual rotate instruction rotates bytes, so we need to scale the
6513 // rotation based on how many bytes are in the vector lane.
6514 int Scale = 16 / NumLaneElts;
6516 // SSSE3 targets can use the palignr instruction.
6517 if (Subtarget->hasSSSE3()) {
6518 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6519 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6520 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6521 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6523 return DAG.getNode(ISD::BITCAST, DL, VT,
6524 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6525 DAG.getConstant(Rotation * Scale, MVT::i8)));
6528 assert(VT.getSizeInBits() == 128 &&
6529 "Rotate-based lowering only supports 128-bit lowering!");
6530 assert(Mask.size() <= 16 &&
6531 "Can shuffle at most 16 bytes in a 128-bit vector!");
6533 // Default SSE2 implementation
6534 int LoByteShift = 16 - Rotation * Scale;
6535 int HiByteShift = Rotation * Scale;
6537 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6538 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6539 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6541 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6542 DAG.getConstant(LoByteShift, MVT::i8));
6543 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6544 DAG.getConstant(HiByteShift, MVT::i8));
6545 return DAG.getNode(ISD::BITCAST, DL, VT,
6546 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6549 /// \brief Compute whether each element of a shuffle is zeroable.
6551 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6552 /// Either it is an undef element in the shuffle mask, the element of the input
6553 /// referenced is undef, or the element of the input referenced is known to be
6554 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6555 /// as many lanes with this technique as possible to simplify the remaining
6557 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6558 SDValue V1, SDValue V2) {
6559 SmallBitVector Zeroable(Mask.size(), false);
6561 while (V1.getOpcode() == ISD::BITCAST)
6562 V1 = V1->getOperand(0);
6563 while (V2.getOpcode() == ISD::BITCAST)
6564 V2 = V2->getOperand(0);
6566 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6567 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6569 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6571 // Handle the easy cases.
6572 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6577 // If this is an index into a build_vector node (which has the same number
6578 // of elements), dig out the input value and use it.
6579 SDValue V = M < Size ? V1 : V2;
6580 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6583 SDValue Input = V.getOperand(M % Size);
6584 // The UNDEF opcode check really should be dead code here, but not quite
6585 // worth asserting on (it isn't invalid, just unexpected).
6586 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6593 /// \brief Try to emit a bitmask instruction for a shuffle.
6595 /// This handles cases where we can model a blend exactly as a bitmask due to
6596 /// one of the inputs being zeroable.
6597 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6598 SDValue V2, ArrayRef<int> Mask,
6599 SelectionDAG &DAG) {
6600 MVT EltVT = VT.getScalarType();
6601 int NumEltBits = EltVT.getSizeInBits();
6602 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6603 SDValue Zero = DAG.getConstant(0, IntEltVT);
6604 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), IntEltVT);
6605 if (EltVT.isFloatingPoint()) {
6606 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6607 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6609 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6610 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6612 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6615 if (Mask[i] % Size != i)
6616 return SDValue(); // Not a blend.
6618 V = Mask[i] < Size ? V1 : V2;
6619 else if (V != (Mask[i] < Size ? V1 : V2))
6620 return SDValue(); // Can only let one input through the mask.
6622 VMaskOps[i] = AllOnes;
6625 return SDValue(); // No non-zeroable elements!
6627 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6628 V = DAG.getNode(VT.isFloatingPoint()
6629 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6634 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6636 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6637 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6638 /// matches elements from one of the input vectors shuffled to the left or
6639 /// right with zeroable elements 'shifted in'. It handles both the strictly
6640 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6643 /// PSHL : (little-endian) left bit shift.
6644 /// [ zz, 0, zz, 2 ]
6645 /// [ -1, 4, zz, -1 ]
6646 /// PSRL : (little-endian) right bit shift.
6648 /// [ -1, -1, 7, zz]
6649 /// PSLLDQ : (little-endian) left byte shift
6650 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6651 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6652 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6653 /// PSRLDQ : (little-endian) right byte shift
6654 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6655 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6656 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6657 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6658 SDValue V2, ArrayRef<int> Mask,
6659 SelectionDAG &DAG) {
6660 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6662 int Size = Mask.size();
6663 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6665 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6666 for (int i = 0; i < Size; i += Scale)
6667 for (int j = 0; j < Shift; ++j)
6668 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6674 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6675 for (int i = 0; i != Size; i += Scale) {
6676 unsigned Pos = Left ? i + Shift : i;
6677 unsigned Low = Left ? i : i + Shift;
6678 unsigned Len = Scale - Shift;
6679 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6680 Low + (V == V1 ? 0 : Size)))
6684 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6685 bool ByteShift = ShiftEltBits > 64;
6686 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6687 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6688 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6690 // Normalize the scale for byte shifts to still produce an i64 element
6692 Scale = ByteShift ? Scale / 2 : Scale;
6694 // We need to round trip through the appropriate type for the shift.
6695 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6696 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6697 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6698 "Illegal integer vector type");
6699 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6701 V = DAG.getNode(OpCode, DL, ShiftVT, V, DAG.getConstant(ShiftAmt, MVT::i8));
6702 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6705 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6706 // keep doubling the size of the integer elements up to that. We can
6707 // then shift the elements of the integer vector by whole multiples of
6708 // their width within the elements of the larger integer vector. Test each
6709 // multiple to see if we can find a match with the moved element indices
6710 // and that the shifted in elements are all zeroable.
6711 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6712 for (int Shift = 1; Shift != Scale; ++Shift)
6713 for (bool Left : {true, false})
6714 if (CheckZeros(Shift, Scale, Left))
6715 for (SDValue V : {V1, V2})
6716 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6723 /// \brief Lower a vector shuffle as a zero or any extension.
6725 /// Given a specific number of elements, element bit width, and extension
6726 /// stride, produce either a zero or any extension based on the available
6727 /// features of the subtarget.
6728 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6729 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6730 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6731 assert(Scale > 1 && "Need a scale to extend.");
6732 int NumElements = VT.getVectorNumElements();
6733 int EltBits = VT.getScalarSizeInBits();
6734 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6735 "Only 8, 16, and 32 bit elements can be extended.");
6736 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6738 // Found a valid zext mask! Try various lowering strategies based on the
6739 // input type and available ISA extensions.
6740 if (Subtarget->hasSSE41()) {
6741 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6742 NumElements / Scale);
6743 return DAG.getNode(ISD::BITCAST, DL, VT,
6744 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6747 // For any extends we can cheat for larger element sizes and use shuffle
6748 // instructions that can fold with a load and/or copy.
6749 if (AnyExt && EltBits == 32) {
6750 int PSHUFDMask[4] = {0, -1, 1, -1};
6752 ISD::BITCAST, DL, VT,
6753 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6754 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6755 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
6757 if (AnyExt && EltBits == 16 && Scale > 2) {
6758 int PSHUFDMask[4] = {0, -1, 0, -1};
6759 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6760 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6761 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
6762 int PSHUFHWMask[4] = {1, -1, -1, -1};
6764 ISD::BITCAST, DL, VT,
6765 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6766 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6767 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
6770 // If this would require more than 2 unpack instructions to expand, use
6771 // pshufb when available. We can only use more than 2 unpack instructions
6772 // when zero extending i8 elements which also makes it easier to use pshufb.
6773 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6774 assert(NumElements == 16 && "Unexpected byte vector width!");
6775 SDValue PSHUFBMask[16];
6776 for (int i = 0; i < 16; ++i)
6778 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
6779 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6780 return DAG.getNode(ISD::BITCAST, DL, VT,
6781 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6782 DAG.getNode(ISD::BUILD_VECTOR, DL,
6783 MVT::v16i8, PSHUFBMask)));
6786 // Otherwise emit a sequence of unpacks.
6788 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6789 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6790 : getZeroVector(InputVT, Subtarget, DAG, DL);
6791 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6792 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6796 } while (Scale > 1);
6797 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6800 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6802 /// This routine will try to do everything in its power to cleverly lower
6803 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6804 /// check for the profitability of this lowering, it tries to aggressively
6805 /// match this pattern. It will use all of the micro-architectural details it
6806 /// can to emit an efficient lowering. It handles both blends with all-zero
6807 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6808 /// masking out later).
6810 /// The reason we have dedicated lowering for zext-style shuffles is that they
6811 /// are both incredibly common and often quite performance sensitive.
6812 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6813 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6814 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6815 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6817 int Bits = VT.getSizeInBits();
6818 int NumElements = VT.getVectorNumElements();
6819 assert(VT.getScalarSizeInBits() <= 32 &&
6820 "Exceeds 32-bit integer zero extension limit");
6821 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6823 // Define a helper function to check a particular ext-scale and lower to it if
6825 auto Lower = [&](int Scale) -> SDValue {
6828 for (int i = 0; i < NumElements; ++i) {
6830 continue; // Valid anywhere but doesn't tell us anything.
6831 if (i % Scale != 0) {
6832 // Each of the extended elements need to be zeroable.
6836 // We no longer are in the anyext case.
6841 // Each of the base elements needs to be consecutive indices into the
6842 // same input vector.
6843 SDValue V = Mask[i] < NumElements ? V1 : V2;
6846 else if (InputV != V)
6847 return SDValue(); // Flip-flopping inputs.
6849 if (Mask[i] % NumElements != i / Scale)
6850 return SDValue(); // Non-consecutive strided elements.
6853 // If we fail to find an input, we have a zero-shuffle which should always
6854 // have already been handled.
6855 // FIXME: Maybe handle this here in case during blending we end up with one?
6859 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6860 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6863 // The widest scale possible for extending is to a 64-bit integer.
6864 assert(Bits % 64 == 0 &&
6865 "The number of bits in a vector must be divisible by 64 on x86!");
6866 int NumExtElements = Bits / 64;
6868 // Each iteration, try extending the elements half as much, but into twice as
6870 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6871 assert(NumElements % NumExtElements == 0 &&
6872 "The input vector size must be divisible by the extended size.");
6873 if (SDValue V = Lower(NumElements / NumExtElements))
6877 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6881 // Returns one of the source operands if the shuffle can be reduced to a
6882 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6883 auto CanZExtLowHalf = [&]() {
6884 for (int i = NumElements / 2; i != NumElements; ++i)
6887 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6889 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6894 if (SDValue V = CanZExtLowHalf()) {
6895 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6896 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6897 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6900 // No viable ext lowering found.
6904 /// \brief Try to get a scalar value for a specific element of a vector.
6906 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6907 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6908 SelectionDAG &DAG) {
6909 MVT VT = V.getSimpleValueType();
6910 MVT EltVT = VT.getVectorElementType();
6911 while (V.getOpcode() == ISD::BITCAST)
6912 V = V.getOperand(0);
6913 // If the bitcasts shift the element size, we can't extract an equivalent
6915 MVT NewVT = V.getSimpleValueType();
6916 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
6919 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6920 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
6921 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
6926 /// \brief Helper to test for a load that can be folded with x86 shuffles.
6928 /// This is particularly important because the set of instructions varies
6929 /// significantly based on whether the operand is a load or not.
6930 static bool isShuffleFoldableLoad(SDValue V) {
6931 while (V.getOpcode() == ISD::BITCAST)
6932 V = V.getOperand(0);
6934 return ISD::isNON_EXTLoad(V.getNode());
6937 /// \brief Try to lower insertion of a single element into a zero vector.
6939 /// This is a common pattern that we have especially efficient patterns to lower
6940 /// across all subtarget feature sets.
6941 static SDValue lowerVectorShuffleAsElementInsertion(
6942 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6943 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6944 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6946 MVT EltVT = VT.getVectorElementType();
6948 int V2Index = std::find_if(Mask.begin(), Mask.end(),
6949 [&Mask](int M) { return M >= (int)Mask.size(); }) -
6951 bool IsV1Zeroable = true;
6952 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6953 if (i != V2Index && !Zeroable[i]) {
6954 IsV1Zeroable = false;
6958 // Check for a single input from a SCALAR_TO_VECTOR node.
6959 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
6960 // all the smarts here sunk into that routine. However, the current
6961 // lowering of BUILD_VECTOR makes that nearly impossible until the old
6962 // vector shuffle lowering is dead.
6963 if (SDValue V2S = getScalarValueForVectorElement(
6964 V2, Mask[V2Index] - Mask.size(), DAG)) {
6965 // We need to zext the scalar if it is smaller than an i32.
6966 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
6967 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
6968 // Using zext to expand a narrow element won't work for non-zero
6973 // Zero-extend directly to i32.
6975 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
6977 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
6978 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
6979 EltVT == MVT::i16) {
6980 // Either not inserting from the low element of the input or the input
6981 // element size is too small to use VZEXT_MOVL to clear the high bits.
6985 if (!IsV1Zeroable) {
6986 // If V1 can't be treated as a zero vector we have fewer options to lower
6987 // this. We can't support integer vectors or non-zero targets cheaply, and
6988 // the V1 elements can't be permuted in any way.
6989 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
6990 if (!VT.isFloatingPoint() || V2Index != 0)
6992 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
6993 V1Mask[V2Index] = -1;
6994 if (!isNoopShuffleMask(V1Mask))
6996 // This is essentially a special case blend operation, but if we have
6997 // general purpose blend operations, they are always faster. Bail and let
6998 // the rest of the lowering handle these as blends.
6999 if (Subtarget->hasSSE41())
7002 // Otherwise, use MOVSD or MOVSS.
7003 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7004 "Only two types of floating point element types to handle!");
7005 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7009 // This lowering only works for the low element with floating point vectors.
7010 if (VT.isFloatingPoint() && V2Index != 0)
7013 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7015 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7018 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7019 // the desired position. Otherwise it is more efficient to do a vector
7020 // shift left. We know that we can do a vector shift left because all
7021 // the inputs are zero.
7022 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7023 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7024 V2Shuffle[V2Index] = 0;
7025 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7027 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7029 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7031 V2Index * EltVT.getSizeInBits()/8,
7032 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7033 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7039 /// \brief Try to lower broadcast of a single element.
7041 /// For convenience, this code also bundles all of the subtarget feature set
7042 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7043 /// a convenient way to factor it out.
7044 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7046 const X86Subtarget *Subtarget,
7047 SelectionDAG &DAG) {
7048 if (!Subtarget->hasAVX())
7050 if (VT.isInteger() && !Subtarget->hasAVX2())
7053 // Check that the mask is a broadcast.
7054 int BroadcastIdx = -1;
7056 if (M >= 0 && BroadcastIdx == -1)
7058 else if (M >= 0 && M != BroadcastIdx)
7061 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7062 "a sorted mask where the broadcast "
7065 // Go up the chain of (vector) values to find a scalar load that we can
7066 // combine with the broadcast.
7068 switch (V.getOpcode()) {
7069 case ISD::CONCAT_VECTORS: {
7070 int OperandSize = Mask.size() / V.getNumOperands();
7071 V = V.getOperand(BroadcastIdx / OperandSize);
7072 BroadcastIdx %= OperandSize;
7076 case ISD::INSERT_SUBVECTOR: {
7077 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7078 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7082 int BeginIdx = (int)ConstantIdx->getZExtValue();
7084 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7085 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7086 BroadcastIdx -= BeginIdx;
7097 // Check if this is a broadcast of a scalar. We special case lowering
7098 // for scalars so that we can more effectively fold with loads.
7099 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7100 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7101 V = V.getOperand(BroadcastIdx);
7103 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7104 // Only AVX2 has register broadcasts.
7105 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7107 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7108 // We can't broadcast from a vector register without AVX2, and we can only
7109 // broadcast from the zero-element of a vector register.
7113 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7116 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7117 // INSERTPS when the V1 elements are already in the correct locations
7118 // because otherwise we can just always use two SHUFPS instructions which
7119 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7120 // perform INSERTPS if a single V1 element is out of place and all V2
7121 // elements are zeroable.
7122 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7124 SelectionDAG &DAG) {
7125 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7126 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7127 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7128 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7130 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7133 int V1DstIndex = -1;
7134 int V2DstIndex = -1;
7135 bool V1UsedInPlace = false;
7137 for (int i = 0; i < 4; ++i) {
7138 // Synthesize a zero mask from the zeroable elements (includes undefs).
7144 // Flag if we use any V1 inputs in place.
7146 V1UsedInPlace = true;
7150 // We can only insert a single non-zeroable element.
7151 if (V1DstIndex != -1 || V2DstIndex != -1)
7155 // V1 input out of place for insertion.
7158 // V2 input for insertion.
7163 // Don't bother if we have no (non-zeroable) element for insertion.
7164 if (V1DstIndex == -1 && V2DstIndex == -1)
7167 // Determine element insertion src/dst indices. The src index is from the
7168 // start of the inserted vector, not the start of the concatenated vector.
7169 unsigned V2SrcIndex = 0;
7170 if (V1DstIndex != -1) {
7171 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7172 // and don't use the original V2 at all.
7173 V2SrcIndex = Mask[V1DstIndex];
7174 V2DstIndex = V1DstIndex;
7177 V2SrcIndex = Mask[V2DstIndex] - 4;
7180 // If no V1 inputs are used in place, then the result is created only from
7181 // the zero mask and the V2 insertion - so remove V1 dependency.
7183 V1 = DAG.getUNDEF(MVT::v4f32);
7185 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7186 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7188 // Insert the V2 element into the desired position.
7190 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7191 DAG.getConstant(InsertPSMask, MVT::i8));
7194 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7195 /// UNPCK instruction.
7197 /// This specifically targets cases where we end up with alternating between
7198 /// the two inputs, and so can permute them into something that feeds a single
7199 /// UNPCK instruction. Note that this routine only targets integer vectors
7200 /// because for floating point vectors we have a generalized SHUFPS lowering
7201 /// strategy that handles everything that doesn't *exactly* match an unpack,
7202 /// making this clever lowering unnecessary.
7203 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7204 SDValue V2, ArrayRef<int> Mask,
7205 SelectionDAG &DAG) {
7206 assert(!VT.isFloatingPoint() &&
7207 "This routine only supports integer vectors.");
7208 assert(!isSingleInputShuffleMask(Mask) &&
7209 "This routine should only be used when blending two inputs.");
7210 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7212 int Size = Mask.size();
7214 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7215 return M >= 0 && M % Size < Size / 2;
7217 int NumHiInputs = std::count_if(
7218 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7220 bool UnpackLo = NumLoInputs >= NumHiInputs;
7222 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7223 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7224 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7226 for (int i = 0; i < Size; ++i) {
7230 // Each element of the unpack contains Scale elements from this mask.
7231 int UnpackIdx = i / Scale;
7233 // We only handle the case where V1 feeds the first slots of the unpack.
7234 // We rely on canonicalization to ensure this is the case.
7235 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7238 // Setup the mask for this input. The indexing is tricky as we have to
7239 // handle the unpack stride.
7240 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7241 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7245 // If we will have to shuffle both inputs to use the unpack, check whether
7246 // we can just unpack first and shuffle the result. If so, skip this unpack.
7247 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7248 !isNoopShuffleMask(V2Mask))
7251 // Shuffle the inputs into place.
7252 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7253 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7255 // Cast the inputs to the type we will use to unpack them.
7256 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7257 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7259 // Unpack the inputs and cast the result back to the desired type.
7260 return DAG.getNode(ISD::BITCAST, DL, VT,
7261 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7262 DL, UnpackVT, V1, V2));
7265 // We try each unpack from the largest to the smallest to try and find one
7266 // that fits this mask.
7267 int OrigNumElements = VT.getVectorNumElements();
7268 int OrigScalarSize = VT.getScalarSizeInBits();
7269 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7270 int Scale = ScalarSize / OrigScalarSize;
7271 int NumElements = OrigNumElements / Scale;
7272 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7273 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7277 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7279 if (NumLoInputs == 0 || NumHiInputs == 0) {
7280 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7281 "We have to have *some* inputs!");
7282 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7284 // FIXME: We could consider the total complexity of the permute of each
7285 // possible unpacking. Or at the least we should consider how many
7286 // half-crossings are created.
7287 // FIXME: We could consider commuting the unpacks.
7289 SmallVector<int, 32> PermMask;
7290 PermMask.assign(Size, -1);
7291 for (int i = 0; i < Size; ++i) {
7295 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7298 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7300 return DAG.getVectorShuffle(
7301 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7303 DAG.getUNDEF(VT), PermMask);
7309 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7311 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7312 /// support for floating point shuffles but not integer shuffles. These
7313 /// instructions will incur a domain crossing penalty on some chips though so
7314 /// it is better to avoid lowering through this for integer vectors where
7316 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7317 const X86Subtarget *Subtarget,
7318 SelectionDAG &DAG) {
7320 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7321 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7322 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7323 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7324 ArrayRef<int> Mask = SVOp->getMask();
7325 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7327 if (isSingleInputShuffleMask(Mask)) {
7328 // Use low duplicate instructions for masks that match their pattern.
7329 if (Subtarget->hasSSE3())
7330 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7331 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7333 // Straight shuffle of a single input vector. Simulate this by using the
7334 // single input as both of the "inputs" to this instruction..
7335 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7337 if (Subtarget->hasAVX()) {
7338 // If we have AVX, we can use VPERMILPS which will allow folding a load
7339 // into the shuffle.
7340 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7341 DAG.getConstant(SHUFPDMask, MVT::i8));
7344 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7345 DAG.getConstant(SHUFPDMask, MVT::i8));
7347 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7348 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7350 // If we have a single input, insert that into V1 if we can do so cheaply.
7351 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7352 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7353 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7355 // Try inverting the insertion since for v2 masks it is easy to do and we
7356 // can't reliably sort the mask one way or the other.
7357 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7358 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7359 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7360 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7364 // Try to use one of the special instruction patterns to handle two common
7365 // blend patterns if a zero-blend above didn't work.
7366 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7367 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7368 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7369 // We can either use a special instruction to load over the low double or
7370 // to move just the low double.
7372 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7374 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7376 if (Subtarget->hasSSE41())
7377 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7381 // Use dedicated unpack instructions for masks that match their pattern.
7382 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7383 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7384 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7385 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7387 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7388 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7389 DAG.getConstant(SHUFPDMask, MVT::i8));
7392 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7394 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7395 /// the integer unit to minimize domain crossing penalties. However, for blends
7396 /// it falls back to the floating point shuffle operation with appropriate bit
7398 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7399 const X86Subtarget *Subtarget,
7400 SelectionDAG &DAG) {
7402 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7403 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7404 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7405 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7406 ArrayRef<int> Mask = SVOp->getMask();
7407 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7409 if (isSingleInputShuffleMask(Mask)) {
7410 // Check for being able to broadcast a single element.
7411 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7412 Mask, Subtarget, DAG))
7415 // Straight shuffle of a single input vector. For everything from SSE2
7416 // onward this has a single fast instruction with no scary immediates.
7417 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7418 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7419 int WidenedMask[4] = {
7420 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7421 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7423 ISD::BITCAST, DL, MVT::v2i64,
7424 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7425 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7427 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7428 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7429 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7430 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7432 // If we have a blend of two PACKUS operations an the blend aligns with the
7433 // low and half halves, we can just merge the PACKUS operations. This is
7434 // particularly important as it lets us merge shuffles that this routine itself
7436 auto GetPackNode = [](SDValue V) {
7437 while (V.getOpcode() == ISD::BITCAST)
7438 V = V.getOperand(0);
7440 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7442 if (SDValue V1Pack = GetPackNode(V1))
7443 if (SDValue V2Pack = GetPackNode(V2))
7444 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7445 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7446 Mask[0] == 0 ? V1Pack.getOperand(0)
7447 : V1Pack.getOperand(1),
7448 Mask[1] == 2 ? V2Pack.getOperand(0)
7449 : V2Pack.getOperand(1)));
7451 // Try to use shift instructions.
7453 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7456 // When loading a scalar and then shuffling it into a vector we can often do
7457 // the insertion cheaply.
7458 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7459 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7461 // Try inverting the insertion since for v2 masks it is easy to do and we
7462 // can't reliably sort the mask one way or the other.
7463 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7464 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7465 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7468 // We have different paths for blend lowering, but they all must use the
7469 // *exact* same predicate.
7470 bool IsBlendSupported = Subtarget->hasSSE41();
7471 if (IsBlendSupported)
7472 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7476 // Use dedicated unpack instructions for masks that match their pattern.
7477 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7478 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7479 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7480 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7482 // Try to use byte rotation instructions.
7483 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7484 if (Subtarget->hasSSSE3())
7485 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7486 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7489 // If we have direct support for blends, we should lower by decomposing into
7490 // a permute. That will be faster than the domain cross.
7491 if (IsBlendSupported)
7492 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7495 // We implement this with SHUFPD which is pretty lame because it will likely
7496 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7497 // However, all the alternatives are still more cycles and newer chips don't
7498 // have this problem. It would be really nice if x86 had better shuffles here.
7499 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7500 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7501 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7502 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7505 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7507 /// This is used to disable more specialized lowerings when the shufps lowering
7508 /// will happen to be efficient.
7509 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7510 // This routine only handles 128-bit shufps.
7511 assert(Mask.size() == 4 && "Unsupported mask size!");
7513 // To lower with a single SHUFPS we need to have the low half and high half
7514 // each requiring a single input.
7515 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7517 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7523 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7525 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7526 /// It makes no assumptions about whether this is the *best* lowering, it simply
7528 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7529 ArrayRef<int> Mask, SDValue V1,
7530 SDValue V2, SelectionDAG &DAG) {
7531 SDValue LowV = V1, HighV = V2;
7532 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7535 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7537 if (NumV2Elements == 1) {
7539 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7542 // Compute the index adjacent to V2Index and in the same half by toggling
7544 int V2AdjIndex = V2Index ^ 1;
7546 if (Mask[V2AdjIndex] == -1) {
7547 // Handles all the cases where we have a single V2 element and an undef.
7548 // This will only ever happen in the high lanes because we commute the
7549 // vector otherwise.
7551 std::swap(LowV, HighV);
7552 NewMask[V2Index] -= 4;
7554 // Handle the case where the V2 element ends up adjacent to a V1 element.
7555 // To make this work, blend them together as the first step.
7556 int V1Index = V2AdjIndex;
7557 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7558 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7559 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7561 // Now proceed to reconstruct the final blend as we have the necessary
7562 // high or low half formed.
7569 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7570 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7572 } else if (NumV2Elements == 2) {
7573 if (Mask[0] < 4 && Mask[1] < 4) {
7574 // Handle the easy case where we have V1 in the low lanes and V2 in the
7578 } else if (Mask[2] < 4 && Mask[3] < 4) {
7579 // We also handle the reversed case because this utility may get called
7580 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7581 // arrange things in the right direction.
7587 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7588 // trying to place elements directly, just blend them and set up the final
7589 // shuffle to place them.
7591 // The first two blend mask elements are for V1, the second two are for
7593 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7594 Mask[2] < 4 ? Mask[2] : Mask[3],
7595 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7596 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7597 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7598 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7600 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7603 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7604 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7605 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7606 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7609 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7610 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7613 /// \brief Lower 4-lane 32-bit floating point shuffles.
7615 /// Uses instructions exclusively from the floating point unit to minimize
7616 /// domain crossing penalties, as these are sufficient to implement all v4f32
7618 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7619 const X86Subtarget *Subtarget,
7620 SelectionDAG &DAG) {
7622 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7623 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7624 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7625 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7626 ArrayRef<int> Mask = SVOp->getMask();
7627 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7630 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7632 if (NumV2Elements == 0) {
7633 // Check for being able to broadcast a single element.
7634 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7635 Mask, Subtarget, DAG))
7638 // Use even/odd duplicate instructions for masks that match their pattern.
7639 if (Subtarget->hasSSE3()) {
7640 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7641 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7642 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7643 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7646 if (Subtarget->hasAVX()) {
7647 // If we have AVX, we can use VPERMILPS which will allow folding a load
7648 // into the shuffle.
7649 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7650 getV4X86ShuffleImm8ForMask(Mask, DAG));
7653 // Otherwise, use a straight shuffle of a single input vector. We pass the
7654 // input vector to both operands to simulate this with a SHUFPS.
7655 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7656 getV4X86ShuffleImm8ForMask(Mask, DAG));
7659 // There are special ways we can lower some single-element blends. However, we
7660 // have custom ways we can lower more complex single-element blends below that
7661 // we defer to if both this and BLENDPS fail to match, so restrict this to
7662 // when the V2 input is targeting element 0 of the mask -- that is the fast
7664 if (NumV2Elements == 1 && Mask[0] >= 4)
7665 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7666 Mask, Subtarget, DAG))
7669 if (Subtarget->hasSSE41()) {
7670 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7674 // Use INSERTPS if we can complete the shuffle efficiently.
7675 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7678 if (!isSingleSHUFPSMask(Mask))
7679 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7680 DL, MVT::v4f32, V1, V2, Mask, DAG))
7684 // Use dedicated unpack instructions for masks that match their pattern.
7685 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7686 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7687 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7688 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7689 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7690 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7691 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7692 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7694 // Otherwise fall back to a SHUFPS lowering strategy.
7695 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7698 /// \brief Lower 4-lane i32 vector shuffles.
7700 /// We try to handle these with integer-domain shuffles where we can, but for
7701 /// blends we use the floating point domain blend instructions.
7702 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7703 const X86Subtarget *Subtarget,
7704 SelectionDAG &DAG) {
7706 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7707 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7708 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7709 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7710 ArrayRef<int> Mask = SVOp->getMask();
7711 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7713 // Whenever we can lower this as a zext, that instruction is strictly faster
7714 // than any alternative. It also allows us to fold memory operands into the
7715 // shuffle in many cases.
7716 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7717 Mask, Subtarget, DAG))
7721 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7723 if (NumV2Elements == 0) {
7724 // Check for being able to broadcast a single element.
7725 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7726 Mask, Subtarget, DAG))
7729 // Straight shuffle of a single input vector. For everything from SSE2
7730 // onward this has a single fast instruction with no scary immediates.
7731 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7732 // but we aren't actually going to use the UNPCK instruction because doing
7733 // so prevents folding a load into this instruction or making a copy.
7734 const int UnpackLoMask[] = {0, 0, 1, 1};
7735 const int UnpackHiMask[] = {2, 2, 3, 3};
7736 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7737 Mask = UnpackLoMask;
7738 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7739 Mask = UnpackHiMask;
7741 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7742 getV4X86ShuffleImm8ForMask(Mask, DAG));
7745 // Try to use shift instructions.
7747 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7750 // There are special ways we can lower some single-element blends.
7751 if (NumV2Elements == 1)
7752 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7753 Mask, Subtarget, DAG))
7756 // We have different paths for blend lowering, but they all must use the
7757 // *exact* same predicate.
7758 bool IsBlendSupported = Subtarget->hasSSE41();
7759 if (IsBlendSupported)
7760 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7764 if (SDValue Masked =
7765 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7768 // Use dedicated unpack instructions for masks that match their pattern.
7769 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7770 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7771 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7772 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7773 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7774 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7775 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7776 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7778 // Try to use byte rotation instructions.
7779 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7780 if (Subtarget->hasSSSE3())
7781 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7782 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7785 // If we have direct support for blends, we should lower by decomposing into
7786 // a permute. That will be faster than the domain cross.
7787 if (IsBlendSupported)
7788 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7791 // Try to lower by permuting the inputs into an unpack instruction.
7792 if (SDValue Unpack =
7793 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7796 // We implement this with SHUFPS because it can blend from two vectors.
7797 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7798 // up the inputs, bypassing domain shift penalties that we would encur if we
7799 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7801 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7802 DAG.getVectorShuffle(
7804 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7805 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7808 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7809 /// shuffle lowering, and the most complex part.
7811 /// The lowering strategy is to try to form pairs of input lanes which are
7812 /// targeted at the same half of the final vector, and then use a dword shuffle
7813 /// to place them onto the right half, and finally unpack the paired lanes into
7814 /// their final position.
7816 /// The exact breakdown of how to form these dword pairs and align them on the
7817 /// correct sides is really tricky. See the comments within the function for
7818 /// more of the details.
7820 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7821 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7822 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7823 /// vector, form the analogous 128-bit 8-element Mask.
7824 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7825 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7826 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7827 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7828 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7830 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7831 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7832 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7834 SmallVector<int, 4> LoInputs;
7835 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7836 [](int M) { return M >= 0; });
7837 std::sort(LoInputs.begin(), LoInputs.end());
7838 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7839 SmallVector<int, 4> HiInputs;
7840 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7841 [](int M) { return M >= 0; });
7842 std::sort(HiInputs.begin(), HiInputs.end());
7843 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7845 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7846 int NumHToL = LoInputs.size() - NumLToL;
7848 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7849 int NumHToH = HiInputs.size() - NumLToH;
7850 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7851 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7852 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7853 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7855 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7856 // such inputs we can swap two of the dwords across the half mark and end up
7857 // with <=2 inputs to each half in each half. Once there, we can fall through
7858 // to the generic code below. For example:
7860 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7861 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7863 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7864 // and an existing 2-into-2 on the other half. In this case we may have to
7865 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7866 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7867 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7868 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7869 // half than the one we target for fixing) will be fixed when we re-enter this
7870 // path. We will also combine away any sequence of PSHUFD instructions that
7871 // result into a single instruction. Here is an example of the tricky case:
7873 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7874 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7876 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7878 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7879 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7881 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7882 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7884 // The result is fine to be handled by the generic logic.
7885 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7886 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7887 int AOffset, int BOffset) {
7888 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7889 "Must call this with A having 3 or 1 inputs from the A half.");
7890 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7891 "Must call this with B having 1 or 3 inputs from the B half.");
7892 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7893 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7895 // Compute the index of dword with only one word among the three inputs in
7896 // a half by taking the sum of the half with three inputs and subtracting
7897 // the sum of the actual three inputs. The difference is the remaining
7900 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7901 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7902 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7903 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7904 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7905 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7906 int TripleNonInputIdx =
7907 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7908 TripleDWord = TripleNonInputIdx / 2;
7910 // We use xor with one to compute the adjacent DWord to whichever one the
7912 OneInputDWord = (OneInput / 2) ^ 1;
7914 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7915 // and BToA inputs. If there is also such a problem with the BToB and AToB
7916 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7917 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7918 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7919 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7920 // Compute how many inputs will be flipped by swapping these DWords. We
7922 // to balance this to ensure we don't form a 3-1 shuffle in the other
7924 int NumFlippedAToBInputs =
7925 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7926 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7927 int NumFlippedBToBInputs =
7928 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7929 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7930 if ((NumFlippedAToBInputs == 1 &&
7931 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7932 (NumFlippedBToBInputs == 1 &&
7933 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7934 // We choose whether to fix the A half or B half based on whether that
7935 // half has zero flipped inputs. At zero, we may not be able to fix it
7936 // with that half. We also bias towards fixing the B half because that
7937 // will more commonly be the high half, and we have to bias one way.
7938 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7939 ArrayRef<int> Inputs) {
7940 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7941 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7942 PinnedIdx ^ 1) != Inputs.end();
7943 // Determine whether the free index is in the flipped dword or the
7944 // unflipped dword based on where the pinned index is. We use this bit
7945 // in an xor to conditionally select the adjacent dword.
7946 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7947 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7948 FixFreeIdx) != Inputs.end();
7949 if (IsFixIdxInput == IsFixFreeIdxInput)
7951 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7952 FixFreeIdx) != Inputs.end();
7953 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7954 "We need to be changing the number of flipped inputs!");
7955 int PSHUFHalfMask[] = {0, 1, 2, 3};
7956 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7957 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7959 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7962 if (M != -1 && M == FixIdx)
7964 else if (M != -1 && M == FixFreeIdx)
7967 if (NumFlippedBToBInputs != 0) {
7969 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7970 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7972 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7974 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7975 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7980 int PSHUFDMask[] = {0, 1, 2, 3};
7981 PSHUFDMask[ADWord] = BDWord;
7982 PSHUFDMask[BDWord] = ADWord;
7983 V = DAG.getNode(ISD::BITCAST, DL, VT,
7984 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
7985 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
7986 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7988 // Adjust the mask to match the new locations of A and B.
7990 if (M != -1 && M/2 == ADWord)
7991 M = 2 * BDWord + M % 2;
7992 else if (M != -1 && M/2 == BDWord)
7993 M = 2 * ADWord + M % 2;
7995 // Recurse back into this routine to re-compute state now that this isn't
7996 // a 3 and 1 problem.
7997 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8000 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8001 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8002 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8003 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8005 // At this point there are at most two inputs to the low and high halves from
8006 // each half. That means the inputs can always be grouped into dwords and
8007 // those dwords can then be moved to the correct half with a dword shuffle.
8008 // We use at most one low and one high word shuffle to collect these paired
8009 // inputs into dwords, and finally a dword shuffle to place them.
8010 int PSHUFLMask[4] = {-1, -1, -1, -1};
8011 int PSHUFHMask[4] = {-1, -1, -1, -1};
8012 int PSHUFDMask[4] = {-1, -1, -1, -1};
8014 // First fix the masks for all the inputs that are staying in their
8015 // original halves. This will then dictate the targets of the cross-half
8017 auto fixInPlaceInputs =
8018 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8019 MutableArrayRef<int> SourceHalfMask,
8020 MutableArrayRef<int> HalfMask, int HalfOffset) {
8021 if (InPlaceInputs.empty())
8023 if (InPlaceInputs.size() == 1) {
8024 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8025 InPlaceInputs[0] - HalfOffset;
8026 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8029 if (IncomingInputs.empty()) {
8030 // Just fix all of the in place inputs.
8031 for (int Input : InPlaceInputs) {
8032 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8033 PSHUFDMask[Input / 2] = Input / 2;
8038 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8039 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8040 InPlaceInputs[0] - HalfOffset;
8041 // Put the second input next to the first so that they are packed into
8042 // a dword. We find the adjacent index by toggling the low bit.
8043 int AdjIndex = InPlaceInputs[0] ^ 1;
8044 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8045 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8046 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8048 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8049 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8051 // Now gather the cross-half inputs and place them into a free dword of
8052 // their target half.
8053 // FIXME: This operation could almost certainly be simplified dramatically to
8054 // look more like the 3-1 fixing operation.
8055 auto moveInputsToRightHalf = [&PSHUFDMask](
8056 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8057 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8058 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8060 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8061 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8063 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8065 int LowWord = Word & ~1;
8066 int HighWord = Word | 1;
8067 return isWordClobbered(SourceHalfMask, LowWord) ||
8068 isWordClobbered(SourceHalfMask, HighWord);
8071 if (IncomingInputs.empty())
8074 if (ExistingInputs.empty()) {
8075 // Map any dwords with inputs from them into the right half.
8076 for (int Input : IncomingInputs) {
8077 // If the source half mask maps over the inputs, turn those into
8078 // swaps and use the swapped lane.
8079 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8080 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8081 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8082 Input - SourceOffset;
8083 // We have to swap the uses in our half mask in one sweep.
8084 for (int &M : HalfMask)
8085 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8087 else if (M == Input)
8088 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8090 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8091 Input - SourceOffset &&
8092 "Previous placement doesn't match!");
8094 // Note that this correctly re-maps both when we do a swap and when
8095 // we observe the other side of the swap above. We rely on that to
8096 // avoid swapping the members of the input list directly.
8097 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8100 // Map the input's dword into the correct half.
8101 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8102 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8104 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8106 "Previous placement doesn't match!");
8109 // And just directly shift any other-half mask elements to be same-half
8110 // as we will have mirrored the dword containing the element into the
8111 // same position within that half.
8112 for (int &M : HalfMask)
8113 if (M >= SourceOffset && M < SourceOffset + 4) {
8114 M = M - SourceOffset + DestOffset;
8115 assert(M >= 0 && "This should never wrap below zero!");
8120 // Ensure we have the input in a viable dword of its current half. This
8121 // is particularly tricky because the original position may be clobbered
8122 // by inputs being moved and *staying* in that half.
8123 if (IncomingInputs.size() == 1) {
8124 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8125 int InputFixed = std::find(std::begin(SourceHalfMask),
8126 std::end(SourceHalfMask), -1) -
8127 std::begin(SourceHalfMask) + SourceOffset;
8128 SourceHalfMask[InputFixed - SourceOffset] =
8129 IncomingInputs[0] - SourceOffset;
8130 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8132 IncomingInputs[0] = InputFixed;
8134 } else if (IncomingInputs.size() == 2) {
8135 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8136 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8137 // We have two non-adjacent or clobbered inputs we need to extract from
8138 // the source half. To do this, we need to map them into some adjacent
8139 // dword slot in the source mask.
8140 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8141 IncomingInputs[1] - SourceOffset};
8143 // If there is a free slot in the source half mask adjacent to one of
8144 // the inputs, place the other input in it. We use (Index XOR 1) to
8145 // compute an adjacent index.
8146 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8147 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8148 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8149 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8150 InputsFixed[1] = InputsFixed[0] ^ 1;
8151 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8152 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8153 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8154 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8155 InputsFixed[0] = InputsFixed[1] ^ 1;
8156 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8157 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8158 // The two inputs are in the same DWord but it is clobbered and the
8159 // adjacent DWord isn't used at all. Move both inputs to the free
8161 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8162 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8163 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8164 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8166 // The only way we hit this point is if there is no clobbering
8167 // (because there are no off-half inputs to this half) and there is no
8168 // free slot adjacent to one of the inputs. In this case, we have to
8169 // swap an input with a non-input.
8170 for (int i = 0; i < 4; ++i)
8171 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8172 "We can't handle any clobbers here!");
8173 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8174 "Cannot have adjacent inputs here!");
8176 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8177 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8179 // We also have to update the final source mask in this case because
8180 // it may need to undo the above swap.
8181 for (int &M : FinalSourceHalfMask)
8182 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8183 M = InputsFixed[1] + SourceOffset;
8184 else if (M == InputsFixed[1] + SourceOffset)
8185 M = (InputsFixed[0] ^ 1) + SourceOffset;
8187 InputsFixed[1] = InputsFixed[0] ^ 1;
8190 // Point everything at the fixed inputs.
8191 for (int &M : HalfMask)
8192 if (M == IncomingInputs[0])
8193 M = InputsFixed[0] + SourceOffset;
8194 else if (M == IncomingInputs[1])
8195 M = InputsFixed[1] + SourceOffset;
8197 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8198 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8201 llvm_unreachable("Unhandled input size!");
8204 // Now hoist the DWord down to the right half.
8205 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8206 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8207 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8208 for (int &M : HalfMask)
8209 for (int Input : IncomingInputs)
8211 M = FreeDWord * 2 + Input % 2;
8213 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8214 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8215 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8216 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8218 // Now enact all the shuffles we've computed to move the inputs into their
8220 if (!isNoopShuffleMask(PSHUFLMask))
8221 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8222 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8223 if (!isNoopShuffleMask(PSHUFHMask))
8224 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8225 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8226 if (!isNoopShuffleMask(PSHUFDMask))
8227 V = DAG.getNode(ISD::BITCAST, DL, VT,
8228 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8229 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8230 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8232 // At this point, each half should contain all its inputs, and we can then
8233 // just shuffle them into their final position.
8234 assert(std::count_if(LoMask.begin(), LoMask.end(),
8235 [](int M) { return M >= 4; }) == 0 &&
8236 "Failed to lift all the high half inputs to the low mask!");
8237 assert(std::count_if(HiMask.begin(), HiMask.end(),
8238 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8239 "Failed to lift all the low half inputs to the high mask!");
8241 // Do a half shuffle for the low mask.
8242 if (!isNoopShuffleMask(LoMask))
8243 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8244 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8246 // Do a half shuffle with the high mask after shifting its values down.
8247 for (int &M : HiMask)
8250 if (!isNoopShuffleMask(HiMask))
8251 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8252 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8257 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8258 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8259 SDValue V2, ArrayRef<int> Mask,
8260 SelectionDAG &DAG, bool &V1InUse,
8262 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8268 int Size = Mask.size();
8269 int Scale = 16 / Size;
8270 for (int i = 0; i < 16; ++i) {
8271 if (Mask[i / Scale] == -1) {
8272 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8274 const int ZeroMask = 0x80;
8275 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8277 int V2Idx = Mask[i / Scale] < Size
8279 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8280 if (Zeroable[i / Scale])
8281 V1Idx = V2Idx = ZeroMask;
8282 V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
8283 V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
8284 V1InUse |= (ZeroMask != V1Idx);
8285 V2InUse |= (ZeroMask != V2Idx);
8290 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8291 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8292 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8294 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8295 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8296 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8298 // If we need shuffled inputs from both, blend the two.
8300 if (V1InUse && V2InUse)
8301 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8303 V = V1InUse ? V1 : V2;
8305 // Cast the result back to the correct type.
8306 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8309 /// \brief Generic lowering of 8-lane i16 shuffles.
8311 /// This handles both single-input shuffles and combined shuffle/blends with
8312 /// two inputs. The single input shuffles are immediately delegated to
8313 /// a dedicated lowering routine.
8315 /// The blends are lowered in one of three fundamental ways. If there are few
8316 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8317 /// of the input is significantly cheaper when lowered as an interleaving of
8318 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8319 /// halves of the inputs separately (making them have relatively few inputs)
8320 /// and then concatenate them.
8321 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8322 const X86Subtarget *Subtarget,
8323 SelectionDAG &DAG) {
8325 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8326 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8327 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8328 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8329 ArrayRef<int> OrigMask = SVOp->getMask();
8330 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8331 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8332 MutableArrayRef<int> Mask(MaskStorage);
8334 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8336 // Whenever we can lower this as a zext, that instruction is strictly faster
8337 // than any alternative.
8338 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8339 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8342 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8344 auto isV2 = [](int M) { return M >= 8; };
8346 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8348 if (NumV2Inputs == 0) {
8349 // Check for being able to broadcast a single element.
8350 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8351 Mask, Subtarget, DAG))
8354 // Try to use shift instructions.
8356 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8359 // Use dedicated unpack instructions for masks that match their pattern.
8360 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8361 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8362 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8363 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8365 // Try to use byte rotation instructions.
8366 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8367 Mask, Subtarget, DAG))
8370 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8374 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8375 "All single-input shuffles should be canonicalized to be V1-input "
8378 // Try to use shift instructions.
8380 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8383 // There are special ways we can lower some single-element blends.
8384 if (NumV2Inputs == 1)
8385 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8386 Mask, Subtarget, DAG))
8389 // We have different paths for blend lowering, but they all must use the
8390 // *exact* same predicate.
8391 bool IsBlendSupported = Subtarget->hasSSE41();
8392 if (IsBlendSupported)
8393 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8397 if (SDValue Masked =
8398 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8401 // Use dedicated unpack instructions for masks that match their pattern.
8402 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8403 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8404 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8405 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8407 // Try to use byte rotation instructions.
8408 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8409 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8412 if (SDValue BitBlend =
8413 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8416 if (SDValue Unpack =
8417 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8420 // If we can't directly blend but can use PSHUFB, that will be better as it
8421 // can both shuffle and set up the inefficient blend.
8422 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8423 bool V1InUse, V2InUse;
8424 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8428 // We can always bit-blend if we have to so the fallback strategy is to
8429 // decompose into single-input permutes and blends.
8430 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8434 /// \brief Check whether a compaction lowering can be done by dropping even
8435 /// elements and compute how many times even elements must be dropped.
8437 /// This handles shuffles which take every Nth element where N is a power of
8438 /// two. Example shuffle masks:
8440 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8441 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8442 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8443 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8444 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8445 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8447 /// Any of these lanes can of course be undef.
8449 /// This routine only supports N <= 3.
8450 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8453 /// \returns N above, or the number of times even elements must be dropped if
8454 /// there is such a number. Otherwise returns zero.
8455 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8456 // Figure out whether we're looping over two inputs or just one.
8457 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8459 // The modulus for the shuffle vector entries is based on whether this is
8460 // a single input or not.
8461 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8462 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8463 "We should only be called with masks with a power-of-2 size!");
8465 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8467 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8468 // and 2^3 simultaneously. This is because we may have ambiguity with
8469 // partially undef inputs.
8470 bool ViableForN[3] = {true, true, true};
8472 for (int i = 0, e = Mask.size(); i < e; ++i) {
8473 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8478 bool IsAnyViable = false;
8479 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8480 if (ViableForN[j]) {
8483 // The shuffle mask must be equal to (i * 2^N) % M.
8484 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8487 ViableForN[j] = false;
8489 // Early exit if we exhaust the possible powers of two.
8494 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8498 // Return 0 as there is no viable power of two.
8502 /// \brief Generic lowering of v16i8 shuffles.
8504 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8505 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8506 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8507 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8509 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8510 const X86Subtarget *Subtarget,
8511 SelectionDAG &DAG) {
8513 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8514 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8515 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8516 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8517 ArrayRef<int> Mask = SVOp->getMask();
8518 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8520 // Try to use shift instructions.
8522 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8525 // Try to use byte rotation instructions.
8526 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8527 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8530 // Try to use a zext lowering.
8531 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8532 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8536 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8538 // For single-input shuffles, there are some nicer lowering tricks we can use.
8539 if (NumV2Elements == 0) {
8540 // Check for being able to broadcast a single element.
8541 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8542 Mask, Subtarget, DAG))
8545 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8546 // Notably, this handles splat and partial-splat shuffles more efficiently.
8547 // However, it only makes sense if the pre-duplication shuffle simplifies
8548 // things significantly. Currently, this means we need to be able to
8549 // express the pre-duplication shuffle as an i16 shuffle.
8551 // FIXME: We should check for other patterns which can be widened into an
8552 // i16 shuffle as well.
8553 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8554 for (int i = 0; i < 16; i += 2)
8555 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8560 auto tryToWidenViaDuplication = [&]() -> SDValue {
8561 if (!canWidenViaDuplication(Mask))
8563 SmallVector<int, 4> LoInputs;
8564 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8565 [](int M) { return M >= 0 && M < 8; });
8566 std::sort(LoInputs.begin(), LoInputs.end());
8567 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8569 SmallVector<int, 4> HiInputs;
8570 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8571 [](int M) { return M >= 8; });
8572 std::sort(HiInputs.begin(), HiInputs.end());
8573 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8576 bool TargetLo = LoInputs.size() >= HiInputs.size();
8577 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8578 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8580 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8581 SmallDenseMap<int, int, 8> LaneMap;
8582 for (int I : InPlaceInputs) {
8583 PreDupI16Shuffle[I/2] = I/2;
8586 int j = TargetLo ? 0 : 4, je = j + 4;
8587 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8588 // Check if j is already a shuffle of this input. This happens when
8589 // there are two adjacent bytes after we move the low one.
8590 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8591 // If we haven't yet mapped the input, search for a slot into which
8593 while (j < je && PreDupI16Shuffle[j] != -1)
8597 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8600 // Map this input with the i16 shuffle.
8601 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8604 // Update the lane map based on the mapping we ended up with.
8605 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8608 ISD::BITCAST, DL, MVT::v16i8,
8609 DAG.getVectorShuffle(MVT::v8i16, DL,
8610 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8611 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8613 // Unpack the bytes to form the i16s that will be shuffled into place.
8614 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8615 MVT::v16i8, V1, V1);
8617 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8618 for (int i = 0; i < 16; ++i)
8619 if (Mask[i] != -1) {
8620 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8621 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8622 if (PostDupI16Shuffle[i / 2] == -1)
8623 PostDupI16Shuffle[i / 2] = MappedMask;
8625 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8626 "Conflicting entrties in the original shuffle!");
8629 ISD::BITCAST, DL, MVT::v16i8,
8630 DAG.getVectorShuffle(MVT::v8i16, DL,
8631 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8632 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8634 if (SDValue V = tryToWidenViaDuplication())
8638 // Use dedicated unpack instructions for masks that match their pattern.
8639 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8640 0, 16, 1, 17, 2, 18, 3, 19,
8642 4, 20, 5, 21, 6, 22, 7, 23}))
8643 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8644 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8645 8, 24, 9, 25, 10, 26, 11, 27,
8647 12, 28, 13, 29, 14, 30, 15, 31}))
8648 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8650 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8651 // with PSHUFB. It is important to do this before we attempt to generate any
8652 // blends but after all of the single-input lowerings. If the single input
8653 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8654 // want to preserve that and we can DAG combine any longer sequences into
8655 // a PSHUFB in the end. But once we start blending from multiple inputs,
8656 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8657 // and there are *very* few patterns that would actually be faster than the
8658 // PSHUFB approach because of its ability to zero lanes.
8660 // FIXME: The only exceptions to the above are blends which are exact
8661 // interleavings with direct instructions supporting them. We currently don't
8662 // handle those well here.
8663 if (Subtarget->hasSSSE3()) {
8664 bool V1InUse = false;
8665 bool V2InUse = false;
8667 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8668 DAG, V1InUse, V2InUse);
8670 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8671 // do so. This avoids using them to handle blends-with-zero which is
8672 // important as a single pshufb is significantly faster for that.
8673 if (V1InUse && V2InUse) {
8674 if (Subtarget->hasSSE41())
8675 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8676 Mask, Subtarget, DAG))
8679 // We can use an unpack to do the blending rather than an or in some
8680 // cases. Even though the or may be (very minorly) more efficient, we
8681 // preference this lowering because there are common cases where part of
8682 // the complexity of the shuffles goes away when we do the final blend as
8684 // FIXME: It might be worth trying to detect if the unpack-feeding
8685 // shuffles will both be pshufb, in which case we shouldn't bother with
8687 if (SDValue Unpack =
8688 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8695 // There are special ways we can lower some single-element blends.
8696 if (NumV2Elements == 1)
8697 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8698 Mask, Subtarget, DAG))
8701 if (SDValue BitBlend =
8702 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8705 // Check whether a compaction lowering can be done. This handles shuffles
8706 // which take every Nth element for some even N. See the helper function for
8709 // We special case these as they can be particularly efficiently handled with
8710 // the PACKUSB instruction on x86 and they show up in common patterns of
8711 // rearranging bytes to truncate wide elements.
8712 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8713 // NumEvenDrops is the power of two stride of the elements. Another way of
8714 // thinking about it is that we need to drop the even elements this many
8715 // times to get the original input.
8716 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8718 // First we need to zero all the dropped bytes.
8719 assert(NumEvenDrops <= 3 &&
8720 "No support for dropping even elements more than 3 times.");
8721 // We use the mask type to pick which bytes are preserved based on how many
8722 // elements are dropped.
8723 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8724 SDValue ByteClearMask =
8725 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8726 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8727 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8729 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8731 // Now pack things back together.
8732 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8733 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8734 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8735 for (int i = 1; i < NumEvenDrops; ++i) {
8736 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8737 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8743 // Handle multi-input cases by blending single-input shuffles.
8744 if (NumV2Elements > 0)
8745 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8748 // The fallback path for single-input shuffles widens this into two v8i16
8749 // vectors with unpacks, shuffles those, and then pulls them back together
8753 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8754 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8755 for (int i = 0; i < 16; ++i)
8757 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8759 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8761 SDValue VLoHalf, VHiHalf;
8762 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8763 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8765 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8766 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8767 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8768 [](int M) { return M >= 0 && M % 2 == 1; })) {
8769 // Use a mask to drop the high bytes.
8770 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8771 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8772 DAG.getConstant(0x00FF, MVT::v8i16));
8774 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8775 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8777 // Squash the masks to point directly into VLoHalf.
8778 for (int &M : LoBlendMask)
8781 for (int &M : HiBlendMask)
8785 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8786 // VHiHalf so that we can blend them as i16s.
8787 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8788 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8789 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8790 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8793 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8794 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8796 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8799 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8801 /// This routine breaks down the specific type of 128-bit shuffle and
8802 /// dispatches to the lowering routines accordingly.
8803 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8804 MVT VT, const X86Subtarget *Subtarget,
8805 SelectionDAG &DAG) {
8806 switch (VT.SimpleTy) {
8808 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8810 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8812 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8814 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8816 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8818 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8821 llvm_unreachable("Unimplemented!");
8825 /// \brief Helper function to test whether a shuffle mask could be
8826 /// simplified by widening the elements being shuffled.
8828 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8829 /// leaves it in an unspecified state.
8831 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8832 /// shuffle masks. The latter have the special property of a '-2' representing
8833 /// a zero-ed lane of a vector.
8834 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8835 SmallVectorImpl<int> &WidenedMask) {
8836 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8837 // If both elements are undef, its trivial.
8838 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8839 WidenedMask.push_back(SM_SentinelUndef);
8843 // Check for an undef mask and a mask value properly aligned to fit with
8844 // a pair of values. If we find such a case, use the non-undef mask's value.
8845 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8846 WidenedMask.push_back(Mask[i + 1] / 2);
8849 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8850 WidenedMask.push_back(Mask[i] / 2);
8854 // When zeroing, we need to spread the zeroing across both lanes to widen.
8855 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8856 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8857 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8858 WidenedMask.push_back(SM_SentinelZero);
8864 // Finally check if the two mask values are adjacent and aligned with
8866 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8867 WidenedMask.push_back(Mask[i] / 2);
8871 // Otherwise we can't safely widen the elements used in this shuffle.
8874 assert(WidenedMask.size() == Mask.size() / 2 &&
8875 "Incorrect size of mask after widening the elements!");
8880 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8882 /// This routine just extracts two subvectors, shuffles them independently, and
8883 /// then concatenates them back together. This should work effectively with all
8884 /// AVX vector shuffle types.
8885 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8886 SDValue V2, ArrayRef<int> Mask,
8887 SelectionDAG &DAG) {
8888 assert(VT.getSizeInBits() >= 256 &&
8889 "Only for 256-bit or wider vector shuffles!");
8890 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8891 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8893 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8894 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8896 int NumElements = VT.getVectorNumElements();
8897 int SplitNumElements = NumElements / 2;
8898 MVT ScalarVT = VT.getScalarType();
8899 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8901 // Rather than splitting build-vectors, just build two narrower build
8902 // vectors. This helps shuffling with splats and zeros.
8903 auto SplitVector = [&](SDValue V) {
8904 while (V.getOpcode() == ISD::BITCAST)
8905 V = V->getOperand(0);
8907 MVT OrigVT = V.getSimpleValueType();
8908 int OrigNumElements = OrigVT.getVectorNumElements();
8909 int OrigSplitNumElements = OrigNumElements / 2;
8910 MVT OrigScalarVT = OrigVT.getScalarType();
8911 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
8915 auto *BV = dyn_cast<BuildVectorSDNode>(V);
8917 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8918 DAG.getIntPtrConstant(0));
8919 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8920 DAG.getIntPtrConstant(OrigSplitNumElements));
8923 SmallVector<SDValue, 16> LoOps, HiOps;
8924 for (int i = 0; i < OrigSplitNumElements; ++i) {
8925 LoOps.push_back(BV->getOperand(i));
8926 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
8928 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
8929 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
8931 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
8932 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
8935 SDValue LoV1, HiV1, LoV2, HiV2;
8936 std::tie(LoV1, HiV1) = SplitVector(V1);
8937 std::tie(LoV2, HiV2) = SplitVector(V2);
8939 // Now create two 4-way blends of these half-width vectors.
8940 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8941 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
8942 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
8943 for (int i = 0; i < SplitNumElements; ++i) {
8944 int M = HalfMask[i];
8945 if (M >= NumElements) {
8946 if (M >= NumElements + SplitNumElements)
8950 V2BlendMask.push_back(M - NumElements);
8951 V1BlendMask.push_back(-1);
8952 BlendMask.push_back(SplitNumElements + i);
8953 } else if (M >= 0) {
8954 if (M >= SplitNumElements)
8958 V2BlendMask.push_back(-1);
8959 V1BlendMask.push_back(M);
8960 BlendMask.push_back(i);
8962 V2BlendMask.push_back(-1);
8963 V1BlendMask.push_back(-1);
8964 BlendMask.push_back(-1);
8968 // Because the lowering happens after all combining takes place, we need to
8969 // manually combine these blend masks as much as possible so that we create
8970 // a minimal number of high-level vector shuffle nodes.
8972 // First try just blending the halves of V1 or V2.
8973 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
8974 return DAG.getUNDEF(SplitVT);
8975 if (!UseLoV2 && !UseHiV2)
8976 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8977 if (!UseLoV1 && !UseHiV1)
8978 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8980 SDValue V1Blend, V2Blend;
8981 if (UseLoV1 && UseHiV1) {
8983 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8985 // We only use half of V1 so map the usage down into the final blend mask.
8986 V1Blend = UseLoV1 ? LoV1 : HiV1;
8987 for (int i = 0; i < SplitNumElements; ++i)
8988 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
8989 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
8991 if (UseLoV2 && UseHiV2) {
8993 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8995 // We only use half of V2 so map the usage down into the final blend mask.
8996 V2Blend = UseLoV2 ? LoV2 : HiV2;
8997 for (int i = 0; i < SplitNumElements; ++i)
8998 if (BlendMask[i] >= SplitNumElements)
8999 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9001 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9003 SDValue Lo = HalfBlend(LoMask);
9004 SDValue Hi = HalfBlend(HiMask);
9005 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9008 /// \brief Either split a vector in halves or decompose the shuffles and the
9011 /// This is provided as a good fallback for many lowerings of non-single-input
9012 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9013 /// between splitting the shuffle into 128-bit components and stitching those
9014 /// back together vs. extracting the single-input shuffles and blending those
9016 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9017 SDValue V2, ArrayRef<int> Mask,
9018 SelectionDAG &DAG) {
9019 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9020 "lower single-input shuffles as it "
9021 "could then recurse on itself.");
9022 int Size = Mask.size();
9024 // If this can be modeled as a broadcast of two elements followed by a blend,
9025 // prefer that lowering. This is especially important because broadcasts can
9026 // often fold with memory operands.
9027 auto DoBothBroadcast = [&] {
9028 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9031 if (V2BroadcastIdx == -1)
9032 V2BroadcastIdx = M - Size;
9033 else if (M - Size != V2BroadcastIdx)
9035 } else if (M >= 0) {
9036 if (V1BroadcastIdx == -1)
9038 else if (M != V1BroadcastIdx)
9043 if (DoBothBroadcast())
9044 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9047 // If the inputs all stem from a single 128-bit lane of each input, then we
9048 // split them rather than blending because the split will decompose to
9049 // unusually few instructions.
9050 int LaneCount = VT.getSizeInBits() / 128;
9051 int LaneSize = Size / LaneCount;
9052 SmallBitVector LaneInputs[2];
9053 LaneInputs[0].resize(LaneCount, false);
9054 LaneInputs[1].resize(LaneCount, false);
9055 for (int i = 0; i < Size; ++i)
9057 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9058 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9059 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9061 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9062 // that the decomposed single-input shuffles don't end up here.
9063 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9066 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9067 /// a permutation and blend of those lanes.
9069 /// This essentially blends the out-of-lane inputs to each lane into the lane
9070 /// from a permuted copy of the vector. This lowering strategy results in four
9071 /// instructions in the worst case for a single-input cross lane shuffle which
9072 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9073 /// of. Special cases for each particular shuffle pattern should be handled
9074 /// prior to trying this lowering.
9075 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9076 SDValue V1, SDValue V2,
9078 SelectionDAG &DAG) {
9079 // FIXME: This should probably be generalized for 512-bit vectors as well.
9080 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9081 int LaneSize = Mask.size() / 2;
9083 // If there are only inputs from one 128-bit lane, splitting will in fact be
9084 // less expensive. The flags track whether the given lane contains an element
9085 // that crosses to another lane.
9086 bool LaneCrossing[2] = {false, false};
9087 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9088 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9089 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9090 if (!LaneCrossing[0] || !LaneCrossing[1])
9091 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9093 if (isSingleInputShuffleMask(Mask)) {
9094 SmallVector<int, 32> FlippedBlendMask;
9095 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9096 FlippedBlendMask.push_back(
9097 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9099 : Mask[i] % LaneSize +
9100 (i / LaneSize) * LaneSize + Size));
9102 // Flip the vector, and blend the results which should now be in-lane. The
9103 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9104 // 5 for the high source. The value 3 selects the high half of source 2 and
9105 // the value 2 selects the low half of source 2. We only use source 2 to
9106 // allow folding it into a memory operand.
9107 unsigned PERMMask = 3 | 2 << 4;
9108 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9109 V1, DAG.getConstant(PERMMask, MVT::i8));
9110 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9113 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9114 // will be handled by the above logic and a blend of the results, much like
9115 // other patterns in AVX.
9116 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9119 /// \brief Handle lowering 2-lane 128-bit shuffles.
9120 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9121 SDValue V2, ArrayRef<int> Mask,
9122 const X86Subtarget *Subtarget,
9123 SelectionDAG &DAG) {
9124 // TODO: If minimizing size and one of the inputs is a zero vector and the
9125 // the zero vector has only one use, we could use a VPERM2X128 to save the
9126 // instruction bytes needed to explicitly generate the zero vector.
9128 // Blends are faster and handle all the non-lane-crossing cases.
9129 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9133 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9134 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9136 // If either input operand is a zero vector, use VPERM2X128 because its mask
9137 // allows us to replace the zero input with an implicit zero.
9138 if (!IsV1Zero && !IsV2Zero) {
9139 // Check for patterns which can be matched with a single insert of a 128-bit
9141 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9142 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9143 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9144 VT.getVectorNumElements() / 2);
9145 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9146 DAG.getIntPtrConstant(0));
9147 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9148 OnlyUsesV1 ? V1 : V2, DAG.getIntPtrConstant(0));
9149 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9153 // Otherwise form a 128-bit permutation. After accounting for undefs,
9154 // convert the 64-bit shuffle mask selection values into 128-bit
9155 // selection bits by dividing the indexes by 2 and shifting into positions
9156 // defined by a vperm2*128 instruction's immediate control byte.
9158 // The immediate permute control byte looks like this:
9159 // [1:0] - select 128 bits from sources for low half of destination
9161 // [3] - zero low half of destination
9162 // [5:4] - select 128 bits from sources for high half of destination
9164 // [7] - zero high half of destination
9166 int MaskLO = Mask[0];
9167 if (MaskLO == SM_SentinelUndef)
9168 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9170 int MaskHI = Mask[2];
9171 if (MaskHI == SM_SentinelUndef)
9172 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9174 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9176 // If either input is a zero vector, replace it with an undef input.
9177 // Shuffle mask values < 4 are selecting elements of V1.
9178 // Shuffle mask values >= 4 are selecting elements of V2.
9179 // Adjust each half of the permute mask by clearing the half that was
9180 // selecting the zero vector and setting the zero mask bit.
9182 V1 = DAG.getUNDEF(VT);
9184 PermMask = (PermMask & 0xf0) | 0x08;
9186 PermMask = (PermMask & 0x0f) | 0x80;
9189 V2 = DAG.getUNDEF(VT);
9191 PermMask = (PermMask & 0xf0) | 0x08;
9193 PermMask = (PermMask & 0x0f) | 0x80;
9196 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9197 DAG.getConstant(PermMask, MVT::i8));
9200 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9201 /// shuffling each lane.
9203 /// This will only succeed when the result of fixing the 128-bit lanes results
9204 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9205 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9206 /// the lane crosses early and then use simpler shuffles within each lane.
9208 /// FIXME: It might be worthwhile at some point to support this without
9209 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9210 /// in x86 only floating point has interesting non-repeating shuffles, and even
9211 /// those are still *marginally* more expensive.
9212 static SDValue lowerVectorShuffleByMerging128BitLanes(
9213 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9214 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9215 assert(!isSingleInputShuffleMask(Mask) &&
9216 "This is only useful with multiple inputs.");
9218 int Size = Mask.size();
9219 int LaneSize = 128 / VT.getScalarSizeInBits();
9220 int NumLanes = Size / LaneSize;
9221 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9223 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9224 // check whether the in-128-bit lane shuffles share a repeating pattern.
9225 SmallVector<int, 4> Lanes;
9226 Lanes.resize(NumLanes, -1);
9227 SmallVector<int, 4> InLaneMask;
9228 InLaneMask.resize(LaneSize, -1);
9229 for (int i = 0; i < Size; ++i) {
9233 int j = i / LaneSize;
9236 // First entry we've seen for this lane.
9237 Lanes[j] = Mask[i] / LaneSize;
9238 } else if (Lanes[j] != Mask[i] / LaneSize) {
9239 // This doesn't match the lane selected previously!
9243 // Check that within each lane we have a consistent shuffle mask.
9244 int k = i % LaneSize;
9245 if (InLaneMask[k] < 0) {
9246 InLaneMask[k] = Mask[i] % LaneSize;
9247 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9248 // This doesn't fit a repeating in-lane mask.
9253 // First shuffle the lanes into place.
9254 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9255 VT.getSizeInBits() / 64);
9256 SmallVector<int, 8> LaneMask;
9257 LaneMask.resize(NumLanes * 2, -1);
9258 for (int i = 0; i < NumLanes; ++i)
9259 if (Lanes[i] >= 0) {
9260 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9261 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9264 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9265 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9266 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9268 // Cast it back to the type we actually want.
9269 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9271 // Now do a simple shuffle that isn't lane crossing.
9272 SmallVector<int, 8> NewMask;
9273 NewMask.resize(Size, -1);
9274 for (int i = 0; i < Size; ++i)
9276 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9277 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9278 "Must not introduce lane crosses at this point!");
9280 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9283 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9286 /// This returns true if the elements from a particular input are already in the
9287 /// slot required by the given mask and require no permutation.
9288 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9289 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9290 int Size = Mask.size();
9291 for (int i = 0; i < Size; ++i)
9292 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9298 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9300 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9301 /// isn't available.
9302 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9303 const X86Subtarget *Subtarget,
9304 SelectionDAG &DAG) {
9306 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9307 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9308 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9309 ArrayRef<int> Mask = SVOp->getMask();
9310 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9312 SmallVector<int, 4> WidenedMask;
9313 if (canWidenShuffleElements(Mask, WidenedMask))
9314 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9317 if (isSingleInputShuffleMask(Mask)) {
9318 // Check for being able to broadcast a single element.
9319 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9320 Mask, Subtarget, DAG))
9323 // Use low duplicate instructions for masks that match their pattern.
9324 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9325 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9327 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9328 // Non-half-crossing single input shuffles can be lowerid with an
9329 // interleaved permutation.
9330 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9331 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9332 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9333 DAG.getConstant(VPERMILPMask, MVT::i8));
9336 // With AVX2 we have direct support for this permutation.
9337 if (Subtarget->hasAVX2())
9338 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9339 getV4X86ShuffleImm8ForMask(Mask, DAG));
9341 // Otherwise, fall back.
9342 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9346 // X86 has dedicated unpack instructions that can handle specific blend
9347 // operations: UNPCKH and UNPCKL.
9348 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9349 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9350 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9351 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9352 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9353 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9354 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9355 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9357 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9361 // Check if the blend happens to exactly fit that of SHUFPD.
9362 if ((Mask[0] == -1 || Mask[0] < 2) &&
9363 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9364 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9365 (Mask[3] == -1 || Mask[3] >= 6)) {
9366 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9367 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9368 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9369 DAG.getConstant(SHUFPDMask, MVT::i8));
9371 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9372 (Mask[1] == -1 || Mask[1] < 2) &&
9373 (Mask[2] == -1 || Mask[2] >= 6) &&
9374 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9375 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9376 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9377 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9378 DAG.getConstant(SHUFPDMask, MVT::i8));
9381 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9382 // shuffle. However, if we have AVX2 and either inputs are already in place,
9383 // we will be able to shuffle even across lanes the other input in a single
9384 // instruction so skip this pattern.
9385 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9386 isShuffleMaskInputInPlace(1, Mask))))
9387 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9388 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9391 // If we have AVX2 then we always want to lower with a blend because an v4 we
9392 // can fully permute the elements.
9393 if (Subtarget->hasAVX2())
9394 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9397 // Otherwise fall back on generic lowering.
9398 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9401 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9403 /// This routine is only called when we have AVX2 and thus a reasonable
9404 /// instruction set for v4i64 shuffling..
9405 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9406 const X86Subtarget *Subtarget,
9407 SelectionDAG &DAG) {
9409 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9410 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9411 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9412 ArrayRef<int> Mask = SVOp->getMask();
9413 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9414 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9416 SmallVector<int, 4> WidenedMask;
9417 if (canWidenShuffleElements(Mask, WidenedMask))
9418 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9421 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9425 // Check for being able to broadcast a single element.
9426 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9427 Mask, Subtarget, DAG))
9430 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9431 // use lower latency instructions that will operate on both 128-bit lanes.
9432 SmallVector<int, 2> RepeatedMask;
9433 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9434 if (isSingleInputShuffleMask(Mask)) {
9435 int PSHUFDMask[] = {-1, -1, -1, -1};
9436 for (int i = 0; i < 2; ++i)
9437 if (RepeatedMask[i] >= 0) {
9438 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9439 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9442 ISD::BITCAST, DL, MVT::v4i64,
9443 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9444 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9445 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9449 // AVX2 provides a direct instruction for permuting a single input across
9451 if (isSingleInputShuffleMask(Mask))
9452 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9453 getV4X86ShuffleImm8ForMask(Mask, DAG));
9455 // Try to use shift instructions.
9457 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9460 // Use dedicated unpack instructions for masks that match their pattern.
9461 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9462 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9463 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9464 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9465 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9466 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9467 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9468 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9470 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9471 // shuffle. However, if we have AVX2 and either inputs are already in place,
9472 // we will be able to shuffle even across lanes the other input in a single
9473 // instruction so skip this pattern.
9474 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9475 isShuffleMaskInputInPlace(1, Mask))))
9476 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9477 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9480 // Otherwise fall back on generic blend lowering.
9481 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9485 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9487 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9488 /// isn't available.
9489 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9490 const X86Subtarget *Subtarget,
9491 SelectionDAG &DAG) {
9493 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9494 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9495 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9496 ArrayRef<int> Mask = SVOp->getMask();
9497 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9499 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9503 // Check for being able to broadcast a single element.
9504 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9505 Mask, Subtarget, DAG))
9508 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9509 // options to efficiently lower the shuffle.
9510 SmallVector<int, 4> RepeatedMask;
9511 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9512 assert(RepeatedMask.size() == 4 &&
9513 "Repeated masks must be half the mask width!");
9515 // Use even/odd duplicate instructions for masks that match their pattern.
9516 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9517 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9518 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9519 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9521 if (isSingleInputShuffleMask(Mask))
9522 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9523 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9525 // Use dedicated unpack instructions for masks that match their pattern.
9526 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9527 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9528 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9529 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9530 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9531 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9532 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9533 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9535 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9536 // have already handled any direct blends. We also need to squash the
9537 // repeated mask into a simulated v4f32 mask.
9538 for (int i = 0; i < 4; ++i)
9539 if (RepeatedMask[i] >= 8)
9540 RepeatedMask[i] -= 4;
9541 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9544 // If we have a single input shuffle with different shuffle patterns in the
9545 // two 128-bit lanes use the variable mask to VPERMILPS.
9546 if (isSingleInputShuffleMask(Mask)) {
9547 SDValue VPermMask[8];
9548 for (int i = 0; i < 8; ++i)
9549 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9550 : DAG.getConstant(Mask[i], MVT::i32);
9551 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9553 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9554 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9556 if (Subtarget->hasAVX2())
9557 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9558 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9559 DAG.getNode(ISD::BUILD_VECTOR, DL,
9560 MVT::v8i32, VPermMask)),
9563 // Otherwise, fall back.
9564 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9568 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9570 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9571 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9574 // If we have AVX2 then we always want to lower with a blend because at v8 we
9575 // can fully permute the elements.
9576 if (Subtarget->hasAVX2())
9577 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9580 // Otherwise fall back on generic lowering.
9581 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9584 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9586 /// This routine is only called when we have AVX2 and thus a reasonable
9587 /// instruction set for v8i32 shuffling..
9588 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9589 const X86Subtarget *Subtarget,
9590 SelectionDAG &DAG) {
9592 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9593 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9594 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9595 ArrayRef<int> Mask = SVOp->getMask();
9596 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9597 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9599 // Whenever we can lower this as a zext, that instruction is strictly faster
9600 // than any alternative. It also allows us to fold memory operands into the
9601 // shuffle in many cases.
9602 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9603 Mask, Subtarget, DAG))
9606 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9610 // Check for being able to broadcast a single element.
9611 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9612 Mask, Subtarget, DAG))
9615 // If the shuffle mask is repeated in each 128-bit lane we can use more
9616 // efficient instructions that mirror the shuffles across the two 128-bit
9618 SmallVector<int, 4> RepeatedMask;
9619 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9620 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9621 if (isSingleInputShuffleMask(Mask))
9622 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9623 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9625 // Use dedicated unpack instructions for masks that match their pattern.
9626 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9627 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9628 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9629 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9630 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9631 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9632 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9633 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9636 // Try to use shift instructions.
9638 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9641 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9642 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9645 // If the shuffle patterns aren't repeated but it is a single input, directly
9646 // generate a cross-lane VPERMD instruction.
9647 if (isSingleInputShuffleMask(Mask)) {
9648 SDValue VPermMask[8];
9649 for (int i = 0; i < 8; ++i)
9650 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9651 : DAG.getConstant(Mask[i], MVT::i32);
9653 X86ISD::VPERMV, DL, MVT::v8i32,
9654 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9657 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9659 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9660 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9663 // Otherwise fall back on generic blend lowering.
9664 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9668 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9670 /// This routine is only called when we have AVX2 and thus a reasonable
9671 /// instruction set for v16i16 shuffling..
9672 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9673 const X86Subtarget *Subtarget,
9674 SelectionDAG &DAG) {
9676 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9677 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9678 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9679 ArrayRef<int> Mask = SVOp->getMask();
9680 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9681 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9683 // Whenever we can lower this as a zext, that instruction is strictly faster
9684 // than any alternative. It also allows us to fold memory operands into the
9685 // shuffle in many cases.
9686 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9687 Mask, Subtarget, DAG))
9690 // Check for being able to broadcast a single element.
9691 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9692 Mask, Subtarget, DAG))
9695 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9699 // Use dedicated unpack instructions for masks that match their pattern.
9700 if (isShuffleEquivalent(V1, V2, Mask,
9701 {// First 128-bit lane:
9702 0, 16, 1, 17, 2, 18, 3, 19,
9703 // Second 128-bit lane:
9704 8, 24, 9, 25, 10, 26, 11, 27}))
9705 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9706 if (isShuffleEquivalent(V1, V2, Mask,
9707 {// First 128-bit lane:
9708 4, 20, 5, 21, 6, 22, 7, 23,
9709 // Second 128-bit lane:
9710 12, 28, 13, 29, 14, 30, 15, 31}))
9711 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9713 // Try to use shift instructions.
9715 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9718 // Try to use byte rotation instructions.
9719 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9720 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9723 if (isSingleInputShuffleMask(Mask)) {
9724 // There are no generalized cross-lane shuffle operations available on i16
9726 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9727 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9730 SmallVector<int, 8> RepeatedMask;
9731 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9732 // As this is a single-input shuffle, the repeated mask should be
9733 // a strictly valid v8i16 mask that we can pass through to the v8i16
9734 // lowering to handle even the v16 case.
9735 return lowerV8I16GeneralSingleInputVectorShuffle(
9736 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9739 SDValue PSHUFBMask[32];
9740 for (int i = 0; i < 16; ++i) {
9741 if (Mask[i] == -1) {
9742 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9746 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9747 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9748 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9749 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9752 ISD::BITCAST, DL, MVT::v16i16,
9754 X86ISD::PSHUFB, DL, MVT::v32i8,
9755 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9756 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9759 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9761 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9762 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9765 // Otherwise fall back on generic lowering.
9766 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9769 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9771 /// This routine is only called when we have AVX2 and thus a reasonable
9772 /// instruction set for v32i8 shuffling..
9773 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9774 const X86Subtarget *Subtarget,
9775 SelectionDAG &DAG) {
9777 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9778 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9779 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9780 ArrayRef<int> Mask = SVOp->getMask();
9781 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9782 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9784 // Whenever we can lower this as a zext, that instruction is strictly faster
9785 // than any alternative. It also allows us to fold memory operands into the
9786 // shuffle in many cases.
9787 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9788 Mask, Subtarget, DAG))
9791 // Check for being able to broadcast a single element.
9792 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9793 Mask, Subtarget, DAG))
9796 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9800 // Use dedicated unpack instructions for masks that match their pattern.
9801 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9803 if (isShuffleEquivalent(
9805 {// First 128-bit lane:
9806 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9807 // Second 128-bit lane:
9808 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9809 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9810 if (isShuffleEquivalent(
9812 {// First 128-bit lane:
9813 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9814 // Second 128-bit lane:
9815 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9816 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9818 // Try to use shift instructions.
9820 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9823 // Try to use byte rotation instructions.
9824 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9825 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9828 if (isSingleInputShuffleMask(Mask)) {
9829 // There are no generalized cross-lane shuffle operations available on i8
9831 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9832 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9835 SDValue PSHUFBMask[32];
9836 for (int i = 0; i < 32; ++i)
9839 ? DAG.getUNDEF(MVT::i8)
9840 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9843 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9844 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9847 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9849 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9850 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9853 // Otherwise fall back on generic lowering.
9854 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9857 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9859 /// This routine either breaks down the specific type of a 256-bit x86 vector
9860 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9861 /// together based on the available instructions.
9862 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9863 MVT VT, const X86Subtarget *Subtarget,
9864 SelectionDAG &DAG) {
9866 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9867 ArrayRef<int> Mask = SVOp->getMask();
9869 // If we have a single input to the zero element, insert that into V1 if we
9870 // can do so cheaply.
9871 int NumElts = VT.getVectorNumElements();
9872 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
9873 return M >= NumElts;
9876 if (NumV2Elements == 1 && Mask[0] >= NumElts)
9877 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9878 DL, VT, V1, V2, Mask, Subtarget, DAG))
9881 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9882 // check for those subtargets here and avoid much of the subtarget querying in
9883 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9884 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9885 // floating point types there eventually, just immediately cast everything to
9886 // a float and operate entirely in that domain.
9887 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9888 int ElementBits = VT.getScalarSizeInBits();
9889 if (ElementBits < 32)
9890 // No floating point type available, decompose into 128-bit vectors.
9891 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9893 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9894 VT.getVectorNumElements());
9895 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9896 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9897 return DAG.getNode(ISD::BITCAST, DL, VT,
9898 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9901 switch (VT.SimpleTy) {
9903 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9905 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9907 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9909 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9911 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9913 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9916 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9920 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9921 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9922 const X86Subtarget *Subtarget,
9923 SelectionDAG &DAG) {
9925 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9926 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9927 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9928 ArrayRef<int> Mask = SVOp->getMask();
9929 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9931 // X86 has dedicated unpack instructions that can handle specific blend
9932 // operations: UNPCKH and UNPCKL.
9933 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9934 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
9935 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9936 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
9938 // FIXME: Implement direct support for this type!
9939 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9942 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9943 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9944 const X86Subtarget *Subtarget,
9945 SelectionDAG &DAG) {
9947 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9948 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9949 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9950 ArrayRef<int> Mask = SVOp->getMask();
9951 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9953 // Use dedicated unpack instructions for masks that match their pattern.
9954 if (isShuffleEquivalent(V1, V2, Mask,
9955 {// First 128-bit lane.
9956 0, 16, 1, 17, 4, 20, 5, 21,
9957 // Second 128-bit lane.
9958 8, 24, 9, 25, 12, 28, 13, 29}))
9959 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
9960 if (isShuffleEquivalent(V1, V2, Mask,
9961 {// First 128-bit lane.
9962 2, 18, 3, 19, 6, 22, 7, 23,
9963 // Second 128-bit lane.
9964 10, 26, 11, 27, 14, 30, 15, 31}))
9965 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
9967 // FIXME: Implement direct support for this type!
9968 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
9971 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
9972 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9973 const X86Subtarget *Subtarget,
9974 SelectionDAG &DAG) {
9976 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9977 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9978 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9979 ArrayRef<int> Mask = SVOp->getMask();
9980 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9982 // X86 has dedicated unpack instructions that can handle specific blend
9983 // operations: UNPCKH and UNPCKL.
9984 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9985 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
9986 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9987 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
9989 // FIXME: Implement direct support for this type!
9990 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
9993 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
9994 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9995 const X86Subtarget *Subtarget,
9996 SelectionDAG &DAG) {
9998 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
9999 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10000 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10001 ArrayRef<int> Mask = SVOp->getMask();
10002 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10004 // Use dedicated unpack instructions for masks that match their pattern.
10005 if (isShuffleEquivalent(V1, V2, Mask,
10006 {// First 128-bit lane.
10007 0, 16, 1, 17, 4, 20, 5, 21,
10008 // Second 128-bit lane.
10009 8, 24, 9, 25, 12, 28, 13, 29}))
10010 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10011 if (isShuffleEquivalent(V1, V2, Mask,
10012 {// First 128-bit lane.
10013 2, 18, 3, 19, 6, 22, 7, 23,
10014 // Second 128-bit lane.
10015 10, 26, 11, 27, 14, 30, 15, 31}))
10016 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10018 // FIXME: Implement direct support for this type!
10019 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10022 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10023 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10024 const X86Subtarget *Subtarget,
10025 SelectionDAG &DAG) {
10027 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10028 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10029 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10030 ArrayRef<int> Mask = SVOp->getMask();
10031 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10032 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10034 // FIXME: Implement direct support for this type!
10035 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10038 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10039 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10040 const X86Subtarget *Subtarget,
10041 SelectionDAG &DAG) {
10043 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10044 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10045 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10046 ArrayRef<int> Mask = SVOp->getMask();
10047 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10048 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10050 // FIXME: Implement direct support for this type!
10051 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10054 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10056 /// This routine either breaks down the specific type of a 512-bit x86 vector
10057 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10058 /// together based on the available instructions.
10059 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10060 MVT VT, const X86Subtarget *Subtarget,
10061 SelectionDAG &DAG) {
10063 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10064 ArrayRef<int> Mask = SVOp->getMask();
10065 assert(Subtarget->hasAVX512() &&
10066 "Cannot lower 512-bit vectors w/ basic ISA!");
10068 // Check for being able to broadcast a single element.
10069 if (SDValue Broadcast =
10070 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10073 // Dispatch to each element type for lowering. If we don't have supprot for
10074 // specific element type shuffles at 512 bits, immediately split them and
10075 // lower them. Each lowering routine of a given type is allowed to assume that
10076 // the requisite ISA extensions for that element type are available.
10077 switch (VT.SimpleTy) {
10079 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10081 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10083 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10085 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10087 if (Subtarget->hasBWI())
10088 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10091 if (Subtarget->hasBWI())
10092 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10096 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10099 // Otherwise fall back on splitting.
10100 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10103 /// \brief Top-level lowering for x86 vector shuffles.
10105 /// This handles decomposition, canonicalization, and lowering of all x86
10106 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10107 /// above in helper routines. The canonicalization attempts to widen shuffles
10108 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10109 /// s.t. only one of the two inputs needs to be tested, etc.
10110 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10111 SelectionDAG &DAG) {
10112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10113 ArrayRef<int> Mask = SVOp->getMask();
10114 SDValue V1 = Op.getOperand(0);
10115 SDValue V2 = Op.getOperand(1);
10116 MVT VT = Op.getSimpleValueType();
10117 int NumElements = VT.getVectorNumElements();
10120 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10122 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10123 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10124 if (V1IsUndef && V2IsUndef)
10125 return DAG.getUNDEF(VT);
10127 // When we create a shuffle node we put the UNDEF node to second operand,
10128 // but in some cases the first operand may be transformed to UNDEF.
10129 // In this case we should just commute the node.
10131 return DAG.getCommutedVectorShuffle(*SVOp);
10133 // Check for non-undef masks pointing at an undef vector and make the masks
10134 // undef as well. This makes it easier to match the shuffle based solely on
10138 if (M >= NumElements) {
10139 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10140 for (int &M : NewMask)
10141 if (M >= NumElements)
10143 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10146 // We actually see shuffles that are entirely re-arrangements of a set of
10147 // zero inputs. This mostly happens while decomposing complex shuffles into
10148 // simple ones. Directly lower these as a buildvector of zeros.
10149 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10150 if (Zeroable.all())
10151 return getZeroVector(VT, Subtarget, DAG, dl);
10153 // Try to collapse shuffles into using a vector type with fewer elements but
10154 // wider element types. We cap this to not form integers or floating point
10155 // elements wider than 64 bits, but it might be interesting to form i128
10156 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10157 SmallVector<int, 16> WidenedMask;
10158 if (VT.getScalarSizeInBits() < 64 &&
10159 canWidenShuffleElements(Mask, WidenedMask)) {
10160 MVT NewEltVT = VT.isFloatingPoint()
10161 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10162 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10163 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10164 // Make sure that the new vector type is legal. For example, v2f64 isn't
10166 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10167 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10168 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10169 return DAG.getNode(ISD::BITCAST, dl, VT,
10170 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10174 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10175 for (int M : SVOp->getMask())
10177 ++NumUndefElements;
10178 else if (M < NumElements)
10183 // Commute the shuffle as needed such that more elements come from V1 than
10184 // V2. This allows us to match the shuffle pattern strictly on how many
10185 // elements come from V1 without handling the symmetric cases.
10186 if (NumV2Elements > NumV1Elements)
10187 return DAG.getCommutedVectorShuffle(*SVOp);
10189 // When the number of V1 and V2 elements are the same, try to minimize the
10190 // number of uses of V2 in the low half of the vector. When that is tied,
10191 // ensure that the sum of indices for V1 is equal to or lower than the sum
10192 // indices for V2. When those are equal, try to ensure that the number of odd
10193 // indices for V1 is lower than the number of odd indices for V2.
10194 if (NumV1Elements == NumV2Elements) {
10195 int LowV1Elements = 0, LowV2Elements = 0;
10196 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10197 if (M >= NumElements)
10201 if (LowV2Elements > LowV1Elements) {
10202 return DAG.getCommutedVectorShuffle(*SVOp);
10203 } else if (LowV2Elements == LowV1Elements) {
10204 int SumV1Indices = 0, SumV2Indices = 0;
10205 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10206 if (SVOp->getMask()[i] >= NumElements)
10208 else if (SVOp->getMask()[i] >= 0)
10210 if (SumV2Indices < SumV1Indices) {
10211 return DAG.getCommutedVectorShuffle(*SVOp);
10212 } else if (SumV2Indices == SumV1Indices) {
10213 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10214 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10215 if (SVOp->getMask()[i] >= NumElements)
10216 NumV2OddIndices += i % 2;
10217 else if (SVOp->getMask()[i] >= 0)
10218 NumV1OddIndices += i % 2;
10219 if (NumV2OddIndices < NumV1OddIndices)
10220 return DAG.getCommutedVectorShuffle(*SVOp);
10225 // For each vector width, delegate to a specialized lowering routine.
10226 if (VT.getSizeInBits() == 128)
10227 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10229 if (VT.getSizeInBits() == 256)
10230 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10232 // Force AVX-512 vectors to be scalarized for now.
10233 // FIXME: Implement AVX-512 support!
10234 if (VT.getSizeInBits() == 512)
10235 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10237 llvm_unreachable("Unimplemented!");
10240 // This function assumes its argument is a BUILD_VECTOR of constants or
10241 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10243 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10244 unsigned &MaskValue) {
10246 unsigned NumElems = BuildVector->getNumOperands();
10247 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10248 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10249 unsigned NumElemsInLane = NumElems / NumLanes;
10251 // Blend for v16i16 should be symetric for the both lanes.
10252 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10253 SDValue EltCond = BuildVector->getOperand(i);
10254 SDValue SndLaneEltCond =
10255 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10257 int Lane1Cond = -1, Lane2Cond = -1;
10258 if (isa<ConstantSDNode>(EltCond))
10259 Lane1Cond = !isZero(EltCond);
10260 if (isa<ConstantSDNode>(SndLaneEltCond))
10261 Lane2Cond = !isZero(SndLaneEltCond);
10263 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10264 // Lane1Cond != 0, means we want the first argument.
10265 // Lane1Cond == 0, means we want the second argument.
10266 // The encoding of this argument is 0 for the first argument, 1
10267 // for the second. Therefore, invert the condition.
10268 MaskValue |= !Lane1Cond << i;
10269 else if (Lane1Cond < 0)
10270 MaskValue |= !Lane2Cond << i;
10277 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10278 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10279 const X86Subtarget *Subtarget,
10280 SelectionDAG &DAG) {
10281 SDValue Cond = Op.getOperand(0);
10282 SDValue LHS = Op.getOperand(1);
10283 SDValue RHS = Op.getOperand(2);
10285 MVT VT = Op.getSimpleValueType();
10287 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10289 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10291 // Only non-legal VSELECTs reach this lowering, convert those into generic
10292 // shuffles and re-use the shuffle lowering path for blends.
10293 SmallVector<int, 32> Mask;
10294 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10295 SDValue CondElt = CondBV->getOperand(i);
10297 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10299 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10302 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10303 // A vselect where all conditions and data are constants can be optimized into
10304 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10305 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10306 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10307 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10310 // Try to lower this to a blend-style vector shuffle. This can handle all
10311 // constant condition cases.
10312 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10315 // Variable blends are only legal from SSE4.1 onward.
10316 if (!Subtarget->hasSSE41())
10319 // Only some types will be legal on some subtargets. If we can emit a legal
10320 // VSELECT-matching blend, return Op, and but if we need to expand, return
10322 switch (Op.getSimpleValueType().SimpleTy) {
10324 // Most of the vector types have blends past SSE4.1.
10328 // The byte blends for AVX vectors were introduced only in AVX2.
10329 if (Subtarget->hasAVX2())
10336 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10337 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10340 // FIXME: We should custom lower this by fixing the condition and using i8
10346 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10347 MVT VT = Op.getSimpleValueType();
10350 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10353 if (VT.getSizeInBits() == 8) {
10354 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10355 Op.getOperand(0), Op.getOperand(1));
10356 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10357 DAG.getValueType(VT));
10358 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10361 if (VT.getSizeInBits() == 16) {
10362 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10363 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10365 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10366 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10367 DAG.getNode(ISD::BITCAST, dl,
10370 Op.getOperand(1)));
10371 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10372 Op.getOperand(0), Op.getOperand(1));
10373 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10374 DAG.getValueType(VT));
10375 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10378 if (VT == MVT::f32) {
10379 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10380 // the result back to FR32 register. It's only worth matching if the
10381 // result has a single use which is a store or a bitcast to i32. And in
10382 // the case of a store, it's not worth it if the index is a constant 0,
10383 // because a MOVSSmr can be used instead, which is smaller and faster.
10384 if (!Op.hasOneUse())
10386 SDNode *User = *Op.getNode()->use_begin();
10387 if ((User->getOpcode() != ISD::STORE ||
10388 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10389 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10390 (User->getOpcode() != ISD::BITCAST ||
10391 User->getValueType(0) != MVT::i32))
10393 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10394 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10397 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10400 if (VT == MVT::i32 || VT == MVT::i64) {
10401 // ExtractPS/pextrq works with constant index.
10402 if (isa<ConstantSDNode>(Op.getOperand(1)))
10408 /// Extract one bit from mask vector, like v16i1 or v8i1.
10409 /// AVX-512 feature.
10411 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10412 SDValue Vec = Op.getOperand(0);
10414 MVT VecVT = Vec.getSimpleValueType();
10415 SDValue Idx = Op.getOperand(1);
10416 MVT EltVT = Op.getSimpleValueType();
10418 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10419 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10420 "Unexpected vector type in ExtractBitFromMaskVector");
10422 // variable index can't be handled in mask registers,
10423 // extend vector to VR512
10424 if (!isa<ConstantSDNode>(Idx)) {
10425 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10426 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10427 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10428 ExtVT.getVectorElementType(), Ext, Idx);
10429 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10432 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10433 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10434 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10435 rc = getRegClassFor(MVT::v16i1);
10436 unsigned MaxSift = rc->getSize()*8 - 1;
10437 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10438 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10439 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10440 DAG.getConstant(MaxSift, MVT::i8));
10441 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10442 DAG.getIntPtrConstant(0));
10446 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10447 SelectionDAG &DAG) const {
10449 SDValue Vec = Op.getOperand(0);
10450 MVT VecVT = Vec.getSimpleValueType();
10451 SDValue Idx = Op.getOperand(1);
10453 if (Op.getSimpleValueType() == MVT::i1)
10454 return ExtractBitFromMaskVector(Op, DAG);
10456 if (!isa<ConstantSDNode>(Idx)) {
10457 if (VecVT.is512BitVector() ||
10458 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10459 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10462 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10463 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10464 MaskEltVT.getSizeInBits());
10466 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10467 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10468 getZeroVector(MaskVT, Subtarget, DAG, dl),
10469 Idx, DAG.getConstant(0, getPointerTy()));
10470 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10471 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10472 Perm, DAG.getConstant(0, getPointerTy()));
10477 // If this is a 256-bit vector result, first extract the 128-bit vector and
10478 // then extract the element from the 128-bit vector.
10479 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10481 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10482 // Get the 128-bit vector.
10483 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10484 MVT EltVT = VecVT.getVectorElementType();
10486 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10488 //if (IdxVal >= NumElems/2)
10489 // IdxVal -= NumElems/2;
10490 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10491 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10492 DAG.getConstant(IdxVal, MVT::i32));
10495 assert(VecVT.is128BitVector() && "Unexpected vector length");
10497 if (Subtarget->hasSSE41()) {
10498 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10503 MVT VT = Op.getSimpleValueType();
10504 // TODO: handle v16i8.
10505 if (VT.getSizeInBits() == 16) {
10506 SDValue Vec = Op.getOperand(0);
10507 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10509 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10510 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10511 DAG.getNode(ISD::BITCAST, dl,
10513 Op.getOperand(1)));
10514 // Transform it so it match pextrw which produces a 32-bit result.
10515 MVT EltVT = MVT::i32;
10516 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10517 Op.getOperand(0), Op.getOperand(1));
10518 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10519 DAG.getValueType(VT));
10520 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10523 if (VT.getSizeInBits() == 32) {
10524 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10528 // SHUFPS the element to the lowest double word, then movss.
10529 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10530 MVT VVT = Op.getOperand(0).getSimpleValueType();
10531 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10532 DAG.getUNDEF(VVT), Mask);
10533 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10534 DAG.getIntPtrConstant(0));
10537 if (VT.getSizeInBits() == 64) {
10538 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10539 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10540 // to match extract_elt for f64.
10541 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10545 // UNPCKHPD the element to the lowest double word, then movsd.
10546 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10547 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10548 int Mask[2] = { 1, -1 };
10549 MVT VVT = Op.getOperand(0).getSimpleValueType();
10550 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10551 DAG.getUNDEF(VVT), Mask);
10552 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10553 DAG.getIntPtrConstant(0));
10559 /// Insert one bit to mask vector, like v16i1 or v8i1.
10560 /// AVX-512 feature.
10562 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10564 SDValue Vec = Op.getOperand(0);
10565 SDValue Elt = Op.getOperand(1);
10566 SDValue Idx = Op.getOperand(2);
10567 MVT VecVT = Vec.getSimpleValueType();
10569 if (!isa<ConstantSDNode>(Idx)) {
10570 // Non constant index. Extend source and destination,
10571 // insert element and then truncate the result.
10572 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10573 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10574 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10575 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10576 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10577 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10580 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10581 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10582 if (Vec.getOpcode() == ISD::UNDEF)
10583 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10584 DAG.getConstant(IdxVal, MVT::i8));
10585 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10586 unsigned MaxSift = rc->getSize()*8 - 1;
10587 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10588 DAG.getConstant(MaxSift, MVT::i8));
10589 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10590 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10591 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10594 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10595 SelectionDAG &DAG) const {
10596 MVT VT = Op.getSimpleValueType();
10597 MVT EltVT = VT.getVectorElementType();
10599 if (EltVT == MVT::i1)
10600 return InsertBitToMaskVector(Op, DAG);
10603 SDValue N0 = Op.getOperand(0);
10604 SDValue N1 = Op.getOperand(1);
10605 SDValue N2 = Op.getOperand(2);
10606 if (!isa<ConstantSDNode>(N2))
10608 auto *N2C = cast<ConstantSDNode>(N2);
10609 unsigned IdxVal = N2C->getZExtValue();
10611 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10612 // into that, and then insert the subvector back into the result.
10613 if (VT.is256BitVector() || VT.is512BitVector()) {
10614 // With a 256-bit vector, we can insert into the zero element efficiently
10615 // using a blend if we have AVX or AVX2 and the right data type.
10616 if (VT.is256BitVector() && IdxVal == 0) {
10617 // TODO: It is worthwhile to cast integer to floating point and back
10618 // and incur a domain crossing penalty if that's what we'll end up
10619 // doing anyway after extracting to a 128-bit vector.
10620 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10621 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10622 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10623 N2 = DAG.getIntPtrConstant(1);
10624 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10628 // Get the desired 128-bit vector chunk.
10629 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10631 // Insert the element into the desired chunk.
10632 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10633 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10635 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10636 DAG.getConstant(IdxIn128, MVT::i32));
10638 // Insert the changed part back into the bigger vector
10639 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10641 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10643 if (Subtarget->hasSSE41()) {
10644 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10646 if (VT == MVT::v8i16) {
10647 Opc = X86ISD::PINSRW;
10649 assert(VT == MVT::v16i8);
10650 Opc = X86ISD::PINSRB;
10653 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10655 if (N1.getValueType() != MVT::i32)
10656 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10657 if (N2.getValueType() != MVT::i32)
10658 N2 = DAG.getIntPtrConstant(IdxVal);
10659 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10662 if (EltVT == MVT::f32) {
10663 // Bits [7:6] of the constant are the source select. This will always be
10664 // zero here. The DAG Combiner may combine an extract_elt index into
10665 // these bits. For example (insert (extract, 3), 2) could be matched by
10666 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10667 // Bits [5:4] of the constant are the destination select. This is the
10668 // value of the incoming immediate.
10669 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10670 // combine either bitwise AND or insert of float 0.0 to set these bits.
10672 const Function *F = DAG.getMachineFunction().getFunction();
10673 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10674 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10675 // If this is an insertion of 32-bits into the low 32-bits of
10676 // a vector, we prefer to generate a blend with immediate rather
10677 // than an insertps. Blends are simpler operations in hardware and so
10678 // will always have equal or better performance than insertps.
10679 // But if optimizing for size and there's a load folding opportunity,
10680 // generate insertps because blendps does not have a 32-bit memory
10682 N2 = DAG.getIntPtrConstant(1);
10683 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10684 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10686 N2 = DAG.getIntPtrConstant(IdxVal << 4);
10687 // Create this as a scalar to vector..
10688 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10689 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10692 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10693 // PINSR* works with constant index.
10698 if (EltVT == MVT::i8)
10701 if (EltVT.getSizeInBits() == 16) {
10702 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10703 // as its second argument.
10704 if (N1.getValueType() != MVT::i32)
10705 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10706 if (N2.getValueType() != MVT::i32)
10707 N2 = DAG.getIntPtrConstant(IdxVal);
10708 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10713 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10715 MVT OpVT = Op.getSimpleValueType();
10717 // If this is a 256-bit vector result, first insert into a 128-bit
10718 // vector and then insert into the 256-bit vector.
10719 if (!OpVT.is128BitVector()) {
10720 // Insert into a 128-bit vector.
10721 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10722 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10723 OpVT.getVectorNumElements() / SizeFactor);
10725 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10727 // Insert the 128-bit vector.
10728 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10731 if (OpVT == MVT::v1i64 &&
10732 Op.getOperand(0).getValueType() == MVT::i64)
10733 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10735 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10736 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10737 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10738 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10741 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10742 // a simple subregister reference or explicit instructions to grab
10743 // upper bits of a vector.
10744 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10745 SelectionDAG &DAG) {
10747 SDValue In = Op.getOperand(0);
10748 SDValue Idx = Op.getOperand(1);
10749 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10750 MVT ResVT = Op.getSimpleValueType();
10751 MVT InVT = In.getSimpleValueType();
10753 if (Subtarget->hasFp256()) {
10754 if (ResVT.is128BitVector() &&
10755 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10756 isa<ConstantSDNode>(Idx)) {
10757 return Extract128BitVector(In, IdxVal, DAG, dl);
10759 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10760 isa<ConstantSDNode>(Idx)) {
10761 return Extract256BitVector(In, IdxVal, DAG, dl);
10767 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10768 // simple superregister reference or explicit instructions to insert
10769 // the upper bits of a vector.
10770 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10771 SelectionDAG &DAG) {
10772 if (!Subtarget->hasAVX())
10776 SDValue Vec = Op.getOperand(0);
10777 SDValue SubVec = Op.getOperand(1);
10778 SDValue Idx = Op.getOperand(2);
10780 if (!isa<ConstantSDNode>(Idx))
10783 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10784 MVT OpVT = Op.getSimpleValueType();
10785 MVT SubVecVT = SubVec.getSimpleValueType();
10787 // Fold two 16-byte subvector loads into one 32-byte load:
10788 // (insert_subvector (insert_subvector undef, (load addr), 0),
10789 // (load addr + 16), Elts/2)
10791 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10792 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10793 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10794 !Subtarget->isUnalignedMem32Slow()) {
10795 SDValue SubVec2 = Vec.getOperand(1);
10796 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10797 if (Idx2->getZExtValue() == 0) {
10798 SDValue Ops[] = { SubVec2, SubVec };
10799 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10806 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10807 SubVecVT.is128BitVector())
10808 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10810 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10811 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10813 if (OpVT.getVectorElementType() == MVT::i1) {
10814 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10816 SDValue ZeroIdx = DAG.getIntPtrConstant(0);
10817 SDValue Undef = DAG.getUNDEF(OpVT);
10818 unsigned NumElems = OpVT.getVectorNumElements();
10819 SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);
10821 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10822 // Zero upper bits of the Vec
10823 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10824 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10826 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10828 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10829 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10832 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10834 // Zero upper bits of the Vec2
10835 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10836 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10837 // Zero lower bits of the Vec
10838 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10839 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10840 // Merge them together
10841 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10847 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10848 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10849 // one of the above mentioned nodes. It has to be wrapped because otherwise
10850 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10851 // be used to form addressing mode. These wrapped nodes will be selected
10854 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10855 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10857 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10858 // global base reg.
10859 unsigned char OpFlag = 0;
10860 unsigned WrapperKind = X86ISD::Wrapper;
10861 CodeModel::Model M = DAG.getTarget().getCodeModel();
10863 if (Subtarget->isPICStyleRIPRel() &&
10864 (M == CodeModel::Small || M == CodeModel::Kernel))
10865 WrapperKind = X86ISD::WrapperRIP;
10866 else if (Subtarget->isPICStyleGOT())
10867 OpFlag = X86II::MO_GOTOFF;
10868 else if (Subtarget->isPICStyleStubPIC())
10869 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10871 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10872 CP->getAlignment(),
10873 CP->getOffset(), OpFlag);
10875 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10876 // With PIC, the address is actually $g + Offset.
10878 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10879 DAG.getNode(X86ISD::GlobalBaseReg,
10880 SDLoc(), getPointerTy()),
10887 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10888 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10890 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10891 // global base reg.
10892 unsigned char OpFlag = 0;
10893 unsigned WrapperKind = X86ISD::Wrapper;
10894 CodeModel::Model M = DAG.getTarget().getCodeModel();
10896 if (Subtarget->isPICStyleRIPRel() &&
10897 (M == CodeModel::Small || M == CodeModel::Kernel))
10898 WrapperKind = X86ISD::WrapperRIP;
10899 else if (Subtarget->isPICStyleGOT())
10900 OpFlag = X86II::MO_GOTOFF;
10901 else if (Subtarget->isPICStyleStubPIC())
10902 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10904 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10907 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10909 // With PIC, the address is actually $g + Offset.
10911 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10912 DAG.getNode(X86ISD::GlobalBaseReg,
10913 SDLoc(), getPointerTy()),
10920 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10921 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10923 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10924 // global base reg.
10925 unsigned char OpFlag = 0;
10926 unsigned WrapperKind = X86ISD::Wrapper;
10927 CodeModel::Model M = DAG.getTarget().getCodeModel();
10929 if (Subtarget->isPICStyleRIPRel() &&
10930 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10931 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10932 OpFlag = X86II::MO_GOTPCREL;
10933 WrapperKind = X86ISD::WrapperRIP;
10934 } else if (Subtarget->isPICStyleGOT()) {
10935 OpFlag = X86II::MO_GOT;
10936 } else if (Subtarget->isPICStyleStubPIC()) {
10937 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10938 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10939 OpFlag = X86II::MO_DARWIN_NONLAZY;
10942 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10945 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10947 // With PIC, the address is actually $g + Offset.
10948 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10949 !Subtarget->is64Bit()) {
10950 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10951 DAG.getNode(X86ISD::GlobalBaseReg,
10952 SDLoc(), getPointerTy()),
10956 // For symbols that require a load from a stub to get the address, emit the
10958 if (isGlobalStubReference(OpFlag))
10959 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10960 MachinePointerInfo::getGOT(), false, false, false, 0);
10966 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10967 // Create the TargetBlockAddressAddress node.
10968 unsigned char OpFlags =
10969 Subtarget->ClassifyBlockAddressReference();
10970 CodeModel::Model M = DAG.getTarget().getCodeModel();
10971 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10972 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10974 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10977 if (Subtarget->isPICStyleRIPRel() &&
10978 (M == CodeModel::Small || M == CodeModel::Kernel))
10979 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10981 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10983 // With PIC, the address is actually $g + Offset.
10984 if (isGlobalRelativeToPICBase(OpFlags)) {
10985 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10986 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10994 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10995 int64_t Offset, SelectionDAG &DAG) const {
10996 // Create the TargetGlobalAddress node, folding in the constant
10997 // offset if it is legal.
10998 unsigned char OpFlags =
10999 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11000 CodeModel::Model M = DAG.getTarget().getCodeModel();
11002 if (OpFlags == X86II::MO_NO_FLAG &&
11003 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11004 // A direct static reference to a global.
11005 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11008 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11011 if (Subtarget->isPICStyleRIPRel() &&
11012 (M == CodeModel::Small || M == CodeModel::Kernel))
11013 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11015 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11017 // With PIC, the address is actually $g + Offset.
11018 if (isGlobalRelativeToPICBase(OpFlags)) {
11019 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11020 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11024 // For globals that require a load from a stub to get the address, emit the
11026 if (isGlobalStubReference(OpFlags))
11027 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11028 MachinePointerInfo::getGOT(), false, false, false, 0);
11030 // If there was a non-zero offset that we didn't fold, create an explicit
11031 // addition for it.
11033 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11034 DAG.getConstant(Offset, getPointerTy()));
11040 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11041 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11042 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11043 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11047 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11048 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11049 unsigned char OperandFlags, bool LocalDynamic = false) {
11050 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11051 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11053 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11054 GA->getValueType(0),
11058 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11062 SDValue Ops[] = { Chain, TGA, *InFlag };
11063 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11065 SDValue Ops[] = { Chain, TGA };
11066 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11069 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11070 MFI->setAdjustsStack(true);
11071 MFI->setHasCalls(true);
11073 SDValue Flag = Chain.getValue(1);
11074 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11077 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11079 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11082 SDLoc dl(GA); // ? function entry point might be better
11083 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11084 DAG.getNode(X86ISD::GlobalBaseReg,
11085 SDLoc(), PtrVT), InFlag);
11086 InFlag = Chain.getValue(1);
11088 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11091 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11093 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11095 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11096 X86::RAX, X86II::MO_TLSGD);
11099 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11105 // Get the start address of the TLS block for this module.
11106 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11107 .getInfo<X86MachineFunctionInfo>();
11108 MFI->incNumLocalDynamicTLSAccesses();
11112 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11113 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11116 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11117 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11118 InFlag = Chain.getValue(1);
11119 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11120 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11123 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11127 unsigned char OperandFlags = X86II::MO_DTPOFF;
11128 unsigned WrapperKind = X86ISD::Wrapper;
11129 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11130 GA->getValueType(0),
11131 GA->getOffset(), OperandFlags);
11132 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11134 // Add x@dtpoff with the base.
11135 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11138 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11139 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11140 const EVT PtrVT, TLSModel::Model model,
11141 bool is64Bit, bool isPIC) {
11144 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11145 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11146 is64Bit ? 257 : 256));
11148 SDValue ThreadPointer =
11149 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11150 MachinePointerInfo(Ptr), false, false, false, 0);
11152 unsigned char OperandFlags = 0;
11153 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11155 unsigned WrapperKind = X86ISD::Wrapper;
11156 if (model == TLSModel::LocalExec) {
11157 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11158 } else if (model == TLSModel::InitialExec) {
11160 OperandFlags = X86II::MO_GOTTPOFF;
11161 WrapperKind = X86ISD::WrapperRIP;
11163 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11166 llvm_unreachable("Unexpected model");
11169 // emit "addl x@ntpoff,%eax" (local exec)
11170 // or "addl x@indntpoff,%eax" (initial exec)
11171 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11173 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11174 GA->getOffset(), OperandFlags);
11175 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11177 if (model == TLSModel::InitialExec) {
11178 if (isPIC && !is64Bit) {
11179 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11180 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11184 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11185 MachinePointerInfo::getGOT(), false, false, false, 0);
11188 // The address of the thread local variable is the add of the thread
11189 // pointer with the offset of the variable.
11190 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11194 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11196 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11197 const GlobalValue *GV = GA->getGlobal();
11199 if (Subtarget->isTargetELF()) {
11200 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11203 case TLSModel::GeneralDynamic:
11204 if (Subtarget->is64Bit())
11205 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11206 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11207 case TLSModel::LocalDynamic:
11208 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11209 Subtarget->is64Bit());
11210 case TLSModel::InitialExec:
11211 case TLSModel::LocalExec:
11212 return LowerToTLSExecModel(
11213 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11214 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11216 llvm_unreachable("Unknown TLS model.");
11219 if (Subtarget->isTargetDarwin()) {
11220 // Darwin only has one model of TLS. Lower to that.
11221 unsigned char OpFlag = 0;
11222 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11223 X86ISD::WrapperRIP : X86ISD::Wrapper;
11225 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11226 // global base reg.
11227 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11228 !Subtarget->is64Bit();
11230 OpFlag = X86II::MO_TLVP_PIC_BASE;
11232 OpFlag = X86II::MO_TLVP;
11234 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11235 GA->getValueType(0),
11236 GA->getOffset(), OpFlag);
11237 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11239 // With PIC32, the address is actually $g + Offset.
11241 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11242 DAG.getNode(X86ISD::GlobalBaseReg,
11243 SDLoc(), getPointerTy()),
11246 // Lowering the machine isd will make sure everything is in the right
11248 SDValue Chain = DAG.getEntryNode();
11249 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11250 SDValue Args[] = { Chain, Offset };
11251 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11253 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11254 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11255 MFI->setAdjustsStack(true);
11257 // And our return value (tls address) is in the standard call return value
11259 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11260 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11261 Chain.getValue(1));
11264 if (Subtarget->isTargetKnownWindowsMSVC() ||
11265 Subtarget->isTargetWindowsGNU()) {
11266 // Just use the implicit TLS architecture
11267 // Need to generate someting similar to:
11268 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11270 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11271 // mov rcx, qword [rdx+rcx*8]
11272 // mov eax, .tls$:tlsvar
11273 // [rax+rcx] contains the address
11274 // Windows 64bit: gs:0x58
11275 // Windows 32bit: fs:__tls_array
11278 SDValue Chain = DAG.getEntryNode();
11280 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11281 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11282 // use its literal value of 0x2C.
11283 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11284 ? Type::getInt8PtrTy(*DAG.getContext(),
11286 : Type::getInt32PtrTy(*DAG.getContext(),
11290 Subtarget->is64Bit()
11291 ? DAG.getIntPtrConstant(0x58)
11292 : (Subtarget->isTargetWindowsGNU()
11293 ? DAG.getIntPtrConstant(0x2C)
11294 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11296 SDValue ThreadPointer =
11297 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11298 MachinePointerInfo(Ptr), false, false, false, 0);
11300 // Load the _tls_index variable
11301 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11302 if (Subtarget->is64Bit())
11303 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11304 IDX, MachinePointerInfo(), MVT::i32,
11305 false, false, false, 0);
11307 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11308 false, false, false, 0);
11310 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11312 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11314 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11315 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11316 false, false, false, 0);
11318 // Get the offset of start of .tls section
11319 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11320 GA->getValueType(0),
11321 GA->getOffset(), X86II::MO_SECREL);
11322 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11324 // The address of the thread local variable is the add of the thread
11325 // pointer with the offset of the variable.
11326 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11329 llvm_unreachable("TLS not implemented for this target.");
11332 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11333 /// and take a 2 x i32 value to shift plus a shift amount.
11334 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11335 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11336 MVT VT = Op.getSimpleValueType();
11337 unsigned VTBits = VT.getSizeInBits();
11339 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11340 SDValue ShOpLo = Op.getOperand(0);
11341 SDValue ShOpHi = Op.getOperand(1);
11342 SDValue ShAmt = Op.getOperand(2);
11343 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11344 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11346 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11347 DAG.getConstant(VTBits - 1, MVT::i8));
11348 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11349 DAG.getConstant(VTBits - 1, MVT::i8))
11350 : DAG.getConstant(0, VT);
11352 SDValue Tmp2, Tmp3;
11353 if (Op.getOpcode() == ISD::SHL_PARTS) {
11354 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11355 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11357 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11358 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11361 // If the shift amount is larger or equal than the width of a part we can't
11362 // rely on the results of shld/shrd. Insert a test and select the appropriate
11363 // values for large shift amounts.
11364 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11365 DAG.getConstant(VTBits, MVT::i8));
11366 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11367 AndNode, DAG.getConstant(0, MVT::i8));
11370 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11371 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11372 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11374 if (Op.getOpcode() == ISD::SHL_PARTS) {
11375 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11376 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11378 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11379 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11382 SDValue Ops[2] = { Lo, Hi };
11383 return DAG.getMergeValues(Ops, dl);
11386 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11387 SelectionDAG &DAG) const {
11388 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11391 if (SrcVT.isVector()) {
11392 if (SrcVT.getVectorElementType() == MVT::i1) {
11393 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11394 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11395 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11396 Op.getOperand(0)));
11401 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11402 "Unknown SINT_TO_FP to lower!");
11404 // These are really Legal; return the operand so the caller accepts it as
11406 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11408 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11409 Subtarget->is64Bit()) {
11413 unsigned Size = SrcVT.getSizeInBits()/8;
11414 MachineFunction &MF = DAG.getMachineFunction();
11415 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11416 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11417 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11419 MachinePointerInfo::getFixedStack(SSFI),
11421 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11424 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11426 SelectionDAG &DAG) const {
11430 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11432 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11434 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11436 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11438 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11439 MachineMemOperand *MMO;
11441 int SSFI = FI->getIndex();
11443 DAG.getMachineFunction()
11444 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11445 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11447 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11448 StackSlot = StackSlot.getOperand(1);
11450 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11451 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11453 Tys, Ops, SrcVT, MMO);
11456 Chain = Result.getValue(1);
11457 SDValue InFlag = Result.getValue(2);
11459 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11460 // shouldn't be necessary except that RFP cannot be live across
11461 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11462 MachineFunction &MF = DAG.getMachineFunction();
11463 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11464 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11465 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11466 Tys = DAG.getVTList(MVT::Other);
11468 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11470 MachineMemOperand *MMO =
11471 DAG.getMachineFunction()
11472 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11473 MachineMemOperand::MOStore, SSFISize, SSFISize);
11475 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11476 Ops, Op.getValueType(), MMO);
11477 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11478 MachinePointerInfo::getFixedStack(SSFI),
11479 false, false, false, 0);
11485 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11486 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11487 SelectionDAG &DAG) const {
11488 // This algorithm is not obvious. Here it is what we're trying to output:
11491 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11492 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11494 haddpd %xmm0, %xmm0
11496 pshufd $0x4e, %xmm0, %xmm1
11502 LLVMContext *Context = DAG.getContext();
11504 // Build some magic constants.
11505 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11506 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11507 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11509 SmallVector<Constant*,2> CV1;
11511 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11512 APInt(64, 0x4330000000000000ULL))));
11514 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11515 APInt(64, 0x4530000000000000ULL))));
11516 Constant *C1 = ConstantVector::get(CV1);
11517 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11519 // Load the 64-bit value into an XMM register.
11520 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11522 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11523 MachinePointerInfo::getConstantPool(),
11524 false, false, false, 16);
11525 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11526 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11529 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11530 MachinePointerInfo::getConstantPool(),
11531 false, false, false, 16);
11532 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11533 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11536 if (Subtarget->hasSSE3()) {
11537 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11538 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11540 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11541 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11543 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11544 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11548 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11549 DAG.getIntPtrConstant(0));
11552 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11553 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11554 SelectionDAG &DAG) const {
11556 // FP constant to bias correct the final result.
11557 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11560 // Load the 32-bit value into an XMM register.
11561 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11564 // Zero out the upper parts of the register.
11565 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11567 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11568 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11569 DAG.getIntPtrConstant(0));
11571 // Or the load with the bias.
11572 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11573 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11574 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11575 MVT::v2f64, Load)),
11576 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11577 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11578 MVT::v2f64, Bias)));
11579 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11580 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11581 DAG.getIntPtrConstant(0));
11583 // Subtract the bias.
11584 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11586 // Handle final rounding.
11587 EVT DestVT = Op.getValueType();
11589 if (DestVT.bitsLT(MVT::f64))
11590 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11591 DAG.getIntPtrConstant(0));
11592 if (DestVT.bitsGT(MVT::f64))
11593 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11595 // Handle final rounding.
11599 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11600 const X86Subtarget &Subtarget) {
11601 // The algorithm is the following:
11602 // #ifdef __SSE4_1__
11603 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11604 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11605 // (uint4) 0x53000000, 0xaa);
11607 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11608 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11610 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11611 // return (float4) lo + fhi;
11614 SDValue V = Op->getOperand(0);
11615 EVT VecIntVT = V.getValueType();
11616 bool Is128 = VecIntVT == MVT::v4i32;
11617 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11618 // If we convert to something else than the supported type, e.g., to v4f64,
11620 if (VecFloatVT != Op->getValueType(0))
11623 unsigned NumElts = VecIntVT.getVectorNumElements();
11624 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11625 "Unsupported custom type");
11626 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11628 // In the #idef/#else code, we have in common:
11629 // - The vector of constants:
11635 // Create the splat vector for 0x4b000000.
11636 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
11637 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11638 CstLow, CstLow, CstLow, CstLow};
11639 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11640 makeArrayRef(&CstLowArray[0], NumElts));
11641 // Create the splat vector for 0x53000000.
11642 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
11643 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11644 CstHigh, CstHigh, CstHigh, CstHigh};
11645 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11646 makeArrayRef(&CstHighArray[0], NumElts));
11648 // Create the right shift.
11649 SDValue CstShift = DAG.getConstant(16, MVT::i32);
11650 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11651 CstShift, CstShift, CstShift, CstShift};
11652 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11653 makeArrayRef(&CstShiftArray[0], NumElts));
11654 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11657 if (Subtarget.hasSSE41()) {
11658 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11659 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11660 SDValue VecCstLowBitcast =
11661 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11662 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11663 // Low will be bitcasted right away, so do not bother bitcasting back to its
11665 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11666 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
11667 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11668 // (uint4) 0x53000000, 0xaa);
11669 SDValue VecCstHighBitcast =
11670 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11671 SDValue VecShiftBitcast =
11672 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11673 // High will be bitcasted right away, so do not bother bitcasting back to
11674 // its original type.
11675 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11676 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
11678 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
11679 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11680 CstMask, CstMask, CstMask);
11681 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11682 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11683 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11685 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11686 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11689 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11690 SDValue CstFAdd = DAG.getConstantFP(
11691 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
11692 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11693 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11694 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11695 makeArrayRef(&CstFAddArray[0], NumElts));
11697 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11698 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11700 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11701 // return (float4) lo + fhi;
11702 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11703 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11706 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11707 SelectionDAG &DAG) const {
11708 SDValue N0 = Op.getOperand(0);
11709 MVT SVT = N0.getSimpleValueType();
11712 switch (SVT.SimpleTy) {
11714 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11719 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11720 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11721 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11725 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11727 llvm_unreachable(nullptr);
11730 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11731 SelectionDAG &DAG) const {
11732 SDValue N0 = Op.getOperand(0);
11735 if (Op.getValueType().isVector())
11736 return lowerUINT_TO_FP_vec(Op, DAG);
11738 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11739 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11740 // the optimization here.
11741 if (DAG.SignBitIsZero(N0))
11742 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11744 MVT SrcVT = N0.getSimpleValueType();
11745 MVT DstVT = Op.getSimpleValueType();
11746 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11747 return LowerUINT_TO_FP_i64(Op, DAG);
11748 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11749 return LowerUINT_TO_FP_i32(Op, DAG);
11750 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11753 // Make a 64-bit buffer, and use it to build an FILD.
11754 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11755 if (SrcVT == MVT::i32) {
11756 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11757 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11758 getPointerTy(), StackSlot, WordOff);
11759 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11760 StackSlot, MachinePointerInfo(),
11762 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11763 OffsetSlot, MachinePointerInfo(),
11765 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11769 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11770 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11771 StackSlot, MachinePointerInfo(),
11773 // For i64 source, we need to add the appropriate power of 2 if the input
11774 // was negative. This is the same as the optimization in
11775 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11776 // we must be careful to do the computation in x87 extended precision, not
11777 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11778 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11779 MachineMemOperand *MMO =
11780 DAG.getMachineFunction()
11781 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11782 MachineMemOperand::MOLoad, 8, 8);
11784 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11785 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11786 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11789 APInt FF(32, 0x5F800000ULL);
11791 // Check whether the sign bit is set.
11792 SDValue SignSet = DAG.getSetCC(dl,
11793 getSetCCResultType(*DAG.getContext(), MVT::i64),
11794 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11797 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11798 SDValue FudgePtr = DAG.getConstantPool(
11799 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11802 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11803 SDValue Zero = DAG.getIntPtrConstant(0);
11804 SDValue Four = DAG.getIntPtrConstant(4);
11805 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11807 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11809 // Load the value out, extending it from f32 to f80.
11810 // FIXME: Avoid the extend by constructing the right constant pool?
11811 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11812 FudgePtr, MachinePointerInfo::getConstantPool(),
11813 MVT::f32, false, false, false, 4);
11814 // Extend everything to 80 bits to force it to be done on x87.
11815 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11816 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11819 std::pair<SDValue,SDValue>
11820 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11821 bool IsSigned, bool IsReplace) const {
11824 EVT DstTy = Op.getValueType();
11826 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11827 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11831 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11832 DstTy.getSimpleVT() >= MVT::i16 &&
11833 "Unknown FP_TO_INT to lower!");
11835 // These are really Legal.
11836 if (DstTy == MVT::i32 &&
11837 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11838 return std::make_pair(SDValue(), SDValue());
11839 if (Subtarget->is64Bit() &&
11840 DstTy == MVT::i64 &&
11841 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11842 return std::make_pair(SDValue(), SDValue());
11844 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11845 // stack slot, or into the FTOL runtime function.
11846 MachineFunction &MF = DAG.getMachineFunction();
11847 unsigned MemSize = DstTy.getSizeInBits()/8;
11848 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11849 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11852 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11853 Opc = X86ISD::WIN_FTOL;
11855 switch (DstTy.getSimpleVT().SimpleTy) {
11856 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11857 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11858 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11859 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11862 SDValue Chain = DAG.getEntryNode();
11863 SDValue Value = Op.getOperand(0);
11864 EVT TheVT = Op.getOperand(0).getValueType();
11865 // FIXME This causes a redundant load/store if the SSE-class value is already
11866 // in memory, such as if it is on the callstack.
11867 if (isScalarFPTypeInSSEReg(TheVT)) {
11868 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11869 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11870 MachinePointerInfo::getFixedStack(SSFI),
11872 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11874 Chain, StackSlot, DAG.getValueType(TheVT)
11877 MachineMemOperand *MMO =
11878 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11879 MachineMemOperand::MOLoad, MemSize, MemSize);
11880 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11881 Chain = Value.getValue(1);
11882 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11883 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11886 MachineMemOperand *MMO =
11887 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11888 MachineMemOperand::MOStore, MemSize, MemSize);
11890 if (Opc != X86ISD::WIN_FTOL) {
11891 // Build the FP_TO_INT*_IN_MEM
11892 SDValue Ops[] = { Chain, Value, StackSlot };
11893 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11895 return std::make_pair(FIST, StackSlot);
11897 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11898 DAG.getVTList(MVT::Other, MVT::Glue),
11900 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11901 MVT::i32, ftol.getValue(1));
11902 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11903 MVT::i32, eax.getValue(2));
11904 SDValue Ops[] = { eax, edx };
11905 SDValue pair = IsReplace
11906 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11907 : DAG.getMergeValues(Ops, DL);
11908 return std::make_pair(pair, SDValue());
11912 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11913 const X86Subtarget *Subtarget) {
11914 MVT VT = Op->getSimpleValueType(0);
11915 SDValue In = Op->getOperand(0);
11916 MVT InVT = In.getSimpleValueType();
11919 // Optimize vectors in AVX mode:
11922 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11923 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11924 // Concat upper and lower parts.
11927 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11928 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11929 // Concat upper and lower parts.
11932 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11933 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11934 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11937 if (Subtarget->hasInt256())
11938 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11940 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11941 SDValue Undef = DAG.getUNDEF(InVT);
11942 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11943 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11944 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11946 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11947 VT.getVectorNumElements()/2);
11949 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11950 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11952 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11955 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11956 SelectionDAG &DAG) {
11957 MVT VT = Op->getSimpleValueType(0);
11958 SDValue In = Op->getOperand(0);
11959 MVT InVT = In.getSimpleValueType();
11961 unsigned int NumElts = VT.getVectorNumElements();
11962 if (NumElts != 8 && NumElts != 16)
11965 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11966 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11968 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11969 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11970 // Now we have only mask extension
11971 assert(InVT.getVectorElementType() == MVT::i1);
11972 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11973 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11974 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11975 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11976 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11977 MachinePointerInfo::getConstantPool(),
11978 false, false, false, Alignment);
11980 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11981 if (VT.is512BitVector())
11983 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11986 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11987 SelectionDAG &DAG) {
11988 if (Subtarget->hasFp256()) {
11989 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11997 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11998 SelectionDAG &DAG) {
12000 MVT VT = Op.getSimpleValueType();
12001 SDValue In = Op.getOperand(0);
12002 MVT SVT = In.getSimpleValueType();
12004 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12005 return LowerZERO_EXTEND_AVX512(Op, DAG);
12007 if (Subtarget->hasFp256()) {
12008 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12013 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12014 VT.getVectorNumElements() != SVT.getVectorNumElements());
12018 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12020 MVT VT = Op.getSimpleValueType();
12021 SDValue In = Op.getOperand(0);
12022 MVT InVT = In.getSimpleValueType();
12024 if (VT == MVT::i1) {
12025 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12026 "Invalid scalar TRUNCATE operation");
12027 if (InVT.getSizeInBits() >= 32)
12029 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12030 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12032 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12033 "Invalid TRUNCATE operation");
12035 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12036 if (VT.getVectorElementType().getSizeInBits() >=8)
12037 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12039 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12040 unsigned NumElts = InVT.getVectorNumElements();
12041 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12042 if (InVT.getSizeInBits() < 512) {
12043 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12044 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12048 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12049 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
12050 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12051 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12052 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12053 MachinePointerInfo::getConstantPool(),
12054 false, false, false, Alignment);
12055 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12056 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12057 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12060 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12061 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12062 if (Subtarget->hasInt256()) {
12063 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12064 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12065 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12067 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12068 DAG.getIntPtrConstant(0));
12071 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12072 DAG.getIntPtrConstant(0));
12073 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12074 DAG.getIntPtrConstant(2));
12075 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12076 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12077 static const int ShufMask[] = {0, 2, 4, 6};
12078 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12081 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12082 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12083 if (Subtarget->hasInt256()) {
12084 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12086 SmallVector<SDValue,32> pshufbMask;
12087 for (unsigned i = 0; i < 2; ++i) {
12088 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12089 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12090 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12091 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12092 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12093 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12094 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12095 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12096 for (unsigned j = 0; j < 8; ++j)
12097 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12099 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12100 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12101 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12103 static const int ShufMask[] = {0, 2, -1, -1};
12104 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12106 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12107 DAG.getIntPtrConstant(0));
12108 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12111 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12112 DAG.getIntPtrConstant(0));
12114 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12115 DAG.getIntPtrConstant(4));
12117 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12118 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12120 // The PSHUFB mask:
12121 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12122 -1, -1, -1, -1, -1, -1, -1, -1};
12124 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12125 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12126 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12128 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12129 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12131 // The MOVLHPS Mask:
12132 static const int ShufMask2[] = {0, 1, 4, 5};
12133 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12134 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12137 // Handle truncation of V256 to V128 using shuffles.
12138 if (!VT.is128BitVector() || !InVT.is256BitVector())
12141 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12143 unsigned NumElems = VT.getVectorNumElements();
12144 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12146 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12147 // Prepare truncation shuffle mask
12148 for (unsigned i = 0; i != NumElems; ++i)
12149 MaskVec[i] = i * 2;
12150 SDValue V = DAG.getVectorShuffle(NVT, DL,
12151 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12152 DAG.getUNDEF(NVT), &MaskVec[0]);
12153 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12154 DAG.getIntPtrConstant(0));
12157 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12158 SelectionDAG &DAG) const {
12159 assert(!Op.getSimpleValueType().isVector());
12161 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12162 /*IsSigned=*/ true, /*IsReplace=*/ false);
12163 SDValue FIST = Vals.first, StackSlot = Vals.second;
12164 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12165 if (!FIST.getNode()) return Op;
12167 if (StackSlot.getNode())
12168 // Load the result.
12169 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12170 FIST, StackSlot, MachinePointerInfo(),
12171 false, false, false, 0);
12173 // The node is the result.
12177 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12178 SelectionDAG &DAG) const {
12179 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12180 /*IsSigned=*/ false, /*IsReplace=*/ false);
12181 SDValue FIST = Vals.first, StackSlot = Vals.second;
12182 assert(FIST.getNode() && "Unexpected failure");
12184 if (StackSlot.getNode())
12185 // Load the result.
12186 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12187 FIST, StackSlot, MachinePointerInfo(),
12188 false, false, false, 0);
12190 // The node is the result.
12194 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12196 MVT VT = Op.getSimpleValueType();
12197 SDValue In = Op.getOperand(0);
12198 MVT SVT = In.getSimpleValueType();
12200 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12202 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12203 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12204 In, DAG.getUNDEF(SVT)));
12207 /// The only differences between FABS and FNEG are the mask and the logic op.
12208 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12209 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12210 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12211 "Wrong opcode for lowering FABS or FNEG.");
12213 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12215 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12216 // into an FNABS. We'll lower the FABS after that if it is still in use.
12218 for (SDNode *User : Op->uses())
12219 if (User->getOpcode() == ISD::FNEG)
12222 SDValue Op0 = Op.getOperand(0);
12223 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12226 MVT VT = Op.getSimpleValueType();
12227 // Assume scalar op for initialization; update for vector if needed.
12228 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12229 // generate a 16-byte vector constant and logic op even for the scalar case.
12230 // Using a 16-byte mask allows folding the load of the mask with
12231 // the logic op, so it can save (~4 bytes) on code size.
12233 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12234 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12235 // decide if we should generate a 16-byte constant mask when we only need 4 or
12236 // 8 bytes for the scalar case.
12237 if (VT.isVector()) {
12238 EltVT = VT.getVectorElementType();
12239 NumElts = VT.getVectorNumElements();
12242 unsigned EltBits = EltVT.getSizeInBits();
12243 LLVMContext *Context = DAG.getContext();
12244 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12246 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12247 Constant *C = ConstantInt::get(*Context, MaskElt);
12248 C = ConstantVector::getSplat(NumElts, C);
12249 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12250 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12251 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12252 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12253 MachinePointerInfo::getConstantPool(),
12254 false, false, false, Alignment);
12256 if (VT.isVector()) {
12257 // For a vector, cast operands to a vector type, perform the logic op,
12258 // and cast the result back to the original value type.
12259 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12260 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12261 SDValue Operand = IsFNABS ?
12262 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12263 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12264 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12265 return DAG.getNode(ISD::BITCAST, dl, VT,
12266 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12269 // If not vector, then scalar.
12270 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12271 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12272 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12275 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12276 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12277 LLVMContext *Context = DAG.getContext();
12278 SDValue Op0 = Op.getOperand(0);
12279 SDValue Op1 = Op.getOperand(1);
12281 MVT VT = Op.getSimpleValueType();
12282 MVT SrcVT = Op1.getSimpleValueType();
12284 // If second operand is smaller, extend it first.
12285 if (SrcVT.bitsLT(VT)) {
12286 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12289 // And if it is bigger, shrink it first.
12290 if (SrcVT.bitsGT(VT)) {
12291 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12295 // At this point the operands and the result should have the same
12296 // type, and that won't be f80 since that is not custom lowered.
12298 const fltSemantics &Sem =
12299 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12300 const unsigned SizeInBits = VT.getSizeInBits();
12302 SmallVector<Constant *, 4> CV(
12303 VT == MVT::f64 ? 2 : 4,
12304 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12306 // First, clear all bits but the sign bit from the second operand (sign).
12307 CV[0] = ConstantFP::get(*Context,
12308 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12309 Constant *C = ConstantVector::get(CV);
12310 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12311 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12312 MachinePointerInfo::getConstantPool(),
12313 false, false, false, 16);
12314 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12316 // Next, clear the sign bit from the first operand (magnitude).
12317 // If it's a constant, we can clear it here.
12318 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12319 APFloat APF = Op0CN->getValueAPF();
12320 // If the magnitude is a positive zero, the sign bit alone is enough.
12321 if (APF.isPosZero())
12324 CV[0] = ConstantFP::get(*Context, APF);
12326 CV[0] = ConstantFP::get(
12328 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12330 C = ConstantVector::get(CV);
12331 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12332 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12333 MachinePointerInfo::getConstantPool(),
12334 false, false, false, 16);
12335 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12336 if (!isa<ConstantFPSDNode>(Op0))
12337 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12339 // OR the magnitude value with the sign bit.
12340 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12343 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12344 SDValue N0 = Op.getOperand(0);
12346 MVT VT = Op.getSimpleValueType();
12348 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12349 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12350 DAG.getConstant(1, VT));
12351 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12354 // Check whether an OR'd tree is PTEST-able.
12355 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12356 SelectionDAG &DAG) {
12357 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12359 if (!Subtarget->hasSSE41())
12362 if (!Op->hasOneUse())
12365 SDNode *N = Op.getNode();
12368 SmallVector<SDValue, 8> Opnds;
12369 DenseMap<SDValue, unsigned> VecInMap;
12370 SmallVector<SDValue, 8> VecIns;
12371 EVT VT = MVT::Other;
12373 // Recognize a special case where a vector is casted into wide integer to
12375 Opnds.push_back(N->getOperand(0));
12376 Opnds.push_back(N->getOperand(1));
12378 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12379 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12380 // BFS traverse all OR'd operands.
12381 if (I->getOpcode() == ISD::OR) {
12382 Opnds.push_back(I->getOperand(0));
12383 Opnds.push_back(I->getOperand(1));
12384 // Re-evaluate the number of nodes to be traversed.
12385 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12389 // Quit if a non-EXTRACT_VECTOR_ELT
12390 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12393 // Quit if without a constant index.
12394 SDValue Idx = I->getOperand(1);
12395 if (!isa<ConstantSDNode>(Idx))
12398 SDValue ExtractedFromVec = I->getOperand(0);
12399 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12400 if (M == VecInMap.end()) {
12401 VT = ExtractedFromVec.getValueType();
12402 // Quit if not 128/256-bit vector.
12403 if (!VT.is128BitVector() && !VT.is256BitVector())
12405 // Quit if not the same type.
12406 if (VecInMap.begin() != VecInMap.end() &&
12407 VT != VecInMap.begin()->first.getValueType())
12409 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12410 VecIns.push_back(ExtractedFromVec);
12412 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12415 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12416 "Not extracted from 128-/256-bit vector.");
12418 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12420 for (DenseMap<SDValue, unsigned>::const_iterator
12421 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12422 // Quit if not all elements are used.
12423 if (I->second != FullMask)
12427 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12429 // Cast all vectors into TestVT for PTEST.
12430 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12431 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12433 // If more than one full vectors are evaluated, OR them first before PTEST.
12434 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12435 // Each iteration will OR 2 nodes and append the result until there is only
12436 // 1 node left, i.e. the final OR'd value of all vectors.
12437 SDValue LHS = VecIns[Slot];
12438 SDValue RHS = VecIns[Slot + 1];
12439 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12442 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12443 VecIns.back(), VecIns.back());
12446 /// \brief return true if \c Op has a use that doesn't just read flags.
12447 static bool hasNonFlagsUse(SDValue Op) {
12448 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12450 SDNode *User = *UI;
12451 unsigned UOpNo = UI.getOperandNo();
12452 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12453 // Look pass truncate.
12454 UOpNo = User->use_begin().getOperandNo();
12455 User = *User->use_begin();
12458 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12459 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12465 /// Emit nodes that will be selected as "test Op0,Op0", or something
12467 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12468 SelectionDAG &DAG) const {
12469 if (Op.getValueType() == MVT::i1) {
12470 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12471 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12472 DAG.getConstant(0, MVT::i8));
12474 // CF and OF aren't always set the way we want. Determine which
12475 // of these we need.
12476 bool NeedCF = false;
12477 bool NeedOF = false;
12480 case X86::COND_A: case X86::COND_AE:
12481 case X86::COND_B: case X86::COND_BE:
12484 case X86::COND_G: case X86::COND_GE:
12485 case X86::COND_L: case X86::COND_LE:
12486 case X86::COND_O: case X86::COND_NO: {
12487 // Check if we really need to set the
12488 // Overflow flag. If NoSignedWrap is present
12489 // that is not actually needed.
12490 switch (Op->getOpcode()) {
12495 const BinaryWithFlagsSDNode *BinNode =
12496 cast<BinaryWithFlagsSDNode>(Op.getNode());
12497 if (BinNode->hasNoSignedWrap())
12507 // See if we can use the EFLAGS value from the operand instead of
12508 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12509 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12510 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12511 // Emit a CMP with 0, which is the TEST pattern.
12512 //if (Op.getValueType() == MVT::i1)
12513 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12514 // DAG.getConstant(0, MVT::i1));
12515 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12516 DAG.getConstant(0, Op.getValueType()));
12518 unsigned Opcode = 0;
12519 unsigned NumOperands = 0;
12521 // Truncate operations may prevent the merge of the SETCC instruction
12522 // and the arithmetic instruction before it. Attempt to truncate the operands
12523 // of the arithmetic instruction and use a reduced bit-width instruction.
12524 bool NeedTruncation = false;
12525 SDValue ArithOp = Op;
12526 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12527 SDValue Arith = Op->getOperand(0);
12528 // Both the trunc and the arithmetic op need to have one user each.
12529 if (Arith->hasOneUse())
12530 switch (Arith.getOpcode()) {
12537 NeedTruncation = true;
12543 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12544 // which may be the result of a CAST. We use the variable 'Op', which is the
12545 // non-casted variable when we check for possible users.
12546 switch (ArithOp.getOpcode()) {
12548 // Due to an isel shortcoming, be conservative if this add is likely to be
12549 // selected as part of a load-modify-store instruction. When the root node
12550 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12551 // uses of other nodes in the match, such as the ADD in this case. This
12552 // leads to the ADD being left around and reselected, with the result being
12553 // two adds in the output. Alas, even if none our users are stores, that
12554 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12555 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12556 // climbing the DAG back to the root, and it doesn't seem to be worth the
12558 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12559 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12560 if (UI->getOpcode() != ISD::CopyToReg &&
12561 UI->getOpcode() != ISD::SETCC &&
12562 UI->getOpcode() != ISD::STORE)
12565 if (ConstantSDNode *C =
12566 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12567 // An add of one will be selected as an INC.
12568 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12569 Opcode = X86ISD::INC;
12574 // An add of negative one (subtract of one) will be selected as a DEC.
12575 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12576 Opcode = X86ISD::DEC;
12582 // Otherwise use a regular EFLAGS-setting add.
12583 Opcode = X86ISD::ADD;
12588 // If we have a constant logical shift that's only used in a comparison
12589 // against zero turn it into an equivalent AND. This allows turning it into
12590 // a TEST instruction later.
12591 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12592 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12593 EVT VT = Op.getValueType();
12594 unsigned BitWidth = VT.getSizeInBits();
12595 unsigned ShAmt = Op->getConstantOperandVal(1);
12596 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12598 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12599 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12600 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12601 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12603 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12604 DAG.getConstant(Mask, VT));
12605 DAG.ReplaceAllUsesWith(Op, New);
12611 // If the primary and result isn't used, don't bother using X86ISD::AND,
12612 // because a TEST instruction will be better.
12613 if (!hasNonFlagsUse(Op))
12619 // Due to the ISEL shortcoming noted above, be conservative if this op is
12620 // likely to be selected as part of a load-modify-store instruction.
12621 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12622 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12623 if (UI->getOpcode() == ISD::STORE)
12626 // Otherwise use a regular EFLAGS-setting instruction.
12627 switch (ArithOp.getOpcode()) {
12628 default: llvm_unreachable("unexpected operator!");
12629 case ISD::SUB: Opcode = X86ISD::SUB; break;
12630 case ISD::XOR: Opcode = X86ISD::XOR; break;
12631 case ISD::AND: Opcode = X86ISD::AND; break;
12633 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12634 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12635 if (EFLAGS.getNode())
12638 Opcode = X86ISD::OR;
12652 return SDValue(Op.getNode(), 1);
12658 // If we found that truncation is beneficial, perform the truncation and
12660 if (NeedTruncation) {
12661 EVT VT = Op.getValueType();
12662 SDValue WideVal = Op->getOperand(0);
12663 EVT WideVT = WideVal.getValueType();
12664 unsigned ConvertedOp = 0;
12665 // Use a target machine opcode to prevent further DAGCombine
12666 // optimizations that may separate the arithmetic operations
12667 // from the setcc node.
12668 switch (WideVal.getOpcode()) {
12670 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12671 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12672 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12673 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12674 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12678 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12679 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12680 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12681 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12682 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12688 // Emit a CMP with 0, which is the TEST pattern.
12689 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12690 DAG.getConstant(0, Op.getValueType()));
12692 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12693 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12695 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12696 DAG.ReplaceAllUsesWith(Op, New);
12697 return SDValue(New.getNode(), 1);
12700 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12702 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12703 SDLoc dl, SelectionDAG &DAG) const {
12704 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12705 if (C->getAPIntValue() == 0)
12706 return EmitTest(Op0, X86CC, dl, DAG);
12708 if (Op0.getValueType() == MVT::i1)
12709 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12712 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12713 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12714 // Do the comparison at i32 if it's smaller, besides the Atom case.
12715 // This avoids subregister aliasing issues. Keep the smaller reference
12716 // if we're optimizing for size, however, as that'll allow better folding
12717 // of memory operations.
12718 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12719 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12720 Attribute::MinSize) &&
12721 !Subtarget->isAtom()) {
12722 unsigned ExtendOp =
12723 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12724 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12725 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12727 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12728 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12729 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12731 return SDValue(Sub.getNode(), 1);
12733 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12736 /// Convert a comparison if required by the subtarget.
12737 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12738 SelectionDAG &DAG) const {
12739 // If the subtarget does not support the FUCOMI instruction, floating-point
12740 // comparisons have to be converted.
12741 if (Subtarget->hasCMov() ||
12742 Cmp.getOpcode() != X86ISD::CMP ||
12743 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12744 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12747 // The instruction selector will select an FUCOM instruction instead of
12748 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12749 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12750 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12752 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12753 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12754 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12755 DAG.getConstant(8, MVT::i8));
12756 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12757 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12760 /// The minimum architected relative accuracy is 2^-12. We need one
12761 /// Newton-Raphson step to have a good float result (24 bits of precision).
12762 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12763 DAGCombinerInfo &DCI,
12764 unsigned &RefinementSteps,
12765 bool &UseOneConstNR) const {
12766 // FIXME: We should use instruction latency models to calculate the cost of
12767 // each potential sequence, but this is very hard to do reliably because
12768 // at least Intel's Core* chips have variable timing based on the number of
12769 // significant digits in the divisor and/or sqrt operand.
12770 if (!Subtarget->useSqrtEst())
12773 EVT VT = Op.getValueType();
12775 // SSE1 has rsqrtss and rsqrtps.
12776 // TODO: Add support for AVX512 (v16f32).
12777 // It is likely not profitable to do this for f64 because a double-precision
12778 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12779 // instructions: convert to single, rsqrtss, convert back to double, refine
12780 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12781 // along with FMA, this could be a throughput win.
12782 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12783 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12784 RefinementSteps = 1;
12785 UseOneConstNR = false;
12786 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12791 /// The minimum architected relative accuracy is 2^-12. We need one
12792 /// Newton-Raphson step to have a good float result (24 bits of precision).
12793 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12794 DAGCombinerInfo &DCI,
12795 unsigned &RefinementSteps) const {
12796 // FIXME: We should use instruction latency models to calculate the cost of
12797 // each potential sequence, but this is very hard to do reliably because
12798 // at least Intel's Core* chips have variable timing based on the number of
12799 // significant digits in the divisor.
12800 if (!Subtarget->useReciprocalEst())
12803 EVT VT = Op.getValueType();
12805 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12806 // TODO: Add support for AVX512 (v16f32).
12807 // It is likely not profitable to do this for f64 because a double-precision
12808 // reciprocal estimate with refinement on x86 prior to FMA requires
12809 // 15 instructions: convert to single, rcpss, convert back to double, refine
12810 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12811 // along with FMA, this could be a throughput win.
12812 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12813 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12814 RefinementSteps = ReciprocalEstimateRefinementSteps;
12815 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12820 static bool isAllOnes(SDValue V) {
12821 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12822 return C && C->isAllOnesValue();
12825 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12826 /// if it's possible.
12827 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12828 SDLoc dl, SelectionDAG &DAG) const {
12829 SDValue Op0 = And.getOperand(0);
12830 SDValue Op1 = And.getOperand(1);
12831 if (Op0.getOpcode() == ISD::TRUNCATE)
12832 Op0 = Op0.getOperand(0);
12833 if (Op1.getOpcode() == ISD::TRUNCATE)
12834 Op1 = Op1.getOperand(0);
12837 if (Op1.getOpcode() == ISD::SHL)
12838 std::swap(Op0, Op1);
12839 if (Op0.getOpcode() == ISD::SHL) {
12840 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12841 if (And00C->getZExtValue() == 1) {
12842 // If we looked past a truncate, check that it's only truncating away
12844 unsigned BitWidth = Op0.getValueSizeInBits();
12845 unsigned AndBitWidth = And.getValueSizeInBits();
12846 if (BitWidth > AndBitWidth) {
12848 DAG.computeKnownBits(Op0, Zeros, Ones);
12849 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12853 RHS = Op0.getOperand(1);
12855 } else if (Op1.getOpcode() == ISD::Constant) {
12856 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12857 uint64_t AndRHSVal = AndRHS->getZExtValue();
12858 SDValue AndLHS = Op0;
12860 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12861 LHS = AndLHS.getOperand(0);
12862 RHS = AndLHS.getOperand(1);
12865 // Use BT if the immediate can't be encoded in a TEST instruction.
12866 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12868 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12872 if (LHS.getNode()) {
12873 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12874 // instruction. Since the shift amount is in-range-or-undefined, we know
12875 // that doing a bittest on the i32 value is ok. We extend to i32 because
12876 // the encoding for the i16 version is larger than the i32 version.
12877 // Also promote i16 to i32 for performance / code size reason.
12878 if (LHS.getValueType() == MVT::i8 ||
12879 LHS.getValueType() == MVT::i16)
12880 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12882 // If the operand types disagree, extend the shift amount to match. Since
12883 // BT ignores high bits (like shifts) we can use anyextend.
12884 if (LHS.getValueType() != RHS.getValueType())
12885 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12887 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12888 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12889 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12890 DAG.getConstant(Cond, MVT::i8), BT);
12896 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12898 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12903 // SSE Condition code mapping:
12912 switch (SetCCOpcode) {
12913 default: llvm_unreachable("Unexpected SETCC condition");
12915 case ISD::SETEQ: SSECC = 0; break;
12917 case ISD::SETGT: Swap = true; // Fallthrough
12919 case ISD::SETOLT: SSECC = 1; break;
12921 case ISD::SETGE: Swap = true; // Fallthrough
12923 case ISD::SETOLE: SSECC = 2; break;
12924 case ISD::SETUO: SSECC = 3; break;
12926 case ISD::SETNE: SSECC = 4; break;
12927 case ISD::SETULE: Swap = true; // Fallthrough
12928 case ISD::SETUGE: SSECC = 5; break;
12929 case ISD::SETULT: Swap = true; // Fallthrough
12930 case ISD::SETUGT: SSECC = 6; break;
12931 case ISD::SETO: SSECC = 7; break;
12933 case ISD::SETONE: SSECC = 8; break;
12936 std::swap(Op0, Op1);
12941 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12942 // ones, and then concatenate the result back.
12943 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12944 MVT VT = Op.getSimpleValueType();
12946 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12947 "Unsupported value type for operation");
12949 unsigned NumElems = VT.getVectorNumElements();
12951 SDValue CC = Op.getOperand(2);
12953 // Extract the LHS vectors
12954 SDValue LHS = Op.getOperand(0);
12955 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12956 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12958 // Extract the RHS vectors
12959 SDValue RHS = Op.getOperand(1);
12960 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12961 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12963 // Issue the operation on the smaller types and concatenate the result back
12964 MVT EltVT = VT.getVectorElementType();
12965 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12966 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12967 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12968 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12971 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12972 const X86Subtarget *Subtarget) {
12973 SDValue Op0 = Op.getOperand(0);
12974 SDValue Op1 = Op.getOperand(1);
12975 SDValue CC = Op.getOperand(2);
12976 MVT VT = Op.getSimpleValueType();
12979 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
12980 Op.getValueType().getScalarType() == MVT::i1 &&
12981 "Cannot set masked compare for this operation");
12983 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12985 bool Unsigned = false;
12988 switch (SetCCOpcode) {
12989 default: llvm_unreachable("Unexpected SETCC condition");
12990 case ISD::SETNE: SSECC = 4; break;
12991 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12992 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12993 case ISD::SETLT: Swap = true; //fall-through
12994 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12995 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12996 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12997 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12998 case ISD::SETULE: Unsigned = true; //fall-through
12999 case ISD::SETLE: SSECC = 2; break;
13003 std::swap(Op0, Op1);
13005 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13006 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13007 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13008 DAG.getConstant(SSECC, MVT::i8));
13011 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13012 /// operand \p Op1. If non-trivial (for example because it's not constant)
13013 /// return an empty value.
13014 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13016 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13020 MVT VT = Op1.getSimpleValueType();
13021 MVT EVT = VT.getVectorElementType();
13022 unsigned n = VT.getVectorNumElements();
13023 SmallVector<SDValue, 8> ULTOp1;
13025 for (unsigned i = 0; i < n; ++i) {
13026 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13027 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13030 // Avoid underflow.
13031 APInt Val = Elt->getAPIntValue();
13035 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13038 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13041 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13042 SelectionDAG &DAG) {
13043 SDValue Op0 = Op.getOperand(0);
13044 SDValue Op1 = Op.getOperand(1);
13045 SDValue CC = Op.getOperand(2);
13046 MVT VT = Op.getSimpleValueType();
13047 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13048 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13053 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13054 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13057 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13058 unsigned Opc = X86ISD::CMPP;
13059 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13060 assert(VT.getVectorNumElements() <= 16);
13061 Opc = X86ISD::CMPM;
13063 // In the two special cases we can't handle, emit two comparisons.
13066 unsigned CombineOpc;
13067 if (SetCCOpcode == ISD::SETUEQ) {
13068 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13070 assert(SetCCOpcode == ISD::SETONE);
13071 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13074 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13075 DAG.getConstant(CC0, MVT::i8));
13076 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13077 DAG.getConstant(CC1, MVT::i8));
13078 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13080 // Handle all other FP comparisons here.
13081 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13082 DAG.getConstant(SSECC, MVT::i8));
13085 // Break 256-bit integer vector compare into smaller ones.
13086 if (VT.is256BitVector() && !Subtarget->hasInt256())
13087 return Lower256IntVSETCC(Op, DAG);
13089 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13090 EVT OpVT = Op1.getValueType();
13091 if (Subtarget->hasAVX512()) {
13092 if (Op1.getValueType().is512BitVector() ||
13093 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13094 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13095 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13097 // In AVX-512 architecture setcc returns mask with i1 elements,
13098 // But there is no compare instruction for i8 and i16 elements in KNL.
13099 // We are not talking about 512-bit operands in this case, these
13100 // types are illegal.
13102 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13103 OpVT.getVectorElementType().getSizeInBits() >= 8))
13104 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13105 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13108 // We are handling one of the integer comparisons here. Since SSE only has
13109 // GT and EQ comparisons for integer, swapping operands and multiple
13110 // operations may be required for some comparisons.
13112 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13113 bool Subus = false;
13115 switch (SetCCOpcode) {
13116 default: llvm_unreachable("Unexpected SETCC condition");
13117 case ISD::SETNE: Invert = true;
13118 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13119 case ISD::SETLT: Swap = true;
13120 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13121 case ISD::SETGE: Swap = true;
13122 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13123 Invert = true; break;
13124 case ISD::SETULT: Swap = true;
13125 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13126 FlipSigns = true; break;
13127 case ISD::SETUGE: Swap = true;
13128 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13129 FlipSigns = true; Invert = true; break;
13132 // Special case: Use min/max operations for SETULE/SETUGE
13133 MVT VET = VT.getVectorElementType();
13135 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13136 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13139 switch (SetCCOpcode) {
13141 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13142 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13145 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13148 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13149 if (!MinMax && hasSubus) {
13150 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13152 // t = psubus Op0, Op1
13153 // pcmpeq t, <0..0>
13154 switch (SetCCOpcode) {
13156 case ISD::SETULT: {
13157 // If the comparison is against a constant we can turn this into a
13158 // setule. With psubus, setule does not require a swap. This is
13159 // beneficial because the constant in the register is no longer
13160 // destructed as the destination so it can be hoisted out of a loop.
13161 // Only do this pre-AVX since vpcmp* is no longer destructive.
13162 if (Subtarget->hasAVX())
13164 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13165 if (ULEOp1.getNode()) {
13167 Subus = true; Invert = false; Swap = false;
13171 // Psubus is better than flip-sign because it requires no inversion.
13172 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13173 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13177 Opc = X86ISD::SUBUS;
13183 std::swap(Op0, Op1);
13185 // Check that the operation in question is available (most are plain SSE2,
13186 // but PCMPGTQ and PCMPEQQ have different requirements).
13187 if (VT == MVT::v2i64) {
13188 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13189 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13191 // First cast everything to the right type.
13192 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13193 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13195 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13196 // bits of the inputs before performing those operations. The lower
13197 // compare is always unsigned.
13200 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13202 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13203 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13204 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13205 Sign, Zero, Sign, Zero);
13207 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13208 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13210 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13211 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13212 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13214 // Create masks for only the low parts/high parts of the 64 bit integers.
13215 static const int MaskHi[] = { 1, 1, 3, 3 };
13216 static const int MaskLo[] = { 0, 0, 2, 2 };
13217 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13218 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13219 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13221 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13222 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13225 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13227 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13230 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13231 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13232 // pcmpeqd + pshufd + pand.
13233 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13235 // First cast everything to the right type.
13236 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13237 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13240 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13242 // Make sure the lower and upper halves are both all-ones.
13243 static const int Mask[] = { 1, 0, 3, 2 };
13244 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13245 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13248 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13250 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13254 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13255 // bits of the inputs before performing those operations.
13257 EVT EltVT = VT.getVectorElementType();
13258 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13259 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13260 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13263 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13265 // If the logical-not of the result is required, perform that now.
13267 Result = DAG.getNOT(dl, Result, VT);
13270 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13273 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13274 getZeroVector(VT, Subtarget, DAG, dl));
13279 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13281 MVT VT = Op.getSimpleValueType();
13283 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13285 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13286 && "SetCC type must be 8-bit or 1-bit integer");
13287 SDValue Op0 = Op.getOperand(0);
13288 SDValue Op1 = Op.getOperand(1);
13290 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13292 // Optimize to BT if possible.
13293 // Lower (X & (1 << N)) == 0 to BT(X, N).
13294 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13295 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13296 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13297 Op1.getOpcode() == ISD::Constant &&
13298 cast<ConstantSDNode>(Op1)->isNullValue() &&
13299 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13300 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13301 if (NewSetCC.getNode()) {
13303 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13308 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13310 if (Op1.getOpcode() == ISD::Constant &&
13311 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13312 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13313 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13315 // If the input is a setcc, then reuse the input setcc or use a new one with
13316 // the inverted condition.
13317 if (Op0.getOpcode() == X86ISD::SETCC) {
13318 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13319 bool Invert = (CC == ISD::SETNE) ^
13320 cast<ConstantSDNode>(Op1)->isNullValue();
13324 CCode = X86::GetOppositeBranchCondition(CCode);
13325 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13326 DAG.getConstant(CCode, MVT::i8),
13327 Op0.getOperand(1));
13329 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13333 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13334 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13335 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13337 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13338 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13341 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13342 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13343 if (X86CC == X86::COND_INVALID)
13346 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13347 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13348 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13349 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13351 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13355 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13356 static bool isX86LogicalCmp(SDValue Op) {
13357 unsigned Opc = Op.getNode()->getOpcode();
13358 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13359 Opc == X86ISD::SAHF)
13361 if (Op.getResNo() == 1 &&
13362 (Opc == X86ISD::ADD ||
13363 Opc == X86ISD::SUB ||
13364 Opc == X86ISD::ADC ||
13365 Opc == X86ISD::SBB ||
13366 Opc == X86ISD::SMUL ||
13367 Opc == X86ISD::UMUL ||
13368 Opc == X86ISD::INC ||
13369 Opc == X86ISD::DEC ||
13370 Opc == X86ISD::OR ||
13371 Opc == X86ISD::XOR ||
13372 Opc == X86ISD::AND))
13375 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13381 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13382 if (V.getOpcode() != ISD::TRUNCATE)
13385 SDValue VOp0 = V.getOperand(0);
13386 unsigned InBits = VOp0.getValueSizeInBits();
13387 unsigned Bits = V.getValueSizeInBits();
13388 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13391 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13392 bool addTest = true;
13393 SDValue Cond = Op.getOperand(0);
13394 SDValue Op1 = Op.getOperand(1);
13395 SDValue Op2 = Op.getOperand(2);
13397 EVT VT = Op1.getValueType();
13400 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13401 // are available or VBLENDV if AVX is available.
13402 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13403 if (Cond.getOpcode() == ISD::SETCC &&
13404 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13405 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13406 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13407 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13408 int SSECC = translateX86FSETCC(
13409 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13412 if (Subtarget->hasAVX512()) {
13413 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13414 DAG.getConstant(SSECC, MVT::i8));
13415 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13418 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13419 DAG.getConstant(SSECC, MVT::i8));
13421 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13422 // of 3 logic instructions for size savings and potentially speed.
13423 // Unfortunately, there is no scalar form of VBLENDV.
13425 // If either operand is a constant, don't try this. We can expect to
13426 // optimize away at least one of the logic instructions later in that
13427 // case, so that sequence would be faster than a variable blend.
13429 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13430 // uses XMM0 as the selection register. That may need just as many
13431 // instructions as the AND/ANDN/OR sequence due to register moves, so
13434 if (Subtarget->hasAVX() &&
13435 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13437 // Convert to vectors, do a VSELECT, and convert back to scalar.
13438 // All of the conversions should be optimized away.
13440 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13441 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13442 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13443 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13445 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13446 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13448 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13450 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13451 VSel, DAG.getIntPtrConstant(0));
13453 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13454 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13455 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13459 if (Cond.getOpcode() == ISD::SETCC) {
13460 SDValue NewCond = LowerSETCC(Cond, DAG);
13461 if (NewCond.getNode())
13465 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13466 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13467 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13468 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13469 if (Cond.getOpcode() == X86ISD::SETCC &&
13470 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13471 isZero(Cond.getOperand(1).getOperand(1))) {
13472 SDValue Cmp = Cond.getOperand(1);
13474 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13476 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13477 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13478 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13480 SDValue CmpOp0 = Cmp.getOperand(0);
13481 // Apply further optimizations for special cases
13482 // (select (x != 0), -1, 0) -> neg & sbb
13483 // (select (x == 0), 0, -1) -> neg & sbb
13484 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13485 if (YC->isNullValue() &&
13486 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13487 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13488 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13489 DAG.getConstant(0, CmpOp0.getValueType()),
13491 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13492 DAG.getConstant(X86::COND_B, MVT::i8),
13493 SDValue(Neg.getNode(), 1));
13497 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13498 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13499 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13501 SDValue Res = // Res = 0 or -1.
13502 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13503 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13505 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13506 Res = DAG.getNOT(DL, Res, Res.getValueType());
13508 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13509 if (!N2C || !N2C->isNullValue())
13510 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13515 // Look past (and (setcc_carry (cmp ...)), 1).
13516 if (Cond.getOpcode() == ISD::AND &&
13517 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13518 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13519 if (C && C->getAPIntValue() == 1)
13520 Cond = Cond.getOperand(0);
13523 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13524 // setting operand in place of the X86ISD::SETCC.
13525 unsigned CondOpcode = Cond.getOpcode();
13526 if (CondOpcode == X86ISD::SETCC ||
13527 CondOpcode == X86ISD::SETCC_CARRY) {
13528 CC = Cond.getOperand(0);
13530 SDValue Cmp = Cond.getOperand(1);
13531 unsigned Opc = Cmp.getOpcode();
13532 MVT VT = Op.getSimpleValueType();
13534 bool IllegalFPCMov = false;
13535 if (VT.isFloatingPoint() && !VT.isVector() &&
13536 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13537 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13539 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13540 Opc == X86ISD::BT) { // FIXME
13544 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13545 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13546 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13547 Cond.getOperand(0).getValueType() != MVT::i8)) {
13548 SDValue LHS = Cond.getOperand(0);
13549 SDValue RHS = Cond.getOperand(1);
13550 unsigned X86Opcode;
13553 switch (CondOpcode) {
13554 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13555 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13556 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13557 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13558 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13559 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13560 default: llvm_unreachable("unexpected overflowing operator");
13562 if (CondOpcode == ISD::UMULO)
13563 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13566 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13568 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13570 if (CondOpcode == ISD::UMULO)
13571 Cond = X86Op.getValue(2);
13573 Cond = X86Op.getValue(1);
13575 CC = DAG.getConstant(X86Cond, MVT::i8);
13580 // Look pass the truncate if the high bits are known zero.
13581 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13582 Cond = Cond.getOperand(0);
13584 // We know the result of AND is compared against zero. Try to match
13586 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13587 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13588 if (NewSetCC.getNode()) {
13589 CC = NewSetCC.getOperand(0);
13590 Cond = NewSetCC.getOperand(1);
13597 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13598 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13601 // a < b ? -1 : 0 -> RES = ~setcc_carry
13602 // a < b ? 0 : -1 -> RES = setcc_carry
13603 // a >= b ? -1 : 0 -> RES = setcc_carry
13604 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13605 if (Cond.getOpcode() == X86ISD::SUB) {
13606 Cond = ConvertCmpIfNecessary(Cond, DAG);
13607 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13609 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13610 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13611 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13612 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13613 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13614 return DAG.getNOT(DL, Res, Res.getValueType());
13619 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13620 // widen the cmov and push the truncate through. This avoids introducing a new
13621 // branch during isel and doesn't add any extensions.
13622 if (Op.getValueType() == MVT::i8 &&
13623 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13624 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13625 if (T1.getValueType() == T2.getValueType() &&
13626 // Blacklist CopyFromReg to avoid partial register stalls.
13627 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13628 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13629 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13630 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13634 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13635 // condition is true.
13636 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13637 SDValue Ops[] = { Op2, Op1, CC, Cond };
13638 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13641 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13642 SelectionDAG &DAG) {
13643 MVT VT = Op->getSimpleValueType(0);
13644 SDValue In = Op->getOperand(0);
13645 MVT InVT = In.getSimpleValueType();
13646 MVT VTElt = VT.getVectorElementType();
13647 MVT InVTElt = InVT.getVectorElementType();
13651 if ((InVTElt == MVT::i1) &&
13652 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13653 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13655 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13656 VTElt.getSizeInBits() <= 16)) ||
13658 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13659 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13661 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13662 VTElt.getSizeInBits() >= 32))))
13663 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13665 unsigned int NumElts = VT.getVectorNumElements();
13667 if (NumElts != 8 && NumElts != 16)
13670 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13671 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13672 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13673 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13676 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13677 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13679 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13680 Constant *C = ConstantInt::get(*DAG.getContext(),
13681 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13683 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13684 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13685 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13686 MachinePointerInfo::getConstantPool(),
13687 false, false, false, Alignment);
13688 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13689 if (VT.is512BitVector())
13691 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13694 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13695 SelectionDAG &DAG) {
13696 MVT VT = Op->getSimpleValueType(0);
13697 SDValue In = Op->getOperand(0);
13698 MVT InVT = In.getSimpleValueType();
13701 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13702 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13704 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13705 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13706 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13709 if (Subtarget->hasInt256())
13710 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13712 // Optimize vectors in AVX mode
13713 // Sign extend v8i16 to v8i32 and
13716 // Divide input vector into two parts
13717 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13718 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13719 // concat the vectors to original VT
13721 unsigned NumElems = InVT.getVectorNumElements();
13722 SDValue Undef = DAG.getUNDEF(InVT);
13724 SmallVector<int,8> ShufMask1(NumElems, -1);
13725 for (unsigned i = 0; i != NumElems/2; ++i)
13728 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13730 SmallVector<int,8> ShufMask2(NumElems, -1);
13731 for (unsigned i = 0; i != NumElems/2; ++i)
13732 ShufMask2[i] = i + NumElems/2;
13734 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13736 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13737 VT.getVectorNumElements()/2);
13739 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13740 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13742 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13745 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13746 // may emit an illegal shuffle but the expansion is still better than scalar
13747 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13748 // we'll emit a shuffle and a arithmetic shift.
13749 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13750 // TODO: It is possible to support ZExt by zeroing the undef values during
13751 // the shuffle phase or after the shuffle.
13752 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13753 SelectionDAG &DAG) {
13754 MVT RegVT = Op.getSimpleValueType();
13755 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13756 assert(RegVT.isInteger() &&
13757 "We only custom lower integer vector sext loads.");
13759 // Nothing useful we can do without SSE2 shuffles.
13760 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13762 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13764 EVT MemVT = Ld->getMemoryVT();
13765 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13766 unsigned RegSz = RegVT.getSizeInBits();
13768 ISD::LoadExtType Ext = Ld->getExtensionType();
13770 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13771 && "Only anyext and sext are currently implemented.");
13772 assert(MemVT != RegVT && "Cannot extend to the same type");
13773 assert(MemVT.isVector() && "Must load a vector from memory");
13775 unsigned NumElems = RegVT.getVectorNumElements();
13776 unsigned MemSz = MemVT.getSizeInBits();
13777 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13779 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13780 // The only way in which we have a legal 256-bit vector result but not the
13781 // integer 256-bit operations needed to directly lower a sextload is if we
13782 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13783 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13784 // correctly legalized. We do this late to allow the canonical form of
13785 // sextload to persist throughout the rest of the DAG combiner -- it wants
13786 // to fold together any extensions it can, and so will fuse a sign_extend
13787 // of an sextload into a sextload targeting a wider value.
13789 if (MemSz == 128) {
13790 // Just switch this to a normal load.
13791 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13792 "it must be a legal 128-bit vector "
13794 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13795 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13796 Ld->isInvariant(), Ld->getAlignment());
13798 assert(MemSz < 128 &&
13799 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13800 // Do an sext load to a 128-bit vector type. We want to use the same
13801 // number of elements, but elements half as wide. This will end up being
13802 // recursively lowered by this routine, but will succeed as we definitely
13803 // have all the necessary features if we're using AVX1.
13805 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13806 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13808 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13809 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13810 Ld->isNonTemporal(), Ld->isInvariant(),
13811 Ld->getAlignment());
13814 // Replace chain users with the new chain.
13815 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13816 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13818 // Finally, do a normal sign-extend to the desired register.
13819 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13822 // All sizes must be a power of two.
13823 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13824 "Non-power-of-two elements are not custom lowered!");
13826 // Attempt to load the original value using scalar loads.
13827 // Find the largest scalar type that divides the total loaded size.
13828 MVT SclrLoadTy = MVT::i8;
13829 for (MVT Tp : MVT::integer_valuetypes()) {
13830 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13835 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13836 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13838 SclrLoadTy = MVT::f64;
13840 // Calculate the number of scalar loads that we need to perform
13841 // in order to load our vector from memory.
13842 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13844 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13845 "Can only lower sext loads with a single scalar load!");
13847 unsigned loadRegZize = RegSz;
13848 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13851 // Represent our vector as a sequence of elements which are the
13852 // largest scalar that we can load.
13853 EVT LoadUnitVecVT = EVT::getVectorVT(
13854 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13856 // Represent the data using the same element type that is stored in
13857 // memory. In practice, we ''widen'' MemVT.
13859 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13860 loadRegZize / MemVT.getScalarType().getSizeInBits());
13862 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13863 "Invalid vector type");
13865 // We can't shuffle using an illegal type.
13866 assert(TLI.isTypeLegal(WideVecVT) &&
13867 "We only lower types that form legal widened vector types");
13869 SmallVector<SDValue, 8> Chains;
13870 SDValue Ptr = Ld->getBasePtr();
13871 SDValue Increment =
13872 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13873 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13875 for (unsigned i = 0; i < NumLoads; ++i) {
13876 // Perform a single load.
13877 SDValue ScalarLoad =
13878 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13879 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13880 Ld->getAlignment());
13881 Chains.push_back(ScalarLoad.getValue(1));
13882 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13883 // another round of DAGCombining.
13885 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13887 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13888 ScalarLoad, DAG.getIntPtrConstant(i));
13890 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13893 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13895 // Bitcast the loaded value to a vector of the original element type, in
13896 // the size of the target vector type.
13897 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13898 unsigned SizeRatio = RegSz / MemSz;
13900 if (Ext == ISD::SEXTLOAD) {
13901 // If we have SSE4.1, we can directly emit a VSEXT node.
13902 if (Subtarget->hasSSE41()) {
13903 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13904 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13908 // Otherwise we'll shuffle the small elements in the high bits of the
13909 // larger type and perform an arithmetic shift. If the shift is not legal
13910 // it's better to scalarize.
13911 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13912 "We can't implement a sext load without an arithmetic right shift!");
13914 // Redistribute the loaded elements into the different locations.
13915 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13916 for (unsigned i = 0; i != NumElems; ++i)
13917 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13919 SDValue Shuff = DAG.getVectorShuffle(
13920 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13922 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13924 // Build the arithmetic shift.
13925 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13926 MemVT.getVectorElementType().getSizeInBits();
13928 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13930 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13934 // Redistribute the loaded elements into the different locations.
13935 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13936 for (unsigned i = 0; i != NumElems; ++i)
13937 ShuffleVec[i * SizeRatio] = i;
13939 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13940 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13942 // Bitcast to the requested type.
13943 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13944 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13948 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13949 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13950 // from the AND / OR.
13951 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13952 Opc = Op.getOpcode();
13953 if (Opc != ISD::OR && Opc != ISD::AND)
13955 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13956 Op.getOperand(0).hasOneUse() &&
13957 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13958 Op.getOperand(1).hasOneUse());
13961 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13962 // 1 and that the SETCC node has a single use.
13963 static bool isXor1OfSetCC(SDValue Op) {
13964 if (Op.getOpcode() != ISD::XOR)
13966 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13967 if (N1C && N1C->getAPIntValue() == 1) {
13968 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13969 Op.getOperand(0).hasOneUse();
13974 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13975 bool addTest = true;
13976 SDValue Chain = Op.getOperand(0);
13977 SDValue Cond = Op.getOperand(1);
13978 SDValue Dest = Op.getOperand(2);
13981 bool Inverted = false;
13983 if (Cond.getOpcode() == ISD::SETCC) {
13984 // Check for setcc([su]{add,sub,mul}o == 0).
13985 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13986 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13987 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13988 Cond.getOperand(0).getResNo() == 1 &&
13989 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13990 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13991 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13992 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13993 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13994 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13996 Cond = Cond.getOperand(0);
13998 SDValue NewCond = LowerSETCC(Cond, DAG);
13999 if (NewCond.getNode())
14004 // FIXME: LowerXALUO doesn't handle these!!
14005 else if (Cond.getOpcode() == X86ISD::ADD ||
14006 Cond.getOpcode() == X86ISD::SUB ||
14007 Cond.getOpcode() == X86ISD::SMUL ||
14008 Cond.getOpcode() == X86ISD::UMUL)
14009 Cond = LowerXALUO(Cond, DAG);
14012 // Look pass (and (setcc_carry (cmp ...)), 1).
14013 if (Cond.getOpcode() == ISD::AND &&
14014 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14015 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14016 if (C && C->getAPIntValue() == 1)
14017 Cond = Cond.getOperand(0);
14020 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14021 // setting operand in place of the X86ISD::SETCC.
14022 unsigned CondOpcode = Cond.getOpcode();
14023 if (CondOpcode == X86ISD::SETCC ||
14024 CondOpcode == X86ISD::SETCC_CARRY) {
14025 CC = Cond.getOperand(0);
14027 SDValue Cmp = Cond.getOperand(1);
14028 unsigned Opc = Cmp.getOpcode();
14029 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14030 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14034 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14038 // These can only come from an arithmetic instruction with overflow,
14039 // e.g. SADDO, UADDO.
14040 Cond = Cond.getNode()->getOperand(1);
14046 CondOpcode = Cond.getOpcode();
14047 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14048 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14049 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14050 Cond.getOperand(0).getValueType() != MVT::i8)) {
14051 SDValue LHS = Cond.getOperand(0);
14052 SDValue RHS = Cond.getOperand(1);
14053 unsigned X86Opcode;
14056 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14057 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14059 switch (CondOpcode) {
14060 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14062 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14064 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14067 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14068 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14072 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14075 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14076 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14077 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14078 default: llvm_unreachable("unexpected overflowing operator");
14081 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14082 if (CondOpcode == ISD::UMULO)
14083 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14086 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14088 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14090 if (CondOpcode == ISD::UMULO)
14091 Cond = X86Op.getValue(2);
14093 Cond = X86Op.getValue(1);
14095 CC = DAG.getConstant(X86Cond, MVT::i8);
14099 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14100 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14101 if (CondOpc == ISD::OR) {
14102 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14103 // two branches instead of an explicit OR instruction with a
14105 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14106 isX86LogicalCmp(Cmp)) {
14107 CC = Cond.getOperand(0).getOperand(0);
14108 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14109 Chain, Dest, CC, Cmp);
14110 CC = Cond.getOperand(1).getOperand(0);
14114 } else { // ISD::AND
14115 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14116 // two branches instead of an explicit AND instruction with a
14117 // separate test. However, we only do this if this block doesn't
14118 // have a fall-through edge, because this requires an explicit
14119 // jmp when the condition is false.
14120 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14121 isX86LogicalCmp(Cmp) &&
14122 Op.getNode()->hasOneUse()) {
14123 X86::CondCode CCode =
14124 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14125 CCode = X86::GetOppositeBranchCondition(CCode);
14126 CC = DAG.getConstant(CCode, MVT::i8);
14127 SDNode *User = *Op.getNode()->use_begin();
14128 // Look for an unconditional branch following this conditional branch.
14129 // We need this because we need to reverse the successors in order
14130 // to implement FCMP_OEQ.
14131 if (User->getOpcode() == ISD::BR) {
14132 SDValue FalseBB = User->getOperand(1);
14134 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14135 assert(NewBR == User);
14139 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14140 Chain, Dest, CC, Cmp);
14141 X86::CondCode CCode =
14142 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14143 CCode = X86::GetOppositeBranchCondition(CCode);
14144 CC = DAG.getConstant(CCode, MVT::i8);
14150 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14151 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14152 // It should be transformed during dag combiner except when the condition
14153 // is set by a arithmetics with overflow node.
14154 X86::CondCode CCode =
14155 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14156 CCode = X86::GetOppositeBranchCondition(CCode);
14157 CC = DAG.getConstant(CCode, MVT::i8);
14158 Cond = Cond.getOperand(0).getOperand(1);
14160 } else if (Cond.getOpcode() == ISD::SETCC &&
14161 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14162 // For FCMP_OEQ, we can emit
14163 // two branches instead of an explicit AND instruction with a
14164 // separate test. However, we only do this if this block doesn't
14165 // have a fall-through edge, because this requires an explicit
14166 // jmp when the condition is false.
14167 if (Op.getNode()->hasOneUse()) {
14168 SDNode *User = *Op.getNode()->use_begin();
14169 // Look for an unconditional branch following this conditional branch.
14170 // We need this because we need to reverse the successors in order
14171 // to implement FCMP_OEQ.
14172 if (User->getOpcode() == ISD::BR) {
14173 SDValue FalseBB = User->getOperand(1);
14175 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14176 assert(NewBR == User);
14180 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14181 Cond.getOperand(0), Cond.getOperand(1));
14182 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14183 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14184 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14185 Chain, Dest, CC, Cmp);
14186 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14191 } else if (Cond.getOpcode() == ISD::SETCC &&
14192 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14193 // For FCMP_UNE, we can emit
14194 // two branches instead of an explicit AND instruction with a
14195 // separate test. However, we only do this if this block doesn't
14196 // have a fall-through edge, because this requires an explicit
14197 // jmp when the condition is false.
14198 if (Op.getNode()->hasOneUse()) {
14199 SDNode *User = *Op.getNode()->use_begin();
14200 // Look for an unconditional branch following this conditional branch.
14201 // We need this because we need to reverse the successors in order
14202 // to implement FCMP_UNE.
14203 if (User->getOpcode() == ISD::BR) {
14204 SDValue FalseBB = User->getOperand(1);
14206 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14207 assert(NewBR == User);
14210 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14211 Cond.getOperand(0), Cond.getOperand(1));
14212 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14213 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14214 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14215 Chain, Dest, CC, Cmp);
14216 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14226 // Look pass the truncate if the high bits are known zero.
14227 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14228 Cond = Cond.getOperand(0);
14230 // We know the result of AND is compared against zero. Try to match
14232 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14233 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14234 if (NewSetCC.getNode()) {
14235 CC = NewSetCC.getOperand(0);
14236 Cond = NewSetCC.getOperand(1);
14243 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14244 CC = DAG.getConstant(X86Cond, MVT::i8);
14245 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14247 Cond = ConvertCmpIfNecessary(Cond, DAG);
14248 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14249 Chain, Dest, CC, Cond);
14252 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14253 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14254 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14255 // that the guard pages used by the OS virtual memory manager are allocated in
14256 // correct sequence.
14258 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14259 SelectionDAG &DAG) const {
14260 MachineFunction &MF = DAG.getMachineFunction();
14261 bool SplitStack = MF.shouldSplitStack();
14262 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14268 SDNode* Node = Op.getNode();
14270 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14271 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14272 " not tell us which reg is the stack pointer!");
14273 EVT VT = Node->getValueType(0);
14274 SDValue Tmp1 = SDValue(Node, 0);
14275 SDValue Tmp2 = SDValue(Node, 1);
14276 SDValue Tmp3 = Node->getOperand(2);
14277 SDValue Chain = Tmp1.getOperand(0);
14279 // Chain the dynamic stack allocation so that it doesn't modify the stack
14280 // pointer when other instructions are using the stack.
14281 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14284 SDValue Size = Tmp2.getOperand(1);
14285 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14286 Chain = SP.getValue(1);
14287 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14288 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14289 unsigned StackAlign = TFI.getStackAlignment();
14290 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14291 if (Align > StackAlign)
14292 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14293 DAG.getConstant(-(uint64_t)Align, VT));
14294 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14296 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14297 DAG.getIntPtrConstant(0, true), SDValue(),
14300 SDValue Ops[2] = { Tmp1, Tmp2 };
14301 return DAG.getMergeValues(Ops, dl);
14305 SDValue Chain = Op.getOperand(0);
14306 SDValue Size = Op.getOperand(1);
14307 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14308 EVT VT = Op.getNode()->getValueType(0);
14310 bool Is64Bit = Subtarget->is64Bit();
14311 EVT SPTy = getPointerTy();
14314 MachineRegisterInfo &MRI = MF.getRegInfo();
14317 // The 64 bit implementation of segmented stacks needs to clobber both r10
14318 // r11. This makes it impossible to use it along with nested parameters.
14319 const Function *F = MF.getFunction();
14321 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14323 if (I->hasNestAttr())
14324 report_fatal_error("Cannot use segmented stacks with functions that "
14325 "have nested arguments.");
14328 const TargetRegisterClass *AddrRegClass =
14329 getRegClassFor(getPointerTy());
14330 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14331 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14332 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14333 DAG.getRegister(Vreg, SPTy));
14334 SDValue Ops1[2] = { Value, Chain };
14335 return DAG.getMergeValues(Ops1, dl);
14338 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14340 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14341 Flag = Chain.getValue(1);
14342 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14344 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14346 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14347 unsigned SPReg = RegInfo->getStackRegister();
14348 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14349 Chain = SP.getValue(1);
14352 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14353 DAG.getConstant(-(uint64_t)Align, VT));
14354 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14357 SDValue Ops1[2] = { SP, Chain };
14358 return DAG.getMergeValues(Ops1, dl);
14362 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14363 MachineFunction &MF = DAG.getMachineFunction();
14364 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14366 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14369 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14370 // vastart just stores the address of the VarArgsFrameIndex slot into the
14371 // memory location argument.
14372 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14374 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14375 MachinePointerInfo(SV), false, false, 0);
14379 // gp_offset (0 - 6 * 8)
14380 // fp_offset (48 - 48 + 8 * 16)
14381 // overflow_arg_area (point to parameters coming in memory).
14383 SmallVector<SDValue, 8> MemOps;
14384 SDValue FIN = Op.getOperand(1);
14386 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14387 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14389 FIN, MachinePointerInfo(SV), false, false, 0);
14390 MemOps.push_back(Store);
14393 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14394 FIN, DAG.getIntPtrConstant(4));
14395 Store = DAG.getStore(Op.getOperand(0), DL,
14396 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14398 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14399 MemOps.push_back(Store);
14401 // Store ptr to overflow_arg_area
14402 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14403 FIN, DAG.getIntPtrConstant(4));
14404 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14406 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14407 MachinePointerInfo(SV, 8),
14409 MemOps.push_back(Store);
14411 // Store ptr to reg_save_area.
14412 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14413 FIN, DAG.getIntPtrConstant(8));
14414 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14416 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14417 MachinePointerInfo(SV, 16), false, false, 0);
14418 MemOps.push_back(Store);
14419 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14422 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14423 assert(Subtarget->is64Bit() &&
14424 "LowerVAARG only handles 64-bit va_arg!");
14425 assert((Subtarget->isTargetLinux() ||
14426 Subtarget->isTargetDarwin()) &&
14427 "Unhandled target in LowerVAARG");
14428 assert(Op.getNode()->getNumOperands() == 4);
14429 SDValue Chain = Op.getOperand(0);
14430 SDValue SrcPtr = Op.getOperand(1);
14431 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14432 unsigned Align = Op.getConstantOperandVal(3);
14435 EVT ArgVT = Op.getNode()->getValueType(0);
14436 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14437 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14440 // Decide which area this value should be read from.
14441 // TODO: Implement the AMD64 ABI in its entirety. This simple
14442 // selection mechanism works only for the basic types.
14443 if (ArgVT == MVT::f80) {
14444 llvm_unreachable("va_arg for f80 not yet implemented");
14445 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14446 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14447 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14448 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14450 llvm_unreachable("Unhandled argument type in LowerVAARG");
14453 if (ArgMode == 2) {
14454 // Sanity Check: Make sure using fp_offset makes sense.
14455 assert(!DAG.getTarget().Options.UseSoftFloat &&
14456 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14457 Attribute::NoImplicitFloat)) &&
14458 Subtarget->hasSSE1());
14461 // Insert VAARG_64 node into the DAG
14462 // VAARG_64 returns two values: Variable Argument Address, Chain
14463 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),
14464 DAG.getConstant(ArgMode, MVT::i8),
14465 DAG.getConstant(Align, MVT::i32)};
14466 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14467 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14468 VTs, InstOps, MVT::i64,
14469 MachinePointerInfo(SV),
14471 /*Volatile=*/false,
14473 /*WriteMem=*/true);
14474 Chain = VAARG.getValue(1);
14476 // Load the next argument and return it
14477 return DAG.getLoad(ArgVT, dl,
14480 MachinePointerInfo(),
14481 false, false, false, 0);
14484 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14485 SelectionDAG &DAG) {
14486 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14487 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14488 SDValue Chain = Op.getOperand(0);
14489 SDValue DstPtr = Op.getOperand(1);
14490 SDValue SrcPtr = Op.getOperand(2);
14491 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14492 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14495 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14496 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14498 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14501 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14502 // amount is a constant. Takes immediate version of shift as input.
14503 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14504 SDValue SrcOp, uint64_t ShiftAmt,
14505 SelectionDAG &DAG) {
14506 MVT ElementType = VT.getVectorElementType();
14508 // Fold this packed shift into its first operand if ShiftAmt is 0.
14512 // Check for ShiftAmt >= element width
14513 if (ShiftAmt >= ElementType.getSizeInBits()) {
14514 if (Opc == X86ISD::VSRAI)
14515 ShiftAmt = ElementType.getSizeInBits() - 1;
14517 return DAG.getConstant(0, VT);
14520 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14521 && "Unknown target vector shift-by-constant node");
14523 // Fold this packed vector shift into a build vector if SrcOp is a
14524 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14525 if (VT == SrcOp.getSimpleValueType() &&
14526 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14527 SmallVector<SDValue, 8> Elts;
14528 unsigned NumElts = SrcOp->getNumOperands();
14529 ConstantSDNode *ND;
14532 default: llvm_unreachable(nullptr);
14533 case X86ISD::VSHLI:
14534 for (unsigned i=0; i!=NumElts; ++i) {
14535 SDValue CurrentOp = SrcOp->getOperand(i);
14536 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14537 Elts.push_back(CurrentOp);
14540 ND = cast<ConstantSDNode>(CurrentOp);
14541 const APInt &C = ND->getAPIntValue();
14542 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14545 case X86ISD::VSRLI:
14546 for (unsigned i=0; i!=NumElts; ++i) {
14547 SDValue CurrentOp = SrcOp->getOperand(i);
14548 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14549 Elts.push_back(CurrentOp);
14552 ND = cast<ConstantSDNode>(CurrentOp);
14553 const APInt &C = ND->getAPIntValue();
14554 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14557 case X86ISD::VSRAI:
14558 for (unsigned i=0; i!=NumElts; ++i) {
14559 SDValue CurrentOp = SrcOp->getOperand(i);
14560 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14561 Elts.push_back(CurrentOp);
14564 ND = cast<ConstantSDNode>(CurrentOp);
14565 const APInt &C = ND->getAPIntValue();
14566 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14571 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14574 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14577 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14578 // may or may not be a constant. Takes immediate version of shift as input.
14579 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14580 SDValue SrcOp, SDValue ShAmt,
14581 SelectionDAG &DAG) {
14582 MVT SVT = ShAmt.getSimpleValueType();
14583 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14585 // Catch shift-by-constant.
14586 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14587 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14588 CShAmt->getZExtValue(), DAG);
14590 // Change opcode to non-immediate version
14592 default: llvm_unreachable("Unknown target vector shift node");
14593 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14594 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14595 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14598 const X86Subtarget &Subtarget =
14599 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14600 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14601 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14602 // Let the shuffle legalizer expand this shift amount node.
14603 SDValue Op0 = ShAmt.getOperand(0);
14604 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14605 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14607 // Need to build a vector containing shift amount.
14608 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14609 SmallVector<SDValue, 4> ShOps;
14610 ShOps.push_back(ShAmt);
14611 if (SVT == MVT::i32) {
14612 ShOps.push_back(DAG.getConstant(0, SVT));
14613 ShOps.push_back(DAG.getUNDEF(SVT));
14615 ShOps.push_back(DAG.getUNDEF(SVT));
14617 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14618 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14621 // The return type has to be a 128-bit type with the same element
14622 // type as the input type.
14623 MVT EltVT = VT.getVectorElementType();
14624 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14626 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14627 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14630 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14631 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14632 /// necessary casting for \p Mask when lowering masking intrinsics.
14633 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14634 SDValue PreservedSrc,
14635 const X86Subtarget *Subtarget,
14636 SelectionDAG &DAG) {
14637 EVT VT = Op.getValueType();
14638 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14639 MVT::i1, VT.getVectorNumElements());
14640 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14641 Mask.getValueType().getSizeInBits());
14644 assert(MaskVT.isSimple() && "invalid mask type");
14646 if (isAllOnes(Mask))
14649 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14650 // are extracted by EXTRACT_SUBVECTOR.
14651 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14652 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14653 DAG.getIntPtrConstant(0));
14655 switch (Op.getOpcode()) {
14657 case X86ISD::PCMPEQM:
14658 case X86ISD::PCMPGTM:
14660 case X86ISD::CMPMU:
14661 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14663 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14664 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14665 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14668 /// \brief Creates an SDNode for a predicated scalar operation.
14669 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14670 /// The mask is comming as MVT::i8 and it should be truncated
14671 /// to MVT::i1 while lowering masking intrinsics.
14672 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14673 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14674 /// a scalar instruction.
14675 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14676 SDValue PreservedSrc,
14677 const X86Subtarget *Subtarget,
14678 SelectionDAG &DAG) {
14679 if (isAllOnes(Mask))
14682 EVT VT = Op.getValueType();
14684 // The mask should be of type MVT::i1
14685 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14687 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14688 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14689 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14692 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14693 SelectionDAG &DAG) {
14695 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14696 EVT VT = Op.getValueType();
14697 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14699 switch(IntrData->Type) {
14700 case INTR_TYPE_1OP:
14701 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14702 case INTR_TYPE_2OP:
14703 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14705 case INTR_TYPE_3OP:
14706 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14707 Op.getOperand(2), Op.getOperand(3));
14708 case INTR_TYPE_1OP_MASK_RM: {
14709 SDValue Src = Op.getOperand(1);
14710 SDValue Src0 = Op.getOperand(2);
14711 SDValue Mask = Op.getOperand(3);
14712 SDValue RoundingMode = Op.getOperand(4);
14713 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14715 Mask, Src0, Subtarget, DAG);
14717 case INTR_TYPE_SCALAR_MASK_RM: {
14718 SDValue Src1 = Op.getOperand(1);
14719 SDValue Src2 = Op.getOperand(2);
14720 SDValue Src0 = Op.getOperand(3);
14721 SDValue Mask = Op.getOperand(4);
14722 // There are 2 kinds of intrinsics in this group:
14723 // (1) With supress-all-exceptions (sae) - 6 operands
14724 // (2) With rounding mode and sae - 7 operands.
14725 if (Op.getNumOperands() == 6) {
14726 SDValue Sae = Op.getOperand(5);
14727 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14729 Mask, Src0, Subtarget, DAG);
14731 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
14732 SDValue RoundingMode = Op.getOperand(5);
14733 SDValue Sae = Op.getOperand(6);
14734 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14735 RoundingMode, Sae),
14736 Mask, Src0, Subtarget, DAG);
14738 case INTR_TYPE_2OP_MASK: {
14739 SDValue Src1 = Op.getOperand(1);
14740 SDValue Src2 = Op.getOperand(2);
14741 SDValue PassThru = Op.getOperand(3);
14742 SDValue Mask = Op.getOperand(4);
14743 // We specify 2 possible opcodes for intrinsics with rounding modes.
14744 // First, we check if the intrinsic may have non-default rounding mode,
14745 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14746 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14747 if (IntrWithRoundingModeOpcode != 0) {
14748 SDValue Rnd = Op.getOperand(5);
14749 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14750 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14751 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14752 dl, Op.getValueType(),
14754 Mask, PassThru, Subtarget, DAG);
14757 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14759 Mask, PassThru, Subtarget, DAG);
14761 case FMA_OP_MASK: {
14762 SDValue Src1 = Op.getOperand(1);
14763 SDValue Src2 = Op.getOperand(2);
14764 SDValue Src3 = Op.getOperand(3);
14765 SDValue Mask = Op.getOperand(4);
14766 // We specify 2 possible opcodes for intrinsics with rounding modes.
14767 // First, we check if the intrinsic may have non-default rounding mode,
14768 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14769 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14770 if (IntrWithRoundingModeOpcode != 0) {
14771 SDValue Rnd = Op.getOperand(5);
14772 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14773 X86::STATIC_ROUNDING::CUR_DIRECTION)
14774 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14775 dl, Op.getValueType(),
14776 Src1, Src2, Src3, Rnd),
14777 Mask, Src1, Subtarget, DAG);
14779 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14780 dl, Op.getValueType(),
14782 Mask, Src1, Subtarget, DAG);
14785 case CMP_MASK_CC: {
14786 // Comparison intrinsics with masks.
14787 // Example of transformation:
14788 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14789 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14791 // (v8i1 (insert_subvector undef,
14792 // (v2i1 (and (PCMPEQM %a, %b),
14793 // (extract_subvector
14794 // (v8i1 (bitcast %mask)), 0))), 0))))
14795 EVT VT = Op.getOperand(1).getValueType();
14796 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14797 VT.getVectorNumElements());
14798 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14799 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14800 Mask.getValueType().getSizeInBits());
14802 if (IntrData->Type == CMP_MASK_CC) {
14803 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14804 Op.getOperand(2), Op.getOperand(3));
14806 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14807 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14810 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
14811 DAG.getTargetConstant(0, MaskVT),
14813 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
14814 DAG.getUNDEF(BitcastVT), CmpMask,
14815 DAG.getIntPtrConstant(0));
14816 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
14818 case COMI: { // Comparison intrinsics
14819 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
14820 SDValue LHS = Op.getOperand(1);
14821 SDValue RHS = Op.getOperand(2);
14822 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14823 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14824 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
14825 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14826 DAG.getConstant(X86CC, MVT::i8), Cond);
14827 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14830 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
14831 Op.getOperand(1), Op.getOperand(2), DAG);
14833 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
14834 Op.getSimpleValueType(),
14836 Op.getOperand(2), DAG),
14837 Op.getOperand(4), Op.getOperand(3), Subtarget,
14839 case COMPRESS_EXPAND_IN_REG: {
14840 SDValue Mask = Op.getOperand(3);
14841 SDValue DataToCompress = Op.getOperand(1);
14842 SDValue PassThru = Op.getOperand(2);
14843 if (isAllOnes(Mask)) // return data as is
14844 return Op.getOperand(1);
14845 EVT VT = Op.getValueType();
14846 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14847 VT.getVectorNumElements());
14848 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14849 Mask.getValueType().getSizeInBits());
14851 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14852 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14853 DAG.getIntPtrConstant(0));
14855 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
14859 SDValue Mask = Op.getOperand(3);
14860 EVT VT = Op.getValueType();
14861 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14862 VT.getVectorNumElements());
14863 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14864 Mask.getValueType().getSizeInBits());
14866 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14867 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14868 DAG.getIntPtrConstant(0));
14869 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
14878 default: return SDValue(); // Don't custom lower most intrinsics.
14880 case Intrinsic::x86_avx2_permd:
14881 case Intrinsic::x86_avx2_permps:
14882 // Operands intentionally swapped. Mask is last operand to intrinsic,
14883 // but second operand for node/instruction.
14884 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14885 Op.getOperand(2), Op.getOperand(1));
14887 case Intrinsic::x86_avx512_mask_valign_q_512:
14888 case Intrinsic::x86_avx512_mask_valign_d_512:
14889 // Vector source operands are swapped.
14890 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14891 Op.getValueType(), Op.getOperand(2),
14894 Op.getOperand(5), Op.getOperand(4),
14897 // ptest and testp intrinsics. The intrinsic these come from are designed to
14898 // return an integer value, not just an instruction so lower it to the ptest
14899 // or testp pattern and a setcc for the result.
14900 case Intrinsic::x86_sse41_ptestz:
14901 case Intrinsic::x86_sse41_ptestc:
14902 case Intrinsic::x86_sse41_ptestnzc:
14903 case Intrinsic::x86_avx_ptestz_256:
14904 case Intrinsic::x86_avx_ptestc_256:
14905 case Intrinsic::x86_avx_ptestnzc_256:
14906 case Intrinsic::x86_avx_vtestz_ps:
14907 case Intrinsic::x86_avx_vtestc_ps:
14908 case Intrinsic::x86_avx_vtestnzc_ps:
14909 case Intrinsic::x86_avx_vtestz_pd:
14910 case Intrinsic::x86_avx_vtestc_pd:
14911 case Intrinsic::x86_avx_vtestnzc_pd:
14912 case Intrinsic::x86_avx_vtestz_ps_256:
14913 case Intrinsic::x86_avx_vtestc_ps_256:
14914 case Intrinsic::x86_avx_vtestnzc_ps_256:
14915 case Intrinsic::x86_avx_vtestz_pd_256:
14916 case Intrinsic::x86_avx_vtestc_pd_256:
14917 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14918 bool IsTestPacked = false;
14921 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14922 case Intrinsic::x86_avx_vtestz_ps:
14923 case Intrinsic::x86_avx_vtestz_pd:
14924 case Intrinsic::x86_avx_vtestz_ps_256:
14925 case Intrinsic::x86_avx_vtestz_pd_256:
14926 IsTestPacked = true; // Fallthrough
14927 case Intrinsic::x86_sse41_ptestz:
14928 case Intrinsic::x86_avx_ptestz_256:
14930 X86CC = X86::COND_E;
14932 case Intrinsic::x86_avx_vtestc_ps:
14933 case Intrinsic::x86_avx_vtestc_pd:
14934 case Intrinsic::x86_avx_vtestc_ps_256:
14935 case Intrinsic::x86_avx_vtestc_pd_256:
14936 IsTestPacked = true; // Fallthrough
14937 case Intrinsic::x86_sse41_ptestc:
14938 case Intrinsic::x86_avx_ptestc_256:
14940 X86CC = X86::COND_B;
14942 case Intrinsic::x86_avx_vtestnzc_ps:
14943 case Intrinsic::x86_avx_vtestnzc_pd:
14944 case Intrinsic::x86_avx_vtestnzc_ps_256:
14945 case Intrinsic::x86_avx_vtestnzc_pd_256:
14946 IsTestPacked = true; // Fallthrough
14947 case Intrinsic::x86_sse41_ptestnzc:
14948 case Intrinsic::x86_avx_ptestnzc_256:
14950 X86CC = X86::COND_A;
14954 SDValue LHS = Op.getOperand(1);
14955 SDValue RHS = Op.getOperand(2);
14956 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14957 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14958 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14959 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14960 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14962 case Intrinsic::x86_avx512_kortestz_w:
14963 case Intrinsic::x86_avx512_kortestc_w: {
14964 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14965 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14966 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14967 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14968 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14969 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14970 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14973 case Intrinsic::x86_sse42_pcmpistria128:
14974 case Intrinsic::x86_sse42_pcmpestria128:
14975 case Intrinsic::x86_sse42_pcmpistric128:
14976 case Intrinsic::x86_sse42_pcmpestric128:
14977 case Intrinsic::x86_sse42_pcmpistrio128:
14978 case Intrinsic::x86_sse42_pcmpestrio128:
14979 case Intrinsic::x86_sse42_pcmpistris128:
14980 case Intrinsic::x86_sse42_pcmpestris128:
14981 case Intrinsic::x86_sse42_pcmpistriz128:
14982 case Intrinsic::x86_sse42_pcmpestriz128: {
14986 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14987 case Intrinsic::x86_sse42_pcmpistria128:
14988 Opcode = X86ISD::PCMPISTRI;
14989 X86CC = X86::COND_A;
14991 case Intrinsic::x86_sse42_pcmpestria128:
14992 Opcode = X86ISD::PCMPESTRI;
14993 X86CC = X86::COND_A;
14995 case Intrinsic::x86_sse42_pcmpistric128:
14996 Opcode = X86ISD::PCMPISTRI;
14997 X86CC = X86::COND_B;
14999 case Intrinsic::x86_sse42_pcmpestric128:
15000 Opcode = X86ISD::PCMPESTRI;
15001 X86CC = X86::COND_B;
15003 case Intrinsic::x86_sse42_pcmpistrio128:
15004 Opcode = X86ISD::PCMPISTRI;
15005 X86CC = X86::COND_O;
15007 case Intrinsic::x86_sse42_pcmpestrio128:
15008 Opcode = X86ISD::PCMPESTRI;
15009 X86CC = X86::COND_O;
15011 case Intrinsic::x86_sse42_pcmpistris128:
15012 Opcode = X86ISD::PCMPISTRI;
15013 X86CC = X86::COND_S;
15015 case Intrinsic::x86_sse42_pcmpestris128:
15016 Opcode = X86ISD::PCMPESTRI;
15017 X86CC = X86::COND_S;
15019 case Intrinsic::x86_sse42_pcmpistriz128:
15020 Opcode = X86ISD::PCMPISTRI;
15021 X86CC = X86::COND_E;
15023 case Intrinsic::x86_sse42_pcmpestriz128:
15024 Opcode = X86ISD::PCMPESTRI;
15025 X86CC = X86::COND_E;
15028 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15029 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15030 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15031 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15032 DAG.getConstant(X86CC, MVT::i8),
15033 SDValue(PCMP.getNode(), 1));
15034 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15037 case Intrinsic::x86_sse42_pcmpistri128:
15038 case Intrinsic::x86_sse42_pcmpestri128: {
15040 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15041 Opcode = X86ISD::PCMPISTRI;
15043 Opcode = X86ISD::PCMPESTRI;
15045 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15046 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15047 return DAG.getNode(Opcode, dl, VTs, NewOps);
15052 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15053 SDValue Src, SDValue Mask, SDValue Base,
15054 SDValue Index, SDValue ScaleOp, SDValue Chain,
15055 const X86Subtarget * Subtarget) {
15057 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15058 assert(C && "Invalid scale type");
15059 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15060 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15061 Index.getSimpleValueType().getVectorNumElements());
15063 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15065 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15067 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15068 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15069 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15070 SDValue Segment = DAG.getRegister(0, MVT::i32);
15071 if (Src.getOpcode() == ISD::UNDEF)
15072 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15073 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15074 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15075 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15076 return DAG.getMergeValues(RetOps, dl);
15079 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15080 SDValue Src, SDValue Mask, SDValue Base,
15081 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15083 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15084 assert(C && "Invalid scale type");
15085 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15086 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15087 SDValue Segment = DAG.getRegister(0, MVT::i32);
15088 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15089 Index.getSimpleValueType().getVectorNumElements());
15091 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15093 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15095 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15096 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15097 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15098 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15099 return SDValue(Res, 1);
15102 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15103 SDValue Mask, SDValue Base, SDValue Index,
15104 SDValue ScaleOp, SDValue Chain) {
15106 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15107 assert(C && "Invalid scale type");
15108 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15109 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15110 SDValue Segment = DAG.getRegister(0, MVT::i32);
15112 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15114 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15116 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15118 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15119 //SDVTList VTs = DAG.getVTList(MVT::Other);
15120 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15121 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15122 return SDValue(Res, 0);
15125 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15126 // read performance monitor counters (x86_rdpmc).
15127 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15128 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15129 SmallVectorImpl<SDValue> &Results) {
15130 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15131 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15134 // The ECX register is used to select the index of the performance counter
15136 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15138 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15140 // Reads the content of a 64-bit performance counter and returns it in the
15141 // registers EDX:EAX.
15142 if (Subtarget->is64Bit()) {
15143 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15144 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15147 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15148 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15151 Chain = HI.getValue(1);
15153 if (Subtarget->is64Bit()) {
15154 // The EAX register is loaded with the low-order 32 bits. The EDX register
15155 // is loaded with the supported high-order bits of the counter.
15156 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15157 DAG.getConstant(32, MVT::i8));
15158 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15159 Results.push_back(Chain);
15163 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15164 SDValue Ops[] = { LO, HI };
15165 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15166 Results.push_back(Pair);
15167 Results.push_back(Chain);
15170 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15171 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15172 // also used to custom lower READCYCLECOUNTER nodes.
15173 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15174 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15175 SmallVectorImpl<SDValue> &Results) {
15176 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15177 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15180 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15181 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15182 // and the EAX register is loaded with the low-order 32 bits.
15183 if (Subtarget->is64Bit()) {
15184 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15185 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15188 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15189 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15192 SDValue Chain = HI.getValue(1);
15194 if (Opcode == X86ISD::RDTSCP_DAG) {
15195 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15197 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15198 // the ECX register. Add 'ecx' explicitly to the chain.
15199 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15201 // Explicitly store the content of ECX at the location passed in input
15202 // to the 'rdtscp' intrinsic.
15203 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15204 MachinePointerInfo(), false, false, 0);
15207 if (Subtarget->is64Bit()) {
15208 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15209 // the EAX register is loaded with the low-order 32 bits.
15210 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15211 DAG.getConstant(32, MVT::i8));
15212 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15213 Results.push_back(Chain);
15217 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15218 SDValue Ops[] = { LO, HI };
15219 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15220 Results.push_back(Pair);
15221 Results.push_back(Chain);
15224 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15225 SelectionDAG &DAG) {
15226 SmallVector<SDValue, 2> Results;
15228 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15230 return DAG.getMergeValues(Results, DL);
15234 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15235 SelectionDAG &DAG) {
15236 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15238 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15243 switch(IntrData->Type) {
15245 llvm_unreachable("Unknown Intrinsic Type");
15249 // Emit the node with the right value type.
15250 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15251 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15253 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15254 // Otherwise return the value from Rand, which is always 0, casted to i32.
15255 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15256 DAG.getConstant(1, Op->getValueType(1)),
15257 DAG.getConstant(X86::COND_B, MVT::i32),
15258 SDValue(Result.getNode(), 1) };
15259 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15260 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15263 // Return { result, isValid, chain }.
15264 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15265 SDValue(Result.getNode(), 2));
15268 //gather(v1, mask, index, base, scale);
15269 SDValue Chain = Op.getOperand(0);
15270 SDValue Src = Op.getOperand(2);
15271 SDValue Base = Op.getOperand(3);
15272 SDValue Index = Op.getOperand(4);
15273 SDValue Mask = Op.getOperand(5);
15274 SDValue Scale = Op.getOperand(6);
15275 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15279 //scatter(base, mask, index, v1, scale);
15280 SDValue Chain = Op.getOperand(0);
15281 SDValue Base = Op.getOperand(2);
15282 SDValue Mask = Op.getOperand(3);
15283 SDValue Index = Op.getOperand(4);
15284 SDValue Src = Op.getOperand(5);
15285 SDValue Scale = Op.getOperand(6);
15286 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15289 SDValue Hint = Op.getOperand(6);
15291 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15292 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15293 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15294 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15295 SDValue Chain = Op.getOperand(0);
15296 SDValue Mask = Op.getOperand(2);
15297 SDValue Index = Op.getOperand(3);
15298 SDValue Base = Op.getOperand(4);
15299 SDValue Scale = Op.getOperand(5);
15300 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15302 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15304 SmallVector<SDValue, 2> Results;
15305 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15306 return DAG.getMergeValues(Results, dl);
15308 // Read Performance Monitoring Counters.
15310 SmallVector<SDValue, 2> Results;
15311 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15312 return DAG.getMergeValues(Results, dl);
15314 // XTEST intrinsics.
15316 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15317 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15318 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15319 DAG.getConstant(X86::COND_NE, MVT::i8),
15321 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15322 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15323 Ret, SDValue(InTrans.getNode(), 1));
15327 SmallVector<SDValue, 2> Results;
15328 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15329 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15330 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15331 DAG.getConstant(-1, MVT::i8));
15332 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15333 Op.getOperand(4), GenCF.getValue(1));
15334 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15335 Op.getOperand(5), MachinePointerInfo(),
15337 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15338 DAG.getConstant(X86::COND_B, MVT::i8),
15340 Results.push_back(SetCC);
15341 Results.push_back(Store);
15342 return DAG.getMergeValues(Results, dl);
15344 case COMPRESS_TO_MEM: {
15346 SDValue Mask = Op.getOperand(4);
15347 SDValue DataToCompress = Op.getOperand(3);
15348 SDValue Addr = Op.getOperand(2);
15349 SDValue Chain = Op.getOperand(0);
15351 if (isAllOnes(Mask)) // return just a store
15352 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15353 MachinePointerInfo(), false, false, 0);
15355 EVT VT = DataToCompress.getValueType();
15356 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15357 VT.getVectorNumElements());
15358 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15359 Mask.getValueType().getSizeInBits());
15360 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15361 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15362 DAG.getIntPtrConstant(0));
15364 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15365 DataToCompress, DAG.getUNDEF(VT));
15366 return DAG.getStore(Chain, dl, Compressed, Addr,
15367 MachinePointerInfo(), false, false, 0);
15369 case EXPAND_FROM_MEM: {
15371 SDValue Mask = Op.getOperand(4);
15372 SDValue PathThru = Op.getOperand(3);
15373 SDValue Addr = Op.getOperand(2);
15374 SDValue Chain = Op.getOperand(0);
15375 EVT VT = Op.getValueType();
15377 if (isAllOnes(Mask)) // return just a load
15378 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15380 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15381 VT.getVectorNumElements());
15382 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15383 Mask.getValueType().getSizeInBits());
15384 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15385 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15386 DAG.getIntPtrConstant(0));
15388 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15389 false, false, false, 0);
15391 SDValue Results[] = {
15392 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15394 return DAG.getMergeValues(Results, dl);
15399 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15400 SelectionDAG &DAG) const {
15401 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15402 MFI->setReturnAddressIsTaken(true);
15404 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15407 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15409 EVT PtrVT = getPointerTy();
15412 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15413 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15414 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15415 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15416 DAG.getNode(ISD::ADD, dl, PtrVT,
15417 FrameAddr, Offset),
15418 MachinePointerInfo(), false, false, false, 0);
15421 // Just load the return address.
15422 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15423 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15424 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15427 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15428 MachineFunction &MF = DAG.getMachineFunction();
15429 MachineFrameInfo *MFI = MF.getFrameInfo();
15430 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15431 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15432 EVT VT = Op.getValueType();
15434 MFI->setFrameAddressIsTaken(true);
15436 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15437 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15438 // is not possible to crawl up the stack without looking at the unwind codes
15440 int FrameAddrIndex = FuncInfo->getFAIndex();
15441 if (!FrameAddrIndex) {
15442 // Set up a frame object for the return address.
15443 unsigned SlotSize = RegInfo->getSlotSize();
15444 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15445 SlotSize, /*Offset=*/INT64_MIN, /*IsImmutable=*/false);
15446 FuncInfo->setFAIndex(FrameAddrIndex);
15448 return DAG.getFrameIndex(FrameAddrIndex, VT);
15451 unsigned FrameReg =
15452 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15453 SDLoc dl(Op); // FIXME probably not meaningful
15454 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15455 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15456 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15457 "Invalid Frame Register!");
15458 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15460 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15461 MachinePointerInfo(),
15462 false, false, false, 0);
15466 // FIXME? Maybe this could be a TableGen attribute on some registers and
15467 // this table could be generated automatically from RegInfo.
15468 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15470 unsigned Reg = StringSwitch<unsigned>(RegName)
15471 .Case("esp", X86::ESP)
15472 .Case("rsp", X86::RSP)
15476 report_fatal_error("Invalid register name global variable");
15479 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15480 SelectionDAG &DAG) const {
15481 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15482 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15485 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15486 SDValue Chain = Op.getOperand(0);
15487 SDValue Offset = Op.getOperand(1);
15488 SDValue Handler = Op.getOperand(2);
15491 EVT PtrVT = getPointerTy();
15492 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15493 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15494 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15495 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15496 "Invalid Frame Register!");
15497 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15498 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15500 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15501 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15502 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15503 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15505 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15507 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15508 DAG.getRegister(StoreAddrReg, PtrVT));
15511 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15512 SelectionDAG &DAG) const {
15514 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15515 DAG.getVTList(MVT::i32, MVT::Other),
15516 Op.getOperand(0), Op.getOperand(1));
15519 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15520 SelectionDAG &DAG) const {
15522 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15523 Op.getOperand(0), Op.getOperand(1));
15526 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15527 return Op.getOperand(0);
15530 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15531 SelectionDAG &DAG) const {
15532 SDValue Root = Op.getOperand(0);
15533 SDValue Trmp = Op.getOperand(1); // trampoline
15534 SDValue FPtr = Op.getOperand(2); // nested function
15535 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15538 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15539 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15541 if (Subtarget->is64Bit()) {
15542 SDValue OutChains[6];
15544 // Large code-model.
15545 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15546 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15548 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15549 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15551 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15553 // Load the pointer to the nested function into R11.
15554 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15555 SDValue Addr = Trmp;
15556 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15557 Addr, MachinePointerInfo(TrmpAddr),
15560 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15561 DAG.getConstant(2, MVT::i64));
15562 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15563 MachinePointerInfo(TrmpAddr, 2),
15566 // Load the 'nest' parameter value into R10.
15567 // R10 is specified in X86CallingConv.td
15568 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15569 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15570 DAG.getConstant(10, MVT::i64));
15571 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15572 Addr, MachinePointerInfo(TrmpAddr, 10),
15575 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15576 DAG.getConstant(12, MVT::i64));
15577 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15578 MachinePointerInfo(TrmpAddr, 12),
15581 // Jump to the nested function.
15582 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15583 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15584 DAG.getConstant(20, MVT::i64));
15585 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15586 Addr, MachinePointerInfo(TrmpAddr, 20),
15589 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15590 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15591 DAG.getConstant(22, MVT::i64));
15592 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15593 MachinePointerInfo(TrmpAddr, 22),
15596 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15598 const Function *Func =
15599 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15600 CallingConv::ID CC = Func->getCallingConv();
15605 llvm_unreachable("Unsupported calling convention");
15606 case CallingConv::C:
15607 case CallingConv::X86_StdCall: {
15608 // Pass 'nest' parameter in ECX.
15609 // Must be kept in sync with X86CallingConv.td
15610 NestReg = X86::ECX;
15612 // Check that ECX wasn't needed by an 'inreg' parameter.
15613 FunctionType *FTy = Func->getFunctionType();
15614 const AttributeSet &Attrs = Func->getAttributes();
15616 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15617 unsigned InRegCount = 0;
15620 for (FunctionType::param_iterator I = FTy->param_begin(),
15621 E = FTy->param_end(); I != E; ++I, ++Idx)
15622 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15623 // FIXME: should only count parameters that are lowered to integers.
15624 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15626 if (InRegCount > 2) {
15627 report_fatal_error("Nest register in use - reduce number of inreg"
15633 case CallingConv::X86_FastCall:
15634 case CallingConv::X86_ThisCall:
15635 case CallingConv::Fast:
15636 // Pass 'nest' parameter in EAX.
15637 // Must be kept in sync with X86CallingConv.td
15638 NestReg = X86::EAX;
15642 SDValue OutChains[4];
15643 SDValue Addr, Disp;
15645 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15646 DAG.getConstant(10, MVT::i32));
15647 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15649 // This is storing the opcode for MOV32ri.
15650 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15651 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15652 OutChains[0] = DAG.getStore(Root, dl,
15653 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15654 Trmp, MachinePointerInfo(TrmpAddr),
15657 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15658 DAG.getConstant(1, MVT::i32));
15659 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15660 MachinePointerInfo(TrmpAddr, 1),
15663 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15664 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15665 DAG.getConstant(5, MVT::i32));
15666 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15667 MachinePointerInfo(TrmpAddr, 5),
15670 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15671 DAG.getConstant(6, MVT::i32));
15672 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15673 MachinePointerInfo(TrmpAddr, 6),
15676 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15680 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15681 SelectionDAG &DAG) const {
15683 The rounding mode is in bits 11:10 of FPSR, and has the following
15685 00 Round to nearest
15690 FLT_ROUNDS, on the other hand, expects the following:
15697 To perform the conversion, we do:
15698 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15701 MachineFunction &MF = DAG.getMachineFunction();
15702 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15703 unsigned StackAlignment = TFI.getStackAlignment();
15704 MVT VT = Op.getSimpleValueType();
15707 // Save FP Control Word to stack slot
15708 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15709 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15711 MachineMemOperand *MMO =
15712 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15713 MachineMemOperand::MOStore, 2, 2);
15715 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15716 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15717 DAG.getVTList(MVT::Other),
15718 Ops, MVT::i16, MMO);
15720 // Load FP Control Word from stack slot
15721 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15722 MachinePointerInfo(), false, false, false, 0);
15724 // Transform as necessary
15726 DAG.getNode(ISD::SRL, DL, MVT::i16,
15727 DAG.getNode(ISD::AND, DL, MVT::i16,
15728 CWD, DAG.getConstant(0x800, MVT::i16)),
15729 DAG.getConstant(11, MVT::i8));
15731 DAG.getNode(ISD::SRL, DL, MVT::i16,
15732 DAG.getNode(ISD::AND, DL, MVT::i16,
15733 CWD, DAG.getConstant(0x400, MVT::i16)),
15734 DAG.getConstant(9, MVT::i8));
15737 DAG.getNode(ISD::AND, DL, MVT::i16,
15738 DAG.getNode(ISD::ADD, DL, MVT::i16,
15739 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15740 DAG.getConstant(1, MVT::i16)),
15741 DAG.getConstant(3, MVT::i16));
15743 return DAG.getNode((VT.getSizeInBits() < 16 ?
15744 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15747 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15748 MVT VT = Op.getSimpleValueType();
15750 unsigned NumBits = VT.getSizeInBits();
15753 Op = Op.getOperand(0);
15754 if (VT == MVT::i8) {
15755 // Zero extend to i32 since there is not an i8 bsr.
15757 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15760 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15761 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15762 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15764 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15767 DAG.getConstant(NumBits+NumBits-1, OpVT),
15768 DAG.getConstant(X86::COND_E, MVT::i8),
15771 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15773 // Finally xor with NumBits-1.
15774 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15777 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15781 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15782 MVT VT = Op.getSimpleValueType();
15784 unsigned NumBits = VT.getSizeInBits();
15787 Op = Op.getOperand(0);
15788 if (VT == MVT::i8) {
15789 // Zero extend to i32 since there is not an i8 bsr.
15791 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15794 // Issue a bsr (scan bits in reverse).
15795 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15796 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15798 // And xor with NumBits-1.
15799 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15802 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15806 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15807 MVT VT = Op.getSimpleValueType();
15808 unsigned NumBits = VT.getSizeInBits();
15810 Op = Op.getOperand(0);
15812 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15813 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15814 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15816 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15819 DAG.getConstant(NumBits, VT),
15820 DAG.getConstant(X86::COND_E, MVT::i8),
15823 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15826 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15827 // ones, and then concatenate the result back.
15828 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15829 MVT VT = Op.getSimpleValueType();
15831 assert(VT.is256BitVector() && VT.isInteger() &&
15832 "Unsupported value type for operation");
15834 unsigned NumElems = VT.getVectorNumElements();
15837 // Extract the LHS vectors
15838 SDValue LHS = Op.getOperand(0);
15839 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15840 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15842 // Extract the RHS vectors
15843 SDValue RHS = Op.getOperand(1);
15844 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15845 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15847 MVT EltVT = VT.getVectorElementType();
15848 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15850 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15851 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15852 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15855 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15856 assert(Op.getSimpleValueType().is256BitVector() &&
15857 Op.getSimpleValueType().isInteger() &&
15858 "Only handle AVX 256-bit vector integer operation");
15859 return Lower256IntArith(Op, DAG);
15862 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15863 assert(Op.getSimpleValueType().is256BitVector() &&
15864 Op.getSimpleValueType().isInteger() &&
15865 "Only handle AVX 256-bit vector integer operation");
15866 return Lower256IntArith(Op, DAG);
15869 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15870 SelectionDAG &DAG) {
15872 MVT VT = Op.getSimpleValueType();
15874 // Decompose 256-bit ops into smaller 128-bit ops.
15875 if (VT.is256BitVector() && !Subtarget->hasInt256())
15876 return Lower256IntArith(Op, DAG);
15878 SDValue A = Op.getOperand(0);
15879 SDValue B = Op.getOperand(1);
15881 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15882 if (VT == MVT::v4i32) {
15883 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15884 "Should not custom lower when pmuldq is available!");
15886 // Extract the odd parts.
15887 static const int UnpackMask[] = { 1, -1, 3, -1 };
15888 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15889 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15891 // Multiply the even parts.
15892 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15893 // Now multiply odd parts.
15894 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15896 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15897 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15899 // Merge the two vectors back together with a shuffle. This expands into 2
15901 static const int ShufMask[] = { 0, 4, 2, 6 };
15902 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15905 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15906 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15908 // Ahi = psrlqi(a, 32);
15909 // Bhi = psrlqi(b, 32);
15911 // AloBlo = pmuludq(a, b);
15912 // AloBhi = pmuludq(a, Bhi);
15913 // AhiBlo = pmuludq(Ahi, b);
15915 // AloBhi = psllqi(AloBhi, 32);
15916 // AhiBlo = psllqi(AhiBlo, 32);
15917 // return AloBlo + AloBhi + AhiBlo;
15919 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15920 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15922 // Bit cast to 32-bit vectors for MULUDQ
15923 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15924 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15925 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15926 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15927 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15928 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15930 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15931 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15932 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15934 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15935 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15937 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15938 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15941 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15942 assert(Subtarget->isTargetWin64() && "Unexpected target");
15943 EVT VT = Op.getValueType();
15944 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15945 "Unexpected return type for lowering");
15949 switch (Op->getOpcode()) {
15950 default: llvm_unreachable("Unexpected request for libcall!");
15951 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15952 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15953 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15954 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15955 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15956 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15960 SDValue InChain = DAG.getEntryNode();
15962 TargetLowering::ArgListTy Args;
15963 TargetLowering::ArgListEntry Entry;
15964 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15965 EVT ArgVT = Op->getOperand(i).getValueType();
15966 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15967 "Unexpected argument type for lowering");
15968 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15969 Entry.Node = StackPtr;
15970 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15972 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15973 Entry.Ty = PointerType::get(ArgTy,0);
15974 Entry.isSExt = false;
15975 Entry.isZExt = false;
15976 Args.push_back(Entry);
15979 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15982 TargetLowering::CallLoweringInfo CLI(DAG);
15983 CLI.setDebugLoc(dl).setChain(InChain)
15984 .setCallee(getLibcallCallingConv(LC),
15985 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15986 Callee, std::move(Args), 0)
15987 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15989 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15990 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15993 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15994 SelectionDAG &DAG) {
15995 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15996 EVT VT = Op0.getValueType();
15999 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16000 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16002 // PMULxD operations multiply each even value (starting at 0) of LHS with
16003 // the related value of RHS and produce a widen result.
16004 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16005 // => <2 x i64> <ae|cg>
16007 // In other word, to have all the results, we need to perform two PMULxD:
16008 // 1. one with the even values.
16009 // 2. one with the odd values.
16010 // To achieve #2, with need to place the odd values at an even position.
16012 // Place the odd value at an even position (basically, shift all values 1
16013 // step to the left):
16014 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16015 // <a|b|c|d> => <b|undef|d|undef>
16016 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16017 // <e|f|g|h> => <f|undef|h|undef>
16018 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16020 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16022 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16023 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16025 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16026 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16027 // => <2 x i64> <ae|cg>
16028 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16029 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16030 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16031 // => <2 x i64> <bf|dh>
16032 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16033 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16035 // Shuffle it back into the right order.
16036 SDValue Highs, Lows;
16037 if (VT == MVT::v8i32) {
16038 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16039 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16040 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16041 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16043 const int HighMask[] = {1, 5, 3, 7};
16044 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16045 const int LowMask[] = {0, 4, 2, 6};
16046 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16049 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16050 // unsigned multiply.
16051 if (IsSigned && !Subtarget->hasSSE41()) {
16053 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16054 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16055 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16056 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16057 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16059 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16060 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16063 // The first result of MUL_LOHI is actually the low value, followed by the
16065 SDValue Ops[] = {Lows, Highs};
16066 return DAG.getMergeValues(Ops, dl);
16069 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16070 const X86Subtarget *Subtarget) {
16071 MVT VT = Op.getSimpleValueType();
16073 SDValue R = Op.getOperand(0);
16074 SDValue Amt = Op.getOperand(1);
16076 // Optimize shl/srl/sra with constant shift amount.
16077 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16078 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16079 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16081 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16082 (Subtarget->hasInt256() &&
16083 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16084 (Subtarget->hasAVX512() &&
16085 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16086 if (Op.getOpcode() == ISD::SHL)
16087 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16089 if (Op.getOpcode() == ISD::SRL)
16090 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16092 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16093 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16097 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16098 unsigned NumElts = VT.getVectorNumElements();
16099 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16101 if (Op.getOpcode() == ISD::SHL) {
16102 // Make a large shift.
16103 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16105 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16106 // Zero out the rightmost bits.
16107 SmallVector<SDValue, 32> V(
16108 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), MVT::i8));
16109 return DAG.getNode(ISD::AND, dl, VT, SHL,
16110 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16112 if (Op.getOpcode() == ISD::SRL) {
16113 // Make a large shift.
16114 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16116 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16117 // Zero out the leftmost bits.
16118 SmallVector<SDValue, 32> V(
16119 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, MVT::i8));
16120 return DAG.getNode(ISD::AND, dl, VT, SRL,
16121 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16123 if (Op.getOpcode() == ISD::SRA) {
16124 if (ShiftAmt == 7) {
16125 // R s>> 7 === R s< 0
16126 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16127 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16130 // R s>> a === ((R u>> a) ^ m) - m
16131 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16132 SmallVector<SDValue, 32> V(NumElts,
16133 DAG.getConstant(128 >> ShiftAmt, MVT::i8));
16134 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16135 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16136 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16139 llvm_unreachable("Unknown shift opcode.");
16144 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16145 if (!Subtarget->is64Bit() &&
16146 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16147 Amt.getOpcode() == ISD::BITCAST &&
16148 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16149 Amt = Amt.getOperand(0);
16150 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16151 VT.getVectorNumElements();
16152 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16153 uint64_t ShiftAmt = 0;
16154 for (unsigned i = 0; i != Ratio; ++i) {
16155 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16159 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16161 // Check remaining shift amounts.
16162 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16163 uint64_t ShAmt = 0;
16164 for (unsigned j = 0; j != Ratio; ++j) {
16165 ConstantSDNode *C =
16166 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16170 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16172 if (ShAmt != ShiftAmt)
16175 switch (Op.getOpcode()) {
16177 llvm_unreachable("Unknown shift opcode!");
16179 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16182 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16185 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16193 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16194 const X86Subtarget* Subtarget) {
16195 MVT VT = Op.getSimpleValueType();
16197 SDValue R = Op.getOperand(0);
16198 SDValue Amt = Op.getOperand(1);
16200 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16201 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16202 (Subtarget->hasInt256() &&
16203 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16204 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16205 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16207 EVT EltVT = VT.getVectorElementType();
16209 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16210 // Check if this build_vector node is doing a splat.
16211 // If so, then set BaseShAmt equal to the splat value.
16212 BaseShAmt = BV->getSplatValue();
16213 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16214 BaseShAmt = SDValue();
16216 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16217 Amt = Amt.getOperand(0);
16219 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16220 if (SVN && SVN->isSplat()) {
16221 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16222 SDValue InVec = Amt.getOperand(0);
16223 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16224 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16225 "Unexpected shuffle index found!");
16226 BaseShAmt = InVec.getOperand(SplatIdx);
16227 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16228 if (ConstantSDNode *C =
16229 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16230 if (C->getZExtValue() == SplatIdx)
16231 BaseShAmt = InVec.getOperand(1);
16236 // Avoid introducing an extract element from a shuffle.
16237 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16238 DAG.getIntPtrConstant(SplatIdx));
16242 if (BaseShAmt.getNode()) {
16243 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16244 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16245 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16246 else if (EltVT.bitsLT(MVT::i32))
16247 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16249 switch (Op.getOpcode()) {
16251 llvm_unreachable("Unknown shift opcode!");
16253 switch (VT.SimpleTy) {
16254 default: return SDValue();
16263 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16266 switch (VT.SimpleTy) {
16267 default: return SDValue();
16274 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16277 switch (VT.SimpleTy) {
16278 default: return SDValue();
16287 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16293 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16294 if (!Subtarget->is64Bit() &&
16295 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16296 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16297 Amt.getOpcode() == ISD::BITCAST &&
16298 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16299 Amt = Amt.getOperand(0);
16300 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16301 VT.getVectorNumElements();
16302 std::vector<SDValue> Vals(Ratio);
16303 for (unsigned i = 0; i != Ratio; ++i)
16304 Vals[i] = Amt.getOperand(i);
16305 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16306 for (unsigned j = 0; j != Ratio; ++j)
16307 if (Vals[j] != Amt.getOperand(i + j))
16310 switch (Op.getOpcode()) {
16312 llvm_unreachable("Unknown shift opcode!");
16314 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16316 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16318 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16325 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16326 SelectionDAG &DAG) {
16327 MVT VT = Op.getSimpleValueType();
16329 SDValue R = Op.getOperand(0);
16330 SDValue Amt = Op.getOperand(1);
16332 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16333 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16335 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16338 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16341 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16344 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16345 if (Subtarget->hasInt256()) {
16346 if (Op.getOpcode() == ISD::SRL &&
16347 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16348 VT == MVT::v4i64 || VT == MVT::v8i32))
16350 if (Op.getOpcode() == ISD::SHL &&
16351 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16352 VT == MVT::v4i64 || VT == MVT::v8i32))
16354 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16358 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16359 // shifts per-lane and then shuffle the partial results back together.
16360 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16361 // Splat the shift amounts so the scalar shifts above will catch it.
16362 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16363 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16364 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16365 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16366 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16369 // If possible, lower this packed shift into a vector multiply instead of
16370 // expanding it into a sequence of scalar shifts.
16371 // Do this only if the vector shift count is a constant build_vector.
16372 if (Op.getOpcode() == ISD::SHL &&
16373 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16374 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16375 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16376 SmallVector<SDValue, 8> Elts;
16377 EVT SVT = VT.getScalarType();
16378 unsigned SVTBits = SVT.getSizeInBits();
16379 const APInt &One = APInt(SVTBits, 1);
16380 unsigned NumElems = VT.getVectorNumElements();
16382 for (unsigned i=0; i !=NumElems; ++i) {
16383 SDValue Op = Amt->getOperand(i);
16384 if (Op->getOpcode() == ISD::UNDEF) {
16385 Elts.push_back(Op);
16389 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16390 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16391 uint64_t ShAmt = C.getZExtValue();
16392 if (ShAmt >= SVTBits) {
16393 Elts.push_back(DAG.getUNDEF(SVT));
16396 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16398 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16399 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16402 // Lower SHL with variable shift amount.
16403 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16404 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16406 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16407 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16408 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16409 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16412 // If possible, lower this shift as a sequence of two shifts by
16413 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16415 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16417 // Could be rewritten as:
16418 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16420 // The advantage is that the two shifts from the example would be
16421 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16422 // the vector shift into four scalar shifts plus four pairs of vector
16424 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16425 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16426 unsigned TargetOpcode = X86ISD::MOVSS;
16427 bool CanBeSimplified;
16428 // The splat value for the first packed shift (the 'X' from the example).
16429 SDValue Amt1 = Amt->getOperand(0);
16430 // The splat value for the second packed shift (the 'Y' from the example).
16431 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16432 Amt->getOperand(2);
16434 // See if it is possible to replace this node with a sequence of
16435 // two shifts followed by a MOVSS/MOVSD
16436 if (VT == MVT::v4i32) {
16437 // Check if it is legal to use a MOVSS.
16438 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16439 Amt2 == Amt->getOperand(3);
16440 if (!CanBeSimplified) {
16441 // Otherwise, check if we can still simplify this node using a MOVSD.
16442 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16443 Amt->getOperand(2) == Amt->getOperand(3);
16444 TargetOpcode = X86ISD::MOVSD;
16445 Amt2 = Amt->getOperand(2);
16448 // Do similar checks for the case where the machine value type
16450 CanBeSimplified = Amt1 == Amt->getOperand(1);
16451 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16452 CanBeSimplified = Amt2 == Amt->getOperand(i);
16454 if (!CanBeSimplified) {
16455 TargetOpcode = X86ISD::MOVSD;
16456 CanBeSimplified = true;
16457 Amt2 = Amt->getOperand(4);
16458 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16459 CanBeSimplified = Amt1 == Amt->getOperand(i);
16460 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16461 CanBeSimplified = Amt2 == Amt->getOperand(j);
16465 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16466 isa<ConstantSDNode>(Amt2)) {
16467 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16468 EVT CastVT = MVT::v4i32;
16470 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16471 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16473 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16474 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16475 if (TargetOpcode == X86ISD::MOVSD)
16476 CastVT = MVT::v2i64;
16477 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16478 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16479 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16481 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16485 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16486 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16489 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16490 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16492 // Turn 'a' into a mask suitable for VSELECT
16493 SDValue VSelM = DAG.getConstant(0x80, VT);
16494 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16495 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16497 SDValue CM1 = DAG.getConstant(0x0f, VT);
16498 SDValue CM2 = DAG.getConstant(0x3f, VT);
16500 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16501 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16502 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16503 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16504 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16507 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16508 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16509 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16511 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16512 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16513 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16514 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16515 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16518 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16519 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16520 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16522 // return VSELECT(r, r+r, a);
16523 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16524 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16528 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16529 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16530 // solution better.
16531 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16532 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16534 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16535 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16536 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16537 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16538 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16541 // Decompose 256-bit shifts into smaller 128-bit shifts.
16542 if (VT.is256BitVector()) {
16543 unsigned NumElems = VT.getVectorNumElements();
16544 MVT EltVT = VT.getVectorElementType();
16545 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16547 // Extract the two vectors
16548 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16549 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16551 // Recreate the shift amount vectors
16552 SDValue Amt1, Amt2;
16553 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16554 // Constant shift amount
16555 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16556 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16557 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16559 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16560 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16562 // Variable shift amount
16563 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16564 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16567 // Issue new vector shifts for the smaller types
16568 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16569 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16571 // Concatenate the result back
16572 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16578 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16579 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16580 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16581 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16582 // has only one use.
16583 SDNode *N = Op.getNode();
16584 SDValue LHS = N->getOperand(0);
16585 SDValue RHS = N->getOperand(1);
16586 unsigned BaseOp = 0;
16589 switch (Op.getOpcode()) {
16590 default: llvm_unreachable("Unknown ovf instruction!");
16592 // A subtract of one will be selected as a INC. Note that INC doesn't
16593 // set CF, so we can't do this for UADDO.
16594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16596 BaseOp = X86ISD::INC;
16597 Cond = X86::COND_O;
16600 BaseOp = X86ISD::ADD;
16601 Cond = X86::COND_O;
16604 BaseOp = X86ISD::ADD;
16605 Cond = X86::COND_B;
16608 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16609 // set CF, so we can't do this for USUBO.
16610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16612 BaseOp = X86ISD::DEC;
16613 Cond = X86::COND_O;
16616 BaseOp = X86ISD::SUB;
16617 Cond = X86::COND_O;
16620 BaseOp = X86ISD::SUB;
16621 Cond = X86::COND_B;
16624 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16625 Cond = X86::COND_O;
16627 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16628 if (N->getValueType(0) == MVT::i8) {
16629 BaseOp = X86ISD::UMUL8;
16630 Cond = X86::COND_O;
16633 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16635 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16638 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16639 DAG.getConstant(X86::COND_O, MVT::i32),
16640 SDValue(Sum.getNode(), 2));
16642 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16646 // Also sets EFLAGS.
16647 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16648 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16651 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16652 DAG.getConstant(Cond, MVT::i32),
16653 SDValue(Sum.getNode(), 1));
16655 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16658 /// Returns true if the operand type is exactly twice the native width, and
16659 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16660 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16661 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16662 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16663 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16666 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16667 else if (OpWidth == 128)
16668 return Subtarget->hasCmpxchg16b();
16673 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16674 return needsCmpXchgNb(SI->getValueOperand()->getType());
16677 // Note: this turns large loads into lock cmpxchg8b/16b.
16678 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16679 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16680 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16681 return needsCmpXchgNb(PTy->getElementType());
16684 TargetLoweringBase::AtomicRMWExpansionKind
16685 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16686 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16687 const Type *MemType = AI->getType();
16689 // If the operand is too big, we must see if cmpxchg8/16b is available
16690 // and default to library calls otherwise.
16691 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
16692 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
16693 : AtomicRMWExpansionKind::None;
16696 AtomicRMWInst::BinOp Op = AI->getOperation();
16699 llvm_unreachable("Unknown atomic operation");
16700 case AtomicRMWInst::Xchg:
16701 case AtomicRMWInst::Add:
16702 case AtomicRMWInst::Sub:
16703 // It's better to use xadd, xsub or xchg for these in all cases.
16704 return AtomicRMWExpansionKind::None;
16705 case AtomicRMWInst::Or:
16706 case AtomicRMWInst::And:
16707 case AtomicRMWInst::Xor:
16708 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16709 // prefix to a normal instruction for these operations.
16710 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
16711 : AtomicRMWExpansionKind::None;
16712 case AtomicRMWInst::Nand:
16713 case AtomicRMWInst::Max:
16714 case AtomicRMWInst::Min:
16715 case AtomicRMWInst::UMax:
16716 case AtomicRMWInst::UMin:
16717 // These always require a non-trivial set of data operations on x86. We must
16718 // use a cmpxchg loop.
16719 return AtomicRMWExpansionKind::CmpXChg;
16723 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16724 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16725 // no-sse2). There isn't any reason to disable it if the target processor
16727 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16731 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16732 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16733 const Type *MemType = AI->getType();
16734 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16735 // there is no benefit in turning such RMWs into loads, and it is actually
16736 // harmful as it introduces a mfence.
16737 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16740 auto Builder = IRBuilder<>(AI);
16741 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16742 auto SynchScope = AI->getSynchScope();
16743 // We must restrict the ordering to avoid generating loads with Release or
16744 // ReleaseAcquire orderings.
16745 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16746 auto Ptr = AI->getPointerOperand();
16748 // Before the load we need a fence. Here is an example lifted from
16749 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16752 // x.store(1, relaxed);
16753 // r1 = y.fetch_add(0, release);
16755 // y.fetch_add(42, acquire);
16756 // r2 = x.load(relaxed);
16757 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16758 // lowered to just a load without a fence. A mfence flushes the store buffer,
16759 // making the optimization clearly correct.
16760 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16761 // otherwise, we might be able to be more agressive on relaxed idempotent
16762 // rmw. In practice, they do not look useful, so we don't try to be
16763 // especially clever.
16764 if (SynchScope == SingleThread) {
16765 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16766 // the IR level, so we must wrap it in an intrinsic.
16768 } else if (hasMFENCE(*Subtarget)) {
16769 Function *MFence = llvm::Intrinsic::getDeclaration(M,
16770 Intrinsic::x86_sse2_mfence);
16771 Builder.CreateCall(MFence);
16773 // FIXME: it might make sense to use a locked operation here but on a
16774 // different cache-line to prevent cache-line bouncing. In practice it
16775 // is probably a small win, and x86 processors without mfence are rare
16776 // enough that we do not bother.
16780 // Finally we can emit the atomic load.
16781 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
16782 AI->getType()->getPrimitiveSizeInBits());
16783 Loaded->setAtomic(Order, SynchScope);
16784 AI->replaceAllUsesWith(Loaded);
16785 AI->eraseFromParent();
16789 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16790 SelectionDAG &DAG) {
16792 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16793 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16794 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16795 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16797 // The only fence that needs an instruction is a sequentially-consistent
16798 // cross-thread fence.
16799 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16800 if (hasMFENCE(*Subtarget))
16801 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16803 SDValue Chain = Op.getOperand(0);
16804 SDValue Zero = DAG.getConstant(0, MVT::i32);
16806 DAG.getRegister(X86::ESP, MVT::i32), // Base
16807 DAG.getTargetConstant(1, MVT::i8), // Scale
16808 DAG.getRegister(0, MVT::i32), // Index
16809 DAG.getTargetConstant(0, MVT::i32), // Disp
16810 DAG.getRegister(0, MVT::i32), // Segment.
16814 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16815 return SDValue(Res, 0);
16818 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16819 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16822 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16823 SelectionDAG &DAG) {
16824 MVT T = Op.getSimpleValueType();
16828 switch(T.SimpleTy) {
16829 default: llvm_unreachable("Invalid value type!");
16830 case MVT::i8: Reg = X86::AL; size = 1; break;
16831 case MVT::i16: Reg = X86::AX; size = 2; break;
16832 case MVT::i32: Reg = X86::EAX; size = 4; break;
16834 assert(Subtarget->is64Bit() && "Node not type legal!");
16835 Reg = X86::RAX; size = 8;
16838 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16839 Op.getOperand(2), SDValue());
16840 SDValue Ops[] = { cpIn.getValue(0),
16843 DAG.getTargetConstant(size, MVT::i8),
16844 cpIn.getValue(1) };
16845 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16846 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16847 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16851 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16852 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16853 MVT::i32, cpOut.getValue(2));
16854 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16855 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16857 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16858 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16859 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16863 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16864 SelectionDAG &DAG) {
16865 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16866 MVT DstVT = Op.getSimpleValueType();
16868 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16869 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16870 if (DstVT != MVT::f64)
16871 // This conversion needs to be expanded.
16874 SDValue InVec = Op->getOperand(0);
16876 unsigned NumElts = SrcVT.getVectorNumElements();
16877 EVT SVT = SrcVT.getVectorElementType();
16879 // Widen the vector in input in the case of MVT::v2i32.
16880 // Example: from MVT::v2i32 to MVT::v4i32.
16881 SmallVector<SDValue, 16> Elts;
16882 for (unsigned i = 0, e = NumElts; i != e; ++i)
16883 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16884 DAG.getIntPtrConstant(i)));
16886 // Explicitly mark the extra elements as Undef.
16887 Elts.append(NumElts, DAG.getUNDEF(SVT));
16889 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16890 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16891 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16892 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16893 DAG.getIntPtrConstant(0));
16896 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16897 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16898 assert((DstVT == MVT::i64 ||
16899 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16900 "Unexpected custom BITCAST");
16901 // i64 <=> MMX conversions are Legal.
16902 if (SrcVT==MVT::i64 && DstVT.isVector())
16904 if (DstVT==MVT::i64 && SrcVT.isVector())
16906 // MMX <=> MMX conversions are Legal.
16907 if (SrcVT.isVector() && DstVT.isVector())
16909 // All other conversions need to be expanded.
16913 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
16914 SelectionDAG &DAG) {
16915 SDNode *Node = Op.getNode();
16918 Op = Op.getOperand(0);
16919 EVT VT = Op.getValueType();
16920 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16921 "CTPOP lowering only implemented for 128/256-bit wide vector types");
16923 unsigned NumElts = VT.getVectorNumElements();
16924 EVT EltVT = VT.getVectorElementType();
16925 unsigned Len = EltVT.getSizeInBits();
16927 // This is the vectorized version of the "best" algorithm from
16928 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
16929 // with a minor tweak to use a series of adds + shifts instead of vector
16930 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
16932 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
16933 // v8i32 => Always profitable
16935 // FIXME: There a couple of possible improvements:
16937 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
16938 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
16940 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
16941 "CTPOP not implemented for this vector element type.");
16943 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
16944 // extra legalization.
16945 bool NeedsBitcast = EltVT == MVT::i32;
16946 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
16948 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
16949 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
16950 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
16952 // v = v - ((v >> 1) & 0x55555555...)
16953 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
16954 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
16955 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
16957 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16959 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
16960 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
16962 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
16964 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
16965 if (VT != And.getValueType())
16966 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16967 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
16969 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
16970 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
16971 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
16972 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
16973 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
16975 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
16976 if (NeedsBitcast) {
16977 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16978 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
16979 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
16982 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
16983 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
16984 if (VT != AndRHS.getValueType()) {
16985 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
16986 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
16988 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
16990 // v = (v + (v >> 4)) & 0x0F0F0F0F...
16991 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
16992 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
16993 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
16994 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
16996 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
16997 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
16998 if (NeedsBitcast) {
16999 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17000 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
17002 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
17003 if (VT != And.getValueType())
17004 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17006 // The algorithm mentioned above uses:
17007 // v = (v * 0x01010101...) >> (Len - 8)
17009 // Change it to use vector adds + vector shifts which yield faster results on
17010 // Haswell than using vector integer multiplication.
17012 // For i32 elements:
17013 // v = v + (v >> 8)
17014 // v = v + (v >> 16)
17016 // For i64 elements:
17017 // v = v + (v >> 8)
17018 // v = v + (v >> 16)
17019 // v = v + (v >> 32)
17022 SmallVector<SDValue, 8> Csts;
17023 for (unsigned i = 8; i <= Len/2; i *= 2) {
17024 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
17025 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
17026 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
17027 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17031 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
17032 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
17033 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
17034 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
17035 if (NeedsBitcast) {
17036 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17037 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
17039 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
17040 if (VT != And.getValueType())
17041 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17046 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17047 SDNode *Node = Op.getNode();
17049 EVT T = Node->getValueType(0);
17050 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17051 DAG.getConstant(0, T), Node->getOperand(2));
17052 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17053 cast<AtomicSDNode>(Node)->getMemoryVT(),
17054 Node->getOperand(0),
17055 Node->getOperand(1), negOp,
17056 cast<AtomicSDNode>(Node)->getMemOperand(),
17057 cast<AtomicSDNode>(Node)->getOrdering(),
17058 cast<AtomicSDNode>(Node)->getSynchScope());
17061 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17062 SDNode *Node = Op.getNode();
17064 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17066 // Convert seq_cst store -> xchg
17067 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17068 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17069 // (The only way to get a 16-byte store is cmpxchg16b)
17070 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17071 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17072 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17073 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17074 cast<AtomicSDNode>(Node)->getMemoryVT(),
17075 Node->getOperand(0),
17076 Node->getOperand(1), Node->getOperand(2),
17077 cast<AtomicSDNode>(Node)->getMemOperand(),
17078 cast<AtomicSDNode>(Node)->getOrdering(),
17079 cast<AtomicSDNode>(Node)->getSynchScope());
17080 return Swap.getValue(1);
17082 // Other atomic stores have a simple pattern.
17086 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17087 EVT VT = Op.getNode()->getSimpleValueType(0);
17089 // Let legalize expand this if it isn't a legal type yet.
17090 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17093 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17096 bool ExtraOp = false;
17097 switch (Op.getOpcode()) {
17098 default: llvm_unreachable("Invalid code");
17099 case ISD::ADDC: Opc = X86ISD::ADD; break;
17100 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17101 case ISD::SUBC: Opc = X86ISD::SUB; break;
17102 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17106 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17108 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17109 Op.getOperand(1), Op.getOperand(2));
17112 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17113 SelectionDAG &DAG) {
17114 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17116 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17117 // which returns the values as { float, float } (in XMM0) or
17118 // { double, double } (which is returned in XMM0, XMM1).
17120 SDValue Arg = Op.getOperand(0);
17121 EVT ArgVT = Arg.getValueType();
17122 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17124 TargetLowering::ArgListTy Args;
17125 TargetLowering::ArgListEntry Entry;
17129 Entry.isSExt = false;
17130 Entry.isZExt = false;
17131 Args.push_back(Entry);
17133 bool isF64 = ArgVT == MVT::f64;
17134 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17135 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17136 // the results are returned via SRet in memory.
17137 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17139 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17141 Type *RetTy = isF64
17142 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17143 : (Type*)VectorType::get(ArgTy, 4);
17145 TargetLowering::CallLoweringInfo CLI(DAG);
17146 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17147 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17149 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17152 // Returned in xmm0 and xmm1.
17153 return CallResult.first;
17155 // Returned in bits 0:31 and 32:64 xmm0.
17156 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17157 CallResult.first, DAG.getIntPtrConstant(0));
17158 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17159 CallResult.first, DAG.getIntPtrConstant(1));
17160 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17161 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17164 /// LowerOperation - Provide custom lowering hooks for some operations.
17166 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17167 switch (Op.getOpcode()) {
17168 default: llvm_unreachable("Should not custom lower this!");
17169 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17170 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17171 return LowerCMP_SWAP(Op, Subtarget, DAG);
17172 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17173 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17174 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17175 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17176 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17177 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17178 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17179 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17180 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17181 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17182 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17183 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17184 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17185 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17186 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17187 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17188 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17189 case ISD::SHL_PARTS:
17190 case ISD::SRA_PARTS:
17191 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17192 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17193 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17194 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17195 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17196 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17197 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17198 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17199 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17200 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17201 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17203 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17204 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17205 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17206 case ISD::SETCC: return LowerSETCC(Op, DAG);
17207 case ISD::SELECT: return LowerSELECT(Op, DAG);
17208 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17209 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17210 case ISD::VASTART: return LowerVASTART(Op, DAG);
17211 case ISD::VAARG: return LowerVAARG(Op, DAG);
17212 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17213 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17214 case ISD::INTRINSIC_VOID:
17215 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17216 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17217 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17218 case ISD::FRAME_TO_ARGS_OFFSET:
17219 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17220 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17221 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17222 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17223 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17224 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17225 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17226 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17227 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17228 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17229 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17230 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17231 case ISD::UMUL_LOHI:
17232 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17235 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17241 case ISD::UMULO: return LowerXALUO(Op, DAG);
17242 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17243 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17247 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17248 case ISD::ADD: return LowerADD(Op, DAG);
17249 case ISD::SUB: return LowerSUB(Op, DAG);
17250 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17254 /// ReplaceNodeResults - Replace a node with an illegal result type
17255 /// with a new node built out of custom code.
17256 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17257 SmallVectorImpl<SDValue>&Results,
17258 SelectionDAG &DAG) const {
17260 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17261 switch (N->getOpcode()) {
17263 llvm_unreachable("Do not know how to custom type legalize this operation!");
17264 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17265 case X86ISD::FMINC:
17267 case X86ISD::FMAXC:
17268 case X86ISD::FMAX: {
17269 EVT VT = N->getValueType(0);
17270 if (VT != MVT::v2f32)
17271 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17272 SDValue UNDEF = DAG.getUNDEF(VT);
17273 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17274 N->getOperand(0), UNDEF);
17275 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17276 N->getOperand(1), UNDEF);
17277 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17280 case ISD::SIGN_EXTEND_INREG:
17285 // We don't want to expand or promote these.
17292 case ISD::UDIVREM: {
17293 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17294 Results.push_back(V);
17297 case ISD::FP_TO_SINT:
17298 case ISD::FP_TO_UINT: {
17299 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17301 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17304 std::pair<SDValue,SDValue> Vals =
17305 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17306 SDValue FIST = Vals.first, StackSlot = Vals.second;
17307 if (FIST.getNode()) {
17308 EVT VT = N->getValueType(0);
17309 // Return a load from the stack slot.
17310 if (StackSlot.getNode())
17311 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17312 MachinePointerInfo(),
17313 false, false, false, 0));
17315 Results.push_back(FIST);
17319 case ISD::UINT_TO_FP: {
17320 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17321 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17322 N->getValueType(0) != MVT::v2f32)
17324 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17326 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17328 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17329 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17330 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17331 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17332 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17333 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17336 case ISD::FP_ROUND: {
17337 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17339 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17340 Results.push_back(V);
17343 case ISD::INTRINSIC_W_CHAIN: {
17344 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17346 default : llvm_unreachable("Do not know how to custom type "
17347 "legalize this intrinsic operation!");
17348 case Intrinsic::x86_rdtsc:
17349 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17351 case Intrinsic::x86_rdtscp:
17352 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17354 case Intrinsic::x86_rdpmc:
17355 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17358 case ISD::READCYCLECOUNTER: {
17359 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17362 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17363 EVT T = N->getValueType(0);
17364 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17365 bool Regs64bit = T == MVT::i128;
17366 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17367 SDValue cpInL, cpInH;
17368 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17369 DAG.getConstant(0, HalfT));
17370 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17371 DAG.getConstant(1, HalfT));
17372 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17373 Regs64bit ? X86::RAX : X86::EAX,
17375 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17376 Regs64bit ? X86::RDX : X86::EDX,
17377 cpInH, cpInL.getValue(1));
17378 SDValue swapInL, swapInH;
17379 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17380 DAG.getConstant(0, HalfT));
17381 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17382 DAG.getConstant(1, HalfT));
17383 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17384 Regs64bit ? X86::RBX : X86::EBX,
17385 swapInL, cpInH.getValue(1));
17386 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17387 Regs64bit ? X86::RCX : X86::ECX,
17388 swapInH, swapInL.getValue(1));
17389 SDValue Ops[] = { swapInH.getValue(0),
17391 swapInH.getValue(1) };
17392 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17393 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17394 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17395 X86ISD::LCMPXCHG8_DAG;
17396 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17397 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17398 Regs64bit ? X86::RAX : X86::EAX,
17399 HalfT, Result.getValue(1));
17400 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17401 Regs64bit ? X86::RDX : X86::EDX,
17402 HalfT, cpOutL.getValue(2));
17403 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17405 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17406 MVT::i32, cpOutH.getValue(2));
17408 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17409 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17410 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17412 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17413 Results.push_back(Success);
17414 Results.push_back(EFLAGS.getValue(1));
17417 case ISD::ATOMIC_SWAP:
17418 case ISD::ATOMIC_LOAD_ADD:
17419 case ISD::ATOMIC_LOAD_SUB:
17420 case ISD::ATOMIC_LOAD_AND:
17421 case ISD::ATOMIC_LOAD_OR:
17422 case ISD::ATOMIC_LOAD_XOR:
17423 case ISD::ATOMIC_LOAD_NAND:
17424 case ISD::ATOMIC_LOAD_MIN:
17425 case ISD::ATOMIC_LOAD_MAX:
17426 case ISD::ATOMIC_LOAD_UMIN:
17427 case ISD::ATOMIC_LOAD_UMAX:
17428 case ISD::ATOMIC_LOAD: {
17429 // Delegate to generic TypeLegalization. Situations we can really handle
17430 // should have already been dealt with by AtomicExpandPass.cpp.
17433 case ISD::BITCAST: {
17434 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17435 EVT DstVT = N->getValueType(0);
17436 EVT SrcVT = N->getOperand(0)->getValueType(0);
17438 if (SrcVT != MVT::f64 ||
17439 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17442 unsigned NumElts = DstVT.getVectorNumElements();
17443 EVT SVT = DstVT.getVectorElementType();
17444 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17445 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17446 MVT::v2f64, N->getOperand(0));
17447 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17449 if (ExperimentalVectorWideningLegalization) {
17450 // If we are legalizing vectors by widening, we already have the desired
17451 // legal vector type, just return it.
17452 Results.push_back(ToVecInt);
17456 SmallVector<SDValue, 8> Elts;
17457 for (unsigned i = 0, e = NumElts; i != e; ++i)
17458 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17459 ToVecInt, DAG.getIntPtrConstant(i)));
17461 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17466 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17468 default: return nullptr;
17469 case X86ISD::BSF: return "X86ISD::BSF";
17470 case X86ISD::BSR: return "X86ISD::BSR";
17471 case X86ISD::SHLD: return "X86ISD::SHLD";
17472 case X86ISD::SHRD: return "X86ISD::SHRD";
17473 case X86ISD::FAND: return "X86ISD::FAND";
17474 case X86ISD::FANDN: return "X86ISD::FANDN";
17475 case X86ISD::FOR: return "X86ISD::FOR";
17476 case X86ISD::FXOR: return "X86ISD::FXOR";
17477 case X86ISD::FSRL: return "X86ISD::FSRL";
17478 case X86ISD::FILD: return "X86ISD::FILD";
17479 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17480 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17481 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17482 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17483 case X86ISD::FLD: return "X86ISD::FLD";
17484 case X86ISD::FST: return "X86ISD::FST";
17485 case X86ISD::CALL: return "X86ISD::CALL";
17486 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17487 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17488 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17489 case X86ISD::BT: return "X86ISD::BT";
17490 case X86ISD::CMP: return "X86ISD::CMP";
17491 case X86ISD::COMI: return "X86ISD::COMI";
17492 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17493 case X86ISD::CMPM: return "X86ISD::CMPM";
17494 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17495 case X86ISD::SETCC: return "X86ISD::SETCC";
17496 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17497 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17498 case X86ISD::CMOV: return "X86ISD::CMOV";
17499 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17500 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17501 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17502 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17503 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17504 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17505 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17506 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17507 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17508 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17509 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17510 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17511 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17512 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17513 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17514 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17515 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17516 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17517 case X86ISD::HADD: return "X86ISD::HADD";
17518 case X86ISD::HSUB: return "X86ISD::HSUB";
17519 case X86ISD::FHADD: return "X86ISD::FHADD";
17520 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17521 case X86ISD::UMAX: return "X86ISD::UMAX";
17522 case X86ISD::UMIN: return "X86ISD::UMIN";
17523 case X86ISD::SMAX: return "X86ISD::SMAX";
17524 case X86ISD::SMIN: return "X86ISD::SMIN";
17525 case X86ISD::FMAX: return "X86ISD::FMAX";
17526 case X86ISD::FMIN: return "X86ISD::FMIN";
17527 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17528 case X86ISD::FMINC: return "X86ISD::FMINC";
17529 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17530 case X86ISD::FRCP: return "X86ISD::FRCP";
17531 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17532 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17533 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17534 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17535 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17536 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17537 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17538 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17539 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17540 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17541 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17542 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17543 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17544 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17545 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17546 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17547 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17548 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17549 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17550 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17551 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17552 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17553 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17554 case X86ISD::VSHL: return "X86ISD::VSHL";
17555 case X86ISD::VSRL: return "X86ISD::VSRL";
17556 case X86ISD::VSRA: return "X86ISD::VSRA";
17557 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17558 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17559 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17560 case X86ISD::CMPP: return "X86ISD::CMPP";
17561 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17562 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17563 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17564 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17565 case X86ISD::ADD: return "X86ISD::ADD";
17566 case X86ISD::SUB: return "X86ISD::SUB";
17567 case X86ISD::ADC: return "X86ISD::ADC";
17568 case X86ISD::SBB: return "X86ISD::SBB";
17569 case X86ISD::SMUL: return "X86ISD::SMUL";
17570 case X86ISD::UMUL: return "X86ISD::UMUL";
17571 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17572 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17573 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17574 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17575 case X86ISD::INC: return "X86ISD::INC";
17576 case X86ISD::DEC: return "X86ISD::DEC";
17577 case X86ISD::OR: return "X86ISD::OR";
17578 case X86ISD::XOR: return "X86ISD::XOR";
17579 case X86ISD::AND: return "X86ISD::AND";
17580 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17581 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17582 case X86ISD::PTEST: return "X86ISD::PTEST";
17583 case X86ISD::TESTP: return "X86ISD::TESTP";
17584 case X86ISD::TESTM: return "X86ISD::TESTM";
17585 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17586 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17587 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17588 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17589 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17590 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17591 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17592 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17593 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17594 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17595 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17596 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17597 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17598 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17599 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17600 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17601 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17602 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17603 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17604 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17605 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17606 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17607 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17608 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17609 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17610 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17611 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17612 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17613 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17614 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17615 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17616 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17617 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17618 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17619 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17620 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17621 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17622 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17623 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17624 case X86ISD::SAHF: return "X86ISD::SAHF";
17625 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17626 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17627 case X86ISD::FMADD: return "X86ISD::FMADD";
17628 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17629 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17630 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17631 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17632 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17633 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17634 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17635 case X86ISD::XTEST: return "X86ISD::XTEST";
17636 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17637 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17638 case X86ISD::SELECT: return "X86ISD::SELECT";
17639 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17640 case X86ISD::RCP28: return "X86ISD::RCP28";
17641 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17642 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17643 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17644 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17645 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17649 // isLegalAddressingMode - Return true if the addressing mode represented
17650 // by AM is legal for this target, for a load/store of the specified type.
17651 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17653 // X86 supports extremely general addressing modes.
17654 CodeModel::Model M = getTargetMachine().getCodeModel();
17655 Reloc::Model R = getTargetMachine().getRelocationModel();
17657 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17658 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17663 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17665 // If a reference to this global requires an extra load, we can't fold it.
17666 if (isGlobalStubReference(GVFlags))
17669 // If BaseGV requires a register for the PIC base, we cannot also have a
17670 // BaseReg specified.
17671 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17674 // If lower 4G is not available, then we must use rip-relative addressing.
17675 if ((M != CodeModel::Small || R != Reloc::Static) &&
17676 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17680 switch (AM.Scale) {
17686 // These scales always work.
17691 // These scales are formed with basereg+scalereg. Only accept if there is
17696 default: // Other stuff never works.
17703 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17704 unsigned Bits = Ty->getScalarSizeInBits();
17706 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17707 // particularly cheaper than those without.
17711 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17712 // variable shifts just as cheap as scalar ones.
17713 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17716 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17717 // fully general vector.
17721 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17722 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17724 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17725 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17726 return NumBits1 > NumBits2;
17729 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17730 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17733 if (!isTypeLegal(EVT::getEVT(Ty1)))
17736 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17738 // Assuming the caller doesn't have a zeroext or signext return parameter,
17739 // truncation all the way down to i1 is valid.
17743 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17744 return isInt<32>(Imm);
17747 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17748 // Can also use sub to handle negated immediates.
17749 return isInt<32>(Imm);
17752 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17753 if (!VT1.isInteger() || !VT2.isInteger())
17755 unsigned NumBits1 = VT1.getSizeInBits();
17756 unsigned NumBits2 = VT2.getSizeInBits();
17757 return NumBits1 > NumBits2;
17760 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17761 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17762 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17765 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17766 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17767 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17770 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17771 EVT VT1 = Val.getValueType();
17772 if (isZExtFree(VT1, VT2))
17775 if (Val.getOpcode() != ISD::LOAD)
17778 if (!VT1.isSimple() || !VT1.isInteger() ||
17779 !VT2.isSimple() || !VT2.isInteger())
17782 switch (VT1.getSimpleVT().SimpleTy) {
17787 // X86 has 8, 16, and 32-bit zero-extending loads.
17794 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
17797 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17798 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17801 VT = VT.getScalarType();
17803 if (!VT.isSimple())
17806 switch (VT.getSimpleVT().SimpleTy) {
17817 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17818 // i16 instructions are longer (0x66 prefix) and potentially slower.
17819 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17822 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17823 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17824 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17825 /// are assumed to be legal.
17827 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17829 if (!VT.isSimple())
17832 // Very little shuffling can be done for 64-bit vectors right now.
17833 if (VT.getSizeInBits() == 64)
17836 // We only care that the types being shuffled are legal. The lowering can
17837 // handle any possible shuffle mask that results.
17838 return isTypeLegal(VT.getSimpleVT());
17842 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17844 // Just delegate to the generic legality, clear masks aren't special.
17845 return isShuffleMaskLegal(Mask, VT);
17848 //===----------------------------------------------------------------------===//
17849 // X86 Scheduler Hooks
17850 //===----------------------------------------------------------------------===//
17852 /// Utility function to emit xbegin specifying the start of an RTM region.
17853 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17854 const TargetInstrInfo *TII) {
17855 DebugLoc DL = MI->getDebugLoc();
17857 const BasicBlock *BB = MBB->getBasicBlock();
17858 MachineFunction::iterator I = MBB;
17861 // For the v = xbegin(), we generate
17872 MachineBasicBlock *thisMBB = MBB;
17873 MachineFunction *MF = MBB->getParent();
17874 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17875 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17876 MF->insert(I, mainMBB);
17877 MF->insert(I, sinkMBB);
17879 // Transfer the remainder of BB and its successor edges to sinkMBB.
17880 sinkMBB->splice(sinkMBB->begin(), MBB,
17881 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17882 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17886 // # fallthrough to mainMBB
17887 // # abortion to sinkMBB
17888 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17889 thisMBB->addSuccessor(mainMBB);
17890 thisMBB->addSuccessor(sinkMBB);
17894 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17895 mainMBB->addSuccessor(sinkMBB);
17898 // EAX is live into the sinkMBB
17899 sinkMBB->addLiveIn(X86::EAX);
17900 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17901 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17904 MI->eraseFromParent();
17908 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17909 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17910 // in the .td file.
17911 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17912 const TargetInstrInfo *TII) {
17914 switch (MI->getOpcode()) {
17915 default: llvm_unreachable("illegal opcode!");
17916 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17917 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17918 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17919 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17920 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17921 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17922 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17923 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17926 DebugLoc dl = MI->getDebugLoc();
17927 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17929 unsigned NumArgs = MI->getNumOperands();
17930 for (unsigned i = 1; i < NumArgs; ++i) {
17931 MachineOperand &Op = MI->getOperand(i);
17932 if (!(Op.isReg() && Op.isImplicit()))
17933 MIB.addOperand(Op);
17935 if (MI->hasOneMemOperand())
17936 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17938 BuildMI(*BB, MI, dl,
17939 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17940 .addReg(X86::XMM0);
17942 MI->eraseFromParent();
17946 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17947 // defs in an instruction pattern
17948 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17949 const TargetInstrInfo *TII) {
17951 switch (MI->getOpcode()) {
17952 default: llvm_unreachable("illegal opcode!");
17953 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17954 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17955 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17956 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17957 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17958 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17959 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17960 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17963 DebugLoc dl = MI->getDebugLoc();
17964 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17966 unsigned NumArgs = MI->getNumOperands(); // remove the results
17967 for (unsigned i = 1; i < NumArgs; ++i) {
17968 MachineOperand &Op = MI->getOperand(i);
17969 if (!(Op.isReg() && Op.isImplicit()))
17970 MIB.addOperand(Op);
17972 if (MI->hasOneMemOperand())
17973 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17975 BuildMI(*BB, MI, dl,
17976 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17979 MI->eraseFromParent();
17983 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17984 const X86Subtarget *Subtarget) {
17985 DebugLoc dl = MI->getDebugLoc();
17986 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
17987 // Address into RAX/EAX, other two args into ECX, EDX.
17988 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17989 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17990 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17991 for (int i = 0; i < X86::AddrNumOperands; ++i)
17992 MIB.addOperand(MI->getOperand(i));
17994 unsigned ValOps = X86::AddrNumOperands;
17995 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17996 .addReg(MI->getOperand(ValOps).getReg());
17997 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17998 .addReg(MI->getOperand(ValOps+1).getReg());
18000 // The instruction doesn't actually take any operands though.
18001 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18003 MI->eraseFromParent(); // The pseudo is gone now.
18007 MachineBasicBlock *
18008 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18009 MachineBasicBlock *MBB) const {
18010 // Emit va_arg instruction on X86-64.
18012 // Operands to this pseudo-instruction:
18013 // 0 ) Output : destination address (reg)
18014 // 1-5) Input : va_list address (addr, i64mem)
18015 // 6 ) ArgSize : Size (in bytes) of vararg type
18016 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18017 // 8 ) Align : Alignment of type
18018 // 9 ) EFLAGS (implicit-def)
18020 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18021 static_assert(X86::AddrNumOperands == 5,
18022 "VAARG_64 assumes 5 address operands");
18024 unsigned DestReg = MI->getOperand(0).getReg();
18025 MachineOperand &Base = MI->getOperand(1);
18026 MachineOperand &Scale = MI->getOperand(2);
18027 MachineOperand &Index = MI->getOperand(3);
18028 MachineOperand &Disp = MI->getOperand(4);
18029 MachineOperand &Segment = MI->getOperand(5);
18030 unsigned ArgSize = MI->getOperand(6).getImm();
18031 unsigned ArgMode = MI->getOperand(7).getImm();
18032 unsigned Align = MI->getOperand(8).getImm();
18034 // Memory Reference
18035 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18036 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18037 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18039 // Machine Information
18040 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18041 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18042 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18043 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18044 DebugLoc DL = MI->getDebugLoc();
18046 // struct va_list {
18049 // i64 overflow_area (address)
18050 // i64 reg_save_area (address)
18052 // sizeof(va_list) = 24
18053 // alignment(va_list) = 8
18055 unsigned TotalNumIntRegs = 6;
18056 unsigned TotalNumXMMRegs = 8;
18057 bool UseGPOffset = (ArgMode == 1);
18058 bool UseFPOffset = (ArgMode == 2);
18059 unsigned MaxOffset = TotalNumIntRegs * 8 +
18060 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18062 /* Align ArgSize to a multiple of 8 */
18063 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18064 bool NeedsAlign = (Align > 8);
18066 MachineBasicBlock *thisMBB = MBB;
18067 MachineBasicBlock *overflowMBB;
18068 MachineBasicBlock *offsetMBB;
18069 MachineBasicBlock *endMBB;
18071 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18072 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18073 unsigned OffsetReg = 0;
18075 if (!UseGPOffset && !UseFPOffset) {
18076 // If we only pull from the overflow region, we don't create a branch.
18077 // We don't need to alter control flow.
18078 OffsetDestReg = 0; // unused
18079 OverflowDestReg = DestReg;
18081 offsetMBB = nullptr;
18082 overflowMBB = thisMBB;
18085 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18086 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18087 // If not, pull from overflow_area. (branch to overflowMBB)
18092 // offsetMBB overflowMBB
18097 // Registers for the PHI in endMBB
18098 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18099 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18101 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18102 MachineFunction *MF = MBB->getParent();
18103 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18104 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18105 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18107 MachineFunction::iterator MBBIter = MBB;
18110 // Insert the new basic blocks
18111 MF->insert(MBBIter, offsetMBB);
18112 MF->insert(MBBIter, overflowMBB);
18113 MF->insert(MBBIter, endMBB);
18115 // Transfer the remainder of MBB and its successor edges to endMBB.
18116 endMBB->splice(endMBB->begin(), thisMBB,
18117 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18118 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18120 // Make offsetMBB and overflowMBB successors of thisMBB
18121 thisMBB->addSuccessor(offsetMBB);
18122 thisMBB->addSuccessor(overflowMBB);
18124 // endMBB is a successor of both offsetMBB and overflowMBB
18125 offsetMBB->addSuccessor(endMBB);
18126 overflowMBB->addSuccessor(endMBB);
18128 // Load the offset value into a register
18129 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18130 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18134 .addDisp(Disp, UseFPOffset ? 4 : 0)
18135 .addOperand(Segment)
18136 .setMemRefs(MMOBegin, MMOEnd);
18138 // Check if there is enough room left to pull this argument.
18139 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18141 .addImm(MaxOffset + 8 - ArgSizeA8);
18143 // Branch to "overflowMBB" if offset >= max
18144 // Fall through to "offsetMBB" otherwise
18145 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18146 .addMBB(overflowMBB);
18149 // In offsetMBB, emit code to use the reg_save_area.
18151 assert(OffsetReg != 0);
18153 // Read the reg_save_area address.
18154 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18155 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18160 .addOperand(Segment)
18161 .setMemRefs(MMOBegin, MMOEnd);
18163 // Zero-extend the offset
18164 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18165 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18168 .addImm(X86::sub_32bit);
18170 // Add the offset to the reg_save_area to get the final address.
18171 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18172 .addReg(OffsetReg64)
18173 .addReg(RegSaveReg);
18175 // Compute the offset for the next argument
18176 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18177 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18179 .addImm(UseFPOffset ? 16 : 8);
18181 // Store it back into the va_list.
18182 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18186 .addDisp(Disp, UseFPOffset ? 4 : 0)
18187 .addOperand(Segment)
18188 .addReg(NextOffsetReg)
18189 .setMemRefs(MMOBegin, MMOEnd);
18192 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18197 // Emit code to use overflow area
18200 // Load the overflow_area address into a register.
18201 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18202 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18207 .addOperand(Segment)
18208 .setMemRefs(MMOBegin, MMOEnd);
18210 // If we need to align it, do so. Otherwise, just copy the address
18211 // to OverflowDestReg.
18213 // Align the overflow address
18214 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18215 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18217 // aligned_addr = (addr + (align-1)) & ~(align-1)
18218 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18219 .addReg(OverflowAddrReg)
18222 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18224 .addImm(~(uint64_t)(Align-1));
18226 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18227 .addReg(OverflowAddrReg);
18230 // Compute the next overflow address after this argument.
18231 // (the overflow address should be kept 8-byte aligned)
18232 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18233 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18234 .addReg(OverflowDestReg)
18235 .addImm(ArgSizeA8);
18237 // Store the new overflow address.
18238 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18243 .addOperand(Segment)
18244 .addReg(NextAddrReg)
18245 .setMemRefs(MMOBegin, MMOEnd);
18247 // If we branched, emit the PHI to the front of endMBB.
18249 BuildMI(*endMBB, endMBB->begin(), DL,
18250 TII->get(X86::PHI), DestReg)
18251 .addReg(OffsetDestReg).addMBB(offsetMBB)
18252 .addReg(OverflowDestReg).addMBB(overflowMBB);
18255 // Erase the pseudo instruction
18256 MI->eraseFromParent();
18261 MachineBasicBlock *
18262 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18264 MachineBasicBlock *MBB) const {
18265 // Emit code to save XMM registers to the stack. The ABI says that the
18266 // number of registers to save is given in %al, so it's theoretically
18267 // possible to do an indirect jump trick to avoid saving all of them,
18268 // however this code takes a simpler approach and just executes all
18269 // of the stores if %al is non-zero. It's less code, and it's probably
18270 // easier on the hardware branch predictor, and stores aren't all that
18271 // expensive anyway.
18273 // Create the new basic blocks. One block contains all the XMM stores,
18274 // and one block is the final destination regardless of whether any
18275 // stores were performed.
18276 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18277 MachineFunction *F = MBB->getParent();
18278 MachineFunction::iterator MBBIter = MBB;
18280 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18281 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18282 F->insert(MBBIter, XMMSaveMBB);
18283 F->insert(MBBIter, EndMBB);
18285 // Transfer the remainder of MBB and its successor edges to EndMBB.
18286 EndMBB->splice(EndMBB->begin(), MBB,
18287 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18288 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18290 // The original block will now fall through to the XMM save block.
18291 MBB->addSuccessor(XMMSaveMBB);
18292 // The XMMSaveMBB will fall through to the end block.
18293 XMMSaveMBB->addSuccessor(EndMBB);
18295 // Now add the instructions.
18296 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18297 DebugLoc DL = MI->getDebugLoc();
18299 unsigned CountReg = MI->getOperand(0).getReg();
18300 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18301 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18303 if (!Subtarget->isTargetWin64()) {
18304 // If %al is 0, branch around the XMM save block.
18305 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18306 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18307 MBB->addSuccessor(EndMBB);
18310 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18311 // that was just emitted, but clearly shouldn't be "saved".
18312 assert((MI->getNumOperands() <= 3 ||
18313 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18314 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18315 && "Expected last argument to be EFLAGS");
18316 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18317 // In the XMM save block, save all the XMM argument registers.
18318 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18319 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18320 MachineMemOperand *MMO =
18321 F->getMachineMemOperand(
18322 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18323 MachineMemOperand::MOStore,
18324 /*Size=*/16, /*Align=*/16);
18325 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18326 .addFrameIndex(RegSaveFrameIndex)
18327 .addImm(/*Scale=*/1)
18328 .addReg(/*IndexReg=*/0)
18329 .addImm(/*Disp=*/Offset)
18330 .addReg(/*Segment=*/0)
18331 .addReg(MI->getOperand(i).getReg())
18332 .addMemOperand(MMO);
18335 MI->eraseFromParent(); // The pseudo instruction is gone now.
18340 // The EFLAGS operand of SelectItr might be missing a kill marker
18341 // because there were multiple uses of EFLAGS, and ISel didn't know
18342 // which to mark. Figure out whether SelectItr should have had a
18343 // kill marker, and set it if it should. Returns the correct kill
18345 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18346 MachineBasicBlock* BB,
18347 const TargetRegisterInfo* TRI) {
18348 // Scan forward through BB for a use/def of EFLAGS.
18349 MachineBasicBlock::iterator miI(std::next(SelectItr));
18350 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18351 const MachineInstr& mi = *miI;
18352 if (mi.readsRegister(X86::EFLAGS))
18354 if (mi.definesRegister(X86::EFLAGS))
18355 break; // Should have kill-flag - update below.
18358 // If we hit the end of the block, check whether EFLAGS is live into a
18360 if (miI == BB->end()) {
18361 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18362 sEnd = BB->succ_end();
18363 sItr != sEnd; ++sItr) {
18364 MachineBasicBlock* succ = *sItr;
18365 if (succ->isLiveIn(X86::EFLAGS))
18370 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18371 // out. SelectMI should have a kill flag on EFLAGS.
18372 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18376 MachineBasicBlock *
18377 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18378 MachineBasicBlock *BB) const {
18379 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18380 DebugLoc DL = MI->getDebugLoc();
18382 // To "insert" a SELECT_CC instruction, we actually have to insert the
18383 // diamond control-flow pattern. The incoming instruction knows the
18384 // destination vreg to set, the condition code register to branch on, the
18385 // true/false values to select between, and a branch opcode to use.
18386 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18387 MachineFunction::iterator It = BB;
18393 // cmpTY ccX, r1, r2
18395 // fallthrough --> copy0MBB
18396 MachineBasicBlock *thisMBB = BB;
18397 MachineFunction *F = BB->getParent();
18399 // We also lower double CMOVs:
18400 // (CMOV (CMOV F, T, cc1), T, cc2)
18401 // to two successives branches. For that, we look for another CMOV as the
18402 // following instruction.
18404 // Without this, we would add a PHI between the two jumps, which ends up
18405 // creating a few copies all around. For instance, for
18407 // (sitofp (zext (fcmp une)))
18409 // we would generate:
18411 // ucomiss %xmm1, %xmm0
18412 // movss <1.0f>, %xmm0
18413 // movaps %xmm0, %xmm1
18415 // xorps %xmm1, %xmm1
18418 // movaps %xmm1, %xmm0
18422 // because this custom-inserter would have generated:
18434 // A: X = ...; Y = ...
18436 // C: Z = PHI [X, A], [Y, B]
18438 // E: PHI [X, C], [Z, D]
18440 // If we lower both CMOVs in a single step, we can instead generate:
18452 // A: X = ...; Y = ...
18454 // E: PHI [X, A], [X, C], [Y, D]
18456 // Which, in our sitofp/fcmp example, gives us something like:
18458 // ucomiss %xmm1, %xmm0
18459 // movss <1.0f>, %xmm0
18462 // xorps %xmm0, %xmm0
18466 MachineInstr *NextCMOV = nullptr;
18467 MachineBasicBlock::iterator NextMIIt =
18468 std::next(MachineBasicBlock::iterator(MI));
18469 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
18470 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
18471 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
18472 NextCMOV = &*NextMIIt;
18474 MachineBasicBlock *jcc1MBB = nullptr;
18476 // If we have a double CMOV, we lower it to two successive branches to
18477 // the same block. EFLAGS is used by both, so mark it as live in the second.
18479 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
18480 F->insert(It, jcc1MBB);
18481 jcc1MBB->addLiveIn(X86::EFLAGS);
18484 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18485 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18486 F->insert(It, copy0MBB);
18487 F->insert(It, sinkMBB);
18489 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18490 // live into the sink and copy blocks.
18491 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18493 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
18494 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
18495 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
18496 copy0MBB->addLiveIn(X86::EFLAGS);
18497 sinkMBB->addLiveIn(X86::EFLAGS);
18500 // Transfer the remainder of BB and its successor edges to sinkMBB.
18501 sinkMBB->splice(sinkMBB->begin(), BB,
18502 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18503 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18505 // Add the true and fallthrough blocks as its successors.
18507 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
18508 BB->addSuccessor(jcc1MBB);
18510 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
18511 // jump to the sinkMBB.
18512 jcc1MBB->addSuccessor(copy0MBB);
18513 jcc1MBB->addSuccessor(sinkMBB);
18515 BB->addSuccessor(copy0MBB);
18518 // The true block target of the first (or only) branch is always sinkMBB.
18519 BB->addSuccessor(sinkMBB);
18521 // Create the conditional branch instruction.
18523 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18524 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18527 unsigned Opc2 = X86::GetCondBranchFromCond(
18528 (X86::CondCode)NextCMOV->getOperand(3).getImm());
18529 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
18533 // %FalseValue = ...
18534 // # fallthrough to sinkMBB
18535 copy0MBB->addSuccessor(sinkMBB);
18538 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18540 MachineInstrBuilder MIB =
18541 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
18542 MI->getOperand(0).getReg())
18543 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18544 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18546 // If we have a double CMOV, the second Jcc provides the same incoming
18547 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
18549 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
18550 // Copy the PHI result to the register defined by the second CMOV.
18551 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
18552 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
18553 .addReg(MI->getOperand(0).getReg());
18554 NextCMOV->eraseFromParent();
18557 MI->eraseFromParent(); // The pseudo instruction is gone now.
18561 MachineBasicBlock *
18562 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18563 MachineBasicBlock *BB) const {
18564 MachineFunction *MF = BB->getParent();
18565 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18566 DebugLoc DL = MI->getDebugLoc();
18567 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18569 assert(MF->shouldSplitStack());
18571 const bool Is64Bit = Subtarget->is64Bit();
18572 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18574 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18575 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18578 // ... [Till the alloca]
18579 // If stacklet is not large enough, jump to mallocMBB
18582 // Allocate by subtracting from RSP
18583 // Jump to continueMBB
18586 // Allocate by call to runtime
18590 // [rest of original BB]
18593 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18594 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18595 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18597 MachineRegisterInfo &MRI = MF->getRegInfo();
18598 const TargetRegisterClass *AddrRegClass =
18599 getRegClassFor(getPointerTy());
18601 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18602 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18603 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18604 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18605 sizeVReg = MI->getOperand(1).getReg(),
18606 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18608 MachineFunction::iterator MBBIter = BB;
18611 MF->insert(MBBIter, bumpMBB);
18612 MF->insert(MBBIter, mallocMBB);
18613 MF->insert(MBBIter, continueMBB);
18615 continueMBB->splice(continueMBB->begin(), BB,
18616 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18617 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18619 // Add code to the main basic block to check if the stack limit has been hit,
18620 // and if so, jump to mallocMBB otherwise to bumpMBB.
18621 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18622 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18623 .addReg(tmpSPVReg).addReg(sizeVReg);
18624 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18625 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18626 .addReg(SPLimitVReg);
18627 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18629 // bumpMBB simply decreases the stack pointer, since we know the current
18630 // stacklet has enough space.
18631 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18632 .addReg(SPLimitVReg);
18633 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18634 .addReg(SPLimitVReg);
18635 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18637 // Calls into a routine in libgcc to allocate more space from the heap.
18638 const uint32_t *RegMask =
18639 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
18641 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18643 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18644 .addExternalSymbol("__morestack_allocate_stack_space")
18645 .addRegMask(RegMask)
18646 .addReg(X86::RDI, RegState::Implicit)
18647 .addReg(X86::RAX, RegState::ImplicitDefine);
18648 } else if (Is64Bit) {
18649 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
18651 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18652 .addExternalSymbol("__morestack_allocate_stack_space")
18653 .addRegMask(RegMask)
18654 .addReg(X86::EDI, RegState::Implicit)
18655 .addReg(X86::EAX, RegState::ImplicitDefine);
18657 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18659 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18660 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18661 .addExternalSymbol("__morestack_allocate_stack_space")
18662 .addRegMask(RegMask)
18663 .addReg(X86::EAX, RegState::ImplicitDefine);
18667 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18670 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18671 .addReg(IsLP64 ? X86::RAX : X86::EAX);
18672 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18674 // Set up the CFG correctly.
18675 BB->addSuccessor(bumpMBB);
18676 BB->addSuccessor(mallocMBB);
18677 mallocMBB->addSuccessor(continueMBB);
18678 bumpMBB->addSuccessor(continueMBB);
18680 // Take care of the PHI nodes.
18681 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18682 MI->getOperand(0).getReg())
18683 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18684 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18686 // Delete the original pseudo instruction.
18687 MI->eraseFromParent();
18690 return continueMBB;
18693 MachineBasicBlock *
18694 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18695 MachineBasicBlock *BB) const {
18696 DebugLoc DL = MI->getDebugLoc();
18698 assert(!Subtarget->isTargetMachO());
18700 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
18702 MI->eraseFromParent(); // The pseudo instruction is gone now.
18706 MachineBasicBlock *
18707 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18708 MachineBasicBlock *BB) const {
18709 // This is pretty easy. We're taking the value that we received from
18710 // our load from the relocation, sticking it in either RDI (x86-64)
18711 // or EAX and doing an indirect call. The return value will then
18712 // be in the normal return register.
18713 MachineFunction *F = BB->getParent();
18714 const X86InstrInfo *TII = Subtarget->getInstrInfo();
18715 DebugLoc DL = MI->getDebugLoc();
18717 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18718 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18720 // Get a register mask for the lowered call.
18721 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18722 // proper register mask.
18723 const uint32_t *RegMask =
18724 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
18725 if (Subtarget->is64Bit()) {
18726 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18727 TII->get(X86::MOV64rm), X86::RDI)
18729 .addImm(0).addReg(0)
18730 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18731 MI->getOperand(3).getTargetFlags())
18733 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18734 addDirectMem(MIB, X86::RDI);
18735 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18736 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18737 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18738 TII->get(X86::MOV32rm), X86::EAX)
18740 .addImm(0).addReg(0)
18741 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18742 MI->getOperand(3).getTargetFlags())
18744 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18745 addDirectMem(MIB, X86::EAX);
18746 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18748 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18749 TII->get(X86::MOV32rm), X86::EAX)
18750 .addReg(TII->getGlobalBaseReg(F))
18751 .addImm(0).addReg(0)
18752 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18753 MI->getOperand(3).getTargetFlags())
18755 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18756 addDirectMem(MIB, X86::EAX);
18757 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18760 MI->eraseFromParent(); // The pseudo instruction is gone now.
18764 MachineBasicBlock *
18765 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18766 MachineBasicBlock *MBB) const {
18767 DebugLoc DL = MI->getDebugLoc();
18768 MachineFunction *MF = MBB->getParent();
18769 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18770 MachineRegisterInfo &MRI = MF->getRegInfo();
18772 const BasicBlock *BB = MBB->getBasicBlock();
18773 MachineFunction::iterator I = MBB;
18776 // Memory Reference
18777 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18778 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18781 unsigned MemOpndSlot = 0;
18783 unsigned CurOp = 0;
18785 DstReg = MI->getOperand(CurOp++).getReg();
18786 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18787 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18788 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18789 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18791 MemOpndSlot = CurOp;
18793 MVT PVT = getPointerTy();
18794 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18795 "Invalid Pointer Size!");
18797 // For v = setjmp(buf), we generate
18800 // buf[LabelOffset] = restoreMBB
18801 // SjLjSetup restoreMBB
18807 // v = phi(main, restore)
18810 // if base pointer being used, load it from frame
18813 MachineBasicBlock *thisMBB = MBB;
18814 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18815 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18816 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18817 MF->insert(I, mainMBB);
18818 MF->insert(I, sinkMBB);
18819 MF->push_back(restoreMBB);
18821 MachineInstrBuilder MIB;
18823 // Transfer the remainder of BB and its successor edges to sinkMBB.
18824 sinkMBB->splice(sinkMBB->begin(), MBB,
18825 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18826 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18829 unsigned PtrStoreOpc = 0;
18830 unsigned LabelReg = 0;
18831 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18832 Reloc::Model RM = MF->getTarget().getRelocationModel();
18833 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18834 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18836 // Prepare IP either in reg or imm.
18837 if (!UseImmLabel) {
18838 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18839 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18840 LabelReg = MRI.createVirtualRegister(PtrRC);
18841 if (Subtarget->is64Bit()) {
18842 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18846 .addMBB(restoreMBB)
18849 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18850 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18851 .addReg(XII->getGlobalBaseReg(MF))
18854 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18858 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18860 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18861 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18862 if (i == X86::AddrDisp)
18863 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18865 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18868 MIB.addReg(LabelReg);
18870 MIB.addMBB(restoreMBB);
18871 MIB.setMemRefs(MMOBegin, MMOEnd);
18873 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18874 .addMBB(restoreMBB);
18876 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18877 MIB.addRegMask(RegInfo->getNoPreservedMask());
18878 thisMBB->addSuccessor(mainMBB);
18879 thisMBB->addSuccessor(restoreMBB);
18883 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18884 mainMBB->addSuccessor(sinkMBB);
18887 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18888 TII->get(X86::PHI), DstReg)
18889 .addReg(mainDstReg).addMBB(mainMBB)
18890 .addReg(restoreDstReg).addMBB(restoreMBB);
18893 if (RegInfo->hasBasePointer(*MF)) {
18894 const bool Uses64BitFramePtr =
18895 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
18896 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
18897 X86FI->setRestoreBasePointer(MF);
18898 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
18899 unsigned BasePtr = RegInfo->getBaseRegister();
18900 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
18901 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
18902 FramePtr, true, X86FI->getRestoreBasePointerOffset())
18903 .setMIFlag(MachineInstr::FrameSetup);
18905 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18906 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
18907 restoreMBB->addSuccessor(sinkMBB);
18909 MI->eraseFromParent();
18913 MachineBasicBlock *
18914 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18915 MachineBasicBlock *MBB) const {
18916 DebugLoc DL = MI->getDebugLoc();
18917 MachineFunction *MF = MBB->getParent();
18918 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18919 MachineRegisterInfo &MRI = MF->getRegInfo();
18921 // Memory Reference
18922 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18923 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18925 MVT PVT = getPointerTy();
18926 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18927 "Invalid Pointer Size!");
18929 const TargetRegisterClass *RC =
18930 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18931 unsigned Tmp = MRI.createVirtualRegister(RC);
18932 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18933 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18934 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18935 unsigned SP = RegInfo->getStackRegister();
18937 MachineInstrBuilder MIB;
18939 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18940 const int64_t SPOffset = 2 * PVT.getStoreSize();
18942 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18943 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18946 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18947 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18948 MIB.addOperand(MI->getOperand(i));
18949 MIB.setMemRefs(MMOBegin, MMOEnd);
18951 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18952 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18953 if (i == X86::AddrDisp)
18954 MIB.addDisp(MI->getOperand(i), LabelOffset);
18956 MIB.addOperand(MI->getOperand(i));
18958 MIB.setMemRefs(MMOBegin, MMOEnd);
18960 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18961 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18962 if (i == X86::AddrDisp)
18963 MIB.addDisp(MI->getOperand(i), SPOffset);
18965 MIB.addOperand(MI->getOperand(i));
18967 MIB.setMemRefs(MMOBegin, MMOEnd);
18969 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18971 MI->eraseFromParent();
18975 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18976 // accumulator loops. Writing back to the accumulator allows the coalescer
18977 // to remove extra copies in the loop.
18978 MachineBasicBlock *
18979 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18980 MachineBasicBlock *MBB) const {
18981 MachineOperand &AddendOp = MI->getOperand(3);
18983 // Bail out early if the addend isn't a register - we can't switch these.
18984 if (!AddendOp.isReg())
18987 MachineFunction &MF = *MBB->getParent();
18988 MachineRegisterInfo &MRI = MF.getRegInfo();
18990 // Check whether the addend is defined by a PHI:
18991 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18992 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18993 if (!AddendDef.isPHI())
18996 // Look for the following pattern:
18998 // %addend = phi [%entry, 0], [%loop, %result]
19000 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19004 // %addend = phi [%entry, 0], [%loop, %result]
19006 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19008 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19009 assert(AddendDef.getOperand(i).isReg());
19010 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19011 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19012 if (&PHISrcInst == MI) {
19013 // Found a matching instruction.
19014 unsigned NewFMAOpc = 0;
19015 switch (MI->getOpcode()) {
19016 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19017 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19018 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19019 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19020 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19021 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19022 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19023 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19024 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19025 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19026 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19027 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19028 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19029 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19030 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19031 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19032 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19033 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19034 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19035 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19037 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19038 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19039 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19040 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19041 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19042 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19043 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19044 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19045 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19046 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19047 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19048 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19049 default: llvm_unreachable("Unrecognized FMA variant.");
19052 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19053 MachineInstrBuilder MIB =
19054 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19055 .addOperand(MI->getOperand(0))
19056 .addOperand(MI->getOperand(3))
19057 .addOperand(MI->getOperand(2))
19058 .addOperand(MI->getOperand(1));
19059 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19060 MI->eraseFromParent();
19067 MachineBasicBlock *
19068 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19069 MachineBasicBlock *BB) const {
19070 switch (MI->getOpcode()) {
19071 default: llvm_unreachable("Unexpected instr type to insert");
19072 case X86::TAILJMPd64:
19073 case X86::TAILJMPr64:
19074 case X86::TAILJMPm64:
19075 case X86::TAILJMPd64_REX:
19076 case X86::TAILJMPr64_REX:
19077 case X86::TAILJMPm64_REX:
19078 llvm_unreachable("TAILJMP64 would not be touched here.");
19079 case X86::TCRETURNdi64:
19080 case X86::TCRETURNri64:
19081 case X86::TCRETURNmi64:
19083 case X86::WIN_ALLOCA:
19084 return EmitLoweredWinAlloca(MI, BB);
19085 case X86::SEG_ALLOCA_32:
19086 case X86::SEG_ALLOCA_64:
19087 return EmitLoweredSegAlloca(MI, BB);
19088 case X86::TLSCall_32:
19089 case X86::TLSCall_64:
19090 return EmitLoweredTLSCall(MI, BB);
19091 case X86::CMOV_GR8:
19092 case X86::CMOV_FR32:
19093 case X86::CMOV_FR64:
19094 case X86::CMOV_V4F32:
19095 case X86::CMOV_V2F64:
19096 case X86::CMOV_V2I64:
19097 case X86::CMOV_V8F32:
19098 case X86::CMOV_V4F64:
19099 case X86::CMOV_V4I64:
19100 case X86::CMOV_V16F32:
19101 case X86::CMOV_V8F64:
19102 case X86::CMOV_V8I64:
19103 case X86::CMOV_GR16:
19104 case X86::CMOV_GR32:
19105 case X86::CMOV_RFP32:
19106 case X86::CMOV_RFP64:
19107 case X86::CMOV_RFP80:
19108 return EmitLoweredSelect(MI, BB);
19110 case X86::FP32_TO_INT16_IN_MEM:
19111 case X86::FP32_TO_INT32_IN_MEM:
19112 case X86::FP32_TO_INT64_IN_MEM:
19113 case X86::FP64_TO_INT16_IN_MEM:
19114 case X86::FP64_TO_INT32_IN_MEM:
19115 case X86::FP64_TO_INT64_IN_MEM:
19116 case X86::FP80_TO_INT16_IN_MEM:
19117 case X86::FP80_TO_INT32_IN_MEM:
19118 case X86::FP80_TO_INT64_IN_MEM: {
19119 MachineFunction *F = BB->getParent();
19120 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19121 DebugLoc DL = MI->getDebugLoc();
19123 // Change the floating point control register to use "round towards zero"
19124 // mode when truncating to an integer value.
19125 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19126 addFrameReference(BuildMI(*BB, MI, DL,
19127 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19129 // Load the old value of the high byte of the control word...
19131 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19132 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19135 // Set the high part to be round to zero...
19136 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19139 // Reload the modified control word now...
19140 addFrameReference(BuildMI(*BB, MI, DL,
19141 TII->get(X86::FLDCW16m)), CWFrameIdx);
19143 // Restore the memory image of control word to original value
19144 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19147 // Get the X86 opcode to use.
19149 switch (MI->getOpcode()) {
19150 default: llvm_unreachable("illegal opcode!");
19151 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19152 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19153 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19154 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19155 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19156 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19157 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19158 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19159 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19163 MachineOperand &Op = MI->getOperand(0);
19165 AM.BaseType = X86AddressMode::RegBase;
19166 AM.Base.Reg = Op.getReg();
19168 AM.BaseType = X86AddressMode::FrameIndexBase;
19169 AM.Base.FrameIndex = Op.getIndex();
19171 Op = MI->getOperand(1);
19173 AM.Scale = Op.getImm();
19174 Op = MI->getOperand(2);
19176 AM.IndexReg = Op.getImm();
19177 Op = MI->getOperand(3);
19178 if (Op.isGlobal()) {
19179 AM.GV = Op.getGlobal();
19181 AM.Disp = Op.getImm();
19183 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19184 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19186 // Reload the original control word now.
19187 addFrameReference(BuildMI(*BB, MI, DL,
19188 TII->get(X86::FLDCW16m)), CWFrameIdx);
19190 MI->eraseFromParent(); // The pseudo instruction is gone now.
19193 // String/text processing lowering.
19194 case X86::PCMPISTRM128REG:
19195 case X86::VPCMPISTRM128REG:
19196 case X86::PCMPISTRM128MEM:
19197 case X86::VPCMPISTRM128MEM:
19198 case X86::PCMPESTRM128REG:
19199 case X86::VPCMPESTRM128REG:
19200 case X86::PCMPESTRM128MEM:
19201 case X86::VPCMPESTRM128MEM:
19202 assert(Subtarget->hasSSE42() &&
19203 "Target must have SSE4.2 or AVX features enabled");
19204 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19206 // String/text processing lowering.
19207 case X86::PCMPISTRIREG:
19208 case X86::VPCMPISTRIREG:
19209 case X86::PCMPISTRIMEM:
19210 case X86::VPCMPISTRIMEM:
19211 case X86::PCMPESTRIREG:
19212 case X86::VPCMPESTRIREG:
19213 case X86::PCMPESTRIMEM:
19214 case X86::VPCMPESTRIMEM:
19215 assert(Subtarget->hasSSE42() &&
19216 "Target must have SSE4.2 or AVX features enabled");
19217 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19219 // Thread synchronization.
19221 return EmitMonitor(MI, BB, Subtarget);
19225 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19227 case X86::VASTART_SAVE_XMM_REGS:
19228 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19230 case X86::VAARG_64:
19231 return EmitVAARG64WithCustomInserter(MI, BB);
19233 case X86::EH_SjLj_SetJmp32:
19234 case X86::EH_SjLj_SetJmp64:
19235 return emitEHSjLjSetJmp(MI, BB);
19237 case X86::EH_SjLj_LongJmp32:
19238 case X86::EH_SjLj_LongJmp64:
19239 return emitEHSjLjLongJmp(MI, BB);
19241 case TargetOpcode::STATEPOINT:
19242 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19243 // this point in the process. We diverge later.
19244 return emitPatchPoint(MI, BB);
19246 case TargetOpcode::STACKMAP:
19247 case TargetOpcode::PATCHPOINT:
19248 return emitPatchPoint(MI, BB);
19250 case X86::VFMADDPDr213r:
19251 case X86::VFMADDPSr213r:
19252 case X86::VFMADDSDr213r:
19253 case X86::VFMADDSSr213r:
19254 case X86::VFMSUBPDr213r:
19255 case X86::VFMSUBPSr213r:
19256 case X86::VFMSUBSDr213r:
19257 case X86::VFMSUBSSr213r:
19258 case X86::VFNMADDPDr213r:
19259 case X86::VFNMADDPSr213r:
19260 case X86::VFNMADDSDr213r:
19261 case X86::VFNMADDSSr213r:
19262 case X86::VFNMSUBPDr213r:
19263 case X86::VFNMSUBPSr213r:
19264 case X86::VFNMSUBSDr213r:
19265 case X86::VFNMSUBSSr213r:
19266 case X86::VFMADDSUBPDr213r:
19267 case X86::VFMADDSUBPSr213r:
19268 case X86::VFMSUBADDPDr213r:
19269 case X86::VFMSUBADDPSr213r:
19270 case X86::VFMADDPDr213rY:
19271 case X86::VFMADDPSr213rY:
19272 case X86::VFMSUBPDr213rY:
19273 case X86::VFMSUBPSr213rY:
19274 case X86::VFNMADDPDr213rY:
19275 case X86::VFNMADDPSr213rY:
19276 case X86::VFNMSUBPDr213rY:
19277 case X86::VFNMSUBPSr213rY:
19278 case X86::VFMADDSUBPDr213rY:
19279 case X86::VFMADDSUBPSr213rY:
19280 case X86::VFMSUBADDPDr213rY:
19281 case X86::VFMSUBADDPSr213rY:
19282 return emitFMA3Instr(MI, BB);
19286 //===----------------------------------------------------------------------===//
19287 // X86 Optimization Hooks
19288 //===----------------------------------------------------------------------===//
19290 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19293 const SelectionDAG &DAG,
19294 unsigned Depth) const {
19295 unsigned BitWidth = KnownZero.getBitWidth();
19296 unsigned Opc = Op.getOpcode();
19297 assert((Opc >= ISD::BUILTIN_OP_END ||
19298 Opc == ISD::INTRINSIC_WO_CHAIN ||
19299 Opc == ISD::INTRINSIC_W_CHAIN ||
19300 Opc == ISD::INTRINSIC_VOID) &&
19301 "Should use MaskedValueIsZero if you don't know whether Op"
19302 " is a target node!");
19304 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19318 // These nodes' second result is a boolean.
19319 if (Op.getResNo() == 0)
19322 case X86ISD::SETCC:
19323 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19325 case ISD::INTRINSIC_WO_CHAIN: {
19326 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19327 unsigned NumLoBits = 0;
19330 case Intrinsic::x86_sse_movmsk_ps:
19331 case Intrinsic::x86_avx_movmsk_ps_256:
19332 case Intrinsic::x86_sse2_movmsk_pd:
19333 case Intrinsic::x86_avx_movmsk_pd_256:
19334 case Intrinsic::x86_mmx_pmovmskb:
19335 case Intrinsic::x86_sse2_pmovmskb_128:
19336 case Intrinsic::x86_avx2_pmovmskb: {
19337 // High bits of movmskp{s|d}, pmovmskb are known zero.
19339 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19340 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19341 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19342 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19343 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19344 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19345 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19346 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19348 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19357 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19359 const SelectionDAG &,
19360 unsigned Depth) const {
19361 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19362 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19363 return Op.getValueType().getScalarType().getSizeInBits();
19369 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19370 /// node is a GlobalAddress + offset.
19371 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19372 const GlobalValue* &GA,
19373 int64_t &Offset) const {
19374 if (N->getOpcode() == X86ISD::Wrapper) {
19375 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19376 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19377 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19381 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19384 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19385 /// same as extracting the high 128-bit part of 256-bit vector and then
19386 /// inserting the result into the low part of a new 256-bit vector
19387 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19388 EVT VT = SVOp->getValueType(0);
19389 unsigned NumElems = VT.getVectorNumElements();
19391 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19392 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19393 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19394 SVOp->getMaskElt(j) >= 0)
19400 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19401 /// same as extracting the low 128-bit part of 256-bit vector and then
19402 /// inserting the result into the high part of a new 256-bit vector
19403 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19404 EVT VT = SVOp->getValueType(0);
19405 unsigned NumElems = VT.getVectorNumElements();
19407 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19408 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19409 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19410 SVOp->getMaskElt(j) >= 0)
19416 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19417 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19418 TargetLowering::DAGCombinerInfo &DCI,
19419 const X86Subtarget* Subtarget) {
19421 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19422 SDValue V1 = SVOp->getOperand(0);
19423 SDValue V2 = SVOp->getOperand(1);
19424 EVT VT = SVOp->getValueType(0);
19425 unsigned NumElems = VT.getVectorNumElements();
19427 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19428 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19432 // V UNDEF BUILD_VECTOR UNDEF
19434 // CONCAT_VECTOR CONCAT_VECTOR
19437 // RESULT: V + zero extended
19439 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19440 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19441 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19444 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19447 // To match the shuffle mask, the first half of the mask should
19448 // be exactly the first vector, and all the rest a splat with the
19449 // first element of the second one.
19450 for (unsigned i = 0; i != NumElems/2; ++i)
19451 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19452 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19455 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19456 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19457 if (Ld->hasNUsesOfValue(1, 0)) {
19458 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19459 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19461 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19463 Ld->getPointerInfo(),
19464 Ld->getAlignment(),
19465 false/*isVolatile*/, true/*ReadMem*/,
19466 false/*WriteMem*/);
19468 // Make sure the newly-created LOAD is in the same position as Ld in
19469 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19470 // and update uses of Ld's output chain to use the TokenFactor.
19471 if (Ld->hasAnyUseOfValue(1)) {
19472 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19473 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19474 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19475 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19476 SDValue(ResNode.getNode(), 1));
19479 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19483 // Emit a zeroed vector and insert the desired subvector on its
19485 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19486 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19487 return DCI.CombineTo(N, InsV);
19490 //===--------------------------------------------------------------------===//
19491 // Combine some shuffles into subvector extracts and inserts:
19494 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19495 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19496 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19497 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19498 return DCI.CombineTo(N, InsV);
19501 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19502 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19503 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19504 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19505 return DCI.CombineTo(N, InsV);
19511 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19514 /// This is the leaf of the recursive combinine below. When we have found some
19515 /// chain of single-use x86 shuffle instructions and accumulated the combined
19516 /// shuffle mask represented by them, this will try to pattern match that mask
19517 /// into either a single instruction if there is a special purpose instruction
19518 /// for this operation, or into a PSHUFB instruction which is a fully general
19519 /// instruction but should only be used to replace chains over a certain depth.
19520 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19521 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19522 TargetLowering::DAGCombinerInfo &DCI,
19523 const X86Subtarget *Subtarget) {
19524 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19526 // Find the operand that enters the chain. Note that multiple uses are OK
19527 // here, we're not going to remove the operand we find.
19528 SDValue Input = Op.getOperand(0);
19529 while (Input.getOpcode() == ISD::BITCAST)
19530 Input = Input.getOperand(0);
19532 MVT VT = Input.getSimpleValueType();
19533 MVT RootVT = Root.getSimpleValueType();
19536 // Just remove no-op shuffle masks.
19537 if (Mask.size() == 1) {
19538 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19543 // Use the float domain if the operand type is a floating point type.
19544 bool FloatDomain = VT.isFloatingPoint();
19546 // For floating point shuffles, we don't have free copies in the shuffle
19547 // instructions or the ability to load as part of the instruction, so
19548 // canonicalize their shuffles to UNPCK or MOV variants.
19550 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19551 // vectors because it can have a load folded into it that UNPCK cannot. This
19552 // doesn't preclude something switching to the shorter encoding post-RA.
19554 // FIXME: Should teach these routines about AVX vector widths.
19555 if (FloatDomain && VT.getSizeInBits() == 128) {
19556 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
19557 bool Lo = Mask.equals({0, 0});
19560 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19561 // is no slower than UNPCKLPD but has the option to fold the input operand
19562 // into even an unaligned memory load.
19563 if (Lo && Subtarget->hasSSE3()) {
19564 Shuffle = X86ISD::MOVDDUP;
19565 ShuffleVT = MVT::v2f64;
19567 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19568 // than the UNPCK variants.
19569 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19570 ShuffleVT = MVT::v4f32;
19572 if (Depth == 1 && Root->getOpcode() == Shuffle)
19573 return false; // Nothing to do!
19574 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19575 DCI.AddToWorklist(Op.getNode());
19576 if (Shuffle == X86ISD::MOVDDUP)
19577 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19579 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19580 DCI.AddToWorklist(Op.getNode());
19581 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19585 if (Subtarget->hasSSE3() &&
19586 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
19587 bool Lo = Mask.equals({0, 0, 2, 2});
19588 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19589 MVT ShuffleVT = MVT::v4f32;
19590 if (Depth == 1 && Root->getOpcode() == Shuffle)
19591 return false; // Nothing to do!
19592 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19593 DCI.AddToWorklist(Op.getNode());
19594 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19595 DCI.AddToWorklist(Op.getNode());
19596 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19600 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
19601 bool Lo = Mask.equals({0, 0, 1, 1});
19602 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19603 MVT ShuffleVT = MVT::v4f32;
19604 if (Depth == 1 && Root->getOpcode() == Shuffle)
19605 return false; // Nothing to do!
19606 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19607 DCI.AddToWorklist(Op.getNode());
19608 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19609 DCI.AddToWorklist(Op.getNode());
19610 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19616 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19617 // variants as none of these have single-instruction variants that are
19618 // superior to the UNPCK formulation.
19619 if (!FloatDomain && VT.getSizeInBits() == 128 &&
19620 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
19621 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
19622 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
19624 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
19625 bool Lo = Mask[0] == 0;
19626 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19627 if (Depth == 1 && Root->getOpcode() == Shuffle)
19628 return false; // Nothing to do!
19630 switch (Mask.size()) {
19632 ShuffleVT = MVT::v8i16;
19635 ShuffleVT = MVT::v16i8;
19638 llvm_unreachable("Impossible mask size!");
19640 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19641 DCI.AddToWorklist(Op.getNode());
19642 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19643 DCI.AddToWorklist(Op.getNode());
19644 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19649 // Don't try to re-form single instruction chains under any circumstances now
19650 // that we've done encoding canonicalization for them.
19654 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19655 // can replace them with a single PSHUFB instruction profitably. Intel's
19656 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19657 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19658 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19659 SmallVector<SDValue, 16> PSHUFBMask;
19660 int NumBytes = VT.getSizeInBits() / 8;
19661 int Ratio = NumBytes / Mask.size();
19662 for (int i = 0; i < NumBytes; ++i) {
19663 if (Mask[i / Ratio] == SM_SentinelUndef) {
19664 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
19667 int M = Mask[i / Ratio] != SM_SentinelZero
19668 ? Ratio * Mask[i / Ratio] + i % Ratio
19670 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19672 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
19673 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
19674 DCI.AddToWorklist(Op.getNode());
19675 SDValue PSHUFBMaskOp =
19676 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
19677 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19678 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
19679 DCI.AddToWorklist(Op.getNode());
19680 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19685 // Failed to find any combines.
19689 /// \brief Fully generic combining of x86 shuffle instructions.
19691 /// This should be the last combine run over the x86 shuffle instructions. Once
19692 /// they have been fully optimized, this will recursively consider all chains
19693 /// of single-use shuffle instructions, build a generic model of the cumulative
19694 /// shuffle operation, and check for simpler instructions which implement this
19695 /// operation. We use this primarily for two purposes:
19697 /// 1) Collapse generic shuffles to specialized single instructions when
19698 /// equivalent. In most cases, this is just an encoding size win, but
19699 /// sometimes we will collapse multiple generic shuffles into a single
19700 /// special-purpose shuffle.
19701 /// 2) Look for sequences of shuffle instructions with 3 or more total
19702 /// instructions, and replace them with the slightly more expensive SSSE3
19703 /// PSHUFB instruction if available. We do this as the last combining step
19704 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19705 /// a suitable short sequence of other instructions. The PHUFB will either
19706 /// use a register or have to read from memory and so is slightly (but only
19707 /// slightly) more expensive than the other shuffle instructions.
19709 /// Because this is inherently a quadratic operation (for each shuffle in
19710 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19711 /// This should never be an issue in practice as the shuffle lowering doesn't
19712 /// produce sequences of more than 8 instructions.
19714 /// FIXME: We will currently miss some cases where the redundant shuffling
19715 /// would simplify under the threshold for PSHUFB formation because of
19716 /// combine-ordering. To fix this, we should do the redundant instruction
19717 /// combining in this recursive walk.
19718 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19719 ArrayRef<int> RootMask,
19720 int Depth, bool HasPSHUFB,
19722 TargetLowering::DAGCombinerInfo &DCI,
19723 const X86Subtarget *Subtarget) {
19724 // Bound the depth of our recursive combine because this is ultimately
19725 // quadratic in nature.
19729 // Directly rip through bitcasts to find the underlying operand.
19730 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19731 Op = Op.getOperand(0);
19733 MVT VT = Op.getSimpleValueType();
19734 if (!VT.isVector())
19735 return false; // Bail if we hit a non-vector.
19737 assert(Root.getSimpleValueType().isVector() &&
19738 "Shuffles operate on vector types!");
19739 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19740 "Can only combine shuffles of the same vector register size.");
19742 if (!isTargetShuffle(Op.getOpcode()))
19744 SmallVector<int, 16> OpMask;
19746 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19747 // We only can combine unary shuffles which we can decode the mask for.
19748 if (!HaveMask || !IsUnary)
19751 assert(VT.getVectorNumElements() == OpMask.size() &&
19752 "Different mask size from vector size!");
19753 assert(((RootMask.size() > OpMask.size() &&
19754 RootMask.size() % OpMask.size() == 0) ||
19755 (OpMask.size() > RootMask.size() &&
19756 OpMask.size() % RootMask.size() == 0) ||
19757 OpMask.size() == RootMask.size()) &&
19758 "The smaller number of elements must divide the larger.");
19759 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19760 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19761 assert(((RootRatio == 1 && OpRatio == 1) ||
19762 (RootRatio == 1) != (OpRatio == 1)) &&
19763 "Must not have a ratio for both incoming and op masks!");
19765 SmallVector<int, 16> Mask;
19766 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19768 // Merge this shuffle operation's mask into our accumulated mask. Note that
19769 // this shuffle's mask will be the first applied to the input, followed by the
19770 // root mask to get us all the way to the root value arrangement. The reason
19771 // for this order is that we are recursing up the operation chain.
19772 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19773 int RootIdx = i / RootRatio;
19774 if (RootMask[RootIdx] < 0) {
19775 // This is a zero or undef lane, we're done.
19776 Mask.push_back(RootMask[RootIdx]);
19780 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19781 int OpIdx = RootMaskedIdx / OpRatio;
19782 if (OpMask[OpIdx] < 0) {
19783 // The incoming lanes are zero or undef, it doesn't matter which ones we
19785 Mask.push_back(OpMask[OpIdx]);
19789 // Ok, we have non-zero lanes, map them through.
19790 Mask.push_back(OpMask[OpIdx] * OpRatio +
19791 RootMaskedIdx % OpRatio);
19794 // See if we can recurse into the operand to combine more things.
19795 switch (Op.getOpcode()) {
19796 case X86ISD::PSHUFB:
19798 case X86ISD::PSHUFD:
19799 case X86ISD::PSHUFHW:
19800 case X86ISD::PSHUFLW:
19801 if (Op.getOperand(0).hasOneUse() &&
19802 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19803 HasPSHUFB, DAG, DCI, Subtarget))
19807 case X86ISD::UNPCKL:
19808 case X86ISD::UNPCKH:
19809 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19810 // We can't check for single use, we have to check that this shuffle is the only user.
19811 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19812 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19813 HasPSHUFB, DAG, DCI, Subtarget))
19818 // Minor canonicalization of the accumulated shuffle mask to make it easier
19819 // to match below. All this does is detect masks with squential pairs of
19820 // elements, and shrink them to the half-width mask. It does this in a loop
19821 // so it will reduce the size of the mask to the minimal width mask which
19822 // performs an equivalent shuffle.
19823 SmallVector<int, 16> WidenedMask;
19824 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
19825 Mask = std::move(WidenedMask);
19826 WidenedMask.clear();
19829 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19833 /// \brief Get the PSHUF-style mask from PSHUF node.
19835 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19836 /// PSHUF-style masks that can be reused with such instructions.
19837 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19838 MVT VT = N.getSimpleValueType();
19839 SmallVector<int, 4> Mask;
19841 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
19845 // If we have more than 128-bits, only the low 128-bits of shuffle mask
19846 // matter. Check that the upper masks are repeats and remove them.
19847 if (VT.getSizeInBits() > 128) {
19848 int LaneElts = 128 / VT.getScalarSizeInBits();
19850 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
19851 for (int j = 0; j < LaneElts; ++j)
19852 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
19853 "Mask doesn't repeat in high 128-bit lanes!");
19855 Mask.resize(LaneElts);
19858 switch (N.getOpcode()) {
19859 case X86ISD::PSHUFD:
19861 case X86ISD::PSHUFLW:
19864 case X86ISD::PSHUFHW:
19865 Mask.erase(Mask.begin(), Mask.begin() + 4);
19866 for (int &M : Mask)
19870 llvm_unreachable("No valid shuffle instruction found!");
19874 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19876 /// We walk up the chain and look for a combinable shuffle, skipping over
19877 /// shuffles that we could hoist this shuffle's transformation past without
19878 /// altering anything.
19880 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19882 TargetLowering::DAGCombinerInfo &DCI) {
19883 assert(N.getOpcode() == X86ISD::PSHUFD &&
19884 "Called with something other than an x86 128-bit half shuffle!");
19887 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
19888 // of the shuffles in the chain so that we can form a fresh chain to replace
19890 SmallVector<SDValue, 8> Chain;
19891 SDValue V = N.getOperand(0);
19892 for (; V.hasOneUse(); V = V.getOperand(0)) {
19893 switch (V.getOpcode()) {
19895 return SDValue(); // Nothing combined!
19898 // Skip bitcasts as we always know the type for the target specific
19902 case X86ISD::PSHUFD:
19903 // Found another dword shuffle.
19906 case X86ISD::PSHUFLW:
19907 // Check that the low words (being shuffled) are the identity in the
19908 // dword shuffle, and the high words are self-contained.
19909 if (Mask[0] != 0 || Mask[1] != 1 ||
19910 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19913 Chain.push_back(V);
19916 case X86ISD::PSHUFHW:
19917 // Check that the high words (being shuffled) are the identity in the
19918 // dword shuffle, and the low words are self-contained.
19919 if (Mask[2] != 2 || Mask[3] != 3 ||
19920 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19923 Chain.push_back(V);
19926 case X86ISD::UNPCKL:
19927 case X86ISD::UNPCKH:
19928 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19929 // shuffle into a preceding word shuffle.
19930 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
19931 V.getSimpleValueType().getScalarType() != MVT::i16)
19934 // Search for a half-shuffle which we can combine with.
19935 unsigned CombineOp =
19936 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19937 if (V.getOperand(0) != V.getOperand(1) ||
19938 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19940 Chain.push_back(V);
19941 V = V.getOperand(0);
19943 switch (V.getOpcode()) {
19945 return SDValue(); // Nothing to combine.
19947 case X86ISD::PSHUFLW:
19948 case X86ISD::PSHUFHW:
19949 if (V.getOpcode() == CombineOp)
19952 Chain.push_back(V);
19956 V = V.getOperand(0);
19960 } while (V.hasOneUse());
19963 // Break out of the loop if we break out of the switch.
19967 if (!V.hasOneUse())
19968 // We fell out of the loop without finding a viable combining instruction.
19971 // Merge this node's mask and our incoming mask.
19972 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19973 for (int &M : Mask)
19975 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19976 getV4X86ShuffleImm8ForMask(Mask, DAG));
19978 // Rebuild the chain around this new shuffle.
19979 while (!Chain.empty()) {
19980 SDValue W = Chain.pop_back_val();
19982 if (V.getValueType() != W.getOperand(0).getValueType())
19983 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
19985 switch (W.getOpcode()) {
19987 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
19989 case X86ISD::UNPCKL:
19990 case X86ISD::UNPCKH:
19991 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
19994 case X86ISD::PSHUFD:
19995 case X86ISD::PSHUFLW:
19996 case X86ISD::PSHUFHW:
19997 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20001 if (V.getValueType() != N.getValueType())
20002 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20004 // Return the new chain to replace N.
20008 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20010 /// We walk up the chain, skipping shuffles of the other half and looking
20011 /// through shuffles which switch halves trying to find a shuffle of the same
20012 /// pair of dwords.
20013 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20015 TargetLowering::DAGCombinerInfo &DCI) {
20017 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20018 "Called with something other than an x86 128-bit half shuffle!");
20020 unsigned CombineOpcode = N.getOpcode();
20022 // Walk up a single-use chain looking for a combinable shuffle.
20023 SDValue V = N.getOperand(0);
20024 for (; V.hasOneUse(); V = V.getOperand(0)) {
20025 switch (V.getOpcode()) {
20027 return false; // Nothing combined!
20030 // Skip bitcasts as we always know the type for the target specific
20034 case X86ISD::PSHUFLW:
20035 case X86ISD::PSHUFHW:
20036 if (V.getOpcode() == CombineOpcode)
20039 // Other-half shuffles are no-ops.
20042 // Break out of the loop if we break out of the switch.
20046 if (!V.hasOneUse())
20047 // We fell out of the loop without finding a viable combining instruction.
20050 // Combine away the bottom node as its shuffle will be accumulated into
20051 // a preceding shuffle.
20052 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20054 // Record the old value.
20057 // Merge this node's mask and our incoming mask (adjusted to account for all
20058 // the pshufd instructions encountered).
20059 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20060 for (int &M : Mask)
20062 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20063 getV4X86ShuffleImm8ForMask(Mask, DAG));
20065 // Check that the shuffles didn't cancel each other out. If not, we need to
20066 // combine to the new one.
20068 // Replace the combinable shuffle with the combined one, updating all users
20069 // so that we re-evaluate the chain here.
20070 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20075 /// \brief Try to combine x86 target specific shuffles.
20076 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20077 TargetLowering::DAGCombinerInfo &DCI,
20078 const X86Subtarget *Subtarget) {
20080 MVT VT = N.getSimpleValueType();
20081 SmallVector<int, 4> Mask;
20083 switch (N.getOpcode()) {
20084 case X86ISD::PSHUFD:
20085 case X86ISD::PSHUFLW:
20086 case X86ISD::PSHUFHW:
20087 Mask = getPSHUFShuffleMask(N);
20088 assert(Mask.size() == 4);
20094 // Nuke no-op shuffles that show up after combining.
20095 if (isNoopShuffleMask(Mask))
20096 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20098 // Look for simplifications involving one or two shuffle instructions.
20099 SDValue V = N.getOperand(0);
20100 switch (N.getOpcode()) {
20103 case X86ISD::PSHUFLW:
20104 case X86ISD::PSHUFHW:
20105 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20107 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20108 return SDValue(); // We combined away this shuffle, so we're done.
20110 // See if this reduces to a PSHUFD which is no more expensive and can
20111 // combine with more operations. Note that it has to at least flip the
20112 // dwords as otherwise it would have been removed as a no-op.
20113 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20114 int DMask[] = {0, 1, 2, 3};
20115 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20116 DMask[DOffset + 0] = DOffset + 1;
20117 DMask[DOffset + 1] = DOffset + 0;
20118 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20119 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20120 DCI.AddToWorklist(V.getNode());
20121 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20122 getV4X86ShuffleImm8ForMask(DMask, DAG));
20123 DCI.AddToWorklist(V.getNode());
20124 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20127 // Look for shuffle patterns which can be implemented as a single unpack.
20128 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20129 // only works when we have a PSHUFD followed by two half-shuffles.
20130 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20131 (V.getOpcode() == X86ISD::PSHUFLW ||
20132 V.getOpcode() == X86ISD::PSHUFHW) &&
20133 V.getOpcode() != N.getOpcode() &&
20135 SDValue D = V.getOperand(0);
20136 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20137 D = D.getOperand(0);
20138 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20139 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20140 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20141 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20142 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20144 for (int i = 0; i < 4; ++i) {
20145 WordMask[i + NOffset] = Mask[i] + NOffset;
20146 WordMask[i + VOffset] = VMask[i] + VOffset;
20148 // Map the word mask through the DWord mask.
20150 for (int i = 0; i < 8; ++i)
20151 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20152 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20153 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20154 // We can replace all three shuffles with an unpack.
20155 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20156 DCI.AddToWorklist(V.getNode());
20157 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20166 case X86ISD::PSHUFD:
20167 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20176 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20178 /// We combine this directly on the abstract vector shuffle nodes so it is
20179 /// easier to generically match. We also insert dummy vector shuffle nodes for
20180 /// the operands which explicitly discard the lanes which are unused by this
20181 /// operation to try to flow through the rest of the combiner the fact that
20182 /// they're unused.
20183 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20185 EVT VT = N->getValueType(0);
20187 // We only handle target-independent shuffles.
20188 // FIXME: It would be easy and harmless to use the target shuffle mask
20189 // extraction tool to support more.
20190 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20193 auto *SVN = cast<ShuffleVectorSDNode>(N);
20194 ArrayRef<int> Mask = SVN->getMask();
20195 SDValue V1 = N->getOperand(0);
20196 SDValue V2 = N->getOperand(1);
20198 // We require the first shuffle operand to be the SUB node, and the second to
20199 // be the ADD node.
20200 // FIXME: We should support the commuted patterns.
20201 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20204 // If there are other uses of these operations we can't fold them.
20205 if (!V1->hasOneUse() || !V2->hasOneUse())
20208 // Ensure that both operations have the same operands. Note that we can
20209 // commute the FADD operands.
20210 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20211 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20212 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20215 // We're looking for blends between FADD and FSUB nodes. We insist on these
20216 // nodes being lined up in a specific expected pattern.
20217 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20218 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20219 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20222 // Only specific types are legal at this point, assert so we notice if and
20223 // when these change.
20224 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20225 VT == MVT::v4f64) &&
20226 "Unknown vector type encountered!");
20228 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20231 /// PerformShuffleCombine - Performs several different shuffle combines.
20232 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20233 TargetLowering::DAGCombinerInfo &DCI,
20234 const X86Subtarget *Subtarget) {
20236 SDValue N0 = N->getOperand(0);
20237 SDValue N1 = N->getOperand(1);
20238 EVT VT = N->getValueType(0);
20240 // Don't create instructions with illegal types after legalize types has run.
20241 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20242 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20245 // If we have legalized the vector types, look for blends of FADD and FSUB
20246 // nodes that we can fuse into an ADDSUB node.
20247 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20248 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20251 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20252 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20253 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20254 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20256 // During Type Legalization, when promoting illegal vector types,
20257 // the backend might introduce new shuffle dag nodes and bitcasts.
20259 // This code performs the following transformation:
20260 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20261 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20263 // We do this only if both the bitcast and the BINOP dag nodes have
20264 // one use. Also, perform this transformation only if the new binary
20265 // operation is legal. This is to avoid introducing dag nodes that
20266 // potentially need to be further expanded (or custom lowered) into a
20267 // less optimal sequence of dag nodes.
20268 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20269 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20270 N0.getOpcode() == ISD::BITCAST) {
20271 SDValue BC0 = N0.getOperand(0);
20272 EVT SVT = BC0.getValueType();
20273 unsigned Opcode = BC0.getOpcode();
20274 unsigned NumElts = VT.getVectorNumElements();
20276 if (BC0.hasOneUse() && SVT.isVector() &&
20277 SVT.getVectorNumElements() * 2 == NumElts &&
20278 TLI.isOperationLegal(Opcode, VT)) {
20279 bool CanFold = false;
20291 unsigned SVTNumElts = SVT.getVectorNumElements();
20292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20293 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20294 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20295 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20296 CanFold = SVOp->getMaskElt(i) < 0;
20299 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20300 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20301 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20302 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20307 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20308 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20309 // consecutive, non-overlapping, and in the right order.
20310 SmallVector<SDValue, 16> Elts;
20311 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20312 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20314 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20318 if (isTargetShuffle(N->getOpcode())) {
20320 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20321 if (Shuffle.getNode())
20324 // Try recursively combining arbitrary sequences of x86 shuffle
20325 // instructions into higher-order shuffles. We do this after combining
20326 // specific PSHUF instruction sequences into their minimal form so that we
20327 // can evaluate how many specialized shuffle instructions are involved in
20328 // a particular chain.
20329 SmallVector<int, 1> NonceMask; // Just a placeholder.
20330 NonceMask.push_back(0);
20331 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20332 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20334 return SDValue(); // This routine will use CombineTo to replace N.
20340 /// PerformTruncateCombine - Converts truncate operation to
20341 /// a sequence of vector shuffle operations.
20342 /// It is possible when we truncate 256-bit vector to 128-bit vector
20343 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20344 TargetLowering::DAGCombinerInfo &DCI,
20345 const X86Subtarget *Subtarget) {
20349 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20350 /// specific shuffle of a load can be folded into a single element load.
20351 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20352 /// shuffles have been custom lowered so we need to handle those here.
20353 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20354 TargetLowering::DAGCombinerInfo &DCI) {
20355 if (DCI.isBeforeLegalizeOps())
20358 SDValue InVec = N->getOperand(0);
20359 SDValue EltNo = N->getOperand(1);
20361 if (!isa<ConstantSDNode>(EltNo))
20364 EVT OriginalVT = InVec.getValueType();
20366 if (InVec.getOpcode() == ISD::BITCAST) {
20367 // Don't duplicate a load with other uses.
20368 if (!InVec.hasOneUse())
20370 EVT BCVT = InVec.getOperand(0).getValueType();
20371 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20373 InVec = InVec.getOperand(0);
20376 EVT CurrentVT = InVec.getValueType();
20378 if (!isTargetShuffle(InVec.getOpcode()))
20381 // Don't duplicate a load with other uses.
20382 if (!InVec.hasOneUse())
20385 SmallVector<int, 16> ShuffleMask;
20387 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20388 ShuffleMask, UnaryShuffle))
20391 // Select the input vector, guarding against out of range extract vector.
20392 unsigned NumElems = CurrentVT.getVectorNumElements();
20393 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20394 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20395 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20396 : InVec.getOperand(1);
20398 // If inputs to shuffle are the same for both ops, then allow 2 uses
20399 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20400 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20402 if (LdNode.getOpcode() == ISD::BITCAST) {
20403 // Don't duplicate a load with other uses.
20404 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20407 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20408 LdNode = LdNode.getOperand(0);
20411 if (!ISD::isNormalLoad(LdNode.getNode()))
20414 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20416 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20419 EVT EltVT = N->getValueType(0);
20420 // If there's a bitcast before the shuffle, check if the load type and
20421 // alignment is valid.
20422 unsigned Align = LN0->getAlignment();
20423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20424 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20425 EltVT.getTypeForEVT(*DAG.getContext()));
20427 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20430 // All checks match so transform back to vector_shuffle so that DAG combiner
20431 // can finish the job
20434 // Create shuffle node taking into account the case that its a unary shuffle
20435 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20436 : InVec.getOperand(1);
20437 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20438 InVec.getOperand(0), Shuffle,
20440 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20441 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20445 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20446 /// special and don't usually play with other vector types, it's better to
20447 /// handle them early to be sure we emit efficient code by avoiding
20448 /// store-load conversions.
20449 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20450 if (N->getValueType(0) != MVT::x86mmx ||
20451 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
20452 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20455 SDValue V = N->getOperand(0);
20456 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20457 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20458 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20459 N->getValueType(0), V.getOperand(0));
20464 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20465 /// generation and convert it from being a bunch of shuffles and extracts
20466 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20467 /// storing the value and loading scalars back, while for x64 we should
20468 /// use 64-bit extracts and shifts.
20469 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20470 TargetLowering::DAGCombinerInfo &DCI) {
20471 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20472 if (NewOp.getNode())
20475 SDValue InputVector = N->getOperand(0);
20477 // Detect mmx to i32 conversion through a v2i32 elt extract.
20478 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20479 N->getValueType(0) == MVT::i32 &&
20480 InputVector.getValueType() == MVT::v2i32) {
20482 // The bitcast source is a direct mmx result.
20483 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20484 if (MMXSrc.getValueType() == MVT::x86mmx)
20485 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20486 N->getValueType(0),
20487 InputVector.getNode()->getOperand(0));
20489 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20490 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20491 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20492 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20493 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20494 MMXSrcOp.getValueType() == MVT::v1i64 &&
20495 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20496 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20497 N->getValueType(0),
20498 MMXSrcOp.getOperand(0));
20501 // Only operate on vectors of 4 elements, where the alternative shuffling
20502 // gets to be more expensive.
20503 if (InputVector.getValueType() != MVT::v4i32)
20506 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20507 // single use which is a sign-extend or zero-extend, and all elements are
20509 SmallVector<SDNode *, 4> Uses;
20510 unsigned ExtractedElements = 0;
20511 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20512 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20513 if (UI.getUse().getResNo() != InputVector.getResNo())
20516 SDNode *Extract = *UI;
20517 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20520 if (Extract->getValueType(0) != MVT::i32)
20522 if (!Extract->hasOneUse())
20524 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20525 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20527 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20530 // Record which element was extracted.
20531 ExtractedElements |=
20532 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20534 Uses.push_back(Extract);
20537 // If not all the elements were used, this may not be worthwhile.
20538 if (ExtractedElements != 15)
20541 // Ok, we've now decided to do the transformation.
20542 // If 64-bit shifts are legal, use the extract-shift sequence,
20543 // otherwise bounce the vector off the cache.
20544 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20546 SDLoc dl(InputVector);
20548 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20549 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20550 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20551 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20552 DAG.getConstant(0, VecIdxTy));
20553 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20554 DAG.getConstant(1, VecIdxTy));
20556 SDValue ShAmt = DAG.getConstant(32,
20557 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20558 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20559 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20560 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20561 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20562 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20563 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20565 // Store the value to a temporary stack slot.
20566 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20567 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20568 MachinePointerInfo(), false, false, 0);
20570 EVT ElementType = InputVector.getValueType().getVectorElementType();
20571 unsigned EltSize = ElementType.getSizeInBits() / 8;
20573 // Replace each use (extract) with a load of the appropriate element.
20574 for (unsigned i = 0; i < 4; ++i) {
20575 uint64_t Offset = EltSize * i;
20576 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20578 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20579 StackPtr, OffsetVal);
20581 // Load the scalar.
20582 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20583 ScalarAddr, MachinePointerInfo(),
20584 false, false, false, 0);
20589 // Replace the extracts
20590 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20591 UE = Uses.end(); UI != UE; ++UI) {
20592 SDNode *Extract = *UI;
20594 SDValue Idx = Extract->getOperand(1);
20595 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20596 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20599 // The replacement was made in place; don't return anything.
20603 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20604 static std::pair<unsigned, bool>
20605 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20606 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20607 if (!VT.isVector())
20608 return std::make_pair(0, false);
20610 bool NeedSplit = false;
20611 switch (VT.getSimpleVT().SimpleTy) {
20612 default: return std::make_pair(0, false);
20615 if (!Subtarget->hasVLX())
20616 return std::make_pair(0, false);
20620 if (!Subtarget->hasBWI())
20621 return std::make_pair(0, false);
20625 if (!Subtarget->hasAVX512())
20626 return std::make_pair(0, false);
20631 if (!Subtarget->hasAVX2())
20633 if (!Subtarget->hasAVX())
20634 return std::make_pair(0, false);
20639 if (!Subtarget->hasSSE2())
20640 return std::make_pair(0, false);
20643 // SSE2 has only a small subset of the operations.
20644 bool hasUnsigned = Subtarget->hasSSE41() ||
20645 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20646 bool hasSigned = Subtarget->hasSSE41() ||
20647 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20649 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20652 // Check for x CC y ? x : y.
20653 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20654 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20659 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20662 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20665 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20668 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20670 // Check for x CC y ? y : x -- a min/max with reversed arms.
20671 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20672 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20677 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20680 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20683 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20686 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20690 return std::make_pair(Opc, NeedSplit);
20694 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20695 const X86Subtarget *Subtarget) {
20697 SDValue Cond = N->getOperand(0);
20698 SDValue LHS = N->getOperand(1);
20699 SDValue RHS = N->getOperand(2);
20701 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20702 SDValue CondSrc = Cond->getOperand(0);
20703 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20704 Cond = CondSrc->getOperand(0);
20707 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20710 // A vselect where all conditions and data are constants can be optimized into
20711 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20712 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20713 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20716 unsigned MaskValue = 0;
20717 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20720 MVT VT = N->getSimpleValueType(0);
20721 unsigned NumElems = VT.getVectorNumElements();
20722 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20723 for (unsigned i = 0; i < NumElems; ++i) {
20724 // Be sure we emit undef where we can.
20725 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20726 ShuffleMask[i] = -1;
20728 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20731 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20732 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
20734 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20737 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20739 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20740 TargetLowering::DAGCombinerInfo &DCI,
20741 const X86Subtarget *Subtarget) {
20743 SDValue Cond = N->getOperand(0);
20744 // Get the LHS/RHS of the select.
20745 SDValue LHS = N->getOperand(1);
20746 SDValue RHS = N->getOperand(2);
20747 EVT VT = LHS.getValueType();
20748 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20750 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20751 // instructions match the semantics of the common C idiom x<y?x:y but not
20752 // x<=y?x:y, because of how they handle negative zero (which can be
20753 // ignored in unsafe-math mode).
20754 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
20755 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20756 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
20757 (Subtarget->hasSSE2() ||
20758 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20759 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20761 unsigned Opcode = 0;
20762 // Check for x CC y ? x : y.
20763 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20764 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20768 // Converting this to a min would handle NaNs incorrectly, and swapping
20769 // the operands would cause it to handle comparisons between positive
20770 // and negative zero incorrectly.
20771 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20772 if (!DAG.getTarget().Options.UnsafeFPMath &&
20773 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20775 std::swap(LHS, RHS);
20777 Opcode = X86ISD::FMIN;
20780 // Converting this to a min would handle comparisons between positive
20781 // and negative zero incorrectly.
20782 if (!DAG.getTarget().Options.UnsafeFPMath &&
20783 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20785 Opcode = X86ISD::FMIN;
20788 // Converting this to a min would handle both negative zeros and NaNs
20789 // incorrectly, but we can swap the operands to fix both.
20790 std::swap(LHS, RHS);
20794 Opcode = X86ISD::FMIN;
20798 // Converting this to a max would handle comparisons between positive
20799 // and negative zero incorrectly.
20800 if (!DAG.getTarget().Options.UnsafeFPMath &&
20801 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20803 Opcode = X86ISD::FMAX;
20806 // Converting this to a max would handle NaNs incorrectly, and swapping
20807 // the operands would cause it to handle comparisons between positive
20808 // and negative zero incorrectly.
20809 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20810 if (!DAG.getTarget().Options.UnsafeFPMath &&
20811 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20813 std::swap(LHS, RHS);
20815 Opcode = X86ISD::FMAX;
20818 // Converting this to a max would handle both negative zeros and NaNs
20819 // incorrectly, but we can swap the operands to fix both.
20820 std::swap(LHS, RHS);
20824 Opcode = X86ISD::FMAX;
20827 // Check for x CC y ? y : x -- a min/max with reversed arms.
20828 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20829 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20833 // Converting this to a min would handle comparisons between positive
20834 // and negative zero incorrectly, and swapping the operands would
20835 // cause it to handle NaNs incorrectly.
20836 if (!DAG.getTarget().Options.UnsafeFPMath &&
20837 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20838 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20840 std::swap(LHS, RHS);
20842 Opcode = X86ISD::FMIN;
20845 // Converting this to a min would handle NaNs incorrectly.
20846 if (!DAG.getTarget().Options.UnsafeFPMath &&
20847 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20849 Opcode = X86ISD::FMIN;
20852 // Converting this to a min would handle both negative zeros and NaNs
20853 // incorrectly, but we can swap the operands to fix both.
20854 std::swap(LHS, RHS);
20858 Opcode = X86ISD::FMIN;
20862 // Converting this to a max would handle NaNs incorrectly.
20863 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20865 Opcode = X86ISD::FMAX;
20868 // Converting this to a max would handle comparisons between positive
20869 // and negative zero incorrectly, and swapping the operands would
20870 // cause it to handle NaNs incorrectly.
20871 if (!DAG.getTarget().Options.UnsafeFPMath &&
20872 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20873 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20875 std::swap(LHS, RHS);
20877 Opcode = X86ISD::FMAX;
20880 // Converting this to a max would handle both negative zeros and NaNs
20881 // incorrectly, but we can swap the operands to fix both.
20882 std::swap(LHS, RHS);
20886 Opcode = X86ISD::FMAX;
20892 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20895 EVT CondVT = Cond.getValueType();
20896 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20897 CondVT.getVectorElementType() == MVT::i1) {
20898 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20899 // lowering on KNL. In this case we convert it to
20900 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20901 // The same situation for all 128 and 256-bit vectors of i8 and i16.
20902 // Since SKX these selects have a proper lowering.
20903 EVT OpVT = LHS.getValueType();
20904 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20905 (OpVT.getVectorElementType() == MVT::i8 ||
20906 OpVT.getVectorElementType() == MVT::i16) &&
20907 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
20908 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20909 DCI.AddToWorklist(Cond.getNode());
20910 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20913 // If this is a select between two integer constants, try to do some
20915 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20916 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20917 // Don't do this for crazy integer types.
20918 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20919 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20920 // so that TrueC (the true value) is larger than FalseC.
20921 bool NeedsCondInvert = false;
20923 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20924 // Efficiently invertible.
20925 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20926 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20927 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20928 NeedsCondInvert = true;
20929 std::swap(TrueC, FalseC);
20932 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20933 if (FalseC->getAPIntValue() == 0 &&
20934 TrueC->getAPIntValue().isPowerOf2()) {
20935 if (NeedsCondInvert) // Invert the condition if needed.
20936 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20937 DAG.getConstant(1, Cond.getValueType()));
20939 // Zero extend the condition if needed.
20940 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20942 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20943 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20944 DAG.getConstant(ShAmt, MVT::i8));
20947 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20948 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20949 if (NeedsCondInvert) // Invert the condition if needed.
20950 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20951 DAG.getConstant(1, Cond.getValueType()));
20953 // Zero extend the condition if needed.
20954 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20955 FalseC->getValueType(0), Cond);
20956 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20957 SDValue(FalseC, 0));
20960 // Optimize cases that will turn into an LEA instruction. This requires
20961 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20962 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20963 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20964 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20966 bool isFastMultiplier = false;
20968 switch ((unsigned char)Diff) {
20970 case 1: // result = add base, cond
20971 case 2: // result = lea base( , cond*2)
20972 case 3: // result = lea base(cond, cond*2)
20973 case 4: // result = lea base( , cond*4)
20974 case 5: // result = lea base(cond, cond*4)
20975 case 8: // result = lea base( , cond*8)
20976 case 9: // result = lea base(cond, cond*8)
20977 isFastMultiplier = true;
20982 if (isFastMultiplier) {
20983 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20984 if (NeedsCondInvert) // Invert the condition if needed.
20985 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20986 DAG.getConstant(1, Cond.getValueType()));
20988 // Zero extend the condition if needed.
20989 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20991 // Scale the condition by the difference.
20993 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20994 DAG.getConstant(Diff, Cond.getValueType()));
20996 // Add the base if non-zero.
20997 if (FalseC->getAPIntValue() != 0)
20998 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20999 SDValue(FalseC, 0));
21006 // Canonicalize max and min:
21007 // (x > y) ? x : y -> (x >= y) ? x : y
21008 // (x < y) ? x : y -> (x <= y) ? x : y
21009 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21010 // the need for an extra compare
21011 // against zero. e.g.
21012 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21014 // testl %edi, %edi
21016 // cmovgl %edi, %eax
21020 // cmovsl %eax, %edi
21021 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21022 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21023 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21024 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21029 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21030 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21031 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21032 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21037 // Early exit check
21038 if (!TLI.isTypeLegal(VT))
21041 // Match VSELECTs into subs with unsigned saturation.
21042 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21043 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21044 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21045 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21046 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21048 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21049 // left side invert the predicate to simplify logic below.
21051 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21053 CC = ISD::getSetCCInverse(CC, true);
21054 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21058 if (Other.getNode() && Other->getNumOperands() == 2 &&
21059 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21060 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21061 SDValue CondRHS = Cond->getOperand(1);
21063 // Look for a general sub with unsigned saturation first.
21064 // x >= y ? x-y : 0 --> subus x, y
21065 // x > y ? x-y : 0 --> subus x, y
21066 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21067 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21068 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21070 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21071 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21072 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21073 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21074 // If the RHS is a constant we have to reverse the const
21075 // canonicalization.
21076 // x > C-1 ? x+-C : 0 --> subus x, C
21077 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21078 CondRHSConst->getAPIntValue() ==
21079 (-OpRHSConst->getAPIntValue() - 1))
21080 return DAG.getNode(
21081 X86ISD::SUBUS, DL, VT, OpLHS,
21082 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21084 // Another special case: If C was a sign bit, the sub has been
21085 // canonicalized into a xor.
21086 // FIXME: Would it be better to use computeKnownBits to determine
21087 // whether it's safe to decanonicalize the xor?
21088 // x s< 0 ? x^C : 0 --> subus x, C
21089 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21090 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21091 OpRHSConst->getAPIntValue().isSignBit())
21092 // Note that we have to rebuild the RHS constant here to ensure we
21093 // don't rely on particular values of undef lanes.
21094 return DAG.getNode(
21095 X86ISD::SUBUS, DL, VT, OpLHS,
21096 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21101 // Try to match a min/max vector operation.
21102 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21103 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21104 unsigned Opc = ret.first;
21105 bool NeedSplit = ret.second;
21107 if (Opc && NeedSplit) {
21108 unsigned NumElems = VT.getVectorNumElements();
21109 // Extract the LHS vectors
21110 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21111 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21113 // Extract the RHS vectors
21114 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21115 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21117 // Create min/max for each subvector
21118 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21119 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21121 // Merge the result
21122 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21124 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21127 // Simplify vector selection if condition value type matches vselect
21129 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21130 assert(Cond.getValueType().isVector() &&
21131 "vector select expects a vector selector!");
21133 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21134 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21136 // Try invert the condition if true value is not all 1s and false value
21138 if (!TValIsAllOnes && !FValIsAllZeros &&
21139 // Check if the selector will be produced by CMPP*/PCMP*
21140 Cond.getOpcode() == ISD::SETCC &&
21141 // Check if SETCC has already been promoted
21142 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21143 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21144 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21146 if (TValIsAllZeros || FValIsAllOnes) {
21147 SDValue CC = Cond.getOperand(2);
21148 ISD::CondCode NewCC =
21149 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21150 Cond.getOperand(0).getValueType().isInteger());
21151 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21152 std::swap(LHS, RHS);
21153 TValIsAllOnes = FValIsAllOnes;
21154 FValIsAllZeros = TValIsAllZeros;
21158 if (TValIsAllOnes || FValIsAllZeros) {
21161 if (TValIsAllOnes && FValIsAllZeros)
21163 else if (TValIsAllOnes)
21164 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21165 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21166 else if (FValIsAllZeros)
21167 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21168 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21170 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21174 // We should generate an X86ISD::BLENDI from a vselect if its argument
21175 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21176 // constants. This specific pattern gets generated when we split a
21177 // selector for a 512 bit vector in a machine without AVX512 (but with
21178 // 256-bit vectors), during legalization:
21180 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21182 // Iff we find this pattern and the build_vectors are built from
21183 // constants, we translate the vselect into a shuffle_vector that we
21184 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21185 if ((N->getOpcode() == ISD::VSELECT ||
21186 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21187 !DCI.isBeforeLegalize()) {
21188 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21189 if (Shuffle.getNode())
21193 // If this is a *dynamic* select (non-constant condition) and we can match
21194 // this node with one of the variable blend instructions, restructure the
21195 // condition so that the blends can use the high bit of each element and use
21196 // SimplifyDemandedBits to simplify the condition operand.
21197 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21198 !DCI.isBeforeLegalize() &&
21199 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21200 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21202 // Don't optimize vector selects that map to mask-registers.
21206 // We can only handle the cases where VSELECT is directly legal on the
21207 // subtarget. We custom lower VSELECT nodes with constant conditions and
21208 // this makes it hard to see whether a dynamic VSELECT will correctly
21209 // lower, so we both check the operation's status and explicitly handle the
21210 // cases where a *dynamic* blend will fail even though a constant-condition
21211 // blend could be custom lowered.
21212 // FIXME: We should find a better way to handle this class of problems.
21213 // Potentially, we should combine constant-condition vselect nodes
21214 // pre-legalization into shuffles and not mark as many types as custom
21216 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21218 // FIXME: We don't support i16-element blends currently. We could and
21219 // should support them by making *all* the bits in the condition be set
21220 // rather than just the high bit and using an i8-element blend.
21221 if (VT.getScalarType() == MVT::i16)
21223 // Dynamic blending was only available from SSE4.1 onward.
21224 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21226 // Byte blends are only available in AVX2
21227 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21228 !Subtarget->hasAVX2())
21231 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21232 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21234 APInt KnownZero, KnownOne;
21235 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21236 DCI.isBeforeLegalizeOps());
21237 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21238 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21240 // If we changed the computation somewhere in the DAG, this change
21241 // will affect all users of Cond.
21242 // Make sure it is fine and update all the nodes so that we do not
21243 // use the generic VSELECT anymore. Otherwise, we may perform
21244 // wrong optimizations as we messed up with the actual expectation
21245 // for the vector boolean values.
21246 if (Cond != TLO.Old) {
21247 // Check all uses of that condition operand to check whether it will be
21248 // consumed by non-BLEND instructions, which may depend on all bits are
21250 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21252 if (I->getOpcode() != ISD::VSELECT)
21253 // TODO: Add other opcodes eventually lowered into BLEND.
21256 // Update all the users of the condition, before committing the change,
21257 // so that the VSELECT optimizations that expect the correct vector
21258 // boolean value will not be triggered.
21259 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21261 DAG.ReplaceAllUsesOfValueWith(
21263 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21264 Cond, I->getOperand(1), I->getOperand(2)));
21265 DCI.CommitTargetLoweringOpt(TLO);
21268 // At this point, only Cond is changed. Change the condition
21269 // just for N to keep the opportunity to optimize all other
21270 // users their own way.
21271 DAG.ReplaceAllUsesOfValueWith(
21273 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21274 TLO.New, N->getOperand(1), N->getOperand(2)));
21282 // Check whether a boolean test is testing a boolean value generated by
21283 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21286 // Simplify the following patterns:
21287 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21288 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21289 // to (Op EFLAGS Cond)
21291 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21292 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21293 // to (Op EFLAGS !Cond)
21295 // where Op could be BRCOND or CMOV.
21297 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21298 // Quit if not CMP and SUB with its value result used.
21299 if (Cmp.getOpcode() != X86ISD::CMP &&
21300 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21303 // Quit if not used as a boolean value.
21304 if (CC != X86::COND_E && CC != X86::COND_NE)
21307 // Check CMP operands. One of them should be 0 or 1 and the other should be
21308 // an SetCC or extended from it.
21309 SDValue Op1 = Cmp.getOperand(0);
21310 SDValue Op2 = Cmp.getOperand(1);
21313 const ConstantSDNode* C = nullptr;
21314 bool needOppositeCond = (CC == X86::COND_E);
21315 bool checkAgainstTrue = false; // Is it a comparison against 1?
21317 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21319 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21321 else // Quit if all operands are not constants.
21324 if (C->getZExtValue() == 1) {
21325 needOppositeCond = !needOppositeCond;
21326 checkAgainstTrue = true;
21327 } else if (C->getZExtValue() != 0)
21328 // Quit if the constant is neither 0 or 1.
21331 bool truncatedToBoolWithAnd = false;
21332 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21333 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21334 SetCC.getOpcode() == ISD::TRUNCATE ||
21335 SetCC.getOpcode() == ISD::AND) {
21336 if (SetCC.getOpcode() == ISD::AND) {
21338 ConstantSDNode *CS;
21339 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21340 CS->getZExtValue() == 1)
21342 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21343 CS->getZExtValue() == 1)
21347 SetCC = SetCC.getOperand(OpIdx);
21348 truncatedToBoolWithAnd = true;
21350 SetCC = SetCC.getOperand(0);
21353 switch (SetCC.getOpcode()) {
21354 case X86ISD::SETCC_CARRY:
21355 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21356 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21357 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21358 // truncated to i1 using 'and'.
21359 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21361 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21362 "Invalid use of SETCC_CARRY!");
21364 case X86ISD::SETCC:
21365 // Set the condition code or opposite one if necessary.
21366 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21367 if (needOppositeCond)
21368 CC = X86::GetOppositeBranchCondition(CC);
21369 return SetCC.getOperand(1);
21370 case X86ISD::CMOV: {
21371 // Check whether false/true value has canonical one, i.e. 0 or 1.
21372 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21373 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21374 // Quit if true value is not a constant.
21377 // Quit if false value is not a constant.
21379 SDValue Op = SetCC.getOperand(0);
21380 // Skip 'zext' or 'trunc' node.
21381 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21382 Op.getOpcode() == ISD::TRUNCATE)
21383 Op = Op.getOperand(0);
21384 // A special case for rdrand/rdseed, where 0 is set if false cond is
21386 if ((Op.getOpcode() != X86ISD::RDRAND &&
21387 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21390 // Quit if false value is not the constant 0 or 1.
21391 bool FValIsFalse = true;
21392 if (FVal && FVal->getZExtValue() != 0) {
21393 if (FVal->getZExtValue() != 1)
21395 // If FVal is 1, opposite cond is needed.
21396 needOppositeCond = !needOppositeCond;
21397 FValIsFalse = false;
21399 // Quit if TVal is not the constant opposite of FVal.
21400 if (FValIsFalse && TVal->getZExtValue() != 1)
21402 if (!FValIsFalse && TVal->getZExtValue() != 0)
21404 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21405 if (needOppositeCond)
21406 CC = X86::GetOppositeBranchCondition(CC);
21407 return SetCC.getOperand(3);
21414 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21416 /// (X86or (X86setcc) (X86setcc))
21417 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21418 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21419 X86::CondCode &CC1, SDValue &Flags,
21421 if (Cond->getOpcode() == X86ISD::CMP) {
21422 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21423 if (!CondOp1C || !CondOp1C->isNullValue())
21426 Cond = Cond->getOperand(0);
21431 SDValue SetCC0, SetCC1;
21432 switch (Cond->getOpcode()) {
21433 default: return false;
21440 SetCC0 = Cond->getOperand(0);
21441 SetCC1 = Cond->getOperand(1);
21445 // Make sure we have SETCC nodes, using the same flags value.
21446 if (SetCC0.getOpcode() != X86ISD::SETCC ||
21447 SetCC1.getOpcode() != X86ISD::SETCC ||
21448 SetCC0->getOperand(1) != SetCC1->getOperand(1))
21451 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
21452 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
21453 Flags = SetCC0->getOperand(1);
21457 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21458 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21459 TargetLowering::DAGCombinerInfo &DCI,
21460 const X86Subtarget *Subtarget) {
21463 // If the flag operand isn't dead, don't touch this CMOV.
21464 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21467 SDValue FalseOp = N->getOperand(0);
21468 SDValue TrueOp = N->getOperand(1);
21469 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21470 SDValue Cond = N->getOperand(3);
21472 if (CC == X86::COND_E || CC == X86::COND_NE) {
21473 switch (Cond.getOpcode()) {
21477 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21478 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21479 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21485 Flags = checkBoolTestSetCCCombine(Cond, CC);
21486 if (Flags.getNode() &&
21487 // Extra check as FCMOV only supports a subset of X86 cond.
21488 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21489 SDValue Ops[] = { FalseOp, TrueOp,
21490 DAG.getConstant(CC, MVT::i8), Flags };
21491 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21494 // If this is a select between two integer constants, try to do some
21495 // optimizations. Note that the operands are ordered the opposite of SELECT
21497 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21498 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21499 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21500 // larger than FalseC (the false value).
21501 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21502 CC = X86::GetOppositeBranchCondition(CC);
21503 std::swap(TrueC, FalseC);
21504 std::swap(TrueOp, FalseOp);
21507 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21508 // This is efficient for any integer data type (including i8/i16) and
21510 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21511 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21512 DAG.getConstant(CC, MVT::i8), Cond);
21514 // Zero extend the condition if needed.
21515 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21517 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21518 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21519 DAG.getConstant(ShAmt, MVT::i8));
21520 if (N->getNumValues() == 2) // Dead flag value?
21521 return DCI.CombineTo(N, Cond, SDValue());
21525 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21526 // for any integer data type, including i8/i16.
21527 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21528 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21529 DAG.getConstant(CC, MVT::i8), Cond);
21531 // Zero extend the condition if needed.
21532 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21533 FalseC->getValueType(0), Cond);
21534 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21535 SDValue(FalseC, 0));
21537 if (N->getNumValues() == 2) // Dead flag value?
21538 return DCI.CombineTo(N, Cond, SDValue());
21542 // Optimize cases that will turn into an LEA instruction. This requires
21543 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21544 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21545 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21546 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21548 bool isFastMultiplier = false;
21550 switch ((unsigned char)Diff) {
21552 case 1: // result = add base, cond
21553 case 2: // result = lea base( , cond*2)
21554 case 3: // result = lea base(cond, cond*2)
21555 case 4: // result = lea base( , cond*4)
21556 case 5: // result = lea base(cond, cond*4)
21557 case 8: // result = lea base( , cond*8)
21558 case 9: // result = lea base(cond, cond*8)
21559 isFastMultiplier = true;
21564 if (isFastMultiplier) {
21565 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21566 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21567 DAG.getConstant(CC, MVT::i8), Cond);
21568 // Zero extend the condition if needed.
21569 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21571 // Scale the condition by the difference.
21573 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21574 DAG.getConstant(Diff, Cond.getValueType()));
21576 // Add the base if non-zero.
21577 if (FalseC->getAPIntValue() != 0)
21578 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21579 SDValue(FalseC, 0));
21580 if (N->getNumValues() == 2) // Dead flag value?
21581 return DCI.CombineTo(N, Cond, SDValue());
21588 // Handle these cases:
21589 // (select (x != c), e, c) -> select (x != c), e, x),
21590 // (select (x == c), c, e) -> select (x == c), x, e)
21591 // where the c is an integer constant, and the "select" is the combination
21592 // of CMOV and CMP.
21594 // The rationale for this change is that the conditional-move from a constant
21595 // needs two instructions, however, conditional-move from a register needs
21596 // only one instruction.
21598 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21599 // some instruction-combining opportunities. This opt needs to be
21600 // postponed as late as possible.
21602 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21603 // the DCI.xxxx conditions are provided to postpone the optimization as
21604 // late as possible.
21606 ConstantSDNode *CmpAgainst = nullptr;
21607 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21608 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21609 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21611 if (CC == X86::COND_NE &&
21612 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21613 CC = X86::GetOppositeBranchCondition(CC);
21614 std::swap(TrueOp, FalseOp);
21617 if (CC == X86::COND_E &&
21618 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21619 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21620 DAG.getConstant(CC, MVT::i8), Cond };
21621 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21626 // Fold and/or of setcc's to double CMOV:
21627 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
21628 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
21630 // This combine lets us generate:
21631 // cmovcc1 (jcc1 if we don't have CMOV)
21637 // cmovne (jne if we don't have CMOV)
21638 // When we can't use the CMOV instruction, it might increase branch
21640 // When we can use CMOV, or when there is no mispredict, this improves
21641 // throughput and reduces register pressure.
21643 if (CC == X86::COND_NE) {
21645 X86::CondCode CC0, CC1;
21647 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
21649 std::swap(FalseOp, TrueOp);
21650 CC0 = X86::GetOppositeBranchCondition(CC0);
21651 CC1 = X86::GetOppositeBranchCondition(CC1);
21654 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, MVT::i8),
21656 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
21657 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, MVT::i8), Flags};
21658 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21659 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
21667 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21668 const X86Subtarget *Subtarget) {
21669 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21671 default: return SDValue();
21672 // SSE/AVX/AVX2 blend intrinsics.
21673 case Intrinsic::x86_avx2_pblendvb:
21674 // Don't try to simplify this intrinsic if we don't have AVX2.
21675 if (!Subtarget->hasAVX2())
21678 case Intrinsic::x86_avx_blendv_pd_256:
21679 case Intrinsic::x86_avx_blendv_ps_256:
21680 // Don't try to simplify this intrinsic if we don't have AVX.
21681 if (!Subtarget->hasAVX())
21684 case Intrinsic::x86_sse41_blendvps:
21685 case Intrinsic::x86_sse41_blendvpd:
21686 case Intrinsic::x86_sse41_pblendvb: {
21687 SDValue Op0 = N->getOperand(1);
21688 SDValue Op1 = N->getOperand(2);
21689 SDValue Mask = N->getOperand(3);
21691 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21692 if (!Subtarget->hasSSE41())
21695 // fold (blend A, A, Mask) -> A
21698 // fold (blend A, B, allZeros) -> A
21699 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21701 // fold (blend A, B, allOnes) -> B
21702 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21705 // Simplify the case where the mask is a constant i32 value.
21706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21707 if (C->isNullValue())
21709 if (C->isAllOnesValue())
21716 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21717 case Intrinsic::x86_sse2_psrai_w:
21718 case Intrinsic::x86_sse2_psrai_d:
21719 case Intrinsic::x86_avx2_psrai_w:
21720 case Intrinsic::x86_avx2_psrai_d:
21721 case Intrinsic::x86_sse2_psra_w:
21722 case Intrinsic::x86_sse2_psra_d:
21723 case Intrinsic::x86_avx2_psra_w:
21724 case Intrinsic::x86_avx2_psra_d: {
21725 SDValue Op0 = N->getOperand(1);
21726 SDValue Op1 = N->getOperand(2);
21727 EVT VT = Op0.getValueType();
21728 assert(VT.isVector() && "Expected a vector type!");
21730 if (isa<BuildVectorSDNode>(Op1))
21731 Op1 = Op1.getOperand(0);
21733 if (!isa<ConstantSDNode>(Op1))
21736 EVT SVT = VT.getVectorElementType();
21737 unsigned SVTBits = SVT.getSizeInBits();
21739 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21740 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21741 uint64_t ShAmt = C.getZExtValue();
21743 // Don't try to convert this shift into a ISD::SRA if the shift
21744 // count is bigger than or equal to the element size.
21745 if (ShAmt >= SVTBits)
21748 // Trivial case: if the shift count is zero, then fold this
21749 // into the first operand.
21753 // Replace this packed shift intrinsic with a target independent
21755 SDValue Splat = DAG.getConstant(C, VT);
21756 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21761 /// PerformMulCombine - Optimize a single multiply with constant into two
21762 /// in order to implement it with two cheaper instructions, e.g.
21763 /// LEA + SHL, LEA + LEA.
21764 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21765 TargetLowering::DAGCombinerInfo &DCI) {
21766 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21769 EVT VT = N->getValueType(0);
21770 if (VT != MVT::i64 && VT != MVT::i32)
21773 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21776 uint64_t MulAmt = C->getZExtValue();
21777 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21780 uint64_t MulAmt1 = 0;
21781 uint64_t MulAmt2 = 0;
21782 if ((MulAmt % 9) == 0) {
21784 MulAmt2 = MulAmt / 9;
21785 } else if ((MulAmt % 5) == 0) {
21787 MulAmt2 = MulAmt / 5;
21788 } else if ((MulAmt % 3) == 0) {
21790 MulAmt2 = MulAmt / 3;
21793 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21796 if (isPowerOf2_64(MulAmt2) &&
21797 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21798 // If second multiplifer is pow2, issue it first. We want the multiply by
21799 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21801 std::swap(MulAmt1, MulAmt2);
21804 if (isPowerOf2_64(MulAmt1))
21805 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21806 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21808 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21809 DAG.getConstant(MulAmt1, VT));
21811 if (isPowerOf2_64(MulAmt2))
21812 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21813 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21815 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21816 DAG.getConstant(MulAmt2, VT));
21818 // Do not add new nodes to DAG combiner worklist.
21819 DCI.CombineTo(N, NewMul, false);
21824 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21825 SDValue N0 = N->getOperand(0);
21826 SDValue N1 = N->getOperand(1);
21827 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21828 EVT VT = N0.getValueType();
21830 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21831 // since the result of setcc_c is all zero's or all ones.
21832 if (VT.isInteger() && !VT.isVector() &&
21833 N1C && N0.getOpcode() == ISD::AND &&
21834 N0.getOperand(1).getOpcode() == ISD::Constant) {
21835 SDValue N00 = N0.getOperand(0);
21836 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21837 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21838 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21839 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21840 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21841 APInt ShAmt = N1C->getAPIntValue();
21842 Mask = Mask.shl(ShAmt);
21844 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21845 N00, DAG.getConstant(Mask, VT));
21849 // Hardware support for vector shifts is sparse which makes us scalarize the
21850 // vector operations in many cases. Also, on sandybridge ADD is faster than
21852 // (shl V, 1) -> add V,V
21853 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21854 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21855 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21856 // We shift all of the values by one. In many cases we do not have
21857 // hardware support for this operation. This is better expressed as an ADD
21859 if (N1SplatC->getZExtValue() == 1)
21860 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21866 /// \brief Returns a vector of 0s if the node in input is a vector logical
21867 /// shift by a constant amount which is known to be bigger than or equal
21868 /// to the vector element size in bits.
21869 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21870 const X86Subtarget *Subtarget) {
21871 EVT VT = N->getValueType(0);
21873 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21874 (!Subtarget->hasInt256() ||
21875 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21878 SDValue Amt = N->getOperand(1);
21880 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21881 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21882 APInt ShiftAmt = AmtSplat->getAPIntValue();
21883 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21885 // SSE2/AVX2 logical shifts always return a vector of 0s
21886 // if the shift amount is bigger than or equal to
21887 // the element size. The constant shift amount will be
21888 // encoded as a 8-bit immediate.
21889 if (ShiftAmt.trunc(8).uge(MaxAmount))
21890 return getZeroVector(VT, Subtarget, DAG, DL);
21896 /// PerformShiftCombine - Combine shifts.
21897 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21898 TargetLowering::DAGCombinerInfo &DCI,
21899 const X86Subtarget *Subtarget) {
21900 if (N->getOpcode() == ISD::SHL) {
21901 SDValue V = PerformSHLCombine(N, DAG);
21902 if (V.getNode()) return V;
21905 if (N->getOpcode() != ISD::SRA) {
21906 // Try to fold this logical shift into a zero vector.
21907 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21908 if (V.getNode()) return V;
21914 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21915 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21916 // and friends. Likewise for OR -> CMPNEQSS.
21917 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21918 TargetLowering::DAGCombinerInfo &DCI,
21919 const X86Subtarget *Subtarget) {
21922 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21923 // we're requiring SSE2 for both.
21924 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21925 SDValue N0 = N->getOperand(0);
21926 SDValue N1 = N->getOperand(1);
21927 SDValue CMP0 = N0->getOperand(1);
21928 SDValue CMP1 = N1->getOperand(1);
21931 // The SETCCs should both refer to the same CMP.
21932 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21935 SDValue CMP00 = CMP0->getOperand(0);
21936 SDValue CMP01 = CMP0->getOperand(1);
21937 EVT VT = CMP00.getValueType();
21939 if (VT == MVT::f32 || VT == MVT::f64) {
21940 bool ExpectingFlags = false;
21941 // Check for any users that want flags:
21942 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21943 !ExpectingFlags && UI != UE; ++UI)
21944 switch (UI->getOpcode()) {
21949 ExpectingFlags = true;
21951 case ISD::CopyToReg:
21952 case ISD::SIGN_EXTEND:
21953 case ISD::ZERO_EXTEND:
21954 case ISD::ANY_EXTEND:
21958 if (!ExpectingFlags) {
21959 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21960 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21962 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21963 X86::CondCode tmp = cc0;
21968 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21969 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21970 // FIXME: need symbolic constants for these magic numbers.
21971 // See X86ATTInstPrinter.cpp:printSSECC().
21972 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21973 if (Subtarget->hasAVX512()) {
21974 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21975 CMP01, DAG.getConstant(x86cc, MVT::i8));
21976 if (N->getValueType(0) != MVT::i1)
21977 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21981 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21982 CMP00.getValueType(), CMP00, CMP01,
21983 DAG.getConstant(x86cc, MVT::i8));
21985 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21986 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21988 if (is64BitFP && !Subtarget->is64Bit()) {
21989 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21990 // 64-bit integer, since that's not a legal type. Since
21991 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21992 // bits, but can do this little dance to extract the lowest 32 bits
21993 // and work with those going forward.
21994 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21996 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21998 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21999 Vector32, DAG.getIntPtrConstant(0));
22003 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22004 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22005 DAG.getConstant(1, IntVT));
22006 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22007 return OneBitOfTruth;
22015 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22016 /// so it can be folded inside ANDNP.
22017 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22018 EVT VT = N->getValueType(0);
22020 // Match direct AllOnes for 128 and 256-bit vectors
22021 if (ISD::isBuildVectorAllOnes(N))
22024 // Look through a bit convert.
22025 if (N->getOpcode() == ISD::BITCAST)
22026 N = N->getOperand(0).getNode();
22028 // Sometimes the operand may come from a insert_subvector building a 256-bit
22030 if (VT.is256BitVector() &&
22031 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22032 SDValue V1 = N->getOperand(0);
22033 SDValue V2 = N->getOperand(1);
22035 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22036 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22037 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22038 ISD::isBuildVectorAllOnes(V2.getNode()))
22045 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22046 // register. In most cases we actually compare or select YMM-sized registers
22047 // and mixing the two types creates horrible code. This method optimizes
22048 // some of the transition sequences.
22049 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22050 TargetLowering::DAGCombinerInfo &DCI,
22051 const X86Subtarget *Subtarget) {
22052 EVT VT = N->getValueType(0);
22053 if (!VT.is256BitVector())
22056 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22057 N->getOpcode() == ISD::ZERO_EXTEND ||
22058 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22060 SDValue Narrow = N->getOperand(0);
22061 EVT NarrowVT = Narrow->getValueType(0);
22062 if (!NarrowVT.is128BitVector())
22065 if (Narrow->getOpcode() != ISD::XOR &&
22066 Narrow->getOpcode() != ISD::AND &&
22067 Narrow->getOpcode() != ISD::OR)
22070 SDValue N0 = Narrow->getOperand(0);
22071 SDValue N1 = Narrow->getOperand(1);
22074 // The Left side has to be a trunc.
22075 if (N0.getOpcode() != ISD::TRUNCATE)
22078 // The type of the truncated inputs.
22079 EVT WideVT = N0->getOperand(0)->getValueType(0);
22083 // The right side has to be a 'trunc' or a constant vector.
22084 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22085 ConstantSDNode *RHSConstSplat = nullptr;
22086 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22087 RHSConstSplat = RHSBV->getConstantSplatNode();
22088 if (!RHSTrunc && !RHSConstSplat)
22091 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22093 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22096 // Set N0 and N1 to hold the inputs to the new wide operation.
22097 N0 = N0->getOperand(0);
22098 if (RHSConstSplat) {
22099 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22100 SDValue(RHSConstSplat, 0));
22101 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22102 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22103 } else if (RHSTrunc) {
22104 N1 = N1->getOperand(0);
22107 // Generate the wide operation.
22108 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22109 unsigned Opcode = N->getOpcode();
22111 case ISD::ANY_EXTEND:
22113 case ISD::ZERO_EXTEND: {
22114 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22115 APInt Mask = APInt::getAllOnesValue(InBits);
22116 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22117 return DAG.getNode(ISD::AND, DL, VT,
22118 Op, DAG.getConstant(Mask, VT));
22120 case ISD::SIGN_EXTEND:
22121 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22122 Op, DAG.getValueType(NarrowVT));
22124 llvm_unreachable("Unexpected opcode");
22128 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22129 TargetLowering::DAGCombinerInfo &DCI,
22130 const X86Subtarget *Subtarget) {
22131 SDValue N0 = N->getOperand(0);
22132 SDValue N1 = N->getOperand(1);
22135 // A vector zext_in_reg may be represented as a shuffle,
22136 // feeding into a bitcast (this represents anyext) feeding into
22137 // an and with a mask.
22138 // We'd like to try to combine that into a shuffle with zero
22139 // plus a bitcast, removing the and.
22140 if (N0.getOpcode() != ISD::BITCAST ||
22141 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22144 // The other side of the AND should be a splat of 2^C, where C
22145 // is the number of bits in the source type.
22146 if (N1.getOpcode() == ISD::BITCAST)
22147 N1 = N1.getOperand(0);
22148 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22150 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22152 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22153 EVT SrcType = Shuffle->getValueType(0);
22155 // We expect a single-source shuffle
22156 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22159 unsigned SrcSize = SrcType.getScalarSizeInBits();
22161 APInt SplatValue, SplatUndef;
22162 unsigned SplatBitSize;
22164 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22165 SplatBitSize, HasAnyUndefs))
22168 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22169 // Make sure the splat matches the mask we expect
22170 if (SplatBitSize > ResSize ||
22171 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22174 // Make sure the input and output size make sense
22175 if (SrcSize >= ResSize || ResSize % SrcSize)
22178 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22179 // The number of u's between each two values depends on the ratio between
22180 // the source and dest type.
22181 unsigned ZextRatio = ResSize / SrcSize;
22182 bool IsZext = true;
22183 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22184 if (i % ZextRatio) {
22185 if (Shuffle->getMaskElt(i) > 0) {
22191 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22192 // Expected element number
22202 // Ok, perform the transformation - replace the shuffle with
22203 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22204 // (instead of undef) where the k elements come from the zero vector.
22205 SmallVector<int, 8> Mask;
22206 unsigned NumElems = SrcType.getVectorNumElements();
22207 for (unsigned i = 0; i < NumElems; ++i)
22209 Mask.push_back(NumElems);
22211 Mask.push_back(i / ZextRatio);
22213 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22214 Shuffle->getOperand(0), DAG.getConstant(0, SrcType), Mask);
22215 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22218 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22219 TargetLowering::DAGCombinerInfo &DCI,
22220 const X86Subtarget *Subtarget) {
22221 if (DCI.isBeforeLegalizeOps())
22224 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22227 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22230 EVT VT = N->getValueType(0);
22231 SDValue N0 = N->getOperand(0);
22232 SDValue N1 = N->getOperand(1);
22235 // Create BEXTR instructions
22236 // BEXTR is ((X >> imm) & (2**size-1))
22237 if (VT == MVT::i32 || VT == MVT::i64) {
22238 // Check for BEXTR.
22239 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22240 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22241 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22242 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22243 if (MaskNode && ShiftNode) {
22244 uint64_t Mask = MaskNode->getZExtValue();
22245 uint64_t Shift = ShiftNode->getZExtValue();
22246 if (isMask_64(Mask)) {
22247 uint64_t MaskSize = countPopulation(Mask);
22248 if (Shift + MaskSize <= VT.getSizeInBits())
22249 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22250 DAG.getConstant(Shift | (MaskSize << 8), VT));
22258 // Want to form ANDNP nodes:
22259 // 1) In the hopes of then easily combining them with OR and AND nodes
22260 // to form PBLEND/PSIGN.
22261 // 2) To match ANDN packed intrinsics
22262 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22265 // Check LHS for vnot
22266 if (N0.getOpcode() == ISD::XOR &&
22267 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22268 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22269 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22271 // Check RHS for vnot
22272 if (N1.getOpcode() == ISD::XOR &&
22273 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22274 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22275 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22280 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22281 TargetLowering::DAGCombinerInfo &DCI,
22282 const X86Subtarget *Subtarget) {
22283 if (DCI.isBeforeLegalizeOps())
22286 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22290 SDValue N0 = N->getOperand(0);
22291 SDValue N1 = N->getOperand(1);
22292 EVT VT = N->getValueType(0);
22294 // look for psign/blend
22295 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22296 if (!Subtarget->hasSSSE3() ||
22297 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22300 // Canonicalize pandn to RHS
22301 if (N0.getOpcode() == X86ISD::ANDNP)
22303 // or (and (m, y), (pandn m, x))
22304 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22305 SDValue Mask = N1.getOperand(0);
22306 SDValue X = N1.getOperand(1);
22308 if (N0.getOperand(0) == Mask)
22309 Y = N0.getOperand(1);
22310 if (N0.getOperand(1) == Mask)
22311 Y = N0.getOperand(0);
22313 // Check to see if the mask appeared in both the AND and ANDNP and
22317 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22318 // Look through mask bitcast.
22319 if (Mask.getOpcode() == ISD::BITCAST)
22320 Mask = Mask.getOperand(0);
22321 if (X.getOpcode() == ISD::BITCAST)
22322 X = X.getOperand(0);
22323 if (Y.getOpcode() == ISD::BITCAST)
22324 Y = Y.getOperand(0);
22326 EVT MaskVT = Mask.getValueType();
22328 // Validate that the Mask operand is a vector sra node.
22329 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22330 // there is no psrai.b
22331 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22332 unsigned SraAmt = ~0;
22333 if (Mask.getOpcode() == ISD::SRA) {
22334 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22335 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22336 SraAmt = AmtConst->getZExtValue();
22337 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22338 SDValue SraC = Mask.getOperand(1);
22339 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22341 if ((SraAmt + 1) != EltBits)
22346 // Now we know we at least have a plendvb with the mask val. See if
22347 // we can form a psignb/w/d.
22348 // psign = x.type == y.type == mask.type && y = sub(0, x);
22349 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22350 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22351 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22352 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22353 "Unsupported VT for PSIGN");
22354 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22355 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22357 // PBLENDVB only available on SSE 4.1
22358 if (!Subtarget->hasSSE41())
22361 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22363 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22364 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22365 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22366 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22367 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22371 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22374 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22375 MachineFunction &MF = DAG.getMachineFunction();
22377 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22379 // SHLD/SHRD instructions have lower register pressure, but on some
22380 // platforms they have higher latency than the equivalent
22381 // series of shifts/or that would otherwise be generated.
22382 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22383 // have higher latencies and we are not optimizing for size.
22384 if (!OptForSize && Subtarget->isSHLDSlow())
22387 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22389 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22391 if (!N0.hasOneUse() || !N1.hasOneUse())
22394 SDValue ShAmt0 = N0.getOperand(1);
22395 if (ShAmt0.getValueType() != MVT::i8)
22397 SDValue ShAmt1 = N1.getOperand(1);
22398 if (ShAmt1.getValueType() != MVT::i8)
22400 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22401 ShAmt0 = ShAmt0.getOperand(0);
22402 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22403 ShAmt1 = ShAmt1.getOperand(0);
22406 unsigned Opc = X86ISD::SHLD;
22407 SDValue Op0 = N0.getOperand(0);
22408 SDValue Op1 = N1.getOperand(0);
22409 if (ShAmt0.getOpcode() == ISD::SUB) {
22410 Opc = X86ISD::SHRD;
22411 std::swap(Op0, Op1);
22412 std::swap(ShAmt0, ShAmt1);
22415 unsigned Bits = VT.getSizeInBits();
22416 if (ShAmt1.getOpcode() == ISD::SUB) {
22417 SDValue Sum = ShAmt1.getOperand(0);
22418 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22419 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22420 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22421 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22422 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22423 return DAG.getNode(Opc, DL, VT,
22425 DAG.getNode(ISD::TRUNCATE, DL,
22428 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22429 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22431 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22432 return DAG.getNode(Opc, DL, VT,
22433 N0.getOperand(0), N1.getOperand(0),
22434 DAG.getNode(ISD::TRUNCATE, DL,
22441 // Generate NEG and CMOV for integer abs.
22442 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22443 EVT VT = N->getValueType(0);
22445 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22446 // 8-bit integer abs to NEG and CMOV.
22447 if (VT.isInteger() && VT.getSizeInBits() == 8)
22450 SDValue N0 = N->getOperand(0);
22451 SDValue N1 = N->getOperand(1);
22454 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22455 // and change it to SUB and CMOV.
22456 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22457 N0.getOpcode() == ISD::ADD &&
22458 N0.getOperand(1) == N1 &&
22459 N1.getOpcode() == ISD::SRA &&
22460 N1.getOperand(0) == N0.getOperand(0))
22461 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22462 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22463 // Generate SUB & CMOV.
22464 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22465 DAG.getConstant(0, VT), N0.getOperand(0));
22467 SDValue Ops[] = { N0.getOperand(0), Neg,
22468 DAG.getConstant(X86::COND_GE, MVT::i8),
22469 SDValue(Neg.getNode(), 1) };
22470 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22475 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22476 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22477 TargetLowering::DAGCombinerInfo &DCI,
22478 const X86Subtarget *Subtarget) {
22479 if (DCI.isBeforeLegalizeOps())
22482 if (Subtarget->hasCMov()) {
22483 SDValue RV = performIntegerAbsCombine(N, DAG);
22491 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22492 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22493 TargetLowering::DAGCombinerInfo &DCI,
22494 const X86Subtarget *Subtarget) {
22495 LoadSDNode *Ld = cast<LoadSDNode>(N);
22496 EVT RegVT = Ld->getValueType(0);
22497 EVT MemVT = Ld->getMemoryVT();
22499 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22501 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
22502 // into two 16-byte operations.
22503 ISD::LoadExtType Ext = Ld->getExtensionType();
22504 unsigned Alignment = Ld->getAlignment();
22505 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22506 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22507 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22508 unsigned NumElems = RegVT.getVectorNumElements();
22512 SDValue Ptr = Ld->getBasePtr();
22513 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22515 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22517 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22518 Ld->getPointerInfo(), Ld->isVolatile(),
22519 Ld->isNonTemporal(), Ld->isInvariant(),
22521 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22522 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22523 Ld->getPointerInfo(), Ld->isVolatile(),
22524 Ld->isNonTemporal(), Ld->isInvariant(),
22525 std::min(16U, Alignment));
22526 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22528 Load2.getValue(1));
22530 SDValue NewVec = DAG.getUNDEF(RegVT);
22531 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22532 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22533 return DCI.CombineTo(N, NewVec, TF, true);
22539 /// PerformMLOADCombine - Resolve extending loads
22540 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22541 TargetLowering::DAGCombinerInfo &DCI,
22542 const X86Subtarget *Subtarget) {
22543 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22544 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22547 EVT VT = Mld->getValueType(0);
22548 unsigned NumElems = VT.getVectorNumElements();
22549 EVT LdVT = Mld->getMemoryVT();
22552 assert(LdVT != VT && "Cannot extend to the same type");
22553 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22554 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22555 // From, To sizes and ElemCount must be pow of two
22556 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22557 "Unexpected size for extending masked load");
22559 unsigned SizeRatio = ToSz / FromSz;
22560 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22562 // Create a type on which we perform the shuffle
22563 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22564 LdVT.getScalarType(), NumElems*SizeRatio);
22565 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22567 // Convert Src0 value
22568 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22569 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22570 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22571 for (unsigned i = 0; i != NumElems; ++i)
22572 ShuffleVec[i] = i * SizeRatio;
22574 // Can't shuffle using an illegal type.
22575 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22576 && "WideVecVT should be legal");
22577 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22578 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22580 // Prepare the new mask
22582 SDValue Mask = Mld->getMask();
22583 if (Mask.getValueType() == VT) {
22584 // Mask and original value have the same type
22585 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22586 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22587 for (unsigned i = 0; i != NumElems; ++i)
22588 ShuffleVec[i] = i * SizeRatio;
22589 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22590 ShuffleVec[i] = NumElems*SizeRatio;
22591 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22592 DAG.getConstant(0, WideVecVT),
22596 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22597 unsigned WidenNumElts = NumElems*SizeRatio;
22598 unsigned MaskNumElts = VT.getVectorNumElements();
22599 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22602 unsigned NumConcat = WidenNumElts / MaskNumElts;
22603 SmallVector<SDValue, 16> Ops(NumConcat);
22604 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22606 for (unsigned i = 1; i != NumConcat; ++i)
22609 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22612 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22613 Mld->getBasePtr(), NewMask, WideSrc0,
22614 Mld->getMemoryVT(), Mld->getMemOperand(),
22616 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22617 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22620 /// PerformMSTORECombine - Resolve truncating stores
22621 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22622 const X86Subtarget *Subtarget) {
22623 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22624 if (!Mst->isTruncatingStore())
22627 EVT VT = Mst->getValue().getValueType();
22628 unsigned NumElems = VT.getVectorNumElements();
22629 EVT StVT = Mst->getMemoryVT();
22632 assert(StVT != VT && "Cannot truncate to the same type");
22633 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22634 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22636 // From, To sizes and ElemCount must be pow of two
22637 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22638 "Unexpected size for truncating masked store");
22639 // We are going to use the original vector elt for storing.
22640 // Accumulated smaller vector elements must be a multiple of the store size.
22641 assert (((NumElems * FromSz) % ToSz) == 0 &&
22642 "Unexpected ratio for truncating masked store");
22644 unsigned SizeRatio = FromSz / ToSz;
22645 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22647 // Create a type on which we perform the shuffle
22648 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22649 StVT.getScalarType(), NumElems*SizeRatio);
22651 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22653 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
22654 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22655 for (unsigned i = 0; i != NumElems; ++i)
22656 ShuffleVec[i] = i * SizeRatio;
22658 // Can't shuffle using an illegal type.
22659 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22660 && "WideVecVT should be legal");
22662 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22663 DAG.getUNDEF(WideVecVT),
22667 SDValue Mask = Mst->getMask();
22668 if (Mask.getValueType() == VT) {
22669 // Mask and original value have the same type
22670 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22671 for (unsigned i = 0; i != NumElems; ++i)
22672 ShuffleVec[i] = i * SizeRatio;
22673 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22674 ShuffleVec[i] = NumElems*SizeRatio;
22675 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22676 DAG.getConstant(0, WideVecVT),
22680 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22681 unsigned WidenNumElts = NumElems*SizeRatio;
22682 unsigned MaskNumElts = VT.getVectorNumElements();
22683 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22686 unsigned NumConcat = WidenNumElts / MaskNumElts;
22687 SmallVector<SDValue, 16> Ops(NumConcat);
22688 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22690 for (unsigned i = 1; i != NumConcat; ++i)
22693 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22696 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
22697 NewMask, StVT, Mst->getMemOperand(), false);
22699 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22700 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22701 const X86Subtarget *Subtarget) {
22702 StoreSDNode *St = cast<StoreSDNode>(N);
22703 EVT VT = St->getValue().getValueType();
22704 EVT StVT = St->getMemoryVT();
22706 SDValue StoredVal = St->getOperand(1);
22707 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22709 // If we are saving a concatenation of two XMM registers and 32-byte stores
22710 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
22711 unsigned Alignment = St->getAlignment();
22712 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22713 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22714 StVT == VT && !IsAligned) {
22715 unsigned NumElems = VT.getVectorNumElements();
22719 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22720 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22722 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22723 SDValue Ptr0 = St->getBasePtr();
22724 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22726 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22727 St->getPointerInfo(), St->isVolatile(),
22728 St->isNonTemporal(), Alignment);
22729 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22730 St->getPointerInfo(), St->isVolatile(),
22731 St->isNonTemporal(),
22732 std::min(16U, Alignment));
22733 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22736 // Optimize trunc store (of multiple scalars) to shuffle and store.
22737 // First, pack all of the elements in one place. Next, store to memory
22738 // in fewer chunks.
22739 if (St->isTruncatingStore() && VT.isVector()) {
22740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22741 unsigned NumElems = VT.getVectorNumElements();
22742 assert(StVT != VT && "Cannot truncate to the same type");
22743 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22744 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22746 // From, To sizes and ElemCount must be pow of two
22747 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22748 // We are going to use the original vector elt for storing.
22749 // Accumulated smaller vector elements must be a multiple of the store size.
22750 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22752 unsigned SizeRatio = FromSz / ToSz;
22754 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22756 // Create a type on which we perform the shuffle
22757 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22758 StVT.getScalarType(), NumElems*SizeRatio);
22760 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22762 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22763 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22764 for (unsigned i = 0; i != NumElems; ++i)
22765 ShuffleVec[i] = i * SizeRatio;
22767 // Can't shuffle using an illegal type.
22768 if (!TLI.isTypeLegal(WideVecVT))
22771 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22772 DAG.getUNDEF(WideVecVT),
22774 // At this point all of the data is stored at the bottom of the
22775 // register. We now need to save it to mem.
22777 // Find the largest store unit
22778 MVT StoreType = MVT::i8;
22779 for (MVT Tp : MVT::integer_valuetypes()) {
22780 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22784 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22785 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22786 (64 <= NumElems * ToSz))
22787 StoreType = MVT::f64;
22789 // Bitcast the original vector into a vector of store-size units
22790 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22791 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22792 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22793 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22794 SmallVector<SDValue, 8> Chains;
22795 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22796 TLI.getPointerTy());
22797 SDValue Ptr = St->getBasePtr();
22799 // Perform one or more big stores into memory.
22800 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22801 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22802 StoreType, ShuffWide,
22803 DAG.getIntPtrConstant(i));
22804 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22805 St->getPointerInfo(), St->isVolatile(),
22806 St->isNonTemporal(), St->getAlignment());
22807 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22808 Chains.push_back(Ch);
22811 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22814 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22815 // the FP state in cases where an emms may be missing.
22816 // A preferable solution to the general problem is to figure out the right
22817 // places to insert EMMS. This qualifies as a quick hack.
22819 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22820 if (VT.getSizeInBits() != 64)
22823 const Function *F = DAG.getMachineFunction().getFunction();
22824 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
22825 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22826 && Subtarget->hasSSE2();
22827 if ((VT.isVector() ||
22828 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22829 isa<LoadSDNode>(St->getValue()) &&
22830 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22831 St->getChain().hasOneUse() && !St->isVolatile()) {
22832 SDNode* LdVal = St->getValue().getNode();
22833 LoadSDNode *Ld = nullptr;
22834 int TokenFactorIndex = -1;
22835 SmallVector<SDValue, 8> Ops;
22836 SDNode* ChainVal = St->getChain().getNode();
22837 // Must be a store of a load. We currently handle two cases: the load
22838 // is a direct child, and it's under an intervening TokenFactor. It is
22839 // possible to dig deeper under nested TokenFactors.
22840 if (ChainVal == LdVal)
22841 Ld = cast<LoadSDNode>(St->getChain());
22842 else if (St->getValue().hasOneUse() &&
22843 ChainVal->getOpcode() == ISD::TokenFactor) {
22844 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22845 if (ChainVal->getOperand(i).getNode() == LdVal) {
22846 TokenFactorIndex = i;
22847 Ld = cast<LoadSDNode>(St->getValue());
22849 Ops.push_back(ChainVal->getOperand(i));
22853 if (!Ld || !ISD::isNormalLoad(Ld))
22856 // If this is not the MMX case, i.e. we are just turning i64 load/store
22857 // into f64 load/store, avoid the transformation if there are multiple
22858 // uses of the loaded value.
22859 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22864 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22865 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22867 if (Subtarget->is64Bit() || F64IsLegal) {
22868 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22869 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22870 Ld->getPointerInfo(), Ld->isVolatile(),
22871 Ld->isNonTemporal(), Ld->isInvariant(),
22872 Ld->getAlignment());
22873 SDValue NewChain = NewLd.getValue(1);
22874 if (TokenFactorIndex != -1) {
22875 Ops.push_back(NewChain);
22876 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22878 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22879 St->getPointerInfo(),
22880 St->isVolatile(), St->isNonTemporal(),
22881 St->getAlignment());
22884 // Otherwise, lower to two pairs of 32-bit loads / stores.
22885 SDValue LoAddr = Ld->getBasePtr();
22886 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22887 DAG.getConstant(4, MVT::i32));
22889 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22890 Ld->getPointerInfo(),
22891 Ld->isVolatile(), Ld->isNonTemporal(),
22892 Ld->isInvariant(), Ld->getAlignment());
22893 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22894 Ld->getPointerInfo().getWithOffset(4),
22895 Ld->isVolatile(), Ld->isNonTemporal(),
22897 MinAlign(Ld->getAlignment(), 4));
22899 SDValue NewChain = LoLd.getValue(1);
22900 if (TokenFactorIndex != -1) {
22901 Ops.push_back(LoLd);
22902 Ops.push_back(HiLd);
22903 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22906 LoAddr = St->getBasePtr();
22907 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22908 DAG.getConstant(4, MVT::i32));
22910 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22911 St->getPointerInfo(),
22912 St->isVolatile(), St->isNonTemporal(),
22913 St->getAlignment());
22914 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22915 St->getPointerInfo().getWithOffset(4),
22917 St->isNonTemporal(),
22918 MinAlign(St->getAlignment(), 4));
22919 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22924 /// Return 'true' if this vector operation is "horizontal"
22925 /// and return the operands for the horizontal operation in LHS and RHS. A
22926 /// horizontal operation performs the binary operation on successive elements
22927 /// of its first operand, then on successive elements of its second operand,
22928 /// returning the resulting values in a vector. For example, if
22929 /// A = < float a0, float a1, float a2, float a3 >
22931 /// B = < float b0, float b1, float b2, float b3 >
22932 /// then the result of doing a horizontal operation on A and B is
22933 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22934 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22935 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22936 /// set to A, RHS to B, and the routine returns 'true'.
22937 /// Note that the binary operation should have the property that if one of the
22938 /// operands is UNDEF then the result is UNDEF.
22939 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22940 // Look for the following pattern: if
22941 // A = < float a0, float a1, float a2, float a3 >
22942 // B = < float b0, float b1, float b2, float b3 >
22944 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22945 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22946 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22947 // which is A horizontal-op B.
22949 // At least one of the operands should be a vector shuffle.
22950 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22951 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22954 MVT VT = LHS.getSimpleValueType();
22956 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22957 "Unsupported vector type for horizontal add/sub");
22959 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22960 // operate independently on 128-bit lanes.
22961 unsigned NumElts = VT.getVectorNumElements();
22962 unsigned NumLanes = VT.getSizeInBits()/128;
22963 unsigned NumLaneElts = NumElts / NumLanes;
22964 assert((NumLaneElts % 2 == 0) &&
22965 "Vector type should have an even number of elements in each lane");
22966 unsigned HalfLaneElts = NumLaneElts/2;
22968 // View LHS in the form
22969 // LHS = VECTOR_SHUFFLE A, B, LMask
22970 // If LHS is not a shuffle then pretend it is the shuffle
22971 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22972 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22975 SmallVector<int, 16> LMask(NumElts);
22976 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22977 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22978 A = LHS.getOperand(0);
22979 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22980 B = LHS.getOperand(1);
22981 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22982 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22984 if (LHS.getOpcode() != ISD::UNDEF)
22986 for (unsigned i = 0; i != NumElts; ++i)
22990 // Likewise, view RHS in the form
22991 // RHS = VECTOR_SHUFFLE C, D, RMask
22993 SmallVector<int, 16> RMask(NumElts);
22994 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22995 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
22996 C = RHS.getOperand(0);
22997 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
22998 D = RHS.getOperand(1);
22999 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23000 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23002 if (RHS.getOpcode() != ISD::UNDEF)
23004 for (unsigned i = 0; i != NumElts; ++i)
23008 // Check that the shuffles are both shuffling the same vectors.
23009 if (!(A == C && B == D) && !(A == D && B == C))
23012 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23013 if (!A.getNode() && !B.getNode())
23016 // If A and B occur in reverse order in RHS, then "swap" them (which means
23017 // rewriting the mask).
23019 ShuffleVectorSDNode::commuteMask(RMask);
23021 // At this point LHS and RHS are equivalent to
23022 // LHS = VECTOR_SHUFFLE A, B, LMask
23023 // RHS = VECTOR_SHUFFLE A, B, RMask
23024 // Check that the masks correspond to performing a horizontal operation.
23025 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23026 for (unsigned i = 0; i != NumLaneElts; ++i) {
23027 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23029 // Ignore any UNDEF components.
23030 if (LIdx < 0 || RIdx < 0 ||
23031 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23032 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23035 // Check that successive elements are being operated on. If not, this is
23036 // not a horizontal operation.
23037 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23038 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23039 if (!(LIdx == Index && RIdx == Index + 1) &&
23040 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23045 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23046 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23050 /// Do target-specific dag combines on floating point adds.
23051 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23052 const X86Subtarget *Subtarget) {
23053 EVT VT = N->getValueType(0);
23054 SDValue LHS = N->getOperand(0);
23055 SDValue RHS = N->getOperand(1);
23057 // Try to synthesize horizontal adds from adds of shuffles.
23058 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23059 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23060 isHorizontalBinOp(LHS, RHS, true))
23061 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23065 /// Do target-specific dag combines on floating point subs.
23066 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23067 const X86Subtarget *Subtarget) {
23068 EVT VT = N->getValueType(0);
23069 SDValue LHS = N->getOperand(0);
23070 SDValue RHS = N->getOperand(1);
23072 // Try to synthesize horizontal subs from subs of shuffles.
23073 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23074 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23075 isHorizontalBinOp(LHS, RHS, false))
23076 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23080 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23081 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23082 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23084 // F[X]OR(0.0, x) -> x
23085 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23086 if (C->getValueAPF().isPosZero())
23087 return N->getOperand(1);
23089 // F[X]OR(x, 0.0) -> x
23090 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23091 if (C->getValueAPF().isPosZero())
23092 return N->getOperand(0);
23096 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23097 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23098 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23100 // Only perform optimizations if UnsafeMath is used.
23101 if (!DAG.getTarget().Options.UnsafeFPMath)
23104 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23105 // into FMINC and FMAXC, which are Commutative operations.
23106 unsigned NewOp = 0;
23107 switch (N->getOpcode()) {
23108 default: llvm_unreachable("unknown opcode");
23109 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23110 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23113 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23114 N->getOperand(0), N->getOperand(1));
23117 /// Do target-specific dag combines on X86ISD::FAND nodes.
23118 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23119 // FAND(0.0, x) -> 0.0
23120 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23121 if (C->getValueAPF().isPosZero())
23122 return N->getOperand(0);
23124 // FAND(x, 0.0) -> 0.0
23125 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23126 if (C->getValueAPF().isPosZero())
23127 return N->getOperand(1);
23132 /// Do target-specific dag combines on X86ISD::FANDN nodes
23133 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23134 // FANDN(0.0, x) -> x
23135 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23136 if (C->getValueAPF().isPosZero())
23137 return N->getOperand(1);
23139 // FANDN(x, 0.0) -> 0.0
23140 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23141 if (C->getValueAPF().isPosZero())
23142 return N->getOperand(1);
23147 static SDValue PerformBTCombine(SDNode *N,
23149 TargetLowering::DAGCombinerInfo &DCI) {
23150 // BT ignores high bits in the bit index operand.
23151 SDValue Op1 = N->getOperand(1);
23152 if (Op1.hasOneUse()) {
23153 unsigned BitWidth = Op1.getValueSizeInBits();
23154 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23155 APInt KnownZero, KnownOne;
23156 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23157 !DCI.isBeforeLegalizeOps());
23158 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23159 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23160 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23161 DCI.CommitTargetLoweringOpt(TLO);
23166 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23167 SDValue Op = N->getOperand(0);
23168 if (Op.getOpcode() == ISD::BITCAST)
23169 Op = Op.getOperand(0);
23170 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23171 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23172 VT.getVectorElementType().getSizeInBits() ==
23173 OpVT.getVectorElementType().getSizeInBits()) {
23174 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23179 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23180 const X86Subtarget *Subtarget) {
23181 EVT VT = N->getValueType(0);
23182 if (!VT.isVector())
23185 SDValue N0 = N->getOperand(0);
23186 SDValue N1 = N->getOperand(1);
23187 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23190 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23191 // both SSE and AVX2 since there is no sign-extended shift right
23192 // operation on a vector with 64-bit elements.
23193 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23194 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23195 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23196 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23197 SDValue N00 = N0.getOperand(0);
23199 // EXTLOAD has a better solution on AVX2,
23200 // it may be replaced with X86ISD::VSEXT node.
23201 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23202 if (!ISD::isNormalLoad(N00.getNode()))
23205 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23206 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23208 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23214 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23215 TargetLowering::DAGCombinerInfo &DCI,
23216 const X86Subtarget *Subtarget) {
23217 SDValue N0 = N->getOperand(0);
23218 EVT VT = N->getValueType(0);
23220 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23221 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23222 // This exposes the sext to the sdivrem lowering, so that it directly extends
23223 // from AH (which we otherwise need to do contortions to access).
23224 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23225 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
23227 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23228 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
23229 N0.getOperand(0), N0.getOperand(1));
23230 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23231 return R.getValue(1);
23234 if (!DCI.isBeforeLegalizeOps())
23237 if (!Subtarget->hasFp256())
23240 if (VT.isVector() && VT.getSizeInBits() == 256) {
23241 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23249 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23250 const X86Subtarget* Subtarget) {
23252 EVT VT = N->getValueType(0);
23254 // Let legalize expand this if it isn't a legal type yet.
23255 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23258 EVT ScalarVT = VT.getScalarType();
23259 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23260 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23263 SDValue A = N->getOperand(0);
23264 SDValue B = N->getOperand(1);
23265 SDValue C = N->getOperand(2);
23267 bool NegA = (A.getOpcode() == ISD::FNEG);
23268 bool NegB = (B.getOpcode() == ISD::FNEG);
23269 bool NegC = (C.getOpcode() == ISD::FNEG);
23271 // Negative multiplication when NegA xor NegB
23272 bool NegMul = (NegA != NegB);
23274 A = A.getOperand(0);
23276 B = B.getOperand(0);
23278 C = C.getOperand(0);
23282 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23284 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23286 return DAG.getNode(Opcode, dl, VT, A, B, C);
23289 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23290 TargetLowering::DAGCombinerInfo &DCI,
23291 const X86Subtarget *Subtarget) {
23292 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23293 // (and (i32 x86isd::setcc_carry), 1)
23294 // This eliminates the zext. This transformation is necessary because
23295 // ISD::SETCC is always legalized to i8.
23297 SDValue N0 = N->getOperand(0);
23298 EVT VT = N->getValueType(0);
23300 if (N0.getOpcode() == ISD::AND &&
23302 N0.getOperand(0).hasOneUse()) {
23303 SDValue N00 = N0.getOperand(0);
23304 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23305 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23306 if (!C || C->getZExtValue() != 1)
23308 return DAG.getNode(ISD::AND, dl, VT,
23309 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23310 N00.getOperand(0), N00.getOperand(1)),
23311 DAG.getConstant(1, VT));
23315 if (N0.getOpcode() == ISD::TRUNCATE &&
23317 N0.getOperand(0).hasOneUse()) {
23318 SDValue N00 = N0.getOperand(0);
23319 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23320 return DAG.getNode(ISD::AND, dl, VT,
23321 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23322 N00.getOperand(0), N00.getOperand(1)),
23323 DAG.getConstant(1, VT));
23326 if (VT.is256BitVector()) {
23327 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23332 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23333 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23334 // This exposes the zext to the udivrem lowering, so that it directly extends
23335 // from AH (which we otherwise need to do contortions to access).
23336 if (N0.getOpcode() == ISD::UDIVREM &&
23337 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23338 (VT == MVT::i32 || VT == MVT::i64)) {
23339 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23340 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23341 N0.getOperand(0), N0.getOperand(1));
23342 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23343 return R.getValue(1);
23349 // Optimize x == -y --> x+y == 0
23350 // x != -y --> x+y != 0
23351 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23352 const X86Subtarget* Subtarget) {
23353 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23354 SDValue LHS = N->getOperand(0);
23355 SDValue RHS = N->getOperand(1);
23356 EVT VT = N->getValueType(0);
23359 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23360 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23361 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23362 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), LHS.getValueType(), RHS,
23363 LHS.getOperand(1));
23364 return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
23365 DAG.getConstant(0, addV.getValueType()), CC);
23367 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23368 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23369 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23370 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), RHS.getValueType(), LHS,
23371 RHS.getOperand(1));
23372 return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
23373 DAG.getConstant(0, addV.getValueType()), CC);
23376 if (VT.getScalarType() == MVT::i1 &&
23377 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
23379 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23380 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23381 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23383 if (!IsSEXT0 || !IsVZero1) {
23384 // Swap the operands and update the condition code.
23385 std::swap(LHS, RHS);
23386 CC = ISD::getSetCCSwappedOperands(CC);
23388 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23389 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23390 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23393 if (IsSEXT0 && IsVZero1) {
23394 assert(VT == LHS.getOperand(0).getValueType() &&
23395 "Uexpected operand type");
23396 if (CC == ISD::SETGT)
23397 return DAG.getConstant(0, VT);
23398 if (CC == ISD::SETLE)
23399 return DAG.getConstant(1, VT);
23400 if (CC == ISD::SETEQ || CC == ISD::SETGE)
23401 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23403 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
23404 "Unexpected condition code!");
23405 return LHS.getOperand(0);
23412 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
23413 SelectionDAG &DAG) {
23415 MVT VT = Load->getSimpleValueType(0);
23416 MVT EVT = VT.getVectorElementType();
23417 SDValue Addr = Load->getOperand(1);
23418 SDValue NewAddr = DAG.getNode(
23419 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
23420 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
23423 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
23424 DAG.getMachineFunction().getMachineMemOperand(
23425 Load->getMemOperand(), 0, EVT.getStoreSize()));
23429 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23430 const X86Subtarget *Subtarget) {
23432 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23433 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23434 "X86insertps is only defined for v4x32");
23436 SDValue Ld = N->getOperand(1);
23437 if (MayFoldLoad(Ld)) {
23438 // Extract the countS bits from the immediate so we can get the proper
23439 // address when narrowing the vector load to a specific element.
23440 // When the second source op is a memory address, insertps doesn't use
23441 // countS and just gets an f32 from that address.
23442 unsigned DestIndex =
23443 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23445 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23447 // Create this as a scalar to vector to match the instruction pattern.
23448 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23449 // countS bits are ignored when loading from memory on insertps, which
23450 // means we don't need to explicitly set them to 0.
23451 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23452 LoadScalarToVector, N->getOperand(2));
23457 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
23458 SDValue V0 = N->getOperand(0);
23459 SDValue V1 = N->getOperand(1);
23461 EVT VT = N->getValueType(0);
23463 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23464 // operands and changing the mask to 1. This saves us a bunch of
23465 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23466 // x86InstrInfo knows how to commute this back after instruction selection
23467 // if it would help register allocation.
23469 // TODO: If optimizing for size or a processor that doesn't suffer from
23470 // partial register update stalls, this should be transformed into a MOVSD
23471 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23473 if (VT == MVT::v2f64)
23474 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23475 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23476 SDValue NewMask = DAG.getConstant(1, MVT::i8);
23477 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23483 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23484 // as "sbb reg,reg", since it can be extended without zext and produces
23485 // an all-ones bit which is more useful than 0/1 in some cases.
23486 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23489 return DAG.getNode(ISD::AND, DL, VT,
23490 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23491 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23492 DAG.getConstant(1, VT));
23493 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23494 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23495 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23496 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23499 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23500 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23501 TargetLowering::DAGCombinerInfo &DCI,
23502 const X86Subtarget *Subtarget) {
23504 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23505 SDValue EFLAGS = N->getOperand(1);
23507 if (CC == X86::COND_A) {
23508 // Try to convert COND_A into COND_B in an attempt to facilitate
23509 // materializing "setb reg".
23511 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23512 // cannot take an immediate as its first operand.
23514 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23515 EFLAGS.getValueType().isInteger() &&
23516 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23517 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23518 EFLAGS.getNode()->getVTList(),
23519 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23520 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23521 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23525 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23526 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23528 if (CC == X86::COND_B)
23529 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23533 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23534 if (Flags.getNode()) {
23535 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23536 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23542 // Optimize branch condition evaluation.
23544 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23545 TargetLowering::DAGCombinerInfo &DCI,
23546 const X86Subtarget *Subtarget) {
23548 SDValue Chain = N->getOperand(0);
23549 SDValue Dest = N->getOperand(1);
23550 SDValue EFLAGS = N->getOperand(3);
23551 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23555 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23556 if (Flags.getNode()) {
23557 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23558 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23565 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23566 SelectionDAG &DAG) {
23567 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23568 // optimize away operation when it's from a constant.
23570 // The general transformation is:
23571 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23572 // AND(VECTOR_CMP(x,y), constant2)
23573 // constant2 = UNARYOP(constant)
23575 // Early exit if this isn't a vector operation, the operand of the
23576 // unary operation isn't a bitwise AND, or if the sizes of the operations
23577 // aren't the same.
23578 EVT VT = N->getValueType(0);
23579 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23580 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23581 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23584 // Now check that the other operand of the AND is a constant. We could
23585 // make the transformation for non-constant splats as well, but it's unclear
23586 // that would be a benefit as it would not eliminate any operations, just
23587 // perform one more step in scalar code before moving to the vector unit.
23588 if (BuildVectorSDNode *BV =
23589 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23590 // Bail out if the vector isn't a constant.
23591 if (!BV->isConstant())
23594 // Everything checks out. Build up the new and improved node.
23596 EVT IntVT = BV->getValueType(0);
23597 // Create a new constant of the appropriate type for the transformed
23599 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23600 // The AND node needs bitcasts to/from an integer vector type around it.
23601 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23602 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23603 N->getOperand(0)->getOperand(0), MaskConst);
23604 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23611 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23612 const X86Subtarget *Subtarget) {
23613 // First try to optimize away the conversion entirely when it's
23614 // conditionally from a constant. Vectors only.
23615 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23616 if (Res != SDValue())
23619 // Now move on to more general possibilities.
23620 SDValue Op0 = N->getOperand(0);
23621 EVT InVT = Op0->getValueType(0);
23623 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23624 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23626 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23627 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23628 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23631 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23632 // a 32-bit target where SSE doesn't support i64->FP operations.
23633 if (Op0.getOpcode() == ISD::LOAD) {
23634 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23635 EVT VT = Ld->getValueType(0);
23636 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23637 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23638 !Subtarget->is64Bit() && VT == MVT::i64) {
23639 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
23640 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
23641 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23648 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23649 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23650 X86TargetLowering::DAGCombinerInfo &DCI) {
23651 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23652 // the result is either zero or one (depending on the input carry bit).
23653 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23654 if (X86::isZeroNode(N->getOperand(0)) &&
23655 X86::isZeroNode(N->getOperand(1)) &&
23656 // We don't have a good way to replace an EFLAGS use, so only do this when
23658 SDValue(N, 1).use_empty()) {
23660 EVT VT = N->getValueType(0);
23661 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23662 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23663 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23664 DAG.getConstant(X86::COND_B,MVT::i8),
23666 DAG.getConstant(1, VT));
23667 return DCI.CombineTo(N, Res1, CarryOut);
23673 // fold (add Y, (sete X, 0)) -> adc 0, Y
23674 // (add Y, (setne X, 0)) -> sbb -1, Y
23675 // (sub (sete X, 0), Y) -> sbb 0, Y
23676 // (sub (setne X, 0), Y) -> adc -1, Y
23677 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23680 // Look through ZExts.
23681 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23682 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23685 SDValue SetCC = Ext.getOperand(0);
23686 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23689 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23690 if (CC != X86::COND_E && CC != X86::COND_NE)
23693 SDValue Cmp = SetCC.getOperand(1);
23694 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23695 !X86::isZeroNode(Cmp.getOperand(1)) ||
23696 !Cmp.getOperand(0).getValueType().isInteger())
23699 SDValue CmpOp0 = Cmp.getOperand(0);
23700 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23701 DAG.getConstant(1, CmpOp0.getValueType()));
23703 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23704 if (CC == X86::COND_NE)
23705 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23706 DL, OtherVal.getValueType(), OtherVal,
23707 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23708 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23709 DL, OtherVal.getValueType(), OtherVal,
23710 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23713 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23714 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23715 const X86Subtarget *Subtarget) {
23716 EVT VT = N->getValueType(0);
23717 SDValue Op0 = N->getOperand(0);
23718 SDValue Op1 = N->getOperand(1);
23720 // Try to synthesize horizontal adds from adds of shuffles.
23721 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23722 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23723 isHorizontalBinOp(Op0, Op1, true))
23724 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23726 return OptimizeConditionalInDecrement(N, DAG);
23729 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23730 const X86Subtarget *Subtarget) {
23731 SDValue Op0 = N->getOperand(0);
23732 SDValue Op1 = N->getOperand(1);
23734 // X86 can't encode an immediate LHS of a sub. See if we can push the
23735 // negation into a preceding instruction.
23736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23737 // If the RHS of the sub is a XOR with one use and a constant, invert the
23738 // immediate. Then add one to the LHS of the sub so we can turn
23739 // X-Y -> X+~Y+1, saving one register.
23740 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23741 isa<ConstantSDNode>(Op1.getOperand(1))) {
23742 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23743 EVT VT = Op0.getValueType();
23744 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23746 DAG.getConstant(~XorC, VT));
23747 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23748 DAG.getConstant(C->getAPIntValue()+1, VT));
23752 // Try to synthesize horizontal adds from adds of shuffles.
23753 EVT VT = N->getValueType(0);
23754 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23755 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23756 isHorizontalBinOp(Op0, Op1, true))
23757 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23759 return OptimizeConditionalInDecrement(N, DAG);
23762 /// performVZEXTCombine - Performs build vector combines
23763 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23764 TargetLowering::DAGCombinerInfo &DCI,
23765 const X86Subtarget *Subtarget) {
23767 MVT VT = N->getSimpleValueType(0);
23768 SDValue Op = N->getOperand(0);
23769 MVT OpVT = Op.getSimpleValueType();
23770 MVT OpEltVT = OpVT.getVectorElementType();
23771 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
23773 // (vzext (bitcast (vzext (x)) -> (vzext x)
23775 while (V.getOpcode() == ISD::BITCAST)
23776 V = V.getOperand(0);
23778 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
23779 MVT InnerVT = V.getSimpleValueType();
23780 MVT InnerEltVT = InnerVT.getVectorElementType();
23782 // If the element sizes match exactly, we can just do one larger vzext. This
23783 // is always an exact type match as vzext operates on integer types.
23784 if (OpEltVT == InnerEltVT) {
23785 assert(OpVT == InnerVT && "Types must match for vzext!");
23786 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
23789 // The only other way we can combine them is if only a single element of the
23790 // inner vzext is used in the input to the outer vzext.
23791 if (InnerEltVT.getSizeInBits() < InputBits)
23794 // In this case, the inner vzext is completely dead because we're going to
23795 // only look at bits inside of the low element. Just do the outer vzext on
23796 // a bitcast of the input to the inner.
23797 return DAG.getNode(X86ISD::VZEXT, DL, VT,
23798 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
23801 // Check if we can bypass extracting and re-inserting an element of an input
23802 // vector. Essentialy:
23803 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
23804 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
23805 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
23806 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
23807 SDValue ExtractedV = V.getOperand(0);
23808 SDValue OrigV = ExtractedV.getOperand(0);
23809 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
23810 if (ExtractIdx->getZExtValue() == 0) {
23811 MVT OrigVT = OrigV.getSimpleValueType();
23812 // Extract a subvector if necessary...
23813 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
23814 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
23815 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
23816 OrigVT.getVectorNumElements() / Ratio);
23817 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
23818 DAG.getIntPtrConstant(0));
23820 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
23821 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
23828 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23829 DAGCombinerInfo &DCI) const {
23830 SelectionDAG &DAG = DCI.DAG;
23831 switch (N->getOpcode()) {
23833 case ISD::EXTRACT_VECTOR_ELT:
23834 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23837 case X86ISD::SHRUNKBLEND:
23838 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23839 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
23840 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23841 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23842 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23843 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23844 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23847 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23848 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23849 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23850 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23851 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23852 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
23853 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23854 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
23855 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
23856 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23857 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23859 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23861 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23862 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23863 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23864 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23865 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23866 case ISD::ANY_EXTEND:
23867 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23868 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23869 case ISD::SIGN_EXTEND_INREG:
23870 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23871 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23872 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23873 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23874 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23875 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23876 case X86ISD::SHUFP: // Handle all target specific shuffles
23877 case X86ISD::PALIGNR:
23878 case X86ISD::UNPCKH:
23879 case X86ISD::UNPCKL:
23880 case X86ISD::MOVHLPS:
23881 case X86ISD::MOVLHPS:
23882 case X86ISD::PSHUFB:
23883 case X86ISD::PSHUFD:
23884 case X86ISD::PSHUFHW:
23885 case X86ISD::PSHUFLW:
23886 case X86ISD::MOVSS:
23887 case X86ISD::MOVSD:
23888 case X86ISD::VPERMILPI:
23889 case X86ISD::VPERM2X128:
23890 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23891 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23892 case ISD::INTRINSIC_WO_CHAIN:
23893 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23894 case X86ISD::INSERTPS: {
23895 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
23896 return PerformINSERTPSCombine(N, DAG, Subtarget);
23899 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
23900 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23906 /// isTypeDesirableForOp - Return true if the target has native support for
23907 /// the specified value type and it is 'desirable' to use the type for the
23908 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23909 /// instruction encodings are longer and some i16 instructions are slow.
23910 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23911 if (!isTypeLegal(VT))
23913 if (VT != MVT::i16)
23920 case ISD::SIGN_EXTEND:
23921 case ISD::ZERO_EXTEND:
23922 case ISD::ANY_EXTEND:
23935 /// IsDesirableToPromoteOp - This method query the target whether it is
23936 /// beneficial for dag combiner to promote the specified node. If true, it
23937 /// should return the desired promotion type by reference.
23938 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23939 EVT VT = Op.getValueType();
23940 if (VT != MVT::i16)
23943 bool Promote = false;
23944 bool Commute = false;
23945 switch (Op.getOpcode()) {
23948 LoadSDNode *LD = cast<LoadSDNode>(Op);
23949 // If the non-extending load has a single use and it's not live out, then it
23950 // might be folded.
23951 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23952 Op.hasOneUse()*/) {
23953 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23954 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23955 // The only case where we'd want to promote LOAD (rather then it being
23956 // promoted as an operand is when it's only use is liveout.
23957 if (UI->getOpcode() != ISD::CopyToReg)
23964 case ISD::SIGN_EXTEND:
23965 case ISD::ZERO_EXTEND:
23966 case ISD::ANY_EXTEND:
23971 SDValue N0 = Op.getOperand(0);
23972 // Look out for (store (shl (load), x)).
23973 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23986 SDValue N0 = Op.getOperand(0);
23987 SDValue N1 = Op.getOperand(1);
23988 if (!Commute && MayFoldLoad(N1))
23990 // Avoid disabling potential load folding opportunities.
23991 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
23993 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24003 //===----------------------------------------------------------------------===//
24004 // X86 Inline Assembly Support
24005 //===----------------------------------------------------------------------===//
24007 // Helper to match a string separated by whitespace.
24008 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24009 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24011 for (StringRef Piece : Pieces) {
24012 if (!S.startswith(Piece)) // Check if the piece matches.
24015 S = S.substr(Piece.size());
24016 StringRef::size_type Pos = S.find_first_not_of(" \t");
24017 if (Pos == 0) // We matched a prefix.
24026 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24028 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24029 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24030 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24031 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24033 if (AsmPieces.size() == 3)
24035 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24042 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24043 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24045 std::string AsmStr = IA->getAsmString();
24047 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24048 if (!Ty || Ty->getBitWidth() % 16 != 0)
24051 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24052 SmallVector<StringRef, 4> AsmPieces;
24053 SplitString(AsmStr, AsmPieces, ";\n");
24055 switch (AsmPieces.size()) {
24056 default: return false;
24058 // FIXME: this should verify that we are targeting a 486 or better. If not,
24059 // we will turn this bswap into something that will be lowered to logical
24060 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24061 // lower so don't worry about this.
24063 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24064 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24065 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24066 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24067 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24068 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24069 // No need to check constraints, nothing other than the equivalent of
24070 // "=r,0" would be valid here.
24071 return IntrinsicLowering::LowerToByteSwap(CI);
24074 // rorw $$8, ${0:w} --> llvm.bswap.i16
24075 if (CI->getType()->isIntegerTy(16) &&
24076 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24077 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24078 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24080 const std::string &ConstraintsStr = IA->getConstraintString();
24081 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24082 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24083 if (clobbersFlagRegisters(AsmPieces))
24084 return IntrinsicLowering::LowerToByteSwap(CI);
24088 if (CI->getType()->isIntegerTy(32) &&
24089 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24090 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24091 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24092 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24094 const std::string &ConstraintsStr = IA->getConstraintString();
24095 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24096 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24097 if (clobbersFlagRegisters(AsmPieces))
24098 return IntrinsicLowering::LowerToByteSwap(CI);
24101 if (CI->getType()->isIntegerTy(64)) {
24102 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24103 if (Constraints.size() >= 2 &&
24104 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24105 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24106 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24107 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24108 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24109 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24110 return IntrinsicLowering::LowerToByteSwap(CI);
24118 /// getConstraintType - Given a constraint letter, return the type of
24119 /// constraint it is for this target.
24120 X86TargetLowering::ConstraintType
24121 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24122 if (Constraint.size() == 1) {
24123 switch (Constraint[0]) {
24134 return C_RegisterClass;
24158 return TargetLowering::getConstraintType(Constraint);
24161 /// Examine constraint type and operand type and determine a weight value.
24162 /// This object must already have been set up with the operand type
24163 /// and the current alternative constraint selected.
24164 TargetLowering::ConstraintWeight
24165 X86TargetLowering::getSingleConstraintMatchWeight(
24166 AsmOperandInfo &info, const char *constraint) const {
24167 ConstraintWeight weight = CW_Invalid;
24168 Value *CallOperandVal = info.CallOperandVal;
24169 // If we don't have a value, we can't do a match,
24170 // but allow it at the lowest weight.
24171 if (!CallOperandVal)
24173 Type *type = CallOperandVal->getType();
24174 // Look at the constraint type.
24175 switch (*constraint) {
24177 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24188 if (CallOperandVal->getType()->isIntegerTy())
24189 weight = CW_SpecificReg;
24194 if (type->isFloatingPointTy())
24195 weight = CW_SpecificReg;
24198 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24199 weight = CW_SpecificReg;
24203 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24204 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24205 weight = CW_Register;
24208 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24209 if (C->getZExtValue() <= 31)
24210 weight = CW_Constant;
24214 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24215 if (C->getZExtValue() <= 63)
24216 weight = CW_Constant;
24220 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24221 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24222 weight = CW_Constant;
24226 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24227 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24228 weight = CW_Constant;
24232 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24233 if (C->getZExtValue() <= 3)
24234 weight = CW_Constant;
24238 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24239 if (C->getZExtValue() <= 0xff)
24240 weight = CW_Constant;
24245 if (dyn_cast<ConstantFP>(CallOperandVal)) {
24246 weight = CW_Constant;
24250 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24251 if ((C->getSExtValue() >= -0x80000000LL) &&
24252 (C->getSExtValue() <= 0x7fffffffLL))
24253 weight = CW_Constant;
24257 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24258 if (C->getZExtValue() <= 0xffffffff)
24259 weight = CW_Constant;
24266 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24267 /// with another that has more specific requirements based on the type of the
24268 /// corresponding operand.
24269 const char *X86TargetLowering::
24270 LowerXConstraint(EVT ConstraintVT) const {
24271 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24272 // 'f' like normal targets.
24273 if (ConstraintVT.isFloatingPoint()) {
24274 if (Subtarget->hasSSE2())
24276 if (Subtarget->hasSSE1())
24280 return TargetLowering::LowerXConstraint(ConstraintVT);
24283 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24284 /// vector. If it is invalid, don't add anything to Ops.
24285 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24286 std::string &Constraint,
24287 std::vector<SDValue>&Ops,
24288 SelectionDAG &DAG) const {
24291 // Only support length 1 constraints for now.
24292 if (Constraint.length() > 1) return;
24294 char ConstraintLetter = Constraint[0];
24295 switch (ConstraintLetter) {
24298 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24299 if (C->getZExtValue() <= 31) {
24300 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24306 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24307 if (C->getZExtValue() <= 63) {
24308 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24314 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24315 if (isInt<8>(C->getSExtValue())) {
24316 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24323 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24324 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24325 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
24331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24332 if (C->getZExtValue() <= 3) {
24333 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24339 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24340 if (C->getZExtValue() <= 255) {
24341 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24347 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24348 if (C->getZExtValue() <= 127) {
24349 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24355 // 32-bit signed value
24356 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24357 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24358 C->getSExtValue())) {
24359 // Widen to 64 bits here to get it sign extended.
24360 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24363 // FIXME gcc accepts some relocatable values here too, but only in certain
24364 // memory models; it's complicated.
24369 // 32-bit unsigned value
24370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24371 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24372 C->getZExtValue())) {
24373 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24377 // FIXME gcc accepts some relocatable values here too, but only in certain
24378 // memory models; it's complicated.
24382 // Literal immediates are always ok.
24383 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24384 // Widen to 64 bits here to get it sign extended.
24385 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24389 // In any sort of PIC mode addresses need to be computed at runtime by
24390 // adding in a register or some sort of table lookup. These can't
24391 // be used as immediates.
24392 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24395 // If we are in non-pic codegen mode, we allow the address of a global (with
24396 // an optional displacement) to be used with 'i'.
24397 GlobalAddressSDNode *GA = nullptr;
24398 int64_t Offset = 0;
24400 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24402 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24403 Offset += GA->getOffset();
24405 } else if (Op.getOpcode() == ISD::ADD) {
24406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24407 Offset += C->getZExtValue();
24408 Op = Op.getOperand(0);
24411 } else if (Op.getOpcode() == ISD::SUB) {
24412 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24413 Offset += -C->getZExtValue();
24414 Op = Op.getOperand(0);
24419 // Otherwise, this isn't something we can handle, reject it.
24423 const GlobalValue *GV = GA->getGlobal();
24424 // If we require an extra load to get this address, as in PIC mode, we
24425 // can't accept it.
24426 if (isGlobalStubReference(
24427 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24430 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24431 GA->getValueType(0), Offset);
24436 if (Result.getNode()) {
24437 Ops.push_back(Result);
24440 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24443 std::pair<unsigned, const TargetRegisterClass *>
24444 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
24445 const std::string &Constraint,
24447 // First, see if this is a constraint that directly corresponds to an LLVM
24449 if (Constraint.size() == 1) {
24450 // GCC Constraint Letters
24451 switch (Constraint[0]) {
24453 // TODO: Slight differences here in allocation order and leaving
24454 // RIP in the class. Do they matter any more here than they do
24455 // in the normal allocation?
24456 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24457 if (Subtarget->is64Bit()) {
24458 if (VT == MVT::i32 || VT == MVT::f32)
24459 return std::make_pair(0U, &X86::GR32RegClass);
24460 if (VT == MVT::i16)
24461 return std::make_pair(0U, &X86::GR16RegClass);
24462 if (VT == MVT::i8 || VT == MVT::i1)
24463 return std::make_pair(0U, &X86::GR8RegClass);
24464 if (VT == MVT::i64 || VT == MVT::f64)
24465 return std::make_pair(0U, &X86::GR64RegClass);
24468 // 32-bit fallthrough
24469 case 'Q': // Q_REGS
24470 if (VT == MVT::i32 || VT == MVT::f32)
24471 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24472 if (VT == MVT::i16)
24473 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24474 if (VT == MVT::i8 || VT == MVT::i1)
24475 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24476 if (VT == MVT::i64)
24477 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24479 case 'r': // GENERAL_REGS
24480 case 'l': // INDEX_REGS
24481 if (VT == MVT::i8 || VT == MVT::i1)
24482 return std::make_pair(0U, &X86::GR8RegClass);
24483 if (VT == MVT::i16)
24484 return std::make_pair(0U, &X86::GR16RegClass);
24485 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24486 return std::make_pair(0U, &X86::GR32RegClass);
24487 return std::make_pair(0U, &X86::GR64RegClass);
24488 case 'R': // LEGACY_REGS
24489 if (VT == MVT::i8 || VT == MVT::i1)
24490 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24491 if (VT == MVT::i16)
24492 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24493 if (VT == MVT::i32 || !Subtarget->is64Bit())
24494 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24495 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24496 case 'f': // FP Stack registers.
24497 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24498 // value to the correct fpstack register class.
24499 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24500 return std::make_pair(0U, &X86::RFP32RegClass);
24501 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24502 return std::make_pair(0U, &X86::RFP64RegClass);
24503 return std::make_pair(0U, &X86::RFP80RegClass);
24504 case 'y': // MMX_REGS if MMX allowed.
24505 if (!Subtarget->hasMMX()) break;
24506 return std::make_pair(0U, &X86::VR64RegClass);
24507 case 'Y': // SSE_REGS if SSE2 allowed
24508 if (!Subtarget->hasSSE2()) break;
24510 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24511 if (!Subtarget->hasSSE1()) break;
24513 switch (VT.SimpleTy) {
24515 // Scalar SSE types.
24518 return std::make_pair(0U, &X86::FR32RegClass);
24521 return std::make_pair(0U, &X86::FR64RegClass);
24529 return std::make_pair(0U, &X86::VR128RegClass);
24537 return std::make_pair(0U, &X86::VR256RegClass);
24542 return std::make_pair(0U, &X86::VR512RegClass);
24548 // Use the default implementation in TargetLowering to convert the register
24549 // constraint into a member of a register class.
24550 std::pair<unsigned, const TargetRegisterClass*> Res;
24551 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
24553 // Not found as a standard register?
24555 // Map st(0) -> st(7) -> ST0
24556 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24557 tolower(Constraint[1]) == 's' &&
24558 tolower(Constraint[2]) == 't' &&
24559 Constraint[3] == '(' &&
24560 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24561 Constraint[5] == ')' &&
24562 Constraint[6] == '}') {
24564 Res.first = X86::FP0+Constraint[4]-'0';
24565 Res.second = &X86::RFP80RegClass;
24569 // GCC allows "st(0)" to be called just plain "st".
24570 if (StringRef("{st}").equals_lower(Constraint)) {
24571 Res.first = X86::FP0;
24572 Res.second = &X86::RFP80RegClass;
24577 if (StringRef("{flags}").equals_lower(Constraint)) {
24578 Res.first = X86::EFLAGS;
24579 Res.second = &X86::CCRRegClass;
24583 // 'A' means EAX + EDX.
24584 if (Constraint == "A") {
24585 Res.first = X86::EAX;
24586 Res.second = &X86::GR32_ADRegClass;
24592 // Otherwise, check to see if this is a register class of the wrong value
24593 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24594 // turn into {ax},{dx}.
24595 if (Res.second->hasType(VT))
24596 return Res; // Correct type already, nothing to do.
24598 // All of the single-register GCC register classes map their values onto
24599 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24600 // really want an 8-bit or 32-bit register, map to the appropriate register
24601 // class and return the appropriate register.
24602 if (Res.second == &X86::GR16RegClass) {
24603 if (VT == MVT::i8 || VT == MVT::i1) {
24604 unsigned DestReg = 0;
24605 switch (Res.first) {
24607 case X86::AX: DestReg = X86::AL; break;
24608 case X86::DX: DestReg = X86::DL; break;
24609 case X86::CX: DestReg = X86::CL; break;
24610 case X86::BX: DestReg = X86::BL; break;
24613 Res.first = DestReg;
24614 Res.second = &X86::GR8RegClass;
24616 } else if (VT == MVT::i32 || VT == MVT::f32) {
24617 unsigned DestReg = 0;
24618 switch (Res.first) {
24620 case X86::AX: DestReg = X86::EAX; break;
24621 case X86::DX: DestReg = X86::EDX; break;
24622 case X86::CX: DestReg = X86::ECX; break;
24623 case X86::BX: DestReg = X86::EBX; break;
24624 case X86::SI: DestReg = X86::ESI; break;
24625 case X86::DI: DestReg = X86::EDI; break;
24626 case X86::BP: DestReg = X86::EBP; break;
24627 case X86::SP: DestReg = X86::ESP; break;
24630 Res.first = DestReg;
24631 Res.second = &X86::GR32RegClass;
24633 } else if (VT == MVT::i64 || VT == MVT::f64) {
24634 unsigned DestReg = 0;
24635 switch (Res.first) {
24637 case X86::AX: DestReg = X86::RAX; break;
24638 case X86::DX: DestReg = X86::RDX; break;
24639 case X86::CX: DestReg = X86::RCX; break;
24640 case X86::BX: DestReg = X86::RBX; break;
24641 case X86::SI: DestReg = X86::RSI; break;
24642 case X86::DI: DestReg = X86::RDI; break;
24643 case X86::BP: DestReg = X86::RBP; break;
24644 case X86::SP: DestReg = X86::RSP; break;
24647 Res.first = DestReg;
24648 Res.second = &X86::GR64RegClass;
24651 } else if (Res.second == &X86::FR32RegClass ||
24652 Res.second == &X86::FR64RegClass ||
24653 Res.second == &X86::VR128RegClass ||
24654 Res.second == &X86::VR256RegClass ||
24655 Res.second == &X86::FR32XRegClass ||
24656 Res.second == &X86::FR64XRegClass ||
24657 Res.second == &X86::VR128XRegClass ||
24658 Res.second == &X86::VR256XRegClass ||
24659 Res.second == &X86::VR512RegClass) {
24660 // Handle references to XMM physical registers that got mapped into the
24661 // wrong class. This can happen with constraints like {xmm0} where the
24662 // target independent register mapper will just pick the first match it can
24663 // find, ignoring the required type.
24665 if (VT == MVT::f32 || VT == MVT::i32)
24666 Res.second = &X86::FR32RegClass;
24667 else if (VT == MVT::f64 || VT == MVT::i64)
24668 Res.second = &X86::FR64RegClass;
24669 else if (X86::VR128RegClass.hasType(VT))
24670 Res.second = &X86::VR128RegClass;
24671 else if (X86::VR256RegClass.hasType(VT))
24672 Res.second = &X86::VR256RegClass;
24673 else if (X86::VR512RegClass.hasType(VT))
24674 Res.second = &X86::VR512RegClass;
24680 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24682 // Scaling factors are not free at all.
24683 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24684 // will take 2 allocations in the out of order engine instead of 1
24685 // for plain addressing mode, i.e. inst (reg1).
24687 // vaddps (%rsi,%drx), %ymm0, %ymm1
24688 // Requires two allocations (one for the load, one for the computation)
24690 // vaddps (%rsi), %ymm0, %ymm1
24691 // Requires just 1 allocation, i.e., freeing allocations for other operations
24692 // and having less micro operations to execute.
24694 // For some X86 architectures, this is even worse because for instance for
24695 // stores, the complex addressing mode forces the instruction to use the
24696 // "load" ports instead of the dedicated "store" port.
24697 // E.g., on Haswell:
24698 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24699 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24700 if (isLegalAddressingMode(AM, Ty))
24701 // Scale represents reg2 * scale, thus account for 1
24702 // as soon as we use a second register.
24703 return AM.Scale != 0;
24707 bool X86TargetLowering::isTargetFTOL() const {
24708 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();